Version:  2.0.40 2.2.26 2.4.37 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2

Linux/drivers/spi/spi-omap2-mcspi.c

  1 /*
  2  * OMAP2 McSPI controller driver
  3  *
  4  * Copyright (C) 2005, 2006 Nokia Corporation
  5  * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
  6  *              Juha Yrj�l� <juha.yrjola@nokia.com>
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License, or
 11  * (at your option) any later version.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 16  * GNU General Public License for more details.
 17  */
 18 
 19 #include <linux/kernel.h>
 20 #include <linux/interrupt.h>
 21 #include <linux/module.h>
 22 #include <linux/device.h>
 23 #include <linux/delay.h>
 24 #include <linux/dma-mapping.h>
 25 #include <linux/dmaengine.h>
 26 #include <linux/omap-dma.h>
 27 #include <linux/platform_device.h>
 28 #include <linux/err.h>
 29 #include <linux/clk.h>
 30 #include <linux/io.h>
 31 #include <linux/slab.h>
 32 #include <linux/pm_runtime.h>
 33 #include <linux/of.h>
 34 #include <linux/of_device.h>
 35 #include <linux/gcd.h>
 36 
 37 #include <linux/spi/spi.h>
 38 #include <linux/gpio.h>
 39 
 40 #include <linux/platform_data/spi-omap2-mcspi.h>
 41 
 42 #define OMAP2_MCSPI_MAX_FREQ            48000000
 43 #define OMAP2_MCSPI_MAX_DIVIDER         4096
 44 #define OMAP2_MCSPI_MAX_FIFODEPTH       64
 45 #define OMAP2_MCSPI_MAX_FIFOWCNT        0xFFFF
 46 #define SPI_AUTOSUSPEND_TIMEOUT         2000
 47 
 48 #define OMAP2_MCSPI_REVISION            0x00
 49 #define OMAP2_MCSPI_SYSSTATUS           0x14
 50 #define OMAP2_MCSPI_IRQSTATUS           0x18
 51 #define OMAP2_MCSPI_IRQENABLE           0x1c
 52 #define OMAP2_MCSPI_WAKEUPENABLE        0x20
 53 #define OMAP2_MCSPI_SYST                0x24
 54 #define OMAP2_MCSPI_MODULCTRL           0x28
 55 #define OMAP2_MCSPI_XFERLEVEL           0x7c
 56 
 57 /* per-channel banks, 0x14 bytes each, first is: */
 58 #define OMAP2_MCSPI_CHCONF0             0x2c
 59 #define OMAP2_MCSPI_CHSTAT0             0x30
 60 #define OMAP2_MCSPI_CHCTRL0             0x34
 61 #define OMAP2_MCSPI_TX0                 0x38
 62 #define OMAP2_MCSPI_RX0                 0x3c
 63 
 64 /* per-register bitmasks: */
 65 #define OMAP2_MCSPI_IRQSTATUS_EOW       BIT(17)
 66 
 67 #define OMAP2_MCSPI_MODULCTRL_SINGLE    BIT(0)
 68 #define OMAP2_MCSPI_MODULCTRL_MS        BIT(2)
 69 #define OMAP2_MCSPI_MODULCTRL_STEST     BIT(3)
 70 
 71 #define OMAP2_MCSPI_CHCONF_PHA          BIT(0)
 72 #define OMAP2_MCSPI_CHCONF_POL          BIT(1)
 73 #define OMAP2_MCSPI_CHCONF_CLKD_MASK    (0x0f << 2)
 74 #define OMAP2_MCSPI_CHCONF_EPOL         BIT(6)
 75 #define OMAP2_MCSPI_CHCONF_WL_MASK      (0x1f << 7)
 76 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY  BIT(12)
 77 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY  BIT(13)
 78 #define OMAP2_MCSPI_CHCONF_TRM_MASK     (0x03 << 12)
 79 #define OMAP2_MCSPI_CHCONF_DMAW         BIT(14)
 80 #define OMAP2_MCSPI_CHCONF_DMAR         BIT(15)
 81 #define OMAP2_MCSPI_CHCONF_DPE0         BIT(16)
 82 #define OMAP2_MCSPI_CHCONF_DPE1         BIT(17)
 83 #define OMAP2_MCSPI_CHCONF_IS           BIT(18)
 84 #define OMAP2_MCSPI_CHCONF_TURBO        BIT(19)
 85 #define OMAP2_MCSPI_CHCONF_FORCE        BIT(20)
 86 #define OMAP2_MCSPI_CHCONF_FFET         BIT(27)
 87 #define OMAP2_MCSPI_CHCONF_FFER         BIT(28)
 88 #define OMAP2_MCSPI_CHCONF_CLKG         BIT(29)
 89 
 90 #define OMAP2_MCSPI_CHSTAT_RXS          BIT(0)
 91 #define OMAP2_MCSPI_CHSTAT_TXS          BIT(1)
 92 #define OMAP2_MCSPI_CHSTAT_EOT          BIT(2)
 93 #define OMAP2_MCSPI_CHSTAT_TXFFE        BIT(3)
 94 
 95 #define OMAP2_MCSPI_CHCTRL_EN           BIT(0)
 96 #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK  (0xff << 8)
 97 
 98 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN   BIT(0)
 99 
100 /* We have 2 DMA channels per CS, one for RX and one for TX */
101 struct omap2_mcspi_dma {
102         struct dma_chan *dma_tx;
103         struct dma_chan *dma_rx;
104 
105         int dma_tx_sync_dev;
106         int dma_rx_sync_dev;
107 
108         struct completion dma_tx_completion;
109         struct completion dma_rx_completion;
110 
111         char dma_rx_ch_name[14];
112         char dma_tx_ch_name[14];
113 };
114 
115 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
116  * cache operations; better heuristics consider wordsize and bitrate.
117  */
118 #define DMA_MIN_BYTES                   160
119 
120 
121 /*
122  * Used for context save and restore, structure members to be updated whenever
123  * corresponding registers are modified.
124  */
125 struct omap2_mcspi_regs {
126         u32 modulctrl;
127         u32 wakeupenable;
128         struct list_head cs;
129 };
130 
131 struct omap2_mcspi {
132         struct spi_master       *master;
133         /* Virtual base address of the controller */
134         void __iomem            *base;
135         unsigned long           phys;
136         /* SPI1 has 4 channels, while SPI2 has 2 */
137         struct omap2_mcspi_dma  *dma_channels;
138         struct device           *dev;
139         struct omap2_mcspi_regs ctx;
140         int                     fifo_depth;
141         unsigned int            pin_dir:1;
142 };
143 
144 struct omap2_mcspi_cs {
145         void __iomem            *base;
146         unsigned long           phys;
147         int                     word_len;
148         u16                     mode;
149         struct list_head        node;
150         /* Context save and restore shadow register */
151         u32                     chconf0, chctrl0;
152 };
153 
154 static inline void mcspi_write_reg(struct spi_master *master,
155                 int idx, u32 val)
156 {
157         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
158 
159         writel_relaxed(val, mcspi->base + idx);
160 }
161 
162 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
163 {
164         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
165 
166         return readl_relaxed(mcspi->base + idx);
167 }
168 
169 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
170                 int idx, u32 val)
171 {
172         struct omap2_mcspi_cs   *cs = spi->controller_state;
173 
174         writel_relaxed(val, cs->base +  idx);
175 }
176 
177 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
178 {
179         struct omap2_mcspi_cs   *cs = spi->controller_state;
180 
181         return readl_relaxed(cs->base + idx);
182 }
183 
184 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
185 {
186         struct omap2_mcspi_cs *cs = spi->controller_state;
187 
188         return cs->chconf0;
189 }
190 
191 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
192 {
193         struct omap2_mcspi_cs *cs = spi->controller_state;
194 
195         cs->chconf0 = val;
196         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
197         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
198 }
199 
200 static inline int mcspi_bytes_per_word(int word_len)
201 {
202         if (word_len <= 8)
203                 return 1;
204         else if (word_len <= 16)
205                 return 2;
206         else /* word_len <= 32 */
207                 return 4;
208 }
209 
210 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
211                 int is_read, int enable)
212 {
213         u32 l, rw;
214 
215         l = mcspi_cached_chconf0(spi);
216 
217         if (is_read) /* 1 is read, 0 write */
218                 rw = OMAP2_MCSPI_CHCONF_DMAR;
219         else
220                 rw = OMAP2_MCSPI_CHCONF_DMAW;
221 
222         if (enable)
223                 l |= rw;
224         else
225                 l &= ~rw;
226 
227         mcspi_write_chconf0(spi, l);
228 }
229 
230 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
231 {
232         struct omap2_mcspi_cs *cs = spi->controller_state;
233         u32 l;
234 
235         l = cs->chctrl0;
236         if (enable)
237                 l |= OMAP2_MCSPI_CHCTRL_EN;
238         else
239                 l &= ~OMAP2_MCSPI_CHCTRL_EN;
240         cs->chctrl0 = l;
241         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
242         /* Flash post-writes */
243         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
244 }
245 
246 static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable)
247 {
248         u32 l;
249 
250         /* The controller handles the inverted chip selects
251          * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert
252          * the inversion from the core spi_set_cs function.
253          */
254         if (spi->mode & SPI_CS_HIGH)
255                 enable = !enable;
256 
257         if (spi->controller_state) {
258                 l = mcspi_cached_chconf0(spi);
259 
260                 if (enable)
261                         l &= ~OMAP2_MCSPI_CHCONF_FORCE;
262                 else
263                         l |= OMAP2_MCSPI_CHCONF_FORCE;
264 
265                 mcspi_write_chconf0(spi, l);
266         }
267 }
268 
269 static void omap2_mcspi_set_master_mode(struct spi_master *master)
270 {
271         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
272         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
273         u32 l;
274 
275         /*
276          * Setup when switching from (reset default) slave mode
277          * to single-channel master mode
278          */
279         l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
280         l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
281         l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
282         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
283 
284         ctx->modulctrl = l;
285 }
286 
287 static void omap2_mcspi_set_fifo(const struct spi_device *spi,
288                                 struct spi_transfer *t, int enable)
289 {
290         struct spi_master *master = spi->master;
291         struct omap2_mcspi_cs *cs = spi->controller_state;
292         struct omap2_mcspi *mcspi;
293         unsigned int wcnt;
294         int max_fifo_depth, fifo_depth, bytes_per_word;
295         u32 chconf, xferlevel;
296 
297         mcspi = spi_master_get_devdata(master);
298 
299         chconf = mcspi_cached_chconf0(spi);
300         if (enable) {
301                 bytes_per_word = mcspi_bytes_per_word(cs->word_len);
302                 if (t->len % bytes_per_word != 0)
303                         goto disable_fifo;
304 
305                 if (t->rx_buf != NULL && t->tx_buf != NULL)
306                         max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2;
307                 else
308                         max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH;
309 
310                 fifo_depth = gcd(t->len, max_fifo_depth);
311                 if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0)
312                         goto disable_fifo;
313 
314                 wcnt = t->len / bytes_per_word;
315                 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
316                         goto disable_fifo;
317 
318                 xferlevel = wcnt << 16;
319                 if (t->rx_buf != NULL) {
320                         chconf |= OMAP2_MCSPI_CHCONF_FFER;
321                         xferlevel |= (fifo_depth - 1) << 8;
322                 }
323                 if (t->tx_buf != NULL) {
324                         chconf |= OMAP2_MCSPI_CHCONF_FFET;
325                         xferlevel |= fifo_depth - 1;
326                 }
327 
328                 mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
329                 mcspi_write_chconf0(spi, chconf);
330                 mcspi->fifo_depth = fifo_depth;
331 
332                 return;
333         }
334 
335 disable_fifo:
336         if (t->rx_buf != NULL)
337                 chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
338 
339         if (t->tx_buf != NULL)
340                 chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
341 
342         mcspi_write_chconf0(spi, chconf);
343         mcspi->fifo_depth = 0;
344 }
345 
346 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
347 {
348         struct spi_master       *spi_cntrl = mcspi->master;
349         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
350         struct omap2_mcspi_cs   *cs;
351 
352         /* McSPI: context restore */
353         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
354         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
355 
356         list_for_each_entry(cs, &ctx->cs, node)
357                 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
358 }
359 
360 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
361 {
362         unsigned long timeout;
363 
364         timeout = jiffies + msecs_to_jiffies(1000);
365         while (!(readl_relaxed(reg) & bit)) {
366                 if (time_after(jiffies, timeout)) {
367                         if (!(readl_relaxed(reg) & bit))
368                                 return -ETIMEDOUT;
369                         else
370                                 return 0;
371                 }
372                 cpu_relax();
373         }
374         return 0;
375 }
376 
377 static void omap2_mcspi_rx_callback(void *data)
378 {
379         struct spi_device *spi = data;
380         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
381         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
382 
383         /* We must disable the DMA RX request */
384         omap2_mcspi_set_dma_req(spi, 1, 0);
385 
386         complete(&mcspi_dma->dma_rx_completion);
387 }
388 
389 static void omap2_mcspi_tx_callback(void *data)
390 {
391         struct spi_device *spi = data;
392         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
393         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
394 
395         /* We must disable the DMA TX request */
396         omap2_mcspi_set_dma_req(spi, 0, 0);
397 
398         complete(&mcspi_dma->dma_tx_completion);
399 }
400 
401 static void omap2_mcspi_tx_dma(struct spi_device *spi,
402                                 struct spi_transfer *xfer,
403                                 struct dma_slave_config cfg)
404 {
405         struct omap2_mcspi      *mcspi;
406         struct omap2_mcspi_dma  *mcspi_dma;
407         unsigned int            count;
408 
409         mcspi = spi_master_get_devdata(spi->master);
410         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
411         count = xfer->len;
412 
413         if (mcspi_dma->dma_tx) {
414                 struct dma_async_tx_descriptor *tx;
415                 struct scatterlist sg;
416 
417                 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
418 
419                 sg_init_table(&sg, 1);
420                 sg_dma_address(&sg) = xfer->tx_dma;
421                 sg_dma_len(&sg) = xfer->len;
422 
423                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
424                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
425                 if (tx) {
426                         tx->callback = omap2_mcspi_tx_callback;
427                         tx->callback_param = spi;
428                         dmaengine_submit(tx);
429                 } else {
430                         /* FIXME: fall back to PIO? */
431                 }
432         }
433         dma_async_issue_pending(mcspi_dma->dma_tx);
434         omap2_mcspi_set_dma_req(spi, 0, 1);
435 
436 }
437 
438 static unsigned
439 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
440                                 struct dma_slave_config cfg,
441                                 unsigned es)
442 {
443         struct omap2_mcspi      *mcspi;
444         struct omap2_mcspi_dma  *mcspi_dma;
445         unsigned int            count, dma_count;
446         u32                     l;
447         int                     elements = 0;
448         int                     word_len, element_count;
449         struct omap2_mcspi_cs   *cs = spi->controller_state;
450         mcspi = spi_master_get_devdata(spi->master);
451         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
452         count = xfer->len;
453         dma_count = xfer->len;
454 
455         if (mcspi->fifo_depth == 0)
456                 dma_count -= es;
457 
458         word_len = cs->word_len;
459         l = mcspi_cached_chconf0(spi);
460 
461         if (word_len <= 8)
462                 element_count = count;
463         else if (word_len <= 16)
464                 element_count = count >> 1;
465         else /* word_len <= 32 */
466                 element_count = count >> 2;
467 
468         if (mcspi_dma->dma_rx) {
469                 struct dma_async_tx_descriptor *tx;
470                 struct scatterlist sg;
471 
472                 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
473 
474                 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
475                         dma_count -= es;
476 
477                 sg_init_table(&sg, 1);
478                 sg_dma_address(&sg) = xfer->rx_dma;
479                 sg_dma_len(&sg) = dma_count;
480 
481                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
482                                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
483                                 DMA_CTRL_ACK);
484                 if (tx) {
485                         tx->callback = omap2_mcspi_rx_callback;
486                         tx->callback_param = spi;
487                         dmaengine_submit(tx);
488                 } else {
489                                 /* FIXME: fall back to PIO? */
490                 }
491         }
492 
493         dma_async_issue_pending(mcspi_dma->dma_rx);
494         omap2_mcspi_set_dma_req(spi, 1, 1);
495 
496         wait_for_completion(&mcspi_dma->dma_rx_completion);
497         dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
498                          DMA_FROM_DEVICE);
499 
500         if (mcspi->fifo_depth > 0)
501                 return count;
502 
503         omap2_mcspi_set_enable(spi, 0);
504 
505         elements = element_count - 1;
506 
507         if (l & OMAP2_MCSPI_CHCONF_TURBO) {
508                 elements--;
509 
510                 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
511                                    & OMAP2_MCSPI_CHSTAT_RXS)) {
512                         u32 w;
513 
514                         w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
515                         if (word_len <= 8)
516                                 ((u8 *)xfer->rx_buf)[elements++] = w;
517                         else if (word_len <= 16)
518                                 ((u16 *)xfer->rx_buf)[elements++] = w;
519                         else /* word_len <= 32 */
520                                 ((u32 *)xfer->rx_buf)[elements++] = w;
521                 } else {
522                         int bytes_per_word = mcspi_bytes_per_word(word_len);
523                         dev_err(&spi->dev, "DMA RX penultimate word empty\n");
524                         count -= (bytes_per_word << 1);
525                         omap2_mcspi_set_enable(spi, 1);
526                         return count;
527                 }
528         }
529         if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
530                                 & OMAP2_MCSPI_CHSTAT_RXS)) {
531                 u32 w;
532 
533                 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
534                 if (word_len <= 8)
535                         ((u8 *)xfer->rx_buf)[elements] = w;
536                 else if (word_len <= 16)
537                         ((u16 *)xfer->rx_buf)[elements] = w;
538                 else /* word_len <= 32 */
539                         ((u32 *)xfer->rx_buf)[elements] = w;
540         } else {
541                 dev_err(&spi->dev, "DMA RX last word empty\n");
542                 count -= mcspi_bytes_per_word(word_len);
543         }
544         omap2_mcspi_set_enable(spi, 1);
545         return count;
546 }
547 
548 static unsigned
549 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
550 {
551         struct omap2_mcspi      *mcspi;
552         struct omap2_mcspi_cs   *cs = spi->controller_state;
553         struct omap2_mcspi_dma  *mcspi_dma;
554         unsigned int            count;
555         u32                     l;
556         u8                      *rx;
557         const u8                *tx;
558         struct dma_slave_config cfg;
559         enum dma_slave_buswidth width;
560         unsigned es;
561         u32                     burst;
562         void __iomem            *chstat_reg;
563         void __iomem            *irqstat_reg;
564         int                     wait_res;
565 
566         mcspi = spi_master_get_devdata(spi->master);
567         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
568         l = mcspi_cached_chconf0(spi);
569 
570 
571         if (cs->word_len <= 8) {
572                 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
573                 es = 1;
574         } else if (cs->word_len <= 16) {
575                 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
576                 es = 2;
577         } else {
578                 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
579                 es = 4;
580         }
581 
582         count = xfer->len;
583         burst = 1;
584 
585         if (mcspi->fifo_depth > 0) {
586                 if (count > mcspi->fifo_depth)
587                         burst = mcspi->fifo_depth / es;
588                 else
589                         burst = count / es;
590         }
591 
592         memset(&cfg, 0, sizeof(cfg));
593         cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
594         cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
595         cfg.src_addr_width = width;
596         cfg.dst_addr_width = width;
597         cfg.src_maxburst = burst;
598         cfg.dst_maxburst = burst;
599 
600         rx = xfer->rx_buf;
601         tx = xfer->tx_buf;
602 
603         if (tx != NULL)
604                 omap2_mcspi_tx_dma(spi, xfer, cfg);
605 
606         if (rx != NULL)
607                 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
608 
609         if (tx != NULL) {
610                 wait_for_completion(&mcspi_dma->dma_tx_completion);
611                 dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len,
612                                  DMA_TO_DEVICE);
613 
614                 if (mcspi->fifo_depth > 0) {
615                         irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
616 
617                         if (mcspi_wait_for_reg_bit(irqstat_reg,
618                                                 OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
619                                 dev_err(&spi->dev, "EOW timed out\n");
620 
621                         mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
622                                         OMAP2_MCSPI_IRQSTATUS_EOW);
623                 }
624 
625                 /* for TX_ONLY mode, be sure all words have shifted out */
626                 if (rx == NULL) {
627                         chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
628                         if (mcspi->fifo_depth > 0) {
629                                 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
630                                                 OMAP2_MCSPI_CHSTAT_TXFFE);
631                                 if (wait_res < 0)
632                                         dev_err(&spi->dev, "TXFFE timed out\n");
633                         } else {
634                                 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
635                                                 OMAP2_MCSPI_CHSTAT_TXS);
636                                 if (wait_res < 0)
637                                         dev_err(&spi->dev, "TXS timed out\n");
638                         }
639                         if (wait_res >= 0 &&
640                                 (mcspi_wait_for_reg_bit(chstat_reg,
641                                         OMAP2_MCSPI_CHSTAT_EOT) < 0))
642                                 dev_err(&spi->dev, "EOT timed out\n");
643                 }
644         }
645         return count;
646 }
647 
648 static unsigned
649 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
650 {
651         struct omap2_mcspi      *mcspi;
652         struct omap2_mcspi_cs   *cs = spi->controller_state;
653         unsigned int            count, c;
654         u32                     l;
655         void __iomem            *base = cs->base;
656         void __iomem            *tx_reg;
657         void __iomem            *rx_reg;
658         void __iomem            *chstat_reg;
659         int                     word_len;
660 
661         mcspi = spi_master_get_devdata(spi->master);
662         count = xfer->len;
663         c = count;
664         word_len = cs->word_len;
665 
666         l = mcspi_cached_chconf0(spi);
667 
668         /* We store the pre-calculated register addresses on stack to speed
669          * up the transfer loop. */
670         tx_reg          = base + OMAP2_MCSPI_TX0;
671         rx_reg          = base + OMAP2_MCSPI_RX0;
672         chstat_reg      = base + OMAP2_MCSPI_CHSTAT0;
673 
674         if (c < (word_len>>3))
675                 return 0;
676 
677         if (word_len <= 8) {
678                 u8              *rx;
679                 const u8        *tx;
680 
681                 rx = xfer->rx_buf;
682                 tx = xfer->tx_buf;
683 
684                 do {
685                         c -= 1;
686                         if (tx != NULL) {
687                                 if (mcspi_wait_for_reg_bit(chstat_reg,
688                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
689                                         dev_err(&spi->dev, "TXS timed out\n");
690                                         goto out;
691                                 }
692                                 dev_vdbg(&spi->dev, "write-%d %02x\n",
693                                                 word_len, *tx);
694                                 writel_relaxed(*tx++, tx_reg);
695                         }
696                         if (rx != NULL) {
697                                 if (mcspi_wait_for_reg_bit(chstat_reg,
698                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
699                                         dev_err(&spi->dev, "RXS timed out\n");
700                                         goto out;
701                                 }
702 
703                                 if (c == 1 && tx == NULL &&
704                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
705                                         omap2_mcspi_set_enable(spi, 0);
706                                         *rx++ = readl_relaxed(rx_reg);
707                                         dev_vdbg(&spi->dev, "read-%d %02x\n",
708                                                     word_len, *(rx - 1));
709                                         if (mcspi_wait_for_reg_bit(chstat_reg,
710                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
711                                                 dev_err(&spi->dev,
712                                                         "RXS timed out\n");
713                                                 goto out;
714                                         }
715                                         c = 0;
716                                 } else if (c == 0 && tx == NULL) {
717                                         omap2_mcspi_set_enable(spi, 0);
718                                 }
719 
720                                 *rx++ = readl_relaxed(rx_reg);
721                                 dev_vdbg(&spi->dev, "read-%d %02x\n",
722                                                 word_len, *(rx - 1));
723                         }
724                 } while (c);
725         } else if (word_len <= 16) {
726                 u16             *rx;
727                 const u16       *tx;
728 
729                 rx = xfer->rx_buf;
730                 tx = xfer->tx_buf;
731                 do {
732                         c -= 2;
733                         if (tx != NULL) {
734                                 if (mcspi_wait_for_reg_bit(chstat_reg,
735                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
736                                         dev_err(&spi->dev, "TXS timed out\n");
737                                         goto out;
738                                 }
739                                 dev_vdbg(&spi->dev, "write-%d %04x\n",
740                                                 word_len, *tx);
741                                 writel_relaxed(*tx++, tx_reg);
742                         }
743                         if (rx != NULL) {
744                                 if (mcspi_wait_for_reg_bit(chstat_reg,
745                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
746                                         dev_err(&spi->dev, "RXS timed out\n");
747                                         goto out;
748                                 }
749 
750                                 if (c == 2 && tx == NULL &&
751                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
752                                         omap2_mcspi_set_enable(spi, 0);
753                                         *rx++ = readl_relaxed(rx_reg);
754                                         dev_vdbg(&spi->dev, "read-%d %04x\n",
755                                                     word_len, *(rx - 1));
756                                         if (mcspi_wait_for_reg_bit(chstat_reg,
757                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
758                                                 dev_err(&spi->dev,
759                                                         "RXS timed out\n");
760                                                 goto out;
761                                         }
762                                         c = 0;
763                                 } else if (c == 0 && tx == NULL) {
764                                         omap2_mcspi_set_enable(spi, 0);
765                                 }
766 
767                                 *rx++ = readl_relaxed(rx_reg);
768                                 dev_vdbg(&spi->dev, "read-%d %04x\n",
769                                                 word_len, *(rx - 1));
770                         }
771                 } while (c >= 2);
772         } else if (word_len <= 32) {
773                 u32             *rx;
774                 const u32       *tx;
775 
776                 rx = xfer->rx_buf;
777                 tx = xfer->tx_buf;
778                 do {
779                         c -= 4;
780                         if (tx != NULL) {
781                                 if (mcspi_wait_for_reg_bit(chstat_reg,
782                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
783                                         dev_err(&spi->dev, "TXS timed out\n");
784                                         goto out;
785                                 }
786                                 dev_vdbg(&spi->dev, "write-%d %08x\n",
787                                                 word_len, *tx);
788                                 writel_relaxed(*tx++, tx_reg);
789                         }
790                         if (rx != NULL) {
791                                 if (mcspi_wait_for_reg_bit(chstat_reg,
792                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
793                                         dev_err(&spi->dev, "RXS timed out\n");
794                                         goto out;
795                                 }
796 
797                                 if (c == 4 && tx == NULL &&
798                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
799                                         omap2_mcspi_set_enable(spi, 0);
800                                         *rx++ = readl_relaxed(rx_reg);
801                                         dev_vdbg(&spi->dev, "read-%d %08x\n",
802                                                     word_len, *(rx - 1));
803                                         if (mcspi_wait_for_reg_bit(chstat_reg,
804                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
805                                                 dev_err(&spi->dev,
806                                                         "RXS timed out\n");
807                                                 goto out;
808                                         }
809                                         c = 0;
810                                 } else if (c == 0 && tx == NULL) {
811                                         omap2_mcspi_set_enable(spi, 0);
812                                 }
813 
814                                 *rx++ = readl_relaxed(rx_reg);
815                                 dev_vdbg(&spi->dev, "read-%d %08x\n",
816                                                 word_len, *(rx - 1));
817                         }
818                 } while (c >= 4);
819         }
820 
821         /* for TX_ONLY mode, be sure all words have shifted out */
822         if (xfer->rx_buf == NULL) {
823                 if (mcspi_wait_for_reg_bit(chstat_reg,
824                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
825                         dev_err(&spi->dev, "TXS timed out\n");
826                 } else if (mcspi_wait_for_reg_bit(chstat_reg,
827                                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
828                         dev_err(&spi->dev, "EOT timed out\n");
829 
830                 /* disable chan to purge rx datas received in TX_ONLY transfer,
831                  * otherwise these rx datas will affect the direct following
832                  * RX_ONLY transfer.
833                  */
834                 omap2_mcspi_set_enable(spi, 0);
835         }
836 out:
837         omap2_mcspi_set_enable(spi, 1);
838         return count - c;
839 }
840 
841 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
842 {
843         u32 div;
844 
845         for (div = 0; div < 15; div++)
846                 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
847                         return div;
848 
849         return 15;
850 }
851 
852 /* called only when no transfer is active to this device */
853 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
854                 struct spi_transfer *t)
855 {
856         struct omap2_mcspi_cs *cs = spi->controller_state;
857         struct omap2_mcspi *mcspi;
858         struct spi_master *spi_cntrl;
859         u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0;
860         u8 word_len = spi->bits_per_word;
861         u32 speed_hz = spi->max_speed_hz;
862 
863         mcspi = spi_master_get_devdata(spi->master);
864         spi_cntrl = mcspi->master;
865 
866         if (t != NULL && t->bits_per_word)
867                 word_len = t->bits_per_word;
868 
869         cs->word_len = word_len;
870 
871         if (t && t->speed_hz)
872                 speed_hz = t->speed_hz;
873 
874         speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
875         if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) {
876                 clkd = omap2_mcspi_calc_divisor(speed_hz);
877                 speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd;
878                 clkg = 0;
879         } else {
880                 div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz;
881                 speed_hz = OMAP2_MCSPI_MAX_FREQ / div;
882                 clkd = (div - 1) & 0xf;
883                 extclk = (div - 1) >> 4;
884                 clkg = OMAP2_MCSPI_CHCONF_CLKG;
885         }
886 
887         l = mcspi_cached_chconf0(spi);
888 
889         /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
890          * REVISIT: this controller could support SPI_3WIRE mode.
891          */
892         if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
893                 l &= ~OMAP2_MCSPI_CHCONF_IS;
894                 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
895                 l |= OMAP2_MCSPI_CHCONF_DPE0;
896         } else {
897                 l |= OMAP2_MCSPI_CHCONF_IS;
898                 l |= OMAP2_MCSPI_CHCONF_DPE1;
899                 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
900         }
901 
902         /* wordlength */
903         l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
904         l |= (word_len - 1) << 7;
905 
906         /* set chipselect polarity; manage with FORCE */
907         if (!(spi->mode & SPI_CS_HIGH))
908                 l |= OMAP2_MCSPI_CHCONF_EPOL;   /* active-low; normal */
909         else
910                 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
911 
912         /* set clock divisor */
913         l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
914         l |= clkd << 2;
915 
916         /* set clock granularity */
917         l &= ~OMAP2_MCSPI_CHCONF_CLKG;
918         l |= clkg;
919         if (clkg) {
920                 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
921                 cs->chctrl0 |= extclk << 8;
922                 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
923         }
924 
925         /* set SPI mode 0..3 */
926         if (spi->mode & SPI_CPOL)
927                 l |= OMAP2_MCSPI_CHCONF_POL;
928         else
929                 l &= ~OMAP2_MCSPI_CHCONF_POL;
930         if (spi->mode & SPI_CPHA)
931                 l |= OMAP2_MCSPI_CHCONF_PHA;
932         else
933                 l &= ~OMAP2_MCSPI_CHCONF_PHA;
934 
935         mcspi_write_chconf0(spi, l);
936 
937         cs->mode = spi->mode;
938 
939         dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
940                         speed_hz,
941                         (spi->mode & SPI_CPHA) ? "trailing" : "leading",
942                         (spi->mode & SPI_CPOL) ? "inverted" : "normal");
943 
944         return 0;
945 }
946 
947 /*
948  * Note that we currently allow DMA only if we get a channel
949  * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
950  */
951 static int omap2_mcspi_request_dma(struct spi_device *spi)
952 {
953         struct spi_master       *master = spi->master;
954         struct omap2_mcspi      *mcspi;
955         struct omap2_mcspi_dma  *mcspi_dma;
956         dma_cap_mask_t mask;
957         unsigned sig;
958 
959         mcspi = spi_master_get_devdata(master);
960         mcspi_dma = mcspi->dma_channels + spi->chip_select;
961 
962         init_completion(&mcspi_dma->dma_rx_completion);
963         init_completion(&mcspi_dma->dma_tx_completion);
964 
965         dma_cap_zero(mask);
966         dma_cap_set(DMA_SLAVE, mask);
967         sig = mcspi_dma->dma_rx_sync_dev;
968 
969         mcspi_dma->dma_rx =
970                 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
971                                                  &sig, &master->dev,
972                                                  mcspi_dma->dma_rx_ch_name);
973         if (!mcspi_dma->dma_rx)
974                 goto no_dma;
975 
976         sig = mcspi_dma->dma_tx_sync_dev;
977         mcspi_dma->dma_tx =
978                 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
979                                                  &sig, &master->dev,
980                                                  mcspi_dma->dma_tx_ch_name);
981 
982         if (!mcspi_dma->dma_tx) {
983                 dma_release_channel(mcspi_dma->dma_rx);
984                 mcspi_dma->dma_rx = NULL;
985                 goto no_dma;
986         }
987 
988         return 0;
989 
990 no_dma:
991         dev_warn(&spi->dev, "not using DMA for McSPI\n");
992         return -EAGAIN;
993 }
994 
995 static int omap2_mcspi_setup(struct spi_device *spi)
996 {
997         int                     ret;
998         struct omap2_mcspi      *mcspi = spi_master_get_devdata(spi->master);
999         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1000         struct omap2_mcspi_dma  *mcspi_dma;
1001         struct omap2_mcspi_cs   *cs = spi->controller_state;
1002 
1003         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1004 
1005         if (!cs) {
1006                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
1007                 if (!cs)
1008                         return -ENOMEM;
1009                 cs->base = mcspi->base + spi->chip_select * 0x14;
1010                 cs->phys = mcspi->phys + spi->chip_select * 0x14;
1011                 cs->mode = 0;
1012                 cs->chconf0 = 0;
1013                 cs->chctrl0 = 0;
1014                 spi->controller_state = cs;
1015                 /* Link this to context save list */
1016                 list_add_tail(&cs->node, &ctx->cs);
1017         }
1018 
1019         if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
1020                 ret = omap2_mcspi_request_dma(spi);
1021                 if (ret < 0 && ret != -EAGAIN)
1022                         return ret;
1023         }
1024 
1025         if (gpio_is_valid(spi->cs_gpio)) {
1026                 ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
1027                 if (ret) {
1028                         dev_err(&spi->dev, "failed to request gpio\n");
1029                         return ret;
1030                 }
1031                 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
1032         }
1033 
1034         ret = pm_runtime_get_sync(mcspi->dev);
1035         if (ret < 0)
1036                 return ret;
1037 
1038         ret = omap2_mcspi_setup_transfer(spi, NULL);
1039         pm_runtime_mark_last_busy(mcspi->dev);
1040         pm_runtime_put_autosuspend(mcspi->dev);
1041 
1042         return ret;
1043 }
1044 
1045 static void omap2_mcspi_cleanup(struct spi_device *spi)
1046 {
1047         struct omap2_mcspi      *mcspi;
1048         struct omap2_mcspi_dma  *mcspi_dma;
1049         struct omap2_mcspi_cs   *cs;
1050 
1051         mcspi = spi_master_get_devdata(spi->master);
1052 
1053         if (spi->controller_state) {
1054                 /* Unlink controller state from context save list */
1055                 cs = spi->controller_state;
1056                 list_del(&cs->node);
1057 
1058                 kfree(cs);
1059         }
1060 
1061         if (spi->chip_select < spi->master->num_chipselect) {
1062                 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1063 
1064                 if (mcspi_dma->dma_rx) {
1065                         dma_release_channel(mcspi_dma->dma_rx);
1066                         mcspi_dma->dma_rx = NULL;
1067                 }
1068                 if (mcspi_dma->dma_tx) {
1069                         dma_release_channel(mcspi_dma->dma_tx);
1070                         mcspi_dma->dma_tx = NULL;
1071                 }
1072         }
1073 
1074         if (gpio_is_valid(spi->cs_gpio))
1075                 gpio_free(spi->cs_gpio);
1076 }
1077 
1078 static int omap2_mcspi_work_one(struct omap2_mcspi *mcspi,
1079                 struct spi_device *spi, struct spi_transfer *t)
1080 {
1081 
1082         /* We only enable one channel at a time -- the one whose message is
1083          * -- although this controller would gladly
1084          * arbitrate among multiple channels.  This corresponds to "single
1085          * channel" master mode.  As a side effect, we need to manage the
1086          * chipselect with the FORCE bit ... CS != channel enable.
1087          */
1088 
1089         struct spi_master               *master;
1090         struct omap2_mcspi_dma          *mcspi_dma;
1091         struct omap2_mcspi_cs           *cs;
1092         struct omap2_mcspi_device_config *cd;
1093         int                             par_override = 0;
1094         int                             status = 0;
1095         u32                             chconf;
1096 
1097         master = spi->master;
1098         mcspi_dma = mcspi->dma_channels + spi->chip_select;
1099         cs = spi->controller_state;
1100         cd = spi->controller_data;
1101 
1102         /*
1103          * The slave driver could have changed spi->mode in which case
1104          * it will be different from cs->mode (the current hardware setup).
1105          * If so, set par_override (even though its not a parity issue) so
1106          * omap2_mcspi_setup_transfer will be called to configure the hardware
1107          * with the correct mode on the first iteration of the loop below.
1108          */
1109         if (spi->mode != cs->mode)
1110                 par_override = 1;
1111 
1112         omap2_mcspi_set_enable(spi, 0);
1113 
1114         if (gpio_is_valid(spi->cs_gpio))
1115                 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);
1116 
1117         if (par_override ||
1118             (t->speed_hz != spi->max_speed_hz) ||
1119             (t->bits_per_word != spi->bits_per_word)) {
1120                 par_override = 1;
1121                 status = omap2_mcspi_setup_transfer(spi, t);
1122                 if (status < 0)
1123                         goto out;
1124                 if (t->speed_hz == spi->max_speed_hz &&
1125                     t->bits_per_word == spi->bits_per_word)
1126                         par_override = 0;
1127         }
1128         if (cd && cd->cs_per_word) {
1129                 chconf = mcspi->ctx.modulctrl;
1130                 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
1131                 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1132                 mcspi->ctx.modulctrl =
1133                         mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1134         }
1135 
1136         chconf = mcspi_cached_chconf0(spi);
1137         chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
1138         chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
1139 
1140         if (t->tx_buf == NULL)
1141                 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
1142         else if (t->rx_buf == NULL)
1143                 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
1144 
1145         if (cd && cd->turbo_mode && t->tx_buf == NULL) {
1146                 /* Turbo mode is for more than one word */
1147                 if (t->len > ((cs->word_len + 7) >> 3))
1148                         chconf |= OMAP2_MCSPI_CHCONF_TURBO;
1149         }
1150 
1151         mcspi_write_chconf0(spi, chconf);
1152 
1153         if (t->len) {
1154                 unsigned        count;
1155 
1156                 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1157                     (t->len >= DMA_MIN_BYTES))
1158                         omap2_mcspi_set_fifo(spi, t, 1);
1159 
1160                 omap2_mcspi_set_enable(spi, 1);
1161 
1162                 /* RX_ONLY mode needs dummy data in TX reg */
1163                 if (t->tx_buf == NULL)
1164                         writel_relaxed(0, cs->base
1165                                         + OMAP2_MCSPI_TX0);
1166 
1167                 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1168                     (t->len >= DMA_MIN_BYTES))
1169                         count = omap2_mcspi_txrx_dma(spi, t);
1170                 else
1171                         count = omap2_mcspi_txrx_pio(spi, t);
1172 
1173                 if (count != t->len) {
1174                         status = -EIO;
1175                         goto out;
1176                 }
1177         }
1178 
1179         omap2_mcspi_set_enable(spi, 0);
1180 
1181         if (mcspi->fifo_depth > 0)
1182                 omap2_mcspi_set_fifo(spi, t, 0);
1183 
1184 out:
1185         /* Restore defaults if they were overriden */
1186         if (par_override) {
1187                 par_override = 0;
1188                 status = omap2_mcspi_setup_transfer(spi, NULL);
1189         }
1190 
1191         if (cd && cd->cs_per_word) {
1192                 chconf = mcspi->ctx.modulctrl;
1193                 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1194                 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1195                 mcspi->ctx.modulctrl =
1196                         mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1197         }
1198 
1199         omap2_mcspi_set_enable(spi, 0);
1200 
1201         if (gpio_is_valid(spi->cs_gpio))
1202                 omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));
1203 
1204         if (mcspi->fifo_depth > 0 && t)
1205                 omap2_mcspi_set_fifo(spi, t, 0);
1206 
1207         return status;
1208 }
1209 
1210 static int omap2_mcspi_transfer_one(struct spi_master *master,
1211                 struct spi_device *spi, struct spi_transfer *t)
1212 {
1213         struct omap2_mcspi      *mcspi;
1214         struct omap2_mcspi_dma  *mcspi_dma;
1215         const void      *tx_buf = t->tx_buf;
1216         void            *rx_buf = t->rx_buf;
1217         unsigned        len = t->len;
1218 
1219         mcspi = spi_master_get_devdata(master);
1220         mcspi_dma = mcspi->dma_channels + spi->chip_select;
1221 
1222         if ((len && !(rx_buf || tx_buf))) {
1223                 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
1224                                 t->speed_hz,
1225                                 len,
1226                                 tx_buf ? "tx" : "",
1227                                 rx_buf ? "rx" : "",
1228                                 t->bits_per_word);
1229                 return -EINVAL;
1230         }
1231 
1232         if (len < DMA_MIN_BYTES)
1233                 goto skip_dma_map;
1234 
1235         if (mcspi_dma->dma_tx && tx_buf != NULL) {
1236                 t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
1237                                 len, DMA_TO_DEVICE);
1238                 if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
1239                         dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1240                                         'T', len);
1241                         return -EINVAL;
1242                 }
1243         }
1244         if (mcspi_dma->dma_rx && rx_buf != NULL) {
1245                 t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
1246                                 DMA_FROM_DEVICE);
1247                 if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
1248                         dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1249                                         'R', len);
1250                         if (tx_buf != NULL)
1251                                 dma_unmap_single(mcspi->dev, t->tx_dma,
1252                                                 len, DMA_TO_DEVICE);
1253                         return -EINVAL;
1254                 }
1255         }
1256 
1257 skip_dma_map:
1258         return omap2_mcspi_work_one(mcspi, spi, t);
1259 }
1260 
1261 static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1262 {
1263         struct spi_master       *master = mcspi->master;
1264         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1265         int                     ret = 0;
1266 
1267         ret = pm_runtime_get_sync(mcspi->dev);
1268         if (ret < 0)
1269                 return ret;
1270 
1271         mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1272                         OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1273         ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1274 
1275         omap2_mcspi_set_master_mode(master);
1276         pm_runtime_mark_last_busy(mcspi->dev);
1277         pm_runtime_put_autosuspend(mcspi->dev);
1278         return 0;
1279 }
1280 
1281 static int omap_mcspi_runtime_resume(struct device *dev)
1282 {
1283         struct omap2_mcspi      *mcspi;
1284         struct spi_master       *master;
1285 
1286         master = dev_get_drvdata(dev);
1287         mcspi = spi_master_get_devdata(master);
1288         omap2_mcspi_restore_ctx(mcspi);
1289 
1290         return 0;
1291 }
1292 
1293 static struct omap2_mcspi_platform_config omap2_pdata = {
1294         .regs_offset = 0,
1295 };
1296 
1297 static struct omap2_mcspi_platform_config omap4_pdata = {
1298         .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1299 };
1300 
1301 static const struct of_device_id omap_mcspi_of_match[] = {
1302         {
1303                 .compatible = "ti,omap2-mcspi",
1304                 .data = &omap2_pdata,
1305         },
1306         {
1307                 .compatible = "ti,omap4-mcspi",
1308                 .data = &omap4_pdata,
1309         },
1310         { },
1311 };
1312 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1313 
1314 static int omap2_mcspi_probe(struct platform_device *pdev)
1315 {
1316         struct spi_master       *master;
1317         const struct omap2_mcspi_platform_config *pdata;
1318         struct omap2_mcspi      *mcspi;
1319         struct resource         *r;
1320         int                     status = 0, i;
1321         u32                     regs_offset = 0;
1322         static int              bus_num = 1;
1323         struct device_node      *node = pdev->dev.of_node;
1324         const struct of_device_id *match;
1325 
1326         master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1327         if (master == NULL) {
1328                 dev_dbg(&pdev->dev, "master allocation failed\n");
1329                 return -ENOMEM;
1330         }
1331 
1332         /* the spi->mode bits understood by this driver: */
1333         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1334         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1335         master->setup = omap2_mcspi_setup;
1336         master->auto_runtime_pm = true;
1337         master->transfer_one = omap2_mcspi_transfer_one;
1338         master->set_cs = omap2_mcspi_set_cs;
1339         master->cleanup = omap2_mcspi_cleanup;
1340         master->dev.of_node = node;
1341         master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
1342         master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
1343 
1344         platform_set_drvdata(pdev, master);
1345 
1346         mcspi = spi_master_get_devdata(master);
1347         mcspi->master = master;
1348 
1349         match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1350         if (match) {
1351                 u32 num_cs = 1; /* default number of chipselect */
1352                 pdata = match->data;
1353 
1354                 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1355                 master->num_chipselect = num_cs;
1356                 master->bus_num = bus_num++;
1357                 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1358                         mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1359         } else {
1360                 pdata = dev_get_platdata(&pdev->dev);
1361                 master->num_chipselect = pdata->num_cs;
1362                 if (pdev->id != -1)
1363                         master->bus_num = pdev->id;
1364                 mcspi->pin_dir = pdata->pin_dir;
1365         }
1366         regs_offset = pdata->regs_offset;
1367 
1368         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1369         if (r == NULL) {
1370                 status = -ENODEV;
1371                 goto free_master;
1372         }
1373 
1374         r->start += regs_offset;
1375         r->end += regs_offset;
1376         mcspi->phys = r->start;
1377 
1378         mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1379         if (IS_ERR(mcspi->base)) {
1380                 status = PTR_ERR(mcspi->base);
1381                 goto free_master;
1382         }
1383 
1384         mcspi->dev = &pdev->dev;
1385 
1386         INIT_LIST_HEAD(&mcspi->ctx.cs);
1387 
1388         mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect,
1389                                            sizeof(struct omap2_mcspi_dma),
1390                                            GFP_KERNEL);
1391         if (mcspi->dma_channels == NULL) {
1392                 status = -ENOMEM;
1393                 goto free_master;
1394         }
1395 
1396         for (i = 0; i < master->num_chipselect; i++) {
1397                 char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name;
1398                 char *dma_tx_ch_name = mcspi->dma_channels[i].dma_tx_ch_name;
1399                 struct resource *dma_res;
1400 
1401                 sprintf(dma_rx_ch_name, "rx%d", i);
1402                 if (!pdev->dev.of_node) {
1403                         dma_res =
1404                                 platform_get_resource_byname(pdev,
1405                                                              IORESOURCE_DMA,
1406                                                              dma_rx_ch_name);
1407                         if (!dma_res) {
1408                                 dev_dbg(&pdev->dev,
1409                                         "cannot get DMA RX channel\n");
1410                                 status = -ENODEV;
1411                                 break;
1412                         }
1413 
1414                         mcspi->dma_channels[i].dma_rx_sync_dev =
1415                                 dma_res->start;
1416                 }
1417                 sprintf(dma_tx_ch_name, "tx%d", i);
1418                 if (!pdev->dev.of_node) {
1419                         dma_res =
1420                                 platform_get_resource_byname(pdev,
1421                                                              IORESOURCE_DMA,
1422                                                              dma_tx_ch_name);
1423                         if (!dma_res) {
1424                                 dev_dbg(&pdev->dev,
1425                                         "cannot get DMA TX channel\n");
1426                                 status = -ENODEV;
1427                                 break;
1428                         }
1429 
1430                         mcspi->dma_channels[i].dma_tx_sync_dev =
1431                                 dma_res->start;
1432                 }
1433         }
1434 
1435         if (status < 0)
1436                 goto free_master;
1437 
1438         pm_runtime_use_autosuspend(&pdev->dev);
1439         pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1440         pm_runtime_enable(&pdev->dev);
1441 
1442         status = omap2_mcspi_master_setup(mcspi);
1443         if (status < 0)
1444                 goto disable_pm;
1445 
1446         status = devm_spi_register_master(&pdev->dev, master);
1447         if (status < 0)
1448                 goto disable_pm;
1449 
1450         return status;
1451 
1452 disable_pm:
1453         pm_runtime_disable(&pdev->dev);
1454 free_master:
1455         spi_master_put(master);
1456         return status;
1457 }
1458 
1459 static int omap2_mcspi_remove(struct platform_device *pdev)
1460 {
1461         struct spi_master *master = platform_get_drvdata(pdev);
1462         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1463 
1464         pm_runtime_put_sync(mcspi->dev);
1465         pm_runtime_disable(&pdev->dev);
1466 
1467         return 0;
1468 }
1469 
1470 /* work with hotplug and coldplug */
1471 MODULE_ALIAS("platform:omap2_mcspi");
1472 
1473 #ifdef  CONFIG_SUSPEND
1474 /*
1475  * When SPI wake up from off-mode, CS is in activate state. If it was in
1476  * unactive state when driver was suspend, then force it to unactive state at
1477  * wake up.
1478  */
1479 static int omap2_mcspi_resume(struct device *dev)
1480 {
1481         struct spi_master       *master = dev_get_drvdata(dev);
1482         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
1483         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1484         struct omap2_mcspi_cs   *cs;
1485 
1486         pm_runtime_get_sync(mcspi->dev);
1487         list_for_each_entry(cs, &ctx->cs, node) {
1488                 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1489                         /*
1490                          * We need to toggle CS state for OMAP take this
1491                          * change in account.
1492                          */
1493                         cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1494                         writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1495                         cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1496                         writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1497                 }
1498         }
1499         pm_runtime_mark_last_busy(mcspi->dev);
1500         pm_runtime_put_autosuspend(mcspi->dev);
1501         return 0;
1502 }
1503 #else
1504 #define omap2_mcspi_resume      NULL
1505 #endif
1506 
1507 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1508         .resume = omap2_mcspi_resume,
1509         .runtime_resume = omap_mcspi_runtime_resume,
1510 };
1511 
1512 static struct platform_driver omap2_mcspi_driver = {
1513         .driver = {
1514                 .name =         "omap2_mcspi",
1515                 .pm =           &omap2_mcspi_pm_ops,
1516                 .of_match_table = omap_mcspi_of_match,
1517         },
1518         .probe =        omap2_mcspi_probe,
1519         .remove =       omap2_mcspi_remove,
1520 };
1521 
1522 module_platform_driver(omap2_mcspi_driver);
1523 MODULE_LICENSE("GPL");
1524 

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