Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/spi/spi-imx.c

  1 /*
  2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  3  * Copyright (C) 2008 Juergen Beisert
  4  *
  5  * This program is free software; you can redistribute it and/or
  6  * modify it under the terms of the GNU General Public License
  7  * as published by the Free Software Foundation; either version 2
  8  * of the License, or (at your option) any later version.
  9  * This program is distributed in the hope that it will be useful,
 10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 12  * GNU General Public License for more details.
 13  *
 14  * You should have received a copy of the GNU General Public License
 15  * along with this program; if not, write to the
 16  * Free Software Foundation
 17  * 51 Franklin Street, Fifth Floor
 18  * Boston, MA  02110-1301, USA.
 19  */
 20 
 21 #include <linux/clk.h>
 22 #include <linux/completion.h>
 23 #include <linux/delay.h>
 24 #include <linux/err.h>
 25 #include <linux/gpio.h>
 26 #include <linux/interrupt.h>
 27 #include <linux/io.h>
 28 #include <linux/irq.h>
 29 #include <linux/kernel.h>
 30 #include <linux/module.h>
 31 #include <linux/platform_device.h>
 32 #include <linux/slab.h>
 33 #include <linux/spi/spi.h>
 34 #include <linux/spi/spi_bitbang.h>
 35 #include <linux/types.h>
 36 #include <linux/of.h>
 37 #include <linux/of_device.h>
 38 #include <linux/of_gpio.h>
 39 
 40 #include <linux/platform_data/spi-imx.h>
 41 
 42 #define DRIVER_NAME "spi_imx"
 43 
 44 #define MXC_CSPIRXDATA          0x00
 45 #define MXC_CSPITXDATA          0x04
 46 #define MXC_CSPICTRL            0x08
 47 #define MXC_CSPIINT             0x0c
 48 #define MXC_RESET               0x1c
 49 
 50 /* generic defines to abstract from the different register layouts */
 51 #define MXC_INT_RR      (1 << 0) /* Receive data ready interrupt */
 52 #define MXC_INT_TE      (1 << 1) /* Transmit FIFO empty interrupt */
 53 
 54 struct spi_imx_config {
 55         unsigned int speed_hz;
 56         unsigned int bpw;
 57         unsigned int mode;
 58         u8 cs;
 59 };
 60 
 61 enum spi_imx_devtype {
 62         IMX1_CSPI,
 63         IMX21_CSPI,
 64         IMX27_CSPI,
 65         IMX31_CSPI,
 66         IMX35_CSPI,     /* CSPI on all i.mx except above */
 67         IMX51_ECSPI,    /* ECSPI on i.mx51 and later */
 68 };
 69 
 70 struct spi_imx_data;
 71 
 72 struct spi_imx_devtype_data {
 73         void (*intctrl)(struct spi_imx_data *, int);
 74         int (*config)(struct spi_imx_data *, struct spi_imx_config *);
 75         void (*trigger)(struct spi_imx_data *);
 76         int (*rx_available)(struct spi_imx_data *);
 77         void (*reset)(struct spi_imx_data *);
 78         enum spi_imx_devtype devtype;
 79 };
 80 
 81 struct spi_imx_data {
 82         struct spi_bitbang bitbang;
 83 
 84         struct completion xfer_done;
 85         void __iomem *base;
 86         int irq;
 87         struct clk *clk_per;
 88         struct clk *clk_ipg;
 89         unsigned long spi_clk;
 90 
 91         unsigned int count;
 92         void (*tx)(struct spi_imx_data *);
 93         void (*rx)(struct spi_imx_data *);
 94         void *rx_buf;
 95         const void *tx_buf;
 96         unsigned int txfifo; /* number of words pushed in tx FIFO */
 97 
 98         const struct spi_imx_devtype_data *devtype_data;
 99         int chipselect[0];
100 };
101 
102 static inline int is_imx27_cspi(struct spi_imx_data *d)
103 {
104         return d->devtype_data->devtype == IMX27_CSPI;
105 }
106 
107 static inline int is_imx35_cspi(struct spi_imx_data *d)
108 {
109         return d->devtype_data->devtype == IMX35_CSPI;
110 }
111 
112 static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d)
113 {
114         return (d->devtype_data->devtype == IMX51_ECSPI) ? 64 : 8;
115 }
116 
117 #define MXC_SPI_BUF_RX(type)                                            \
118 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx)         \
119 {                                                                       \
120         unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);       \
121                                                                         \
122         if (spi_imx->rx_buf) {                                          \
123                 *(type *)spi_imx->rx_buf = val;                         \
124                 spi_imx->rx_buf += sizeof(type);                        \
125         }                                                               \
126 }
127 
128 #define MXC_SPI_BUF_TX(type)                                            \
129 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx)         \
130 {                                                                       \
131         type val = 0;                                                   \
132                                                                         \
133         if (spi_imx->tx_buf) {                                          \
134                 val = *(type *)spi_imx->tx_buf;                         \
135                 spi_imx->tx_buf += sizeof(type);                        \
136         }                                                               \
137                                                                         \
138         spi_imx->count -= sizeof(type);                                 \
139                                                                         \
140         writel(val, spi_imx->base + MXC_CSPITXDATA);                    \
141 }
142 
143 MXC_SPI_BUF_RX(u8)
144 MXC_SPI_BUF_TX(u8)
145 MXC_SPI_BUF_RX(u16)
146 MXC_SPI_BUF_TX(u16)
147 MXC_SPI_BUF_RX(u32)
148 MXC_SPI_BUF_TX(u32)
149 
150 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
151  * (which is currently not the case in this driver)
152  */
153 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
154         256, 384, 512, 768, 1024};
155 
156 /* MX21, MX27 */
157 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
158                 unsigned int fspi, unsigned int max)
159 {
160         int i;
161 
162         for (i = 2; i < max; i++)
163                 if (fspi * mxc_clkdivs[i] >= fin)
164                         return i;
165 
166         return max;
167 }
168 
169 /* MX1, MX31, MX35, MX51 CSPI */
170 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
171                 unsigned int fspi)
172 {
173         int i, div = 4;
174 
175         for (i = 0; i < 7; i++) {
176                 if (fspi * div >= fin)
177                         return i;
178                 div <<= 1;
179         }
180 
181         return 7;
182 }
183 
184 #define MX51_ECSPI_CTRL         0x08
185 #define MX51_ECSPI_CTRL_ENABLE          (1 <<  0)
186 #define MX51_ECSPI_CTRL_XCH             (1 <<  2)
187 #define MX51_ECSPI_CTRL_MODE_MASK       (0xf << 4)
188 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET  8
189 #define MX51_ECSPI_CTRL_PREDIV_OFFSET   12
190 #define MX51_ECSPI_CTRL_CS(cs)          ((cs) << 18)
191 #define MX51_ECSPI_CTRL_BL_OFFSET       20
192 
193 #define MX51_ECSPI_CONFIG       0x0c
194 #define MX51_ECSPI_CONFIG_SCLKPHA(cs)   (1 << ((cs) +  0))
195 #define MX51_ECSPI_CONFIG_SCLKPOL(cs)   (1 << ((cs) +  4))
196 #define MX51_ECSPI_CONFIG_SBBCTRL(cs)   (1 << ((cs) +  8))
197 #define MX51_ECSPI_CONFIG_SSBPOL(cs)    (1 << ((cs) + 12))
198 #define MX51_ECSPI_CONFIG_SCLKCTL(cs)   (1 << ((cs) + 20))
199 
200 #define MX51_ECSPI_INT          0x10
201 #define MX51_ECSPI_INT_TEEN             (1 <<  0)
202 #define MX51_ECSPI_INT_RREN             (1 <<  3)
203 
204 #define MX51_ECSPI_STAT         0x18
205 #define MX51_ECSPI_STAT_RR              (1 <<  3)
206 
207 /* MX51 eCSPI */
208 static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi,
209                                       unsigned int *fres)
210 {
211         /*
212          * there are two 4-bit dividers, the pre-divider divides by
213          * $pre, the post-divider by 2^$post
214          */
215         unsigned int pre, post;
216 
217         if (unlikely(fspi > fin))
218                 return 0;
219 
220         post = fls(fin) - fls(fspi);
221         if (fin > fspi << post)
222                 post++;
223 
224         /* now we have: (fin <= fspi << post) with post being minimal */
225 
226         post = max(4U, post) - 4;
227         if (unlikely(post > 0xf)) {
228                 pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
229                                 __func__, fspi, fin);
230                 return 0xff;
231         }
232 
233         pre = DIV_ROUND_UP(fin, fspi << post) - 1;
234 
235         pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
236                         __func__, fin, fspi, post, pre);
237 
238         /* Resulting frequency for the SCLK line. */
239         *fres = (fin / (pre + 1)) >> post;
240 
241         return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
242                 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
243 }
244 
245 static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
246 {
247         unsigned val = 0;
248 
249         if (enable & MXC_INT_TE)
250                 val |= MX51_ECSPI_INT_TEEN;
251 
252         if (enable & MXC_INT_RR)
253                 val |= MX51_ECSPI_INT_RREN;
254 
255         writel(val, spi_imx->base + MX51_ECSPI_INT);
256 }
257 
258 static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
259 {
260         u32 reg;
261 
262         reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
263         reg |= MX51_ECSPI_CTRL_XCH;
264         writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
265 }
266 
267 static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
268                 struct spi_imx_config *config)
269 {
270         u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0;
271         u32 clk = config->speed_hz, delay;
272 
273         /*
274          * The hardware seems to have a race condition when changing modes. The
275          * current assumption is that the selection of the channel arrives
276          * earlier in the hardware than the mode bits when they are written at
277          * the same time.
278          * So set master mode for all channels as we do not support slave mode.
279          */
280         ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
281 
282         /* set clock speed */
283         ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz, &clk);
284 
285         /* set chip select to use */
286         ctrl |= MX51_ECSPI_CTRL_CS(config->cs);
287 
288         ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
289 
290         cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs);
291 
292         if (config->mode & SPI_CPHA)
293                 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
294 
295         if (config->mode & SPI_CPOL) {
296                 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
297                 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
298         }
299         if (config->mode & SPI_CS_HIGH)
300                 cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
301 
302         writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
303         writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
304 
305         /*
306          * Wait until the changes in the configuration register CONFIGREG
307          * propagate into the hardware. It takes exactly one tick of the
308          * SCLK clock, but we will wait two SCLK clock just to be sure. The
309          * effect of the delay it takes for the hardware to apply changes
310          * is noticable if the SCLK clock run very slow. In such a case, if
311          * the polarity of SCLK should be inverted, the GPIO ChipSelect might
312          * be asserted before the SCLK polarity changes, which would disrupt
313          * the SPI communication as the device on the other end would consider
314          * the change of SCLK polarity as a clock tick already.
315          */
316         delay = (2 * 1000000) / clk;
317         if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
318                 udelay(delay);
319         else                    /* SCLK is _very_ slow */
320                 usleep_range(delay, delay + 10);
321 
322         return 0;
323 }
324 
325 static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
326 {
327         return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
328 }
329 
330 static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx)
331 {
332         /* drain receive buffer */
333         while (mx51_ecspi_rx_available(spi_imx))
334                 readl(spi_imx->base + MXC_CSPIRXDATA);
335 }
336 
337 #define MX31_INTREG_TEEN        (1 << 0)
338 #define MX31_INTREG_RREN        (1 << 3)
339 
340 #define MX31_CSPICTRL_ENABLE    (1 << 0)
341 #define MX31_CSPICTRL_MASTER    (1 << 1)
342 #define MX31_CSPICTRL_XCH       (1 << 2)
343 #define MX31_CSPICTRL_POL       (1 << 4)
344 #define MX31_CSPICTRL_PHA       (1 << 5)
345 #define MX31_CSPICTRL_SSCTL     (1 << 6)
346 #define MX31_CSPICTRL_SSPOL     (1 << 7)
347 #define MX31_CSPICTRL_BC_SHIFT  8
348 #define MX35_CSPICTRL_BL_SHIFT  20
349 #define MX31_CSPICTRL_CS_SHIFT  24
350 #define MX35_CSPICTRL_CS_SHIFT  12
351 #define MX31_CSPICTRL_DR_SHIFT  16
352 
353 #define MX31_CSPISTATUS         0x14
354 #define MX31_STATUS_RR          (1 << 3)
355 
356 /* These functions also work for the i.MX35, but be aware that
357  * the i.MX35 has a slightly different register layout for bits
358  * we do not use here.
359  */
360 static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
361 {
362         unsigned int val = 0;
363 
364         if (enable & MXC_INT_TE)
365                 val |= MX31_INTREG_TEEN;
366         if (enable & MXC_INT_RR)
367                 val |= MX31_INTREG_RREN;
368 
369         writel(val, spi_imx->base + MXC_CSPIINT);
370 }
371 
372 static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
373 {
374         unsigned int reg;
375 
376         reg = readl(spi_imx->base + MXC_CSPICTRL);
377         reg |= MX31_CSPICTRL_XCH;
378         writel(reg, spi_imx->base + MXC_CSPICTRL);
379 }
380 
381 static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
382                 struct spi_imx_config *config)
383 {
384         unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
385         int cs = spi_imx->chipselect[config->cs];
386 
387         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
388                 MX31_CSPICTRL_DR_SHIFT;
389 
390         if (is_imx35_cspi(spi_imx)) {
391                 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
392                 reg |= MX31_CSPICTRL_SSCTL;
393         } else {
394                 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
395         }
396 
397         if (config->mode & SPI_CPHA)
398                 reg |= MX31_CSPICTRL_PHA;
399         if (config->mode & SPI_CPOL)
400                 reg |= MX31_CSPICTRL_POL;
401         if (config->mode & SPI_CS_HIGH)
402                 reg |= MX31_CSPICTRL_SSPOL;
403         if (cs < 0)
404                 reg |= (cs + 32) <<
405                         (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
406                                                   MX31_CSPICTRL_CS_SHIFT);
407 
408         writel(reg, spi_imx->base + MXC_CSPICTRL);
409 
410         return 0;
411 }
412 
413 static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
414 {
415         return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
416 }
417 
418 static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx)
419 {
420         /* drain receive buffer */
421         while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
422                 readl(spi_imx->base + MXC_CSPIRXDATA);
423 }
424 
425 #define MX21_INTREG_RR          (1 << 4)
426 #define MX21_INTREG_TEEN        (1 << 9)
427 #define MX21_INTREG_RREN        (1 << 13)
428 
429 #define MX21_CSPICTRL_POL       (1 << 5)
430 #define MX21_CSPICTRL_PHA       (1 << 6)
431 #define MX21_CSPICTRL_SSPOL     (1 << 8)
432 #define MX21_CSPICTRL_XCH       (1 << 9)
433 #define MX21_CSPICTRL_ENABLE    (1 << 10)
434 #define MX21_CSPICTRL_MASTER    (1 << 11)
435 #define MX21_CSPICTRL_DR_SHIFT  14
436 #define MX21_CSPICTRL_CS_SHIFT  19
437 
438 static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
439 {
440         unsigned int val = 0;
441 
442         if (enable & MXC_INT_TE)
443                 val |= MX21_INTREG_TEEN;
444         if (enable & MXC_INT_RR)
445                 val |= MX21_INTREG_RREN;
446 
447         writel(val, spi_imx->base + MXC_CSPIINT);
448 }
449 
450 static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
451 {
452         unsigned int reg;
453 
454         reg = readl(spi_imx->base + MXC_CSPICTRL);
455         reg |= MX21_CSPICTRL_XCH;
456         writel(reg, spi_imx->base + MXC_CSPICTRL);
457 }
458 
459 static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx,
460                 struct spi_imx_config *config)
461 {
462         unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
463         int cs = spi_imx->chipselect[config->cs];
464         unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
465 
466         reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) <<
467                 MX21_CSPICTRL_DR_SHIFT;
468         reg |= config->bpw - 1;
469 
470         if (config->mode & SPI_CPHA)
471                 reg |= MX21_CSPICTRL_PHA;
472         if (config->mode & SPI_CPOL)
473                 reg |= MX21_CSPICTRL_POL;
474         if (config->mode & SPI_CS_HIGH)
475                 reg |= MX21_CSPICTRL_SSPOL;
476         if (cs < 0)
477                 reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT;
478 
479         writel(reg, spi_imx->base + MXC_CSPICTRL);
480 
481         return 0;
482 }
483 
484 static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx)
485 {
486         return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
487 }
488 
489 static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx)
490 {
491         writel(1, spi_imx->base + MXC_RESET);
492 }
493 
494 #define MX1_INTREG_RR           (1 << 3)
495 #define MX1_INTREG_TEEN         (1 << 8)
496 #define MX1_INTREG_RREN         (1 << 11)
497 
498 #define MX1_CSPICTRL_POL        (1 << 4)
499 #define MX1_CSPICTRL_PHA        (1 << 5)
500 #define MX1_CSPICTRL_XCH        (1 << 8)
501 #define MX1_CSPICTRL_ENABLE     (1 << 9)
502 #define MX1_CSPICTRL_MASTER     (1 << 10)
503 #define MX1_CSPICTRL_DR_SHIFT   13
504 
505 static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
506 {
507         unsigned int val = 0;
508 
509         if (enable & MXC_INT_TE)
510                 val |= MX1_INTREG_TEEN;
511         if (enable & MXC_INT_RR)
512                 val |= MX1_INTREG_RREN;
513 
514         writel(val, spi_imx->base + MXC_CSPIINT);
515 }
516 
517 static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
518 {
519         unsigned int reg;
520 
521         reg = readl(spi_imx->base + MXC_CSPICTRL);
522         reg |= MX1_CSPICTRL_XCH;
523         writel(reg, spi_imx->base + MXC_CSPICTRL);
524 }
525 
526 static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
527                 struct spi_imx_config *config)
528 {
529         unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
530 
531         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
532                 MX1_CSPICTRL_DR_SHIFT;
533         reg |= config->bpw - 1;
534 
535         if (config->mode & SPI_CPHA)
536                 reg |= MX1_CSPICTRL_PHA;
537         if (config->mode & SPI_CPOL)
538                 reg |= MX1_CSPICTRL_POL;
539 
540         writel(reg, spi_imx->base + MXC_CSPICTRL);
541 
542         return 0;
543 }
544 
545 static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
546 {
547         return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
548 }
549 
550 static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
551 {
552         writel(1, spi_imx->base + MXC_RESET);
553 }
554 
555 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
556         .intctrl = mx1_intctrl,
557         .config = mx1_config,
558         .trigger = mx1_trigger,
559         .rx_available = mx1_rx_available,
560         .reset = mx1_reset,
561         .devtype = IMX1_CSPI,
562 };
563 
564 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
565         .intctrl = mx21_intctrl,
566         .config = mx21_config,
567         .trigger = mx21_trigger,
568         .rx_available = mx21_rx_available,
569         .reset = mx21_reset,
570         .devtype = IMX21_CSPI,
571 };
572 
573 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
574         /* i.mx27 cspi shares the functions with i.mx21 one */
575         .intctrl = mx21_intctrl,
576         .config = mx21_config,
577         .trigger = mx21_trigger,
578         .rx_available = mx21_rx_available,
579         .reset = mx21_reset,
580         .devtype = IMX27_CSPI,
581 };
582 
583 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
584         .intctrl = mx31_intctrl,
585         .config = mx31_config,
586         .trigger = mx31_trigger,
587         .rx_available = mx31_rx_available,
588         .reset = mx31_reset,
589         .devtype = IMX31_CSPI,
590 };
591 
592 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
593         /* i.mx35 and later cspi shares the functions with i.mx31 one */
594         .intctrl = mx31_intctrl,
595         .config = mx31_config,
596         .trigger = mx31_trigger,
597         .rx_available = mx31_rx_available,
598         .reset = mx31_reset,
599         .devtype = IMX35_CSPI,
600 };
601 
602 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
603         .intctrl = mx51_ecspi_intctrl,
604         .config = mx51_ecspi_config,
605         .trigger = mx51_ecspi_trigger,
606         .rx_available = mx51_ecspi_rx_available,
607         .reset = mx51_ecspi_reset,
608         .devtype = IMX51_ECSPI,
609 };
610 
611 static struct platform_device_id spi_imx_devtype[] = {
612         {
613                 .name = "imx1-cspi",
614                 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
615         }, {
616                 .name = "imx21-cspi",
617                 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
618         }, {
619                 .name = "imx27-cspi",
620                 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
621         }, {
622                 .name = "imx31-cspi",
623                 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
624         }, {
625                 .name = "imx35-cspi",
626                 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
627         }, {
628                 .name = "imx51-ecspi",
629                 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
630         }, {
631                 /* sentinel */
632         }
633 };
634 
635 static const struct of_device_id spi_imx_dt_ids[] = {
636         { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
637         { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
638         { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
639         { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
640         { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
641         { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
642         { /* sentinel */ }
643 };
644 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
645 
646 static void spi_imx_chipselect(struct spi_device *spi, int is_active)
647 {
648         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
649         int gpio = spi_imx->chipselect[spi->chip_select];
650         int active = is_active != BITBANG_CS_INACTIVE;
651         int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
652 
653         if (!gpio_is_valid(gpio))
654                 return;
655 
656         gpio_set_value(gpio, dev_is_lowactive ^ active);
657 }
658 
659 static void spi_imx_push(struct spi_imx_data *spi_imx)
660 {
661         while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) {
662                 if (!spi_imx->count)
663                         break;
664                 spi_imx->tx(spi_imx);
665                 spi_imx->txfifo++;
666         }
667 
668         spi_imx->devtype_data->trigger(spi_imx);
669 }
670 
671 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
672 {
673         struct spi_imx_data *spi_imx = dev_id;
674 
675         while (spi_imx->devtype_data->rx_available(spi_imx)) {
676                 spi_imx->rx(spi_imx);
677                 spi_imx->txfifo--;
678         }
679 
680         if (spi_imx->count) {
681                 spi_imx_push(spi_imx);
682                 return IRQ_HANDLED;
683         }
684 
685         if (spi_imx->txfifo) {
686                 /* No data left to push, but still waiting for rx data,
687                  * enable receive data available interrupt.
688                  */
689                 spi_imx->devtype_data->intctrl(
690                                 spi_imx, MXC_INT_RR);
691                 return IRQ_HANDLED;
692         }
693 
694         spi_imx->devtype_data->intctrl(spi_imx, 0);
695         complete(&spi_imx->xfer_done);
696 
697         return IRQ_HANDLED;
698 }
699 
700 static int spi_imx_setupxfer(struct spi_device *spi,
701                                  struct spi_transfer *t)
702 {
703         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
704         struct spi_imx_config config;
705 
706         config.bpw = t ? t->bits_per_word : spi->bits_per_word;
707         config.speed_hz  = t ? t->speed_hz : spi->max_speed_hz;
708         config.mode = spi->mode;
709         config.cs = spi->chip_select;
710 
711         if (!config.speed_hz)
712                 config.speed_hz = spi->max_speed_hz;
713         if (!config.bpw)
714                 config.bpw = spi->bits_per_word;
715 
716         /* Initialize the functions for transfer */
717         if (config.bpw <= 8) {
718                 spi_imx->rx = spi_imx_buf_rx_u8;
719                 spi_imx->tx = spi_imx_buf_tx_u8;
720         } else if (config.bpw <= 16) {
721                 spi_imx->rx = spi_imx_buf_rx_u16;
722                 spi_imx->tx = spi_imx_buf_tx_u16;
723         } else {
724                 spi_imx->rx = spi_imx_buf_rx_u32;
725                 spi_imx->tx = spi_imx_buf_tx_u32;
726         }
727 
728         spi_imx->devtype_data->config(spi_imx, &config);
729 
730         return 0;
731 }
732 
733 static int spi_imx_transfer(struct spi_device *spi,
734                                 struct spi_transfer *transfer)
735 {
736         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
737 
738         spi_imx->tx_buf = transfer->tx_buf;
739         spi_imx->rx_buf = transfer->rx_buf;
740         spi_imx->count = transfer->len;
741         spi_imx->txfifo = 0;
742 
743         reinit_completion(&spi_imx->xfer_done);
744 
745         spi_imx_push(spi_imx);
746 
747         spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
748 
749         wait_for_completion(&spi_imx->xfer_done);
750 
751         return transfer->len;
752 }
753 
754 static int spi_imx_setup(struct spi_device *spi)
755 {
756         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
757         int gpio = spi_imx->chipselect[spi->chip_select];
758 
759         dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
760                  spi->mode, spi->bits_per_word, spi->max_speed_hz);
761 
762         if (gpio_is_valid(gpio))
763                 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
764 
765         spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
766 
767         return 0;
768 }
769 
770 static void spi_imx_cleanup(struct spi_device *spi)
771 {
772 }
773 
774 static int
775 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
776 {
777         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
778         int ret;
779 
780         ret = clk_enable(spi_imx->clk_per);
781         if (ret)
782                 return ret;
783 
784         ret = clk_enable(spi_imx->clk_ipg);
785         if (ret) {
786                 clk_disable(spi_imx->clk_per);
787                 return ret;
788         }
789 
790         return 0;
791 }
792 
793 static int
794 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
795 {
796         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
797 
798         clk_disable(spi_imx->clk_ipg);
799         clk_disable(spi_imx->clk_per);
800         return 0;
801 }
802 
803 static int spi_imx_probe(struct platform_device *pdev)
804 {
805         struct device_node *np = pdev->dev.of_node;
806         const struct of_device_id *of_id =
807                         of_match_device(spi_imx_dt_ids, &pdev->dev);
808         struct spi_imx_master *mxc_platform_info =
809                         dev_get_platdata(&pdev->dev);
810         struct spi_master *master;
811         struct spi_imx_data *spi_imx;
812         struct resource *res;
813         int i, ret, num_cs;
814 
815         if (!np && !mxc_platform_info) {
816                 dev_err(&pdev->dev, "can't get the platform data\n");
817                 return -EINVAL;
818         }
819 
820         ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs);
821         if (ret < 0) {
822                 if (mxc_platform_info)
823                         num_cs = mxc_platform_info->num_chipselect;
824                 else
825                         return ret;
826         }
827 
828         master = spi_alloc_master(&pdev->dev,
829                         sizeof(struct spi_imx_data) + sizeof(int) * num_cs);
830         if (!master)
831                 return -ENOMEM;
832 
833         platform_set_drvdata(pdev, master);
834 
835         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
836         master->bus_num = pdev->id;
837         master->num_chipselect = num_cs;
838 
839         spi_imx = spi_master_get_devdata(master);
840         spi_imx->bitbang.master = master;
841 
842         for (i = 0; i < master->num_chipselect; i++) {
843                 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
844                 if (!gpio_is_valid(cs_gpio) && mxc_platform_info)
845                         cs_gpio = mxc_platform_info->chipselect[i];
846 
847                 spi_imx->chipselect[i] = cs_gpio;
848                 if (!gpio_is_valid(cs_gpio))
849                         continue;
850 
851                 ret = devm_gpio_request(&pdev->dev, spi_imx->chipselect[i],
852                                         DRIVER_NAME);
853                 if (ret) {
854                         dev_err(&pdev->dev, "can't get cs gpios\n");
855                         goto out_master_put;
856                 }
857         }
858 
859         spi_imx->bitbang.chipselect = spi_imx_chipselect;
860         spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
861         spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
862         spi_imx->bitbang.master->setup = spi_imx_setup;
863         spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
864         spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
865         spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
866         spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
867 
868         init_completion(&spi_imx->xfer_done);
869 
870         spi_imx->devtype_data = of_id ? of_id->data :
871                 (struct spi_imx_devtype_data *) pdev->id_entry->driver_data;
872 
873         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
874         spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
875         if (IS_ERR(spi_imx->base)) {
876                 ret = PTR_ERR(spi_imx->base);
877                 goto out_master_put;
878         }
879 
880         spi_imx->irq = platform_get_irq(pdev, 0);
881         if (spi_imx->irq < 0) {
882                 ret = spi_imx->irq;
883                 goto out_master_put;
884         }
885 
886         ret = devm_request_irq(&pdev->dev, spi_imx->irq, spi_imx_isr, 0,
887                                dev_name(&pdev->dev), spi_imx);
888         if (ret) {
889                 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
890                 goto out_master_put;
891         }
892 
893         spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
894         if (IS_ERR(spi_imx->clk_ipg)) {
895                 ret = PTR_ERR(spi_imx->clk_ipg);
896                 goto out_master_put;
897         }
898 
899         spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
900         if (IS_ERR(spi_imx->clk_per)) {
901                 ret = PTR_ERR(spi_imx->clk_per);
902                 goto out_master_put;
903         }
904 
905         ret = clk_prepare_enable(spi_imx->clk_per);
906         if (ret)
907                 goto out_master_put;
908 
909         ret = clk_prepare_enable(spi_imx->clk_ipg);
910         if (ret)
911                 goto out_put_per;
912 
913         spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
914 
915         spi_imx->devtype_data->reset(spi_imx);
916 
917         spi_imx->devtype_data->intctrl(spi_imx, 0);
918 
919         master->dev.of_node = pdev->dev.of_node;
920         ret = spi_bitbang_start(&spi_imx->bitbang);
921         if (ret) {
922                 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
923                 goto out_clk_put;
924         }
925 
926         dev_info(&pdev->dev, "probed\n");
927 
928         clk_disable(spi_imx->clk_ipg);
929         clk_disable(spi_imx->clk_per);
930         return ret;
931 
932 out_clk_put:
933         clk_disable_unprepare(spi_imx->clk_ipg);
934 out_put_per:
935         clk_disable_unprepare(spi_imx->clk_per);
936 out_master_put:
937         spi_master_put(master);
938 
939         return ret;
940 }
941 
942 static int spi_imx_remove(struct platform_device *pdev)
943 {
944         struct spi_master *master = platform_get_drvdata(pdev);
945         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
946 
947         spi_bitbang_stop(&spi_imx->bitbang);
948 
949         writel(0, spi_imx->base + MXC_CSPICTRL);
950         clk_unprepare(spi_imx->clk_ipg);
951         clk_unprepare(spi_imx->clk_per);
952         spi_master_put(master);
953 
954         return 0;
955 }
956 
957 static struct platform_driver spi_imx_driver = {
958         .driver = {
959                    .name = DRIVER_NAME,
960                    .owner = THIS_MODULE,
961                    .of_match_table = spi_imx_dt_ids,
962                    },
963         .id_table = spi_imx_devtype,
964         .probe = spi_imx_probe,
965         .remove = spi_imx_remove,
966 };
967 module_platform_driver(spi_imx_driver);
968 
969 MODULE_DESCRIPTION("SPI Master Controller driver");
970 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
971 MODULE_LICENSE("GPL");
972 MODULE_ALIAS("platform:" DRIVER_NAME);
973 

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