Version:  2.0.40 2.2.26 2.4.37 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9

Linux/drivers/spi/spi-imx.c

  1 /*
  2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  3  * Copyright (C) 2008 Juergen Beisert
  4  *
  5  * This program is free software; you can redistribute it and/or
  6  * modify it under the terms of the GNU General Public License
  7  * as published by the Free Software Foundation; either version 2
  8  * of the License, or (at your option) any later version.
  9  * This program is distributed in the hope that it will be useful,
 10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 12  * GNU General Public License for more details.
 13  *
 14  * You should have received a copy of the GNU General Public License
 15  * along with this program; if not, write to the
 16  * Free Software Foundation
 17  * 51 Franklin Street, Fifth Floor
 18  * Boston, MA  02110-1301, USA.
 19  */
 20 
 21 #include <linux/clk.h>
 22 #include <linux/completion.h>
 23 #include <linux/delay.h>
 24 #include <linux/dmaengine.h>
 25 #include <linux/dma-mapping.h>
 26 #include <linux/err.h>
 27 #include <linux/gpio.h>
 28 #include <linux/interrupt.h>
 29 #include <linux/io.h>
 30 #include <linux/irq.h>
 31 #include <linux/kernel.h>
 32 #include <linux/module.h>
 33 #include <linux/platform_device.h>
 34 #include <linux/slab.h>
 35 #include <linux/spi/spi.h>
 36 #include <linux/spi/spi_bitbang.h>
 37 #include <linux/types.h>
 38 #include <linux/of.h>
 39 #include <linux/of_device.h>
 40 #include <linux/of_gpio.h>
 41 
 42 #include <linux/platform_data/dma-imx.h>
 43 #include <linux/platform_data/spi-imx.h>
 44 
 45 #define DRIVER_NAME "spi_imx"
 46 
 47 #define MXC_CSPIRXDATA          0x00
 48 #define MXC_CSPITXDATA          0x04
 49 #define MXC_CSPICTRL            0x08
 50 #define MXC_CSPIINT             0x0c
 51 #define MXC_RESET               0x1c
 52 
 53 /* generic defines to abstract from the different register layouts */
 54 #define MXC_INT_RR      (1 << 0) /* Receive data ready interrupt */
 55 #define MXC_INT_TE      (1 << 1) /* Transmit FIFO empty interrupt */
 56 
 57 /* The maximum  bytes that a sdma BD can transfer.*/
 58 #define MAX_SDMA_BD_BYTES  (1 << 15)
 59 struct spi_imx_config {
 60         unsigned int speed_hz;
 61         unsigned int bpw;
 62 };
 63 
 64 enum spi_imx_devtype {
 65         IMX1_CSPI,
 66         IMX21_CSPI,
 67         IMX27_CSPI,
 68         IMX31_CSPI,
 69         IMX35_CSPI,     /* CSPI on all i.mx except above */
 70         IMX51_ECSPI,    /* ECSPI on i.mx51 and later */
 71 };
 72 
 73 struct spi_imx_data;
 74 
 75 struct spi_imx_devtype_data {
 76         void (*intctrl)(struct spi_imx_data *, int);
 77         int (*config)(struct spi_device *, struct spi_imx_config *);
 78         void (*trigger)(struct spi_imx_data *);
 79         int (*rx_available)(struct spi_imx_data *);
 80         void (*reset)(struct spi_imx_data *);
 81         enum spi_imx_devtype devtype;
 82 };
 83 
 84 struct spi_imx_data {
 85         struct spi_bitbang bitbang;
 86         struct device *dev;
 87 
 88         struct completion xfer_done;
 89         void __iomem *base;
 90         unsigned long base_phys;
 91 
 92         struct clk *clk_per;
 93         struct clk *clk_ipg;
 94         unsigned long spi_clk;
 95         unsigned int spi_bus_clk;
 96 
 97         unsigned int bytes_per_word;
 98 
 99         unsigned int count;
100         void (*tx)(struct spi_imx_data *);
101         void (*rx)(struct spi_imx_data *);
102         void *rx_buf;
103         const void *tx_buf;
104         unsigned int txfifo; /* number of words pushed in tx FIFO */
105 
106         /* DMA */
107         bool usedma;
108         u32 wml;
109         struct completion dma_rx_completion;
110         struct completion dma_tx_completion;
111 
112         const struct spi_imx_devtype_data *devtype_data;
113 };
114 
115 static inline int is_imx27_cspi(struct spi_imx_data *d)
116 {
117         return d->devtype_data->devtype == IMX27_CSPI;
118 }
119 
120 static inline int is_imx35_cspi(struct spi_imx_data *d)
121 {
122         return d->devtype_data->devtype == IMX35_CSPI;
123 }
124 
125 static inline int is_imx51_ecspi(struct spi_imx_data *d)
126 {
127         return d->devtype_data->devtype == IMX51_ECSPI;
128 }
129 
130 static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d)
131 {
132         return is_imx51_ecspi(d) ? 64 : 8;
133 }
134 
135 #define MXC_SPI_BUF_RX(type)                                            \
136 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx)         \
137 {                                                                       \
138         unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);       \
139                                                                         \
140         if (spi_imx->rx_buf) {                                          \
141                 *(type *)spi_imx->rx_buf = val;                         \
142                 spi_imx->rx_buf += sizeof(type);                        \
143         }                                                               \
144 }
145 
146 #define MXC_SPI_BUF_TX(type)                                            \
147 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx)         \
148 {                                                                       \
149         type val = 0;                                                   \
150                                                                         \
151         if (spi_imx->tx_buf) {                                          \
152                 val = *(type *)spi_imx->tx_buf;                         \
153                 spi_imx->tx_buf += sizeof(type);                        \
154         }                                                               \
155                                                                         \
156         spi_imx->count -= sizeof(type);                                 \
157                                                                         \
158         writel(val, spi_imx->base + MXC_CSPITXDATA);                    \
159 }
160 
161 MXC_SPI_BUF_RX(u8)
162 MXC_SPI_BUF_TX(u8)
163 MXC_SPI_BUF_RX(u16)
164 MXC_SPI_BUF_TX(u16)
165 MXC_SPI_BUF_RX(u32)
166 MXC_SPI_BUF_TX(u32)
167 
168 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
169  * (which is currently not the case in this driver)
170  */
171 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
172         256, 384, 512, 768, 1024};
173 
174 /* MX21, MX27 */
175 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
176                 unsigned int fspi, unsigned int max)
177 {
178         int i;
179 
180         for (i = 2; i < max; i++)
181                 if (fspi * mxc_clkdivs[i] >= fin)
182                         return i;
183 
184         return max;
185 }
186 
187 /* MX1, MX31, MX35, MX51 CSPI */
188 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
189                 unsigned int fspi, unsigned int *fres)
190 {
191         int i, div = 4;
192 
193         for (i = 0; i < 7; i++) {
194                 if (fspi * div >= fin)
195                         goto out;
196                 div <<= 1;
197         }
198 
199 out:
200         *fres = fin / div;
201         return i;
202 }
203 
204 static int spi_imx_bytes_per_word(const int bpw)
205 {
206         return DIV_ROUND_UP(bpw, BITS_PER_BYTE);
207 }
208 
209 static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
210                          struct spi_transfer *transfer)
211 {
212         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
213         unsigned int bpw;
214 
215         if (!master->dma_rx)
216                 return false;
217 
218         if (!transfer)
219                 return false;
220 
221         bpw = transfer->bits_per_word;
222         if (!bpw)
223                 bpw = spi->bits_per_word;
224 
225         bpw = spi_imx_bytes_per_word(bpw);
226 
227         if (bpw != 1 && bpw != 2 && bpw != 4)
228                 return false;
229 
230         if (transfer->len < spi_imx->wml * bpw)
231                 return false;
232 
233         if (transfer->len % (spi_imx->wml * bpw))
234                 return false;
235 
236         return true;
237 }
238 
239 #define MX51_ECSPI_CTRL         0x08
240 #define MX51_ECSPI_CTRL_ENABLE          (1 <<  0)
241 #define MX51_ECSPI_CTRL_XCH             (1 <<  2)
242 #define MX51_ECSPI_CTRL_SMC             (1 << 3)
243 #define MX51_ECSPI_CTRL_MODE_MASK       (0xf << 4)
244 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET  8
245 #define MX51_ECSPI_CTRL_PREDIV_OFFSET   12
246 #define MX51_ECSPI_CTRL_CS(cs)          ((cs) << 18)
247 #define MX51_ECSPI_CTRL_BL_OFFSET       20
248 
249 #define MX51_ECSPI_CONFIG       0x0c
250 #define MX51_ECSPI_CONFIG_SCLKPHA(cs)   (1 << ((cs) +  0))
251 #define MX51_ECSPI_CONFIG_SCLKPOL(cs)   (1 << ((cs) +  4))
252 #define MX51_ECSPI_CONFIG_SBBCTRL(cs)   (1 << ((cs) +  8))
253 #define MX51_ECSPI_CONFIG_SSBPOL(cs)    (1 << ((cs) + 12))
254 #define MX51_ECSPI_CONFIG_SCLKCTL(cs)   (1 << ((cs) + 20))
255 
256 #define MX51_ECSPI_INT          0x10
257 #define MX51_ECSPI_INT_TEEN             (1 <<  0)
258 #define MX51_ECSPI_INT_RREN             (1 <<  3)
259 
260 #define MX51_ECSPI_DMA      0x14
261 #define MX51_ECSPI_DMA_TX_WML(wml)      ((wml) & 0x3f)
262 #define MX51_ECSPI_DMA_RX_WML(wml)      (((wml) & 0x3f) << 16)
263 #define MX51_ECSPI_DMA_RXT_WML(wml)     (((wml) & 0x3f) << 24)
264 
265 #define MX51_ECSPI_DMA_TEDEN            (1 << 7)
266 #define MX51_ECSPI_DMA_RXDEN            (1 << 23)
267 #define MX51_ECSPI_DMA_RXTDEN           (1 << 31)
268 
269 #define MX51_ECSPI_STAT         0x18
270 #define MX51_ECSPI_STAT_RR              (1 <<  3)
271 
272 #define MX51_ECSPI_TESTREG      0x20
273 #define MX51_ECSPI_TESTREG_LBC  BIT(31)
274 
275 /* MX51 eCSPI */
276 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
277                                       unsigned int fspi, unsigned int *fres)
278 {
279         /*
280          * there are two 4-bit dividers, the pre-divider divides by
281          * $pre, the post-divider by 2^$post
282          */
283         unsigned int pre, post;
284         unsigned int fin = spi_imx->spi_clk;
285 
286         if (unlikely(fspi > fin))
287                 return 0;
288 
289         post = fls(fin) - fls(fspi);
290         if (fin > fspi << post)
291                 post++;
292 
293         /* now we have: (fin <= fspi << post) with post being minimal */
294 
295         post = max(4U, post) - 4;
296         if (unlikely(post > 0xf)) {
297                 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
298                                 fspi, fin);
299                 return 0xff;
300         }
301 
302         pre = DIV_ROUND_UP(fin, fspi << post) - 1;
303 
304         dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
305                         __func__, fin, fspi, post, pre);
306 
307         /* Resulting frequency for the SCLK line. */
308         *fres = (fin / (pre + 1)) >> post;
309 
310         return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
311                 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
312 }
313 
314 static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
315 {
316         unsigned val = 0;
317 
318         if (enable & MXC_INT_TE)
319                 val |= MX51_ECSPI_INT_TEEN;
320 
321         if (enable & MXC_INT_RR)
322                 val |= MX51_ECSPI_INT_RREN;
323 
324         writel(val, spi_imx->base + MX51_ECSPI_INT);
325 }
326 
327 static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
328 {
329         u32 reg;
330 
331         reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
332         reg |= MX51_ECSPI_CTRL_XCH;
333         writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
334 }
335 
336 static int mx51_ecspi_config(struct spi_device *spi,
337                              struct spi_imx_config *config)
338 {
339         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
340         u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
341         u32 clk = config->speed_hz, delay, reg;
342         u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
343 
344         /*
345          * The hardware seems to have a race condition when changing modes. The
346          * current assumption is that the selection of the channel arrives
347          * earlier in the hardware than the mode bits when they are written at
348          * the same time.
349          * So set master mode for all channels as we do not support slave mode.
350          */
351         ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
352 
353         /* set clock speed */
354         ctrl |= mx51_ecspi_clkdiv(spi_imx, config->speed_hz, &clk);
355         spi_imx->spi_bus_clk = clk;
356 
357         /* set chip select to use */
358         ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
359 
360         ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
361 
362         cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
363 
364         if (spi->mode & SPI_CPHA)
365                 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
366         else
367                 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
368 
369         if (spi->mode & SPI_CPOL) {
370                 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
371                 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
372         } else {
373                 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
374                 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
375         }
376         if (spi->mode & SPI_CS_HIGH)
377                 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
378         else
379                 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
380 
381         if (spi_imx->usedma)
382                 ctrl |= MX51_ECSPI_CTRL_SMC;
383 
384         /* CTRL register always go first to bring out controller from reset */
385         writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
386 
387         reg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
388         if (spi->mode & SPI_LOOP)
389                 reg |= MX51_ECSPI_TESTREG_LBC;
390         else
391                 reg &= ~MX51_ECSPI_TESTREG_LBC;
392         writel(reg, spi_imx->base + MX51_ECSPI_TESTREG);
393 
394         writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
395 
396         /*
397          * Wait until the changes in the configuration register CONFIGREG
398          * propagate into the hardware. It takes exactly one tick of the
399          * SCLK clock, but we will wait two SCLK clock just to be sure. The
400          * effect of the delay it takes for the hardware to apply changes
401          * is noticable if the SCLK clock run very slow. In such a case, if
402          * the polarity of SCLK should be inverted, the GPIO ChipSelect might
403          * be asserted before the SCLK polarity changes, which would disrupt
404          * the SPI communication as the device on the other end would consider
405          * the change of SCLK polarity as a clock tick already.
406          */
407         delay = (2 * 1000000) / clk;
408         if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
409                 udelay(delay);
410         else                    /* SCLK is _very_ slow */
411                 usleep_range(delay, delay + 10);
412 
413         /*
414          * Configure the DMA register: setup the watermark
415          * and enable DMA request.
416          */
417 
418         writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml) |
419                 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
420                 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
421                 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
422                 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
423 
424         return 0;
425 }
426 
427 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
428 {
429         return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
430 }
431 
432 static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
433 {
434         /* drain receive buffer */
435         while (mx51_ecspi_rx_available(spi_imx))
436                 readl(spi_imx->base + MXC_CSPIRXDATA);
437 }
438 
439 #define MX31_INTREG_TEEN        (1 << 0)
440 #define MX31_INTREG_RREN        (1 << 3)
441 
442 #define MX31_CSPICTRL_ENABLE    (1 << 0)
443 #define MX31_CSPICTRL_MASTER    (1 << 1)
444 #define MX31_CSPICTRL_XCH       (1 << 2)
445 #define MX31_CSPICTRL_POL       (1 << 4)
446 #define MX31_CSPICTRL_PHA       (1 << 5)
447 #define MX31_CSPICTRL_SSCTL     (1 << 6)
448 #define MX31_CSPICTRL_SSPOL     (1 << 7)
449 #define MX31_CSPICTRL_BC_SHIFT  8
450 #define MX35_CSPICTRL_BL_SHIFT  20
451 #define MX31_CSPICTRL_CS_SHIFT  24
452 #define MX35_CSPICTRL_CS_SHIFT  12
453 #define MX31_CSPICTRL_DR_SHIFT  16
454 
455 #define MX31_CSPISTATUS         0x14
456 #define MX31_STATUS_RR          (1 << 3)
457 
458 #define MX31_CSPI_TESTREG       0x1C
459 #define MX31_TEST_LBC           (1 << 14)
460 
461 /* These functions also work for the i.MX35, but be aware that
462  * the i.MX35 has a slightly different register layout for bits
463  * we do not use here.
464  */
465 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
466 {
467         unsigned int val = 0;
468 
469         if (enable & MXC_INT_TE)
470                 val |= MX31_INTREG_TEEN;
471         if (enable & MXC_INT_RR)
472                 val |= MX31_INTREG_RREN;
473 
474         writel(val, spi_imx->base + MXC_CSPIINT);
475 }
476 
477 static void mx31_trigger(struct spi_imx_data *spi_imx)
478 {
479         unsigned int reg;
480 
481         reg = readl(spi_imx->base + MXC_CSPICTRL);
482         reg |= MX31_CSPICTRL_XCH;
483         writel(reg, spi_imx->base + MXC_CSPICTRL);
484 }
485 
486 static int mx31_config(struct spi_device *spi, struct spi_imx_config *config)
487 {
488         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
489         unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
490         unsigned int clk;
491 
492         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz, &clk) <<
493                 MX31_CSPICTRL_DR_SHIFT;
494         spi_imx->spi_bus_clk = clk;
495 
496         if (is_imx35_cspi(spi_imx)) {
497                 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
498                 reg |= MX31_CSPICTRL_SSCTL;
499         } else {
500                 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
501         }
502 
503         if (spi->mode & SPI_CPHA)
504                 reg |= MX31_CSPICTRL_PHA;
505         if (spi->mode & SPI_CPOL)
506                 reg |= MX31_CSPICTRL_POL;
507         if (spi->mode & SPI_CS_HIGH)
508                 reg |= MX31_CSPICTRL_SSPOL;
509         if (spi->cs_gpio < 0)
510                 reg |= (spi->cs_gpio + 32) <<
511                         (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
512                                                   MX31_CSPICTRL_CS_SHIFT);
513 
514         writel(reg, spi_imx->base + MXC_CSPICTRL);
515 
516         reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
517         if (spi->mode & SPI_LOOP)
518                 reg |= MX31_TEST_LBC;
519         else
520                 reg &= ~MX31_TEST_LBC;
521         writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
522 
523         return 0;
524 }
525 
526 static int mx31_rx_available(struct spi_imx_data *spi_imx)
527 {
528         return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
529 }
530 
531 static void mx31_reset(struct spi_imx_data *spi_imx)
532 {
533         /* drain receive buffer */
534         while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
535                 readl(spi_imx->base + MXC_CSPIRXDATA);
536 }
537 
538 #define MX21_INTREG_RR          (1 << 4)
539 #define MX21_INTREG_TEEN        (1 << 9)
540 #define MX21_INTREG_RREN        (1 << 13)
541 
542 #define MX21_CSPICTRL_POL       (1 << 5)
543 #define MX21_CSPICTRL_PHA       (1 << 6)
544 #define MX21_CSPICTRL_SSPOL     (1 << 8)
545 #define MX21_CSPICTRL_XCH       (1 << 9)
546 #define MX21_CSPICTRL_ENABLE    (1 << 10)
547 #define MX21_CSPICTRL_MASTER    (1 << 11)
548 #define MX21_CSPICTRL_DR_SHIFT  14
549 #define MX21_CSPICTRL_CS_SHIFT  19
550 
551 static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
552 {
553         unsigned int val = 0;
554 
555         if (enable & MXC_INT_TE)
556                 val |= MX21_INTREG_TEEN;
557         if (enable & MXC_INT_RR)
558                 val |= MX21_INTREG_RREN;
559 
560         writel(val, spi_imx->base + MXC_CSPIINT);
561 }
562 
563 static void mx21_trigger(struct spi_imx_data *spi_imx)
564 {
565         unsigned int reg;
566 
567         reg = readl(spi_imx->base + MXC_CSPICTRL);
568         reg |= MX21_CSPICTRL_XCH;
569         writel(reg, spi_imx->base + MXC_CSPICTRL);
570 }
571 
572 static int mx21_config(struct spi_device *spi, struct spi_imx_config *config)
573 {
574         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
575         unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
576         unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
577 
578         reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) <<
579                 MX21_CSPICTRL_DR_SHIFT;
580         reg |= config->bpw - 1;
581 
582         if (spi->mode & SPI_CPHA)
583                 reg |= MX21_CSPICTRL_PHA;
584         if (spi->mode & SPI_CPOL)
585                 reg |= MX21_CSPICTRL_POL;
586         if (spi->mode & SPI_CS_HIGH)
587                 reg |= MX21_CSPICTRL_SSPOL;
588         if (spi->cs_gpio < 0)
589                 reg |= (spi->cs_gpio + 32) << MX21_CSPICTRL_CS_SHIFT;
590 
591         writel(reg, spi_imx->base + MXC_CSPICTRL);
592 
593         return 0;
594 }
595 
596 static int mx21_rx_available(struct spi_imx_data *spi_imx)
597 {
598         return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
599 }
600 
601 static void mx21_reset(struct spi_imx_data *spi_imx)
602 {
603         writel(1, spi_imx->base + MXC_RESET);
604 }
605 
606 #define MX1_INTREG_RR           (1 << 3)
607 #define MX1_INTREG_TEEN         (1 << 8)
608 #define MX1_INTREG_RREN         (1 << 11)
609 
610 #define MX1_CSPICTRL_POL        (1 << 4)
611 #define MX1_CSPICTRL_PHA        (1 << 5)
612 #define MX1_CSPICTRL_XCH        (1 << 8)
613 #define MX1_CSPICTRL_ENABLE     (1 << 9)
614 #define MX1_CSPICTRL_MASTER     (1 << 10)
615 #define MX1_CSPICTRL_DR_SHIFT   13
616 
617 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
618 {
619         unsigned int val = 0;
620 
621         if (enable & MXC_INT_TE)
622                 val |= MX1_INTREG_TEEN;
623         if (enable & MXC_INT_RR)
624                 val |= MX1_INTREG_RREN;
625 
626         writel(val, spi_imx->base + MXC_CSPIINT);
627 }
628 
629 static void mx1_trigger(struct spi_imx_data *spi_imx)
630 {
631         unsigned int reg;
632 
633         reg = readl(spi_imx->base + MXC_CSPICTRL);
634         reg |= MX1_CSPICTRL_XCH;
635         writel(reg, spi_imx->base + MXC_CSPICTRL);
636 }
637 
638 static int mx1_config(struct spi_device *spi, struct spi_imx_config *config)
639 {
640         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
641         unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
642         unsigned int clk;
643 
644         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz, &clk) <<
645                 MX1_CSPICTRL_DR_SHIFT;
646         spi_imx->spi_bus_clk = clk;
647 
648         reg |= config->bpw - 1;
649 
650         if (spi->mode & SPI_CPHA)
651                 reg |= MX1_CSPICTRL_PHA;
652         if (spi->mode & SPI_CPOL)
653                 reg |= MX1_CSPICTRL_POL;
654 
655         writel(reg, spi_imx->base + MXC_CSPICTRL);
656 
657         return 0;
658 }
659 
660 static int mx1_rx_available(struct spi_imx_data *spi_imx)
661 {
662         return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
663 }
664 
665 static void mx1_reset(struct spi_imx_data *spi_imx)
666 {
667         writel(1, spi_imx->base + MXC_RESET);
668 }
669 
670 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
671         .intctrl = mx1_intctrl,
672         .config = mx1_config,
673         .trigger = mx1_trigger,
674         .rx_available = mx1_rx_available,
675         .reset = mx1_reset,
676         .devtype = IMX1_CSPI,
677 };
678 
679 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
680         .intctrl = mx21_intctrl,
681         .config = mx21_config,
682         .trigger = mx21_trigger,
683         .rx_available = mx21_rx_available,
684         .reset = mx21_reset,
685         .devtype = IMX21_CSPI,
686 };
687 
688 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
689         /* i.mx27 cspi shares the functions with i.mx21 one */
690         .intctrl = mx21_intctrl,
691         .config = mx21_config,
692         .trigger = mx21_trigger,
693         .rx_available = mx21_rx_available,
694         .reset = mx21_reset,
695         .devtype = IMX27_CSPI,
696 };
697 
698 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
699         .intctrl = mx31_intctrl,
700         .config = mx31_config,
701         .trigger = mx31_trigger,
702         .rx_available = mx31_rx_available,
703         .reset = mx31_reset,
704         .devtype = IMX31_CSPI,
705 };
706 
707 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
708         /* i.mx35 and later cspi shares the functions with i.mx31 one */
709         .intctrl = mx31_intctrl,
710         .config = mx31_config,
711         .trigger = mx31_trigger,
712         .rx_available = mx31_rx_available,
713         .reset = mx31_reset,
714         .devtype = IMX35_CSPI,
715 };
716 
717 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
718         .intctrl = mx51_ecspi_intctrl,
719         .config = mx51_ecspi_config,
720         .trigger = mx51_ecspi_trigger,
721         .rx_available = mx51_ecspi_rx_available,
722         .reset = mx51_ecspi_reset,
723         .devtype = IMX51_ECSPI,
724 };
725 
726 static const struct platform_device_id spi_imx_devtype[] = {
727         {
728                 .name = "imx1-cspi",
729                 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
730         }, {
731                 .name = "imx21-cspi",
732                 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
733         }, {
734                 .name = "imx27-cspi",
735                 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
736         }, {
737                 .name = "imx31-cspi",
738                 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
739         }, {
740                 .name = "imx35-cspi",
741                 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
742         }, {
743                 .name = "imx51-ecspi",
744                 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
745         }, {
746                 /* sentinel */
747         }
748 };
749 
750 static const struct of_device_id spi_imx_dt_ids[] = {
751         { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
752         { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
753         { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
754         { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
755         { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
756         { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
757         { /* sentinel */ }
758 };
759 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
760 
761 static void spi_imx_chipselect(struct spi_device *spi, int is_active)
762 {
763         int active = is_active != BITBANG_CS_INACTIVE;
764         int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
765 
766         if (!gpio_is_valid(spi->cs_gpio))
767                 return;
768 
769         gpio_set_value(spi->cs_gpio, dev_is_lowactive ^ active);
770 }
771 
772 static void spi_imx_push(struct spi_imx_data *spi_imx)
773 {
774         while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) {
775                 if (!spi_imx->count)
776                         break;
777                 spi_imx->tx(spi_imx);
778                 spi_imx->txfifo++;
779         }
780 
781         spi_imx->devtype_data->trigger(spi_imx);
782 }
783 
784 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
785 {
786         struct spi_imx_data *spi_imx = dev_id;
787 
788         while (spi_imx->devtype_data->rx_available(spi_imx)) {
789                 spi_imx->rx(spi_imx);
790                 spi_imx->txfifo--;
791         }
792 
793         if (spi_imx->count) {
794                 spi_imx_push(spi_imx);
795                 return IRQ_HANDLED;
796         }
797 
798         if (spi_imx->txfifo) {
799                 /* No data left to push, but still waiting for rx data,
800                  * enable receive data available interrupt.
801                  */
802                 spi_imx->devtype_data->intctrl(
803                                 spi_imx, MXC_INT_RR);
804                 return IRQ_HANDLED;
805         }
806 
807         spi_imx->devtype_data->intctrl(spi_imx, 0);
808         complete(&spi_imx->xfer_done);
809 
810         return IRQ_HANDLED;
811 }
812 
813 static int spi_imx_dma_configure(struct spi_master *master,
814                                  int bytes_per_word)
815 {
816         int ret;
817         enum dma_slave_buswidth buswidth;
818         struct dma_slave_config rx = {}, tx = {};
819         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
820 
821         if (bytes_per_word == spi_imx->bytes_per_word)
822                 /* Same as last time */
823                 return 0;
824 
825         switch (bytes_per_word) {
826         case 4:
827                 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
828                 break;
829         case 2:
830                 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
831                 break;
832         case 1:
833                 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
834                 break;
835         default:
836                 return -EINVAL;
837         }
838 
839         tx.direction = DMA_MEM_TO_DEV;
840         tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
841         tx.dst_addr_width = buswidth;
842         tx.dst_maxburst = spi_imx->wml;
843         ret = dmaengine_slave_config(master->dma_tx, &tx);
844         if (ret) {
845                 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
846                 return ret;
847         }
848 
849         rx.direction = DMA_DEV_TO_MEM;
850         rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
851         rx.src_addr_width = buswidth;
852         rx.src_maxburst = spi_imx->wml;
853         ret = dmaengine_slave_config(master->dma_rx, &rx);
854         if (ret) {
855                 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
856                 return ret;
857         }
858 
859         spi_imx->bytes_per_word = bytes_per_word;
860 
861         return 0;
862 }
863 
864 static int spi_imx_setupxfer(struct spi_device *spi,
865                                  struct spi_transfer *t)
866 {
867         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
868         struct spi_imx_config config;
869         int ret;
870 
871         config.bpw = t ? t->bits_per_word : spi->bits_per_word;
872         config.speed_hz  = t ? t->speed_hz : spi->max_speed_hz;
873 
874         if (!config.speed_hz)
875                 config.speed_hz = spi->max_speed_hz;
876         if (!config.bpw)
877                 config.bpw = spi->bits_per_word;
878 
879         /* Initialize the functions for transfer */
880         if (config.bpw <= 8) {
881                 spi_imx->rx = spi_imx_buf_rx_u8;
882                 spi_imx->tx = spi_imx_buf_tx_u8;
883         } else if (config.bpw <= 16) {
884                 spi_imx->rx = spi_imx_buf_rx_u16;
885                 spi_imx->tx = spi_imx_buf_tx_u16;
886         } else {
887                 spi_imx->rx = spi_imx_buf_rx_u32;
888                 spi_imx->tx = spi_imx_buf_tx_u32;
889         }
890 
891         if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
892                 spi_imx->usedma = 1;
893         else
894                 spi_imx->usedma = 0;
895 
896         if (spi_imx->usedma) {
897                 ret = spi_imx_dma_configure(spi->master,
898                                             spi_imx_bytes_per_word(config.bpw));
899                 if (ret)
900                         return ret;
901         }
902 
903         spi_imx->devtype_data->config(spi, &config);
904 
905         return 0;
906 }
907 
908 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
909 {
910         struct spi_master *master = spi_imx->bitbang.master;
911 
912         if (master->dma_rx) {
913                 dma_release_channel(master->dma_rx);
914                 master->dma_rx = NULL;
915         }
916 
917         if (master->dma_tx) {
918                 dma_release_channel(master->dma_tx);
919                 master->dma_tx = NULL;
920         }
921 }
922 
923 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
924                              struct spi_master *master)
925 {
926         int ret;
927 
928         /* use pio mode for i.mx6dl chip TKT238285 */
929         if (of_machine_is_compatible("fsl,imx6dl"))
930                 return 0;
931 
932         spi_imx->wml = spi_imx_get_fifosize(spi_imx) / 2;
933 
934         /* Prepare for TX DMA: */
935         master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
936         if (IS_ERR(master->dma_tx)) {
937                 ret = PTR_ERR(master->dma_tx);
938                 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
939                 master->dma_tx = NULL;
940                 goto err;
941         }
942 
943         /* Prepare for RX : */
944         master->dma_rx = dma_request_slave_channel_reason(dev, "rx");
945         if (IS_ERR(master->dma_rx)) {
946                 ret = PTR_ERR(master->dma_rx);
947                 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
948                 master->dma_rx = NULL;
949                 goto err;
950         }
951 
952         spi_imx_dma_configure(master, 1);
953 
954         init_completion(&spi_imx->dma_rx_completion);
955         init_completion(&spi_imx->dma_tx_completion);
956         master->can_dma = spi_imx_can_dma;
957         master->max_dma_len = MAX_SDMA_BD_BYTES;
958         spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
959                                          SPI_MASTER_MUST_TX;
960 
961         return 0;
962 err:
963         spi_imx_sdma_exit(spi_imx);
964         return ret;
965 }
966 
967 static void spi_imx_dma_rx_callback(void *cookie)
968 {
969         struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
970 
971         complete(&spi_imx->dma_rx_completion);
972 }
973 
974 static void spi_imx_dma_tx_callback(void *cookie)
975 {
976         struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
977 
978         complete(&spi_imx->dma_tx_completion);
979 }
980 
981 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
982 {
983         unsigned long timeout = 0;
984 
985         /* Time with actual data transfer and CS change delay related to HW */
986         timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
987 
988         /* Add extra second for scheduler related activities */
989         timeout += 1;
990 
991         /* Double calculated timeout */
992         return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
993 }
994 
995 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
996                                 struct spi_transfer *transfer)
997 {
998         struct dma_async_tx_descriptor *desc_tx, *desc_rx;
999         unsigned long transfer_timeout;
1000         unsigned long timeout;
1001         struct spi_master *master = spi_imx->bitbang.master;
1002         struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1003 
1004         /*
1005          * The TX DMA setup starts the transfer, so make sure RX is configured
1006          * before TX.
1007          */
1008         desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
1009                                 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1010                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1011         if (!desc_rx)
1012                 return -EINVAL;
1013 
1014         desc_rx->callback = spi_imx_dma_rx_callback;
1015         desc_rx->callback_param = (void *)spi_imx;
1016         dmaengine_submit(desc_rx);
1017         reinit_completion(&spi_imx->dma_rx_completion);
1018         dma_async_issue_pending(master->dma_rx);
1019 
1020         desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
1021                                 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1022                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1023         if (!desc_tx) {
1024                 dmaengine_terminate_all(master->dma_tx);
1025                 return -EINVAL;
1026         }
1027 
1028         desc_tx->callback = spi_imx_dma_tx_callback;
1029         desc_tx->callback_param = (void *)spi_imx;
1030         dmaengine_submit(desc_tx);
1031         reinit_completion(&spi_imx->dma_tx_completion);
1032         dma_async_issue_pending(master->dma_tx);
1033 
1034         transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1035 
1036         /* Wait SDMA to finish the data transfer.*/
1037         timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1038                                                 transfer_timeout);
1039         if (!timeout) {
1040                 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1041                 dmaengine_terminate_all(master->dma_tx);
1042                 dmaengine_terminate_all(master->dma_rx);
1043                 return -ETIMEDOUT;
1044         }
1045 
1046         timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1047                                               transfer_timeout);
1048         if (!timeout) {
1049                 dev_err(&master->dev, "I/O Error in DMA RX\n");
1050                 spi_imx->devtype_data->reset(spi_imx);
1051                 dmaengine_terminate_all(master->dma_rx);
1052                 return -ETIMEDOUT;
1053         }
1054 
1055         return transfer->len;
1056 }
1057 
1058 static int spi_imx_pio_transfer(struct spi_device *spi,
1059                                 struct spi_transfer *transfer)
1060 {
1061         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1062         unsigned long transfer_timeout;
1063         unsigned long timeout;
1064 
1065         spi_imx->tx_buf = transfer->tx_buf;
1066         spi_imx->rx_buf = transfer->rx_buf;
1067         spi_imx->count = transfer->len;
1068         spi_imx->txfifo = 0;
1069 
1070         reinit_completion(&spi_imx->xfer_done);
1071 
1072         spi_imx_push(spi_imx);
1073 
1074         spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1075 
1076         transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1077 
1078         timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
1079                                               transfer_timeout);
1080         if (!timeout) {
1081                 dev_err(&spi->dev, "I/O Error in PIO\n");
1082                 spi_imx->devtype_data->reset(spi_imx);
1083                 return -ETIMEDOUT;
1084         }
1085 
1086         return transfer->len;
1087 }
1088 
1089 static int spi_imx_transfer(struct spi_device *spi,
1090                                 struct spi_transfer *transfer)
1091 {
1092         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1093 
1094         if (spi_imx->usedma)
1095                 return spi_imx_dma_transfer(spi_imx, transfer);
1096         else
1097                 return spi_imx_pio_transfer(spi, transfer);
1098 }
1099 
1100 static int spi_imx_setup(struct spi_device *spi)
1101 {
1102         dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1103                  spi->mode, spi->bits_per_word, spi->max_speed_hz);
1104 
1105         if (gpio_is_valid(spi->cs_gpio))
1106                 gpio_direction_output(spi->cs_gpio,
1107                                       spi->mode & SPI_CS_HIGH ? 0 : 1);
1108 
1109         spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
1110 
1111         return 0;
1112 }
1113 
1114 static void spi_imx_cleanup(struct spi_device *spi)
1115 {
1116 }
1117 
1118 static int
1119 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1120 {
1121         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1122         int ret;
1123 
1124         ret = clk_enable(spi_imx->clk_per);
1125         if (ret)
1126                 return ret;
1127 
1128         ret = clk_enable(spi_imx->clk_ipg);
1129         if (ret) {
1130                 clk_disable(spi_imx->clk_per);
1131                 return ret;
1132         }
1133 
1134         return 0;
1135 }
1136 
1137 static int
1138 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1139 {
1140         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1141 
1142         clk_disable(spi_imx->clk_ipg);
1143         clk_disable(spi_imx->clk_per);
1144         return 0;
1145 }
1146 
1147 static int spi_imx_probe(struct platform_device *pdev)
1148 {
1149         struct device_node *np = pdev->dev.of_node;
1150         const struct of_device_id *of_id =
1151                         of_match_device(spi_imx_dt_ids, &pdev->dev);
1152         struct spi_imx_master *mxc_platform_info =
1153                         dev_get_platdata(&pdev->dev);
1154         struct spi_master *master;
1155         struct spi_imx_data *spi_imx;
1156         struct resource *res;
1157         int i, ret, irq;
1158 
1159         if (!np && !mxc_platform_info) {
1160                 dev_err(&pdev->dev, "can't get the platform data\n");
1161                 return -EINVAL;
1162         }
1163 
1164         master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data));
1165         if (!master)
1166                 return -ENOMEM;
1167 
1168         platform_set_drvdata(pdev, master);
1169 
1170         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1171         master->bus_num = np ? -1 : pdev->id;
1172 
1173         spi_imx = spi_master_get_devdata(master);
1174         spi_imx->bitbang.master = master;
1175         spi_imx->dev = &pdev->dev;
1176 
1177         spi_imx->devtype_data = of_id ? of_id->data :
1178                 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
1179 
1180         if (mxc_platform_info) {
1181                 master->num_chipselect = mxc_platform_info->num_chipselect;
1182                 master->cs_gpios = devm_kzalloc(&master->dev,
1183                         sizeof(int) * master->num_chipselect, GFP_KERNEL);
1184                 if (!master->cs_gpios)
1185                         return -ENOMEM;
1186 
1187                 for (i = 0; i < master->num_chipselect; i++)
1188                         master->cs_gpios[i] = mxc_platform_info->chipselect[i];
1189         }
1190 
1191         spi_imx->bitbang.chipselect = spi_imx_chipselect;
1192         spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1193         spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1194         spi_imx->bitbang.master->setup = spi_imx_setup;
1195         spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1196         spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1197         spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1198         spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1199         if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx))
1200                 spi_imx->bitbang.master->mode_bits |= SPI_LOOP;
1201 
1202         init_completion(&spi_imx->xfer_done);
1203 
1204         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1205         spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1206         if (IS_ERR(spi_imx->base)) {
1207                 ret = PTR_ERR(spi_imx->base);
1208                 goto out_master_put;
1209         }
1210         spi_imx->base_phys = res->start;
1211 
1212         irq = platform_get_irq(pdev, 0);
1213         if (irq < 0) {
1214                 ret = irq;
1215                 goto out_master_put;
1216         }
1217 
1218         ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1219                                dev_name(&pdev->dev), spi_imx);
1220         if (ret) {
1221                 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1222                 goto out_master_put;
1223         }
1224 
1225         spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1226         if (IS_ERR(spi_imx->clk_ipg)) {
1227                 ret = PTR_ERR(spi_imx->clk_ipg);
1228                 goto out_master_put;
1229         }
1230 
1231         spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1232         if (IS_ERR(spi_imx->clk_per)) {
1233                 ret = PTR_ERR(spi_imx->clk_per);
1234                 goto out_master_put;
1235         }
1236 
1237         ret = clk_prepare_enable(spi_imx->clk_per);
1238         if (ret)
1239                 goto out_master_put;
1240 
1241         ret = clk_prepare_enable(spi_imx->clk_ipg);
1242         if (ret)
1243                 goto out_put_per;
1244 
1245         spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1246         /*
1247          * Only validated on i.mx6 now, can remove the constrain if validated on
1248          * other chips.
1249          */
1250         if (is_imx51_ecspi(spi_imx)) {
1251                 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
1252                 if (ret == -EPROBE_DEFER)
1253                         goto out_clk_put;
1254 
1255                 if (ret < 0)
1256                         dev_err(&pdev->dev, "dma setup error %d, use pio\n",
1257                                 ret);
1258         }
1259 
1260         spi_imx->devtype_data->reset(spi_imx);
1261 
1262         spi_imx->devtype_data->intctrl(spi_imx, 0);
1263 
1264         master->dev.of_node = pdev->dev.of_node;
1265         ret = spi_bitbang_start(&spi_imx->bitbang);
1266         if (ret) {
1267                 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
1268                 goto out_clk_put;
1269         }
1270 
1271         if (!master->cs_gpios) {
1272                 dev_err(&pdev->dev, "No CS GPIOs available\n");
1273                 ret = -EINVAL;
1274                 goto out_clk_put;
1275         }
1276 
1277         for (i = 0; i < master->num_chipselect; i++) {
1278                 if (!gpio_is_valid(master->cs_gpios[i]))
1279                         continue;
1280 
1281                 ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i],
1282                                         DRIVER_NAME);
1283                 if (ret) {
1284                         dev_err(&pdev->dev, "Can't get CS GPIO %i\n",
1285                                 master->cs_gpios[i]);
1286                         goto out_clk_put;
1287                 }
1288         }
1289 
1290         dev_info(&pdev->dev, "probed\n");
1291 
1292         clk_disable(spi_imx->clk_ipg);
1293         clk_disable(spi_imx->clk_per);
1294         return ret;
1295 
1296 out_clk_put:
1297         clk_disable_unprepare(spi_imx->clk_ipg);
1298 out_put_per:
1299         clk_disable_unprepare(spi_imx->clk_per);
1300 out_master_put:
1301         spi_master_put(master);
1302 
1303         return ret;
1304 }
1305 
1306 static int spi_imx_remove(struct platform_device *pdev)
1307 {
1308         struct spi_master *master = platform_get_drvdata(pdev);
1309         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1310 
1311         spi_bitbang_stop(&spi_imx->bitbang);
1312 
1313         writel(0, spi_imx->base + MXC_CSPICTRL);
1314         clk_unprepare(spi_imx->clk_ipg);
1315         clk_unprepare(spi_imx->clk_per);
1316         spi_imx_sdma_exit(spi_imx);
1317         spi_master_put(master);
1318 
1319         return 0;
1320 }
1321 
1322 static struct platform_driver spi_imx_driver = {
1323         .driver = {
1324                    .name = DRIVER_NAME,
1325                    .of_match_table = spi_imx_dt_ids,
1326                    },
1327         .id_table = spi_imx_devtype,
1328         .probe = spi_imx_probe,
1329         .remove = spi_imx_remove,
1330 };
1331 module_platform_driver(spi_imx_driver);
1332 
1333 MODULE_DESCRIPTION("SPI Master Controller driver");
1334 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1335 MODULE_LICENSE("GPL");
1336 MODULE_ALIAS("platform:" DRIVER_NAME);
1337 

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