Version:  2.0.40 2.2.26 2.4.37 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8

Linux/drivers/spi/spi-imx.c

  1 /*
  2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  3  * Copyright (C) 2008 Juergen Beisert
  4  *
  5  * This program is free software; you can redistribute it and/or
  6  * modify it under the terms of the GNU General Public License
  7  * as published by the Free Software Foundation; either version 2
  8  * of the License, or (at your option) any later version.
  9  * This program is distributed in the hope that it will be useful,
 10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 12  * GNU General Public License for more details.
 13  *
 14  * You should have received a copy of the GNU General Public License
 15  * along with this program; if not, write to the
 16  * Free Software Foundation
 17  * 51 Franklin Street, Fifth Floor
 18  * Boston, MA  02110-1301, USA.
 19  */
 20 
 21 #include <linux/clk.h>
 22 #include <linux/completion.h>
 23 #include <linux/delay.h>
 24 #include <linux/dmaengine.h>
 25 #include <linux/dma-mapping.h>
 26 #include <linux/err.h>
 27 #include <linux/gpio.h>
 28 #include <linux/interrupt.h>
 29 #include <linux/io.h>
 30 #include <linux/irq.h>
 31 #include <linux/kernel.h>
 32 #include <linux/module.h>
 33 #include <linux/platform_device.h>
 34 #include <linux/slab.h>
 35 #include <linux/spi/spi.h>
 36 #include <linux/spi/spi_bitbang.h>
 37 #include <linux/types.h>
 38 #include <linux/of.h>
 39 #include <linux/of_device.h>
 40 #include <linux/of_gpio.h>
 41 
 42 #include <linux/platform_data/dma-imx.h>
 43 #include <linux/platform_data/spi-imx.h>
 44 
 45 #define DRIVER_NAME "spi_imx"
 46 
 47 #define MXC_CSPIRXDATA          0x00
 48 #define MXC_CSPITXDATA          0x04
 49 #define MXC_CSPICTRL            0x08
 50 #define MXC_CSPIINT             0x0c
 51 #define MXC_RESET               0x1c
 52 
 53 /* generic defines to abstract from the different register layouts */
 54 #define MXC_INT_RR      (1 << 0) /* Receive data ready interrupt */
 55 #define MXC_INT_TE      (1 << 1) /* Transmit FIFO empty interrupt */
 56 
 57 /* The maximum  bytes that a sdma BD can transfer.*/
 58 #define MAX_SDMA_BD_BYTES  (1 << 15)
 59 struct spi_imx_config {
 60         unsigned int speed_hz;
 61         unsigned int bpw;
 62 };
 63 
 64 enum spi_imx_devtype {
 65         IMX1_CSPI,
 66         IMX21_CSPI,
 67         IMX27_CSPI,
 68         IMX31_CSPI,
 69         IMX35_CSPI,     /* CSPI on all i.mx except above */
 70         IMX51_ECSPI,    /* ECSPI on i.mx51 and later */
 71 };
 72 
 73 struct spi_imx_data;
 74 
 75 struct spi_imx_devtype_data {
 76         void (*intctrl)(struct spi_imx_data *, int);
 77         int (*config)(struct spi_device *, struct spi_imx_config *);
 78         void (*trigger)(struct spi_imx_data *);
 79         int (*rx_available)(struct spi_imx_data *);
 80         void (*reset)(struct spi_imx_data *);
 81         enum spi_imx_devtype devtype;
 82 };
 83 
 84 struct spi_imx_data {
 85         struct spi_bitbang bitbang;
 86         struct device *dev;
 87 
 88         struct completion xfer_done;
 89         void __iomem *base;
 90         unsigned long base_phys;
 91 
 92         struct clk *clk_per;
 93         struct clk *clk_ipg;
 94         unsigned long spi_clk;
 95         unsigned int spi_bus_clk;
 96 
 97         unsigned int bytes_per_word;
 98 
 99         unsigned int count;
100         void (*tx)(struct spi_imx_data *);
101         void (*rx)(struct spi_imx_data *);
102         void *rx_buf;
103         const void *tx_buf;
104         unsigned int txfifo; /* number of words pushed in tx FIFO */
105 
106         /* DMA */
107         bool usedma;
108         u32 wml;
109         struct completion dma_rx_completion;
110         struct completion dma_tx_completion;
111 
112         const struct spi_imx_devtype_data *devtype_data;
113 };
114 
115 static inline int is_imx27_cspi(struct spi_imx_data *d)
116 {
117         return d->devtype_data->devtype == IMX27_CSPI;
118 }
119 
120 static inline int is_imx35_cspi(struct spi_imx_data *d)
121 {
122         return d->devtype_data->devtype == IMX35_CSPI;
123 }
124 
125 static inline int is_imx51_ecspi(struct spi_imx_data *d)
126 {
127         return d->devtype_data->devtype == IMX51_ECSPI;
128 }
129 
130 static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d)
131 {
132         return is_imx51_ecspi(d) ? 64 : 8;
133 }
134 
135 #define MXC_SPI_BUF_RX(type)                                            \
136 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx)         \
137 {                                                                       \
138         unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);       \
139                                                                         \
140         if (spi_imx->rx_buf) {                                          \
141                 *(type *)spi_imx->rx_buf = val;                         \
142                 spi_imx->rx_buf += sizeof(type);                        \
143         }                                                               \
144 }
145 
146 #define MXC_SPI_BUF_TX(type)                                            \
147 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx)         \
148 {                                                                       \
149         type val = 0;                                                   \
150                                                                         \
151         if (spi_imx->tx_buf) {                                          \
152                 val = *(type *)spi_imx->tx_buf;                         \
153                 spi_imx->tx_buf += sizeof(type);                        \
154         }                                                               \
155                                                                         \
156         spi_imx->count -= sizeof(type);                                 \
157                                                                         \
158         writel(val, spi_imx->base + MXC_CSPITXDATA);                    \
159 }
160 
161 MXC_SPI_BUF_RX(u8)
162 MXC_SPI_BUF_TX(u8)
163 MXC_SPI_BUF_RX(u16)
164 MXC_SPI_BUF_TX(u16)
165 MXC_SPI_BUF_RX(u32)
166 MXC_SPI_BUF_TX(u32)
167 
168 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
169  * (which is currently not the case in this driver)
170  */
171 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
172         256, 384, 512, 768, 1024};
173 
174 /* MX21, MX27 */
175 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
176                 unsigned int fspi, unsigned int max)
177 {
178         int i;
179 
180         for (i = 2; i < max; i++)
181                 if (fspi * mxc_clkdivs[i] >= fin)
182                         return i;
183 
184         return max;
185 }
186 
187 /* MX1, MX31, MX35, MX51 CSPI */
188 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
189                 unsigned int fspi)
190 {
191         int i, div = 4;
192 
193         for (i = 0; i < 7; i++) {
194                 if (fspi * div >= fin)
195                         return i;
196                 div <<= 1;
197         }
198 
199         return 7;
200 }
201 
202 static int spi_imx_bytes_per_word(const int bpw)
203 {
204         return DIV_ROUND_UP(bpw, BITS_PER_BYTE);
205 }
206 
207 static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
208                          struct spi_transfer *transfer)
209 {
210         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
211         unsigned int bpw;
212 
213         if (!master->dma_rx)
214                 return false;
215 
216         if (!transfer)
217                 return false;
218 
219         bpw = transfer->bits_per_word;
220         if (!bpw)
221                 bpw = spi->bits_per_word;
222 
223         bpw = spi_imx_bytes_per_word(bpw);
224 
225         if (bpw != 1 && bpw != 2 && bpw != 4)
226                 return false;
227 
228         if (transfer->len < spi_imx->wml * bpw)
229                 return false;
230 
231         if (transfer->len % (spi_imx->wml * bpw))
232                 return false;
233 
234         return true;
235 }
236 
237 #define MX51_ECSPI_CTRL         0x08
238 #define MX51_ECSPI_CTRL_ENABLE          (1 <<  0)
239 #define MX51_ECSPI_CTRL_XCH             (1 <<  2)
240 #define MX51_ECSPI_CTRL_SMC             (1 << 3)
241 #define MX51_ECSPI_CTRL_MODE_MASK       (0xf << 4)
242 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET  8
243 #define MX51_ECSPI_CTRL_PREDIV_OFFSET   12
244 #define MX51_ECSPI_CTRL_CS(cs)          ((cs) << 18)
245 #define MX51_ECSPI_CTRL_BL_OFFSET       20
246 
247 #define MX51_ECSPI_CONFIG       0x0c
248 #define MX51_ECSPI_CONFIG_SCLKPHA(cs)   (1 << ((cs) +  0))
249 #define MX51_ECSPI_CONFIG_SCLKPOL(cs)   (1 << ((cs) +  4))
250 #define MX51_ECSPI_CONFIG_SBBCTRL(cs)   (1 << ((cs) +  8))
251 #define MX51_ECSPI_CONFIG_SSBPOL(cs)    (1 << ((cs) + 12))
252 #define MX51_ECSPI_CONFIG_SCLKCTL(cs)   (1 << ((cs) + 20))
253 
254 #define MX51_ECSPI_INT          0x10
255 #define MX51_ECSPI_INT_TEEN             (1 <<  0)
256 #define MX51_ECSPI_INT_RREN             (1 <<  3)
257 
258 #define MX51_ECSPI_DMA      0x14
259 #define MX51_ECSPI_DMA_TX_WML(wml)      ((wml) & 0x3f)
260 #define MX51_ECSPI_DMA_RX_WML(wml)      (((wml) & 0x3f) << 16)
261 #define MX51_ECSPI_DMA_RXT_WML(wml)     (((wml) & 0x3f) << 24)
262 
263 #define MX51_ECSPI_DMA_TEDEN            (1 << 7)
264 #define MX51_ECSPI_DMA_RXDEN            (1 << 23)
265 #define MX51_ECSPI_DMA_RXTDEN           (1 << 31)
266 
267 #define MX51_ECSPI_STAT         0x18
268 #define MX51_ECSPI_STAT_RR              (1 <<  3)
269 
270 #define MX51_ECSPI_TESTREG      0x20
271 #define MX51_ECSPI_TESTREG_LBC  BIT(31)
272 
273 /* MX51 eCSPI */
274 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
275                                       unsigned int fspi, unsigned int *fres)
276 {
277         /*
278          * there are two 4-bit dividers, the pre-divider divides by
279          * $pre, the post-divider by 2^$post
280          */
281         unsigned int pre, post;
282         unsigned int fin = spi_imx->spi_clk;
283 
284         if (unlikely(fspi > fin))
285                 return 0;
286 
287         post = fls(fin) - fls(fspi);
288         if (fin > fspi << post)
289                 post++;
290 
291         /* now we have: (fin <= fspi << post) with post being minimal */
292 
293         post = max(4U, post) - 4;
294         if (unlikely(post > 0xf)) {
295                 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
296                                 fspi, fin);
297                 return 0xff;
298         }
299 
300         pre = DIV_ROUND_UP(fin, fspi << post) - 1;
301 
302         dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
303                         __func__, fin, fspi, post, pre);
304 
305         /* Resulting frequency for the SCLK line. */
306         *fres = (fin / (pre + 1)) >> post;
307 
308         return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
309                 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
310 }
311 
312 static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
313 {
314         unsigned val = 0;
315 
316         if (enable & MXC_INT_TE)
317                 val |= MX51_ECSPI_INT_TEEN;
318 
319         if (enable & MXC_INT_RR)
320                 val |= MX51_ECSPI_INT_RREN;
321 
322         writel(val, spi_imx->base + MX51_ECSPI_INT);
323 }
324 
325 static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
326 {
327         u32 reg;
328 
329         reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
330         reg |= MX51_ECSPI_CTRL_XCH;
331         writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
332 }
333 
334 static int mx51_ecspi_config(struct spi_device *spi,
335                              struct spi_imx_config *config)
336 {
337         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
338         u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
339         u32 clk = config->speed_hz, delay, reg;
340         u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
341 
342         /*
343          * The hardware seems to have a race condition when changing modes. The
344          * current assumption is that the selection of the channel arrives
345          * earlier in the hardware than the mode bits when they are written at
346          * the same time.
347          * So set master mode for all channels as we do not support slave mode.
348          */
349         ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
350 
351         /* set clock speed */
352         ctrl |= mx51_ecspi_clkdiv(spi_imx, config->speed_hz, &clk);
353         spi_imx->spi_bus_clk = clk;
354 
355         /* set chip select to use */
356         ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
357 
358         ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
359 
360         cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
361 
362         if (spi->mode & SPI_CPHA)
363                 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
364         else
365                 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
366 
367         if (spi->mode & SPI_CPOL) {
368                 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
369                 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
370         } else {
371                 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
372                 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
373         }
374         if (spi->mode & SPI_CS_HIGH)
375                 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
376         else
377                 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
378 
379         if (spi_imx->usedma)
380                 ctrl |= MX51_ECSPI_CTRL_SMC;
381 
382         /* CTRL register always go first to bring out controller from reset */
383         writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
384 
385         reg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
386         if (spi->mode & SPI_LOOP)
387                 reg |= MX51_ECSPI_TESTREG_LBC;
388         else
389                 reg &= ~MX51_ECSPI_TESTREG_LBC;
390         writel(reg, spi_imx->base + MX51_ECSPI_TESTREG);
391 
392         writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
393 
394         /*
395          * Wait until the changes in the configuration register CONFIGREG
396          * propagate into the hardware. It takes exactly one tick of the
397          * SCLK clock, but we will wait two SCLK clock just to be sure. The
398          * effect of the delay it takes for the hardware to apply changes
399          * is noticable if the SCLK clock run very slow. In such a case, if
400          * the polarity of SCLK should be inverted, the GPIO ChipSelect might
401          * be asserted before the SCLK polarity changes, which would disrupt
402          * the SPI communication as the device on the other end would consider
403          * the change of SCLK polarity as a clock tick already.
404          */
405         delay = (2 * 1000000) / clk;
406         if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
407                 udelay(delay);
408         else                    /* SCLK is _very_ slow */
409                 usleep_range(delay, delay + 10);
410 
411         /*
412          * Configure the DMA register: setup the watermark
413          * and enable DMA request.
414          */
415 
416         writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml) |
417                 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
418                 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
419                 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
420                 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
421 
422         return 0;
423 }
424 
425 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
426 {
427         return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
428 }
429 
430 static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
431 {
432         /* drain receive buffer */
433         while (mx51_ecspi_rx_available(spi_imx))
434                 readl(spi_imx->base + MXC_CSPIRXDATA);
435 }
436 
437 #define MX31_INTREG_TEEN        (1 << 0)
438 #define MX31_INTREG_RREN        (1 << 3)
439 
440 #define MX31_CSPICTRL_ENABLE    (1 << 0)
441 #define MX31_CSPICTRL_MASTER    (1 << 1)
442 #define MX31_CSPICTRL_XCH       (1 << 2)
443 #define MX31_CSPICTRL_POL       (1 << 4)
444 #define MX31_CSPICTRL_PHA       (1 << 5)
445 #define MX31_CSPICTRL_SSCTL     (1 << 6)
446 #define MX31_CSPICTRL_SSPOL     (1 << 7)
447 #define MX31_CSPICTRL_BC_SHIFT  8
448 #define MX35_CSPICTRL_BL_SHIFT  20
449 #define MX31_CSPICTRL_CS_SHIFT  24
450 #define MX35_CSPICTRL_CS_SHIFT  12
451 #define MX31_CSPICTRL_DR_SHIFT  16
452 
453 #define MX31_CSPISTATUS         0x14
454 #define MX31_STATUS_RR          (1 << 3)
455 
456 /* These functions also work for the i.MX35, but be aware that
457  * the i.MX35 has a slightly different register layout for bits
458  * we do not use here.
459  */
460 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
461 {
462         unsigned int val = 0;
463 
464         if (enable & MXC_INT_TE)
465                 val |= MX31_INTREG_TEEN;
466         if (enable & MXC_INT_RR)
467                 val |= MX31_INTREG_RREN;
468 
469         writel(val, spi_imx->base + MXC_CSPIINT);
470 }
471 
472 static void mx31_trigger(struct spi_imx_data *spi_imx)
473 {
474         unsigned int reg;
475 
476         reg = readl(spi_imx->base + MXC_CSPICTRL);
477         reg |= MX31_CSPICTRL_XCH;
478         writel(reg, spi_imx->base + MXC_CSPICTRL);
479 }
480 
481 static int mx31_config(struct spi_device *spi, struct spi_imx_config *config)
482 {
483         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
484         unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
485 
486         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
487                 MX31_CSPICTRL_DR_SHIFT;
488 
489         if (is_imx35_cspi(spi_imx)) {
490                 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
491                 reg |= MX31_CSPICTRL_SSCTL;
492         } else {
493                 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
494         }
495 
496         if (spi->mode & SPI_CPHA)
497                 reg |= MX31_CSPICTRL_PHA;
498         if (spi->mode & SPI_CPOL)
499                 reg |= MX31_CSPICTRL_POL;
500         if (spi->mode & SPI_CS_HIGH)
501                 reg |= MX31_CSPICTRL_SSPOL;
502         if (spi->cs_gpio < 0)
503                 reg |= (spi->cs_gpio + 32) <<
504                         (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
505                                                   MX31_CSPICTRL_CS_SHIFT);
506 
507         writel(reg, spi_imx->base + MXC_CSPICTRL);
508 
509         return 0;
510 }
511 
512 static int mx31_rx_available(struct spi_imx_data *spi_imx)
513 {
514         return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
515 }
516 
517 static void mx31_reset(struct spi_imx_data *spi_imx)
518 {
519         /* drain receive buffer */
520         while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
521                 readl(spi_imx->base + MXC_CSPIRXDATA);
522 }
523 
524 #define MX21_INTREG_RR          (1 << 4)
525 #define MX21_INTREG_TEEN        (1 << 9)
526 #define MX21_INTREG_RREN        (1 << 13)
527 
528 #define MX21_CSPICTRL_POL       (1 << 5)
529 #define MX21_CSPICTRL_PHA       (1 << 6)
530 #define MX21_CSPICTRL_SSPOL     (1 << 8)
531 #define MX21_CSPICTRL_XCH       (1 << 9)
532 #define MX21_CSPICTRL_ENABLE    (1 << 10)
533 #define MX21_CSPICTRL_MASTER    (1 << 11)
534 #define MX21_CSPICTRL_DR_SHIFT  14
535 #define MX21_CSPICTRL_CS_SHIFT  19
536 
537 static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
538 {
539         unsigned int val = 0;
540 
541         if (enable & MXC_INT_TE)
542                 val |= MX21_INTREG_TEEN;
543         if (enable & MXC_INT_RR)
544                 val |= MX21_INTREG_RREN;
545 
546         writel(val, spi_imx->base + MXC_CSPIINT);
547 }
548 
549 static void mx21_trigger(struct spi_imx_data *spi_imx)
550 {
551         unsigned int reg;
552 
553         reg = readl(spi_imx->base + MXC_CSPICTRL);
554         reg |= MX21_CSPICTRL_XCH;
555         writel(reg, spi_imx->base + MXC_CSPICTRL);
556 }
557 
558 static int mx21_config(struct spi_device *spi, struct spi_imx_config *config)
559 {
560         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
561         unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
562         unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
563 
564         reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) <<
565                 MX21_CSPICTRL_DR_SHIFT;
566         reg |= config->bpw - 1;
567 
568         if (spi->mode & SPI_CPHA)
569                 reg |= MX21_CSPICTRL_PHA;
570         if (spi->mode & SPI_CPOL)
571                 reg |= MX21_CSPICTRL_POL;
572         if (spi->mode & SPI_CS_HIGH)
573                 reg |= MX21_CSPICTRL_SSPOL;
574         if (spi->cs_gpio < 0)
575                 reg |= (spi->cs_gpio + 32) << MX21_CSPICTRL_CS_SHIFT;
576 
577         writel(reg, spi_imx->base + MXC_CSPICTRL);
578 
579         return 0;
580 }
581 
582 static int mx21_rx_available(struct spi_imx_data *spi_imx)
583 {
584         return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
585 }
586 
587 static void mx21_reset(struct spi_imx_data *spi_imx)
588 {
589         writel(1, spi_imx->base + MXC_RESET);
590 }
591 
592 #define MX1_INTREG_RR           (1 << 3)
593 #define MX1_INTREG_TEEN         (1 << 8)
594 #define MX1_INTREG_RREN         (1 << 11)
595 
596 #define MX1_CSPICTRL_POL        (1 << 4)
597 #define MX1_CSPICTRL_PHA        (1 << 5)
598 #define MX1_CSPICTRL_XCH        (1 << 8)
599 #define MX1_CSPICTRL_ENABLE     (1 << 9)
600 #define MX1_CSPICTRL_MASTER     (1 << 10)
601 #define MX1_CSPICTRL_DR_SHIFT   13
602 
603 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
604 {
605         unsigned int val = 0;
606 
607         if (enable & MXC_INT_TE)
608                 val |= MX1_INTREG_TEEN;
609         if (enable & MXC_INT_RR)
610                 val |= MX1_INTREG_RREN;
611 
612         writel(val, spi_imx->base + MXC_CSPIINT);
613 }
614 
615 static void mx1_trigger(struct spi_imx_data *spi_imx)
616 {
617         unsigned int reg;
618 
619         reg = readl(spi_imx->base + MXC_CSPICTRL);
620         reg |= MX1_CSPICTRL_XCH;
621         writel(reg, spi_imx->base + MXC_CSPICTRL);
622 }
623 
624 static int mx1_config(struct spi_device *spi, struct spi_imx_config *config)
625 {
626         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
627         unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
628 
629         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
630                 MX1_CSPICTRL_DR_SHIFT;
631         reg |= config->bpw - 1;
632 
633         if (spi->mode & SPI_CPHA)
634                 reg |= MX1_CSPICTRL_PHA;
635         if (spi->mode & SPI_CPOL)
636                 reg |= MX1_CSPICTRL_POL;
637 
638         writel(reg, spi_imx->base + MXC_CSPICTRL);
639 
640         return 0;
641 }
642 
643 static int mx1_rx_available(struct spi_imx_data *spi_imx)
644 {
645         return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
646 }
647 
648 static void mx1_reset(struct spi_imx_data *spi_imx)
649 {
650         writel(1, spi_imx->base + MXC_RESET);
651 }
652 
653 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
654         .intctrl = mx1_intctrl,
655         .config = mx1_config,
656         .trigger = mx1_trigger,
657         .rx_available = mx1_rx_available,
658         .reset = mx1_reset,
659         .devtype = IMX1_CSPI,
660 };
661 
662 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
663         .intctrl = mx21_intctrl,
664         .config = mx21_config,
665         .trigger = mx21_trigger,
666         .rx_available = mx21_rx_available,
667         .reset = mx21_reset,
668         .devtype = IMX21_CSPI,
669 };
670 
671 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
672         /* i.mx27 cspi shares the functions with i.mx21 one */
673         .intctrl = mx21_intctrl,
674         .config = mx21_config,
675         .trigger = mx21_trigger,
676         .rx_available = mx21_rx_available,
677         .reset = mx21_reset,
678         .devtype = IMX27_CSPI,
679 };
680 
681 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
682         .intctrl = mx31_intctrl,
683         .config = mx31_config,
684         .trigger = mx31_trigger,
685         .rx_available = mx31_rx_available,
686         .reset = mx31_reset,
687         .devtype = IMX31_CSPI,
688 };
689 
690 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
691         /* i.mx35 and later cspi shares the functions with i.mx31 one */
692         .intctrl = mx31_intctrl,
693         .config = mx31_config,
694         .trigger = mx31_trigger,
695         .rx_available = mx31_rx_available,
696         .reset = mx31_reset,
697         .devtype = IMX35_CSPI,
698 };
699 
700 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
701         .intctrl = mx51_ecspi_intctrl,
702         .config = mx51_ecspi_config,
703         .trigger = mx51_ecspi_trigger,
704         .rx_available = mx51_ecspi_rx_available,
705         .reset = mx51_ecspi_reset,
706         .devtype = IMX51_ECSPI,
707 };
708 
709 static const struct platform_device_id spi_imx_devtype[] = {
710         {
711                 .name = "imx1-cspi",
712                 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
713         }, {
714                 .name = "imx21-cspi",
715                 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
716         }, {
717                 .name = "imx27-cspi",
718                 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
719         }, {
720                 .name = "imx31-cspi",
721                 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
722         }, {
723                 .name = "imx35-cspi",
724                 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
725         }, {
726                 .name = "imx51-ecspi",
727                 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
728         }, {
729                 /* sentinel */
730         }
731 };
732 
733 static const struct of_device_id spi_imx_dt_ids[] = {
734         { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
735         { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
736         { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
737         { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
738         { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
739         { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
740         { /* sentinel */ }
741 };
742 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
743 
744 static void spi_imx_chipselect(struct spi_device *spi, int is_active)
745 {
746         int active = is_active != BITBANG_CS_INACTIVE;
747         int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
748 
749         if (!gpio_is_valid(spi->cs_gpio))
750                 return;
751 
752         gpio_set_value(spi->cs_gpio, dev_is_lowactive ^ active);
753 }
754 
755 static void spi_imx_push(struct spi_imx_data *spi_imx)
756 {
757         while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) {
758                 if (!spi_imx->count)
759                         break;
760                 spi_imx->tx(spi_imx);
761                 spi_imx->txfifo++;
762         }
763 
764         spi_imx->devtype_data->trigger(spi_imx);
765 }
766 
767 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
768 {
769         struct spi_imx_data *spi_imx = dev_id;
770 
771         while (spi_imx->devtype_data->rx_available(spi_imx)) {
772                 spi_imx->rx(spi_imx);
773                 spi_imx->txfifo--;
774         }
775 
776         if (spi_imx->count) {
777                 spi_imx_push(spi_imx);
778                 return IRQ_HANDLED;
779         }
780 
781         if (spi_imx->txfifo) {
782                 /* No data left to push, but still waiting for rx data,
783                  * enable receive data available interrupt.
784                  */
785                 spi_imx->devtype_data->intctrl(
786                                 spi_imx, MXC_INT_RR);
787                 return IRQ_HANDLED;
788         }
789 
790         spi_imx->devtype_data->intctrl(spi_imx, 0);
791         complete(&spi_imx->xfer_done);
792 
793         return IRQ_HANDLED;
794 }
795 
796 static int spi_imx_dma_configure(struct spi_master *master,
797                                  int bytes_per_word)
798 {
799         int ret;
800         enum dma_slave_buswidth buswidth;
801         struct dma_slave_config rx = {}, tx = {};
802         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
803 
804         if (bytes_per_word == spi_imx->bytes_per_word)
805                 /* Same as last time */
806                 return 0;
807 
808         switch (bytes_per_word) {
809         case 4:
810                 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
811                 break;
812         case 2:
813                 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
814                 break;
815         case 1:
816                 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
817                 break;
818         default:
819                 return -EINVAL;
820         }
821 
822         tx.direction = DMA_MEM_TO_DEV;
823         tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
824         tx.dst_addr_width = buswidth;
825         tx.dst_maxburst = spi_imx->wml;
826         ret = dmaengine_slave_config(master->dma_tx, &tx);
827         if (ret) {
828                 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
829                 return ret;
830         }
831 
832         rx.direction = DMA_DEV_TO_MEM;
833         rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
834         rx.src_addr_width = buswidth;
835         rx.src_maxburst = spi_imx->wml;
836         ret = dmaengine_slave_config(master->dma_rx, &rx);
837         if (ret) {
838                 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
839                 return ret;
840         }
841 
842         spi_imx->bytes_per_word = bytes_per_word;
843 
844         return 0;
845 }
846 
847 static int spi_imx_setupxfer(struct spi_device *spi,
848                                  struct spi_transfer *t)
849 {
850         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
851         struct spi_imx_config config;
852         int ret;
853 
854         config.bpw = t ? t->bits_per_word : spi->bits_per_word;
855         config.speed_hz  = t ? t->speed_hz : spi->max_speed_hz;
856 
857         if (!config.speed_hz)
858                 config.speed_hz = spi->max_speed_hz;
859         if (!config.bpw)
860                 config.bpw = spi->bits_per_word;
861 
862         /* Initialize the functions for transfer */
863         if (config.bpw <= 8) {
864                 spi_imx->rx = spi_imx_buf_rx_u8;
865                 spi_imx->tx = spi_imx_buf_tx_u8;
866         } else if (config.bpw <= 16) {
867                 spi_imx->rx = spi_imx_buf_rx_u16;
868                 spi_imx->tx = spi_imx_buf_tx_u16;
869         } else {
870                 spi_imx->rx = spi_imx_buf_rx_u32;
871                 spi_imx->tx = spi_imx_buf_tx_u32;
872         }
873 
874         if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
875                 spi_imx->usedma = 1;
876         else
877                 spi_imx->usedma = 0;
878 
879         if (spi_imx->usedma) {
880                 ret = spi_imx_dma_configure(spi->master,
881                                             spi_imx_bytes_per_word(config.bpw));
882                 if (ret)
883                         return ret;
884         }
885 
886         spi_imx->devtype_data->config(spi, &config);
887 
888         return 0;
889 }
890 
891 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
892 {
893         struct spi_master *master = spi_imx->bitbang.master;
894 
895         if (master->dma_rx) {
896                 dma_release_channel(master->dma_rx);
897                 master->dma_rx = NULL;
898         }
899 
900         if (master->dma_tx) {
901                 dma_release_channel(master->dma_tx);
902                 master->dma_tx = NULL;
903         }
904 }
905 
906 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
907                              struct spi_master *master)
908 {
909         int ret;
910 
911         /* use pio mode for i.mx6dl chip TKT238285 */
912         if (of_machine_is_compatible("fsl,imx6dl"))
913                 return 0;
914 
915         spi_imx->wml = spi_imx_get_fifosize(spi_imx) / 2;
916 
917         /* Prepare for TX DMA: */
918         master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
919         if (IS_ERR(master->dma_tx)) {
920                 ret = PTR_ERR(master->dma_tx);
921                 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
922                 master->dma_tx = NULL;
923                 goto err;
924         }
925 
926         /* Prepare for RX : */
927         master->dma_rx = dma_request_slave_channel_reason(dev, "rx");
928         if (IS_ERR(master->dma_rx)) {
929                 ret = PTR_ERR(master->dma_rx);
930                 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
931                 master->dma_rx = NULL;
932                 goto err;
933         }
934 
935         spi_imx_dma_configure(master, 1);
936 
937         init_completion(&spi_imx->dma_rx_completion);
938         init_completion(&spi_imx->dma_tx_completion);
939         master->can_dma = spi_imx_can_dma;
940         master->max_dma_len = MAX_SDMA_BD_BYTES;
941         spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
942                                          SPI_MASTER_MUST_TX;
943 
944         return 0;
945 err:
946         spi_imx_sdma_exit(spi_imx);
947         return ret;
948 }
949 
950 static void spi_imx_dma_rx_callback(void *cookie)
951 {
952         struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
953 
954         complete(&spi_imx->dma_rx_completion);
955 }
956 
957 static void spi_imx_dma_tx_callback(void *cookie)
958 {
959         struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
960 
961         complete(&spi_imx->dma_tx_completion);
962 }
963 
964 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
965 {
966         unsigned long timeout = 0;
967 
968         /* Time with actual data transfer and CS change delay related to HW */
969         timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
970 
971         /* Add extra second for scheduler related activities */
972         timeout += 1;
973 
974         /* Double calculated timeout */
975         return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
976 }
977 
978 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
979                                 struct spi_transfer *transfer)
980 {
981         struct dma_async_tx_descriptor *desc_tx, *desc_rx;
982         unsigned long transfer_timeout;
983         unsigned long timeout;
984         struct spi_master *master = spi_imx->bitbang.master;
985         struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
986 
987         /*
988          * The TX DMA setup starts the transfer, so make sure RX is configured
989          * before TX.
990          */
991         desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
992                                 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
993                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
994         if (!desc_rx)
995                 return -EINVAL;
996 
997         desc_rx->callback = spi_imx_dma_rx_callback;
998         desc_rx->callback_param = (void *)spi_imx;
999         dmaengine_submit(desc_rx);
1000         reinit_completion(&spi_imx->dma_rx_completion);
1001         dma_async_issue_pending(master->dma_rx);
1002 
1003         desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
1004                                 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1005                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1006         if (!desc_tx) {
1007                 dmaengine_terminate_all(master->dma_tx);
1008                 return -EINVAL;
1009         }
1010 
1011         desc_tx->callback = spi_imx_dma_tx_callback;
1012         desc_tx->callback_param = (void *)spi_imx;
1013         dmaengine_submit(desc_tx);
1014         reinit_completion(&spi_imx->dma_tx_completion);
1015         dma_async_issue_pending(master->dma_tx);
1016 
1017         transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1018 
1019         /* Wait SDMA to finish the data transfer.*/
1020         timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1021                                                 transfer_timeout);
1022         if (!timeout) {
1023                 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1024                 dmaengine_terminate_all(master->dma_tx);
1025                 dmaengine_terminate_all(master->dma_rx);
1026                 return -ETIMEDOUT;
1027         }
1028 
1029         timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1030                                               transfer_timeout);
1031         if (!timeout) {
1032                 dev_err(&master->dev, "I/O Error in DMA RX\n");
1033                 spi_imx->devtype_data->reset(spi_imx);
1034                 dmaengine_terminate_all(master->dma_rx);
1035                 return -ETIMEDOUT;
1036         }
1037 
1038         return transfer->len;
1039 }
1040 
1041 static int spi_imx_pio_transfer(struct spi_device *spi,
1042                                 struct spi_transfer *transfer)
1043 {
1044         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1045         unsigned long transfer_timeout;
1046         unsigned long timeout;
1047 
1048         spi_imx->tx_buf = transfer->tx_buf;
1049         spi_imx->rx_buf = transfer->rx_buf;
1050         spi_imx->count = transfer->len;
1051         spi_imx->txfifo = 0;
1052 
1053         reinit_completion(&spi_imx->xfer_done);
1054 
1055         spi_imx_push(spi_imx);
1056 
1057         spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1058 
1059         transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1060 
1061         timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
1062                                               transfer_timeout);
1063         if (!timeout) {
1064                 dev_err(&spi->dev, "I/O Error in PIO\n");
1065                 spi_imx->devtype_data->reset(spi_imx);
1066                 return -ETIMEDOUT;
1067         }
1068 
1069         return transfer->len;
1070 }
1071 
1072 static int spi_imx_transfer(struct spi_device *spi,
1073                                 struct spi_transfer *transfer)
1074 {
1075         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1076 
1077         if (spi_imx->usedma)
1078                 return spi_imx_dma_transfer(spi_imx, transfer);
1079         else
1080                 return spi_imx_pio_transfer(spi, transfer);
1081 }
1082 
1083 static int spi_imx_setup(struct spi_device *spi)
1084 {
1085         dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1086                  spi->mode, spi->bits_per_word, spi->max_speed_hz);
1087 
1088         if (gpio_is_valid(spi->cs_gpio))
1089                 gpio_direction_output(spi->cs_gpio,
1090                                       spi->mode & SPI_CS_HIGH ? 0 : 1);
1091 
1092         spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
1093 
1094         return 0;
1095 }
1096 
1097 static void spi_imx_cleanup(struct spi_device *spi)
1098 {
1099 }
1100 
1101 static int
1102 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1103 {
1104         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1105         int ret;
1106 
1107         ret = clk_enable(spi_imx->clk_per);
1108         if (ret)
1109                 return ret;
1110 
1111         ret = clk_enable(spi_imx->clk_ipg);
1112         if (ret) {
1113                 clk_disable(spi_imx->clk_per);
1114                 return ret;
1115         }
1116 
1117         return 0;
1118 }
1119 
1120 static int
1121 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1122 {
1123         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1124 
1125         clk_disable(spi_imx->clk_ipg);
1126         clk_disable(spi_imx->clk_per);
1127         return 0;
1128 }
1129 
1130 static int spi_imx_probe(struct platform_device *pdev)
1131 {
1132         struct device_node *np = pdev->dev.of_node;
1133         const struct of_device_id *of_id =
1134                         of_match_device(spi_imx_dt_ids, &pdev->dev);
1135         struct spi_imx_master *mxc_platform_info =
1136                         dev_get_platdata(&pdev->dev);
1137         struct spi_master *master;
1138         struct spi_imx_data *spi_imx;
1139         struct resource *res;
1140         int i, ret, irq;
1141 
1142         if (!np && !mxc_platform_info) {
1143                 dev_err(&pdev->dev, "can't get the platform data\n");
1144                 return -EINVAL;
1145         }
1146 
1147         master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data));
1148         if (!master)
1149                 return -ENOMEM;
1150 
1151         platform_set_drvdata(pdev, master);
1152 
1153         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1154         master->bus_num = np ? -1 : pdev->id;
1155 
1156         spi_imx = spi_master_get_devdata(master);
1157         spi_imx->bitbang.master = master;
1158         spi_imx->dev = &pdev->dev;
1159 
1160         spi_imx->devtype_data = of_id ? of_id->data :
1161                 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
1162 
1163         if (mxc_platform_info) {
1164                 master->num_chipselect = mxc_platform_info->num_chipselect;
1165                 master->cs_gpios = devm_kzalloc(&master->dev,
1166                         sizeof(int) * master->num_chipselect, GFP_KERNEL);
1167                 if (!master->cs_gpios)
1168                         return -ENOMEM;
1169 
1170                 for (i = 0; i < master->num_chipselect; i++)
1171                         master->cs_gpios[i] = mxc_platform_info->chipselect[i];
1172         }
1173 
1174         spi_imx->bitbang.chipselect = spi_imx_chipselect;
1175         spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1176         spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1177         spi_imx->bitbang.master->setup = spi_imx_setup;
1178         spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1179         spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1180         spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1181         spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1182         if (is_imx51_ecspi(spi_imx))
1183                 spi_imx->bitbang.master->mode_bits |= SPI_LOOP;
1184 
1185         init_completion(&spi_imx->xfer_done);
1186 
1187         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1188         spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1189         if (IS_ERR(spi_imx->base)) {
1190                 ret = PTR_ERR(spi_imx->base);
1191                 goto out_master_put;
1192         }
1193         spi_imx->base_phys = res->start;
1194 
1195         irq = platform_get_irq(pdev, 0);
1196         if (irq < 0) {
1197                 ret = irq;
1198                 goto out_master_put;
1199         }
1200 
1201         ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1202                                dev_name(&pdev->dev), spi_imx);
1203         if (ret) {
1204                 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1205                 goto out_master_put;
1206         }
1207 
1208         spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1209         if (IS_ERR(spi_imx->clk_ipg)) {
1210                 ret = PTR_ERR(spi_imx->clk_ipg);
1211                 goto out_master_put;
1212         }
1213 
1214         spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1215         if (IS_ERR(spi_imx->clk_per)) {
1216                 ret = PTR_ERR(spi_imx->clk_per);
1217                 goto out_master_put;
1218         }
1219 
1220         ret = clk_prepare_enable(spi_imx->clk_per);
1221         if (ret)
1222                 goto out_master_put;
1223 
1224         ret = clk_prepare_enable(spi_imx->clk_ipg);
1225         if (ret)
1226                 goto out_put_per;
1227 
1228         spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1229         /*
1230          * Only validated on i.mx6 now, can remove the constrain if validated on
1231          * other chips.
1232          */
1233         if (is_imx51_ecspi(spi_imx)) {
1234                 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
1235                 if (ret == -EPROBE_DEFER)
1236                         goto out_clk_put;
1237 
1238                 if (ret < 0)
1239                         dev_err(&pdev->dev, "dma setup error %d, use pio\n",
1240                                 ret);
1241         }
1242 
1243         spi_imx->devtype_data->reset(spi_imx);
1244 
1245         spi_imx->devtype_data->intctrl(spi_imx, 0);
1246 
1247         master->dev.of_node = pdev->dev.of_node;
1248         ret = spi_bitbang_start(&spi_imx->bitbang);
1249         if (ret) {
1250                 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
1251                 goto out_clk_put;
1252         }
1253 
1254         for (i = 0; i < master->num_chipselect; i++) {
1255                 if (!gpio_is_valid(master->cs_gpios[i]))
1256                         continue;
1257 
1258                 ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i],
1259                                         DRIVER_NAME);
1260                 if (ret) {
1261                         dev_err(&pdev->dev, "Can't get CS GPIO %i\n",
1262                                 master->cs_gpios[i]);
1263                         goto out_clk_put;
1264                 }
1265         }
1266 
1267         dev_info(&pdev->dev, "probed\n");
1268 
1269         clk_disable(spi_imx->clk_ipg);
1270         clk_disable(spi_imx->clk_per);
1271         return ret;
1272 
1273 out_clk_put:
1274         clk_disable_unprepare(spi_imx->clk_ipg);
1275 out_put_per:
1276         clk_disable_unprepare(spi_imx->clk_per);
1277 out_master_put:
1278         spi_master_put(master);
1279 
1280         return ret;
1281 }
1282 
1283 static int spi_imx_remove(struct platform_device *pdev)
1284 {
1285         struct spi_master *master = platform_get_drvdata(pdev);
1286         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1287 
1288         spi_bitbang_stop(&spi_imx->bitbang);
1289 
1290         writel(0, spi_imx->base + MXC_CSPICTRL);
1291         clk_unprepare(spi_imx->clk_ipg);
1292         clk_unprepare(spi_imx->clk_per);
1293         spi_imx_sdma_exit(spi_imx);
1294         spi_master_put(master);
1295 
1296         return 0;
1297 }
1298 
1299 static struct platform_driver spi_imx_driver = {
1300         .driver = {
1301                    .name = DRIVER_NAME,
1302                    .of_match_table = spi_imx_dt_ids,
1303                    },
1304         .id_table = spi_imx_devtype,
1305         .probe = spi_imx_probe,
1306         .remove = spi_imx_remove,
1307 };
1308 module_platform_driver(spi_imx_driver);
1309 
1310 MODULE_DESCRIPTION("SPI Master Controller driver");
1311 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1312 MODULE_LICENSE("GPL");
1313 MODULE_ALIAS("platform:" DRIVER_NAME);
1314 

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