Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/spi/spi-fsl-spi.c

  1 /*
  2  * Freescale SPI controller driver.
  3  *
  4  * Maintainer: Kumar Gala
  5  *
  6  * Copyright (C) 2006 Polycom, Inc.
  7  * Copyright 2010 Freescale Semiconductor, Inc.
  8  *
  9  * CPM SPI and QE buffer descriptors mode support:
 10  * Copyright (c) 2009  MontaVista Software, Inc.
 11  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
 12  *
 13  * GRLIB support:
 14  * Copyright (c) 2012 Aeroflex Gaisler AB.
 15  * Author: Andreas Larsson <andreas@gaisler.com>
 16  *
 17  * This program is free software; you can redistribute  it and/or modify it
 18  * under  the terms of  the GNU General  Public License as published by the
 19  * Free Software Foundation;  either version 2 of the  License, or (at your
 20  * option) any later version.
 21  */
 22 #include <linux/module.h>
 23 #include <linux/types.h>
 24 #include <linux/kernel.h>
 25 #include <linux/interrupt.h>
 26 #include <linux/delay.h>
 27 #include <linux/irq.h>
 28 #include <linux/spi/spi.h>
 29 #include <linux/spi/spi_bitbang.h>
 30 #include <linux/platform_device.h>
 31 #include <linux/fsl_devices.h>
 32 #include <linux/dma-mapping.h>
 33 #include <linux/mm.h>
 34 #include <linux/mutex.h>
 35 #include <linux/of.h>
 36 #include <linux/of_platform.h>
 37 #include <linux/of_address.h>
 38 #include <linux/of_irq.h>
 39 #include <linux/gpio.h>
 40 #include <linux/of_gpio.h>
 41 
 42 #include "spi-fsl-lib.h"
 43 #include "spi-fsl-cpm.h"
 44 #include "spi-fsl-spi.h"
 45 
 46 #define TYPE_FSL        0
 47 #define TYPE_GRLIB      1
 48 
 49 struct fsl_spi_match_data {
 50         int type;
 51 };
 52 
 53 static struct fsl_spi_match_data of_fsl_spi_fsl_config = {
 54         .type = TYPE_FSL,
 55 };
 56 
 57 static struct fsl_spi_match_data of_fsl_spi_grlib_config = {
 58         .type = TYPE_GRLIB,
 59 };
 60 
 61 static const struct of_device_id of_fsl_spi_match[] = {
 62         {
 63                 .compatible = "fsl,spi",
 64                 .data = &of_fsl_spi_fsl_config,
 65         },
 66         {
 67                 .compatible = "aeroflexgaisler,spictrl",
 68                 .data = &of_fsl_spi_grlib_config,
 69         },
 70         {}
 71 };
 72 MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
 73 
 74 static int fsl_spi_get_type(struct device *dev)
 75 {
 76         const struct of_device_id *match;
 77 
 78         if (dev->of_node) {
 79                 match = of_match_node(of_fsl_spi_match, dev->of_node);
 80                 if (match && match->data)
 81                         return ((struct fsl_spi_match_data *)match->data)->type;
 82         }
 83         return TYPE_FSL;
 84 }
 85 
 86 static void fsl_spi_change_mode(struct spi_device *spi)
 87 {
 88         struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
 89         struct spi_mpc8xxx_cs *cs = spi->controller_state;
 90         struct fsl_spi_reg *reg_base = mspi->reg_base;
 91         __be32 __iomem *mode = &reg_base->mode;
 92         unsigned long flags;
 93 
 94         if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
 95                 return;
 96 
 97         /* Turn off IRQs locally to minimize time that SPI is disabled. */
 98         local_irq_save(flags);
 99 
100         /* Turn off SPI unit prior changing mode */
101         mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
102 
103         /* When in CPM mode, we need to reinit tx and rx. */
104         if (mspi->flags & SPI_CPM_MODE) {
105                 fsl_spi_cpm_reinit_txrx(mspi);
106         }
107         mpc8xxx_spi_write_reg(mode, cs->hw_mode);
108         local_irq_restore(flags);
109 }
110 
111 static void fsl_spi_chipselect(struct spi_device *spi, int value)
112 {
113         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
114         struct fsl_spi_platform_data *pdata;
115         bool pol = spi->mode & SPI_CS_HIGH;
116         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
117 
118         pdata = spi->dev.parent->parent->platform_data;
119 
120         if (value == BITBANG_CS_INACTIVE) {
121                 if (pdata->cs_control)
122                         pdata->cs_control(spi, !pol);
123         }
124 
125         if (value == BITBANG_CS_ACTIVE) {
126                 mpc8xxx_spi->rx_shift = cs->rx_shift;
127                 mpc8xxx_spi->tx_shift = cs->tx_shift;
128                 mpc8xxx_spi->get_rx = cs->get_rx;
129                 mpc8xxx_spi->get_tx = cs->get_tx;
130 
131                 fsl_spi_change_mode(spi);
132 
133                 if (pdata->cs_control)
134                         pdata->cs_control(spi, pol);
135         }
136 }
137 
138 static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift,
139                                       int bits_per_word, int msb_first)
140 {
141         *rx_shift = 0;
142         *tx_shift = 0;
143         if (msb_first) {
144                 if (bits_per_word <= 8) {
145                         *rx_shift = 16;
146                         *tx_shift = 24;
147                 } else if (bits_per_word <= 16) {
148                         *rx_shift = 16;
149                         *tx_shift = 16;
150                 }
151         } else {
152                 if (bits_per_word <= 8)
153                         *rx_shift = 8;
154         }
155 }
156 
157 static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift,
158                                      int bits_per_word, int msb_first)
159 {
160         *rx_shift = 0;
161         *tx_shift = 0;
162         if (bits_per_word <= 16) {
163                 if (msb_first) {
164                         *rx_shift = 16; /* LSB in bit 16 */
165                         *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */
166                 } else {
167                         *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */
168                 }
169         }
170 }
171 
172 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
173                                 struct spi_device *spi,
174                                 struct mpc8xxx_spi *mpc8xxx_spi,
175                                 int bits_per_word)
176 {
177         cs->rx_shift = 0;
178         cs->tx_shift = 0;
179         if (bits_per_word <= 8) {
180                 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
181                 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
182         } else if (bits_per_word <= 16) {
183                 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
184                 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
185         } else if (bits_per_word <= 32) {
186                 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
187                 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
188         } else
189                 return -EINVAL;
190 
191         if (mpc8xxx_spi->set_shifts)
192                 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
193                                         bits_per_word,
194                                         !(spi->mode & SPI_LSB_FIRST));
195 
196         mpc8xxx_spi->rx_shift = cs->rx_shift;
197         mpc8xxx_spi->tx_shift = cs->tx_shift;
198         mpc8xxx_spi->get_rx = cs->get_rx;
199         mpc8xxx_spi->get_tx = cs->get_tx;
200 
201         return bits_per_word;
202 }
203 
204 static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
205                                 struct spi_device *spi,
206                                 int bits_per_word)
207 {
208         /* QE uses Little Endian for words > 8
209          * so transform all words > 8 into 8 bits
210          * Unfortnatly that doesn't work for LSB so
211          * reject these for now */
212         /* Note: 32 bits word, LSB works iff
213          * tfcr/rfcr is set to CPMFCR_GBL */
214         if (spi->mode & SPI_LSB_FIRST &&
215             bits_per_word > 8)
216                 return -EINVAL;
217         if (bits_per_word > 8)
218                 return 8; /* pretend its 8 bits */
219         return bits_per_word;
220 }
221 
222 static int fsl_spi_setup_transfer(struct spi_device *spi,
223                                         struct spi_transfer *t)
224 {
225         struct mpc8xxx_spi *mpc8xxx_spi;
226         int bits_per_word = 0;
227         u8 pm;
228         u32 hz = 0;
229         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
230 
231         mpc8xxx_spi = spi_master_get_devdata(spi->master);
232 
233         if (t) {
234                 bits_per_word = t->bits_per_word;
235                 hz = t->speed_hz;
236         }
237 
238         /* spi_transfer level calls that work per-word */
239         if (!bits_per_word)
240                 bits_per_word = spi->bits_per_word;
241 
242         if (!hz)
243                 hz = spi->max_speed_hz;
244 
245         if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
246                 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
247                                                            mpc8xxx_spi,
248                                                            bits_per_word);
249         else if (mpc8xxx_spi->flags & SPI_QE)
250                 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
251                                                           bits_per_word);
252 
253         if (bits_per_word < 0)
254                 return bits_per_word;
255 
256         if (bits_per_word == 32)
257                 bits_per_word = 0;
258         else
259                 bits_per_word = bits_per_word - 1;
260 
261         /* mask out bits we are going to set */
262         cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
263                                   | SPMODE_PM(0xF));
264 
265         cs->hw_mode |= SPMODE_LEN(bits_per_word);
266 
267         if ((mpc8xxx_spi->spibrg / hz) > 64) {
268                 cs->hw_mode |= SPMODE_DIV16;
269                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
270 
271                 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
272                           "Will use %d Hz instead.\n", dev_name(&spi->dev),
273                           hz, mpc8xxx_spi->spibrg / 1024);
274                 if (pm > 16)
275                         pm = 16;
276         } else {
277                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
278         }
279         if (pm)
280                 pm--;
281 
282         cs->hw_mode |= SPMODE_PM(pm);
283 
284         fsl_spi_change_mode(spi);
285         return 0;
286 }
287 
288 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
289                                 struct spi_transfer *t, unsigned int len)
290 {
291         u32 word;
292         struct fsl_spi_reg *reg_base = mspi->reg_base;
293 
294         mspi->count = len;
295 
296         /* enable rx ints */
297         mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
298 
299         /* transmit word */
300         word = mspi->get_tx(mspi);
301         mpc8xxx_spi_write_reg(&reg_base->transmit, word);
302 
303         return 0;
304 }
305 
306 static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
307                             bool is_dma_mapped)
308 {
309         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
310         struct fsl_spi_reg *reg_base;
311         unsigned int len = t->len;
312         u8 bits_per_word;
313         int ret;
314 
315         reg_base = mpc8xxx_spi->reg_base;
316         bits_per_word = spi->bits_per_word;
317         if (t->bits_per_word)
318                 bits_per_word = t->bits_per_word;
319 
320         if (bits_per_word > 8) {
321                 /* invalid length? */
322                 if (len & 1)
323                         return -EINVAL;
324                 len /= 2;
325         }
326         if (bits_per_word > 16) {
327                 /* invalid length? */
328                 if (len & 1)
329                         return -EINVAL;
330                 len /= 2;
331         }
332 
333         mpc8xxx_spi->tx = t->tx_buf;
334         mpc8xxx_spi->rx = t->rx_buf;
335 
336         reinit_completion(&mpc8xxx_spi->done);
337 
338         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
339                 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
340         else
341                 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
342         if (ret)
343                 return ret;
344 
345         wait_for_completion(&mpc8xxx_spi->done);
346 
347         /* disable rx ints */
348         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
349 
350         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
351                 fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
352 
353         return mpc8xxx_spi->count;
354 }
355 
356 static void fsl_spi_do_one_msg(struct spi_message *m)
357 {
358         struct spi_device *spi = m->spi;
359         struct spi_transfer *t, *first;
360         unsigned int cs_change;
361         const int nsecs = 50;
362         int status;
363 
364         /* Don't allow changes if CS is active */
365         first = list_first_entry(&m->transfers, struct spi_transfer,
366                         transfer_list);
367         list_for_each_entry(t, &m->transfers, transfer_list) {
368                 if ((first->bits_per_word != t->bits_per_word) ||
369                         (first->speed_hz != t->speed_hz)) {
370                         status = -EINVAL;
371                         dev_err(&spi->dev,
372                                 "bits_per_word/speed_hz should be same for the same SPI transfer\n");
373                         return;
374                 }
375         }
376 
377         cs_change = 1;
378         status = -EINVAL;
379         list_for_each_entry(t, &m->transfers, transfer_list) {
380                 if (t->bits_per_word || t->speed_hz) {
381                         if (cs_change)
382                                 status = fsl_spi_setup_transfer(spi, t);
383                         if (status < 0)
384                                 break;
385                 }
386 
387                 if (cs_change) {
388                         fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);
389                         ndelay(nsecs);
390                 }
391                 cs_change = t->cs_change;
392                 if (t->len)
393                         status = fsl_spi_bufs(spi, t, m->is_dma_mapped);
394                 if (status) {
395                         status = -EMSGSIZE;
396                         break;
397                 }
398                 m->actual_length += t->len;
399 
400                 if (t->delay_usecs)
401                         udelay(t->delay_usecs);
402 
403                 if (cs_change) {
404                         ndelay(nsecs);
405                         fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
406                         ndelay(nsecs);
407                 }
408         }
409 
410         m->status = status;
411         if (m->complete)
412                 m->complete(m->context);
413 
414         if (status || !cs_change) {
415                 ndelay(nsecs);
416                 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
417         }
418 
419         fsl_spi_setup_transfer(spi, NULL);
420 }
421 
422 static int fsl_spi_setup(struct spi_device *spi)
423 {
424         struct mpc8xxx_spi *mpc8xxx_spi;
425         struct fsl_spi_reg *reg_base;
426         int retval;
427         u32 hw_mode;
428         struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
429 
430         if (!spi->max_speed_hz)
431                 return -EINVAL;
432 
433         if (!cs) {
434                 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
435                 if (!cs)
436                         return -ENOMEM;
437                 spi_set_ctldata(spi, cs);
438         }
439         mpc8xxx_spi = spi_master_get_devdata(spi->master);
440 
441         reg_base = mpc8xxx_spi->reg_base;
442 
443         hw_mode = cs->hw_mode; /* Save original settings */
444         cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
445         /* mask out bits we are going to set */
446         cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
447                          | SPMODE_REV | SPMODE_LOOP);
448 
449         if (spi->mode & SPI_CPHA)
450                 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
451         if (spi->mode & SPI_CPOL)
452                 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
453         if (!(spi->mode & SPI_LSB_FIRST))
454                 cs->hw_mode |= SPMODE_REV;
455         if (spi->mode & SPI_LOOP)
456                 cs->hw_mode |= SPMODE_LOOP;
457 
458         retval = fsl_spi_setup_transfer(spi, NULL);
459         if (retval < 0) {
460                 cs->hw_mode = hw_mode; /* Restore settings */
461                 return retval;
462         }
463 
464         if (mpc8xxx_spi->type == TYPE_GRLIB) {
465                 if (gpio_is_valid(spi->cs_gpio)) {
466                         int desel;
467 
468                         retval = gpio_request(spi->cs_gpio,
469                                               dev_name(&spi->dev));
470                         if (retval)
471                                 return retval;
472 
473                         desel = !(spi->mode & SPI_CS_HIGH);
474                         retval = gpio_direction_output(spi->cs_gpio, desel);
475                         if (retval) {
476                                 gpio_free(spi->cs_gpio);
477                                 return retval;
478                         }
479                 } else if (spi->cs_gpio != -ENOENT) {
480                         if (spi->cs_gpio < 0)
481                                 return spi->cs_gpio;
482                         return -EINVAL;
483                 }
484                 /* When spi->cs_gpio == -ENOENT, a hole in the phandle list
485                  * indicates to use native chipselect if present, or allow for
486                  * an always selected chip
487                  */
488         }
489 
490         /* Initialize chipselect - might be active for SPI_CS_HIGH mode */
491         fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
492 
493         return 0;
494 }
495 
496 static void fsl_spi_cleanup(struct spi_device *spi)
497 {
498         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
499         struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
500 
501         if (mpc8xxx_spi->type == TYPE_GRLIB && gpio_is_valid(spi->cs_gpio))
502                 gpio_free(spi->cs_gpio);
503 
504         kfree(cs);
505         spi_set_ctldata(spi, NULL);
506 }
507 
508 static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
509 {
510         struct fsl_spi_reg *reg_base = mspi->reg_base;
511 
512         /* We need handle RX first */
513         if (events & SPIE_NE) {
514                 u32 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
515 
516                 if (mspi->rx)
517                         mspi->get_rx(rx_data, mspi);
518         }
519 
520         if ((events & SPIE_NF) == 0)
521                 /* spin until TX is done */
522                 while (((events =
523                         mpc8xxx_spi_read_reg(&reg_base->event)) &
524                                                 SPIE_NF) == 0)
525                         cpu_relax();
526 
527         /* Clear the events */
528         mpc8xxx_spi_write_reg(&reg_base->event, events);
529 
530         mspi->count -= 1;
531         if (mspi->count) {
532                 u32 word = mspi->get_tx(mspi);
533 
534                 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
535         } else {
536                 complete(&mspi->done);
537         }
538 }
539 
540 static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
541 {
542         struct mpc8xxx_spi *mspi = context_data;
543         irqreturn_t ret = IRQ_NONE;
544         u32 events;
545         struct fsl_spi_reg *reg_base = mspi->reg_base;
546 
547         /* Get interrupt events(tx/rx) */
548         events = mpc8xxx_spi_read_reg(&reg_base->event);
549         if (events)
550                 ret = IRQ_HANDLED;
551 
552         dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
553 
554         if (mspi->flags & SPI_CPM_MODE)
555                 fsl_spi_cpm_irq(mspi, events);
556         else
557                 fsl_spi_cpu_irq(mspi, events);
558 
559         return ret;
560 }
561 
562 static void fsl_spi_remove(struct mpc8xxx_spi *mspi)
563 {
564         iounmap(mspi->reg_base);
565         fsl_spi_cpm_free(mspi);
566 }
567 
568 static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
569 {
570         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
571         struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
572         u32 slvsel;
573         u16 cs = spi->chip_select;
574 
575         if (gpio_is_valid(spi->cs_gpio)) {
576                 gpio_set_value(spi->cs_gpio, on);
577         } else if (cs < mpc8xxx_spi->native_chipselects) {
578                 slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel);
579                 slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
580                 mpc8xxx_spi_write_reg(&reg_base->slvsel, slvsel);
581         }
582 }
583 
584 static void fsl_spi_grlib_probe(struct device *dev)
585 {
586         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
587         struct spi_master *master = dev_get_drvdata(dev);
588         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
589         struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
590         int mbits;
591         u32 capabilities;
592 
593         capabilities = mpc8xxx_spi_read_reg(&reg_base->cap);
594 
595         mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
596         mbits = SPCAP_MAXWLEN(capabilities);
597         if (mbits)
598                 mpc8xxx_spi->max_bits_per_word = mbits + 1;
599 
600         mpc8xxx_spi->native_chipselects = 0;
601         if (SPCAP_SSEN(capabilities)) {
602                 mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
603                 mpc8xxx_spi_write_reg(&reg_base->slvsel, 0xffffffff);
604         }
605         master->num_chipselect = mpc8xxx_spi->native_chipselects;
606         pdata->cs_control = fsl_spi_grlib_cs_control;
607 }
608 
609 static struct spi_master * fsl_spi_probe(struct device *dev,
610                 struct resource *mem, unsigned int irq)
611 {
612         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
613         struct spi_master *master;
614         struct mpc8xxx_spi *mpc8xxx_spi;
615         struct fsl_spi_reg *reg_base;
616         u32 regval;
617         int ret = 0;
618 
619         master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
620         if (master == NULL) {
621                 ret = -ENOMEM;
622                 goto err;
623         }
624 
625         dev_set_drvdata(dev, master);
626 
627         ret = mpc8xxx_spi_probe(dev, mem, irq);
628         if (ret)
629                 goto err_probe;
630 
631         master->setup = fsl_spi_setup;
632         master->cleanup = fsl_spi_cleanup;
633 
634         mpc8xxx_spi = spi_master_get_devdata(master);
635         mpc8xxx_spi->spi_do_one_msg = fsl_spi_do_one_msg;
636         mpc8xxx_spi->spi_remove = fsl_spi_remove;
637         mpc8xxx_spi->max_bits_per_word = 32;
638         mpc8xxx_spi->type = fsl_spi_get_type(dev);
639 
640         ret = fsl_spi_cpm_init(mpc8xxx_spi);
641         if (ret)
642                 goto err_cpm_init;
643 
644         mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
645         if (mpc8xxx_spi->reg_base == NULL) {
646                 ret = -ENOMEM;
647                 goto err_ioremap;
648         }
649 
650         if (mpc8xxx_spi->type == TYPE_GRLIB)
651                 fsl_spi_grlib_probe(dev);
652 
653         master->bits_per_word_mask =
654                 (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) &
655                 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
656 
657         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
658                 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
659 
660         if (mpc8xxx_spi->set_shifts)
661                 /* 8 bits per word and MSB first */
662                 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
663                                         &mpc8xxx_spi->tx_shift, 8, 1);
664 
665         /* Register for SPI Interrupt */
666         ret = request_irq(mpc8xxx_spi->irq, fsl_spi_irq,
667                           0, "fsl_spi", mpc8xxx_spi);
668 
669         if (ret != 0)
670                 goto free_irq;
671 
672         reg_base = mpc8xxx_spi->reg_base;
673 
674         /* SPI controller initializations */
675         mpc8xxx_spi_write_reg(&reg_base->mode, 0);
676         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
677         mpc8xxx_spi_write_reg(&reg_base->command, 0);
678         mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
679 
680         /* Enable SPI interface */
681         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
682         if (mpc8xxx_spi->max_bits_per_word < 8) {
683                 regval &= ~SPMODE_LEN(0xF);
684                 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
685         }
686         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
687                 regval |= SPMODE_OP;
688 
689         mpc8xxx_spi_write_reg(&reg_base->mode, regval);
690 
691         ret = spi_register_master(master);
692         if (ret < 0)
693                 goto unreg_master;
694 
695         dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
696                  mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
697 
698         return master;
699 
700 unreg_master:
701         free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
702 free_irq:
703         iounmap(mpc8xxx_spi->reg_base);
704 err_ioremap:
705         fsl_spi_cpm_free(mpc8xxx_spi);
706 err_cpm_init:
707 err_probe:
708         spi_master_put(master);
709 err:
710         return ERR_PTR(ret);
711 }
712 
713 static void fsl_spi_cs_control(struct spi_device *spi, bool on)
714 {
715         struct device *dev = spi->dev.parent->parent;
716         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
717         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
718         u16 cs = spi->chip_select;
719         int gpio = pinfo->gpios[cs];
720         bool alow = pinfo->alow_flags[cs];
721 
722         gpio_set_value(gpio, on ^ alow);
723 }
724 
725 static int of_fsl_spi_get_chipselects(struct device *dev)
726 {
727         struct device_node *np = dev->of_node;
728         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
729         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
730         int ngpios;
731         int i = 0;
732         int ret;
733 
734         ngpios = of_gpio_count(np);
735         if (ngpios <= 0) {
736                 /*
737                  * SPI w/o chip-select line. One SPI device is still permitted
738                  * though.
739                  */
740                 pdata->max_chipselect = 1;
741                 return 0;
742         }
743 
744         pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
745         if (!pinfo->gpios)
746                 return -ENOMEM;
747         memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
748 
749         pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
750                                     GFP_KERNEL);
751         if (!pinfo->alow_flags) {
752                 ret = -ENOMEM;
753                 goto err_alloc_flags;
754         }
755 
756         for (; i < ngpios; i++) {
757                 int gpio;
758                 enum of_gpio_flags flags;
759 
760                 gpio = of_get_gpio_flags(np, i, &flags);
761                 if (!gpio_is_valid(gpio)) {
762                         dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
763                         ret = gpio;
764                         goto err_loop;
765                 }
766 
767                 ret = gpio_request(gpio, dev_name(dev));
768                 if (ret) {
769                         dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
770                         goto err_loop;
771                 }
772 
773                 pinfo->gpios[i] = gpio;
774                 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
775 
776                 ret = gpio_direction_output(pinfo->gpios[i],
777                                             pinfo->alow_flags[i]);
778                 if (ret) {
779                         dev_err(dev, "can't set output direction for gpio "
780                                 "#%d: %d\n", i, ret);
781                         goto err_loop;
782                 }
783         }
784 
785         pdata->max_chipselect = ngpios;
786         pdata->cs_control = fsl_spi_cs_control;
787 
788         return 0;
789 
790 err_loop:
791         while (i >= 0) {
792                 if (gpio_is_valid(pinfo->gpios[i]))
793                         gpio_free(pinfo->gpios[i]);
794                 i--;
795         }
796 
797         kfree(pinfo->alow_flags);
798         pinfo->alow_flags = NULL;
799 err_alloc_flags:
800         kfree(pinfo->gpios);
801         pinfo->gpios = NULL;
802         return ret;
803 }
804 
805 static int of_fsl_spi_free_chipselects(struct device *dev)
806 {
807         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
808         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
809         int i;
810 
811         if (!pinfo->gpios)
812                 return 0;
813 
814         for (i = 0; i < pdata->max_chipselect; i++) {
815                 if (gpio_is_valid(pinfo->gpios[i]))
816                         gpio_free(pinfo->gpios[i]);
817         }
818 
819         kfree(pinfo->gpios);
820         kfree(pinfo->alow_flags);
821         return 0;
822 }
823 
824 static int of_fsl_spi_probe(struct platform_device *ofdev)
825 {
826         struct device *dev = &ofdev->dev;
827         struct device_node *np = ofdev->dev.of_node;
828         struct spi_master *master;
829         struct resource mem;
830         int irq, type;
831         int ret = -ENOMEM;
832 
833         ret = of_mpc8xxx_spi_probe(ofdev);
834         if (ret)
835                 return ret;
836 
837         type = fsl_spi_get_type(&ofdev->dev);
838         if (type == TYPE_FSL) {
839                 ret = of_fsl_spi_get_chipselects(dev);
840                 if (ret)
841                         goto err;
842         }
843 
844         ret = of_address_to_resource(np, 0, &mem);
845         if (ret)
846                 goto err;
847 
848         irq = irq_of_parse_and_map(np, 0);
849         if (!irq) {
850                 ret = -EINVAL;
851                 goto err;
852         }
853 
854         master = fsl_spi_probe(dev, &mem, irq);
855         if (IS_ERR(master)) {
856                 ret = PTR_ERR(master);
857                 goto err;
858         }
859 
860         return 0;
861 
862 err:
863         if (type == TYPE_FSL)
864                 of_fsl_spi_free_chipselects(dev);
865         return ret;
866 }
867 
868 static int of_fsl_spi_remove(struct platform_device *ofdev)
869 {
870         struct spi_master *master = platform_get_drvdata(ofdev);
871         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
872         int ret;
873 
874         ret = mpc8xxx_spi_remove(&ofdev->dev);
875         if (ret)
876                 return ret;
877         if (mpc8xxx_spi->type == TYPE_FSL)
878                 of_fsl_spi_free_chipselects(&ofdev->dev);
879         return 0;
880 }
881 
882 static struct platform_driver of_fsl_spi_driver = {
883         .driver = {
884                 .name = "fsl_spi",
885                 .owner = THIS_MODULE,
886                 .of_match_table = of_fsl_spi_match,
887         },
888         .probe          = of_fsl_spi_probe,
889         .remove         = of_fsl_spi_remove,
890 };
891 
892 #ifdef CONFIG_MPC832x_RDB
893 /*
894  * XXX XXX XXX
895  * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
896  * only. The driver should go away soon, since newer MPC8323E-RDB's device
897  * tree can work with OpenFirmware driver. But for now we support old trees
898  * as well.
899  */
900 static int plat_mpc8xxx_spi_probe(struct platform_device *pdev)
901 {
902         struct resource *mem;
903         int irq;
904         struct spi_master *master;
905 
906         if (!dev_get_platdata(&pdev->dev))
907                 return -EINVAL;
908 
909         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
910         if (!mem)
911                 return -EINVAL;
912 
913         irq = platform_get_irq(pdev, 0);
914         if (irq <= 0)
915                 return -EINVAL;
916 
917         master = fsl_spi_probe(&pdev->dev, mem, irq);
918         return PTR_ERR_OR_ZERO(master);
919 }
920 
921 static int plat_mpc8xxx_spi_remove(struct platform_device *pdev)
922 {
923         return mpc8xxx_spi_remove(&pdev->dev);
924 }
925 
926 MODULE_ALIAS("platform:mpc8xxx_spi");
927 static struct platform_driver mpc8xxx_spi_driver = {
928         .probe = plat_mpc8xxx_spi_probe,
929         .remove = plat_mpc8xxx_spi_remove,
930         .driver = {
931                 .name = "mpc8xxx_spi",
932                 .owner = THIS_MODULE,
933         },
934 };
935 
936 static bool legacy_driver_failed;
937 
938 static void __init legacy_driver_register(void)
939 {
940         legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
941 }
942 
943 static void __exit legacy_driver_unregister(void)
944 {
945         if (legacy_driver_failed)
946                 return;
947         platform_driver_unregister(&mpc8xxx_spi_driver);
948 }
949 #else
950 static void __init legacy_driver_register(void) {}
951 static void __exit legacy_driver_unregister(void) {}
952 #endif /* CONFIG_MPC832x_RDB */
953 
954 static int __init fsl_spi_init(void)
955 {
956         legacy_driver_register();
957         return platform_driver_register(&of_fsl_spi_driver);
958 }
959 module_init(fsl_spi_init);
960 
961 static void __exit fsl_spi_exit(void)
962 {
963         platform_driver_unregister(&of_fsl_spi_driver);
964         legacy_driver_unregister();
965 }
966 module_exit(fsl_spi_exit);
967 
968 MODULE_AUTHOR("Kumar Gala");
969 MODULE_DESCRIPTION("Simple Freescale SPI Driver");
970 MODULE_LICENSE("GPL");
971 

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