Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/spi/spi-fsl-spi.c

  1 /*
  2  * Freescale SPI controller driver.
  3  *
  4  * Maintainer: Kumar Gala
  5  *
  6  * Copyright (C) 2006 Polycom, Inc.
  7  * Copyright 2010 Freescale Semiconductor, Inc.
  8  *
  9  * CPM SPI and QE buffer descriptors mode support:
 10  * Copyright (c) 2009  MontaVista Software, Inc.
 11  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
 12  *
 13  * GRLIB support:
 14  * Copyright (c) 2012 Aeroflex Gaisler AB.
 15  * Author: Andreas Larsson <andreas@gaisler.com>
 16  *
 17  * This program is free software; you can redistribute  it and/or modify it
 18  * under  the terms of  the GNU General  Public License as published by the
 19  * Free Software Foundation;  either version 2 of the  License, or (at your
 20  * option) any later version.
 21  */
 22 #include <linux/module.h>
 23 #include <linux/types.h>
 24 #include <linux/kernel.h>
 25 #include <linux/interrupt.h>
 26 #include <linux/delay.h>
 27 #include <linux/irq.h>
 28 #include <linux/spi/spi.h>
 29 #include <linux/spi/spi_bitbang.h>
 30 #include <linux/platform_device.h>
 31 #include <linux/fsl_devices.h>
 32 #include <linux/dma-mapping.h>
 33 #include <linux/mm.h>
 34 #include <linux/mutex.h>
 35 #include <linux/of.h>
 36 #include <linux/of_platform.h>
 37 #include <linux/of_address.h>
 38 #include <linux/of_irq.h>
 39 #include <linux/gpio.h>
 40 #include <linux/of_gpio.h>
 41 
 42 #include "spi-fsl-lib.h"
 43 #include "spi-fsl-cpm.h"
 44 #include "spi-fsl-spi.h"
 45 
 46 #define TYPE_FSL        0
 47 #define TYPE_GRLIB      1
 48 
 49 struct fsl_spi_match_data {
 50         int type;
 51 };
 52 
 53 static struct fsl_spi_match_data of_fsl_spi_fsl_config = {
 54         .type = TYPE_FSL,
 55 };
 56 
 57 static struct fsl_spi_match_data of_fsl_spi_grlib_config = {
 58         .type = TYPE_GRLIB,
 59 };
 60 
 61 static struct of_device_id of_fsl_spi_match[] = {
 62         {
 63                 .compatible = "fsl,spi",
 64                 .data = &of_fsl_spi_fsl_config,
 65         },
 66         {
 67                 .compatible = "aeroflexgaisler,spictrl",
 68                 .data = &of_fsl_spi_grlib_config,
 69         },
 70         {}
 71 };
 72 MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
 73 
 74 static int fsl_spi_get_type(struct device *dev)
 75 {
 76         const struct of_device_id *match;
 77 
 78         if (dev->of_node) {
 79                 match = of_match_node(of_fsl_spi_match, dev->of_node);
 80                 if (match && match->data)
 81                         return ((struct fsl_spi_match_data *)match->data)->type;
 82         }
 83         return TYPE_FSL;
 84 }
 85 
 86 static void fsl_spi_change_mode(struct spi_device *spi)
 87 {
 88         struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
 89         struct spi_mpc8xxx_cs *cs = spi->controller_state;
 90         struct fsl_spi_reg *reg_base = mspi->reg_base;
 91         __be32 __iomem *mode = &reg_base->mode;
 92         unsigned long flags;
 93 
 94         if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
 95                 return;
 96 
 97         /* Turn off IRQs locally to minimize time that SPI is disabled. */
 98         local_irq_save(flags);
 99 
100         /* Turn off SPI unit prior changing mode */
101         mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
102 
103         /* When in CPM mode, we need to reinit tx and rx. */
104         if (mspi->flags & SPI_CPM_MODE) {
105                 fsl_spi_cpm_reinit_txrx(mspi);
106         }
107         mpc8xxx_spi_write_reg(mode, cs->hw_mode);
108         local_irq_restore(flags);
109 }
110 
111 static void fsl_spi_chipselect(struct spi_device *spi, int value)
112 {
113         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
114         struct fsl_spi_platform_data *pdata;
115         bool pol = spi->mode & SPI_CS_HIGH;
116         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
117 
118         pdata = spi->dev.parent->parent->platform_data;
119 
120         if (value == BITBANG_CS_INACTIVE) {
121                 if (pdata->cs_control)
122                         pdata->cs_control(spi, !pol);
123         }
124 
125         if (value == BITBANG_CS_ACTIVE) {
126                 mpc8xxx_spi->rx_shift = cs->rx_shift;
127                 mpc8xxx_spi->tx_shift = cs->tx_shift;
128                 mpc8xxx_spi->get_rx = cs->get_rx;
129                 mpc8xxx_spi->get_tx = cs->get_tx;
130 
131                 fsl_spi_change_mode(spi);
132 
133                 if (pdata->cs_control)
134                         pdata->cs_control(spi, pol);
135         }
136 }
137 
138 static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift,
139                                       int bits_per_word, int msb_first)
140 {
141         *rx_shift = 0;
142         *tx_shift = 0;
143         if (msb_first) {
144                 if (bits_per_word <= 8) {
145                         *rx_shift = 16;
146                         *tx_shift = 24;
147                 } else if (bits_per_word <= 16) {
148                         *rx_shift = 16;
149                         *tx_shift = 16;
150                 }
151         } else {
152                 if (bits_per_word <= 8)
153                         *rx_shift = 8;
154         }
155 }
156 
157 static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift,
158                                      int bits_per_word, int msb_first)
159 {
160         *rx_shift = 0;
161         *tx_shift = 0;
162         if (bits_per_word <= 16) {
163                 if (msb_first) {
164                         *rx_shift = 16; /* LSB in bit 16 */
165                         *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */
166                 } else {
167                         *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */
168                 }
169         }
170 }
171 
172 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
173                                 struct spi_device *spi,
174                                 struct mpc8xxx_spi *mpc8xxx_spi,
175                                 int bits_per_word)
176 {
177         cs->rx_shift = 0;
178         cs->tx_shift = 0;
179         if (bits_per_word <= 8) {
180                 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
181                 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
182         } else if (bits_per_word <= 16) {
183                 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
184                 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
185         } else if (bits_per_word <= 32) {
186                 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
187                 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
188         } else
189                 return -EINVAL;
190 
191         if (mpc8xxx_spi->set_shifts)
192                 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
193                                         bits_per_word,
194                                         !(spi->mode & SPI_LSB_FIRST));
195 
196         mpc8xxx_spi->rx_shift = cs->rx_shift;
197         mpc8xxx_spi->tx_shift = cs->tx_shift;
198         mpc8xxx_spi->get_rx = cs->get_rx;
199         mpc8xxx_spi->get_tx = cs->get_tx;
200 
201         return bits_per_word;
202 }
203 
204 static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
205                                 struct spi_device *spi,
206                                 int bits_per_word)
207 {
208         /* QE uses Little Endian for words > 8
209          * so transform all words > 8 into 8 bits
210          * Unfortnatly that doesn't work for LSB so
211          * reject these for now */
212         /* Note: 32 bits word, LSB works iff
213          * tfcr/rfcr is set to CPMFCR_GBL */
214         if (spi->mode & SPI_LSB_FIRST &&
215             bits_per_word > 8)
216                 return -EINVAL;
217         if (bits_per_word > 8)
218                 return 8; /* pretend its 8 bits */
219         return bits_per_word;
220 }
221 
222 static int fsl_spi_setup_transfer(struct spi_device *spi,
223                                         struct spi_transfer *t)
224 {
225         struct mpc8xxx_spi *mpc8xxx_spi;
226         int bits_per_word = 0;
227         u8 pm;
228         u32 hz = 0;
229         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
230 
231         mpc8xxx_spi = spi_master_get_devdata(spi->master);
232 
233         if (t) {
234                 bits_per_word = t->bits_per_word;
235                 hz = t->speed_hz;
236         }
237 
238         /* spi_transfer level calls that work per-word */
239         if (!bits_per_word)
240                 bits_per_word = spi->bits_per_word;
241 
242         if (!hz)
243                 hz = spi->max_speed_hz;
244 
245         if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
246                 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
247                                                            mpc8xxx_spi,
248                                                            bits_per_word);
249         else if (mpc8xxx_spi->flags & SPI_QE)
250                 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
251                                                           bits_per_word);
252 
253         if (bits_per_word < 0)
254                 return bits_per_word;
255 
256         if (bits_per_word == 32)
257                 bits_per_word = 0;
258         else
259                 bits_per_word = bits_per_word - 1;
260 
261         /* mask out bits we are going to set */
262         cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
263                                   | SPMODE_PM(0xF));
264 
265         cs->hw_mode |= SPMODE_LEN(bits_per_word);
266 
267         if ((mpc8xxx_spi->spibrg / hz) > 64) {
268                 cs->hw_mode |= SPMODE_DIV16;
269                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
270 
271                 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
272                           "Will use %d Hz instead.\n", dev_name(&spi->dev),
273                           hz, mpc8xxx_spi->spibrg / 1024);
274                 if (pm > 16)
275                         pm = 16;
276         } else {
277                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
278         }
279         if (pm)
280                 pm--;
281 
282         cs->hw_mode |= SPMODE_PM(pm);
283 
284         fsl_spi_change_mode(spi);
285         return 0;
286 }
287 
288 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
289                                 struct spi_transfer *t, unsigned int len)
290 {
291         u32 word;
292         struct fsl_spi_reg *reg_base = mspi->reg_base;
293 
294         mspi->count = len;
295 
296         /* enable rx ints */
297         mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
298 
299         /* transmit word */
300         word = mspi->get_tx(mspi);
301         mpc8xxx_spi_write_reg(&reg_base->transmit, word);
302 
303         return 0;
304 }
305 
306 static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
307                             bool is_dma_mapped)
308 {
309         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
310         struct fsl_spi_reg *reg_base;
311         unsigned int len = t->len;
312         u8 bits_per_word;
313         int ret;
314 
315         reg_base = mpc8xxx_spi->reg_base;
316         bits_per_word = spi->bits_per_word;
317         if (t->bits_per_word)
318                 bits_per_word = t->bits_per_word;
319 
320         if (bits_per_word > 8) {
321                 /* invalid length? */
322                 if (len & 1)
323                         return -EINVAL;
324                 len /= 2;
325         }
326         if (bits_per_word > 16) {
327                 /* invalid length? */
328                 if (len & 1)
329                         return -EINVAL;
330                 len /= 2;
331         }
332 
333         mpc8xxx_spi->tx = t->tx_buf;
334         mpc8xxx_spi->rx = t->rx_buf;
335 
336         reinit_completion(&mpc8xxx_spi->done);
337 
338         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
339                 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
340         else
341                 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
342         if (ret)
343                 return ret;
344 
345         wait_for_completion(&mpc8xxx_spi->done);
346 
347         /* disable rx ints */
348         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
349 
350         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
351                 fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
352 
353         return mpc8xxx_spi->count;
354 }
355 
356 static void fsl_spi_do_one_msg(struct spi_message *m)
357 {
358         struct spi_device *spi = m->spi;
359         struct spi_transfer *t, *first;
360         unsigned int cs_change;
361         const int nsecs = 50;
362         int status;
363 
364         /* Don't allow changes if CS is active */
365         first = list_first_entry(&m->transfers, struct spi_transfer,
366                         transfer_list);
367         list_for_each_entry(t, &m->transfers, transfer_list) {
368                 if ((first->bits_per_word != t->bits_per_word) ||
369                         (first->speed_hz != t->speed_hz)) {
370                         status = -EINVAL;
371                         dev_err(&spi->dev,
372                                 "bits_per_word/speed_hz should be same for the same SPI transfer\n");
373                         return;
374                 }
375         }
376 
377         cs_change = 1;
378         status = -EINVAL;
379         list_for_each_entry(t, &m->transfers, transfer_list) {
380                 if (t->bits_per_word || t->speed_hz) {
381                         if (cs_change)
382                                 status = fsl_spi_setup_transfer(spi, t);
383                         if (status < 0)
384                                 break;
385                 }
386 
387                 if (cs_change) {
388                         fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);
389                         ndelay(nsecs);
390                 }
391                 cs_change = t->cs_change;
392                 if (t->len)
393                         status = fsl_spi_bufs(spi, t, m->is_dma_mapped);
394                 if (status) {
395                         status = -EMSGSIZE;
396                         break;
397                 }
398                 m->actual_length += t->len;
399 
400                 if (t->delay_usecs)
401                         udelay(t->delay_usecs);
402 
403                 if (cs_change) {
404                         ndelay(nsecs);
405                         fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
406                         ndelay(nsecs);
407                 }
408         }
409 
410         m->status = status;
411         if (m->complete)
412                 m->complete(m->context);
413 
414         if (status || !cs_change) {
415                 ndelay(nsecs);
416                 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
417         }
418 
419         fsl_spi_setup_transfer(spi, NULL);
420 }
421 
422 static int fsl_spi_setup(struct spi_device *spi)
423 {
424         struct mpc8xxx_spi *mpc8xxx_spi;
425         struct fsl_spi_reg *reg_base;
426         int retval;
427         u32 hw_mode;
428         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
429 
430         if (!spi->max_speed_hz)
431                 return -EINVAL;
432 
433         if (!cs) {
434                 cs = devm_kzalloc(&spi->dev, sizeof(*cs), GFP_KERNEL);
435                 if (!cs)
436                         return -ENOMEM;
437                 spi->controller_state = cs;
438         }
439         mpc8xxx_spi = spi_master_get_devdata(spi->master);
440 
441         reg_base = mpc8xxx_spi->reg_base;
442 
443         hw_mode = cs->hw_mode; /* Save original settings */
444         cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
445         /* mask out bits we are going to set */
446         cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
447                          | SPMODE_REV | SPMODE_LOOP);
448 
449         if (spi->mode & SPI_CPHA)
450                 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
451         if (spi->mode & SPI_CPOL)
452                 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
453         if (!(spi->mode & SPI_LSB_FIRST))
454                 cs->hw_mode |= SPMODE_REV;
455         if (spi->mode & SPI_LOOP)
456                 cs->hw_mode |= SPMODE_LOOP;
457 
458         retval = fsl_spi_setup_transfer(spi, NULL);
459         if (retval < 0) {
460                 cs->hw_mode = hw_mode; /* Restore settings */
461                 return retval;
462         }
463 
464         if (mpc8xxx_spi->type == TYPE_GRLIB) {
465                 if (gpio_is_valid(spi->cs_gpio)) {
466                         int desel;
467 
468                         retval = gpio_request(spi->cs_gpio,
469                                               dev_name(&spi->dev));
470                         if (retval)
471                                 return retval;
472 
473                         desel = !(spi->mode & SPI_CS_HIGH);
474                         retval = gpio_direction_output(spi->cs_gpio, desel);
475                         if (retval) {
476                                 gpio_free(spi->cs_gpio);
477                                 return retval;
478                         }
479                 } else if (spi->cs_gpio != -ENOENT) {
480                         if (spi->cs_gpio < 0)
481                                 return spi->cs_gpio;
482                         return -EINVAL;
483                 }
484                 /* When spi->cs_gpio == -ENOENT, a hole in the phandle list
485                  * indicates to use native chipselect if present, or allow for
486                  * an always selected chip
487                  */
488         }
489 
490         /* Initialize chipselect - might be active for SPI_CS_HIGH mode */
491         fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
492 
493         return 0;
494 }
495 
496 static void fsl_spi_cleanup(struct spi_device *spi)
497 {
498         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
499 
500         if (mpc8xxx_spi->type == TYPE_GRLIB && gpio_is_valid(spi->cs_gpio))
501                 gpio_free(spi->cs_gpio);
502 }
503 
504 static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
505 {
506         struct fsl_spi_reg *reg_base = mspi->reg_base;
507 
508         /* We need handle RX first */
509         if (events & SPIE_NE) {
510                 u32 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
511 
512                 if (mspi->rx)
513                         mspi->get_rx(rx_data, mspi);
514         }
515 
516         if ((events & SPIE_NF) == 0)
517                 /* spin until TX is done */
518                 while (((events =
519                         mpc8xxx_spi_read_reg(&reg_base->event)) &
520                                                 SPIE_NF) == 0)
521                         cpu_relax();
522 
523         /* Clear the events */
524         mpc8xxx_spi_write_reg(&reg_base->event, events);
525 
526         mspi->count -= 1;
527         if (mspi->count) {
528                 u32 word = mspi->get_tx(mspi);
529 
530                 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
531         } else {
532                 complete(&mspi->done);
533         }
534 }
535 
536 static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
537 {
538         struct mpc8xxx_spi *mspi = context_data;
539         irqreturn_t ret = IRQ_NONE;
540         u32 events;
541         struct fsl_spi_reg *reg_base = mspi->reg_base;
542 
543         /* Get interrupt events(tx/rx) */
544         events = mpc8xxx_spi_read_reg(&reg_base->event);
545         if (events)
546                 ret = IRQ_HANDLED;
547 
548         dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
549 
550         if (mspi->flags & SPI_CPM_MODE)
551                 fsl_spi_cpm_irq(mspi, events);
552         else
553                 fsl_spi_cpu_irq(mspi, events);
554 
555         return ret;
556 }
557 
558 static void fsl_spi_remove(struct mpc8xxx_spi *mspi)
559 {
560         iounmap(mspi->reg_base);
561         fsl_spi_cpm_free(mspi);
562 }
563 
564 static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
565 {
566         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
567         struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
568         u32 slvsel;
569         u16 cs = spi->chip_select;
570 
571         if (gpio_is_valid(spi->cs_gpio)) {
572                 gpio_set_value(spi->cs_gpio, on);
573         } else if (cs < mpc8xxx_spi->native_chipselects) {
574                 slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel);
575                 slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
576                 mpc8xxx_spi_write_reg(&reg_base->slvsel, slvsel);
577         }
578 }
579 
580 static void fsl_spi_grlib_probe(struct device *dev)
581 {
582         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
583         struct spi_master *master = dev_get_drvdata(dev);
584         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
585         struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
586         int mbits;
587         u32 capabilities;
588 
589         capabilities = mpc8xxx_spi_read_reg(&reg_base->cap);
590 
591         mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
592         mbits = SPCAP_MAXWLEN(capabilities);
593         if (mbits)
594                 mpc8xxx_spi->max_bits_per_word = mbits + 1;
595 
596         mpc8xxx_spi->native_chipselects = 0;
597         if (SPCAP_SSEN(capabilities)) {
598                 mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
599                 mpc8xxx_spi_write_reg(&reg_base->slvsel, 0xffffffff);
600         }
601         master->num_chipselect = mpc8xxx_spi->native_chipselects;
602         pdata->cs_control = fsl_spi_grlib_cs_control;
603 }
604 
605 static struct spi_master * fsl_spi_probe(struct device *dev,
606                 struct resource *mem, unsigned int irq)
607 {
608         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
609         struct spi_master *master;
610         struct mpc8xxx_spi *mpc8xxx_spi;
611         struct fsl_spi_reg *reg_base;
612         u32 regval;
613         int ret = 0;
614 
615         master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
616         if (master == NULL) {
617                 ret = -ENOMEM;
618                 goto err;
619         }
620 
621         dev_set_drvdata(dev, master);
622 
623         ret = mpc8xxx_spi_probe(dev, mem, irq);
624         if (ret)
625                 goto err_probe;
626 
627         master->setup = fsl_spi_setup;
628         master->cleanup = fsl_spi_cleanup;
629 
630         mpc8xxx_spi = spi_master_get_devdata(master);
631         mpc8xxx_spi->spi_do_one_msg = fsl_spi_do_one_msg;
632         mpc8xxx_spi->spi_remove = fsl_spi_remove;
633         mpc8xxx_spi->max_bits_per_word = 32;
634         mpc8xxx_spi->type = fsl_spi_get_type(dev);
635 
636         ret = fsl_spi_cpm_init(mpc8xxx_spi);
637         if (ret)
638                 goto err_cpm_init;
639 
640         mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
641         if (mpc8xxx_spi->reg_base == NULL) {
642                 ret = -ENOMEM;
643                 goto err_ioremap;
644         }
645 
646         if (mpc8xxx_spi->type == TYPE_GRLIB)
647                 fsl_spi_grlib_probe(dev);
648 
649         master->bits_per_word_mask =
650                 (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) &
651                 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
652 
653         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
654                 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
655 
656         if (mpc8xxx_spi->set_shifts)
657                 /* 8 bits per word and MSB first */
658                 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
659                                         &mpc8xxx_spi->tx_shift, 8, 1);
660 
661         /* Register for SPI Interrupt */
662         ret = request_irq(mpc8xxx_spi->irq, fsl_spi_irq,
663                           0, "fsl_spi", mpc8xxx_spi);
664 
665         if (ret != 0)
666                 goto free_irq;
667 
668         reg_base = mpc8xxx_spi->reg_base;
669 
670         /* SPI controller initializations */
671         mpc8xxx_spi_write_reg(&reg_base->mode, 0);
672         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
673         mpc8xxx_spi_write_reg(&reg_base->command, 0);
674         mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
675 
676         /* Enable SPI interface */
677         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
678         if (mpc8xxx_spi->max_bits_per_word < 8) {
679                 regval &= ~SPMODE_LEN(0xF);
680                 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
681         }
682         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
683                 regval |= SPMODE_OP;
684 
685         mpc8xxx_spi_write_reg(&reg_base->mode, regval);
686 
687         ret = spi_register_master(master);
688         if (ret < 0)
689                 goto unreg_master;
690 
691         dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
692                  mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
693 
694         return master;
695 
696 unreg_master:
697         free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
698 free_irq:
699         iounmap(mpc8xxx_spi->reg_base);
700 err_ioremap:
701         fsl_spi_cpm_free(mpc8xxx_spi);
702 err_cpm_init:
703 err_probe:
704         spi_master_put(master);
705 err:
706         return ERR_PTR(ret);
707 }
708 
709 static void fsl_spi_cs_control(struct spi_device *spi, bool on)
710 {
711         struct device *dev = spi->dev.parent->parent;
712         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
713         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
714         u16 cs = spi->chip_select;
715         int gpio = pinfo->gpios[cs];
716         bool alow = pinfo->alow_flags[cs];
717 
718         gpio_set_value(gpio, on ^ alow);
719 }
720 
721 static int of_fsl_spi_get_chipselects(struct device *dev)
722 {
723         struct device_node *np = dev->of_node;
724         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
725         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
726         int ngpios;
727         int i = 0;
728         int ret;
729 
730         ngpios = of_gpio_count(np);
731         if (ngpios <= 0) {
732                 /*
733                  * SPI w/o chip-select line. One SPI device is still permitted
734                  * though.
735                  */
736                 pdata->max_chipselect = 1;
737                 return 0;
738         }
739 
740         pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
741         if (!pinfo->gpios)
742                 return -ENOMEM;
743         memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
744 
745         pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
746                                     GFP_KERNEL);
747         if (!pinfo->alow_flags) {
748                 ret = -ENOMEM;
749                 goto err_alloc_flags;
750         }
751 
752         for (; i < ngpios; i++) {
753                 int gpio;
754                 enum of_gpio_flags flags;
755 
756                 gpio = of_get_gpio_flags(np, i, &flags);
757                 if (!gpio_is_valid(gpio)) {
758                         dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
759                         ret = gpio;
760                         goto err_loop;
761                 }
762 
763                 ret = gpio_request(gpio, dev_name(dev));
764                 if (ret) {
765                         dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
766                         goto err_loop;
767                 }
768 
769                 pinfo->gpios[i] = gpio;
770                 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
771 
772                 ret = gpio_direction_output(pinfo->gpios[i],
773                                             pinfo->alow_flags[i]);
774                 if (ret) {
775                         dev_err(dev, "can't set output direction for gpio "
776                                 "#%d: %d\n", i, ret);
777                         goto err_loop;
778                 }
779         }
780 
781         pdata->max_chipselect = ngpios;
782         pdata->cs_control = fsl_spi_cs_control;
783 
784         return 0;
785 
786 err_loop:
787         while (i >= 0) {
788                 if (gpio_is_valid(pinfo->gpios[i]))
789                         gpio_free(pinfo->gpios[i]);
790                 i--;
791         }
792 
793         kfree(pinfo->alow_flags);
794         pinfo->alow_flags = NULL;
795 err_alloc_flags:
796         kfree(pinfo->gpios);
797         pinfo->gpios = NULL;
798         return ret;
799 }
800 
801 static int of_fsl_spi_free_chipselects(struct device *dev)
802 {
803         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
804         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
805         int i;
806 
807         if (!pinfo->gpios)
808                 return 0;
809 
810         for (i = 0; i < pdata->max_chipselect; i++) {
811                 if (gpio_is_valid(pinfo->gpios[i]))
812                         gpio_free(pinfo->gpios[i]);
813         }
814 
815         kfree(pinfo->gpios);
816         kfree(pinfo->alow_flags);
817         return 0;
818 }
819 
820 static int of_fsl_spi_probe(struct platform_device *ofdev)
821 {
822         struct device *dev = &ofdev->dev;
823         struct device_node *np = ofdev->dev.of_node;
824         struct spi_master *master;
825         struct resource mem;
826         int irq, type;
827         int ret = -ENOMEM;
828 
829         ret = of_mpc8xxx_spi_probe(ofdev);
830         if (ret)
831                 return ret;
832 
833         type = fsl_spi_get_type(&ofdev->dev);
834         if (type == TYPE_FSL) {
835                 ret = of_fsl_spi_get_chipselects(dev);
836                 if (ret)
837                         goto err;
838         }
839 
840         ret = of_address_to_resource(np, 0, &mem);
841         if (ret)
842                 goto err;
843 
844         irq = irq_of_parse_and_map(np, 0);
845         if (!irq) {
846                 ret = -EINVAL;
847                 goto err;
848         }
849 
850         master = fsl_spi_probe(dev, &mem, irq);
851         if (IS_ERR(master)) {
852                 ret = PTR_ERR(master);
853                 goto err;
854         }
855 
856         return 0;
857 
858 err:
859         if (type == TYPE_FSL)
860                 of_fsl_spi_free_chipselects(dev);
861         return ret;
862 }
863 
864 static int of_fsl_spi_remove(struct platform_device *ofdev)
865 {
866         struct spi_master *master = platform_get_drvdata(ofdev);
867         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
868         int ret;
869 
870         ret = mpc8xxx_spi_remove(&ofdev->dev);
871         if (ret)
872                 return ret;
873         if (mpc8xxx_spi->type == TYPE_FSL)
874                 of_fsl_spi_free_chipselects(&ofdev->dev);
875         return 0;
876 }
877 
878 static struct platform_driver of_fsl_spi_driver = {
879         .driver = {
880                 .name = "fsl_spi",
881                 .owner = THIS_MODULE,
882                 .of_match_table = of_fsl_spi_match,
883         },
884         .probe          = of_fsl_spi_probe,
885         .remove         = of_fsl_spi_remove,
886 };
887 
888 #ifdef CONFIG_MPC832x_RDB
889 /*
890  * XXX XXX XXX
891  * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
892  * only. The driver should go away soon, since newer MPC8323E-RDB's device
893  * tree can work with OpenFirmware driver. But for now we support old trees
894  * as well.
895  */
896 static int plat_mpc8xxx_spi_probe(struct platform_device *pdev)
897 {
898         struct resource *mem;
899         int irq;
900         struct spi_master *master;
901 
902         if (!dev_get_platdata(&pdev->dev))
903                 return -EINVAL;
904 
905         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
906         if (!mem)
907                 return -EINVAL;
908 
909         irq = platform_get_irq(pdev, 0);
910         if (irq <= 0)
911                 return -EINVAL;
912 
913         master = fsl_spi_probe(&pdev->dev, mem, irq);
914         return PTR_ERR_OR_ZERO(master);
915 }
916 
917 static int plat_mpc8xxx_spi_remove(struct platform_device *pdev)
918 {
919         return mpc8xxx_spi_remove(&pdev->dev);
920 }
921 
922 MODULE_ALIAS("platform:mpc8xxx_spi");
923 static struct platform_driver mpc8xxx_spi_driver = {
924         .probe = plat_mpc8xxx_spi_probe,
925         .remove = plat_mpc8xxx_spi_remove,
926         .driver = {
927                 .name = "mpc8xxx_spi",
928                 .owner = THIS_MODULE,
929         },
930 };
931 
932 static bool legacy_driver_failed;
933 
934 static void __init legacy_driver_register(void)
935 {
936         legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
937 }
938 
939 static void __exit legacy_driver_unregister(void)
940 {
941         if (legacy_driver_failed)
942                 return;
943         platform_driver_unregister(&mpc8xxx_spi_driver);
944 }
945 #else
946 static void __init legacy_driver_register(void) {}
947 static void __exit legacy_driver_unregister(void) {}
948 #endif /* CONFIG_MPC832x_RDB */
949 
950 static int __init fsl_spi_init(void)
951 {
952         legacy_driver_register();
953         return platform_driver_register(&of_fsl_spi_driver);
954 }
955 module_init(fsl_spi_init);
956 
957 static void __exit fsl_spi_exit(void)
958 {
959         platform_driver_unregister(&of_fsl_spi_driver);
960         legacy_driver_unregister();
961 }
962 module_exit(fsl_spi_exit);
963 
964 MODULE_AUTHOR("Kumar Gala");
965 MODULE_DESCRIPTION("Simple Freescale SPI Driver");
966 MODULE_LICENSE("GPL");
967 

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