Version:  2.0.40 2.2.26 2.4.37 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0

Linux/drivers/spi/spi-fsl-dspi.c

  1 /*
  2  * drivers/spi/spi-fsl-dspi.c
  3  *
  4  * Copyright 2013 Freescale Semiconductor, Inc.
  5  *
  6  * Freescale DSPI driver
  7  * This file contains a driver for the Freescale DSPI
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License as published by
 11  * the Free Software Foundation; either version 2 of the License, or
 12  * (at your option) any later version.
 13  *
 14  */
 15 
 16 #include <linux/clk.h>
 17 #include <linux/delay.h>
 18 #include <linux/err.h>
 19 #include <linux/errno.h>
 20 #include <linux/interrupt.h>
 21 #include <linux/io.h>
 22 #include <linux/kernel.h>
 23 #include <linux/module.h>
 24 #include <linux/of.h>
 25 #include <linux/of_device.h>
 26 #include <linux/platform_device.h>
 27 #include <linux/pm_runtime.h>
 28 #include <linux/regmap.h>
 29 #include <linux/sched.h>
 30 #include <linux/spi/spi.h>
 31 #include <linux/spi/spi_bitbang.h>
 32 
 33 #define DRIVER_NAME "fsl-dspi"
 34 
 35 #define TRAN_STATE_RX_VOID              0x01
 36 #define TRAN_STATE_TX_VOID              0x02
 37 #define TRAN_STATE_WORD_ODD_NUM 0x04
 38 
 39 #define DSPI_FIFO_SIZE                  4
 40 
 41 #define SPI_MCR         0x00
 42 #define SPI_MCR_MASTER          (1 << 31)
 43 #define SPI_MCR_PCSIS           (0x3F << 16)
 44 #define SPI_MCR_CLR_TXF (1 << 11)
 45 #define SPI_MCR_CLR_RXF (1 << 10)
 46 
 47 #define SPI_TCR                 0x08
 48 
 49 #define SPI_CTAR(x)             (0x0c + (((x) & 0x3) * 4))
 50 #define SPI_CTAR_FMSZ(x)        (((x) & 0x0000000f) << 27)
 51 #define SPI_CTAR_CPOL(x)        ((x) << 26)
 52 #define SPI_CTAR_CPHA(x)        ((x) << 25)
 53 #define SPI_CTAR_LSBFE(x)       ((x) << 24)
 54 #define SPI_CTAR_PCSSCR(x)      (((x) & 0x00000003) << 22)
 55 #define SPI_CTAR_PASC(x)        (((x) & 0x00000003) << 20)
 56 #define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18)
 57 #define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16)
 58 #define SPI_CTAR_CSSCK(x)       (((x) & 0x0000000f) << 12)
 59 #define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8)
 60 #define SPI_CTAR_DT(x)          (((x) & 0x0000000f) << 4)
 61 #define SPI_CTAR_BR(x)          ((x) & 0x0000000f)
 62 
 63 #define SPI_CTAR0_SLAVE 0x0c
 64 
 65 #define SPI_SR                  0x2c
 66 #define SPI_SR_EOQF             0x10000000
 67 
 68 #define SPI_RSER                0x30
 69 #define SPI_RSER_EOQFE          0x10000000
 70 
 71 #define SPI_PUSHR               0x34
 72 #define SPI_PUSHR_CONT          (1 << 31)
 73 #define SPI_PUSHR_CTAS(x)       (((x) & 0x00000003) << 28)
 74 #define SPI_PUSHR_EOQ           (1 << 27)
 75 #define SPI_PUSHR_CTCNT (1 << 26)
 76 #define SPI_PUSHR_PCS(x)        (((1 << x) & 0x0000003f) << 16)
 77 #define SPI_PUSHR_TXDATA(x)     ((x) & 0x0000ffff)
 78 
 79 #define SPI_PUSHR_SLAVE 0x34
 80 
 81 #define SPI_POPR                0x38
 82 #define SPI_POPR_RXDATA(x)      ((x) & 0x0000ffff)
 83 
 84 #define SPI_TXFR0               0x3c
 85 #define SPI_TXFR1               0x40
 86 #define SPI_TXFR2               0x44
 87 #define SPI_TXFR3               0x48
 88 #define SPI_RXFR0               0x7c
 89 #define SPI_RXFR1               0x80
 90 #define SPI_RXFR2               0x84
 91 #define SPI_RXFR3               0x88
 92 
 93 #define SPI_FRAME_BITS(bits)    SPI_CTAR_FMSZ((bits) - 1)
 94 #define SPI_FRAME_BITS_MASK     SPI_CTAR_FMSZ(0xf)
 95 #define SPI_FRAME_BITS_16       SPI_CTAR_FMSZ(0xf)
 96 #define SPI_FRAME_BITS_8        SPI_CTAR_FMSZ(0x7)
 97 
 98 #define SPI_CS_INIT             0x01
 99 #define SPI_CS_ASSERT           0x02
100 #define SPI_CS_DROP             0x04
101 
102 struct chip_data {
103         u32 mcr_val;
104         u32 ctar_val;
105         u16 void_write_data;
106 };
107 
108 struct fsl_dspi {
109         struct spi_master       *master;
110         struct platform_device  *pdev;
111 
112         struct regmap           *regmap;
113         int                     irq;
114         struct clk              *clk;
115 
116         struct spi_transfer     *cur_transfer;
117         struct spi_message      *cur_msg;
118         struct chip_data        *cur_chip;
119         size_t                  len;
120         void                    *tx;
121         void                    *tx_end;
122         void                    *rx;
123         void                    *rx_end;
124         char                    dataflags;
125         u8                      cs;
126         u16                     void_write_data;
127         u32                     cs_change;
128 
129         wait_queue_head_t       waitq;
130         u32                     waitflags;
131 };
132 
133 static inline int is_double_byte_mode(struct fsl_dspi *dspi)
134 {
135         unsigned int val;
136 
137         regmap_read(dspi->regmap, SPI_CTAR(dspi->cs), &val);
138 
139         return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1;
140 }
141 
142 static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
143                 unsigned long clkrate)
144 {
145         /* Valid baud rate pre-scaler values */
146         int pbr_tbl[4] = {2, 3, 5, 7};
147         int brs[16] = { 2,      4,      6,      8,
148                 16,     32,     64,     128,
149                 256,    512,    1024,   2048,
150                 4096,   8192,   16384,  32768 };
151         int temp, i = 0, j = 0;
152 
153         temp = clkrate / 2 / speed_hz;
154 
155         for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++)
156                 for (j = 0; j < ARRAY_SIZE(brs); j++) {
157                         if (pbr_tbl[i] * brs[j] >= temp) {
158                                 *pbr = i;
159                                 *br = j;
160                                 return;
161                         }
162                 }
163 
164         pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld\
165                 ,we use the max prescaler value.\n", speed_hz, clkrate);
166         *pbr = ARRAY_SIZE(pbr_tbl) - 1;
167         *br =  ARRAY_SIZE(brs) - 1;
168 }
169 
170 static int dspi_transfer_write(struct fsl_dspi *dspi)
171 {
172         int tx_count = 0;
173         int tx_word;
174         u16 d16;
175         u8  d8;
176         u32 dspi_pushr = 0;
177         int first = 1;
178 
179         tx_word = is_double_byte_mode(dspi);
180 
181         /* If we are in word mode, but only have a single byte to transfer
182          * then switch to byte mode temporarily.  Will switch back at the
183          * end of the transfer.
184          */
185         if (tx_word && (dspi->len == 1)) {
186                 dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
187                 regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
188                                 SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
189                 tx_word = 0;
190         }
191 
192         while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) {
193                 if (tx_word) {
194                         if (dspi->len == 1)
195                                 break;
196 
197                         if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {
198                                 d16 = *(u16 *)dspi->tx;
199                                 dspi->tx += 2;
200                         } else {
201                                 d16 = dspi->void_write_data;
202                         }
203 
204                         dspi_pushr = SPI_PUSHR_TXDATA(d16) |
205                                 SPI_PUSHR_PCS(dspi->cs) |
206                                 SPI_PUSHR_CTAS(dspi->cs) |
207                                 SPI_PUSHR_CONT;
208 
209                         dspi->len -= 2;
210                 } else {
211                         if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {
212 
213                                 d8 = *(u8 *)dspi->tx;
214                                 dspi->tx++;
215                         } else {
216                                 d8 = (u8)dspi->void_write_data;
217                         }
218 
219                         dspi_pushr = SPI_PUSHR_TXDATA(d8) |
220                                 SPI_PUSHR_PCS(dspi->cs) |
221                                 SPI_PUSHR_CTAS(dspi->cs) |
222                                 SPI_PUSHR_CONT;
223 
224                         dspi->len--;
225                 }
226 
227                 if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1) {
228                         /* last transfer in the transfer */
229                         dspi_pushr |= SPI_PUSHR_EOQ;
230                         if ((dspi->cs_change) && (!dspi->len))
231                                 dspi_pushr &= ~SPI_PUSHR_CONT;
232                 } else if (tx_word && (dspi->len == 1))
233                         dspi_pushr |= SPI_PUSHR_EOQ;
234 
235                 if (first) {
236                         first = 0;
237                         dspi_pushr |= SPI_PUSHR_CTCNT; /* clear counter */
238                 }
239 
240                 regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);
241 
242                 tx_count++;
243         }
244 
245         return tx_count * (tx_word + 1);
246 }
247 
248 static int dspi_transfer_read(struct fsl_dspi *dspi)
249 {
250         int rx_count = 0;
251         int rx_word = is_double_byte_mode(dspi);
252         u16 d;
253 
254         while ((dspi->rx < dspi->rx_end)
255                         && (rx_count < DSPI_FIFO_SIZE)) {
256                 if (rx_word) {
257                         unsigned int val;
258 
259                         if ((dspi->rx_end - dspi->rx) == 1)
260                                 break;
261 
262                         regmap_read(dspi->regmap, SPI_POPR, &val);
263                         d = SPI_POPR_RXDATA(val);
264 
265                         if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
266                                 *(u16 *)dspi->rx = d;
267                         dspi->rx += 2;
268 
269                 } else {
270                         unsigned int val;
271 
272                         regmap_read(dspi->regmap, SPI_POPR, &val);
273                         d = SPI_POPR_RXDATA(val);
274                         if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
275                                 *(u8 *)dspi->rx = d;
276                         dspi->rx++;
277                 }
278                 rx_count++;
279         }
280 
281         return rx_count;
282 }
283 
284 static int dspi_transfer_one_message(struct spi_master *master,
285                 struct spi_message *message)
286 {
287         struct fsl_dspi *dspi = spi_master_get_devdata(master);
288         struct spi_device *spi = message->spi;
289         struct spi_transfer *transfer;
290         int status = 0;
291         message->actual_length = 0;
292 
293         list_for_each_entry(transfer, &message->transfers, transfer_list) {
294                 dspi->cur_transfer = transfer;
295                 dspi->cur_msg = message;
296                 dspi->cur_chip = spi_get_ctldata(spi);
297                 dspi->cs = spi->chip_select;
298                 if (dspi->cur_transfer->transfer_list.next
299                                 == &dspi->cur_msg->transfers)
300                         transfer->cs_change = 1;
301                 dspi->cs_change = transfer->cs_change;
302                 dspi->void_write_data = dspi->cur_chip->void_write_data;
303 
304                 dspi->dataflags = 0;
305                 dspi->tx = (void *)transfer->tx_buf;
306                 dspi->tx_end = dspi->tx + transfer->len;
307                 dspi->rx = transfer->rx_buf;
308                 dspi->rx_end = dspi->rx + transfer->len;
309                 dspi->len = transfer->len;
310 
311                 if (!dspi->rx)
312                         dspi->dataflags |= TRAN_STATE_RX_VOID;
313 
314                 if (!dspi->tx)
315                         dspi->dataflags |= TRAN_STATE_TX_VOID;
316 
317                 regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val);
318                 regmap_update_bits(dspi->regmap, SPI_MCR,
319                                 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
320                                 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
321                 regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
322                                 dspi->cur_chip->ctar_val);
323                 if (transfer->speed_hz)
324                         regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
325                                         dspi->cur_chip->ctar_val);
326 
327                 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
328                 message->actual_length += dspi_transfer_write(dspi);
329 
330                 if (wait_event_interruptible(dspi->waitq, dspi->waitflags))
331                         dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n");
332                 dspi->waitflags = 0;
333 
334                 if (transfer->delay_usecs)
335                         udelay(transfer->delay_usecs);
336         }
337 
338         message->status = status;
339         spi_finalize_current_message(master);
340 
341         return status;
342 }
343 
344 static int dspi_setup(struct spi_device *spi)
345 {
346         struct chip_data *chip;
347         struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
348         unsigned char br = 0, pbr = 0, fmsz = 0;
349 
350         if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
351                 fmsz = spi->bits_per_word - 1;
352         } else {
353                 pr_err("Invalid wordsize\n");
354                 return -ENODEV;
355         }
356 
357         /* Only alloc on first setup */
358         chip = spi_get_ctldata(spi);
359         if (chip == NULL) {
360                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
361                 if (!chip)
362                         return -ENOMEM;
363         }
364 
365         chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS |
366                 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF;
367 
368         chip->void_write_data = 0;
369 
370         hz_to_spi_baud(&pbr, &br,
371                         spi->max_speed_hz, clk_get_rate(dspi->clk));
372 
373         chip->ctar_val =  SPI_CTAR_FMSZ(fmsz)
374                 | SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
375                 | SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0)
376                 | SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0)
377                 | SPI_CTAR_PBR(pbr)
378                 | SPI_CTAR_BR(br);
379 
380         spi_set_ctldata(spi, chip);
381 
382         return 0;
383 }
384 
385 static void dspi_cleanup(struct spi_device *spi)
386 {
387         struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
388 
389         dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
390                         spi->master->bus_num, spi->chip_select);
391 
392         kfree(chip);
393 }
394 
395 static irqreturn_t dspi_interrupt(int irq, void *dev_id)
396 {
397         struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
398 
399         struct spi_message *msg = dspi->cur_msg;
400 
401         regmap_write(dspi->regmap, SPI_SR, SPI_SR_EOQF);
402         dspi_transfer_read(dspi);
403 
404         if (!dspi->len) {
405                 if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM)
406                         regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
407                         SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(16));
408 
409                 dspi->waitflags = 1;
410                 wake_up_interruptible(&dspi->waitq);
411         } else
412                 msg->actual_length += dspi_transfer_write(dspi);
413 
414         return IRQ_HANDLED;
415 }
416 
417 static const struct of_device_id fsl_dspi_dt_ids[] = {
418         { .compatible = "fsl,vf610-dspi", .data = NULL, },
419         { /* sentinel */ }
420 };
421 MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
422 
423 #ifdef CONFIG_PM_SLEEP
424 static int dspi_suspend(struct device *dev)
425 {
426         struct spi_master *master = dev_get_drvdata(dev);
427         struct fsl_dspi *dspi = spi_master_get_devdata(master);
428 
429         spi_master_suspend(master);
430         clk_disable_unprepare(dspi->clk);
431 
432         return 0;
433 }
434 
435 static int dspi_resume(struct device *dev)
436 {
437         struct spi_master *master = dev_get_drvdata(dev);
438         struct fsl_dspi *dspi = spi_master_get_devdata(master);
439 
440         clk_prepare_enable(dspi->clk);
441         spi_master_resume(master);
442 
443         return 0;
444 }
445 #endif /* CONFIG_PM_SLEEP */
446 
447 static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
448 
449 static const struct regmap_config dspi_regmap_config = {
450         .reg_bits = 32,
451         .val_bits = 32,
452         .reg_stride = 4,
453         .max_register = 0x88,
454 };
455 
456 static int dspi_probe(struct platform_device *pdev)
457 {
458         struct device_node *np = pdev->dev.of_node;
459         struct spi_master *master;
460         struct fsl_dspi *dspi;
461         struct resource *res;
462         void __iomem *base;
463         int ret = 0, cs_num, bus_num;
464 
465         master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
466         if (!master)
467                 return -ENOMEM;
468 
469         dspi = spi_master_get_devdata(master);
470         dspi->pdev = pdev;
471         dspi->master = master;
472 
473         master->transfer = NULL;
474         master->setup = dspi_setup;
475         master->transfer_one_message = dspi_transfer_one_message;
476         master->dev.of_node = pdev->dev.of_node;
477 
478         master->cleanup = dspi_cleanup;
479         master->mode_bits = SPI_CPOL | SPI_CPHA;
480         master->bits_per_word_mask = SPI_BPW_MASK(4) | SPI_BPW_MASK(8) |
481                                         SPI_BPW_MASK(16);
482 
483         ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
484         if (ret < 0) {
485                 dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
486                 goto out_master_put;
487         }
488         master->num_chipselect = cs_num;
489 
490         ret = of_property_read_u32(np, "bus-num", &bus_num);
491         if (ret < 0) {
492                 dev_err(&pdev->dev, "can't get bus-num\n");
493                 goto out_master_put;
494         }
495         master->bus_num = bus_num;
496 
497         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
498         base = devm_ioremap_resource(&pdev->dev, res);
499         if (IS_ERR(base)) {
500                 ret = PTR_ERR(base);
501                 goto out_master_put;
502         }
503 
504         dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dspi", base,
505                                                 &dspi_regmap_config);
506         if (IS_ERR(dspi->regmap)) {
507                 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
508                                 PTR_ERR(dspi->regmap));
509                 return PTR_ERR(dspi->regmap);
510         }
511 
512         dspi->irq = platform_get_irq(pdev, 0);
513         if (dspi->irq < 0) {
514                 dev_err(&pdev->dev, "can't get platform irq\n");
515                 ret = dspi->irq;
516                 goto out_master_put;
517         }
518 
519         ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0,
520                         pdev->name, dspi);
521         if (ret < 0) {
522                 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
523                 goto out_master_put;
524         }
525 
526         dspi->clk = devm_clk_get(&pdev->dev, "dspi");
527         if (IS_ERR(dspi->clk)) {
528                 ret = PTR_ERR(dspi->clk);
529                 dev_err(&pdev->dev, "unable to get clock\n");
530                 goto out_master_put;
531         }
532         clk_prepare_enable(dspi->clk);
533 
534         init_waitqueue_head(&dspi->waitq);
535         platform_set_drvdata(pdev, master);
536 
537         ret = spi_register_master(master);
538         if (ret != 0) {
539                 dev_err(&pdev->dev, "Problem registering DSPI master\n");
540                 goto out_clk_put;
541         }
542 
543         return ret;
544 
545 out_clk_put:
546         clk_disable_unprepare(dspi->clk);
547 out_master_put:
548         spi_master_put(master);
549 
550         return ret;
551 }
552 
553 static int dspi_remove(struct platform_device *pdev)
554 {
555         struct spi_master *master = platform_get_drvdata(pdev);
556         struct fsl_dspi *dspi = spi_master_get_devdata(master);
557 
558         /* Disconnect from the SPI framework */
559         clk_disable_unprepare(dspi->clk);
560         spi_unregister_master(dspi->master);
561         spi_master_put(dspi->master);
562 
563         return 0;
564 }
565 
566 static struct platform_driver fsl_dspi_driver = {
567         .driver.name    = DRIVER_NAME,
568         .driver.of_match_table = fsl_dspi_dt_ids,
569         .driver.owner   = THIS_MODULE,
570         .driver.pm = &dspi_pm,
571         .probe          = dspi_probe,
572         .remove         = dspi_remove,
573 };
574 module_platform_driver(fsl_dspi_driver);
575 
576 MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
577 MODULE_LICENSE("GPL");
578 MODULE_ALIAS("platform:" DRIVER_NAME);
579 

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