Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/spi/spi-davinci.c

  1 /*
  2  * Copyright (C) 2009 Texas Instruments.
  3  * Copyright (C) 2010 EF Johnson Technologies
  4  *
  5  * This program is free software; you can redistribute it and/or modify
  6  * it under the terms of the GNU General Public License as published by
  7  * the Free Software Foundation; either version 2 of the License, or
  8  * (at your option) any later version.
  9  *
 10  * This program is distributed in the hope that it will be useful,
 11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  *
 15  * You should have received a copy of the GNU General Public License
 16  * along with this program; if not, write to the Free Software
 17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 18  */
 19 
 20 #include <linux/interrupt.h>
 21 #include <linux/io.h>
 22 #include <linux/gpio.h>
 23 #include <linux/module.h>
 24 #include <linux/delay.h>
 25 #include <linux/platform_device.h>
 26 #include <linux/err.h>
 27 #include <linux/clk.h>
 28 #include <linux/dmaengine.h>
 29 #include <linux/dma-mapping.h>
 30 #include <linux/edma.h>
 31 #include <linux/of.h>
 32 #include <linux/of_device.h>
 33 #include <linux/spi/spi.h>
 34 #include <linux/spi/spi_bitbang.h>
 35 #include <linux/slab.h>
 36 
 37 #include <linux/platform_data/spi-davinci.h>
 38 
 39 #define SPI_NO_RESOURCE         ((resource_size_t)-1)
 40 
 41 #define SPI_MAX_CHIPSELECT      2
 42 
 43 #define CS_DEFAULT      0xFF
 44 
 45 #define SPIFMT_PHASE_MASK       BIT(16)
 46 #define SPIFMT_POLARITY_MASK    BIT(17)
 47 #define SPIFMT_DISTIMER_MASK    BIT(18)
 48 #define SPIFMT_SHIFTDIR_MASK    BIT(20)
 49 #define SPIFMT_WAITENA_MASK     BIT(21)
 50 #define SPIFMT_PARITYENA_MASK   BIT(22)
 51 #define SPIFMT_ODD_PARITY_MASK  BIT(23)
 52 #define SPIFMT_WDELAY_MASK      0x3f000000u
 53 #define SPIFMT_WDELAY_SHIFT     24
 54 #define SPIFMT_PRESCALE_SHIFT   8
 55 
 56 /* SPIPC0 */
 57 #define SPIPC0_DIFUN_MASK       BIT(11)         /* MISO */
 58 #define SPIPC0_DOFUN_MASK       BIT(10)         /* MOSI */
 59 #define SPIPC0_CLKFUN_MASK      BIT(9)          /* CLK */
 60 #define SPIPC0_SPIENA_MASK      BIT(8)          /* nREADY */
 61 
 62 #define SPIINT_MASKALL          0x0101035F
 63 #define SPIINT_MASKINT          0x0000015F
 64 #define SPI_INTLVL_1            0x000001FF
 65 #define SPI_INTLVL_0            0x00000000
 66 
 67 /* SPIDAT1 (upper 16 bit defines) */
 68 #define SPIDAT1_CSHOLD_MASK     BIT(12)
 69 
 70 /* SPIGCR1 */
 71 #define SPIGCR1_CLKMOD_MASK     BIT(1)
 72 #define SPIGCR1_MASTER_MASK     BIT(0)
 73 #define SPIGCR1_POWERDOWN_MASK  BIT(8)
 74 #define SPIGCR1_LOOPBACK_MASK   BIT(16)
 75 #define SPIGCR1_SPIENA_MASK     BIT(24)
 76 
 77 /* SPIBUF */
 78 #define SPIBUF_TXFULL_MASK      BIT(29)
 79 #define SPIBUF_RXEMPTY_MASK     BIT(31)
 80 
 81 /* SPIDELAY */
 82 #define SPIDELAY_C2TDELAY_SHIFT 24
 83 #define SPIDELAY_C2TDELAY_MASK  (0xFF << SPIDELAY_C2TDELAY_SHIFT)
 84 #define SPIDELAY_T2CDELAY_SHIFT 16
 85 #define SPIDELAY_T2CDELAY_MASK  (0xFF << SPIDELAY_T2CDELAY_SHIFT)
 86 #define SPIDELAY_T2EDELAY_SHIFT 8
 87 #define SPIDELAY_T2EDELAY_MASK  (0xFF << SPIDELAY_T2EDELAY_SHIFT)
 88 #define SPIDELAY_C2EDELAY_SHIFT 0
 89 #define SPIDELAY_C2EDELAY_MASK  0xFF
 90 
 91 /* Error Masks */
 92 #define SPIFLG_DLEN_ERR_MASK            BIT(0)
 93 #define SPIFLG_TIMEOUT_MASK             BIT(1)
 94 #define SPIFLG_PARERR_MASK              BIT(2)
 95 #define SPIFLG_DESYNC_MASK              BIT(3)
 96 #define SPIFLG_BITERR_MASK              BIT(4)
 97 #define SPIFLG_OVRRUN_MASK              BIT(6)
 98 #define SPIFLG_BUF_INIT_ACTIVE_MASK     BIT(24)
 99 #define SPIFLG_ERROR_MASK               (SPIFLG_DLEN_ERR_MASK \
100                                 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
101                                 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
102                                 | SPIFLG_OVRRUN_MASK)
103 
104 #define SPIINT_DMA_REQ_EN       BIT(16)
105 
106 /* SPI Controller registers */
107 #define SPIGCR0         0x00
108 #define SPIGCR1         0x04
109 #define SPIINT          0x08
110 #define SPILVL          0x0c
111 #define SPIFLG          0x10
112 #define SPIPC0          0x14
113 #define SPIDAT1         0x3c
114 #define SPIBUF          0x40
115 #define SPIDELAY        0x48
116 #define SPIDEF          0x4c
117 #define SPIFMT0         0x50
118 
119 /* SPI Controller driver's private data. */
120 struct davinci_spi {
121         struct spi_bitbang      bitbang;
122         struct clk              *clk;
123 
124         u8                      version;
125         resource_size_t         pbase;
126         void __iomem            *base;
127         u32                     irq;
128         struct completion       done;
129 
130         const void              *tx;
131         void                    *rx;
132         int                     rcount;
133         int                     wcount;
134 
135         struct dma_chan         *dma_rx;
136         struct dma_chan         *dma_tx;
137         int                     dma_rx_chnum;
138         int                     dma_tx_chnum;
139 
140         struct davinci_spi_platform_data pdata;
141 
142         void                    (*get_rx)(u32 rx_data, struct davinci_spi *);
143         u32                     (*get_tx)(struct davinci_spi *);
144 
145         u8                      bytes_per_word[SPI_MAX_CHIPSELECT];
146 };
147 
148 static struct davinci_spi_config davinci_spi_default_cfg;
149 
150 static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi)
151 {
152         if (dspi->rx) {
153                 u8 *rx = dspi->rx;
154                 *rx++ = (u8)data;
155                 dspi->rx = rx;
156         }
157 }
158 
159 static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
160 {
161         if (dspi->rx) {
162                 u16 *rx = dspi->rx;
163                 *rx++ = (u16)data;
164                 dspi->rx = rx;
165         }
166 }
167 
168 static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
169 {
170         u32 data = 0;
171         if (dspi->tx) {
172                 const u8 *tx = dspi->tx;
173                 data = *tx++;
174                 dspi->tx = tx;
175         }
176         return data;
177 }
178 
179 static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
180 {
181         u32 data = 0;
182         if (dspi->tx) {
183                 const u16 *tx = dspi->tx;
184                 data = *tx++;
185                 dspi->tx = tx;
186         }
187         return data;
188 }
189 
190 static inline void set_io_bits(void __iomem *addr, u32 bits)
191 {
192         u32 v = ioread32(addr);
193 
194         v |= bits;
195         iowrite32(v, addr);
196 }
197 
198 static inline void clear_io_bits(void __iomem *addr, u32 bits)
199 {
200         u32 v = ioread32(addr);
201 
202         v &= ~bits;
203         iowrite32(v, addr);
204 }
205 
206 /*
207  * Interface to control the chip select signal
208  */
209 static void davinci_spi_chipselect(struct spi_device *spi, int value)
210 {
211         struct davinci_spi *dspi;
212         struct davinci_spi_platform_data *pdata;
213         u8 chip_sel = spi->chip_select;
214         u16 spidat1 = CS_DEFAULT;
215         bool gpio_chipsel = false;
216 
217         dspi = spi_master_get_devdata(spi->master);
218         pdata = &dspi->pdata;
219 
220         if (pdata->chip_sel && chip_sel < pdata->num_chipselect &&
221                                 pdata->chip_sel[chip_sel] != SPI_INTERN_CS)
222                 gpio_chipsel = true;
223 
224         /*
225          * Board specific chip select logic decides the polarity and cs
226          * line for the controller
227          */
228         if (gpio_chipsel) {
229                 if (value == BITBANG_CS_ACTIVE)
230                         gpio_set_value(pdata->chip_sel[chip_sel], 0);
231                 else
232                         gpio_set_value(pdata->chip_sel[chip_sel], 1);
233         } else {
234                 if (value == BITBANG_CS_ACTIVE) {
235                         spidat1 |= SPIDAT1_CSHOLD_MASK;
236                         spidat1 &= ~(0x1 << chip_sel);
237                 }
238 
239                 iowrite16(spidat1, dspi->base + SPIDAT1 + 2);
240         }
241 }
242 
243 /**
244  * davinci_spi_get_prescale - Calculates the correct prescale value
245  * @maxspeed_hz: the maximum rate the SPI clock can run at
246  *
247  * This function calculates the prescale value that generates a clock rate
248  * less than or equal to the specified maximum.
249  *
250  * Returns: calculated prescale - 1 for easy programming into SPI registers
251  * or negative error number if valid prescalar cannot be updated.
252  */
253 static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
254                                                         u32 max_speed_hz)
255 {
256         int ret;
257 
258         ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz);
259 
260         if (ret < 3 || ret > 256)
261                 return -EINVAL;
262 
263         return ret - 1;
264 }
265 
266 /**
267  * davinci_spi_setup_transfer - This functions will determine transfer method
268  * @spi: spi device on which data transfer to be done
269  * @t: spi transfer in which transfer info is filled
270  *
271  * This function determines data transfer method (8/16/32 bit transfer).
272  * It will also set the SPI Clock Control register according to
273  * SPI slave device freq.
274  */
275 static int davinci_spi_setup_transfer(struct spi_device *spi,
276                 struct spi_transfer *t)
277 {
278 
279         struct davinci_spi *dspi;
280         struct davinci_spi_config *spicfg;
281         u8 bits_per_word = 0;
282         u32 hz = 0, spifmt = 0;
283         int prescale;
284 
285         dspi = spi_master_get_devdata(spi->master);
286         spicfg = (struct davinci_spi_config *)spi->controller_data;
287         if (!spicfg)
288                 spicfg = &davinci_spi_default_cfg;
289 
290         if (t) {
291                 bits_per_word = t->bits_per_word;
292                 hz = t->speed_hz;
293         }
294 
295         /* if bits_per_word is not set then set it default */
296         if (!bits_per_word)
297                 bits_per_word = spi->bits_per_word;
298 
299         /*
300          * Assign function pointer to appropriate transfer method
301          * 8bit, 16bit or 32bit transfer
302          */
303         if (bits_per_word <= 8) {
304                 dspi->get_rx = davinci_spi_rx_buf_u8;
305                 dspi->get_tx = davinci_spi_tx_buf_u8;
306                 dspi->bytes_per_word[spi->chip_select] = 1;
307         } else {
308                 dspi->get_rx = davinci_spi_rx_buf_u16;
309                 dspi->get_tx = davinci_spi_tx_buf_u16;
310                 dspi->bytes_per_word[spi->chip_select] = 2;
311         }
312 
313         if (!hz)
314                 hz = spi->max_speed_hz;
315 
316         /* Set up SPIFMTn register, unique to this chipselect. */
317 
318         prescale = davinci_spi_get_prescale(dspi, hz);
319         if (prescale < 0)
320                 return prescale;
321 
322         spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
323 
324         if (spi->mode & SPI_LSB_FIRST)
325                 spifmt |= SPIFMT_SHIFTDIR_MASK;
326 
327         if (spi->mode & SPI_CPOL)
328                 spifmt |= SPIFMT_POLARITY_MASK;
329 
330         if (!(spi->mode & SPI_CPHA))
331                 spifmt |= SPIFMT_PHASE_MASK;
332 
333         /*
334          * Version 1 hardware supports two basic SPI modes:
335          *  - Standard SPI mode uses 4 pins, with chipselect
336          *  - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
337          *      (distinct from SPI_3WIRE, with just one data wire;
338          *      or similar variants without MOSI or without MISO)
339          *
340          * Version 2 hardware supports an optional handshaking signal,
341          * so it can support two more modes:
342          *  - 5 pin SPI variant is standard SPI plus SPI_READY
343          *  - 4 pin with enable is (SPI_READY | SPI_NO_CS)
344          */
345 
346         if (dspi->version == SPI_VERSION_2) {
347 
348                 u32 delay = 0;
349 
350                 spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
351                                                         & SPIFMT_WDELAY_MASK);
352 
353                 if (spicfg->odd_parity)
354                         spifmt |= SPIFMT_ODD_PARITY_MASK;
355 
356                 if (spicfg->parity_enable)
357                         spifmt |= SPIFMT_PARITYENA_MASK;
358 
359                 if (spicfg->timer_disable) {
360                         spifmt |= SPIFMT_DISTIMER_MASK;
361                 } else {
362                         delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
363                                                 & SPIDELAY_C2TDELAY_MASK;
364                         delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
365                                                 & SPIDELAY_T2CDELAY_MASK;
366                 }
367 
368                 if (spi->mode & SPI_READY) {
369                         spifmt |= SPIFMT_WAITENA_MASK;
370                         delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
371                                                 & SPIDELAY_T2EDELAY_MASK;
372                         delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
373                                                 & SPIDELAY_C2EDELAY_MASK;
374                 }
375 
376                 iowrite32(delay, dspi->base + SPIDELAY);
377         }
378 
379         iowrite32(spifmt, dspi->base + SPIFMT0);
380 
381         return 0;
382 }
383 
384 /**
385  * davinci_spi_setup - This functions will set default transfer method
386  * @spi: spi device on which data transfer to be done
387  *
388  * This functions sets the default transfer method.
389  */
390 static int davinci_spi_setup(struct spi_device *spi)
391 {
392         int retval = 0;
393         struct davinci_spi *dspi;
394         struct davinci_spi_platform_data *pdata;
395 
396         dspi = spi_master_get_devdata(spi->master);
397         pdata = &dspi->pdata;
398 
399         if (!(spi->mode & SPI_NO_CS)) {
400                 if ((pdata->chip_sel == NULL) ||
401                     (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS))
402                         set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
403 
404         }
405 
406         if (spi->mode & SPI_READY)
407                 set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
408 
409         if (spi->mode & SPI_LOOP)
410                 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
411         else
412                 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
413 
414         return retval;
415 }
416 
417 static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
418 {
419         struct device *sdev = dspi->bitbang.master->dev.parent;
420 
421         if (int_status & SPIFLG_TIMEOUT_MASK) {
422                 dev_dbg(sdev, "SPI Time-out Error\n");
423                 return -ETIMEDOUT;
424         }
425         if (int_status & SPIFLG_DESYNC_MASK) {
426                 dev_dbg(sdev, "SPI Desynchronization Error\n");
427                 return -EIO;
428         }
429         if (int_status & SPIFLG_BITERR_MASK) {
430                 dev_dbg(sdev, "SPI Bit error\n");
431                 return -EIO;
432         }
433 
434         if (dspi->version == SPI_VERSION_2) {
435                 if (int_status & SPIFLG_DLEN_ERR_MASK) {
436                         dev_dbg(sdev, "SPI Data Length Error\n");
437                         return -EIO;
438                 }
439                 if (int_status & SPIFLG_PARERR_MASK) {
440                         dev_dbg(sdev, "SPI Parity Error\n");
441                         return -EIO;
442                 }
443                 if (int_status & SPIFLG_OVRRUN_MASK) {
444                         dev_dbg(sdev, "SPI Data Overrun error\n");
445                         return -EIO;
446                 }
447                 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
448                         dev_dbg(sdev, "SPI Buffer Init Active\n");
449                         return -EBUSY;
450                 }
451         }
452 
453         return 0;
454 }
455 
456 /**
457  * davinci_spi_process_events - check for and handle any SPI controller events
458  * @dspi: the controller data
459  *
460  * This function will check the SPIFLG register and handle any events that are
461  * detected there
462  */
463 static int davinci_spi_process_events(struct davinci_spi *dspi)
464 {
465         u32 buf, status, errors = 0, spidat1;
466 
467         buf = ioread32(dspi->base + SPIBUF);
468 
469         if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
470                 dspi->get_rx(buf & 0xFFFF, dspi);
471                 dspi->rcount--;
472         }
473 
474         status = ioread32(dspi->base + SPIFLG);
475 
476         if (unlikely(status & SPIFLG_ERROR_MASK)) {
477                 errors = status & SPIFLG_ERROR_MASK;
478                 goto out;
479         }
480 
481         if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
482                 spidat1 = ioread32(dspi->base + SPIDAT1);
483                 dspi->wcount--;
484                 spidat1 &= ~0xFFFF;
485                 spidat1 |= 0xFFFF & dspi->get_tx(dspi);
486                 iowrite32(spidat1, dspi->base + SPIDAT1);
487         }
488 
489 out:
490         return errors;
491 }
492 
493 static void davinci_spi_dma_rx_callback(void *data)
494 {
495         struct davinci_spi *dspi = (struct davinci_spi *)data;
496 
497         dspi->rcount = 0;
498 
499         if (!dspi->wcount && !dspi->rcount)
500                 complete(&dspi->done);
501 }
502 
503 static void davinci_spi_dma_tx_callback(void *data)
504 {
505         struct davinci_spi *dspi = (struct davinci_spi *)data;
506 
507         dspi->wcount = 0;
508 
509         if (!dspi->wcount && !dspi->rcount)
510                 complete(&dspi->done);
511 }
512 
513 /**
514  * davinci_spi_bufs - functions which will handle transfer data
515  * @spi: spi device on which data transfer to be done
516  * @t: spi transfer in which transfer info is filled
517  *
518  * This function will put data to be transferred into data register
519  * of SPI controller and then wait until the completion will be marked
520  * by the IRQ Handler.
521  */
522 static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
523 {
524         struct davinci_spi *dspi;
525         int data_type, ret = -ENOMEM;
526         u32 tx_data, spidat1;
527         u32 errors = 0;
528         struct davinci_spi_config *spicfg;
529         struct davinci_spi_platform_data *pdata;
530         unsigned uninitialized_var(rx_buf_count);
531         void *dummy_buf = NULL;
532         struct scatterlist sg_rx, sg_tx;
533 
534         dspi = spi_master_get_devdata(spi->master);
535         pdata = &dspi->pdata;
536         spicfg = (struct davinci_spi_config *)spi->controller_data;
537         if (!spicfg)
538                 spicfg = &davinci_spi_default_cfg;
539 
540         /* convert len to words based on bits_per_word */
541         data_type = dspi->bytes_per_word[spi->chip_select];
542 
543         dspi->tx = t->tx_buf;
544         dspi->rx = t->rx_buf;
545         dspi->wcount = t->len / data_type;
546         dspi->rcount = dspi->wcount;
547 
548         spidat1 = ioread32(dspi->base + SPIDAT1);
549 
550         clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
551         set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
552 
553         reinit_completion(&dspi->done);
554 
555         if (spicfg->io_type == SPI_IO_TYPE_INTR)
556                 set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
557 
558         if (spicfg->io_type != SPI_IO_TYPE_DMA) {
559                 /* start the transfer */
560                 dspi->wcount--;
561                 tx_data = dspi->get_tx(dspi);
562                 spidat1 &= 0xFFFF0000;
563                 spidat1 |= tx_data & 0xFFFF;
564                 iowrite32(spidat1, dspi->base + SPIDAT1);
565         } else {
566                 struct dma_slave_config dma_rx_conf = {
567                         .direction = DMA_DEV_TO_MEM,
568                         .src_addr = (unsigned long)dspi->pbase + SPIBUF,
569                         .src_addr_width = data_type,
570                         .src_maxburst = 1,
571                 };
572                 struct dma_slave_config dma_tx_conf = {
573                         .direction = DMA_MEM_TO_DEV,
574                         .dst_addr = (unsigned long)dspi->pbase + SPIDAT1,
575                         .dst_addr_width = data_type,
576                         .dst_maxburst = 1,
577                 };
578                 struct dma_async_tx_descriptor *rxdesc;
579                 struct dma_async_tx_descriptor *txdesc;
580                 void *buf;
581 
582                 dummy_buf = kzalloc(t->len, GFP_KERNEL);
583                 if (!dummy_buf)
584                         goto err_alloc_dummy_buf;
585 
586                 dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf);
587                 dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf);
588 
589                 sg_init_table(&sg_rx, 1);
590                 if (!t->rx_buf)
591                         buf = dummy_buf;
592                 else
593                         buf = t->rx_buf;
594                 t->rx_dma = dma_map_single(&spi->dev, buf,
595                                 t->len, DMA_FROM_DEVICE);
596                 if (!t->rx_dma) {
597                         ret = -EFAULT;
598                         goto err_rx_map;
599                 }
600                 sg_dma_address(&sg_rx) = t->rx_dma;
601                 sg_dma_len(&sg_rx) = t->len;
602 
603                 sg_init_table(&sg_tx, 1);
604                 if (!t->tx_buf)
605                         buf = dummy_buf;
606                 else
607                         buf = (void *)t->tx_buf;
608                 t->tx_dma = dma_map_single(&spi->dev, buf,
609                                 t->len, DMA_TO_DEVICE);
610                 if (!t->tx_dma) {
611                         ret = -EFAULT;
612                         goto err_tx_map;
613                 }
614                 sg_dma_address(&sg_tx) = t->tx_dma;
615                 sg_dma_len(&sg_tx) = t->len;
616 
617                 rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx,
618                                 &sg_rx, 1, DMA_DEV_TO_MEM,
619                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
620                 if (!rxdesc)
621                         goto err_desc;
622 
623                 txdesc = dmaengine_prep_slave_sg(dspi->dma_tx,
624                                 &sg_tx, 1, DMA_MEM_TO_DEV,
625                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
626                 if (!txdesc)
627                         goto err_desc;
628 
629                 rxdesc->callback = davinci_spi_dma_rx_callback;
630                 rxdesc->callback_param = (void *)dspi;
631                 txdesc->callback = davinci_spi_dma_tx_callback;
632                 txdesc->callback_param = (void *)dspi;
633 
634                 if (pdata->cshold_bug)
635                         iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
636 
637                 dmaengine_submit(rxdesc);
638                 dmaengine_submit(txdesc);
639 
640                 dma_async_issue_pending(dspi->dma_rx);
641                 dma_async_issue_pending(dspi->dma_tx);
642 
643                 set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
644         }
645 
646         /* Wait for the transfer to complete */
647         if (spicfg->io_type != SPI_IO_TYPE_POLL) {
648                 wait_for_completion_interruptible(&(dspi->done));
649         } else {
650                 while (dspi->rcount > 0 || dspi->wcount > 0) {
651                         errors = davinci_spi_process_events(dspi);
652                         if (errors)
653                                 break;
654                         cpu_relax();
655                 }
656         }
657 
658         clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
659         if (spicfg->io_type == SPI_IO_TYPE_DMA) {
660                 clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
661 
662                 dma_unmap_single(&spi->dev, t->rx_dma,
663                                 t->len, DMA_FROM_DEVICE);
664                 dma_unmap_single(&spi->dev, t->tx_dma,
665                                 t->len, DMA_TO_DEVICE);
666                 kfree(dummy_buf);
667         }
668 
669         clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
670         set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
671 
672         /*
673          * Check for bit error, desync error,parity error,timeout error and
674          * receive overflow errors
675          */
676         if (errors) {
677                 ret = davinci_spi_check_error(dspi, errors);
678                 WARN(!ret, "%s: error reported but no error found!\n",
679                                                         dev_name(&spi->dev));
680                 return ret;
681         }
682 
683         if (dspi->rcount != 0 || dspi->wcount != 0) {
684                 dev_err(&spi->dev, "SPI data transfer error\n");
685                 return -EIO;
686         }
687 
688         return t->len;
689 
690 err_desc:
691         dma_unmap_single(&spi->dev, t->tx_dma, t->len, DMA_TO_DEVICE);
692 err_tx_map:
693         dma_unmap_single(&spi->dev, t->rx_dma, t->len, DMA_FROM_DEVICE);
694 err_rx_map:
695         kfree(dummy_buf);
696 err_alloc_dummy_buf:
697         return ret;
698 }
699 
700 /**
701  * dummy_thread_fn - dummy thread function
702  * @irq: IRQ number for this SPI Master
703  * @context_data: structure for SPI Master controller davinci_spi
704  *
705  * This is to satisfy the request_threaded_irq() API so that the irq
706  * handler is called in interrupt context.
707  */
708 static irqreturn_t dummy_thread_fn(s32 irq, void *data)
709 {
710         return IRQ_HANDLED;
711 }
712 
713 /**
714  * davinci_spi_irq - Interrupt handler for SPI Master Controller
715  * @irq: IRQ number for this SPI Master
716  * @context_data: structure for SPI Master controller davinci_spi
717  *
718  * ISR will determine that interrupt arrives either for READ or WRITE command.
719  * According to command it will do the appropriate action. It will check
720  * transfer length and if it is not zero then dispatch transfer command again.
721  * If transfer length is zero then it will indicate the COMPLETION so that
722  * davinci_spi_bufs function can go ahead.
723  */
724 static irqreturn_t davinci_spi_irq(s32 irq, void *data)
725 {
726         struct davinci_spi *dspi = data;
727         int status;
728 
729         status = davinci_spi_process_events(dspi);
730         if (unlikely(status != 0))
731                 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
732 
733         if ((!dspi->rcount && !dspi->wcount) || status)
734                 complete(&dspi->done);
735 
736         return IRQ_HANDLED;
737 }
738 
739 static int davinci_spi_request_dma(struct davinci_spi *dspi)
740 {
741         dma_cap_mask_t mask;
742         struct device *sdev = dspi->bitbang.master->dev.parent;
743         int r;
744 
745         dma_cap_zero(mask);
746         dma_cap_set(DMA_SLAVE, mask);
747 
748         dspi->dma_rx = dma_request_channel(mask, edma_filter_fn,
749                                            &dspi->dma_rx_chnum);
750         if (!dspi->dma_rx) {
751                 dev_err(sdev, "request RX DMA channel failed\n");
752                 r = -ENODEV;
753                 goto rx_dma_failed;
754         }
755 
756         dspi->dma_tx = dma_request_channel(mask, edma_filter_fn,
757                                            &dspi->dma_tx_chnum);
758         if (!dspi->dma_tx) {
759                 dev_err(sdev, "request TX DMA channel failed\n");
760                 r = -ENODEV;
761                 goto tx_dma_failed;
762         }
763 
764         return 0;
765 
766 tx_dma_failed:
767         dma_release_channel(dspi->dma_rx);
768 rx_dma_failed:
769         return r;
770 }
771 
772 #if defined(CONFIG_OF)
773 static const struct of_device_id davinci_spi_of_match[] = {
774         {
775                 .compatible = "ti,dm6441-spi",
776         },
777         {
778                 .compatible = "ti,da830-spi",
779                 .data = (void *)SPI_VERSION_2,
780         },
781         { },
782 };
783 MODULE_DEVICE_TABLE(of, davinci_spi_of_match);
784 
785 /**
786  * spi_davinci_get_pdata - Get platform data from DTS binding
787  * @pdev: ptr to platform data
788  * @dspi: ptr to driver data
789  *
790  * Parses and populates pdata in dspi from device tree bindings.
791  *
792  * NOTE: Not all platform data params are supported currently.
793  */
794 static int spi_davinci_get_pdata(struct platform_device *pdev,
795                         struct davinci_spi *dspi)
796 {
797         struct device_node *node = pdev->dev.of_node;
798         struct davinci_spi_platform_data *pdata;
799         unsigned int num_cs, intr_line = 0;
800         const struct of_device_id *match;
801 
802         pdata = &dspi->pdata;
803 
804         pdata->version = SPI_VERSION_1;
805         match = of_match_device(davinci_spi_of_match, &pdev->dev);
806         if (!match)
807                 return -ENODEV;
808 
809         /* match data has the SPI version number for SPI_VERSION_2 */
810         if (match->data == (void *)SPI_VERSION_2)
811                 pdata->version = SPI_VERSION_2;
812 
813         /*
814          * default num_cs is 1 and all chipsel are internal to the chip
815          * indicated by chip_sel being NULL. GPIO based CS is not
816          * supported yet in DT bindings.
817          */
818         num_cs = 1;
819         of_property_read_u32(node, "num-cs", &num_cs);
820         pdata->num_chipselect = num_cs;
821         of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line);
822         pdata->intr_line = intr_line;
823         return 0;
824 }
825 #else
826 static struct davinci_spi_platform_data
827         *spi_davinci_get_pdata(struct platform_device *pdev,
828                 struct davinci_spi *dspi)
829 {
830         return -ENODEV;
831 }
832 #endif
833 
834 /**
835  * davinci_spi_probe - probe function for SPI Master Controller
836  * @pdev: platform_device structure which contains plateform specific data
837  *
838  * According to Linux Device Model this function will be invoked by Linux
839  * with platform_device struct which contains the device specific info.
840  * This function will map the SPI controller's memory, register IRQ,
841  * Reset SPI controller and setting its registers to default value.
842  * It will invoke spi_bitbang_start to create work queue so that client driver
843  * can register transfer method to work queue.
844  */
845 static int davinci_spi_probe(struct platform_device *pdev)
846 {
847         struct spi_master *master;
848         struct davinci_spi *dspi;
849         struct davinci_spi_platform_data *pdata;
850         struct resource *r;
851         resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
852         resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
853         int i = 0, ret = 0;
854         u32 spipc0;
855 
856         master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
857         if (master == NULL) {
858                 ret = -ENOMEM;
859                 goto err;
860         }
861 
862         platform_set_drvdata(pdev, master);
863 
864         dspi = spi_master_get_devdata(master);
865 
866         if (dev_get_platdata(&pdev->dev)) {
867                 pdata = dev_get_platdata(&pdev->dev);
868                 dspi->pdata = *pdata;
869         } else {
870                 /* update dspi pdata with that from the DT */
871                 ret = spi_davinci_get_pdata(pdev, dspi);
872                 if (ret < 0)
873                         goto free_master;
874         }
875 
876         /* pdata in dspi is now updated and point pdata to that */
877         pdata = &dspi->pdata;
878 
879         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
880         if (r == NULL) {
881                 ret = -ENOENT;
882                 goto free_master;
883         }
884 
885         dspi->pbase = r->start;
886 
887         dspi->base = devm_ioremap_resource(&pdev->dev, r);
888         if (IS_ERR(dspi->base)) {
889                 ret = PTR_ERR(dspi->base);
890                 goto free_master;
891         }
892 
893         dspi->irq = platform_get_irq(pdev, 0);
894         if (dspi->irq <= 0) {
895                 ret = -EINVAL;
896                 goto free_master;
897         }
898 
899         ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq,
900                                 dummy_thread_fn, 0, dev_name(&pdev->dev), dspi);
901         if (ret)
902                 goto free_master;
903 
904         dspi->bitbang.master = master;
905 
906         dspi->clk = devm_clk_get(&pdev->dev, NULL);
907         if (IS_ERR(dspi->clk)) {
908                 ret = -ENODEV;
909                 goto free_master;
910         }
911         clk_prepare_enable(dspi->clk);
912 
913         master->dev.of_node = pdev->dev.of_node;
914         master->bus_num = pdev->id;
915         master->num_chipselect = pdata->num_chipselect;
916         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16);
917         master->setup = davinci_spi_setup;
918 
919         dspi->bitbang.chipselect = davinci_spi_chipselect;
920         dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
921 
922         dspi->version = pdata->version;
923 
924         dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
925         if (dspi->version == SPI_VERSION_2)
926                 dspi->bitbang.flags |= SPI_READY;
927 
928         r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
929         if (r)
930                 dma_rx_chan = r->start;
931         r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
932         if (r)
933                 dma_tx_chan = r->start;
934 
935         dspi->bitbang.txrx_bufs = davinci_spi_bufs;
936         if (dma_rx_chan != SPI_NO_RESOURCE &&
937             dma_tx_chan != SPI_NO_RESOURCE) {
938                 dspi->dma_rx_chnum = dma_rx_chan;
939                 dspi->dma_tx_chnum = dma_tx_chan;
940 
941                 ret = davinci_spi_request_dma(dspi);
942                 if (ret)
943                         goto free_clk;
944 
945                 dev_info(&pdev->dev, "DMA: supported\n");
946                 dev_info(&pdev->dev, "DMA: RX channel: %pa, TX channel: %pa, "
947                                 "event queue: %d\n", &dma_rx_chan, &dma_tx_chan,
948                                 pdata->dma_event_q);
949         }
950 
951         dspi->get_rx = davinci_spi_rx_buf_u8;
952         dspi->get_tx = davinci_spi_tx_buf_u8;
953 
954         init_completion(&dspi->done);
955 
956         /* Reset In/OUT SPI module */
957         iowrite32(0, dspi->base + SPIGCR0);
958         udelay(100);
959         iowrite32(1, dspi->base + SPIGCR0);
960 
961         /* Set up SPIPC0.  CS and ENA init is done in davinci_spi_setup */
962         spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
963         iowrite32(spipc0, dspi->base + SPIPC0);
964 
965         /* initialize chip selects */
966         if (pdata->chip_sel) {
967                 for (i = 0; i < pdata->num_chipselect; i++) {
968                         if (pdata->chip_sel[i] != SPI_INTERN_CS)
969                                 gpio_direction_output(pdata->chip_sel[i], 1);
970                 }
971         }
972 
973         if (pdata->intr_line)
974                 iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);
975         else
976                 iowrite32(SPI_INTLVL_0, dspi->base + SPILVL);
977 
978         iowrite32(CS_DEFAULT, dspi->base + SPIDEF);
979 
980         /* master mode default */
981         set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
982         set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
983         set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
984 
985         ret = spi_bitbang_start(&dspi->bitbang);
986         if (ret)
987                 goto free_dma;
988 
989         dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base);
990 
991         return ret;
992 
993 free_dma:
994         dma_release_channel(dspi->dma_rx);
995         dma_release_channel(dspi->dma_tx);
996 free_clk:
997         clk_disable_unprepare(dspi->clk);
998 free_master:
999         spi_master_put(master);
1000 err:
1001         return ret;
1002 }
1003 
1004 /**
1005  * davinci_spi_remove - remove function for SPI Master Controller
1006  * @pdev: platform_device structure which contains plateform specific data
1007  *
1008  * This function will do the reverse action of davinci_spi_probe function
1009  * It will free the IRQ and SPI controller's memory region.
1010  * It will also call spi_bitbang_stop to destroy the work queue which was
1011  * created by spi_bitbang_start.
1012  */
1013 static int davinci_spi_remove(struct platform_device *pdev)
1014 {
1015         struct davinci_spi *dspi;
1016         struct spi_master *master;
1017 
1018         master = platform_get_drvdata(pdev);
1019         dspi = spi_master_get_devdata(master);
1020 
1021         spi_bitbang_stop(&dspi->bitbang);
1022 
1023         clk_disable_unprepare(dspi->clk);
1024         spi_master_put(master);
1025 
1026         return 0;
1027 }
1028 
1029 static struct platform_driver davinci_spi_driver = {
1030         .driver = {
1031                 .name = "spi_davinci",
1032                 .owner = THIS_MODULE,
1033                 .of_match_table = of_match_ptr(davinci_spi_of_match),
1034         },
1035         .probe = davinci_spi_probe,
1036         .remove = davinci_spi_remove,
1037 };
1038 module_platform_driver(davinci_spi_driver);
1039 
1040 MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1041 MODULE_LICENSE("GPL");
1042 

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