Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/spi/spi-coldfire-qspi.c

  1 /*
  2  * Freescale/Motorola Coldfire Queued SPI driver
  3  *
  4  * Copyright 2010 Steven King <sfking@fdwdc.com>
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License as published by
  8  * the Free Software Foundation; either version 2 of the License, or
  9  * (at your option) any later version.
 10  *
 11  * This program is distributed in the hope that it will be useful,
 12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14  * GNU General Public License for more details.
 15  *
 16  * You should have received a copy of the GNU General Public License
 17  * along with this program; if not, write to the Free Software
 18  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA
 19  *
 20 */
 21 
 22 #include <linux/kernel.h>
 23 #include <linux/module.h>
 24 #include <linux/interrupt.h>
 25 #include <linux/errno.h>
 26 #include <linux/platform_device.h>
 27 #include <linux/sched.h>
 28 #include <linux/delay.h>
 29 #include <linux/io.h>
 30 #include <linux/clk.h>
 31 #include <linux/err.h>
 32 #include <linux/spi/spi.h>
 33 #include <linux/pm_runtime.h>
 34 
 35 #include <asm/coldfire.h>
 36 #include <asm/mcfsim.h>
 37 #include <asm/mcfqspi.h>
 38 
 39 #define DRIVER_NAME "mcfqspi"
 40 
 41 #define MCFQSPI_BUSCLK                  (MCF_BUSCLK / 2)
 42 
 43 #define MCFQSPI_QMR                     0x00
 44 #define         MCFQSPI_QMR_MSTR        0x8000
 45 #define         MCFQSPI_QMR_CPOL        0x0200
 46 #define         MCFQSPI_QMR_CPHA        0x0100
 47 #define MCFQSPI_QDLYR                   0x04
 48 #define         MCFQSPI_QDLYR_SPE       0x8000
 49 #define MCFQSPI_QWR                     0x08
 50 #define         MCFQSPI_QWR_HALT        0x8000
 51 #define         MCFQSPI_QWR_WREN        0x4000
 52 #define         MCFQSPI_QWR_CSIV        0x1000
 53 #define MCFQSPI_QIR                     0x0C
 54 #define         MCFQSPI_QIR_WCEFB       0x8000
 55 #define         MCFQSPI_QIR_ABRTB       0x4000
 56 #define         MCFQSPI_QIR_ABRTL       0x1000
 57 #define         MCFQSPI_QIR_WCEFE       0x0800
 58 #define         MCFQSPI_QIR_ABRTE       0x0400
 59 #define         MCFQSPI_QIR_SPIFE       0x0100
 60 #define         MCFQSPI_QIR_WCEF        0x0008
 61 #define         MCFQSPI_QIR_ABRT        0x0004
 62 #define         MCFQSPI_QIR_SPIF        0x0001
 63 #define MCFQSPI_QAR                     0x010
 64 #define         MCFQSPI_QAR_TXBUF       0x00
 65 #define         MCFQSPI_QAR_RXBUF       0x10
 66 #define         MCFQSPI_QAR_CMDBUF      0x20
 67 #define MCFQSPI_QDR                     0x014
 68 #define MCFQSPI_QCR                     0x014
 69 #define         MCFQSPI_QCR_CONT        0x8000
 70 #define         MCFQSPI_QCR_BITSE       0x4000
 71 #define         MCFQSPI_QCR_DT          0x2000
 72 
 73 struct mcfqspi {
 74         void __iomem *iobase;
 75         int irq;
 76         struct clk *clk;
 77         struct mcfqspi_cs_control *cs_control;
 78 
 79         wait_queue_head_t waitq;
 80 };
 81 
 82 static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val)
 83 {
 84         writew(val, mcfqspi->iobase + MCFQSPI_QMR);
 85 }
 86 
 87 static void mcfqspi_wr_qdlyr(struct mcfqspi *mcfqspi, u16 val)
 88 {
 89         writew(val, mcfqspi->iobase + MCFQSPI_QDLYR);
 90 }
 91 
 92 static u16 mcfqspi_rd_qdlyr(struct mcfqspi *mcfqspi)
 93 {
 94         return readw(mcfqspi->iobase + MCFQSPI_QDLYR);
 95 }
 96 
 97 static void mcfqspi_wr_qwr(struct mcfqspi *mcfqspi, u16 val)
 98 {
 99         writew(val, mcfqspi->iobase + MCFQSPI_QWR);
100 }
101 
102 static void mcfqspi_wr_qir(struct mcfqspi *mcfqspi, u16 val)
103 {
104         writew(val, mcfqspi->iobase + MCFQSPI_QIR);
105 }
106 
107 static void mcfqspi_wr_qar(struct mcfqspi *mcfqspi, u16 val)
108 {
109         writew(val, mcfqspi->iobase + MCFQSPI_QAR);
110 }
111 
112 static void mcfqspi_wr_qdr(struct mcfqspi *mcfqspi, u16 val)
113 {
114         writew(val, mcfqspi->iobase + MCFQSPI_QDR);
115 }
116 
117 static u16 mcfqspi_rd_qdr(struct mcfqspi *mcfqspi)
118 {
119         return readw(mcfqspi->iobase + MCFQSPI_QDR);
120 }
121 
122 static void mcfqspi_cs_select(struct mcfqspi *mcfqspi, u8 chip_select,
123                             bool cs_high)
124 {
125         mcfqspi->cs_control->select(mcfqspi->cs_control, chip_select, cs_high);
126 }
127 
128 static void mcfqspi_cs_deselect(struct mcfqspi *mcfqspi, u8 chip_select,
129                                 bool cs_high)
130 {
131         mcfqspi->cs_control->deselect(mcfqspi->cs_control, chip_select, cs_high);
132 }
133 
134 static int mcfqspi_cs_setup(struct mcfqspi *mcfqspi)
135 {
136         return (mcfqspi->cs_control->setup) ?
137                 mcfqspi->cs_control->setup(mcfqspi->cs_control) : 0;
138 }
139 
140 static void mcfqspi_cs_teardown(struct mcfqspi *mcfqspi)
141 {
142         if (mcfqspi->cs_control->teardown)
143                 mcfqspi->cs_control->teardown(mcfqspi->cs_control);
144 }
145 
146 static u8 mcfqspi_qmr_baud(u32 speed_hz)
147 {
148         return clamp((MCFQSPI_BUSCLK + speed_hz - 1) / speed_hz, 2u, 255u);
149 }
150 
151 static bool mcfqspi_qdlyr_spe(struct mcfqspi *mcfqspi)
152 {
153         return mcfqspi_rd_qdlyr(mcfqspi) & MCFQSPI_QDLYR_SPE;
154 }
155 
156 static irqreturn_t mcfqspi_irq_handler(int this_irq, void *dev_id)
157 {
158         struct mcfqspi *mcfqspi = dev_id;
159 
160         /* clear interrupt */
161         mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE | MCFQSPI_QIR_SPIF);
162         wake_up(&mcfqspi->waitq);
163 
164         return IRQ_HANDLED;
165 }
166 
167 static void mcfqspi_transfer_msg8(struct mcfqspi *mcfqspi, unsigned count,
168                                   const u8 *txbuf, u8 *rxbuf)
169 {
170         unsigned i, n, offset = 0;
171 
172         n = min(count, 16u);
173 
174         mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
175         for (i = 0; i < n; ++i)
176                 mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);
177 
178         mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
179         if (txbuf)
180                 for (i = 0; i < n; ++i)
181                         mcfqspi_wr_qdr(mcfqspi, *txbuf++);
182         else
183                 for (i = 0; i < count; ++i)
184                         mcfqspi_wr_qdr(mcfqspi, 0);
185 
186         count -= n;
187         if (count) {
188                 u16 qwr = 0xf08;
189                 mcfqspi_wr_qwr(mcfqspi, 0x700);
190                 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
191 
192                 do {
193                         wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
194                         mcfqspi_wr_qwr(mcfqspi, qwr);
195                         mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
196                         if (rxbuf) {
197                                 mcfqspi_wr_qar(mcfqspi,
198                                                MCFQSPI_QAR_RXBUF + offset);
199                                 for (i = 0; i < 8; ++i)
200                                         *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
201                         }
202                         n = min(count, 8u);
203                         if (txbuf) {
204                                 mcfqspi_wr_qar(mcfqspi,
205                                                MCFQSPI_QAR_TXBUF + offset);
206                                 for (i = 0; i < n; ++i)
207                                         mcfqspi_wr_qdr(mcfqspi, *txbuf++);
208                         }
209                         qwr = (offset ? 0x808 : 0) + ((n - 1) << 8);
210                         offset ^= 8;
211                         count -= n;
212                 } while (count);
213                 wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
214                 mcfqspi_wr_qwr(mcfqspi, qwr);
215                 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
216                 if (rxbuf) {
217                         mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
218                         for (i = 0; i < 8; ++i)
219                                 *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
220                         offset ^= 8;
221                 }
222         } else {
223                 mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
224                 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
225         }
226         wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
227         if (rxbuf) {
228                 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
229                 for (i = 0; i < n; ++i)
230                         *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
231         }
232 }
233 
234 static void mcfqspi_transfer_msg16(struct mcfqspi *mcfqspi, unsigned count,
235                                    const u16 *txbuf, u16 *rxbuf)
236 {
237         unsigned i, n, offset = 0;
238 
239         n = min(count, 16u);
240 
241         mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
242         for (i = 0; i < n; ++i)
243                 mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);
244 
245         mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
246         if (txbuf)
247                 for (i = 0; i < n; ++i)
248                         mcfqspi_wr_qdr(mcfqspi, *txbuf++);
249         else
250                 for (i = 0; i < count; ++i)
251                         mcfqspi_wr_qdr(mcfqspi, 0);
252 
253         count -= n;
254         if (count) {
255                 u16 qwr = 0xf08;
256                 mcfqspi_wr_qwr(mcfqspi, 0x700);
257                 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
258 
259                 do {
260                         wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
261                         mcfqspi_wr_qwr(mcfqspi, qwr);
262                         mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
263                         if (rxbuf) {
264                                 mcfqspi_wr_qar(mcfqspi,
265                                                MCFQSPI_QAR_RXBUF + offset);
266                                 for (i = 0; i < 8; ++i)
267                                         *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
268                         }
269                         n = min(count, 8u);
270                         if (txbuf) {
271                                 mcfqspi_wr_qar(mcfqspi,
272                                                MCFQSPI_QAR_TXBUF + offset);
273                                 for (i = 0; i < n; ++i)
274                                         mcfqspi_wr_qdr(mcfqspi, *txbuf++);
275                         }
276                         qwr = (offset ? 0x808 : 0x000) + ((n - 1) << 8);
277                         offset ^= 8;
278                         count -= n;
279                 } while (count);
280                 wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
281                 mcfqspi_wr_qwr(mcfqspi, qwr);
282                 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
283                 if (rxbuf) {
284                         mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
285                         for (i = 0; i < 8; ++i)
286                                 *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
287                         offset ^= 8;
288                 }
289         } else {
290                 mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
291                 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
292         }
293         wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
294         if (rxbuf) {
295                 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
296                 for (i = 0; i < n; ++i)
297                         *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
298         }
299 }
300 
301 static void mcfqspi_set_cs(struct spi_device *spi, bool enable)
302 {
303         struct mcfqspi *mcfqspi = spi_master_get_devdata(spi->master);
304         bool cs_high = spi->mode & SPI_CS_HIGH;
305 
306         if (enable)
307                 mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high);
308         else
309                 mcfqspi_cs_deselect(mcfqspi, spi->chip_select, cs_high);
310 }
311 
312 static int mcfqspi_transfer_one(struct spi_master *master,
313                                 struct spi_device *spi,
314                                 struct spi_transfer *t)
315 {
316         struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
317         u16 qmr = MCFQSPI_QMR_MSTR;
318 
319         qmr |= t->bits_per_word << 10;
320         if (spi->mode & SPI_CPHA)
321                 qmr |= MCFQSPI_QMR_CPHA;
322         if (spi->mode & SPI_CPOL)
323                 qmr |= MCFQSPI_QMR_CPOL;
324         qmr |= mcfqspi_qmr_baud(t->speed_hz);
325         mcfqspi_wr_qmr(mcfqspi, qmr);
326 
327         mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE);
328         if (t->bits_per_word == 8)
329                 mcfqspi_transfer_msg8(mcfqspi, t->len, t->tx_buf, t->rx_buf);
330         else
331                 mcfqspi_transfer_msg16(mcfqspi, t->len / 2, t->tx_buf,
332                                        t->rx_buf);
333         mcfqspi_wr_qir(mcfqspi, 0);
334 
335         return 0;
336 }
337 
338 static int mcfqspi_setup(struct spi_device *spi)
339 {
340         mcfqspi_cs_deselect(spi_master_get_devdata(spi->master),
341                             spi->chip_select, spi->mode & SPI_CS_HIGH);
342 
343         dev_dbg(&spi->dev,
344                         "bits per word %d, chip select %d, speed %d KHz\n",
345                         spi->bits_per_word, spi->chip_select,
346                         (MCFQSPI_BUSCLK / mcfqspi_qmr_baud(spi->max_speed_hz))
347                         / 1000);
348 
349         return 0;
350 }
351 
352 static int mcfqspi_probe(struct platform_device *pdev)
353 {
354         struct spi_master *master;
355         struct mcfqspi *mcfqspi;
356         struct resource *res;
357         struct mcfqspi_platform_data *pdata;
358         int status;
359 
360         pdata = dev_get_platdata(&pdev->dev);
361         if (!pdata) {
362                 dev_dbg(&pdev->dev, "platform data is missing\n");
363                 return -ENOENT;
364         }
365 
366         if (!pdata->cs_control) {
367                 dev_dbg(&pdev->dev, "pdata->cs_control is NULL\n");
368                 return -EINVAL;
369         }
370 
371         master = spi_alloc_master(&pdev->dev, sizeof(*mcfqspi));
372         if (master == NULL) {
373                 dev_dbg(&pdev->dev, "spi_alloc_master failed\n");
374                 return -ENOMEM;
375         }
376 
377         mcfqspi = spi_master_get_devdata(master);
378 
379         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
380         mcfqspi->iobase = devm_ioremap_resource(&pdev->dev, res);
381         if (IS_ERR(mcfqspi->iobase)) {
382                 status = PTR_ERR(mcfqspi->iobase);
383                 goto fail0;
384         }
385 
386         mcfqspi->irq = platform_get_irq(pdev, 0);
387         if (mcfqspi->irq < 0) {
388                 dev_dbg(&pdev->dev, "platform_get_irq failed\n");
389                 status = -ENXIO;
390                 goto fail0;
391         }
392 
393         status = devm_request_irq(&pdev->dev, mcfqspi->irq, mcfqspi_irq_handler,
394                                 0, pdev->name, mcfqspi);
395         if (status) {
396                 dev_dbg(&pdev->dev, "request_irq failed\n");
397                 goto fail0;
398         }
399 
400         mcfqspi->clk = devm_clk_get(&pdev->dev, "qspi_clk");
401         if (IS_ERR(mcfqspi->clk)) {
402                 dev_dbg(&pdev->dev, "clk_get failed\n");
403                 status = PTR_ERR(mcfqspi->clk);
404                 goto fail0;
405         }
406         clk_enable(mcfqspi->clk);
407 
408         master->bus_num = pdata->bus_num;
409         master->num_chipselect = pdata->num_chipselect;
410 
411         mcfqspi->cs_control = pdata->cs_control;
412         status = mcfqspi_cs_setup(mcfqspi);
413         if (status) {
414                 dev_dbg(&pdev->dev, "error initializing cs_control\n");
415                 goto fail1;
416         }
417 
418         init_waitqueue_head(&mcfqspi->waitq);
419 
420         master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA;
421         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
422         master->setup = mcfqspi_setup;
423         master->set_cs = mcfqspi_set_cs;
424         master->transfer_one = mcfqspi_transfer_one;
425         master->auto_runtime_pm = true;
426 
427         platform_set_drvdata(pdev, master);
428 
429         status = devm_spi_register_master(&pdev->dev, master);
430         if (status) {
431                 dev_dbg(&pdev->dev, "spi_register_master failed\n");
432                 goto fail2;
433         }
434         pm_runtime_enable(&pdev->dev);
435 
436         dev_info(&pdev->dev, "Coldfire QSPI bus driver\n");
437 
438         return 0;
439 
440 fail2:
441         mcfqspi_cs_teardown(mcfqspi);
442 fail1:
443         clk_disable(mcfqspi->clk);
444 fail0:
445         spi_master_put(master);
446 
447         dev_dbg(&pdev->dev, "Coldfire QSPI probe failed\n");
448 
449         return status;
450 }
451 
452 static int mcfqspi_remove(struct platform_device *pdev)
453 {
454         struct spi_master *master = platform_get_drvdata(pdev);
455         struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
456 
457         pm_runtime_disable(&pdev->dev);
458         /* disable the hardware (set the baud rate to 0) */
459         mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR);
460 
461         mcfqspi_cs_teardown(mcfqspi);
462         clk_disable(mcfqspi->clk);
463 
464         return 0;
465 }
466 
467 #ifdef CONFIG_PM_SLEEP
468 static int mcfqspi_suspend(struct device *dev)
469 {
470         struct spi_master *master = dev_get_drvdata(dev);
471         struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
472         int ret;
473 
474         ret = spi_master_suspend(master);
475         if (ret)
476                 return ret;
477 
478         clk_disable(mcfqspi->clk);
479 
480         return 0;
481 }
482 
483 static int mcfqspi_resume(struct device *dev)
484 {
485         struct spi_master *master = dev_get_drvdata(dev);
486         struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
487 
488         clk_enable(mcfqspi->clk);
489 
490         return spi_master_resume(master);
491 }
492 #endif
493 
494 #ifdef CONFIG_PM_RUNTIME
495 static int mcfqspi_runtime_suspend(struct device *dev)
496 {
497         struct spi_master *master = dev_get_drvdata(dev);
498         struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
499 
500         clk_disable(mcfqspi->clk);
501 
502         return 0;
503 }
504 
505 static int mcfqspi_runtime_resume(struct device *dev)
506 {
507         struct spi_master *master = dev_get_drvdata(dev);
508         struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
509 
510         clk_enable(mcfqspi->clk);
511 
512         return 0;
513 }
514 #endif
515 
516 static const struct dev_pm_ops mcfqspi_pm = {
517         SET_SYSTEM_SLEEP_PM_OPS(mcfqspi_suspend, mcfqspi_resume)
518         SET_RUNTIME_PM_OPS(mcfqspi_runtime_suspend, mcfqspi_runtime_resume,
519                         NULL)
520 };
521 
522 static struct platform_driver mcfqspi_driver = {
523         .driver.name    = DRIVER_NAME,
524         .driver.owner   = THIS_MODULE,
525         .driver.pm      = &mcfqspi_pm,
526         .probe          = mcfqspi_probe,
527         .remove         = mcfqspi_remove,
528 };
529 module_platform_driver(mcfqspi_driver);
530 
531 MODULE_AUTHOR("Steven King <sfking@fdwdc.com>");
532 MODULE_DESCRIPTION("Coldfire QSPI Controller Driver");
533 MODULE_LICENSE("GPL");
534 MODULE_ALIAS("platform:" DRIVER_NAME);
535 

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