Version:  2.0.40 2.2.26 2.4.37 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1

Linux/drivers/spi/spi-coldfire-qspi.c

  1 /*
  2  * Freescale/Motorola Coldfire Queued SPI driver
  3  *
  4  * Copyright 2010 Steven King <sfking@fdwdc.com>
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License as published by
  8  * the Free Software Foundation; either version 2 of the License, or
  9  * (at your option) any later version.
 10  *
 11  * This program is distributed in the hope that it will be useful,
 12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14  * GNU General Public License for more details.
 15 */
 16 
 17 #include <linux/kernel.h>
 18 #include <linux/module.h>
 19 #include <linux/interrupt.h>
 20 #include <linux/errno.h>
 21 #include <linux/platform_device.h>
 22 #include <linux/sched.h>
 23 #include <linux/delay.h>
 24 #include <linux/io.h>
 25 #include <linux/clk.h>
 26 #include <linux/err.h>
 27 #include <linux/spi/spi.h>
 28 #include <linux/pm_runtime.h>
 29 
 30 #include <asm/coldfire.h>
 31 #include <asm/mcfsim.h>
 32 #include <asm/mcfqspi.h>
 33 
 34 #define DRIVER_NAME "mcfqspi"
 35 
 36 #define MCFQSPI_BUSCLK                  (MCF_BUSCLK / 2)
 37 
 38 #define MCFQSPI_QMR                     0x00
 39 #define         MCFQSPI_QMR_MSTR        0x8000
 40 #define         MCFQSPI_QMR_CPOL        0x0200
 41 #define         MCFQSPI_QMR_CPHA        0x0100
 42 #define MCFQSPI_QDLYR                   0x04
 43 #define         MCFQSPI_QDLYR_SPE       0x8000
 44 #define MCFQSPI_QWR                     0x08
 45 #define         MCFQSPI_QWR_HALT        0x8000
 46 #define         MCFQSPI_QWR_WREN        0x4000
 47 #define         MCFQSPI_QWR_CSIV        0x1000
 48 #define MCFQSPI_QIR                     0x0C
 49 #define         MCFQSPI_QIR_WCEFB       0x8000
 50 #define         MCFQSPI_QIR_ABRTB       0x4000
 51 #define         MCFQSPI_QIR_ABRTL       0x1000
 52 #define         MCFQSPI_QIR_WCEFE       0x0800
 53 #define         MCFQSPI_QIR_ABRTE       0x0400
 54 #define         MCFQSPI_QIR_SPIFE       0x0100
 55 #define         MCFQSPI_QIR_WCEF        0x0008
 56 #define         MCFQSPI_QIR_ABRT        0x0004
 57 #define         MCFQSPI_QIR_SPIF        0x0001
 58 #define MCFQSPI_QAR                     0x010
 59 #define         MCFQSPI_QAR_TXBUF       0x00
 60 #define         MCFQSPI_QAR_RXBUF       0x10
 61 #define         MCFQSPI_QAR_CMDBUF      0x20
 62 #define MCFQSPI_QDR                     0x014
 63 #define MCFQSPI_QCR                     0x014
 64 #define         MCFQSPI_QCR_CONT        0x8000
 65 #define         MCFQSPI_QCR_BITSE       0x4000
 66 #define         MCFQSPI_QCR_DT          0x2000
 67 
 68 struct mcfqspi {
 69         void __iomem *iobase;
 70         int irq;
 71         struct clk *clk;
 72         struct mcfqspi_cs_control *cs_control;
 73 
 74         wait_queue_head_t waitq;
 75 };
 76 
 77 static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val)
 78 {
 79         writew(val, mcfqspi->iobase + MCFQSPI_QMR);
 80 }
 81 
 82 static void mcfqspi_wr_qdlyr(struct mcfqspi *mcfqspi, u16 val)
 83 {
 84         writew(val, mcfqspi->iobase + MCFQSPI_QDLYR);
 85 }
 86 
 87 static u16 mcfqspi_rd_qdlyr(struct mcfqspi *mcfqspi)
 88 {
 89         return readw(mcfqspi->iobase + MCFQSPI_QDLYR);
 90 }
 91 
 92 static void mcfqspi_wr_qwr(struct mcfqspi *mcfqspi, u16 val)
 93 {
 94         writew(val, mcfqspi->iobase + MCFQSPI_QWR);
 95 }
 96 
 97 static void mcfqspi_wr_qir(struct mcfqspi *mcfqspi, u16 val)
 98 {
 99         writew(val, mcfqspi->iobase + MCFQSPI_QIR);
100 }
101 
102 static void mcfqspi_wr_qar(struct mcfqspi *mcfqspi, u16 val)
103 {
104         writew(val, mcfqspi->iobase + MCFQSPI_QAR);
105 }
106 
107 static void mcfqspi_wr_qdr(struct mcfqspi *mcfqspi, u16 val)
108 {
109         writew(val, mcfqspi->iobase + MCFQSPI_QDR);
110 }
111 
112 static u16 mcfqspi_rd_qdr(struct mcfqspi *mcfqspi)
113 {
114         return readw(mcfqspi->iobase + MCFQSPI_QDR);
115 }
116 
117 static void mcfqspi_cs_select(struct mcfqspi *mcfqspi, u8 chip_select,
118                             bool cs_high)
119 {
120         mcfqspi->cs_control->select(mcfqspi->cs_control, chip_select, cs_high);
121 }
122 
123 static void mcfqspi_cs_deselect(struct mcfqspi *mcfqspi, u8 chip_select,
124                                 bool cs_high)
125 {
126         mcfqspi->cs_control->deselect(mcfqspi->cs_control, chip_select, cs_high);
127 }
128 
129 static int mcfqspi_cs_setup(struct mcfqspi *mcfqspi)
130 {
131         return (mcfqspi->cs_control->setup) ?
132                 mcfqspi->cs_control->setup(mcfqspi->cs_control) : 0;
133 }
134 
135 static void mcfqspi_cs_teardown(struct mcfqspi *mcfqspi)
136 {
137         if (mcfqspi->cs_control->teardown)
138                 mcfqspi->cs_control->teardown(mcfqspi->cs_control);
139 }
140 
141 static u8 mcfqspi_qmr_baud(u32 speed_hz)
142 {
143         return clamp((MCFQSPI_BUSCLK + speed_hz - 1) / speed_hz, 2u, 255u);
144 }
145 
146 static bool mcfqspi_qdlyr_spe(struct mcfqspi *mcfqspi)
147 {
148         return mcfqspi_rd_qdlyr(mcfqspi) & MCFQSPI_QDLYR_SPE;
149 }
150 
151 static irqreturn_t mcfqspi_irq_handler(int this_irq, void *dev_id)
152 {
153         struct mcfqspi *mcfqspi = dev_id;
154 
155         /* clear interrupt */
156         mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE | MCFQSPI_QIR_SPIF);
157         wake_up(&mcfqspi->waitq);
158 
159         return IRQ_HANDLED;
160 }
161 
162 static void mcfqspi_transfer_msg8(struct mcfqspi *mcfqspi, unsigned count,
163                                   const u8 *txbuf, u8 *rxbuf)
164 {
165         unsigned i, n, offset = 0;
166 
167         n = min(count, 16u);
168 
169         mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
170         for (i = 0; i < n; ++i)
171                 mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);
172 
173         mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
174         if (txbuf)
175                 for (i = 0; i < n; ++i)
176                         mcfqspi_wr_qdr(mcfqspi, *txbuf++);
177         else
178                 for (i = 0; i < count; ++i)
179                         mcfqspi_wr_qdr(mcfqspi, 0);
180 
181         count -= n;
182         if (count) {
183                 u16 qwr = 0xf08;
184                 mcfqspi_wr_qwr(mcfqspi, 0x700);
185                 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
186 
187                 do {
188                         wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
189                         mcfqspi_wr_qwr(mcfqspi, qwr);
190                         mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
191                         if (rxbuf) {
192                                 mcfqspi_wr_qar(mcfqspi,
193                                                MCFQSPI_QAR_RXBUF + offset);
194                                 for (i = 0; i < 8; ++i)
195                                         *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
196                         }
197                         n = min(count, 8u);
198                         if (txbuf) {
199                                 mcfqspi_wr_qar(mcfqspi,
200                                                MCFQSPI_QAR_TXBUF + offset);
201                                 for (i = 0; i < n; ++i)
202                                         mcfqspi_wr_qdr(mcfqspi, *txbuf++);
203                         }
204                         qwr = (offset ? 0x808 : 0) + ((n - 1) << 8);
205                         offset ^= 8;
206                         count -= n;
207                 } while (count);
208                 wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
209                 mcfqspi_wr_qwr(mcfqspi, qwr);
210                 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
211                 if (rxbuf) {
212                         mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
213                         for (i = 0; i < 8; ++i)
214                                 *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
215                         offset ^= 8;
216                 }
217         } else {
218                 mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
219                 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
220         }
221         wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
222         if (rxbuf) {
223                 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
224                 for (i = 0; i < n; ++i)
225                         *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
226         }
227 }
228 
229 static void mcfqspi_transfer_msg16(struct mcfqspi *mcfqspi, unsigned count,
230                                    const u16 *txbuf, u16 *rxbuf)
231 {
232         unsigned i, n, offset = 0;
233 
234         n = min(count, 16u);
235 
236         mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
237         for (i = 0; i < n; ++i)
238                 mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);
239 
240         mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
241         if (txbuf)
242                 for (i = 0; i < n; ++i)
243                         mcfqspi_wr_qdr(mcfqspi, *txbuf++);
244         else
245                 for (i = 0; i < count; ++i)
246                         mcfqspi_wr_qdr(mcfqspi, 0);
247 
248         count -= n;
249         if (count) {
250                 u16 qwr = 0xf08;
251                 mcfqspi_wr_qwr(mcfqspi, 0x700);
252                 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
253 
254                 do {
255                         wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
256                         mcfqspi_wr_qwr(mcfqspi, qwr);
257                         mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
258                         if (rxbuf) {
259                                 mcfqspi_wr_qar(mcfqspi,
260                                                MCFQSPI_QAR_RXBUF + offset);
261                                 for (i = 0; i < 8; ++i)
262                                         *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
263                         }
264                         n = min(count, 8u);
265                         if (txbuf) {
266                                 mcfqspi_wr_qar(mcfqspi,
267                                                MCFQSPI_QAR_TXBUF + offset);
268                                 for (i = 0; i < n; ++i)
269                                         mcfqspi_wr_qdr(mcfqspi, *txbuf++);
270                         }
271                         qwr = (offset ? 0x808 : 0x000) + ((n - 1) << 8);
272                         offset ^= 8;
273                         count -= n;
274                 } while (count);
275                 wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
276                 mcfqspi_wr_qwr(mcfqspi, qwr);
277                 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
278                 if (rxbuf) {
279                         mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
280                         for (i = 0; i < 8; ++i)
281                                 *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
282                         offset ^= 8;
283                 }
284         } else {
285                 mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
286                 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
287         }
288         wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
289         if (rxbuf) {
290                 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
291                 for (i = 0; i < n; ++i)
292                         *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
293         }
294 }
295 
296 static void mcfqspi_set_cs(struct spi_device *spi, bool enable)
297 {
298         struct mcfqspi *mcfqspi = spi_master_get_devdata(spi->master);
299         bool cs_high = spi->mode & SPI_CS_HIGH;
300 
301         if (enable)
302                 mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high);
303         else
304                 mcfqspi_cs_deselect(mcfqspi, spi->chip_select, cs_high);
305 }
306 
307 static int mcfqspi_transfer_one(struct spi_master *master,
308                                 struct spi_device *spi,
309                                 struct spi_transfer *t)
310 {
311         struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
312         u16 qmr = MCFQSPI_QMR_MSTR;
313 
314         qmr |= t->bits_per_word << 10;
315         if (spi->mode & SPI_CPHA)
316                 qmr |= MCFQSPI_QMR_CPHA;
317         if (spi->mode & SPI_CPOL)
318                 qmr |= MCFQSPI_QMR_CPOL;
319         qmr |= mcfqspi_qmr_baud(t->speed_hz);
320         mcfqspi_wr_qmr(mcfqspi, qmr);
321 
322         mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE);
323         if (t->bits_per_word == 8)
324                 mcfqspi_transfer_msg8(mcfqspi, t->len, t->tx_buf, t->rx_buf);
325         else
326                 mcfqspi_transfer_msg16(mcfqspi, t->len / 2, t->tx_buf,
327                                        t->rx_buf);
328         mcfqspi_wr_qir(mcfqspi, 0);
329 
330         return 0;
331 }
332 
333 static int mcfqspi_setup(struct spi_device *spi)
334 {
335         mcfqspi_cs_deselect(spi_master_get_devdata(spi->master),
336                             spi->chip_select, spi->mode & SPI_CS_HIGH);
337 
338         dev_dbg(&spi->dev,
339                         "bits per word %d, chip select %d, speed %d KHz\n",
340                         spi->bits_per_word, spi->chip_select,
341                         (MCFQSPI_BUSCLK / mcfqspi_qmr_baud(spi->max_speed_hz))
342                         / 1000);
343 
344         return 0;
345 }
346 
347 static int mcfqspi_probe(struct platform_device *pdev)
348 {
349         struct spi_master *master;
350         struct mcfqspi *mcfqspi;
351         struct resource *res;
352         struct mcfqspi_platform_data *pdata;
353         int status;
354 
355         pdata = dev_get_platdata(&pdev->dev);
356         if (!pdata) {
357                 dev_dbg(&pdev->dev, "platform data is missing\n");
358                 return -ENOENT;
359         }
360 
361         if (!pdata->cs_control) {
362                 dev_dbg(&pdev->dev, "pdata->cs_control is NULL\n");
363                 return -EINVAL;
364         }
365 
366         master = spi_alloc_master(&pdev->dev, sizeof(*mcfqspi));
367         if (master == NULL) {
368                 dev_dbg(&pdev->dev, "spi_alloc_master failed\n");
369                 return -ENOMEM;
370         }
371 
372         mcfqspi = spi_master_get_devdata(master);
373 
374         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
375         mcfqspi->iobase = devm_ioremap_resource(&pdev->dev, res);
376         if (IS_ERR(mcfqspi->iobase)) {
377                 status = PTR_ERR(mcfqspi->iobase);
378                 goto fail0;
379         }
380 
381         mcfqspi->irq = platform_get_irq(pdev, 0);
382         if (mcfqspi->irq < 0) {
383                 dev_dbg(&pdev->dev, "platform_get_irq failed\n");
384                 status = -ENXIO;
385                 goto fail0;
386         }
387 
388         status = devm_request_irq(&pdev->dev, mcfqspi->irq, mcfqspi_irq_handler,
389                                 0, pdev->name, mcfqspi);
390         if (status) {
391                 dev_dbg(&pdev->dev, "request_irq failed\n");
392                 goto fail0;
393         }
394 
395         mcfqspi->clk = devm_clk_get(&pdev->dev, "qspi_clk");
396         if (IS_ERR(mcfqspi->clk)) {
397                 dev_dbg(&pdev->dev, "clk_get failed\n");
398                 status = PTR_ERR(mcfqspi->clk);
399                 goto fail0;
400         }
401         clk_enable(mcfqspi->clk);
402 
403         master->bus_num = pdata->bus_num;
404         master->num_chipselect = pdata->num_chipselect;
405 
406         mcfqspi->cs_control = pdata->cs_control;
407         status = mcfqspi_cs_setup(mcfqspi);
408         if (status) {
409                 dev_dbg(&pdev->dev, "error initializing cs_control\n");
410                 goto fail1;
411         }
412 
413         init_waitqueue_head(&mcfqspi->waitq);
414 
415         master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA;
416         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
417         master->setup = mcfqspi_setup;
418         master->set_cs = mcfqspi_set_cs;
419         master->transfer_one = mcfqspi_transfer_one;
420         master->auto_runtime_pm = true;
421 
422         platform_set_drvdata(pdev, master);
423 
424         status = devm_spi_register_master(&pdev->dev, master);
425         if (status) {
426                 dev_dbg(&pdev->dev, "spi_register_master failed\n");
427                 goto fail2;
428         }
429         pm_runtime_enable(&pdev->dev);
430 
431         dev_info(&pdev->dev, "Coldfire QSPI bus driver\n");
432 
433         return 0;
434 
435 fail2:
436         mcfqspi_cs_teardown(mcfqspi);
437 fail1:
438         clk_disable(mcfqspi->clk);
439 fail0:
440         spi_master_put(master);
441 
442         dev_dbg(&pdev->dev, "Coldfire QSPI probe failed\n");
443 
444         return status;
445 }
446 
447 static int mcfqspi_remove(struct platform_device *pdev)
448 {
449         struct spi_master *master = platform_get_drvdata(pdev);
450         struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
451 
452         pm_runtime_disable(&pdev->dev);
453         /* disable the hardware (set the baud rate to 0) */
454         mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR);
455 
456         mcfqspi_cs_teardown(mcfqspi);
457         clk_disable(mcfqspi->clk);
458 
459         return 0;
460 }
461 
462 #ifdef CONFIG_PM_SLEEP
463 static int mcfqspi_suspend(struct device *dev)
464 {
465         struct spi_master *master = dev_get_drvdata(dev);
466         struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
467         int ret;
468 
469         ret = spi_master_suspend(master);
470         if (ret)
471                 return ret;
472 
473         clk_disable(mcfqspi->clk);
474 
475         return 0;
476 }
477 
478 static int mcfqspi_resume(struct device *dev)
479 {
480         struct spi_master *master = dev_get_drvdata(dev);
481         struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
482 
483         clk_enable(mcfqspi->clk);
484 
485         return spi_master_resume(master);
486 }
487 #endif
488 
489 #ifdef CONFIG_PM
490 static int mcfqspi_runtime_suspend(struct device *dev)
491 {
492         struct spi_master *master = dev_get_drvdata(dev);
493         struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
494 
495         clk_disable(mcfqspi->clk);
496 
497         return 0;
498 }
499 
500 static int mcfqspi_runtime_resume(struct device *dev)
501 {
502         struct spi_master *master = dev_get_drvdata(dev);
503         struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
504 
505         clk_enable(mcfqspi->clk);
506 
507         return 0;
508 }
509 #endif
510 
511 static const struct dev_pm_ops mcfqspi_pm = {
512         SET_SYSTEM_SLEEP_PM_OPS(mcfqspi_suspend, mcfqspi_resume)
513         SET_RUNTIME_PM_OPS(mcfqspi_runtime_suspend, mcfqspi_runtime_resume,
514                         NULL)
515 };
516 
517 static struct platform_driver mcfqspi_driver = {
518         .driver.name    = DRIVER_NAME,
519         .driver.owner   = THIS_MODULE,
520         .driver.pm      = &mcfqspi_pm,
521         .probe          = mcfqspi_probe,
522         .remove         = mcfqspi_remove,
523 };
524 module_platform_driver(mcfqspi_driver);
525 
526 MODULE_AUTHOR("Steven King <sfking@fdwdc.com>");
527 MODULE_DESCRIPTION("Coldfire QSPI Controller Driver");
528 MODULE_LICENSE("GPL");
529 MODULE_ALIAS("platform:" DRIVER_NAME);
530 

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