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Linux/drivers/spi/spi-bcm2835.c

  1 /*
  2  * Driver for Broadcom BCM2835 SPI Controllers
  3  *
  4  * Copyright (C) 2012 Chris Boot
  5  * Copyright (C) 2013 Stephen Warren
  6  *
  7  * This driver is inspired by:
  8  * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
  9  * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
 10  *
 11  * This program is free software; you can redistribute it and/or modify
 12  * it under the terms of the GNU General Public License as published by
 13  * the Free Software Foundation; either version 2 of the License, or
 14  * (at your option) any later version.
 15  *
 16  * This program is distributed in the hope that it will be useful,
 17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 19  * GNU General Public License for more details.
 20  *
 21  * You should have received a copy of the GNU General Public License
 22  * along with this program; if not, write to the Free Software
 23  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 24  */
 25 
 26 #include <linux/clk.h>
 27 #include <linux/completion.h>
 28 #include <linux/delay.h>
 29 #include <linux/err.h>
 30 #include <linux/interrupt.h>
 31 #include <linux/io.h>
 32 #include <linux/kernel.h>
 33 #include <linux/module.h>
 34 #include <linux/of.h>
 35 #include <linux/of_irq.h>
 36 #include <linux/of_device.h>
 37 #include <linux/spi/spi.h>
 38 
 39 /* SPI register offsets */
 40 #define BCM2835_SPI_CS                  0x00
 41 #define BCM2835_SPI_FIFO                0x04
 42 #define BCM2835_SPI_CLK                 0x08
 43 #define BCM2835_SPI_DLEN                0x0c
 44 #define BCM2835_SPI_LTOH                0x10
 45 #define BCM2835_SPI_DC                  0x14
 46 
 47 /* Bitfields in CS */
 48 #define BCM2835_SPI_CS_LEN_LONG         0x02000000
 49 #define BCM2835_SPI_CS_DMA_LEN          0x01000000
 50 #define BCM2835_SPI_CS_CSPOL2           0x00800000
 51 #define BCM2835_SPI_CS_CSPOL1           0x00400000
 52 #define BCM2835_SPI_CS_CSPOL0           0x00200000
 53 #define BCM2835_SPI_CS_RXF              0x00100000
 54 #define BCM2835_SPI_CS_RXR              0x00080000
 55 #define BCM2835_SPI_CS_TXD              0x00040000
 56 #define BCM2835_SPI_CS_RXD              0x00020000
 57 #define BCM2835_SPI_CS_DONE             0x00010000
 58 #define BCM2835_SPI_CS_LEN              0x00002000
 59 #define BCM2835_SPI_CS_REN              0x00001000
 60 #define BCM2835_SPI_CS_ADCS             0x00000800
 61 #define BCM2835_SPI_CS_INTR             0x00000400
 62 #define BCM2835_SPI_CS_INTD             0x00000200
 63 #define BCM2835_SPI_CS_DMAEN            0x00000100
 64 #define BCM2835_SPI_CS_TA               0x00000080
 65 #define BCM2835_SPI_CS_CSPOL            0x00000040
 66 #define BCM2835_SPI_CS_CLEAR_RX         0x00000020
 67 #define BCM2835_SPI_CS_CLEAR_TX         0x00000010
 68 #define BCM2835_SPI_CS_CPOL             0x00000008
 69 #define BCM2835_SPI_CS_CPHA             0x00000004
 70 #define BCM2835_SPI_CS_CS_10            0x00000002
 71 #define BCM2835_SPI_CS_CS_01            0x00000001
 72 
 73 #define BCM2835_SPI_TIMEOUT_MS  30000
 74 #define BCM2835_SPI_MODE_BITS   (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS)
 75 
 76 #define DRV_NAME        "spi-bcm2835"
 77 
 78 struct bcm2835_spi {
 79         void __iomem *regs;
 80         struct clk *clk;
 81         int irq;
 82         struct completion done;
 83         const u8 *tx_buf;
 84         u8 *rx_buf;
 85         int len;
 86 };
 87 
 88 static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg)
 89 {
 90         return readl(bs->regs + reg);
 91 }
 92 
 93 static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val)
 94 {
 95         writel(val, bs->regs + reg);
 96 }
 97 
 98 static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs, int len)
 99 {
100         u8 byte;
101 
102         while (len--) {
103                 byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
104                 if (bs->rx_buf)
105                         *bs->rx_buf++ = byte;
106         }
107 }
108 
109 static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs, int len)
110 {
111         u8 byte;
112 
113         if (len > bs->len)
114                 len = bs->len;
115 
116         while (len--) {
117                 byte = bs->tx_buf ? *bs->tx_buf++ : 0;
118                 bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
119                 bs->len--;
120         }
121 }
122 
123 static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
124 {
125         struct spi_master *master = dev_id;
126         struct bcm2835_spi *bs = spi_master_get_devdata(master);
127         u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
128 
129         /*
130          * RXR - RX needs Reading. This means 12 (or more) bytes have been
131          * transmitted and hence 12 (or more) bytes have been received.
132          *
133          * The FIFO is 16-bytes deep. We check for this interrupt to keep the
134          * FIFO full; we have a 4-byte-time buffer for IRQ latency. We check
135          * this before DONE (TX empty) just in case we delayed processing this
136          * interrupt for some reason.
137          *
138          * We only check for this case if we have more bytes to TX; at the end
139          * of the transfer, we ignore this pipelining optimization, and let
140          * bcm2835_spi_finish_transfer() drain the RX FIFO.
141          */
142         if (bs->len && (cs & BCM2835_SPI_CS_RXR)) {
143                 /* Read 12 bytes of data */
144                 bcm2835_rd_fifo(bs, 12);
145 
146                 /* Write up to 12 bytes */
147                 bcm2835_wr_fifo(bs, 12);
148 
149                 /*
150                  * We must have written something to the TX FIFO due to the
151                  * bs->len check above, so cannot be DONE. Hence, return
152                  * early. Note that DONE could also be set if we serviced an
153                  * RXR interrupt really late.
154                  */
155                 return IRQ_HANDLED;
156         }
157 
158         /*
159          * DONE - TX empty. This occurs when we first enable the transfer
160          * since we do not pre-fill the TX FIFO. At any other time, given that
161          * we refill the TX FIFO above based on RXR, and hence ignore DONE if
162          * RXR is set, DONE really does mean end-of-transfer.
163          */
164         if (cs & BCM2835_SPI_CS_DONE) {
165                 if (bs->len) { /* First interrupt in a transfer */
166                         bcm2835_wr_fifo(bs, 16);
167                 } else { /* Transfer complete */
168                         /* Disable SPI interrupts */
169                         cs &= ~(BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD);
170                         bcm2835_wr(bs, BCM2835_SPI_CS, cs);
171 
172                         /*
173                          * Wake up bcm2835_spi_transfer_one(), which will call
174                          * bcm2835_spi_finish_transfer(), to drain the RX FIFO.
175                          */
176                         complete(&bs->done);
177                 }
178 
179                 return IRQ_HANDLED;
180         }
181 
182         return IRQ_NONE;
183 }
184 
185 static int bcm2835_spi_start_transfer(struct spi_device *spi,
186                 struct spi_transfer *tfr)
187 {
188         struct bcm2835_spi *bs = spi_master_get_devdata(spi->master);
189         unsigned long spi_hz, clk_hz, cdiv;
190         u32 cs = BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA;
191 
192         spi_hz = tfr->speed_hz;
193         clk_hz = clk_get_rate(bs->clk);
194 
195         if (spi_hz >= clk_hz / 2) {
196                 cdiv = 2; /* clk_hz/2 is the fastest we can go */
197         } else if (spi_hz) {
198                 /* CDIV must be a power of two */
199                 cdiv = roundup_pow_of_two(DIV_ROUND_UP(clk_hz, spi_hz));
200 
201                 if (cdiv >= 65536)
202                         cdiv = 0; /* 0 is the slowest we can go */
203         } else
204                 cdiv = 0; /* 0 is the slowest we can go */
205 
206         if (spi->mode & SPI_CPOL)
207                 cs |= BCM2835_SPI_CS_CPOL;
208         if (spi->mode & SPI_CPHA)
209                 cs |= BCM2835_SPI_CS_CPHA;
210 
211         if (!(spi->mode & SPI_NO_CS)) {
212                 if (spi->mode & SPI_CS_HIGH) {
213                         cs |= BCM2835_SPI_CS_CSPOL;
214                         cs |= BCM2835_SPI_CS_CSPOL0 << spi->chip_select;
215                 }
216 
217                 cs |= spi->chip_select;
218         }
219 
220         reinit_completion(&bs->done);
221         bs->tx_buf = tfr->tx_buf;
222         bs->rx_buf = tfr->rx_buf;
223         bs->len = tfr->len;
224 
225         bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
226         /*
227          * Enable the HW block. This will immediately trigger a DONE (TX
228          * empty) interrupt, upon which we will fill the TX FIFO with the
229          * first TX bytes. Pre-filling the TX FIFO here to avoid the
230          * interrupt doesn't work:-(
231          */
232         bcm2835_wr(bs, BCM2835_SPI_CS, cs);
233 
234         return 0;
235 }
236 
237 static int bcm2835_spi_finish_transfer(struct spi_device *spi,
238                 struct spi_transfer *tfr, bool cs_change)
239 {
240         struct bcm2835_spi *bs = spi_master_get_devdata(spi->master);
241         u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
242 
243         /* Drain RX FIFO */
244         while (cs & BCM2835_SPI_CS_RXD) {
245                 bcm2835_rd_fifo(bs, 1);
246                 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
247         }
248 
249         if (tfr->delay_usecs)
250                 udelay(tfr->delay_usecs);
251 
252         if (cs_change)
253                 /* Clear TA flag */
254                 bcm2835_wr(bs, BCM2835_SPI_CS, cs & ~BCM2835_SPI_CS_TA);
255 
256         return 0;
257 }
258 
259 static int bcm2835_spi_transfer_one(struct spi_master *master,
260                 struct spi_message *mesg)
261 {
262         struct bcm2835_spi *bs = spi_master_get_devdata(master);
263         struct spi_transfer *tfr;
264         struct spi_device *spi = mesg->spi;
265         int err = 0;
266         unsigned int timeout;
267         bool cs_change;
268 
269         list_for_each_entry(tfr, &mesg->transfers, transfer_list) {
270                 err = bcm2835_spi_start_transfer(spi, tfr);
271                 if (err)
272                         goto out;
273 
274                 timeout = wait_for_completion_timeout(&bs->done,
275                                 msecs_to_jiffies(BCM2835_SPI_TIMEOUT_MS));
276                 if (!timeout) {
277                         err = -ETIMEDOUT;
278                         goto out;
279                 }
280 
281                 cs_change = tfr->cs_change ||
282                         list_is_last(&tfr->transfer_list, &mesg->transfers);
283 
284                 err = bcm2835_spi_finish_transfer(spi, tfr, cs_change);
285                 if (err)
286                         goto out;
287 
288                 mesg->actual_length += (tfr->len - bs->len);
289         }
290 
291 out:
292         /* Clear FIFOs, and disable the HW block */
293         bcm2835_wr(bs, BCM2835_SPI_CS,
294                    BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
295         mesg->status = err;
296         spi_finalize_current_message(master);
297 
298         return 0;
299 }
300 
301 static int bcm2835_spi_probe(struct platform_device *pdev)
302 {
303         struct spi_master *master;
304         struct bcm2835_spi *bs;
305         struct resource *res;
306         int err;
307 
308         master = spi_alloc_master(&pdev->dev, sizeof(*bs));
309         if (!master) {
310                 dev_err(&pdev->dev, "spi_alloc_master() failed\n");
311                 return -ENOMEM;
312         }
313 
314         platform_set_drvdata(pdev, master);
315 
316         master->mode_bits = BCM2835_SPI_MODE_BITS;
317         master->bits_per_word_mask = SPI_BPW_MASK(8);
318         master->num_chipselect = 3;
319         master->transfer_one_message = bcm2835_spi_transfer_one;
320         master->dev.of_node = pdev->dev.of_node;
321 
322         bs = spi_master_get_devdata(master);
323 
324         init_completion(&bs->done);
325 
326         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
327         bs->regs = devm_ioremap_resource(&pdev->dev, res);
328         if (IS_ERR(bs->regs)) {
329                 err = PTR_ERR(bs->regs);
330                 goto out_master_put;
331         }
332 
333         bs->clk = devm_clk_get(&pdev->dev, NULL);
334         if (IS_ERR(bs->clk)) {
335                 err = PTR_ERR(bs->clk);
336                 dev_err(&pdev->dev, "could not get clk: %d\n", err);
337                 goto out_master_put;
338         }
339 
340         bs->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
341         if (bs->irq <= 0) {
342                 dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
343                 err = bs->irq ? bs->irq : -ENODEV;
344                 goto out_master_put;
345         }
346 
347         clk_prepare_enable(bs->clk);
348 
349         err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
350                                 dev_name(&pdev->dev), master);
351         if (err) {
352                 dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
353                 goto out_clk_disable;
354         }
355 
356         /* initialise the hardware */
357         bcm2835_wr(bs, BCM2835_SPI_CS,
358                    BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
359 
360         err = devm_spi_register_master(&pdev->dev, master);
361         if (err) {
362                 dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
363                 goto out_clk_disable;
364         }
365 
366         return 0;
367 
368 out_clk_disable:
369         clk_disable_unprepare(bs->clk);
370 out_master_put:
371         spi_master_put(master);
372         return err;
373 }
374 
375 static int bcm2835_spi_remove(struct platform_device *pdev)
376 {
377         struct spi_master *master = platform_get_drvdata(pdev);
378         struct bcm2835_spi *bs = spi_master_get_devdata(master);
379 
380         /* Clear FIFOs, and disable the HW block */
381         bcm2835_wr(bs, BCM2835_SPI_CS,
382                    BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
383 
384         clk_disable_unprepare(bs->clk);
385 
386         return 0;
387 }
388 
389 static const struct of_device_id bcm2835_spi_match[] = {
390         { .compatible = "brcm,bcm2835-spi", },
391         {}
392 };
393 MODULE_DEVICE_TABLE(of, bcm2835_spi_match);
394 
395 static struct platform_driver bcm2835_spi_driver = {
396         .driver         = {
397                 .name           = DRV_NAME,
398                 .owner          = THIS_MODULE,
399                 .of_match_table = bcm2835_spi_match,
400         },
401         .probe          = bcm2835_spi_probe,
402         .remove         = bcm2835_spi_remove,
403 };
404 module_platform_driver(bcm2835_spi_driver);
405 
406 MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835");
407 MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
408 MODULE_LICENSE("GPL v2");
409 

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