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Linux/drivers/spi/spi-bcm2835.c

  1 /*
  2  * Driver for Broadcom BCM2835 SPI Controllers
  3  *
  4  * Copyright (C) 2012 Chris Boot
  5  * Copyright (C) 2013 Stephen Warren
  6  * Copyright (C) 2015 Martin Sperl
  7  *
  8  * This driver is inspired by:
  9  * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
 10  * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
 11  *
 12  * This program is free software; you can redistribute it and/or modify
 13  * it under the terms of the GNU General Public License as published by
 14  * the Free Software Foundation; either version 2 of the License, or
 15  * (at your option) any later version.
 16  *
 17  * This program is distributed in the hope that it will be useful,
 18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 20  * GNU General Public License for more details.
 21  */
 22 
 23 #include <linux/clk.h>
 24 #include <linux/completion.h>
 25 #include <linux/delay.h>
 26 #include <linux/err.h>
 27 #include <linux/interrupt.h>
 28 #include <linux/io.h>
 29 #include <linux/kernel.h>
 30 #include <linux/module.h>
 31 #include <linux/of.h>
 32 #include <linux/of_irq.h>
 33 #include <linux/of_gpio.h>
 34 #include <linux/of_device.h>
 35 #include <linux/spi/spi.h>
 36 
 37 /* SPI register offsets */
 38 #define BCM2835_SPI_CS                  0x00
 39 #define BCM2835_SPI_FIFO                0x04
 40 #define BCM2835_SPI_CLK                 0x08
 41 #define BCM2835_SPI_DLEN                0x0c
 42 #define BCM2835_SPI_LTOH                0x10
 43 #define BCM2835_SPI_DC                  0x14
 44 
 45 /* Bitfields in CS */
 46 #define BCM2835_SPI_CS_LEN_LONG         0x02000000
 47 #define BCM2835_SPI_CS_DMA_LEN          0x01000000
 48 #define BCM2835_SPI_CS_CSPOL2           0x00800000
 49 #define BCM2835_SPI_CS_CSPOL1           0x00400000
 50 #define BCM2835_SPI_CS_CSPOL0           0x00200000
 51 #define BCM2835_SPI_CS_RXF              0x00100000
 52 #define BCM2835_SPI_CS_RXR              0x00080000
 53 #define BCM2835_SPI_CS_TXD              0x00040000
 54 #define BCM2835_SPI_CS_RXD              0x00020000
 55 #define BCM2835_SPI_CS_DONE             0x00010000
 56 #define BCM2835_SPI_CS_LEN              0x00002000
 57 #define BCM2835_SPI_CS_REN              0x00001000
 58 #define BCM2835_SPI_CS_ADCS             0x00000800
 59 #define BCM2835_SPI_CS_INTR             0x00000400
 60 #define BCM2835_SPI_CS_INTD             0x00000200
 61 #define BCM2835_SPI_CS_DMAEN            0x00000100
 62 #define BCM2835_SPI_CS_TA               0x00000080
 63 #define BCM2835_SPI_CS_CSPOL            0x00000040
 64 #define BCM2835_SPI_CS_CLEAR_RX         0x00000020
 65 #define BCM2835_SPI_CS_CLEAR_TX         0x00000010
 66 #define BCM2835_SPI_CS_CPOL             0x00000008
 67 #define BCM2835_SPI_CS_CPHA             0x00000004
 68 #define BCM2835_SPI_CS_CS_10            0x00000002
 69 #define BCM2835_SPI_CS_CS_01            0x00000001
 70 
 71 #define BCM2835_SPI_POLLING_LIMIT_US    30
 72 #define BCM2835_SPI_TIMEOUT_MS          30000
 73 #define BCM2835_SPI_MODE_BITS   (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
 74                                 | SPI_NO_CS | SPI_3WIRE)
 75 
 76 #define DRV_NAME        "spi-bcm2835"
 77 
 78 struct bcm2835_spi {
 79         void __iomem *regs;
 80         struct clk *clk;
 81         int irq;
 82         const u8 *tx_buf;
 83         u8 *rx_buf;
 84         int tx_len;
 85         int rx_len;
 86 };
 87 
 88 static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg)
 89 {
 90         return readl(bs->regs + reg);
 91 }
 92 
 93 static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val)
 94 {
 95         writel(val, bs->regs + reg);
 96 }
 97 
 98 static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs)
 99 {
100         u8 byte;
101 
102         while ((bs->rx_len) &&
103                (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) {
104                 byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
105                 if (bs->rx_buf)
106                         *bs->rx_buf++ = byte;
107                 bs->rx_len--;
108         }
109 }
110 
111 static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs)
112 {
113         u8 byte;
114 
115         while ((bs->tx_len) &&
116                (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) {
117                 byte = bs->tx_buf ? *bs->tx_buf++ : 0;
118                 bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
119                 bs->tx_len--;
120         }
121 }
122 
123 static void bcm2835_spi_reset_hw(struct spi_master *master)
124 {
125         struct bcm2835_spi *bs = spi_master_get_devdata(master);
126         u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
127 
128         /* Disable SPI interrupts and transfer */
129         cs &= ~(BCM2835_SPI_CS_INTR |
130                 BCM2835_SPI_CS_INTD |
131                 BCM2835_SPI_CS_TA);
132         /* and reset RX/TX FIFOS */
133         cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX;
134 
135         /* and reset the SPI_HW */
136         bcm2835_wr(bs, BCM2835_SPI_CS, cs);
137 }
138 
139 static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
140 {
141         struct spi_master *master = dev_id;
142         struct bcm2835_spi *bs = spi_master_get_devdata(master);
143 
144         /* Read as many bytes as possible from FIFO */
145         bcm2835_rd_fifo(bs);
146         /* Write as many bytes as possible to FIFO */
147         bcm2835_wr_fifo(bs);
148 
149         /* based on flags decide if we can finish the transfer */
150         if (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE) {
151                 /* Transfer complete - reset SPI HW */
152                 bcm2835_spi_reset_hw(master);
153                 /* wake up the framework */
154                 complete(&master->xfer_completion);
155         }
156 
157         return IRQ_HANDLED;
158 }
159 
160 static int bcm2835_spi_transfer_one_poll(struct spi_master *master,
161                                          struct spi_device *spi,
162                                          struct spi_transfer *tfr,
163                                          u32 cs,
164                                          unsigned long xfer_time_us)
165 {
166         struct bcm2835_spi *bs = spi_master_get_devdata(master);
167         /* set timeout to 1 second of maximum polling */
168         unsigned long timeout = jiffies + HZ;
169 
170         /* enable HW block without interrupts */
171         bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA);
172 
173         /* loop until finished the transfer */
174         while (bs->rx_len) {
175                 /* read from fifo as much as possible */
176                 bcm2835_rd_fifo(bs);
177                 /* fill in tx fifo as much as possible */
178                 bcm2835_wr_fifo(bs);
179                 /* if we still expect some data after the read,
180                  * check for a possible timeout
181                  */
182                 if (bs->rx_len && time_after(jiffies, timeout)) {
183                         /* Transfer complete - reset SPI HW */
184                         bcm2835_spi_reset_hw(master);
185                         /* and return timeout */
186                         return -ETIMEDOUT;
187                 }
188         }
189 
190         /* Transfer complete - reset SPI HW */
191         bcm2835_spi_reset_hw(master);
192         /* and return without waiting for completion */
193         return 0;
194 }
195 
196 static int bcm2835_spi_transfer_one_irq(struct spi_master *master,
197                                         struct spi_device *spi,
198                                         struct spi_transfer *tfr,
199                                         u32 cs)
200 {
201         struct bcm2835_spi *bs = spi_master_get_devdata(master);
202 
203         /* fill in fifo if we have gpio-cs
204          * note that there have been rare events where the native-CS
205          * flapped for <1us which may change the behaviour
206          * with gpio-cs this does not happen, so it is implemented
207          * only for this case
208          */
209         if (gpio_is_valid(spi->cs_gpio)) {
210                 /* enable HW block, but without interrupts enabled
211                  * this would triggern an immediate interrupt
212                  */
213                 bcm2835_wr(bs, BCM2835_SPI_CS,
214                            cs | BCM2835_SPI_CS_TA);
215                 /* fill in tx fifo as much as possible */
216                 bcm2835_wr_fifo(bs);
217         }
218 
219         /*
220          * Enable the HW block. This will immediately trigger a DONE (TX
221          * empty) interrupt, upon which we will fill the TX FIFO with the
222          * first TX bytes. Pre-filling the TX FIFO here to avoid the
223          * interrupt doesn't work:-(
224          */
225         cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA;
226         bcm2835_wr(bs, BCM2835_SPI_CS, cs);
227 
228         /* signal that we need to wait for completion */
229         return 1;
230 }
231 
232 static int bcm2835_spi_transfer_one(struct spi_master *master,
233                                     struct spi_device *spi,
234                                     struct spi_transfer *tfr)
235 {
236         struct bcm2835_spi *bs = spi_master_get_devdata(master);
237         unsigned long spi_hz, clk_hz, cdiv;
238         unsigned long spi_used_hz, xfer_time_us;
239         u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
240 
241         /* set clock */
242         spi_hz = tfr->speed_hz;
243         clk_hz = clk_get_rate(bs->clk);
244 
245         if (spi_hz >= clk_hz / 2) {
246                 cdiv = 2; /* clk_hz/2 is the fastest we can go */
247         } else if (spi_hz) {
248                 /* CDIV must be a multiple of two */
249                 cdiv = DIV_ROUND_UP(clk_hz, spi_hz);
250                 cdiv += (cdiv % 2);
251 
252                 if (cdiv >= 65536)
253                         cdiv = 0; /* 0 is the slowest we can go */
254         } else {
255                 cdiv = 0; /* 0 is the slowest we can go */
256         }
257         spi_used_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536);
258         bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
259 
260         /* handle all the modes */
261         if ((spi->mode & SPI_3WIRE) && (tfr->rx_buf))
262                 cs |= BCM2835_SPI_CS_REN;
263         if (spi->mode & SPI_CPOL)
264                 cs |= BCM2835_SPI_CS_CPOL;
265         if (spi->mode & SPI_CPHA)
266                 cs |= BCM2835_SPI_CS_CPHA;
267 
268         /* for gpio_cs set dummy CS so that no HW-CS get changed
269          * we can not run this in bcm2835_spi_set_cs, as it does
270          * not get called for cs_gpio cases, so we need to do it here
271          */
272         if (gpio_is_valid(spi->cs_gpio) || (spi->mode & SPI_NO_CS))
273                 cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
274 
275         /* set transmit buffers and length */
276         bs->tx_buf = tfr->tx_buf;
277         bs->rx_buf = tfr->rx_buf;
278         bs->tx_len = tfr->len;
279         bs->rx_len = tfr->len;
280 
281         /* calculate the estimated time in us the transfer runs */
282         xfer_time_us = tfr->len
283                 * 9 /* clocks/byte - SPI-HW waits 1 clock after each byte */
284                 * 1000000 / spi_used_hz;
285 
286         /* for short requests run polling*/
287         if (xfer_time_us <= BCM2835_SPI_POLLING_LIMIT_US)
288                 return bcm2835_spi_transfer_one_poll(master, spi, tfr,
289                                                      cs, xfer_time_us);
290 
291         return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs);
292 }
293 
294 static void bcm2835_spi_handle_err(struct spi_master *master,
295                                    struct spi_message *msg)
296 {
297         bcm2835_spi_reset_hw(master);
298 }
299 
300 static void bcm2835_spi_set_cs(struct spi_device *spi, bool gpio_level)
301 {
302         /*
303          * we can assume that we are "native" as per spi_set_cs
304          *   calling us ONLY when cs_gpio is not set
305          * we can also assume that we are CS < 3 as per bcm2835_spi_setup
306          *   we would not get called because of error handling there.
307          * the level passed is the electrical level not enabled/disabled
308          *   so it has to get translated back to enable/disable
309          *   see spi_set_cs in spi.c for the implementation
310          */
311 
312         struct spi_master *master = spi->master;
313         struct bcm2835_spi *bs = spi_master_get_devdata(master);
314         u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
315         bool enable;
316 
317         /* calculate the enable flag from the passed gpio_level */
318         enable = (spi->mode & SPI_CS_HIGH) ? gpio_level : !gpio_level;
319 
320         /* set flags for "reverse" polarity in the registers */
321         if (spi->mode & SPI_CS_HIGH) {
322                 /* set the correct CS-bits */
323                 cs |= BCM2835_SPI_CS_CSPOL;
324                 cs |= BCM2835_SPI_CS_CSPOL0 << spi->chip_select;
325         } else {
326                 /* clean the CS-bits */
327                 cs &= ~BCM2835_SPI_CS_CSPOL;
328                 cs &= ~(BCM2835_SPI_CS_CSPOL0 << spi->chip_select);
329         }
330 
331         /* select the correct chip_select depending on disabled/enabled */
332         if (enable) {
333                 /* set cs correctly */
334                 if (spi->mode & SPI_NO_CS) {
335                         /* use the "undefined" chip-select */
336                         cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
337                 } else {
338                         /* set the chip select */
339                         cs &= ~(BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01);
340                         cs |= spi->chip_select;
341                 }
342         } else {
343                 /* disable CSPOL which puts HW-CS into deselected state */
344                 cs &= ~BCM2835_SPI_CS_CSPOL;
345                 /* use the "undefined" chip-select as precaution */
346                 cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
347         }
348 
349         /* finally set the calculated flags in SPI_CS */
350         bcm2835_wr(bs, BCM2835_SPI_CS, cs);
351 }
352 
353 static int chip_match_name(struct gpio_chip *chip, void *data)
354 {
355         return !strcmp(chip->label, data);
356 }
357 
358 static int bcm2835_spi_setup(struct spi_device *spi)
359 {
360         int err;
361         struct gpio_chip *chip;
362         /*
363          * sanity checking the native-chipselects
364          */
365         if (spi->mode & SPI_NO_CS)
366                 return 0;
367         if (gpio_is_valid(spi->cs_gpio))
368                 return 0;
369         if (spi->chip_select > 1) {
370                 /* error in the case of native CS requested with CS > 1
371                  * officially there is a CS2, but it is not documented
372                  * which GPIO is connected with that...
373                  */
374                 dev_err(&spi->dev,
375                         "setup: only two native chip-selects are supported\n");
376                 return -EINVAL;
377         }
378         /* now translate native cs to GPIO */
379 
380         /* get the gpio chip for the base */
381         chip = gpiochip_find("pinctrl-bcm2835", chip_match_name);
382         if (!chip)
383                 return 0;
384 
385         /* and calculate the real CS */
386         spi->cs_gpio = chip->base + 8 - spi->chip_select;
387 
388         /* and set up the "mode" and level */
389         dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n",
390                  spi->chip_select, spi->cs_gpio);
391 
392         /* set up GPIO as output and pull to the correct level */
393         err = gpio_direction_output(spi->cs_gpio,
394                                     (spi->mode & SPI_CS_HIGH) ? 0 : 1);
395         if (err) {
396                 dev_err(&spi->dev,
397                         "could not set CS%i gpio %i as output: %i",
398                         spi->chip_select, spi->cs_gpio, err);
399                 return err;
400         }
401         /* the implementation of pinctrl-bcm2835 currently does not
402          * set the GPIO value when using gpio_direction_output
403          * so we are setting it here explicitly
404          */
405         gpio_set_value(spi->cs_gpio, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
406 
407         return 0;
408 }
409 
410 static int bcm2835_spi_probe(struct platform_device *pdev)
411 {
412         struct spi_master *master;
413         struct bcm2835_spi *bs;
414         struct resource *res;
415         int err;
416 
417         master = spi_alloc_master(&pdev->dev, sizeof(*bs));
418         if (!master) {
419                 dev_err(&pdev->dev, "spi_alloc_master() failed\n");
420                 return -ENOMEM;
421         }
422 
423         platform_set_drvdata(pdev, master);
424 
425         master->mode_bits = BCM2835_SPI_MODE_BITS;
426         master->bits_per_word_mask = SPI_BPW_MASK(8);
427         master->num_chipselect = 3;
428         master->setup = bcm2835_spi_setup;
429         master->set_cs = bcm2835_spi_set_cs;
430         master->transfer_one = bcm2835_spi_transfer_one;
431         master->handle_err = bcm2835_spi_handle_err;
432         master->dev.of_node = pdev->dev.of_node;
433 
434         bs = spi_master_get_devdata(master);
435 
436         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
437         bs->regs = devm_ioremap_resource(&pdev->dev, res);
438         if (IS_ERR(bs->regs)) {
439                 err = PTR_ERR(bs->regs);
440                 goto out_master_put;
441         }
442 
443         bs->clk = devm_clk_get(&pdev->dev, NULL);
444         if (IS_ERR(bs->clk)) {
445                 err = PTR_ERR(bs->clk);
446                 dev_err(&pdev->dev, "could not get clk: %d\n", err);
447                 goto out_master_put;
448         }
449 
450         bs->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
451         if (bs->irq <= 0) {
452                 dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
453                 err = bs->irq ? bs->irq : -ENODEV;
454                 goto out_master_put;
455         }
456 
457         clk_prepare_enable(bs->clk);
458 
459         err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
460                                dev_name(&pdev->dev), master);
461         if (err) {
462                 dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
463                 goto out_clk_disable;
464         }
465 
466         /* initialise the hardware with the default polarities */
467         bcm2835_wr(bs, BCM2835_SPI_CS,
468                    BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
469 
470         err = devm_spi_register_master(&pdev->dev, master);
471         if (err) {
472                 dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
473                 goto out_clk_disable;
474         }
475 
476         return 0;
477 
478 out_clk_disable:
479         clk_disable_unprepare(bs->clk);
480 out_master_put:
481         spi_master_put(master);
482         return err;
483 }
484 
485 static int bcm2835_spi_remove(struct platform_device *pdev)
486 {
487         struct spi_master *master = platform_get_drvdata(pdev);
488         struct bcm2835_spi *bs = spi_master_get_devdata(master);
489 
490         /* Clear FIFOs, and disable the HW block */
491         bcm2835_wr(bs, BCM2835_SPI_CS,
492                    BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
493 
494         clk_disable_unprepare(bs->clk);
495 
496         return 0;
497 }
498 
499 static const struct of_device_id bcm2835_spi_match[] = {
500         { .compatible = "brcm,bcm2835-spi", },
501         {}
502 };
503 MODULE_DEVICE_TABLE(of, bcm2835_spi_match);
504 
505 static struct platform_driver bcm2835_spi_driver = {
506         .driver         = {
507                 .name           = DRV_NAME,
508                 .of_match_table = bcm2835_spi_match,
509         },
510         .probe          = bcm2835_spi_probe,
511         .remove         = bcm2835_spi_remove,
512 };
513 module_platform_driver(bcm2835_spi_driver);
514 
515 MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835");
516 MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
517 MODULE_LICENSE("GPL v2");
518 

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