Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/spi/spi-au1550.c

  1 /*
  2  * au1550 psc spi controller driver
  3  * may work also with au1200, au1210, au1250
  4  * will not work on au1000, au1100 and au1500 (no full spi controller there)
  5  *
  6  * Copyright (c) 2006 ATRON electronic GmbH
  7  * Author: Jan Nikitenko <jan.nikitenko@gmail.com>
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License as published by
 11  * the Free Software Foundation; either version 2 of the License, or
 12  * (at your option) any later version.
 13  *
 14  * This program is distributed in the hope that it will be useful,
 15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 17  * GNU General Public License for more details.
 18  *
 19  * You should have received a copy of the GNU General Public License
 20  * along with this program; if not, write to the Free Software
 21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 22  */
 23 
 24 #include <linux/init.h>
 25 #include <linux/interrupt.h>
 26 #include <linux/slab.h>
 27 #include <linux/errno.h>
 28 #include <linux/module.h>
 29 #include <linux/device.h>
 30 #include <linux/platform_device.h>
 31 #include <linux/resource.h>
 32 #include <linux/spi/spi.h>
 33 #include <linux/spi/spi_bitbang.h>
 34 #include <linux/dma-mapping.h>
 35 #include <linux/completion.h>
 36 #include <asm/mach-au1x00/au1000.h>
 37 #include <asm/mach-au1x00/au1xxx_psc.h>
 38 #include <asm/mach-au1x00/au1xxx_dbdma.h>
 39 
 40 #include <asm/mach-au1x00/au1550_spi.h>
 41 
 42 static unsigned usedma = 1;
 43 module_param(usedma, uint, 0644);
 44 
 45 /*
 46 #define AU1550_SPI_DEBUG_LOOPBACK
 47 */
 48 
 49 
 50 #define AU1550_SPI_DBDMA_DESCRIPTORS 1
 51 #define AU1550_SPI_DMA_RXTMP_MINSIZE 2048U
 52 
 53 struct au1550_spi {
 54         struct spi_bitbang bitbang;
 55 
 56         volatile psc_spi_t __iomem *regs;
 57         int irq;
 58 
 59         unsigned len;
 60         unsigned tx_count;
 61         unsigned rx_count;
 62         const u8 *tx;
 63         u8 *rx;
 64 
 65         void (*rx_word)(struct au1550_spi *hw);
 66         void (*tx_word)(struct au1550_spi *hw);
 67         int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t);
 68         irqreturn_t (*irq_callback)(struct au1550_spi *hw);
 69 
 70         struct completion master_done;
 71 
 72         unsigned usedma;
 73         u32 dma_tx_id;
 74         u32 dma_rx_id;
 75         u32 dma_tx_ch;
 76         u32 dma_rx_ch;
 77 
 78         u8 *dma_rx_tmpbuf;
 79         unsigned dma_rx_tmpbuf_size;
 80         u32 dma_rx_tmpbuf_addr;
 81 
 82         struct spi_master *master;
 83         struct device *dev;
 84         struct au1550_spi_info *pdata;
 85         struct resource *ioarea;
 86 };
 87 
 88 
 89 /* we use an 8-bit memory device for dma transfers to/from spi fifo */
 90 static dbdev_tab_t au1550_spi_mem_dbdev =
 91 {
 92         .dev_id                 = DBDMA_MEM_CHAN,
 93         .dev_flags              = DEV_FLAGS_ANYUSE|DEV_FLAGS_SYNC,
 94         .dev_tsize              = 0,
 95         .dev_devwidth           = 8,
 96         .dev_physaddr           = 0x00000000,
 97         .dev_intlevel           = 0,
 98         .dev_intpolarity        = 0
 99 };
100 
101 static int ddma_memid;  /* id to above mem dma device */
102 
103 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw);
104 
105 
106 /*
107  *  compute BRG and DIV bits to setup spi clock based on main input clock rate
108  *  that was specified in platform data structure
109  *  according to au1550 datasheet:
110  *    psc_tempclk = psc_mainclk / (2 << DIV)
111  *    spiclk = psc_tempclk / (2 * (BRG + 1))
112  *    BRG valid range is 4..63
113  *    DIV valid range is 0..3
114  */
115 static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned speed_hz)
116 {
117         u32 mainclk_hz = hw->pdata->mainclk_hz;
118         u32 div, brg;
119 
120         for (div = 0; div < 4; div++) {
121                 brg = mainclk_hz / speed_hz / (4 << div);
122                 /* now we have BRG+1 in brg, so count with that */
123                 if (brg < (4 + 1)) {
124                         brg = (4 + 1);  /* speed_hz too big */
125                         break;          /* set lowest brg (div is == 0) */
126                 }
127                 if (brg <= (63 + 1))
128                         break;          /* we have valid brg and div */
129         }
130         if (div == 4) {
131                 div = 3;                /* speed_hz too small */
132                 brg = (63 + 1);         /* set highest brg and div */
133         }
134         brg--;
135         return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div);
136 }
137 
138 static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw)
139 {
140         hw->regs->psc_spimsk =
141                   PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO
142                 | PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO
143                 | PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD;
144         au_sync();
145 
146         hw->regs->psc_spievent =
147                   PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO
148                 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO
149                 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD;
150         au_sync();
151 }
152 
153 static void au1550_spi_reset_fifos(struct au1550_spi *hw)
154 {
155         u32 pcr;
156 
157         hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC;
158         au_sync();
159         do {
160                 pcr = hw->regs->psc_spipcr;
161                 au_sync();
162         } while (pcr != 0);
163 }
164 
165 /*
166  * dma transfers are used for the most common spi word size of 8-bits
167  * we cannot easily change already set up dma channels' width, so if we wanted
168  * dma support for more than 8-bit words (up to 24 bits), we would need to
169  * setup dma channels from scratch on each spi transfer, based on bits_per_word
170  * instead we have pre set up 8 bit dma channels supporting spi 4 to 8 bits
171  * transfers, and 9 to 24 bits spi transfers will be done in pio irq based mode
172  * callbacks to handle dma or pio are set up in au1550_spi_bits_handlers_set()
173  */
174 static void au1550_spi_chipsel(struct spi_device *spi, int value)
175 {
176         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
177         unsigned cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
178         u32 cfg, stat;
179 
180         switch (value) {
181         case BITBANG_CS_INACTIVE:
182                 if (hw->pdata->deactivate_cs)
183                         hw->pdata->deactivate_cs(hw->pdata, spi->chip_select,
184                                         cspol);
185                 break;
186 
187         case BITBANG_CS_ACTIVE:
188                 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
189 
190                 cfg = hw->regs->psc_spicfg;
191                 au_sync();
192                 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
193                 au_sync();
194 
195                 if (spi->mode & SPI_CPOL)
196                         cfg |= PSC_SPICFG_BI;
197                 else
198                         cfg &= ~PSC_SPICFG_BI;
199                 if (spi->mode & SPI_CPHA)
200                         cfg &= ~PSC_SPICFG_CDE;
201                 else
202                         cfg |= PSC_SPICFG_CDE;
203 
204                 if (spi->mode & SPI_LSB_FIRST)
205                         cfg |= PSC_SPICFG_MLF;
206                 else
207                         cfg &= ~PSC_SPICFG_MLF;
208 
209                 if (hw->usedma && spi->bits_per_word <= 8)
210                         cfg &= ~PSC_SPICFG_DD_DISABLE;
211                 else
212                         cfg |= PSC_SPICFG_DD_DISABLE;
213                 cfg = PSC_SPICFG_CLR_LEN(cfg);
214                 cfg |= PSC_SPICFG_SET_LEN(spi->bits_per_word);
215 
216                 cfg = PSC_SPICFG_CLR_BAUD(cfg);
217                 cfg &= ~PSC_SPICFG_SET_DIV(3);
218                 cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz);
219 
220                 hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE;
221                 au_sync();
222                 do {
223                         stat = hw->regs->psc_spistat;
224                         au_sync();
225                 } while ((stat & PSC_SPISTAT_DR) == 0);
226 
227                 if (hw->pdata->activate_cs)
228                         hw->pdata->activate_cs(hw->pdata, spi->chip_select,
229                                         cspol);
230                 break;
231         }
232 }
233 
234 static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
235 {
236         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
237         unsigned bpw, hz;
238         u32 cfg, stat;
239 
240         bpw = spi->bits_per_word;
241         hz = spi->max_speed_hz;
242         if (t) {
243                 if (t->bits_per_word)
244                         bpw = t->bits_per_word;
245                 if (t->speed_hz)
246                         hz = t->speed_hz;
247         }
248 
249         if (!hz)
250                 return -EINVAL;
251 
252         au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
253 
254         cfg = hw->regs->psc_spicfg;
255         au_sync();
256         hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
257         au_sync();
258 
259         if (hw->usedma && bpw <= 8)
260                 cfg &= ~PSC_SPICFG_DD_DISABLE;
261         else
262                 cfg |= PSC_SPICFG_DD_DISABLE;
263         cfg = PSC_SPICFG_CLR_LEN(cfg);
264         cfg |= PSC_SPICFG_SET_LEN(bpw);
265 
266         cfg = PSC_SPICFG_CLR_BAUD(cfg);
267         cfg &= ~PSC_SPICFG_SET_DIV(3);
268         cfg |= au1550_spi_baudcfg(hw, hz);
269 
270         hw->regs->psc_spicfg = cfg;
271         au_sync();
272 
273         if (cfg & PSC_SPICFG_DE_ENABLE) {
274                 do {
275                         stat = hw->regs->psc_spistat;
276                         au_sync();
277                 } while ((stat & PSC_SPISTAT_DR) == 0);
278         }
279 
280         au1550_spi_reset_fifos(hw);
281         au1550_spi_mask_ack_all(hw);
282         return 0;
283 }
284 
285 /*
286  * for dma spi transfers, we have to setup rx channel, otherwise there is
287  * no reliable way how to recognize that spi transfer is done
288  * dma complete callbacks are called before real spi transfer is finished
289  * and if only tx dma channel is set up (and rx fifo overflow event masked)
290  * spi master done event irq is not generated unless rx fifo is empty (emptied)
291  * so we need rx tmp buffer to use for rx dma if user does not provide one
292  */
293 static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned size)
294 {
295         hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL);
296         if (!hw->dma_rx_tmpbuf)
297                 return -ENOMEM;
298         hw->dma_rx_tmpbuf_size = size;
299         hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf,
300                         size, DMA_FROM_DEVICE);
301         if (dma_mapping_error(hw->dev, hw->dma_rx_tmpbuf_addr)) {
302                 kfree(hw->dma_rx_tmpbuf);
303                 hw->dma_rx_tmpbuf = 0;
304                 hw->dma_rx_tmpbuf_size = 0;
305                 return -EFAULT;
306         }
307         return 0;
308 }
309 
310 static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw)
311 {
312         dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr,
313                         hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE);
314         kfree(hw->dma_rx_tmpbuf);
315         hw->dma_rx_tmpbuf = 0;
316         hw->dma_rx_tmpbuf_size = 0;
317 }
318 
319 static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t)
320 {
321         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
322         dma_addr_t dma_tx_addr;
323         dma_addr_t dma_rx_addr;
324         u32 res;
325 
326         hw->len = t->len;
327         hw->tx_count = 0;
328         hw->rx_count = 0;
329 
330         hw->tx = t->tx_buf;
331         hw->rx = t->rx_buf;
332         dma_tx_addr = t->tx_dma;
333         dma_rx_addr = t->rx_dma;
334 
335         /*
336          * check if buffers are already dma mapped, map them otherwise:
337          * - first map the TX buffer, so cache data gets written to memory
338          * - then map the RX buffer, so that cache entries (with
339          *   soon-to-be-stale data) get removed
340          * use rx buffer in place of tx if tx buffer was not provided
341          * use temp rx buffer (preallocated or realloc to fit) for rx dma
342          */
343         if (t->tx_buf) {
344                 if (t->tx_dma == 0) {   /* if DMA_ADDR_INVALID, map it */
345                         dma_tx_addr = dma_map_single(hw->dev,
346                                         (void *)t->tx_buf,
347                                         t->len, DMA_TO_DEVICE);
348                         if (dma_mapping_error(hw->dev, dma_tx_addr))
349                                 dev_err(hw->dev, "tx dma map error\n");
350                 }
351         }
352 
353         if (t->rx_buf) {
354                 if (t->rx_dma == 0) {   /* if DMA_ADDR_INVALID, map it */
355                         dma_rx_addr = dma_map_single(hw->dev,
356                                         (void *)t->rx_buf,
357                                         t->len, DMA_FROM_DEVICE);
358                         if (dma_mapping_error(hw->dev, dma_rx_addr))
359                                 dev_err(hw->dev, "rx dma map error\n");
360                 }
361         } else {
362                 if (t->len > hw->dma_rx_tmpbuf_size) {
363                         int ret;
364 
365                         au1550_spi_dma_rxtmp_free(hw);
366                         ret = au1550_spi_dma_rxtmp_alloc(hw, max(t->len,
367                                         AU1550_SPI_DMA_RXTMP_MINSIZE));
368                         if (ret < 0)
369                                 return ret;
370                 }
371                 hw->rx = hw->dma_rx_tmpbuf;
372                 dma_rx_addr = hw->dma_rx_tmpbuf_addr;
373                 dma_sync_single_for_device(hw->dev, dma_rx_addr,
374                         t->len, DMA_FROM_DEVICE);
375         }
376 
377         if (!t->tx_buf) {
378                 dma_sync_single_for_device(hw->dev, dma_rx_addr,
379                                 t->len, DMA_BIDIRECTIONAL);
380                 hw->tx = hw->rx;
381         }
382 
383         /* put buffers on the ring */
384         res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, virt_to_phys(hw->rx),
385                                     t->len, DDMA_FLAGS_IE);
386         if (!res)
387                 dev_err(hw->dev, "rx dma put dest error\n");
388 
389         res = au1xxx_dbdma_put_source(hw->dma_tx_ch, virt_to_phys(hw->tx),
390                                       t->len, DDMA_FLAGS_IE);
391         if (!res)
392                 dev_err(hw->dev, "tx dma put source error\n");
393 
394         au1xxx_dbdma_start(hw->dma_rx_ch);
395         au1xxx_dbdma_start(hw->dma_tx_ch);
396 
397         /* by default enable nearly all events interrupt */
398         hw->regs->psc_spimsk = PSC_SPIMSK_SD;
399         au_sync();
400 
401         /* start the transfer */
402         hw->regs->psc_spipcr = PSC_SPIPCR_MS;
403         au_sync();
404 
405         wait_for_completion(&hw->master_done);
406 
407         au1xxx_dbdma_stop(hw->dma_tx_ch);
408         au1xxx_dbdma_stop(hw->dma_rx_ch);
409 
410         if (!t->rx_buf) {
411                 /* using the temporal preallocated and premapped buffer */
412                 dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len,
413                         DMA_FROM_DEVICE);
414         }
415         /* unmap buffers if mapped above */
416         if (t->rx_buf && t->rx_dma == 0 )
417                 dma_unmap_single(hw->dev, dma_rx_addr, t->len,
418                         DMA_FROM_DEVICE);
419         if (t->tx_buf && t->tx_dma == 0 )
420                 dma_unmap_single(hw->dev, dma_tx_addr, t->len,
421                         DMA_TO_DEVICE);
422 
423         return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
424 }
425 
426 static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw)
427 {
428         u32 stat, evnt;
429 
430         stat = hw->regs->psc_spistat;
431         evnt = hw->regs->psc_spievent;
432         au_sync();
433         if ((stat & PSC_SPISTAT_DI) == 0) {
434                 dev_err(hw->dev, "Unexpected IRQ!\n");
435                 return IRQ_NONE;
436         }
437 
438         if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
439                                 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
440                                 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD))
441                         != 0) {
442                 /*
443                  * due to an spi error we consider transfer as done,
444                  * so mask all events until before next transfer start
445                  * and stop the possibly running dma immediately
446                  */
447                 au1550_spi_mask_ack_all(hw);
448                 au1xxx_dbdma_stop(hw->dma_rx_ch);
449                 au1xxx_dbdma_stop(hw->dma_tx_ch);
450 
451                 /* get number of transferred bytes */
452                 hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch);
453                 hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch);
454 
455                 au1xxx_dbdma_reset(hw->dma_rx_ch);
456                 au1xxx_dbdma_reset(hw->dma_tx_ch);
457                 au1550_spi_reset_fifos(hw);
458 
459                 if (evnt == PSC_SPIEVNT_RO)
460                         dev_err(hw->dev,
461                                 "dma transfer: receive FIFO overflow!\n");
462                 else
463                         dev_err(hw->dev,
464                                 "dma transfer: unexpected SPI error "
465                                 "(event=0x%x stat=0x%x)!\n", evnt, stat);
466 
467                 complete(&hw->master_done);
468                 return IRQ_HANDLED;
469         }
470 
471         if ((evnt & PSC_SPIEVNT_MD) != 0) {
472                 /* transfer completed successfully */
473                 au1550_spi_mask_ack_all(hw);
474                 hw->rx_count = hw->len;
475                 hw->tx_count = hw->len;
476                 complete(&hw->master_done);
477         }
478         return IRQ_HANDLED;
479 }
480 
481 
482 /* routines to handle different word sizes in pio mode */
483 #define AU1550_SPI_RX_WORD(size, mask)                                  \
484 static void au1550_spi_rx_word_##size(struct au1550_spi *hw)            \
485 {                                                                       \
486         u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask);             \
487         au_sync();                                                      \
488         if (hw->rx) {                                                   \
489                 *(u##size *)hw->rx = (u##size)fifoword;                 \
490                 hw->rx += (size) / 8;                                   \
491         }                                                               \
492         hw->rx_count += (size) / 8;                                     \
493 }
494 
495 #define AU1550_SPI_TX_WORD(size, mask)                                  \
496 static void au1550_spi_tx_word_##size(struct au1550_spi *hw)            \
497 {                                                                       \
498         u32 fifoword = 0;                                               \
499         if (hw->tx) {                                                   \
500                 fifoword = *(u##size *)hw->tx & (u32)(mask);            \
501                 hw->tx += (size) / 8;                                   \
502         }                                                               \
503         hw->tx_count += (size) / 8;                                     \
504         if (hw->tx_count >= hw->len)                                    \
505                 fifoword |= PSC_SPITXRX_LC;                             \
506         hw->regs->psc_spitxrx = fifoword;                               \
507         au_sync();                                                      \
508 }
509 
510 AU1550_SPI_RX_WORD(8,0xff)
511 AU1550_SPI_RX_WORD(16,0xffff)
512 AU1550_SPI_RX_WORD(32,0xffffff)
513 AU1550_SPI_TX_WORD(8,0xff)
514 AU1550_SPI_TX_WORD(16,0xffff)
515 AU1550_SPI_TX_WORD(32,0xffffff)
516 
517 static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t)
518 {
519         u32 stat, mask;
520         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
521 
522         hw->tx = t->tx_buf;
523         hw->rx = t->rx_buf;
524         hw->len = t->len;
525         hw->tx_count = 0;
526         hw->rx_count = 0;
527 
528         /* by default enable nearly all events after filling tx fifo */
529         mask = PSC_SPIMSK_SD;
530 
531         /* fill the transmit FIFO */
532         while (hw->tx_count < hw->len) {
533 
534                 hw->tx_word(hw);
535 
536                 if (hw->tx_count >= hw->len) {
537                         /* mask tx fifo request interrupt as we are done */
538                         mask |= PSC_SPIMSK_TR;
539                 }
540 
541                 stat = hw->regs->psc_spistat;
542                 au_sync();
543                 if (stat & PSC_SPISTAT_TF)
544                         break;
545         }
546 
547         /* enable event interrupts */
548         hw->regs->psc_spimsk = mask;
549         au_sync();
550 
551         /* start the transfer */
552         hw->regs->psc_spipcr = PSC_SPIPCR_MS;
553         au_sync();
554 
555         wait_for_completion(&hw->master_done);
556 
557         return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
558 }
559 
560 static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
561 {
562         int busy;
563         u32 stat, evnt;
564 
565         stat = hw->regs->psc_spistat;
566         evnt = hw->regs->psc_spievent;
567         au_sync();
568         if ((stat & PSC_SPISTAT_DI) == 0) {
569                 dev_err(hw->dev, "Unexpected IRQ!\n");
570                 return IRQ_NONE;
571         }
572 
573         if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
574                                 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
575                                 | PSC_SPIEVNT_SD))
576                         != 0) {
577                 /*
578                  * due to an error we consider transfer as done,
579                  * so mask all events until before next transfer start
580                  */
581                 au1550_spi_mask_ack_all(hw);
582                 au1550_spi_reset_fifos(hw);
583                 dev_err(hw->dev,
584                         "pio transfer: unexpected SPI error "
585                         "(event=0x%x stat=0x%x)!\n", evnt, stat);
586                 complete(&hw->master_done);
587                 return IRQ_HANDLED;
588         }
589 
590         /*
591          * while there is something to read from rx fifo
592          * or there is a space to write to tx fifo:
593          */
594         do {
595                 busy = 0;
596                 stat = hw->regs->psc_spistat;
597                 au_sync();
598 
599                 /*
600                  * Take care to not let the Rx FIFO overflow.
601                  *
602                  * We only write a byte if we have read one at least. Initially,
603                  * the write fifo is full, so we should read from the read fifo
604                  * first.
605                  * In case we miss a word from the read fifo, we should get a
606                  * RO event and should back out.
607                  */
608                 if (!(stat & PSC_SPISTAT_RE) && hw->rx_count < hw->len) {
609                         hw->rx_word(hw);
610                         busy = 1;
611 
612                         if (!(stat & PSC_SPISTAT_TF) && hw->tx_count < hw->len)
613                                 hw->tx_word(hw);
614                 }
615         } while (busy);
616 
617         hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR;
618         au_sync();
619 
620         /*
621          * Restart the SPI transmission in case of a transmit underflow.
622          * This seems to work despite the notes in the Au1550 data book
623          * of Figure 8-4 with flowchart for SPI master operation:
624          *
625          * """Note 1: An XFR Error Interrupt occurs, unless masked,
626          * for any of the following events: Tx FIFO Underflow,
627          * Rx FIFO Overflow, or Multiple-master Error
628          *    Note 2: In case of a Tx Underflow Error, all zeroes are
629          * transmitted."""
630          *
631          * By simply restarting the spi transfer on Tx Underflow Error,
632          * we assume that spi transfer was paused instead of zeroes
633          * transmittion mentioned in the Note 2 of Au1550 data book.
634          */
635         if (evnt & PSC_SPIEVNT_TU) {
636                 hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD;
637                 au_sync();
638                 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
639                 au_sync();
640         }
641 
642         if (hw->rx_count >= hw->len) {
643                 /* transfer completed successfully */
644                 au1550_spi_mask_ack_all(hw);
645                 complete(&hw->master_done);
646         }
647         return IRQ_HANDLED;
648 }
649 
650 static int au1550_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
651 {
652         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
653         return hw->txrx_bufs(spi, t);
654 }
655 
656 static irqreturn_t au1550_spi_irq(int irq, void *dev)
657 {
658         struct au1550_spi *hw = dev;
659         return hw->irq_callback(hw);
660 }
661 
662 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw)
663 {
664         if (bpw <= 8) {
665                 if (hw->usedma) {
666                         hw->txrx_bufs = &au1550_spi_dma_txrxb;
667                         hw->irq_callback = &au1550_spi_dma_irq_callback;
668                 } else {
669                         hw->rx_word = &au1550_spi_rx_word_8;
670                         hw->tx_word = &au1550_spi_tx_word_8;
671                         hw->txrx_bufs = &au1550_spi_pio_txrxb;
672                         hw->irq_callback = &au1550_spi_pio_irq_callback;
673                 }
674         } else if (bpw <= 16) {
675                 hw->rx_word = &au1550_spi_rx_word_16;
676                 hw->tx_word = &au1550_spi_tx_word_16;
677                 hw->txrx_bufs = &au1550_spi_pio_txrxb;
678                 hw->irq_callback = &au1550_spi_pio_irq_callback;
679         } else {
680                 hw->rx_word = &au1550_spi_rx_word_32;
681                 hw->tx_word = &au1550_spi_tx_word_32;
682                 hw->txrx_bufs = &au1550_spi_pio_txrxb;
683                 hw->irq_callback = &au1550_spi_pio_irq_callback;
684         }
685 }
686 
687 static void au1550_spi_setup_psc_as_spi(struct au1550_spi *hw)
688 {
689         u32 stat, cfg;
690 
691         /* set up the PSC for SPI mode */
692         hw->regs->psc_ctrl = PSC_CTRL_DISABLE;
693         au_sync();
694         hw->regs->psc_sel = PSC_SEL_PS_SPIMODE;
695         au_sync();
696 
697         hw->regs->psc_spicfg = 0;
698         au_sync();
699 
700         hw->regs->psc_ctrl = PSC_CTRL_ENABLE;
701         au_sync();
702 
703         do {
704                 stat = hw->regs->psc_spistat;
705                 au_sync();
706         } while ((stat & PSC_SPISTAT_SR) == 0);
707 
708 
709         cfg = hw->usedma ? 0 : PSC_SPICFG_DD_DISABLE;
710         cfg |= PSC_SPICFG_SET_LEN(8);
711         cfg |= PSC_SPICFG_RT_FIFO8 | PSC_SPICFG_TT_FIFO8;
712         /* use minimal allowed brg and div values as initial setting: */
713         cfg |= PSC_SPICFG_SET_BAUD(4) | PSC_SPICFG_SET_DIV(0);
714 
715 #ifdef AU1550_SPI_DEBUG_LOOPBACK
716         cfg |= PSC_SPICFG_LB;
717 #endif
718 
719         hw->regs->psc_spicfg = cfg;
720         au_sync();
721 
722         au1550_spi_mask_ack_all(hw);
723 
724         hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE;
725         au_sync();
726 
727         do {
728                 stat = hw->regs->psc_spistat;
729                 au_sync();
730         } while ((stat & PSC_SPISTAT_DR) == 0);
731 
732         au1550_spi_reset_fifos(hw);
733 }
734 
735 
736 static int au1550_spi_probe(struct platform_device *pdev)
737 {
738         struct au1550_spi *hw;
739         struct spi_master *master;
740         struct resource *r;
741         int err = 0;
742 
743         master = spi_alloc_master(&pdev->dev, sizeof(struct au1550_spi));
744         if (master == NULL) {
745                 dev_err(&pdev->dev, "No memory for spi_master\n");
746                 err = -ENOMEM;
747                 goto err_nomem;
748         }
749 
750         /* the spi->mode bits understood by this driver: */
751         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
752         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 24);
753 
754         hw = spi_master_get_devdata(master);
755 
756         hw->master = master;
757         hw->pdata = dev_get_platdata(&pdev->dev);
758         hw->dev = &pdev->dev;
759 
760         if (hw->pdata == NULL) {
761                 dev_err(&pdev->dev, "No platform data supplied\n");
762                 err = -ENOENT;
763                 goto err_no_pdata;
764         }
765 
766         r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
767         if (!r) {
768                 dev_err(&pdev->dev, "no IRQ\n");
769                 err = -ENODEV;
770                 goto err_no_iores;
771         }
772         hw->irq = r->start;
773 
774         hw->usedma = 0;
775         r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
776         if (r) {
777                 hw->dma_tx_id = r->start;
778                 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
779                 if (r) {
780                         hw->dma_rx_id = r->start;
781                         if (usedma && ddma_memid) {
782                                 if (pdev->dev.dma_mask == NULL)
783                                         dev_warn(&pdev->dev, "no dma mask\n");
784                                 else
785                                         hw->usedma = 1;
786                         }
787                 }
788         }
789 
790         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
791         if (!r) {
792                 dev_err(&pdev->dev, "no mmio resource\n");
793                 err = -ENODEV;
794                 goto err_no_iores;
795         }
796 
797         hw->ioarea = request_mem_region(r->start, sizeof(psc_spi_t),
798                                         pdev->name);
799         if (!hw->ioarea) {
800                 dev_err(&pdev->dev, "Cannot reserve iomem region\n");
801                 err = -ENXIO;
802                 goto err_no_iores;
803         }
804 
805         hw->regs = (psc_spi_t __iomem *)ioremap(r->start, sizeof(psc_spi_t));
806         if (!hw->regs) {
807                 dev_err(&pdev->dev, "cannot ioremap\n");
808                 err = -ENXIO;
809                 goto err_ioremap;
810         }
811 
812         platform_set_drvdata(pdev, hw);
813 
814         init_completion(&hw->master_done);
815 
816         hw->bitbang.master = hw->master;
817         hw->bitbang.setup_transfer = au1550_spi_setupxfer;
818         hw->bitbang.chipselect = au1550_spi_chipsel;
819         hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs;
820 
821         if (hw->usedma) {
822                 hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(ddma_memid,
823                         hw->dma_tx_id, NULL, (void *)hw);
824                 if (hw->dma_tx_ch == 0) {
825                         dev_err(&pdev->dev,
826                                 "Cannot allocate tx dma channel\n");
827                         err = -ENXIO;
828                         goto err_no_txdma;
829                 }
830                 au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8);
831                 if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch,
832                         AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
833                         dev_err(&pdev->dev,
834                                 "Cannot allocate tx dma descriptors\n");
835                         err = -ENXIO;
836                         goto err_no_txdma_descr;
837                 }
838 
839 
840                 hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id,
841                         ddma_memid, NULL, (void *)hw);
842                 if (hw->dma_rx_ch == 0) {
843                         dev_err(&pdev->dev,
844                                 "Cannot allocate rx dma channel\n");
845                         err = -ENXIO;
846                         goto err_no_rxdma;
847                 }
848                 au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8);
849                 if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch,
850                         AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
851                         dev_err(&pdev->dev,
852                                 "Cannot allocate rx dma descriptors\n");
853                         err = -ENXIO;
854                         goto err_no_rxdma_descr;
855                 }
856 
857                 err = au1550_spi_dma_rxtmp_alloc(hw,
858                         AU1550_SPI_DMA_RXTMP_MINSIZE);
859                 if (err < 0) {
860                         dev_err(&pdev->dev,
861                                 "Cannot allocate initial rx dma tmp buffer\n");
862                         goto err_dma_rxtmp_alloc;
863                 }
864         }
865 
866         au1550_spi_bits_handlers_set(hw, 8);
867 
868         err = request_irq(hw->irq, au1550_spi_irq, 0, pdev->name, hw);
869         if (err) {
870                 dev_err(&pdev->dev, "Cannot claim IRQ\n");
871                 goto err_no_irq;
872         }
873 
874         master->bus_num = pdev->id;
875         master->num_chipselect = hw->pdata->num_chipselect;
876 
877         /*
878          *  precompute valid range for spi freq - from au1550 datasheet:
879          *    psc_tempclk = psc_mainclk / (2 << DIV)
880          *    spiclk = psc_tempclk / (2 * (BRG + 1))
881          *    BRG valid range is 4..63
882          *    DIV valid range is 0..3
883          *  round the min and max frequencies to values that would still
884          *  produce valid brg and div
885          */
886         {
887                 int min_div = (2 << 0) * (2 * (4 + 1));
888                 int max_div = (2 << 3) * (2 * (63 + 1));
889                 master->max_speed_hz = hw->pdata->mainclk_hz / min_div;
890                 master->min_speed_hz =
891                                 hw->pdata->mainclk_hz / (max_div + 1) + 1;
892         }
893 
894         au1550_spi_setup_psc_as_spi(hw);
895 
896         err = spi_bitbang_start(&hw->bitbang);
897         if (err) {
898                 dev_err(&pdev->dev, "Failed to register SPI master\n");
899                 goto err_register;
900         }
901 
902         dev_info(&pdev->dev,
903                 "spi master registered: bus_num=%d num_chipselect=%d\n",
904                 master->bus_num, master->num_chipselect);
905 
906         return 0;
907 
908 err_register:
909         free_irq(hw->irq, hw);
910 
911 err_no_irq:
912         au1550_spi_dma_rxtmp_free(hw);
913 
914 err_dma_rxtmp_alloc:
915 err_no_rxdma_descr:
916         if (hw->usedma)
917                 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
918 
919 err_no_rxdma:
920 err_no_txdma_descr:
921         if (hw->usedma)
922                 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
923 
924 err_no_txdma:
925         iounmap((void __iomem *)hw->regs);
926 
927 err_ioremap:
928         release_resource(hw->ioarea);
929         kfree(hw->ioarea);
930 
931 err_no_iores:
932 err_no_pdata:
933         spi_master_put(hw->master);
934 
935 err_nomem:
936         return err;
937 }
938 
939 static int au1550_spi_remove(struct platform_device *pdev)
940 {
941         struct au1550_spi *hw = platform_get_drvdata(pdev);
942 
943         dev_info(&pdev->dev, "spi master remove: bus_num=%d\n",
944                 hw->master->bus_num);
945 
946         spi_bitbang_stop(&hw->bitbang);
947         free_irq(hw->irq, hw);
948         iounmap((void __iomem *)hw->regs);
949         release_resource(hw->ioarea);
950         kfree(hw->ioarea);
951 
952         if (hw->usedma) {
953                 au1550_spi_dma_rxtmp_free(hw);
954                 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
955                 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
956         }
957 
958         spi_master_put(hw->master);
959         return 0;
960 }
961 
962 /* work with hotplug and coldplug */
963 MODULE_ALIAS("platform:au1550-spi");
964 
965 static struct platform_driver au1550_spi_drv = {
966         .probe = au1550_spi_probe,
967         .remove = au1550_spi_remove,
968         .driver = {
969                 .name = "au1550-spi",
970                 .owner = THIS_MODULE,
971         },
972 };
973 
974 static int __init au1550_spi_init(void)
975 {
976         /*
977          * create memory device with 8 bits dev_devwidth
978          * needed for proper byte ordering to spi fifo
979          */
980         switch (alchemy_get_cputype()) {
981         case ALCHEMY_CPU_AU1550:
982         case ALCHEMY_CPU_AU1200:
983         case ALCHEMY_CPU_AU1300:
984                 break;
985         default:
986                 return -ENODEV;
987         }
988 
989         if (usedma) {
990                 ddma_memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev);
991                 if (!ddma_memid)
992                         printk(KERN_ERR "au1550-spi: cannot add memory"
993                                         "dbdma device\n");
994         }
995         return platform_driver_register(&au1550_spi_drv);
996 }
997 module_init(au1550_spi_init);
998 
999 static void __exit au1550_spi_exit(void)
1000 {
1001         if (usedma && ddma_memid)
1002                 au1xxx_ddma_del_device(ddma_memid);
1003         platform_driver_unregister(&au1550_spi_drv);
1004 }
1005 module_exit(au1550_spi_exit);
1006 
1007 MODULE_DESCRIPTION("Au1550 PSC SPI Driver");
1008 MODULE_AUTHOR("Jan Nikitenko <jan.nikitenko@gmail.com>");
1009 MODULE_LICENSE("GPL");
1010 

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