Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/drivers/spi/spi-ath79.c

  1 /*
  2  * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
  3  *
  4  * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
  5  *
  6  * This driver has been based on the spi-gpio.c:
  7  *      Copyright (C) 2006,2008 David Brownell
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2 as
 11  * published by the Free Software Foundation.
 12  *
 13  */
 14 
 15 #include <linux/kernel.h>
 16 #include <linux/module.h>
 17 #include <linux/delay.h>
 18 #include <linux/spinlock.h>
 19 #include <linux/platform_device.h>
 20 #include <linux/io.h>
 21 #include <linux/spi/spi.h>
 22 #include <linux/spi/spi_bitbang.h>
 23 #include <linux/bitops.h>
 24 #include <linux/gpio.h>
 25 #include <linux/clk.h>
 26 #include <linux/err.h>
 27 
 28 #include <asm/mach-ath79/ar71xx_regs.h>
 29 #include <asm/mach-ath79/ath79_spi_platform.h>
 30 
 31 #define DRV_NAME        "ath79-spi"
 32 
 33 #define ATH79_SPI_RRW_DELAY_FACTOR      12000
 34 #define MHZ                             (1000 * 1000)
 35 
 36 struct ath79_spi {
 37         struct spi_bitbang      bitbang;
 38         u32                     ioc_base;
 39         u32                     reg_ctrl;
 40         void __iomem            *base;
 41         struct clk              *clk;
 42         unsigned                rrw_delay;
 43 };
 44 
 45 static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
 46 {
 47         return ioread32(sp->base + reg);
 48 }
 49 
 50 static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val)
 51 {
 52         iowrite32(val, sp->base + reg);
 53 }
 54 
 55 static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
 56 {
 57         return spi_master_get_devdata(spi->master);
 58 }
 59 
 60 static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs)
 61 {
 62         if (nsecs > sp->rrw_delay)
 63                 ndelay(nsecs - sp->rrw_delay);
 64 }
 65 
 66 static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
 67 {
 68         struct ath79_spi *sp = ath79_spidev_to_sp(spi);
 69         int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
 70 
 71         if (is_active) {
 72                 /* set initial clock polarity */
 73                 if (spi->mode & SPI_CPOL)
 74                         sp->ioc_base |= AR71XX_SPI_IOC_CLK;
 75                 else
 76                         sp->ioc_base &= ~AR71XX_SPI_IOC_CLK;
 77 
 78                 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
 79         }
 80 
 81         if (spi->chip_select) {
 82                 struct ath79_spi_controller_data *cdata = spi->controller_data;
 83 
 84                 /* SPI is normally active-low */
 85                 gpio_set_value(cdata->gpio, cs_high);
 86         } else {
 87                 if (cs_high)
 88                         sp->ioc_base |= AR71XX_SPI_IOC_CS0;
 89                 else
 90                         sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
 91 
 92                 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
 93         }
 94 
 95 }
 96 
 97 static void ath79_spi_enable(struct ath79_spi *sp)
 98 {
 99         /* enable GPIO mode */
100         ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
101 
102         /* save CTRL register */
103         sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
104         sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
105 
106         /* TODO: setup speed? */
107         ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
108 }
109 
110 static void ath79_spi_disable(struct ath79_spi *sp)
111 {
112         /* restore CTRL register */
113         ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
114         /* disable GPIO mode */
115         ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
116 }
117 
118 static int ath79_spi_setup_cs(struct spi_device *spi)
119 {
120         struct ath79_spi_controller_data *cdata;
121         int status;
122 
123         cdata = spi->controller_data;
124         if (spi->chip_select && !cdata)
125                 return -EINVAL;
126 
127         status = 0;
128         if (spi->chip_select) {
129                 unsigned long flags;
130 
131                 flags = GPIOF_DIR_OUT;
132                 if (spi->mode & SPI_CS_HIGH)
133                         flags |= GPIOF_INIT_LOW;
134                 else
135                         flags |= GPIOF_INIT_HIGH;
136 
137                 status = gpio_request_one(cdata->gpio, flags,
138                                           dev_name(&spi->dev));
139         }
140 
141         return status;
142 }
143 
144 static void ath79_spi_cleanup_cs(struct spi_device *spi)
145 {
146         if (spi->chip_select) {
147                 struct ath79_spi_controller_data *cdata = spi->controller_data;
148                 gpio_free(cdata->gpio);
149         }
150 }
151 
152 static int ath79_spi_setup(struct spi_device *spi)
153 {
154         int status = 0;
155 
156         if (!spi->controller_state) {
157                 status = ath79_spi_setup_cs(spi);
158                 if (status)
159                         return status;
160         }
161 
162         status = spi_bitbang_setup(spi);
163         if (status && !spi->controller_state)
164                 ath79_spi_cleanup_cs(spi);
165 
166         return status;
167 }
168 
169 static void ath79_spi_cleanup(struct spi_device *spi)
170 {
171         ath79_spi_cleanup_cs(spi);
172         spi_bitbang_cleanup(spi);
173 }
174 
175 static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs,
176                                u32 word, u8 bits)
177 {
178         struct ath79_spi *sp = ath79_spidev_to_sp(spi);
179         u32 ioc = sp->ioc_base;
180 
181         /* clock starts at inactive polarity */
182         for (word <<= (32 - bits); likely(bits); bits--) {
183                 u32 out;
184 
185                 if (word & (1 << 31))
186                         out = ioc | AR71XX_SPI_IOC_DO;
187                 else
188                         out = ioc & ~AR71XX_SPI_IOC_DO;
189 
190                 /* setup MSB (to slave) on trailing edge */
191                 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
192                 ath79_spi_delay(sp, nsecs);
193                 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
194                 ath79_spi_delay(sp, nsecs);
195                 if (bits == 1)
196                         ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
197 
198                 word <<= 1;
199         }
200 
201         return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
202 }
203 
204 static int ath79_spi_probe(struct platform_device *pdev)
205 {
206         struct spi_master *master;
207         struct ath79_spi *sp;
208         struct ath79_spi_platform_data *pdata;
209         struct resource *r;
210         unsigned long rate;
211         int ret;
212 
213         master = spi_alloc_master(&pdev->dev, sizeof(*sp));
214         if (master == NULL) {
215                 dev_err(&pdev->dev, "failed to allocate spi master\n");
216                 return -ENOMEM;
217         }
218 
219         sp = spi_master_get_devdata(master);
220         platform_set_drvdata(pdev, sp);
221 
222         pdata = dev_get_platdata(&pdev->dev);
223 
224         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
225         master->setup = ath79_spi_setup;
226         master->cleanup = ath79_spi_cleanup;
227         if (pdata) {
228                 master->bus_num = pdata->bus_num;
229                 master->num_chipselect = pdata->num_chipselect;
230         }
231 
232         sp->bitbang.master = master;
233         sp->bitbang.chipselect = ath79_spi_chipselect;
234         sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
235         sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
236         sp->bitbang.flags = SPI_CS_HIGH;
237 
238         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
239         if (r == NULL) {
240                 ret = -ENOENT;
241                 goto err_put_master;
242         }
243 
244         sp->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
245         if (!sp->base) {
246                 ret = -ENXIO;
247                 goto err_put_master;
248         }
249 
250         sp->clk = devm_clk_get(&pdev->dev, "ahb");
251         if (IS_ERR(sp->clk)) {
252                 ret = PTR_ERR(sp->clk);
253                 goto err_put_master;
254         }
255 
256         ret = clk_enable(sp->clk);
257         if (ret)
258                 goto err_put_master;
259 
260         rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
261         if (!rate) {
262                 ret = -EINVAL;
263                 goto err_clk_disable;
264         }
265 
266         sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
267         dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
268                 sp->rrw_delay);
269 
270         ath79_spi_enable(sp);
271         ret = spi_bitbang_start(&sp->bitbang);
272         if (ret)
273                 goto err_disable;
274 
275         return 0;
276 
277 err_disable:
278         ath79_spi_disable(sp);
279 err_clk_disable:
280         clk_disable(sp->clk);
281 err_put_master:
282         spi_master_put(sp->bitbang.master);
283 
284         return ret;
285 }
286 
287 static int ath79_spi_remove(struct platform_device *pdev)
288 {
289         struct ath79_spi *sp = platform_get_drvdata(pdev);
290 
291         spi_bitbang_stop(&sp->bitbang);
292         ath79_spi_disable(sp);
293         clk_disable(sp->clk);
294         spi_master_put(sp->bitbang.master);
295 
296         return 0;
297 }
298 
299 static void ath79_spi_shutdown(struct platform_device *pdev)
300 {
301         ath79_spi_remove(pdev);
302 }
303 
304 static struct platform_driver ath79_spi_driver = {
305         .probe          = ath79_spi_probe,
306         .remove         = ath79_spi_remove,
307         .shutdown       = ath79_spi_shutdown,
308         .driver         = {
309                 .name   = DRV_NAME,
310                 .owner  = THIS_MODULE,
311         },
312 };
313 module_platform_driver(ath79_spi_driver);
314 
315 MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
316 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
317 MODULE_LICENSE("GPL v2");
318 MODULE_ALIAS("platform:" DRV_NAME);
319 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us