Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/serial/8250.c

  1 /*
  2  *  linux/drivers/char/8250.c
  3  *
  4  *  Driver for 8250/16550-type serial ports
  5  *
  6  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
  7  *
  8  *  Copyright (C) 2001 Russell King.
  9  *
 10  * This program is free software; you can redistribute it and/or modify
 11  * it under the terms of the GNU General Public License as published by
 12  * the Free Software Foundation; either version 2 of the License, or
 13  * (at your option) any later version.
 14  *
 15  * A note about mapbase / membase
 16  *
 17  *  mapbase is the physical address of the IO port.
 18  *  membase is an 'ioremapped' cookie.
 19  */
 20 
 21 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 22 #define SUPPORT_SYSRQ
 23 #endif
 24 
 25 #include <linux/module.h>
 26 #include <linux/moduleparam.h>
 27 #include <linux/ioport.h>
 28 #include <linux/init.h>
 29 #include <linux/console.h>
 30 #include <linux/sysrq.h>
 31 #include <linux/delay.h>
 32 #include <linux/platform_device.h>
 33 #include <linux/tty.h>
 34 #include <linux/tty_flip.h>
 35 #include <linux/serial_reg.h>
 36 #include <linux/serial_core.h>
 37 #include <linux/serial.h>
 38 #include <linux/serial_8250.h>
 39 #include <linux/nmi.h>
 40 #include <linux/mutex.h>
 41 
 42 #include <asm/io.h>
 43 #include <asm/irq.h>
 44 
 45 #include "8250.h"
 46 
 47 #ifdef CONFIG_SPARC
 48 #include "suncore.h"
 49 #endif
 50 
 51 /*
 52  * Configuration:
 53  *   share_irqs - whether we pass IRQF_SHARED to request_irq().  This option
 54  *                is unsafe when used on edge-triggered interrupts.
 55  */
 56 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
 57 
 58 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
 59 
 60 static struct uart_driver serial8250_reg;
 61 
 62 static int serial_index(struct uart_port *port)
 63 {
 64         return (serial8250_reg.minor - 64) + port->line;
 65 }
 66 
 67 static unsigned int skip_txen_test; /* force skip of txen test at init time */
 68 
 69 /*
 70  * Debugging.
 71  */
 72 #if 0
 73 #define DEBUG_AUTOCONF(fmt...)  printk(fmt)
 74 #else
 75 #define DEBUG_AUTOCONF(fmt...)  do { } while (0)
 76 #endif
 77 
 78 #if 0
 79 #define DEBUG_INTR(fmt...)      printk(fmt)
 80 #else
 81 #define DEBUG_INTR(fmt...)      do { } while (0)
 82 #endif
 83 
 84 #define PASS_LIMIT      256
 85 
 86 #define BOTH_EMPTY      (UART_LSR_TEMT | UART_LSR_THRE)
 87 
 88 
 89 /*
 90  * We default to IRQ0 for the "no irq" hack.   Some
 91  * machine types want others as well - they're free
 92  * to redefine this in their header file.
 93  */
 94 #define is_real_interrupt(irq)  ((irq) != 0)
 95 
 96 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
 97 #define CONFIG_SERIAL_DETECT_IRQ 1
 98 #endif
 99 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
100 #define CONFIG_SERIAL_MANY_PORTS 1
101 #endif
102 
103 /*
104  * HUB6 is always on.  This will be removed once the header
105  * files have been cleaned.
106  */
107 #define CONFIG_HUB6 1
108 
109 #include <asm/serial.h>
110 /*
111  * SERIAL_PORT_DFNS tells us about built-in ports that have no
112  * standard enumeration mechanism.   Platforms that can find all
113  * serial ports via mechanisms like ACPI or PCI need not supply it.
114  */
115 #ifndef SERIAL_PORT_DFNS
116 #define SERIAL_PORT_DFNS
117 #endif
118 
119 static const struct old_serial_port old_serial_port[] = {
120         SERIAL_PORT_DFNS /* defined in asm/serial.h */
121 };
122 
123 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
124 
125 #ifdef CONFIG_SERIAL_8250_RSA
126 
127 #define PORT_RSA_MAX 4
128 static unsigned long probe_rsa[PORT_RSA_MAX];
129 static unsigned int probe_rsa_count;
130 #endif /* CONFIG_SERIAL_8250_RSA  */
131 
132 struct uart_8250_port {
133         struct uart_port        port;
134         struct timer_list       timer;          /* "no irq" timer */
135         struct list_head        list;           /* ports on this IRQ */
136         unsigned short          capabilities;   /* port capabilities */
137         unsigned short          bugs;           /* port bugs */
138         unsigned int            tx_loadsz;      /* transmit fifo load size */
139         unsigned char           acr;
140         unsigned char           ier;
141         unsigned char           lcr;
142         unsigned char           mcr;
143         unsigned char           mcr_mask;       /* mask of user bits */
144         unsigned char           mcr_force;      /* mask of forced bits */
145         unsigned char           cur_iotype;     /* Running I/O type */
146 
147         /*
148          * Some bits in registers are cleared on a read, so they must
149          * be saved whenever the register is read but the bits will not
150          * be immediately processed.
151          */
152 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
153         unsigned char           lsr_saved_flags;
154 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
155         unsigned char           msr_saved_flags;
156 
157         /*
158          * We provide a per-port pm hook.
159          */
160         void                    (*pm)(struct uart_port *port,
161                                       unsigned int state, unsigned int old);
162 };
163 
164 struct irq_info {
165         struct                  hlist_node node;
166         int                     irq;
167         spinlock_t              lock;   /* Protects list not the hash */
168         struct list_head        *head;
169 };
170 
171 #define NR_IRQ_HASH             32      /* Can be adjusted later */
172 static struct hlist_head irq_lists[NR_IRQ_HASH];
173 static DEFINE_MUTEX(hash_mutex);        /* Used to walk the hash */
174 
175 /*
176  * Here we define the default xmit fifo size used for each type of UART.
177  */
178 static const struct serial8250_config uart_config[] = {
179         [PORT_UNKNOWN] = {
180                 .name           = "unknown",
181                 .fifo_size      = 1,
182                 .tx_loadsz      = 1,
183         },
184         [PORT_8250] = {
185                 .name           = "8250",
186                 .fifo_size      = 1,
187                 .tx_loadsz      = 1,
188         },
189         [PORT_16450] = {
190                 .name           = "16450",
191                 .fifo_size      = 1,
192                 .tx_loadsz      = 1,
193         },
194         [PORT_16550] = {
195                 .name           = "16550",
196                 .fifo_size      = 1,
197                 .tx_loadsz      = 1,
198         },
199         [PORT_16550A] = {
200                 .name           = "16550A",
201                 .fifo_size      = 16,
202                 .tx_loadsz      = 16,
203                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
204                 .flags          = UART_CAP_FIFO,
205         },
206         [PORT_CIRRUS] = {
207                 .name           = "Cirrus",
208                 .fifo_size      = 1,
209                 .tx_loadsz      = 1,
210         },
211         [PORT_16650] = {
212                 .name           = "ST16650",
213                 .fifo_size      = 1,
214                 .tx_loadsz      = 1,
215                 .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
216         },
217         [PORT_16650V2] = {
218                 .name           = "ST16650V2",
219                 .fifo_size      = 32,
220                 .tx_loadsz      = 16,
221                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
222                                   UART_FCR_T_TRIG_00,
223                 .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
224         },
225         [PORT_16750] = {
226                 .name           = "TI16750",
227                 .fifo_size      = 64,
228                 .tx_loadsz      = 64,
229                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
230                                   UART_FCR7_64BYTE,
231                 .flags          = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
232         },
233         [PORT_STARTECH] = {
234                 .name           = "Startech",
235                 .fifo_size      = 1,
236                 .tx_loadsz      = 1,
237         },
238         [PORT_16C950] = {
239                 .name           = "16C950/954",
240                 .fifo_size      = 128,
241                 .tx_loadsz      = 128,
242                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
243                 .flags          = UART_CAP_FIFO,
244         },
245         [PORT_16654] = {
246                 .name           = "ST16654",
247                 .fifo_size      = 64,
248                 .tx_loadsz      = 32,
249                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
250                                   UART_FCR_T_TRIG_10,
251                 .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
252         },
253         [PORT_16850] = {
254                 .name           = "XR16850",
255                 .fifo_size      = 128,
256                 .tx_loadsz      = 128,
257                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
258                 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
259                 .flags          = UART_CAP_FIFO | UART_CAP_SLEEP,
260         },
261         [PORT_RSA] = {
262                 .name           = "RSA",
263                 .fifo_size      = 2048,
264                 .tx_loadsz      = 2048,
265                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
266                 .flags          = UART_CAP_FIFO,
267         },
268         [PORT_NS16550A] = {
269                 .name           = "NS16550A",
270                 .fifo_size      = 16,
271                 .tx_loadsz      = 16,
272                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
273                 .flags          = UART_CAP_FIFO | UART_NATSEMI,
274         },
275         [PORT_XSCALE] = {
276                 .name           = "XScale",
277                 .fifo_size      = 32,
278                 .tx_loadsz      = 32,
279                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
280                 .flags          = UART_CAP_FIFO | UART_CAP_UUE,
281         },
282         [PORT_RM9000] = {
283                 .name           = "RM9000",
284                 .fifo_size      = 16,
285                 .tx_loadsz      = 16,
286                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
287                 .flags          = UART_CAP_FIFO,
288         },
289         [PORT_OCTEON] = {
290                 .name           = "OCTEON",
291                 .fifo_size      = 64,
292                 .tx_loadsz      = 64,
293                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
294                 .flags          = UART_CAP_FIFO,
295         },
296         [PORT_AR7] = {
297                 .name           = "AR7",
298                 .fifo_size      = 16,
299                 .tx_loadsz      = 16,
300                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
301                 .flags          = UART_CAP_FIFO | UART_CAP_AFE,
302         },
303 };
304 
305 #if defined (CONFIG_SERIAL_8250_AU1X00)
306 
307 /* Au1x00 UART hardware has a weird register layout */
308 static const u8 au_io_in_map[] = {
309         [UART_RX]  = 0,
310         [UART_IER] = 2,
311         [UART_IIR] = 3,
312         [UART_LCR] = 5,
313         [UART_MCR] = 6,
314         [UART_LSR] = 7,
315         [UART_MSR] = 8,
316 };
317 
318 static const u8 au_io_out_map[] = {
319         [UART_TX]  = 1,
320         [UART_IER] = 2,
321         [UART_FCR] = 4,
322         [UART_LCR] = 5,
323         [UART_MCR] = 6,
324 };
325 
326 /* sane hardware needs no mapping */
327 static inline int map_8250_in_reg(struct uart_port *p, int offset)
328 {
329         if (p->iotype != UPIO_AU)
330                 return offset;
331         return au_io_in_map[offset];
332 }
333 
334 static inline int map_8250_out_reg(struct uart_port *p, int offset)
335 {
336         if (p->iotype != UPIO_AU)
337                 return offset;
338         return au_io_out_map[offset];
339 }
340 
341 #elif defined(CONFIG_SERIAL_8250_RM9K)
342 
343 static const u8
344         regmap_in[8] = {
345                 [UART_RX]       = 0x00,
346                 [UART_IER]      = 0x0c,
347                 [UART_IIR]      = 0x14,
348                 [UART_LCR]      = 0x1c,
349                 [UART_MCR]      = 0x20,
350                 [UART_LSR]      = 0x24,
351                 [UART_MSR]      = 0x28,
352                 [UART_SCR]      = 0x2c
353         },
354         regmap_out[8] = {
355                 [UART_TX]       = 0x04,
356                 [UART_IER]      = 0x0c,
357                 [UART_FCR]      = 0x18,
358                 [UART_LCR]      = 0x1c,
359                 [UART_MCR]      = 0x20,
360                 [UART_LSR]      = 0x24,
361                 [UART_MSR]      = 0x28,
362                 [UART_SCR]      = 0x2c
363         };
364 
365 static inline int map_8250_in_reg(struct uart_port *p, int offset)
366 {
367         if (p->iotype != UPIO_RM9000)
368                 return offset;
369         return regmap_in[offset];
370 }
371 
372 static inline int map_8250_out_reg(struct uart_port *p, int offset)
373 {
374         if (p->iotype != UPIO_RM9000)
375                 return offset;
376         return regmap_out[offset];
377 }
378 
379 #else
380 
381 /* sane hardware needs no mapping */
382 #define map_8250_in_reg(up, offset) (offset)
383 #define map_8250_out_reg(up, offset) (offset)
384 
385 #endif
386 
387 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
388 {
389         offset = map_8250_in_reg(p, offset) << p->regshift;
390         outb(p->hub6 - 1 + offset, p->iobase);
391         return inb(p->iobase + 1);
392 }
393 
394 static void hub6_serial_out(struct uart_port *p, int offset, int value)
395 {
396         offset = map_8250_out_reg(p, offset) << p->regshift;
397         outb(p->hub6 - 1 + offset, p->iobase);
398         outb(value, p->iobase + 1);
399 }
400 
401 static unsigned int mem_serial_in(struct uart_port *p, int offset)
402 {
403         offset = map_8250_in_reg(p, offset) << p->regshift;
404         return readb(p->membase + offset);
405 }
406 
407 static void mem_serial_out(struct uart_port *p, int offset, int value)
408 {
409         offset = map_8250_out_reg(p, offset) << p->regshift;
410         writeb(value, p->membase + offset);
411 }
412 
413 static void mem32_serial_out(struct uart_port *p, int offset, int value)
414 {
415         offset = map_8250_out_reg(p, offset) << p->regshift;
416         writel(value, p->membase + offset);
417 }
418 
419 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
420 {
421         offset = map_8250_in_reg(p, offset) << p->regshift;
422         return readl(p->membase + offset);
423 }
424 
425 #ifdef CONFIG_SERIAL_8250_AU1X00
426 static unsigned int au_serial_in(struct uart_port *p, int offset)
427 {
428         offset = map_8250_in_reg(p, offset) << p->regshift;
429         return __raw_readl(p->membase + offset);
430 }
431 
432 static void au_serial_out(struct uart_port *p, int offset, int value)
433 {
434         offset = map_8250_out_reg(p, offset) << p->regshift;
435         __raw_writel(value, p->membase + offset);
436 }
437 #endif
438 
439 static unsigned int tsi_serial_in(struct uart_port *p, int offset)
440 {
441         unsigned int tmp;
442         offset = map_8250_in_reg(p, offset) << p->regshift;
443         if (offset == UART_IIR) {
444                 tmp = readl(p->membase + (UART_IIR & ~3));
445                 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
446         } else
447                 return readb(p->membase + offset);
448 }
449 
450 static void tsi_serial_out(struct uart_port *p, int offset, int value)
451 {
452         offset = map_8250_out_reg(p, offset) << p->regshift;
453         if (!((offset == UART_IER) && (value & UART_IER_UUE)))
454                 writeb(value, p->membase + offset);
455 }
456 
457 static void dwapb_serial_out(struct uart_port *p, int offset, int value)
458 {
459         int save_offset = offset;
460         offset = map_8250_out_reg(p, offset) << p->regshift;
461         /* Save the LCR value so it can be re-written when a
462          * Busy Detect interrupt occurs. */
463         if (save_offset == UART_LCR) {
464                 struct uart_8250_port *up = (struct uart_8250_port *)p;
465                 up->lcr = value;
466         }
467         writeb(value, p->membase + offset);
468         /* Read the IER to ensure any interrupt is cleared before
469          * returning from ISR. */
470         if (save_offset == UART_TX || save_offset == UART_IER)
471                 value = p->serial_in(p, UART_IER);
472 }
473 
474 static unsigned int io_serial_in(struct uart_port *p, int offset)
475 {
476         offset = map_8250_in_reg(p, offset) << p->regshift;
477         return inb(p->iobase + offset);
478 }
479 
480 static void io_serial_out(struct uart_port *p, int offset, int value)
481 {
482         offset = map_8250_out_reg(p, offset) << p->regshift;
483         outb(value, p->iobase + offset);
484 }
485 
486 static void set_io_from_upio(struct uart_port *p)
487 {
488         struct uart_8250_port *up = (struct uart_8250_port *)p;
489         switch (p->iotype) {
490         case UPIO_HUB6:
491                 p->serial_in = hub6_serial_in;
492                 p->serial_out = hub6_serial_out;
493                 break;
494 
495         case UPIO_MEM:
496                 p->serial_in = mem_serial_in;
497                 p->serial_out = mem_serial_out;
498                 break;
499 
500         case UPIO_RM9000:
501         case UPIO_MEM32:
502                 p->serial_in = mem32_serial_in;
503                 p->serial_out = mem32_serial_out;
504                 break;
505 
506 #ifdef CONFIG_SERIAL_8250_AU1X00
507         case UPIO_AU:
508                 p->serial_in = au_serial_in;
509                 p->serial_out = au_serial_out;
510                 break;
511 #endif
512         case UPIO_TSI:
513                 p->serial_in = tsi_serial_in;
514                 p->serial_out = tsi_serial_out;
515                 break;
516 
517         case UPIO_DWAPB:
518                 p->serial_in = mem_serial_in;
519                 p->serial_out = dwapb_serial_out;
520                 break;
521 
522         default:
523                 p->serial_in = io_serial_in;
524                 p->serial_out = io_serial_out;
525                 break;
526         }
527         /* Remember loaded iotype */
528         up->cur_iotype = p->iotype;
529 }
530 
531 static void
532 serial_out_sync(struct uart_8250_port *up, int offset, int value)
533 {
534         struct uart_port *p = &up->port;
535         switch (p->iotype) {
536         case UPIO_MEM:
537         case UPIO_MEM32:
538 #ifdef CONFIG_SERIAL_8250_AU1X00
539         case UPIO_AU:
540 #endif
541         case UPIO_DWAPB:
542                 p->serial_out(p, offset, value);
543                 p->serial_in(p, UART_LCR);      /* safe, no side-effects */
544                 break;
545         default:
546                 p->serial_out(p, offset, value);
547         }
548 }
549 
550 #define serial_in(up, offset)           \
551         (up->port.serial_in(&(up)->port, (offset)))
552 #define serial_out(up, offset, value)   \
553         (up->port.serial_out(&(up)->port, (offset), (value)))
554 /*
555  * We used to support using pause I/O for certain machines.  We
556  * haven't supported this for a while, but just in case it's badly
557  * needed for certain old 386 machines, I've left these #define's
558  * in....
559  */
560 #define serial_inp(up, offset)          serial_in(up, offset)
561 #define serial_outp(up, offset, value)  serial_out(up, offset, value)
562 
563 /* Uart divisor latch read */
564 static inline int _serial_dl_read(struct uart_8250_port *up)
565 {
566         return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
567 }
568 
569 /* Uart divisor latch write */
570 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
571 {
572         serial_outp(up, UART_DLL, value & 0xff);
573         serial_outp(up, UART_DLM, value >> 8 & 0xff);
574 }
575 
576 #if defined(CONFIG_SERIAL_8250_AU1X00)
577 /* Au1x00 haven't got a standard divisor latch */
578 static int serial_dl_read(struct uart_8250_port *up)
579 {
580         if (up->port.iotype == UPIO_AU)
581                 return __raw_readl(up->port.membase + 0x28);
582         else
583                 return _serial_dl_read(up);
584 }
585 
586 static void serial_dl_write(struct uart_8250_port *up, int value)
587 {
588         if (up->port.iotype == UPIO_AU)
589                 __raw_writel(value, up->port.membase + 0x28);
590         else
591                 _serial_dl_write(up, value);
592 }
593 #elif defined(CONFIG_SERIAL_8250_RM9K)
594 static int serial_dl_read(struct uart_8250_port *up)
595 {
596         return  (up->port.iotype == UPIO_RM9000) ?
597                 (((__raw_readl(up->port.membase + 0x10) << 8) |
598                 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
599                 _serial_dl_read(up);
600 }
601 
602 static void serial_dl_write(struct uart_8250_port *up, int value)
603 {
604         if (up->port.iotype == UPIO_RM9000) {
605                 __raw_writel(value, up->port.membase + 0x08);
606                 __raw_writel(value >> 8, up->port.membase + 0x10);
607         } else {
608                 _serial_dl_write(up, value);
609         }
610 }
611 #else
612 #define serial_dl_read(up) _serial_dl_read(up)
613 #define serial_dl_write(up, value) _serial_dl_write(up, value)
614 #endif
615 
616 /*
617  * For the 16C950
618  */
619 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
620 {
621         serial_out(up, UART_SCR, offset);
622         serial_out(up, UART_ICR, value);
623 }
624 
625 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
626 {
627         unsigned int value;
628 
629         serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
630         serial_out(up, UART_SCR, offset);
631         value = serial_in(up, UART_ICR);
632         serial_icr_write(up, UART_ACR, up->acr);
633 
634         return value;
635 }
636 
637 /*
638  * FIFO support.
639  */
640 static void serial8250_clear_fifos(struct uart_8250_port *p)
641 {
642         if (p->capabilities & UART_CAP_FIFO) {
643                 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
644                 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
645                                UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
646                 serial_outp(p, UART_FCR, 0);
647         }
648 }
649 
650 /*
651  * IER sleep support.  UARTs which have EFRs need the "extended
652  * capability" bit enabled.  Note that on XR16C850s, we need to
653  * reset LCR to write to IER.
654  */
655 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
656 {
657         if (p->capabilities & UART_CAP_SLEEP) {
658                 if (p->capabilities & UART_CAP_EFR) {
659                         serial_outp(p, UART_LCR, 0xBF);
660                         serial_outp(p, UART_EFR, UART_EFR_ECB);
661                         serial_outp(p, UART_LCR, 0);
662                 }
663                 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
664                 if (p->capabilities & UART_CAP_EFR) {
665                         serial_outp(p, UART_LCR, 0xBF);
666                         serial_outp(p, UART_EFR, 0);
667                         serial_outp(p, UART_LCR, 0);
668                 }
669         }
670 }
671 
672 #ifdef CONFIG_SERIAL_8250_RSA
673 /*
674  * Attempts to turn on the RSA FIFO.  Returns zero on failure.
675  * We set the port uart clock rate if we succeed.
676  */
677 static int __enable_rsa(struct uart_8250_port *up)
678 {
679         unsigned char mode;
680         int result;
681 
682         mode = serial_inp(up, UART_RSA_MSR);
683         result = mode & UART_RSA_MSR_FIFO;
684 
685         if (!result) {
686                 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
687                 mode = serial_inp(up, UART_RSA_MSR);
688                 result = mode & UART_RSA_MSR_FIFO;
689         }
690 
691         if (result)
692                 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
693 
694         return result;
695 }
696 
697 static void enable_rsa(struct uart_8250_port *up)
698 {
699         if (up->port.type == PORT_RSA) {
700                 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
701                         spin_lock_irq(&up->port.lock);
702                         __enable_rsa(up);
703                         spin_unlock_irq(&up->port.lock);
704                 }
705                 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
706                         serial_outp(up, UART_RSA_FRR, 0);
707         }
708 }
709 
710 /*
711  * Attempts to turn off the RSA FIFO.  Returns zero on failure.
712  * It is unknown why interrupts were disabled in here.  However,
713  * the caller is expected to preserve this behaviour by grabbing
714  * the spinlock before calling this function.
715  */
716 static void disable_rsa(struct uart_8250_port *up)
717 {
718         unsigned char mode;
719         int result;
720 
721         if (up->port.type == PORT_RSA &&
722             up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
723                 spin_lock_irq(&up->port.lock);
724 
725                 mode = serial_inp(up, UART_RSA_MSR);
726                 result = !(mode & UART_RSA_MSR_FIFO);
727 
728                 if (!result) {
729                         serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
730                         mode = serial_inp(up, UART_RSA_MSR);
731                         result = !(mode & UART_RSA_MSR_FIFO);
732                 }
733 
734                 if (result)
735                         up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
736                 spin_unlock_irq(&up->port.lock);
737         }
738 }
739 #endif /* CONFIG_SERIAL_8250_RSA */
740 
741 /*
742  * This is a quickie test to see how big the FIFO is.
743  * It doesn't work at all the time, more's the pity.
744  */
745 static int size_fifo(struct uart_8250_port *up)
746 {
747         unsigned char old_fcr, old_mcr, old_lcr;
748         unsigned short old_dl;
749         int count;
750 
751         old_lcr = serial_inp(up, UART_LCR);
752         serial_outp(up, UART_LCR, 0);
753         old_fcr = serial_inp(up, UART_FCR);
754         old_mcr = serial_inp(up, UART_MCR);
755         serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
756                     UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
757         serial_outp(up, UART_MCR, UART_MCR_LOOP);
758         serial_outp(up, UART_LCR, UART_LCR_DLAB);
759         old_dl = serial_dl_read(up);
760         serial_dl_write(up, 0x0001);
761         serial_outp(up, UART_LCR, 0x03);
762         for (count = 0; count < 256; count++)
763                 serial_outp(up, UART_TX, count);
764         mdelay(20);/* FIXME - schedule_timeout */
765         for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
766              (count < 256); count++)
767                 serial_inp(up, UART_RX);
768         serial_outp(up, UART_FCR, old_fcr);
769         serial_outp(up, UART_MCR, old_mcr);
770         serial_outp(up, UART_LCR, UART_LCR_DLAB);
771         serial_dl_write(up, old_dl);
772         serial_outp(up, UART_LCR, old_lcr);
773 
774         return count;
775 }
776 
777 /*
778  * Read UART ID using the divisor method - set DLL and DLM to zero
779  * and the revision will be in DLL and device type in DLM.  We
780  * preserve the device state across this.
781  */
782 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
783 {
784         unsigned char old_dll, old_dlm, old_lcr;
785         unsigned int id;
786 
787         old_lcr = serial_inp(p, UART_LCR);
788         serial_outp(p, UART_LCR, UART_LCR_DLAB);
789 
790         old_dll = serial_inp(p, UART_DLL);
791         old_dlm = serial_inp(p, UART_DLM);
792 
793         serial_outp(p, UART_DLL, 0);
794         serial_outp(p, UART_DLM, 0);
795 
796         id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
797 
798         serial_outp(p, UART_DLL, old_dll);
799         serial_outp(p, UART_DLM, old_dlm);
800         serial_outp(p, UART_LCR, old_lcr);
801 
802         return id;
803 }
804 
805 /*
806  * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
807  * When this function is called we know it is at least a StarTech
808  * 16650 V2, but it might be one of several StarTech UARTs, or one of
809  * its clones.  (We treat the broken original StarTech 16650 V1 as a
810  * 16550, and why not?  Startech doesn't seem to even acknowledge its
811  * existence.)
812  *
813  * What evil have men's minds wrought...
814  */
815 static void autoconfig_has_efr(struct uart_8250_port *up)
816 {
817         unsigned int id1, id2, id3, rev;
818 
819         /*
820          * Everything with an EFR has SLEEP
821          */
822         up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
823 
824         /*
825          * First we check to see if it's an Oxford Semiconductor UART.
826          *
827          * If we have to do this here because some non-National
828          * Semiconductor clone chips lock up if you try writing to the
829          * LSR register (which serial_icr_read does)
830          */
831 
832         /*
833          * Check for Oxford Semiconductor 16C950.
834          *
835          * EFR [4] must be set else this test fails.
836          *
837          * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
838          * claims that it's needed for 952 dual UART's (which are not
839          * recommended for new designs).
840          */
841         up->acr = 0;
842         serial_out(up, UART_LCR, 0xBF);
843         serial_out(up, UART_EFR, UART_EFR_ECB);
844         serial_out(up, UART_LCR, 0x00);
845         id1 = serial_icr_read(up, UART_ID1);
846         id2 = serial_icr_read(up, UART_ID2);
847         id3 = serial_icr_read(up, UART_ID3);
848         rev = serial_icr_read(up, UART_REV);
849 
850         DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
851 
852         if (id1 == 0x16 && id2 == 0xC9 &&
853             (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
854                 up->port.type = PORT_16C950;
855 
856                 /*
857                  * Enable work around for the Oxford Semiconductor 952 rev B
858                  * chip which causes it to seriously miscalculate baud rates
859                  * when DLL is 0.
860                  */
861                 if (id3 == 0x52 && rev == 0x01)
862                         up->bugs |= UART_BUG_QUOT;
863                 return;
864         }
865 
866         /*
867          * We check for a XR16C850 by setting DLL and DLM to 0, and then
868          * reading back DLL and DLM.  The chip type depends on the DLM
869          * value read back:
870          *  0x10 - XR16C850 and the DLL contains the chip revision.
871          *  0x12 - XR16C2850.
872          *  0x14 - XR16C854.
873          */
874         id1 = autoconfig_read_divisor_id(up);
875         DEBUG_AUTOCONF("850id=%04x ", id1);
876 
877         id2 = id1 >> 8;
878         if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
879                 up->port.type = PORT_16850;
880                 return;
881         }
882 
883         /*
884          * It wasn't an XR16C850.
885          *
886          * We distinguish between the '654 and the '650 by counting
887          * how many bytes are in the FIFO.  I'm using this for now,
888          * since that's the technique that was sent to me in the
889          * serial driver update, but I'm not convinced this works.
890          * I've had problems doing this in the past.  -TYT
891          */
892         if (size_fifo(up) == 64)
893                 up->port.type = PORT_16654;
894         else
895                 up->port.type = PORT_16650V2;
896 }
897 
898 /*
899  * We detected a chip without a FIFO.  Only two fall into
900  * this category - the original 8250 and the 16450.  The
901  * 16450 has a scratch register (accessible with LCR=0)
902  */
903 static void autoconfig_8250(struct uart_8250_port *up)
904 {
905         unsigned char scratch, status1, status2;
906 
907         up->port.type = PORT_8250;
908 
909         scratch = serial_in(up, UART_SCR);
910         serial_outp(up, UART_SCR, 0xa5);
911         status1 = serial_in(up, UART_SCR);
912         serial_outp(up, UART_SCR, 0x5a);
913         status2 = serial_in(up, UART_SCR);
914         serial_outp(up, UART_SCR, scratch);
915 
916         if (status1 == 0xa5 && status2 == 0x5a)
917                 up->port.type = PORT_16450;
918 }
919 
920 static int broken_efr(struct uart_8250_port *up)
921 {
922         /*
923          * Exar ST16C2550 "A2" devices incorrectly detect as
924          * having an EFR, and report an ID of 0x0201.  See
925          * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
926          */
927         if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
928                 return 1;
929 
930         return 0;
931 }
932 
933 /*
934  * We know that the chip has FIFOs.  Does it have an EFR?  The
935  * EFR is located in the same register position as the IIR and
936  * we know the top two bits of the IIR are currently set.  The
937  * EFR should contain zero.  Try to read the EFR.
938  */
939 static void autoconfig_16550a(struct uart_8250_port *up)
940 {
941         unsigned char status1, status2;
942         unsigned int iersave;
943 
944         up->port.type = PORT_16550A;
945         up->capabilities |= UART_CAP_FIFO;
946 
947         /*
948          * Check for presence of the EFR when DLAB is set.
949          * Only ST16C650V1 UARTs pass this test.
950          */
951         serial_outp(up, UART_LCR, UART_LCR_DLAB);
952         if (serial_in(up, UART_EFR) == 0) {
953                 serial_outp(up, UART_EFR, 0xA8);
954                 if (serial_in(up, UART_EFR) != 0) {
955                         DEBUG_AUTOCONF("EFRv1 ");
956                         up->port.type = PORT_16650;
957                         up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
958                 } else {
959                         DEBUG_AUTOCONF("Motorola 8xxx DUART ");
960                 }
961                 serial_outp(up, UART_EFR, 0);
962                 return;
963         }
964 
965         /*
966          * Maybe it requires 0xbf to be written to the LCR.
967          * (other ST16C650V2 UARTs, TI16C752A, etc)
968          */
969         serial_outp(up, UART_LCR, 0xBF);
970         if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
971                 DEBUG_AUTOCONF("EFRv2 ");
972                 autoconfig_has_efr(up);
973                 return;
974         }
975 
976         /*
977          * Check for a National Semiconductor SuperIO chip.
978          * Attempt to switch to bank 2, read the value of the LOOP bit
979          * from EXCR1. Switch back to bank 0, change it in MCR. Then
980          * switch back to bank 2, read it from EXCR1 again and check
981          * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
982          */
983         serial_outp(up, UART_LCR, 0);
984         status1 = serial_in(up, UART_MCR);
985         serial_outp(up, UART_LCR, 0xE0);
986         status2 = serial_in(up, 0x02); /* EXCR1 */
987 
988         if (!((status2 ^ status1) & UART_MCR_LOOP)) {
989                 serial_outp(up, UART_LCR, 0);
990                 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
991                 serial_outp(up, UART_LCR, 0xE0);
992                 status2 = serial_in(up, 0x02); /* EXCR1 */
993                 serial_outp(up, UART_LCR, 0);
994                 serial_outp(up, UART_MCR, status1);
995 
996                 if ((status2 ^ status1) & UART_MCR_LOOP) {
997                         unsigned short quot;
998 
999                         serial_outp(up, UART_LCR, 0xE0);
1000 
1001                         quot = serial_dl_read(up);
1002                         quot <<= 3;
1003 
1004                         status1 = serial_in(up, 0x04); /* EXCR2 */
1005                         status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
1006                         status1 |= 0x10;  /* 1.625 divisor for baud_base --> 921600 */
1007                         serial_outp(up, 0x04, status1);
1008 
1009                         serial_dl_write(up, quot);
1010 
1011                         serial_outp(up, UART_LCR, 0);
1012 
1013                         up->port.uartclk = 921600*16;
1014                         up->port.type = PORT_NS16550A;
1015                         up->capabilities |= UART_NATSEMI;
1016                         return;
1017                 }
1018         }
1019 
1020         /*
1021          * No EFR.  Try to detect a TI16750, which only sets bit 5 of
1022          * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1023          * Try setting it with and without DLAB set.  Cheap clones
1024          * set bit 5 without DLAB set.
1025          */
1026         serial_outp(up, UART_LCR, 0);
1027         serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1028         status1 = serial_in(up, UART_IIR) >> 5;
1029         serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1030         serial_outp(up, UART_LCR, UART_LCR_DLAB);
1031         serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1032         status2 = serial_in(up, UART_IIR) >> 5;
1033         serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1034         serial_outp(up, UART_LCR, 0);
1035 
1036         DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1037 
1038         if (status1 == 6 && status2 == 7) {
1039                 up->port.type = PORT_16750;
1040                 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1041                 return;
1042         }
1043 
1044         /*
1045          * Try writing and reading the UART_IER_UUE bit (b6).
1046          * If it works, this is probably one of the Xscale platform's
1047          * internal UARTs.
1048          * We're going to explicitly set the UUE bit to 0 before
1049          * trying to write and read a 1 just to make sure it's not
1050          * already a 1 and maybe locked there before we even start start.
1051          */
1052         iersave = serial_in(up, UART_IER);
1053         serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1054         if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1055                 /*
1056                  * OK it's in a known zero state, try writing and reading
1057                  * without disturbing the current state of the other bits.
1058                  */
1059                 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1060                 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1061                         /*
1062                          * It's an Xscale.
1063                          * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1064                          */
1065                         DEBUG_AUTOCONF("Xscale ");
1066                         up->port.type = PORT_XSCALE;
1067                         up->capabilities |= UART_CAP_UUE;
1068                         return;
1069                 }
1070         } else {
1071                 /*
1072                  * If we got here we couldn't force the IER_UUE bit to 0.
1073                  * Log it and continue.
1074                  */
1075                 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1076         }
1077         serial_outp(up, UART_IER, iersave);
1078 }
1079 
1080 /*
1081  * This routine is called by rs_init() to initialize a specific serial
1082  * port.  It determines what type of UART chip this serial port is
1083  * using: 8250, 16450, 16550, 16550A.  The important question is
1084  * whether or not this UART is a 16550A or not, since this will
1085  * determine whether or not we can use its FIFO features or not.
1086  */
1087 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1088 {
1089         unsigned char status1, scratch, scratch2, scratch3;
1090         unsigned char save_lcr, save_mcr;
1091         unsigned long flags;
1092 
1093         if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1094                 return;
1095 
1096         DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1097                        serial_index(&up->port), up->port.iobase, up->port.membase);
1098 
1099         /*
1100          * We really do need global IRQs disabled here - we're going to
1101          * be frobbing the chips IRQ enable register to see if it exists.
1102          */
1103         spin_lock_irqsave(&up->port.lock, flags);
1104 
1105         up->capabilities = 0;
1106         up->bugs = 0;
1107 
1108         if (!(up->port.flags & UPF_BUGGY_UART)) {
1109                 /*
1110                  * Do a simple existence test first; if we fail this,
1111                  * there's no point trying anything else.
1112                  *
1113                  * 0x80 is used as a nonsense port to prevent against
1114                  * false positives due to ISA bus float.  The
1115                  * assumption is that 0x80 is a non-existent port;
1116                  * which should be safe since include/asm/io.h also
1117                  * makes this assumption.
1118                  *
1119                  * Note: this is safe as long as MCR bit 4 is clear
1120                  * and the device is in "PC" mode.
1121                  */
1122                 scratch = serial_inp(up, UART_IER);
1123                 serial_outp(up, UART_IER, 0);
1124 #ifdef __i386__
1125                 outb(0xff, 0x080);
1126 #endif
1127                 /*
1128                  * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1129                  * 16C754B) allow only to modify them if an EFR bit is set.
1130                  */
1131                 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1132                 serial_outp(up, UART_IER, 0x0F);
1133 #ifdef __i386__
1134                 outb(0, 0x080);
1135 #endif
1136                 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1137                 serial_outp(up, UART_IER, scratch);
1138                 if (scratch2 != 0 || scratch3 != 0x0F) {
1139                         /*
1140                          * We failed; there's nothing here
1141                          */
1142                         DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1143                                        scratch2, scratch3);
1144                         goto out;
1145                 }
1146         }
1147 
1148         save_mcr = serial_in(up, UART_MCR);
1149         save_lcr = serial_in(up, UART_LCR);
1150 
1151         /*
1152          * Check to see if a UART is really there.  Certain broken
1153          * internal modems based on the Rockwell chipset fail this
1154          * test, because they apparently don't implement the loopback
1155          * test mode.  So this test is skipped on the COM 1 through
1156          * COM 4 ports.  This *should* be safe, since no board
1157          * manufacturer would be stupid enough to design a board
1158          * that conflicts with COM 1-4 --- we hope!
1159          */
1160         if (!(up->port.flags & UPF_SKIP_TEST)) {
1161                 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1162                 status1 = serial_inp(up, UART_MSR) & 0xF0;
1163                 serial_outp(up, UART_MCR, save_mcr);
1164                 if (status1 != 0x90) {
1165                         DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1166                                        status1);
1167                         goto out;
1168                 }
1169         }
1170 
1171         /*
1172          * We're pretty sure there's a port here.  Lets find out what
1173          * type of port it is.  The IIR top two bits allows us to find
1174          * out if it's 8250 or 16450, 16550, 16550A or later.  This
1175          * determines what we test for next.
1176          *
1177          * We also initialise the EFR (if any) to zero for later.  The
1178          * EFR occupies the same register location as the FCR and IIR.
1179          */
1180         serial_outp(up, UART_LCR, 0xBF);
1181         serial_outp(up, UART_EFR, 0);
1182         serial_outp(up, UART_LCR, 0);
1183 
1184         serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1185         scratch = serial_in(up, UART_IIR) >> 6;
1186 
1187         DEBUG_AUTOCONF("iir=%d ", scratch);
1188 
1189         switch (scratch) {
1190         case 0:
1191                 autoconfig_8250(up);
1192                 break;
1193         case 1:
1194                 up->port.type = PORT_UNKNOWN;
1195                 break;
1196         case 2:
1197                 up->port.type = PORT_16550;
1198                 break;
1199         case 3:
1200                 autoconfig_16550a(up);
1201                 break;
1202         }
1203 
1204 #ifdef CONFIG_SERIAL_8250_RSA
1205         /*
1206          * Only probe for RSA ports if we got the region.
1207          */
1208         if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1209                 int i;
1210 
1211                 for (i = 0 ; i < probe_rsa_count; ++i) {
1212                         if (probe_rsa[i] == up->port.iobase &&
1213                             __enable_rsa(up)) {
1214                                 up->port.type = PORT_RSA;
1215                                 break;
1216                         }
1217                 }
1218         }
1219 #endif
1220 
1221 #ifdef CONFIG_SERIAL_8250_AU1X00
1222         /* if access method is AU, it is a 16550 with a quirk */
1223         if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1224                 up->bugs |= UART_BUG_NOMSR;
1225 #endif
1226 
1227         serial_outp(up, UART_LCR, save_lcr);
1228 
1229         if (up->capabilities != uart_config[up->port.type].flags) {
1230                 printk(KERN_WARNING
1231                        "ttyS%d: detected caps %08x should be %08x\n",
1232                        serial_index(&up->port), up->capabilities,
1233                        uart_config[up->port.type].flags);
1234         }
1235 
1236         up->port.fifosize = uart_config[up->port.type].fifo_size;
1237         up->capabilities = uart_config[up->port.type].flags;
1238         up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1239 
1240         if (up->port.type == PORT_UNKNOWN)
1241                 goto out;
1242 
1243         /*
1244          * Reset the UART.
1245          */
1246 #ifdef CONFIG_SERIAL_8250_RSA
1247         if (up->port.type == PORT_RSA)
1248                 serial_outp(up, UART_RSA_FRR, 0);
1249 #endif
1250         serial_outp(up, UART_MCR, save_mcr);
1251         serial8250_clear_fifos(up);
1252         serial_in(up, UART_RX);
1253         if (up->capabilities & UART_CAP_UUE)
1254                 serial_outp(up, UART_IER, UART_IER_UUE);
1255         else
1256                 serial_outp(up, UART_IER, 0);
1257 
1258  out:
1259         spin_unlock_irqrestore(&up->port.lock, flags);
1260         DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1261 }
1262 
1263 static void autoconfig_irq(struct uart_8250_port *up)
1264 {
1265         unsigned char save_mcr, save_ier;
1266         unsigned char save_ICP = 0;
1267         unsigned int ICP = 0;
1268         unsigned long irqs;
1269         int irq;
1270 
1271         if (up->port.flags & UPF_FOURPORT) {
1272                 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1273                 save_ICP = inb_p(ICP);
1274                 outb_p(0x80, ICP);
1275                 (void) inb_p(ICP);
1276         }
1277 
1278         /* forget possible initially masked and pending IRQ */
1279         probe_irq_off(probe_irq_on());
1280         save_mcr = serial_inp(up, UART_MCR);
1281         save_ier = serial_inp(up, UART_IER);
1282         serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1283 
1284         irqs = probe_irq_on();
1285         serial_outp(up, UART_MCR, 0);
1286         udelay(10);
1287         if (up->port.flags & UPF_FOURPORT) {
1288                 serial_outp(up, UART_MCR,
1289                             UART_MCR_DTR | UART_MCR_RTS);
1290         } else {
1291                 serial_outp(up, UART_MCR,
1292                             UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1293         }
1294         serial_outp(up, UART_IER, 0x0f);        /* enable all intrs */
1295         (void)serial_inp(up, UART_LSR);
1296         (void)serial_inp(up, UART_RX);
1297         (void)serial_inp(up, UART_IIR);
1298         (void)serial_inp(up, UART_MSR);
1299         serial_outp(up, UART_TX, 0xFF);
1300         udelay(20);
1301         irq = probe_irq_off(irqs);
1302 
1303         serial_outp(up, UART_MCR, save_mcr);
1304         serial_outp(up, UART_IER, save_ier);
1305 
1306         if (up->port.flags & UPF_FOURPORT)
1307                 outb_p(save_ICP, ICP);
1308 
1309         up->port.irq = (irq > 0) ? irq : 0;
1310 }
1311 
1312 static inline void __stop_tx(struct uart_8250_port *p)
1313 {
1314         if (p->ier & UART_IER_THRI) {
1315                 p->ier &= ~UART_IER_THRI;
1316                 serial_out(p, UART_IER, p->ier);
1317         }
1318 }
1319 
1320 static void serial8250_stop_tx(struct uart_port *port)
1321 {
1322         struct uart_8250_port *up = (struct uart_8250_port *)port;
1323 
1324         __stop_tx(up);
1325 
1326         /*
1327          * We really want to stop the transmitter from sending.
1328          */
1329         if (up->port.type == PORT_16C950) {
1330                 up->acr |= UART_ACR_TXDIS;
1331                 serial_icr_write(up, UART_ACR, up->acr);
1332         }
1333 }
1334 
1335 static void transmit_chars(struct uart_8250_port *up);
1336 
1337 static void serial8250_start_tx(struct uart_port *port)
1338 {
1339         struct uart_8250_port *up = (struct uart_8250_port *)port;
1340 
1341         if (!(up->ier & UART_IER_THRI)) {
1342                 up->ier |= UART_IER_THRI;
1343                 serial_out(up, UART_IER, up->ier);
1344 
1345                 if (up->bugs & UART_BUG_TXEN) {
1346                         unsigned char lsr;
1347                         lsr = serial_in(up, UART_LSR);
1348                         up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1349                         if ((up->port.type == PORT_RM9000) ?
1350                                 (lsr & UART_LSR_THRE) :
1351                                 (lsr & UART_LSR_TEMT))
1352                                 transmit_chars(up);
1353                 }
1354         }
1355 
1356         /*
1357          * Re-enable the transmitter if we disabled it.
1358          */
1359         if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1360                 up->acr &= ~UART_ACR_TXDIS;
1361                 serial_icr_write(up, UART_ACR, up->acr);
1362         }
1363 }
1364 
1365 static void serial8250_stop_rx(struct uart_port *port)
1366 {
1367         struct uart_8250_port *up = (struct uart_8250_port *)port;
1368 
1369         up->ier &= ~UART_IER_RLSI;
1370         up->port.read_status_mask &= ~UART_LSR_DR;
1371         serial_out(up, UART_IER, up->ier);
1372 }
1373 
1374 static void serial8250_enable_ms(struct uart_port *port)
1375 {
1376         struct uart_8250_port *up = (struct uart_8250_port *)port;
1377 
1378         /* no MSR capabilities */
1379         if (up->bugs & UART_BUG_NOMSR)
1380                 return;
1381 
1382         up->ier |= UART_IER_MSI;
1383         serial_out(up, UART_IER, up->ier);
1384 }
1385 
1386 static void
1387 receive_chars(struct uart_8250_port *up, unsigned int *status)
1388 {
1389         struct tty_struct *tty = up->port.state->port.tty;
1390         unsigned char ch, lsr = *status;
1391         int max_count = 256;
1392         char flag;
1393 
1394         do {
1395                 if (likely(lsr & UART_LSR_DR))
1396                         ch = serial_inp(up, UART_RX);
1397                 else
1398                         /*
1399                          * Intel 82571 has a Serial Over Lan device that will
1400                          * set UART_LSR_BI without setting UART_LSR_DR when
1401                          * it receives a break. To avoid reading from the
1402                          * receive buffer without UART_LSR_DR bit set, we
1403                          * just force the read character to be 0
1404                          */
1405                         ch = 0;
1406 
1407                 flag = TTY_NORMAL;
1408                 up->port.icount.rx++;
1409 
1410                 lsr |= up->lsr_saved_flags;
1411                 up->lsr_saved_flags = 0;
1412 
1413                 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1414                         /*
1415                          * For statistics only
1416                          */
1417                         if (lsr & UART_LSR_BI) {
1418                                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1419                                 up->port.icount.brk++;
1420                                 /*
1421                                  * We do the SysRQ and SAK checking
1422                                  * here because otherwise the break
1423                                  * may get masked by ignore_status_mask
1424                                  * or read_status_mask.
1425                                  */
1426                                 if (uart_handle_break(&up->port))
1427                                         goto ignore_char;
1428                         } else if (lsr & UART_LSR_PE)
1429                                 up->port.icount.parity++;
1430                         else if (lsr & UART_LSR_FE)
1431                                 up->port.icount.frame++;
1432                         if (lsr & UART_LSR_OE)
1433                                 up->port.icount.overrun++;
1434 
1435                         /*
1436                          * Mask off conditions which should be ignored.
1437                          */
1438                         lsr &= up->port.read_status_mask;
1439 
1440                         if (lsr & UART_LSR_BI) {
1441                                 DEBUG_INTR("handling break....");
1442                                 flag = TTY_BREAK;
1443                         } else if (lsr & UART_LSR_PE)
1444                                 flag = TTY_PARITY;
1445                         else if (lsr & UART_LSR_FE)
1446                                 flag = TTY_FRAME;
1447                 }
1448                 if (uart_handle_sysrq_char(&up->port, ch))
1449                         goto ignore_char;
1450 
1451                 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1452 
1453 ignore_char:
1454                 lsr = serial_inp(up, UART_LSR);
1455         } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1456         spin_unlock(&up->port.lock);
1457         tty_flip_buffer_push(tty);
1458         spin_lock(&up->port.lock);
1459         *status = lsr;
1460 }
1461 
1462 static void transmit_chars(struct uart_8250_port *up)
1463 {
1464         struct circ_buf *xmit = &up->port.state->xmit;
1465         int count;
1466 
1467         if (up->port.x_char) {
1468                 serial_outp(up, UART_TX, up->port.x_char);
1469                 up->port.icount.tx++;
1470                 up->port.x_char = 0;
1471                 return;
1472         }
1473         if (uart_tx_stopped(&up->port)) {
1474                 serial8250_stop_tx(&up->port);
1475                 return;
1476         }
1477         if (uart_circ_empty(xmit)) {
1478                 __stop_tx(up);
1479                 return;
1480         }
1481 
1482         count = up->tx_loadsz;
1483         do {
1484                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1485                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1486                 up->port.icount.tx++;
1487                 if (uart_circ_empty(xmit))
1488                         break;
1489         } while (--count > 0);
1490 
1491         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1492                 uart_write_wakeup(&up->port);
1493 
1494         DEBUG_INTR("THRE...");
1495 
1496         if (uart_circ_empty(xmit))
1497                 __stop_tx(up);
1498 }
1499 
1500 static unsigned int check_modem_status(struct uart_8250_port *up)
1501 {
1502         unsigned int status = serial_in(up, UART_MSR);
1503 
1504         status |= up->msr_saved_flags;
1505         up->msr_saved_flags = 0;
1506         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1507             up->port.state != NULL) {
1508                 if (status & UART_MSR_TERI)
1509                         up->port.icount.rng++;
1510                 if (status & UART_MSR_DDSR)
1511                         up->port.icount.dsr++;
1512                 if (status & UART_MSR_DDCD)
1513                         uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1514                 if (status & UART_MSR_DCTS)
1515                         uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1516 
1517                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1518         }
1519 
1520         return status;
1521 }
1522 
1523 /*
1524  * This handles the interrupt from one port.
1525  */
1526 static void serial8250_handle_port(struct uart_8250_port *up)
1527 {
1528         unsigned int status;
1529         unsigned long flags;
1530 
1531         spin_lock_irqsave(&up->port.lock, flags);
1532 
1533         status = serial_inp(up, UART_LSR);
1534 
1535         DEBUG_INTR("status = %x...", status);
1536 
1537         if (status & (UART_LSR_DR | UART_LSR_BI))
1538                 receive_chars(up, &status);
1539         check_modem_status(up);
1540         if (status & UART_LSR_THRE)
1541                 transmit_chars(up);
1542 
1543         spin_unlock_irqrestore(&up->port.lock, flags);
1544 }
1545 
1546 /*
1547  * This is the serial driver's interrupt routine.
1548  *
1549  * Arjan thinks the old way was overly complex, so it got simplified.
1550  * Alan disagrees, saying that need the complexity to handle the weird
1551  * nature of ISA shared interrupts.  (This is a special exception.)
1552  *
1553  * In order to handle ISA shared interrupts properly, we need to check
1554  * that all ports have been serviced, and therefore the ISA interrupt
1555  * line has been de-asserted.
1556  *
1557  * This means we need to loop through all ports. checking that they
1558  * don't have an interrupt pending.
1559  */
1560 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1561 {
1562         struct irq_info *i = dev_id;
1563         struct list_head *l, *end = NULL;
1564         int pass_counter = 0, handled = 0;
1565 
1566         DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1567 
1568         spin_lock(&i->lock);
1569 
1570         l = i->head;
1571         do {
1572                 struct uart_8250_port *up;
1573                 unsigned int iir;
1574 
1575                 up = list_entry(l, struct uart_8250_port, list);
1576 
1577                 iir = serial_in(up, UART_IIR);
1578                 if (!(iir & UART_IIR_NO_INT)) {
1579                         serial8250_handle_port(up);
1580 
1581                         handled = 1;
1582 
1583                         end = NULL;
1584                 } else if (up->port.iotype == UPIO_DWAPB &&
1585                           (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1586                         /* The DesignWare APB UART has an Busy Detect (0x07)
1587                          * interrupt meaning an LCR write attempt occured while the
1588                          * UART was busy. The interrupt must be cleared by reading
1589                          * the UART status register (USR) and the LCR re-written. */
1590                         unsigned int status;
1591                         status = *(volatile u32 *)up->port.private_data;
1592                         serial_out(up, UART_LCR, up->lcr);
1593 
1594                         handled = 1;
1595 
1596                         end = NULL;
1597                 } else if (end == NULL)
1598                         end = l;
1599 
1600                 l = l->next;
1601 
1602                 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1603                         /* If we hit this, we're dead. */
1604                         printk(KERN_ERR "serial8250: too much work for "
1605                                 "irq%d\n", irq);
1606                         break;
1607                 }
1608         } while (l != end);
1609 
1610         spin_unlock(&i->lock);
1611 
1612         DEBUG_INTR("end.\n");
1613 
1614         return IRQ_RETVAL(handled);
1615 }
1616 
1617 /*
1618  * To support ISA shared interrupts, we need to have one interrupt
1619  * handler that ensures that the IRQ line has been deasserted
1620  * before returning.  Failing to do this will result in the IRQ
1621  * line being stuck active, and, since ISA irqs are edge triggered,
1622  * no more IRQs will be seen.
1623  */
1624 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1625 {
1626         spin_lock_irq(&i->lock);
1627 
1628         if (!list_empty(i->head)) {
1629                 if (i->head == &up->list)
1630                         i->head = i->head->next;
1631                 list_del(&up->list);
1632         } else {
1633                 BUG_ON(i->head != &up->list);
1634                 i->head = NULL;
1635         }
1636         spin_unlock_irq(&i->lock);
1637         /* List empty so throw away the hash node */
1638         if (i->head == NULL) {
1639                 hlist_del(&i->node);
1640                 kfree(i);
1641         }
1642 }
1643 
1644 static int serial_link_irq_chain(struct uart_8250_port *up)
1645 {
1646         struct hlist_head *h;
1647         struct hlist_node *n;
1648         struct irq_info *i;
1649         int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1650 
1651         mutex_lock(&hash_mutex);
1652 
1653         h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1654 
1655         hlist_for_each(n, h) {
1656                 i = hlist_entry(n, struct irq_info, node);
1657                 if (i->irq == up->port.irq)
1658                         break;
1659         }
1660 
1661         if (n == NULL) {
1662                 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1663                 if (i == NULL) {
1664                         mutex_unlock(&hash_mutex);
1665                         return -ENOMEM;
1666                 }
1667                 spin_lock_init(&i->lock);
1668                 i->irq = up->port.irq;
1669                 hlist_add_head(&i->node, h);
1670         }
1671         mutex_unlock(&hash_mutex);
1672 
1673         spin_lock_irq(&i->lock);
1674 
1675         if (i->head) {
1676                 list_add(&up->list, i->head);
1677                 spin_unlock_irq(&i->lock);
1678 
1679                 ret = 0;
1680         } else {
1681                 INIT_LIST_HEAD(&up->list);
1682                 i->head = &up->list;
1683                 spin_unlock_irq(&i->lock);
1684                 irq_flags |= up->port.irqflags;
1685                 ret = request_irq(up->port.irq, serial8250_interrupt,
1686                                   irq_flags, "serial", i);
1687                 if (ret < 0)
1688                         serial_do_unlink(i, up);
1689         }
1690 
1691         return ret;
1692 }
1693 
1694 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1695 {
1696         struct irq_info *i;
1697         struct hlist_node *n;
1698         struct hlist_head *h;
1699 
1700         mutex_lock(&hash_mutex);
1701 
1702         h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1703 
1704         hlist_for_each(n, h) {
1705                 i = hlist_entry(n, struct irq_info, node);
1706                 if (i->irq == up->port.irq)
1707                         break;
1708         }
1709 
1710         BUG_ON(n == NULL);
1711         BUG_ON(i->head == NULL);
1712 
1713         if (list_empty(i->head))
1714                 free_irq(up->port.irq, i);
1715 
1716         serial_do_unlink(i, up);
1717         mutex_unlock(&hash_mutex);
1718 }
1719 
1720 /* Base timer interval for polling */
1721 static inline int poll_timeout(int timeout)
1722 {
1723         return timeout > 6 ? (timeout / 2 - 2) : 1;
1724 }
1725 
1726 /*
1727  * This function is used to handle ports that do not have an
1728  * interrupt.  This doesn't work very well for 16450's, but gives
1729  * barely passable results for a 16550A.  (Although at the expense
1730  * of much CPU overhead).
1731  */
1732 static void serial8250_timeout(unsigned long data)
1733 {
1734         struct uart_8250_port *up = (struct uart_8250_port *)data;
1735         unsigned int iir;
1736 
1737         iir = serial_in(up, UART_IIR);
1738         if (!(iir & UART_IIR_NO_INT))
1739                 serial8250_handle_port(up);
1740         mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1741 }
1742 
1743 static void serial8250_backup_timeout(unsigned long data)
1744 {
1745         struct uart_8250_port *up = (struct uart_8250_port *)data;
1746         unsigned int iir, ier = 0, lsr;
1747         unsigned long flags;
1748 
1749         /*
1750          * Must disable interrupts or else we risk racing with the interrupt
1751          * based handler.
1752          */
1753         if (is_real_interrupt(up->port.irq)) {
1754                 ier = serial_in(up, UART_IER);
1755                 serial_out(up, UART_IER, 0);
1756         }
1757 
1758         iir = serial_in(up, UART_IIR);
1759 
1760         /*
1761          * This should be a safe test for anyone who doesn't trust the
1762          * IIR bits on their UART, but it's specifically designed for
1763          * the "Diva" UART used on the management processor on many HP
1764          * ia64 and parisc boxes.
1765          */
1766         spin_lock_irqsave(&up->port.lock, flags);
1767         lsr = serial_in(up, UART_LSR);
1768         up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1769         spin_unlock_irqrestore(&up->port.lock, flags);
1770         if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1771             (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1772             (lsr & UART_LSR_THRE)) {
1773                 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1774                 iir |= UART_IIR_THRI;
1775         }
1776 
1777         if (!(iir & UART_IIR_NO_INT))
1778                 serial8250_handle_port(up);
1779 
1780         if (is_real_interrupt(up->port.irq))
1781                 serial_out(up, UART_IER, ier);
1782 
1783         /* Standard timer interval plus 0.2s to keep the port running */
1784         mod_timer(&up->timer,
1785                 jiffies + poll_timeout(up->port.timeout) + HZ / 5);
1786 }
1787 
1788 static unsigned int serial8250_tx_empty(struct uart_port *port)
1789 {
1790         struct uart_8250_port *up = (struct uart_8250_port *)port;
1791         unsigned long flags;
1792         unsigned int lsr;
1793 
1794         spin_lock_irqsave(&up->port.lock, flags);
1795         lsr = serial_in(up, UART_LSR);
1796         up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1797         spin_unlock_irqrestore(&up->port.lock, flags);
1798 
1799         return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1800 }
1801 
1802 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1803 {
1804         struct uart_8250_port *up = (struct uart_8250_port *)port;
1805         unsigned int status;
1806         unsigned int ret;
1807 
1808         status = check_modem_status(up);
1809 
1810         ret = 0;
1811         if (status & UART_MSR_DCD)
1812                 ret |= TIOCM_CAR;
1813         if (status & UART_MSR_RI)
1814                 ret |= TIOCM_RNG;
1815         if (status & UART_MSR_DSR)
1816                 ret |= TIOCM_DSR;
1817         if (status & UART_MSR_CTS)
1818                 ret |= TIOCM_CTS;
1819         return ret;
1820 }
1821 
1822 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1823 {
1824         struct uart_8250_port *up = (struct uart_8250_port *)port;
1825         unsigned char mcr = 0;
1826 
1827         if (mctrl & TIOCM_RTS)
1828                 mcr |= UART_MCR_RTS;
1829         if (mctrl & TIOCM_DTR)
1830                 mcr |= UART_MCR_DTR;
1831         if (mctrl & TIOCM_OUT1)
1832                 mcr |= UART_MCR_OUT1;
1833         if (mctrl & TIOCM_OUT2)
1834                 mcr |= UART_MCR_OUT2;
1835         if (mctrl & TIOCM_LOOP)
1836                 mcr |= UART_MCR_LOOP;
1837 
1838         mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1839 
1840         serial_out(up, UART_MCR, mcr);
1841 }
1842 
1843 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1844 {
1845         struct uart_8250_port *up = (struct uart_8250_port *)port;
1846         unsigned long flags;
1847 
1848         spin_lock_irqsave(&up->port.lock, flags);
1849         if (break_state == -1)
1850                 up->lcr |= UART_LCR_SBC;
1851         else
1852                 up->lcr &= ~UART_LCR_SBC;
1853         serial_out(up, UART_LCR, up->lcr);
1854         spin_unlock_irqrestore(&up->port.lock, flags);
1855 }
1856 
1857 /*
1858  *      Wait for transmitter & holding register to empty
1859  */
1860 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1861 {
1862         unsigned int status, tmout = 10000;
1863 
1864         /* Wait up to 10ms for the character(s) to be sent. */
1865         do {
1866                 status = serial_in(up, UART_LSR);
1867 
1868                 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1869 
1870                 if (--tmout == 0)
1871                         break;
1872                 udelay(1);
1873         } while ((status & bits) != bits);
1874 
1875         /* Wait up to 1s for flow control if necessary */
1876         if (up->port.flags & UPF_CONS_FLOW) {
1877                 unsigned int tmout;
1878                 for (tmout = 1000000; tmout; tmout--) {
1879                         unsigned int msr = serial_in(up, UART_MSR);
1880                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1881                         if (msr & UART_MSR_CTS)
1882                                 break;
1883                         udelay(1);
1884                         touch_nmi_watchdog();
1885                 }
1886         }
1887 }
1888 
1889 #ifdef CONFIG_CONSOLE_POLL
1890 /*
1891  * Console polling routines for writing and reading from the uart while
1892  * in an interrupt or debug context.
1893  */
1894 
1895 static int serial8250_get_poll_char(struct uart_port *port)
1896 {
1897         struct uart_8250_port *up = (struct uart_8250_port *)port;
1898         unsigned char lsr = serial_inp(up, UART_LSR);
1899 
1900         while (!(lsr & UART_LSR_DR))
1901                 lsr = serial_inp(up, UART_LSR);
1902 
1903         return serial_inp(up, UART_RX);
1904 }
1905 
1906 
1907 static void serial8250_put_poll_char(struct uart_port *port,
1908                          unsigned char c)
1909 {
1910         unsigned int ier;
1911         struct uart_8250_port *up = (struct uart_8250_port *)port;
1912 
1913         /*
1914          *      First save the IER then disable the interrupts
1915          */
1916         ier = serial_in(up, UART_IER);
1917         if (up->capabilities & UART_CAP_UUE)
1918                 serial_out(up, UART_IER, UART_IER_UUE);
1919         else
1920                 serial_out(up, UART_IER, 0);
1921 
1922         wait_for_xmitr(up, BOTH_EMPTY);
1923         /*
1924          *      Send the character out.
1925          *      If a LF, also do CR...
1926          */
1927         serial_out(up, UART_TX, c);
1928         if (c == 10) {
1929                 wait_for_xmitr(up, BOTH_EMPTY);
1930                 serial_out(up, UART_TX, 13);
1931         }
1932 
1933         /*
1934          *      Finally, wait for transmitter to become empty
1935          *      and restore the IER
1936          */
1937         wait_for_xmitr(up, BOTH_EMPTY);
1938         serial_out(up, UART_IER, ier);
1939 }
1940 
1941 #endif /* CONFIG_CONSOLE_POLL */
1942 
1943 static int serial8250_startup(struct uart_port *port)
1944 {
1945         struct uart_8250_port *up = (struct uart_8250_port *)port;
1946         unsigned long flags;
1947         unsigned char lsr, iir;
1948         int retval;
1949 
1950         up->capabilities = uart_config[up->port.type].flags;
1951         up->mcr = 0;
1952 
1953         if (up->port.iotype != up->cur_iotype)
1954                 set_io_from_upio(port);
1955 
1956         if (up->port.type == PORT_16C950) {
1957                 /* Wake up and initialize UART */
1958                 up->acr = 0;
1959                 serial_outp(up, UART_LCR, 0xBF);
1960                 serial_outp(up, UART_EFR, UART_EFR_ECB);
1961                 serial_outp(up, UART_IER, 0);
1962                 serial_outp(up, UART_LCR, 0);
1963                 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1964                 serial_outp(up, UART_LCR, 0xBF);
1965                 serial_outp(up, UART_EFR, UART_EFR_ECB);
1966                 serial_outp(up, UART_LCR, 0);
1967         }
1968 
1969 #ifdef CONFIG_SERIAL_8250_RSA
1970         /*
1971          * If this is an RSA port, see if we can kick it up to the
1972          * higher speed clock.
1973          */
1974         enable_rsa(up);
1975 #endif
1976 
1977         /*
1978          * Clear the FIFO buffers and disable them.
1979          * (they will be reenabled in set_termios())
1980          */
1981         serial8250_clear_fifos(up);
1982 
1983         /*
1984          * Clear the interrupt registers.
1985          */
1986         (void) serial_inp(up, UART_LSR);
1987         (void) serial_inp(up, UART_RX);
1988         (void) serial_inp(up, UART_IIR);
1989         (void) serial_inp(up, UART_MSR);
1990 
1991         /*
1992          * At this point, there's no way the LSR could still be 0xff;
1993          * if it is, then bail out, because there's likely no UART
1994          * here.
1995          */
1996         if (!(up->port.flags & UPF_BUGGY_UART) &&
1997             (serial_inp(up, UART_LSR) == 0xff)) {
1998                 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1999                        serial_index(&up->port));
2000                 return -ENODEV;
2001         }
2002 
2003         /*
2004          * For a XR16C850, we need to set the trigger levels
2005          */
2006         if (up->port.type == PORT_16850) {
2007                 unsigned char fctr;
2008 
2009                 serial_outp(up, UART_LCR, 0xbf);
2010 
2011                 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2012                 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2013                 serial_outp(up, UART_TRG, UART_TRG_96);
2014                 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2015                 serial_outp(up, UART_TRG, UART_TRG_96);
2016 
2017                 serial_outp(up, UART_LCR, 0);
2018         }
2019 
2020         if (is_real_interrupt(up->port.irq)) {
2021                 unsigned char iir1;
2022                 /*
2023                  * Test for UARTs that do not reassert THRE when the
2024                  * transmitter is idle and the interrupt has already
2025                  * been cleared.  Real 16550s should always reassert
2026                  * this interrupt whenever the transmitter is idle and
2027                  * the interrupt is enabled.  Delays are necessary to
2028                  * allow register changes to become visible.
2029                  */
2030                 spin_lock_irqsave(&up->port.lock, flags);
2031                 if (up->port.irqflags & IRQF_SHARED)
2032                         disable_irq_nosync(up->port.irq);
2033 
2034                 wait_for_xmitr(up, UART_LSR_THRE);
2035                 serial_out_sync(up, UART_IER, UART_IER_THRI);
2036                 udelay(1); /* allow THRE to set */
2037                 iir1 = serial_in(up, UART_IIR);
2038                 serial_out(up, UART_IER, 0);
2039                 serial_out_sync(up, UART_IER, UART_IER_THRI);
2040                 udelay(1); /* allow a working UART time to re-assert THRE */
2041                 iir = serial_in(up, UART_IIR);
2042                 serial_out(up, UART_IER, 0);
2043 
2044                 if (up->port.irqflags & IRQF_SHARED)
2045                         enable_irq(up->port.irq);
2046                 spin_unlock_irqrestore(&up->port.lock, flags);
2047 
2048                 /*
2049                  * If the interrupt is not reasserted, setup a timer to
2050                  * kick the UART on a regular basis.
2051                  */
2052                 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2053                         up->bugs |= UART_BUG_THRE;
2054                         pr_debug("ttyS%d - using backup timer\n",
2055                                  serial_index(port));
2056                 }
2057         }
2058 
2059         /*
2060          * The above check will only give an accurate result the first time
2061          * the port is opened so this value needs to be preserved.
2062          */
2063         if (up->bugs & UART_BUG_THRE) {
2064                 up->timer.function = serial8250_backup_timeout;
2065                 up->timer.data = (unsigned long)up;
2066                 mod_timer(&up->timer, jiffies +
2067                           poll_timeout(up->port.timeout) + HZ / 5);
2068         }
2069 
2070         /*
2071          * If the "interrupt" for this port doesn't correspond with any
2072          * hardware interrupt, we use a timer-based system.  The original
2073          * driver used to do this with IRQ0.
2074          */
2075         if (!is_real_interrupt(up->port.irq)) {
2076                 up->timer.data = (unsigned long)up;
2077                 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
2078         } else {
2079                 retval = serial_link_irq_chain(up);
2080                 if (retval)
2081                         return retval;
2082         }
2083 
2084         /*
2085          * Now, initialize the UART
2086          */
2087         serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2088 
2089         spin_lock_irqsave(&up->port.lock, flags);
2090         if (up->port.flags & UPF_FOURPORT) {
2091                 if (!is_real_interrupt(up->port.irq))
2092                         up->port.mctrl |= TIOCM_OUT1;
2093         } else
2094                 /*
2095                  * Most PC uarts need OUT2 raised to enable interrupts.
2096                  */
2097                 if (is_real_interrupt(up->port.irq))
2098                         up->port.mctrl |= TIOCM_OUT2;
2099 
2100         serial8250_set_mctrl(&up->port, up->port.mctrl);
2101 
2102         /* Serial over Lan (SoL) hack:
2103            Intel 8257x Gigabit ethernet chips have a
2104            16550 emulation, to be used for Serial Over Lan.
2105            Those chips take a longer time than a normal
2106            serial device to signalize that a transmission
2107            data was queued. Due to that, the above test generally
2108            fails. One solution would be to delay the reading of
2109            iir. However, this is not reliable, since the timeout
2110            is variable. So, let's just don't test if we receive
2111            TX irq. This way, we'll never enable UART_BUG_TXEN.
2112          */
2113         if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2114                 goto dont_test_tx_en;
2115 
2116         /*
2117          * Do a quick test to see if we receive an
2118          * interrupt when we enable the TX irq.
2119          */
2120         serial_outp(up, UART_IER, UART_IER_THRI);
2121         lsr = serial_in(up, UART_LSR);
2122         iir = serial_in(up, UART_IIR);
2123         serial_outp(up, UART_IER, 0);
2124 
2125         if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2126                 if (!(up->bugs & UART_BUG_TXEN)) {
2127                         up->bugs |= UART_BUG_TXEN;
2128                         pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2129                                  serial_index(port));
2130                 }
2131         } else {
2132                 up->bugs &= ~UART_BUG_TXEN;
2133         }
2134 
2135 dont_test_tx_en:
2136         spin_unlock_irqrestore(&up->port.lock, flags);
2137 
2138         /*
2139          * Clear the interrupt registers again for luck, and clear the
2140          * saved flags to avoid getting false values from polling
2141          * routines or the previous session.
2142          */
2143         serial_inp(up, UART_LSR);
2144         serial_inp(up, UART_RX);
2145         serial_inp(up, UART_IIR);
2146         serial_inp(up, UART_MSR);
2147         up->lsr_saved_flags = 0;
2148         up->msr_saved_flags = 0;
2149 
2150         /*
2151          * Finally, enable interrupts.  Note: Modem status interrupts
2152          * are set via set_termios(), which will be occurring imminently
2153          * anyway, so we don't enable them here.
2154          */
2155         up->ier = UART_IER_RLSI | UART_IER_RDI;
2156         serial_outp(up, UART_IER, up->ier);
2157 
2158         if (up->port.flags & UPF_FOURPORT) {
2159                 unsigned int icp;
2160                 /*
2161                  * Enable interrupts on the AST Fourport board
2162                  */
2163                 icp = (up->port.iobase & 0xfe0) | 0x01f;
2164                 outb_p(0x80, icp);
2165                 (void) inb_p(icp);
2166         }
2167 
2168         return 0;
2169 }
2170 
2171 static void serial8250_shutdown(struct uart_port *port)
2172 {
2173         struct uart_8250_port *up = (struct uart_8250_port *)port;
2174         unsigned long flags;
2175 
2176         /*
2177          * Disable interrupts from this port
2178          */
2179         up->ier = 0;
2180         serial_outp(up, UART_IER, 0);
2181 
2182         spin_lock_irqsave(&up->port.lock, flags);
2183         if (up->port.flags & UPF_FOURPORT) {
2184                 /* reset interrupts on the AST Fourport board */
2185                 inb((up->port.iobase & 0xfe0) | 0x1f);
2186                 up->port.mctrl |= TIOCM_OUT1;
2187         } else
2188                 up->port.mctrl &= ~TIOCM_OUT2;
2189 
2190         serial8250_set_mctrl(&up->port, up->port.mctrl);
2191         spin_unlock_irqrestore(&up->port.lock, flags);
2192 
2193         /*
2194          * Disable break condition and FIFOs
2195          */
2196         serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2197         serial8250_clear_fifos(up);
2198 
2199 #ifdef CONFIG_SERIAL_8250_RSA
2200         /*
2201          * Reset the RSA board back to 115kbps compat mode.
2202          */
2203         disable_rsa(up);
2204 #endif
2205 
2206         /*
2207          * Read data port to reset things, and then unlink from
2208          * the IRQ chain.
2209          */
2210         (void) serial_in(up, UART_RX);
2211 
2212         del_timer_sync(&up->timer);
2213         up->timer.function = serial8250_timeout;
2214         if (is_real_interrupt(up->port.irq))
2215                 serial_unlink_irq_chain(up);
2216 }
2217 
2218 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2219 {
2220         unsigned int quot;
2221 
2222         /*
2223          * Handle magic divisors for baud rates above baud_base on
2224          * SMSC SuperIO chips.
2225          */
2226         if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2227             baud == (port->uartclk/4))
2228                 quot = 0x8001;
2229         else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2230                  baud == (port->uartclk/8))
2231                 quot = 0x8002;
2232         else
2233                 quot = uart_get_divisor(port, baud);
2234 
2235         return quot;
2236 }
2237 
2238 static void
2239 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2240                        struct ktermios *old)
2241 {
2242         struct uart_8250_port *up = (struct uart_8250_port *)port;
2243         unsigned char cval, fcr = 0;
2244         unsigned long flags;
2245         unsigned int baud, quot;
2246 
2247         switch (termios->c_cflag & CSIZE) {
2248         case CS5:
2249                 cval = UART_LCR_WLEN5;
2250                 break;
2251         case CS6:
2252                 cval = UART_LCR_WLEN6;
2253                 break;
2254         case CS7:
2255                 cval = UART_LCR_WLEN7;
2256                 break;
2257         default:
2258         case CS8:
2259                 cval = UART_LCR_WLEN8;
2260                 break;
2261         }
2262 
2263         if (termios->c_cflag & CSTOPB)
2264                 cval |= UART_LCR_STOP;
2265         if (termios->c_cflag & PARENB)
2266                 cval |= UART_LCR_PARITY;
2267         if (!(termios->c_cflag & PARODD))
2268                 cval |= UART_LCR_EPAR;
2269 #ifdef CMSPAR
2270         if (termios->c_cflag & CMSPAR)
2271                 cval |= UART_LCR_SPAR;
2272 #endif
2273 
2274         /*
2275          * Ask the core to calculate the divisor for us.
2276          */
2277         baud = uart_get_baud_rate(port, termios, old,
2278                                   port->uartclk / 16 / 0xffff,
2279                                   port->uartclk / 16);
2280         quot = serial8250_get_divisor(port, baud);
2281 
2282         /*
2283          * Oxford Semi 952 rev B workaround
2284          */
2285         if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2286                 quot++;
2287 
2288         if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2289                 if (baud < 2400)
2290                         fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2291                 else
2292                         fcr = uart_config[up->port.type].fcr;
2293         }
2294 
2295         /*
2296          * MCR-based auto flow control.  When AFE is enabled, RTS will be
2297          * deasserted when the receive FIFO contains more characters than
2298          * the trigger, or the MCR RTS bit is cleared.  In the case where
2299          * the remote UART is not using CTS auto flow control, we must
2300          * have sufficient FIFO entries for the latency of the remote
2301          * UART to respond.  IOW, at least 32 bytes of FIFO.
2302          */
2303         if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2304                 up->mcr &= ~UART_MCR_AFE;
2305                 if (termios->c_cflag & CRTSCTS)
2306                         up->mcr |= UART_MCR_AFE;
2307         }
2308 
2309         /*
2310          * Ok, we're now changing the port state.  Do it with
2311          * interrupts disabled.
2312          */
2313         spin_lock_irqsave(&up->port.lock, flags);
2314 
2315         /*
2316          * Update the per-port timeout.
2317          */
2318         uart_update_timeout(port, termios->c_cflag, baud);
2319 
2320         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2321         if (termios->c_iflag & INPCK)
2322                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2323         if (termios->c_iflag & (BRKINT | PARMRK))
2324                 up->port.read_status_mask |= UART_LSR_BI;
2325 
2326         /*
2327          * Characteres to ignore
2328          */
2329         up->port.ignore_status_mask = 0;
2330         if (termios->c_iflag & IGNPAR)
2331                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2332         if (termios->c_iflag & IGNBRK) {
2333                 up->port.ignore_status_mask |= UART_LSR_BI;
2334                 /*
2335                  * If we're ignoring parity and break indicators,
2336                  * ignore overruns too (for real raw support).
2337                  */
2338                 if (termios->c_iflag & IGNPAR)
2339                         up->port.ignore_status_mask |= UART_LSR_OE;
2340         }
2341 
2342         /*
2343          * ignore all characters if CREAD is not set
2344          */
2345         if ((termios->c_cflag & CREAD) == 0)
2346                 up->port.ignore_status_mask |= UART_LSR_DR;
2347 
2348         /*
2349          * CTS flow control flag and modem status interrupts
2350          */
2351         up->ier &= ~UART_IER_MSI;
2352         if (!(up->bugs & UART_BUG_NOMSR) &&
2353                         UART_ENABLE_MS(&up->port, termios->c_cflag))
2354                 up->ier |= UART_IER_MSI;
2355         if (up->capabilities & UART_CAP_UUE)
2356                 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2357 
2358         serial_out(up, UART_IER, up->ier);
2359 
2360         if (up->capabilities & UART_CAP_EFR) {
2361                 unsigned char efr = 0;
2362                 /*
2363                  * TI16C752/Startech hardware flow control.  FIXME:
2364                  * - TI16C752 requires control thresholds to be set.
2365                  * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2366                  */
2367                 if (termios->c_cflag & CRTSCTS)
2368                         efr |= UART_EFR_CTS;
2369 
2370                 serial_outp(up, UART_LCR, 0xBF);
2371                 serial_outp(up, UART_EFR, efr);
2372         }
2373 
2374 #ifdef CONFIG_ARCH_OMAP
2375         /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2376         if (cpu_is_omap1510() && is_omap_port(up)) {
2377                 if (baud == 115200) {
2378                         quot = 1;
2379                         serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2380                 } else
2381                         serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2382         }
2383 #endif
2384 
2385         if (up->capabilities & UART_NATSEMI) {
2386                 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2387                 serial_outp(up, UART_LCR, 0xe0);
2388         } else {
2389                 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2390         }
2391 
2392         serial_dl_write(up, quot);
2393 
2394         /*
2395          * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2396          * is written without DLAB set, this mode will be disabled.
2397          */
2398         if (up->port.type == PORT_16750)
2399                 serial_outp(up, UART_FCR, fcr);
2400 
2401         serial_outp(up, UART_LCR, cval);                /* reset DLAB */
2402         up->lcr = cval;                                 /* Save LCR */
2403         if (up->port.type != PORT_16750) {
2404                 if (fcr & UART_FCR_ENABLE_FIFO) {
2405                         /* emulated UARTs (Lucent Venus 167x) need two steps */
2406                         serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2407                 }
2408                 serial_outp(up, UART_FCR, fcr);         /* set fcr */
2409         }
2410         serial8250_set_mctrl(&up->port, up->port.mctrl);
2411         spin_unlock_irqrestore(&up->port.lock, flags);
2412         /* Don't rewrite B0 */
2413         if (tty_termios_baud_rate(termios))
2414                 tty_termios_encode_baud_rate(termios, baud, baud);
2415 }
2416 
2417 static void
2418 serial8250_pm(struct uart_port *port, unsigned int state,
2419               unsigned int oldstate)
2420 {
2421         struct uart_8250_port *p = (struct uart_8250_port *)port;
2422 
2423         serial8250_set_sleep(p, state != 0);
2424 
2425         if (p->pm)
2426                 p->pm(port, state, oldstate);
2427 }
2428 
2429 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2430 {
2431         if (pt->port.iotype == UPIO_AU)
2432                 return 0x100000;
2433 #ifdef CONFIG_ARCH_OMAP
2434         if (is_omap_port(pt))
2435                 return 0x16 << pt->port.regshift;
2436 #endif
2437         return 8 << pt->port.regshift;
2438 }
2439 
2440 /*
2441  * Resource handling.
2442  */
2443 static int serial8250_request_std_resource(struct uart_8250_port *up)
2444 {
2445         unsigned int size = serial8250_port_size(up);
2446         int ret = 0;
2447 
2448         switch (up->port.iotype) {
2449         case UPIO_AU:
2450         case UPIO_TSI:
2451         case UPIO_MEM32:
2452         case UPIO_MEM:
2453         case UPIO_DWAPB:
2454                 if (!up->port.mapbase)
2455                         break;
2456 
2457                 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2458                         ret = -EBUSY;
2459                         break;
2460                 }
2461 
2462                 if (up->port.flags & UPF_IOREMAP) {
2463                         up->port.membase = ioremap_nocache(up->port.mapbase,
2464                                                                         size);
2465                         if (!up->port.membase) {
2466                                 release_mem_region(up->port.mapbase, size);
2467                                 ret = -ENOMEM;
2468                         }
2469                 }
2470                 break;
2471 
2472         case UPIO_HUB6:
2473         case UPIO_PORT:
2474                 if (!request_region(up->port.iobase, size, "serial"))
2475                         ret = -EBUSY;
2476                 break;
2477         }
2478         return ret;
2479 }
2480 
2481 static void serial8250_release_std_resource(struct uart_8250_port *up)
2482 {
2483         unsigned int size = serial8250_port_size(up);
2484 
2485         switch (up->port.iotype) {
2486         case UPIO_AU:
2487         case UPIO_TSI:
2488         case UPIO_MEM32:
2489         case UPIO_MEM:
2490         case UPIO_DWAPB:
2491                 if (!up->port.mapbase)
2492                         break;
2493 
2494                 if (up->port.flags & UPF_IOREMAP) {
2495                         iounmap(up->port.membase);
2496                         up->port.membase = NULL;
2497                 }
2498 
2499                 release_mem_region(up->port.mapbase, size);
2500                 break;
2501 
2502         case UPIO_HUB6:
2503         case UPIO_PORT:
2504                 release_region(up->port.iobase, size);
2505                 break;
2506         }
2507 }
2508 
2509 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2510 {
2511         unsigned long start = UART_RSA_BASE << up->port.regshift;
2512         unsigned int size = 8 << up->port.regshift;
2513         int ret = -EINVAL;
2514 
2515         switch (up->port.iotype) {
2516         case UPIO_HUB6:
2517         case UPIO_PORT:
2518                 start += up->port.iobase;
2519                 if (request_region(start, size, "serial-rsa"))
2520                         ret = 0;
2521                 else
2522                         ret = -EBUSY;
2523                 break;
2524         }
2525 
2526         return ret;
2527 }
2528 
2529 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2530 {
2531         unsigned long offset = UART_RSA_BASE << up->port.regshift;
2532         unsigned int size = 8 << up->port.regshift;
2533 
2534         switch (up->port.iotype) {
2535         case UPIO_HUB6:
2536         case UPIO_PORT:
2537                 release_region(up->port.iobase + offset, size);
2538                 break;
2539         }
2540 }
2541 
2542 static void serial8250_release_port(struct uart_port *port)
2543 {
2544         struct uart_8250_port *up = (struct uart_8250_port *)port;
2545 
2546         serial8250_release_std_resource(up);
2547         if (up->port.type == PORT_RSA)
2548                 serial8250_release_rsa_resource(up);
2549 }
2550 
2551 static int serial8250_request_port(struct uart_port *port)
2552 {
2553         struct uart_8250_port *up = (struct uart_8250_port *)port;
2554         int ret = 0;
2555 
2556         ret = serial8250_request_std_resource(up);
2557         if (ret == 0 && up->port.type == PORT_RSA) {
2558                 ret = serial8250_request_rsa_resource(up);
2559                 if (ret < 0)
2560                         serial8250_release_std_resource(up);
2561         }
2562 
2563         return ret;
2564 }
2565 
2566 static void serial8250_config_port(struct uart_port *port, int flags)
2567 {
2568         struct uart_8250_port *up = (struct uart_8250_port *)port;
2569         int probeflags = PROBE_ANY;
2570         int ret;
2571 
2572         /*
2573          * Find the region that we can probe for.  This in turn
2574          * tells us whether we can probe for the type of port.
2575          */
2576         ret = serial8250_request_std_resource(up);
2577         if (ret < 0)
2578                 return;
2579 
2580         ret = serial8250_request_rsa_resource(up);
2581         if (ret < 0)
2582                 probeflags &= ~PROBE_RSA;
2583 
2584         if (up->port.iotype != up->cur_iotype)
2585                 set_io_from_upio(port);
2586 
2587         if (flags & UART_CONFIG_TYPE)
2588                 autoconfig(up, probeflags);
2589         if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2590                 autoconfig_irq(up);
2591 
2592         if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2593                 serial8250_release_rsa_resource(up);
2594         if (up->port.type == PORT_UNKNOWN)
2595                 serial8250_release_std_resource(up);
2596 }
2597 
2598 static int
2599 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2600 {
2601         if (ser->irq >= nr_irqs || ser->irq < 0 ||
2602             ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2603             ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2604             ser->type == PORT_STARTECH)
2605                 return -EINVAL;
2606         return 0;
2607 }
2608 
2609 static const char *
2610 serial8250_type(struct uart_port *port)
2611 {
2612         int type = port->type;
2613 
2614         if (type >= ARRAY_SIZE(uart_config))
2615                 type = 0;
2616         return uart_config[type].name;
2617 }
2618 
2619 static struct uart_ops serial8250_pops = {
2620         .tx_empty       = serial8250_tx_empty,
2621         .set_mctrl      = serial8250_set_mctrl,
2622         .get_mctrl      = serial8250_get_mctrl,
2623         .stop_tx        = serial8250_stop_tx,
2624         .start_tx       = serial8250_start_tx,
2625         .stop_rx        = serial8250_stop_rx,
2626         .enable_ms      = serial8250_enable_ms,
2627         .break_ctl      = serial8250_break_ctl,
2628         .startup        = serial8250_startup,
2629         .shutdown       = serial8250_shutdown,
2630         .set_termios    = serial8250_set_termios,
2631         .pm             = serial8250_pm,
2632         .type           = serial8250_type,
2633         .release_port   = serial8250_release_port,
2634         .request_port   = serial8250_request_port,
2635         .config_port    = serial8250_config_port,
2636         .verify_port    = serial8250_verify_port,
2637 #ifdef CONFIG_CONSOLE_POLL
2638         .poll_get_char = serial8250_get_poll_char,
2639         .poll_put_char = serial8250_put_poll_char,
2640 #endif
2641 };
2642 
2643 static struct uart_8250_port serial8250_ports[UART_NR];
2644 
2645 static void __init serial8250_isa_init_ports(void)
2646 {
2647         struct uart_8250_port *up;
2648         static int first = 1;
2649         int i;
2650 
2651         if (!first)
2652                 return;
2653         first = 0;
2654 
2655         for (i = 0; i < nr_uarts; i++) {
2656                 struct uart_8250_port *up = &serial8250_ports[i];
2657 
2658                 up->port.line = i;
2659                 spin_lock_init(&up->port.lock);
2660 
2661                 init_timer(&up->timer);
2662                 up->timer.function = serial8250_timeout;
2663 
2664                 /*
2665                  * ALPHA_KLUDGE_MCR needs to be killed.
2666                  */
2667                 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2668                 up->mcr_force = ALPHA_KLUDGE_MCR;
2669 
2670                 up->port.ops = &serial8250_pops;
2671         }
2672 
2673         for (i = 0, up = serial8250_ports;
2674              i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2675              i++, up++) {
2676                 up->port.iobase   = old_serial_port[i].port;
2677                 up->port.irq      = irq_canonicalize(old_serial_port[i].irq);
2678                 up->port.irqflags = old_serial_port[i].irqflags;
2679                 up->port.uartclk  = old_serial_port[i].baud_base * 16;
2680                 up->port.flags    = old_serial_port[i].flags;
2681                 up->port.hub6     = old_serial_port[i].hub6;
2682                 up->port.membase  = old_serial_port[i].iomem_base;
2683                 up->port.iotype   = old_serial_port[i].io_type;
2684                 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2685                 set_io_from_upio(&up->port);
2686                 if (share_irqs)
2687                         up->port.irqflags |= IRQF_SHARED;
2688         }
2689 }
2690 
2691 static void __init
2692 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2693 {
2694         int i;
2695 
2696         for (i = 0; i < nr_uarts; i++) {
2697                 struct uart_8250_port *up = &serial8250_ports[i];
2698                 up->cur_iotype = 0xFF;
2699         }
2700 
2701         serial8250_isa_init_ports();
2702 
2703         for (i = 0; i < nr_uarts; i++) {
2704                 struct uart_8250_port *up = &serial8250_ports[i];
2705 
2706                 up->port.dev = dev;
2707                 uart_add_one_port(drv, &up->port);
2708         }
2709 }
2710 
2711 #ifdef CONFIG_SERIAL_8250_CONSOLE
2712 
2713 static void serial8250_console_putchar(struct uart_port *port, int ch)
2714 {
2715         struct uart_8250_port *up = (struct uart_8250_port *)port;
2716 
2717         wait_for_xmitr(up, UART_LSR_THRE);
2718         serial_out(up, UART_TX, ch);
2719 }
2720 
2721 /*
2722  *      Print a string to the serial port trying not to disturb
2723  *      any possible real use of the port...
2724  *
2725  *      The console_lock must be held when we get here.
2726  */
2727 static void
2728 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2729 {
2730         struct uart_8250_port *up = &serial8250_ports[co->index];
2731         unsigned long flags;
2732         unsigned int ier;
2733         int locked = 1;
2734 
2735         touch_nmi_watchdog();
2736 
2737         local_irq_save(flags);
2738         if (up->port.sysrq) {
2739                 /* serial8250_handle_port() already took the lock */
2740                 locked = 0;
2741         } else if (oops_in_progress) {
2742                 locked = spin_trylock(&up->port.lock);
2743         } else
2744                 spin_lock(&up->port.lock);
2745 
2746         /*
2747          *      First save the IER then disable the interrupts
2748          */
2749         ier = serial_in(up, UART_IER);
2750 
2751         if (up->capabilities & UART_CAP_UUE)
2752                 serial_out(up, UART_IER, UART_IER_UUE);
2753         else
2754                 serial_out(up, UART_IER, 0);
2755 
2756         uart_console_write(&up->port, s, count, serial8250_console_putchar);
2757 
2758         /*
2759          *      Finally, wait for transmitter to become empty
2760          *      and restore the IER
2761          */
2762         wait_for_xmitr(up, BOTH_EMPTY);
2763         serial_out(up, UART_IER, ier);
2764 
2765         /*
2766          *      The receive handling will happen properly because the
2767          *      receive ready bit will still be set; it is not cleared
2768          *      on read.  However, modem control will not, we must
2769          *      call it if we have saved something in the saved flags
2770          *      while processing with interrupts off.
2771          */
2772         if (up->msr_saved_flags)
2773                 check_modem_status(up);
2774 
2775         if (locked)
2776                 spin_unlock(&up->port.lock);
2777         local_irq_restore(flags);
2778 }
2779 
2780 static int __init serial8250_console_setup(struct console *co, char *options)
2781 {
2782         struct uart_port *port;
2783         int baud = 9600;
2784         int bits = 8;
2785         int parity = 'n';
2786         int flow = 'n';
2787 
2788         /*
2789          * Check whether an invalid uart number has been specified, and
2790          * if so, search for the first available port that does have
2791          * console support.
2792          */
2793         if (co->index >= nr_uarts)
2794                 co->index = 0;
2795         port = &serial8250_ports[co->index].port;
2796         if (!port->iobase && !port->membase)
2797                 return -ENODEV;
2798 
2799         if (options)
2800                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2801 
2802         return uart_set_options(port, co, baud, parity, bits, flow);
2803 }
2804 
2805 static int serial8250_console_early_setup(void)
2806 {
2807         return serial8250_find_port_for_earlycon();
2808 }
2809 
2810 static struct console serial8250_console = {
2811         .name           = "ttyS",
2812         .write          = serial8250_console_write,
2813         .device         = uart_console_device,
2814         .setup          = serial8250_console_setup,
2815         .early_setup    = serial8250_console_early_setup,
2816         .flags          = CON_PRINTBUFFER,
2817         .index          = -1,
2818         .data           = &serial8250_reg,
2819 };
2820 
2821 static int __init serial8250_console_init(void)
2822 {
2823         if (nr_uarts > UART_NR)
2824                 nr_uarts = UART_NR;
2825 
2826         serial8250_isa_init_ports();
2827         register_console(&serial8250_console);
2828         return 0;
2829 }
2830 console_initcall(serial8250_console_init);
2831 
2832 int serial8250_find_port(struct uart_port *p)
2833 {
2834         int line;
2835         struct uart_port *port;
2836 
2837         for (line = 0; line < nr_uarts; line++) {
2838                 port = &serial8250_ports[line].port;
2839                 if (uart_match_port(p, port))
2840                         return line;
2841         }
2842         return -ENODEV;
2843 }
2844 
2845 #define SERIAL8250_CONSOLE      &serial8250_console
2846 #else
2847 #define SERIAL8250_CONSOLE      NULL
2848 #endif
2849 
2850 static struct uart_driver serial8250_reg = {
2851         .owner                  = THIS_MODULE,
2852         .driver_name            = "serial",
2853         .dev_name               = "ttyS",
2854         .major                  = TTY_MAJOR,
2855         .minor                  = 64,
2856         .cons                   = SERIAL8250_CONSOLE,
2857 };
2858 
2859 /*
2860  * early_serial_setup - early registration for 8250 ports
2861  *
2862  * Setup an 8250 port structure prior to console initialisation.  Use
2863  * after console initialisation will cause undefined behaviour.
2864  */
2865 int __init early_serial_setup(struct uart_port *port)
2866 {
2867         struct uart_port *p;
2868 
2869         if (port->line >= ARRAY_SIZE(serial8250_ports))
2870                 return -ENODEV;
2871 
2872         serial8250_isa_init_ports();
2873         p = &serial8250_ports[port->line].port;
2874         p->iobase       = port->iobase;
2875         p->membase      = port->membase;
2876         p->irq          = port->irq;
2877         p->irqflags     = port->irqflags;
2878         p->uartclk      = port->uartclk;
2879         p->fifosize     = port->fifosize;
2880         p->regshift     = port->regshift;
2881         p->iotype       = port->iotype;
2882         p->flags        = port->flags;
2883         p->mapbase      = port->mapbase;
2884         p->private_data = port->private_data;
2885         p->type         = port->type;
2886         p->line         = port->line;
2887 
2888         set_io_from_upio(p);
2889         if (port->serial_in)
2890                 p->serial_in = port->serial_in;
2891         if (port->serial_out)
2892                 p->serial_out = port->serial_out;
2893 
2894         return 0;
2895 }
2896 
2897 /**
2898  *      serial8250_suspend_port - suspend one serial port
2899  *      @line:  serial line number
2900  *
2901  *      Suspend one serial port.
2902  */
2903 void serial8250_suspend_port(int line)
2904 {
2905         uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2906 }
2907 
2908 /**
2909  *      serial8250_resume_port - resume one serial port
2910  *      @line:  serial line number
2911  *
2912  *      Resume one serial port.
2913  */
2914 void serial8250_resume_port(int line)
2915 {
2916         struct uart_8250_port *up = &serial8250_ports[line];
2917 
2918         if (up->capabilities & UART_NATSEMI) {
2919                 unsigned char tmp;
2920 
2921                 /* Ensure it's still in high speed mode */
2922                 serial_outp(up, UART_LCR, 0xE0);
2923 
2924                 tmp = serial_in(up, 0x04); /* EXCR2 */
2925                 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2926                 tmp |= 0x10;  /* 1.625 divisor for baud_base --> 921600 */
2927                 serial_outp(up, 0x04, tmp);
2928 
2929                 serial_outp(up, UART_LCR, 0);
2930         }
2931         uart_resume_port(&serial8250_reg, &up->port);
2932 }
2933 
2934 /*
2935  * Register a set of serial devices attached to a platform device.  The
2936  * list is terminated with a zero flags entry, which means we expect
2937  * all entries to have at least UPF_BOOT_AUTOCONF set.
2938  */
2939 static int __devinit serial8250_probe(struct platform_device *dev)
2940 {
2941         struct plat_serial8250_port *p = dev->dev.platform_data;
2942         struct uart_port port;
2943         int ret, i;
2944 
2945         memset(&port, 0, sizeof(struct uart_port));
2946 
2947         for (i = 0; p && p->flags != 0; p++, i++) {
2948                 port.iobase             = p->iobase;
2949                 port.membase            = p->membase;
2950                 port.irq                = p->irq;
2951                 port.irqflags           = p->irqflags;
2952                 port.uartclk            = p->uartclk;
2953                 port.regshift           = p->regshift;
2954                 port.iotype             = p->iotype;
2955                 port.flags              = p->flags;
2956                 port.mapbase            = p->mapbase;
2957                 port.hub6               = p->hub6;
2958                 port.private_data       = p->private_data;
2959                 port.type               = p->type;
2960                 port.serial_in          = p->serial_in;
2961                 port.serial_out         = p->serial_out;
2962                 port.dev                = &dev->dev;
2963                 if (share_irqs)
2964                         port.irqflags |= IRQF_SHARED;
2965                 ret = serial8250_register_port(&port);
2966                 if (ret < 0) {
2967                         dev_err(&dev->dev, "unable to register port at index %d "
2968                                 "(IO%lx MEM%llx IRQ%d): %d\n", i,
2969                                 p->iobase, (unsigned long long)p->mapbase,
2970                                 p->irq, ret);
2971                 }
2972         }
2973         return 0;
2974 }
2975 
2976 /*
2977  * Remove serial ports registered against a platform device.
2978  */
2979 static int __devexit serial8250_remove(struct platform_device *dev)
2980 {
2981         int i;
2982 
2983         for (i = 0; i < nr_uarts; i++) {
2984                 struct uart_8250_port *up = &serial8250_ports[i];
2985 
2986                 if (up->port.dev == &dev->dev)
2987                         serial8250_unregister_port(i);
2988         }
2989         return 0;
2990 }
2991 
2992 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
2993 {
2994         int i;
2995 
2996         for (i = 0; i < UART_NR; i++) {
2997                 struct uart_8250_port *up = &serial8250_ports[i];
2998 
2999                 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3000                         uart_suspend_port(&serial8250_reg, &up->port);
3001         }
3002 
3003         return 0;
3004 }
3005 
3006 static int serial8250_resume(struct platform_device *dev)
3007 {
3008         int i;
3009 
3010         for (i = 0; i < UART_NR; i++) {
3011                 struct uart_8250_port *up = &serial8250_ports[i];
3012 
3013                 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3014                         serial8250_resume_port(i);
3015         }
3016 
3017         return 0;
3018 }
3019 
3020 static struct platform_driver serial8250_isa_driver = {
3021         .probe          = serial8250_probe,
3022         .remove         = __devexit_p(serial8250_remove),
3023         .suspend        = serial8250_suspend,
3024         .resume         = serial8250_resume,
3025         .driver         = {
3026                 .name   = "serial8250",
3027                 .owner  = THIS_MODULE,
3028         },
3029 };
3030 
3031 /*
3032  * This "device" covers _all_ ISA 8250-compatible serial devices listed
3033  * in the table in include/asm/serial.h
3034  */
3035 static struct platform_device *serial8250_isa_devs;
3036 
3037 /*
3038  * serial8250_register_port and serial8250_unregister_port allows for
3039  * 16x50 serial ports to be configured at run-time, to support PCMCIA
3040  * modems and PCI multiport cards.
3041  */
3042 static DEFINE_MUTEX(serial_mutex);
3043 
3044 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3045 {
3046         int i;
3047 
3048         /*
3049          * First, find a port entry which matches.
3050          */
3051         for (i = 0; i < nr_uarts; i++)
3052                 if (uart_match_port(&serial8250_ports[i].port, port))
3053                         return &serial8250_ports[i];
3054 
3055         /*
3056          * We didn't find a matching entry, so look for the first
3057          * free entry.  We look for one which hasn't been previously
3058          * used (indicated by zero iobase).
3059          */
3060         for (i = 0; i < nr_uarts; i++)
3061                 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3062                     serial8250_ports[i].port.iobase == 0)
3063                         return &serial8250_ports[i];
3064 
3065         /*
3066          * That also failed.  Last resort is to find any entry which
3067          * doesn't have a real port associated with it.
3068          */
3069         for (i = 0; i < nr_uarts; i++)
3070                 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3071                         return &serial8250_ports[i];
3072 
3073         return NULL;
3074 }
3075 
3076 /**
3077  *      serial8250_register_port - register a serial port
3078  *      @port: serial port template
3079  *
3080  *      Configure the serial port specified by the request. If the
3081  *      port exists and is in use, it is hung up and unregistered
3082  *      first.
3083  *
3084  *      The port is then probed and if necessary the IRQ is autodetected
3085  *      If this fails an error is returned.
3086  *
3087  *      On success the port is ready to use and the line number is returned.
3088  */
3089 int serial8250_register_port(struct uart_port *port)
3090 {
3091         struct uart_8250_port *uart;
3092         int ret = -ENOSPC;
3093 
3094         if (port->uartclk == 0)
3095                 return -EINVAL;
3096 
3097         mutex_lock(&serial_mutex);
3098 
3099         uart = serial8250_find_match_or_unused(port);
3100         if (uart) {
3101                 uart_remove_one_port(&serial8250_reg, &uart->port);
3102 
3103                 uart->port.iobase       = port->iobase;
3104                 uart->port.membase      = port->membase;
3105                 uart->port.irq          = port->irq;
3106                 uart->port.irqflags     = port->irqflags;
3107                 uart->port.uartclk      = port->uartclk;
3108                 uart->port.fifosize     = port->fifosize;
3109                 uart->port.regshift     = port->regshift;
3110                 uart->port.iotype       = port->iotype;
3111                 uart->port.flags        = port->flags | UPF_BOOT_AUTOCONF;
3112                 uart->port.mapbase      = port->mapbase;
3113                 uart->port.private_data = port->private_data;
3114                 if (port->dev)
3115                         uart->port.dev = port->dev;
3116 
3117                 if (port->flags & UPF_FIXED_TYPE) {
3118                         uart->port.type = port->type;
3119                         uart->port.fifosize = uart_config[port->type].fifo_size;
3120                         uart->capabilities = uart_config[port->type].flags;
3121                         uart->tx_loadsz = uart_config[port->type].tx_loadsz;
3122                 }
3123 
3124                 set_io_from_upio(&uart->port);
3125                 /* Possibly override default I/O functions.  */
3126                 if (port->serial_in)
3127                         uart->port.serial_in = port->serial_in;
3128                 if (port->serial_out)
3129                         uart->port.serial_out = port->serial_out;
3130 
3131                 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3132                 if (ret == 0)
3133                         ret = uart->port.line;
3134         }
3135         mutex_unlock(&serial_mutex);
3136 
3137         return ret;
3138 }
3139 EXPORT_SYMBOL(serial8250_register_port);
3140 
3141 /**
3142  *      serial8250_unregister_port - remove a 16x50 serial port at runtime
3143  *      @line: serial line number
3144  *
3145  *      Remove one serial port.  This may not be called from interrupt
3146  *      context.  We hand the port back to the our control.
3147  */
3148 void serial8250_unregister_port(int line)
3149 {
3150         struct uart_8250_port *uart = &serial8250_ports[line];
3151 
3152         mutex_lock(&serial_mutex);
3153         uart_remove_one_port(&serial8250_reg, &uart->port);
3154         if (serial8250_isa_devs) {
3155                 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3156                 uart->port.type = PORT_UNKNOWN;
3157                 uart->port.dev = &serial8250_isa_devs->dev;
3158                 uart_add_one_port(&serial8250_reg, &uart->port);
3159         } else {
3160                 uart->port.dev = NULL;
3161         }
3162         mutex_unlock(&serial_mutex);
3163 }
3164 EXPORT_SYMBOL(serial8250_unregister_port);
3165 
3166 static int __init serial8250_init(void)
3167 {
3168         int ret;
3169 
3170         if (nr_uarts > UART_NR)
3171                 nr_uarts = UART_NR;
3172 
3173         printk(KERN_INFO "Serial: 8250/16550 driver, "
3174                 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3175                 share_irqs ? "en" : "dis");
3176 
3177 #ifdef CONFIG_SPARC
3178         ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3179 #else
3180         serial8250_reg.nr = UART_NR;
3181         ret = uart_register_driver(&serial8250_reg);
3182 #endif
3183         if (ret)
3184                 goto out;
3185 
3186         serial8250_isa_devs = platform_device_alloc("serial8250",
3187                                                     PLAT8250_DEV_LEGACY);
3188         if (!serial8250_isa_devs) {
3189                 ret = -ENOMEM;
3190                 goto unreg_uart_drv;
3191         }
3192 
3193         ret = platform_device_add(serial8250_isa_devs);
3194         if (ret)
3195                 goto put_dev;
3196 
3197         serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3198 
3199         ret = platform_driver_register(&serial8250_isa_driver);
3200         if (ret == 0)
3201                 goto out;
3202 
3203         platform_device_del(serial8250_isa_devs);
3204 put_dev:
3205         platform_device_put(serial8250_isa_devs);
3206 unreg_uart_drv:
3207 #ifdef CONFIG_SPARC
3208         sunserial_unregister_minors(&serial8250_reg, UART_NR);
3209 #else
3210         uart_unregister_driver(&serial8250_reg);
3211 #endif
3212 out:
3213         return ret;
3214 }
3215 
3216 static void __exit serial8250_exit(void)
3217 {
3218         struct platform_device *isa_dev = serial8250_isa_devs;
3219 
3220         /*
3221          * This tells serial8250_unregister_port() not to re-register
3222          * the ports (thereby making serial8250_isa_driver permanently
3223          * in use.)
3224          */
3225         serial8250_isa_devs = NULL;
3226 
3227         platform_driver_unregister(&serial8250_isa_driver);
3228         platform_device_unregister(isa_dev);
3229 
3230 #ifdef CONFIG_SPARC
3231         sunserial_unregister_minors(&serial8250_reg, UART_NR);
3232 #else
3233         uart_unregister_driver(&serial8250_reg);
3234 #endif
3235 }
3236 
3237 module_init(serial8250_init);
3238 module_exit(serial8250_exit);
3239 
3240 EXPORT_SYMBOL(serial8250_suspend_port);
3241 EXPORT_SYMBOL(serial8250_resume_port);
3242 
3243 MODULE_LICENSE("GPL");
3244 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3245 
3246 module_param(share_irqs, uint, 0644);
3247 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3248         " (unsafe)");
3249 
3250 module_param(nr_uarts, uint, 0644);
3251 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3252 
3253 module_param(skip_txen_test, uint, 0644);
3254 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3255 
3256 #ifdef CONFIG_SERIAL_8250_RSA
3257 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3258 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3259 #endif
3260 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
3261 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us