Version:  2.0.40 2.2.26 2.4.37 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1

Linux/drivers/scsi/pm8001/pm8001_init.c

  1 /*
  2  * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
  3  *
  4  * Copyright (c) 2008-2009 USI Co., Ltd.
  5  * All rights reserved.
  6  *
  7  * Redistribution and use in source and binary forms, with or without
  8  * modification, are permitted provided that the following conditions
  9  * are met:
 10  * 1. Redistributions of source code must retain the above copyright
 11  *    notice, this list of conditions, and the following disclaimer,
 12  *    without modification.
 13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
 14  *    substantially similar to the "NO WARRANTY" disclaimer below
 15  *    ("Disclaimer") and any redistribution must be conditioned upon
 16  *    including a substantially similar Disclaimer requirement for further
 17  *    binary redistribution.
 18  * 3. Neither the names of the above-listed copyright holders nor the names
 19  *    of any contributors may be used to endorse or promote products derived
 20  *    from this software without specific prior written permission.
 21  *
 22  * Alternatively, this software may be distributed under the terms of the
 23  * GNU General Public License ("GPL") version 2 as published by the Free
 24  * Software Foundation.
 25  *
 26  * NO WARRANTY
 27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
 30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 37  * POSSIBILITY OF SUCH DAMAGES.
 38  *
 39  */
 40 
 41 #include <linux/slab.h>
 42 #include "pm8001_sas.h"
 43 #include "pm8001_chips.h"
 44 
 45 static struct scsi_transport_template *pm8001_stt;
 46 
 47 /**
 48  * chip info structure to identify chip key functionality as
 49  * encryption available/not, no of ports, hw specific function ref
 50  */
 51 static const struct pm8001_chip_info pm8001_chips[] = {
 52         [chip_8001] = {0,  8, &pm8001_8001_dispatch,},
 53         [chip_8008] = {0,  8, &pm8001_80xx_dispatch,},
 54         [chip_8009] = {1,  8, &pm8001_80xx_dispatch,},
 55         [chip_8018] = {0,  16, &pm8001_80xx_dispatch,},
 56         [chip_8019] = {1,  16, &pm8001_80xx_dispatch,},
 57         [chip_8074] = {0,  8, &pm8001_80xx_dispatch,},
 58         [chip_8076] = {0,  16, &pm8001_80xx_dispatch,},
 59         [chip_8077] = {0,  16, &pm8001_80xx_dispatch,},
 60 };
 61 static int pm8001_id;
 62 
 63 LIST_HEAD(hba_list);
 64 
 65 struct workqueue_struct *pm8001_wq;
 66 
 67 /**
 68  * The main structure which LLDD must register for scsi core.
 69  */
 70 static struct scsi_host_template pm8001_sht = {
 71         .module                 = THIS_MODULE,
 72         .name                   = DRV_NAME,
 73         .queuecommand           = sas_queuecommand,
 74         .target_alloc           = sas_target_alloc,
 75         .slave_configure        = sas_slave_configure,
 76         .scan_finished          = pm8001_scan_finished,
 77         .scan_start             = pm8001_scan_start,
 78         .change_queue_depth     = sas_change_queue_depth,
 79         .bios_param             = sas_bios_param,
 80         .can_queue              = 1,
 81         .cmd_per_lun            = 1,
 82         .this_id                = -1,
 83         .sg_tablesize           = SG_ALL,
 84         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
 85         .use_clustering         = ENABLE_CLUSTERING,
 86         .eh_device_reset_handler = sas_eh_device_reset_handler,
 87         .eh_bus_reset_handler   = sas_eh_bus_reset_handler,
 88         .target_destroy         = sas_target_destroy,
 89         .ioctl                  = sas_ioctl,
 90         .shost_attrs            = pm8001_host_attrs,
 91         .use_blk_tags           = 1,
 92         .track_queue_depth      = 1,
 93 };
 94 
 95 /**
 96  * Sas layer call this function to execute specific task.
 97  */
 98 static struct sas_domain_function_template pm8001_transport_ops = {
 99         .lldd_dev_found         = pm8001_dev_found,
100         .lldd_dev_gone          = pm8001_dev_gone,
101 
102         .lldd_execute_task      = pm8001_queue_command,
103         .lldd_control_phy       = pm8001_phy_control,
104 
105         .lldd_abort_task        = pm8001_abort_task,
106         .lldd_abort_task_set    = pm8001_abort_task_set,
107         .lldd_clear_aca         = pm8001_clear_aca,
108         .lldd_clear_task_set    = pm8001_clear_task_set,
109         .lldd_I_T_nexus_reset   = pm8001_I_T_nexus_reset,
110         .lldd_lu_reset          = pm8001_lu_reset,
111         .lldd_query_task        = pm8001_query_task,
112 };
113 
114 /**
115  *pm8001_phy_init - initiate our adapter phys
116  *@pm8001_ha: our hba structure.
117  *@phy_id: phy id.
118  */
119 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
120 {
121         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
122         struct asd_sas_phy *sas_phy = &phy->sas_phy;
123         phy->phy_state = 0;
124         phy->pm8001_ha = pm8001_ha;
125         sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
126         sas_phy->class = SAS;
127         sas_phy->iproto = SAS_PROTOCOL_ALL;
128         sas_phy->tproto = 0;
129         sas_phy->type = PHY_TYPE_PHYSICAL;
130         sas_phy->role = PHY_ROLE_INITIATOR;
131         sas_phy->oob_mode = OOB_NOT_CONNECTED;
132         sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
133         sas_phy->id = phy_id;
134         sas_phy->sas_addr = &pm8001_ha->sas_addr[0];
135         sas_phy->frame_rcvd = &phy->frame_rcvd[0];
136         sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
137         sas_phy->lldd_phy = phy;
138 }
139 
140 /**
141  *pm8001_free - free hba
142  *@pm8001_ha:   our hba structure.
143  *
144  */
145 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
146 {
147         int i;
148 
149         if (!pm8001_ha)
150                 return;
151 
152         for (i = 0; i < USI_MAX_MEMCNT; i++) {
153                 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
154                         pci_free_consistent(pm8001_ha->pdev,
155                                 (pm8001_ha->memoryMap.region[i].total_len +
156                                 pm8001_ha->memoryMap.region[i].alignment),
157                                 pm8001_ha->memoryMap.region[i].virt_ptr,
158                                 pm8001_ha->memoryMap.region[i].phys_addr);
159                         }
160         }
161         PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
162         if (pm8001_ha->shost)
163                 scsi_host_put(pm8001_ha->shost);
164         flush_workqueue(pm8001_wq);
165         kfree(pm8001_ha->tags);
166         kfree(pm8001_ha);
167 }
168 
169 #ifdef PM8001_USE_TASKLET
170 
171 /**
172  * tasklet for 64 msi-x interrupt handler
173  * @opaque: the passed general host adapter struct
174  * Note: pm8001_tasklet is common for pm8001 & pm80xx
175  */
176 static void pm8001_tasklet(unsigned long opaque)
177 {
178         struct pm8001_hba_info *pm8001_ha;
179         struct isr_param *irq_vector;
180 
181         irq_vector = (struct isr_param *)opaque;
182         pm8001_ha = irq_vector->drv_inst;
183         if (unlikely(!pm8001_ha))
184                 BUG_ON(1);
185         PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
186 }
187 #endif
188 
189 /**
190  * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
191  * It obtains the vector number and calls the equivalent bottom
192  * half or services directly.
193  * @opaque: the passed outbound queue/vector. Host structure is
194  * retrieved from the same.
195  */
196 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
197 {
198         struct isr_param *irq_vector;
199         struct pm8001_hba_info *pm8001_ha;
200         irqreturn_t ret = IRQ_HANDLED;
201         irq_vector = (struct isr_param *)opaque;
202         pm8001_ha = irq_vector->drv_inst;
203 
204         if (unlikely(!pm8001_ha))
205                 return IRQ_NONE;
206         if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
207                 return IRQ_NONE;
208 #ifdef PM8001_USE_TASKLET
209         tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
210 #else
211         ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
212 #endif
213         return ret;
214 }
215 
216 /**
217  * pm8001_interrupt_handler_intx - main INTx interrupt handler.
218  * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure.
219  */
220 
221 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
222 {
223         struct pm8001_hba_info *pm8001_ha;
224         irqreturn_t ret = IRQ_HANDLED;
225         struct sas_ha_struct *sha = dev_id;
226         pm8001_ha = sha->lldd_ha;
227         if (unlikely(!pm8001_ha))
228                 return IRQ_NONE;
229         if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
230                 return IRQ_NONE;
231 
232 #ifdef PM8001_USE_TASKLET
233         tasklet_schedule(&pm8001_ha->tasklet[0]);
234 #else
235         ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
236 #endif
237         return ret;
238 }
239 
240 /**
241  * pm8001_alloc - initiate our hba structure and 6 DMAs area.
242  * @pm8001_ha:our hba structure.
243  *
244  */
245 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
246                         const struct pci_device_id *ent)
247 {
248         int i;
249         spin_lock_init(&pm8001_ha->lock);
250         spin_lock_init(&pm8001_ha->bitmap_lock);
251         PM8001_INIT_DBG(pm8001_ha,
252                 pm8001_printk("pm8001_alloc: PHY:%x\n",
253                                 pm8001_ha->chip->n_phy));
254         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
255                 pm8001_phy_init(pm8001_ha, i);
256                 pm8001_ha->port[i].wide_port_phymap = 0;
257                 pm8001_ha->port[i].port_attached = 0;
258                 pm8001_ha->port[i].port_state = 0;
259                 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
260         }
261 
262         pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL);
263         if (!pm8001_ha->tags)
264                 goto err_out;
265         /* MPI Memory region 1 for AAP Event Log for fw */
266         pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
267         pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
268         pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
269         pm8001_ha->memoryMap.region[AAP1].alignment = 32;
270 
271         /* MPI Memory region 2 for IOP Event Log for fw */
272         pm8001_ha->memoryMap.region[IOP].num_elements = 1;
273         pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
274         pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
275         pm8001_ha->memoryMap.region[IOP].alignment = 32;
276 
277         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
278                 /* MPI Memory region 3 for consumer Index of inbound queues */
279                 pm8001_ha->memoryMap.region[CI+i].num_elements = 1;
280                 pm8001_ha->memoryMap.region[CI+i].element_size = 4;
281                 pm8001_ha->memoryMap.region[CI+i].total_len = 4;
282                 pm8001_ha->memoryMap.region[CI+i].alignment = 4;
283 
284                 if ((ent->driver_data) != chip_8001) {
285                         /* MPI Memory region 5 inbound queues */
286                         pm8001_ha->memoryMap.region[IB+i].num_elements =
287                                                 PM8001_MPI_QUEUE;
288                         pm8001_ha->memoryMap.region[IB+i].element_size = 128;
289                         pm8001_ha->memoryMap.region[IB+i].total_len =
290                                                 PM8001_MPI_QUEUE * 128;
291                         pm8001_ha->memoryMap.region[IB+i].alignment = 128;
292                 } else {
293                         pm8001_ha->memoryMap.region[IB+i].num_elements =
294                                                 PM8001_MPI_QUEUE;
295                         pm8001_ha->memoryMap.region[IB+i].element_size = 64;
296                         pm8001_ha->memoryMap.region[IB+i].total_len =
297                                                 PM8001_MPI_QUEUE * 64;
298                         pm8001_ha->memoryMap.region[IB+i].alignment = 64;
299                 }
300         }
301 
302         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
303                 /* MPI Memory region 4 for producer Index of outbound queues */
304                 pm8001_ha->memoryMap.region[PI+i].num_elements = 1;
305                 pm8001_ha->memoryMap.region[PI+i].element_size = 4;
306                 pm8001_ha->memoryMap.region[PI+i].total_len = 4;
307                 pm8001_ha->memoryMap.region[PI+i].alignment = 4;
308 
309                 if (ent->driver_data != chip_8001) {
310                         /* MPI Memory region 6 Outbound queues */
311                         pm8001_ha->memoryMap.region[OB+i].num_elements =
312                                                 PM8001_MPI_QUEUE;
313                         pm8001_ha->memoryMap.region[OB+i].element_size = 128;
314                         pm8001_ha->memoryMap.region[OB+i].total_len =
315                                                 PM8001_MPI_QUEUE * 128;
316                         pm8001_ha->memoryMap.region[OB+i].alignment = 128;
317                 } else {
318                         /* MPI Memory region 6 Outbound queues */
319                         pm8001_ha->memoryMap.region[OB+i].num_elements =
320                                                 PM8001_MPI_QUEUE;
321                         pm8001_ha->memoryMap.region[OB+i].element_size = 64;
322                         pm8001_ha->memoryMap.region[OB+i].total_len =
323                                                 PM8001_MPI_QUEUE * 64;
324                         pm8001_ha->memoryMap.region[OB+i].alignment = 64;
325                 }
326 
327         }
328         /* Memory region write DMA*/
329         pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
330         pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
331         pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
332         /* Memory region for devices*/
333         pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1;
334         pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES *
335                 sizeof(struct pm8001_device);
336         pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES *
337                 sizeof(struct pm8001_device);
338 
339         /* Memory region for ccb_info*/
340         pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1;
341         pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB *
342                 sizeof(struct pm8001_ccb_info);
343         pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB *
344                 sizeof(struct pm8001_ccb_info);
345 
346         /* Memory region for fw flash */
347         pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
348 
349         pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
350         pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
351         pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
352         pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
353         for (i = 0; i < USI_MAX_MEMCNT; i++) {
354                 if (pm8001_mem_alloc(pm8001_ha->pdev,
355                         &pm8001_ha->memoryMap.region[i].virt_ptr,
356                         &pm8001_ha->memoryMap.region[i].phys_addr,
357                         &pm8001_ha->memoryMap.region[i].phys_addr_hi,
358                         &pm8001_ha->memoryMap.region[i].phys_addr_lo,
359                         pm8001_ha->memoryMap.region[i].total_len,
360                         pm8001_ha->memoryMap.region[i].alignment) != 0) {
361                                 PM8001_FAIL_DBG(pm8001_ha,
362                                         pm8001_printk("Mem%d alloc failed\n",
363                                         i));
364                                 goto err_out;
365                 }
366         }
367 
368         pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr;
369         for (i = 0; i < PM8001_MAX_DEVICES; i++) {
370                 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
371                 pm8001_ha->devices[i].id = i;
372                 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
373                 pm8001_ha->devices[i].running_req = 0;
374         }
375         pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr;
376         for (i = 0; i < PM8001_MAX_CCB; i++) {
377                 pm8001_ha->ccb_info[i].ccb_dma_handle =
378                         pm8001_ha->memoryMap.region[CCB_MEM].phys_addr +
379                         i * sizeof(struct pm8001_ccb_info);
380                 pm8001_ha->ccb_info[i].task = NULL;
381                 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
382                 pm8001_ha->ccb_info[i].device = NULL;
383                 ++pm8001_ha->tags_num;
384         }
385         pm8001_ha->flags = PM8001F_INIT_TIME;
386         /* Initialize tags */
387         pm8001_tag_init(pm8001_ha);
388         return 0;
389 err_out:
390         return 1;
391 }
392 
393 /**
394  * pm8001_ioremap - remap the pci high physical address to kernal virtual
395  * address so that we can access them.
396  * @pm8001_ha:our hba structure.
397  */
398 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
399 {
400         u32 bar;
401         u32 logicalBar = 0;
402         struct pci_dev *pdev;
403 
404         pdev = pm8001_ha->pdev;
405         /* map pci mem (PMC pci base 0-3)*/
406         for (bar = 0; bar < 6; bar++) {
407                 /*
408                 ** logical BARs for SPC:
409                 ** bar 0 and 1 - logical BAR0
410                 ** bar 2 and 3 - logical BAR1
411                 ** bar4 - logical BAR2
412                 ** bar5 - logical BAR3
413                 ** Skip the appropriate assignments:
414                 */
415                 if ((bar == 1) || (bar == 3))
416                         continue;
417                 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
418                         pm8001_ha->io_mem[logicalBar].membase =
419                                 pci_resource_start(pdev, bar);
420                         pm8001_ha->io_mem[logicalBar].membase &=
421                                 (u32)PCI_BASE_ADDRESS_MEM_MASK;
422                         pm8001_ha->io_mem[logicalBar].memsize =
423                                 pci_resource_len(pdev, bar);
424                         pm8001_ha->io_mem[logicalBar].memvirtaddr =
425                                 ioremap(pm8001_ha->io_mem[logicalBar].membase,
426                                 pm8001_ha->io_mem[logicalBar].memsize);
427                         PM8001_INIT_DBG(pm8001_ha,
428                                 pm8001_printk("PCI: bar %d, logicalBar %d ",
429                                 bar, logicalBar));
430                         PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
431                                 "base addr %llx virt_addr=%llx len=%d\n",
432                                 (u64)pm8001_ha->io_mem[logicalBar].membase,
433                                 (u64)(unsigned long)
434                                 pm8001_ha->io_mem[logicalBar].memvirtaddr,
435                                 pm8001_ha->io_mem[logicalBar].memsize));
436                 } else {
437                         pm8001_ha->io_mem[logicalBar].membase   = 0;
438                         pm8001_ha->io_mem[logicalBar].memsize   = 0;
439                         pm8001_ha->io_mem[logicalBar].memvirtaddr = 0;
440                 }
441                 logicalBar++;
442         }
443         return 0;
444 }
445 
446 /**
447  * pm8001_pci_alloc - initialize our ha card structure
448  * @pdev: pci device.
449  * @ent: ent
450  * @shost: scsi host struct which has been initialized before.
451  */
452 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
453                                  const struct pci_device_id *ent,
454                                 struct Scsi_Host *shost)
455 
456 {
457         struct pm8001_hba_info *pm8001_ha;
458         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
459         int j;
460 
461         pm8001_ha = sha->lldd_ha;
462         if (!pm8001_ha)
463                 return NULL;
464 
465         pm8001_ha->pdev = pdev;
466         pm8001_ha->dev = &pdev->dev;
467         pm8001_ha->chip_id = ent->driver_data;
468         pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
469         pm8001_ha->irq = pdev->irq;
470         pm8001_ha->sas = sha;
471         pm8001_ha->shost = shost;
472         pm8001_ha->id = pm8001_id++;
473         pm8001_ha->logging_level = 0x01;
474         sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
475         /* IOMB size is 128 for 8088/89 controllers */
476         if (pm8001_ha->chip_id != chip_8001)
477                 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
478         else
479                 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
480 
481 #ifdef PM8001_USE_TASKLET
482         /* Tasklet for non msi-x interrupt handler */
483         if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
484                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
485                         (unsigned long)&(pm8001_ha->irq_vector[0]));
486         else
487                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
488                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
489                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
490 #endif
491         pm8001_ioremap(pm8001_ha);
492         if (!pm8001_alloc(pm8001_ha, ent))
493                 return pm8001_ha;
494         pm8001_free(pm8001_ha);
495         return NULL;
496 }
497 
498 /**
499  * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
500  * @pdev: pci device.
501  */
502 static int pci_go_44(struct pci_dev *pdev)
503 {
504         int rc;
505 
506         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(44))) {
507                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(44));
508                 if (rc) {
509                         rc = pci_set_consistent_dma_mask(pdev,
510                                 DMA_BIT_MASK(32));
511                         if (rc) {
512                                 dev_printk(KERN_ERR, &pdev->dev,
513                                         "44-bit DMA enable failed\n");
514                                 return rc;
515                         }
516                 }
517         } else {
518                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
519                 if (rc) {
520                         dev_printk(KERN_ERR, &pdev->dev,
521                                 "32-bit DMA enable failed\n");
522                         return rc;
523                 }
524                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
525                 if (rc) {
526                         dev_printk(KERN_ERR, &pdev->dev,
527                                 "32-bit consistent DMA enable failed\n");
528                         return rc;
529                 }
530         }
531         return rc;
532 }
533 
534 /**
535  * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
536  * @shost: scsi host which has been allocated outside.
537  * @chip_info: our ha struct.
538  */
539 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
540                                    const struct pm8001_chip_info *chip_info)
541 {
542         int phy_nr, port_nr;
543         struct asd_sas_phy **arr_phy;
544         struct asd_sas_port **arr_port;
545         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
546 
547         phy_nr = chip_info->n_phy;
548         port_nr = phy_nr;
549         memset(sha, 0x00, sizeof(*sha));
550         arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
551         if (!arr_phy)
552                 goto exit;
553         arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
554         if (!arr_port)
555                 goto exit_free2;
556 
557         sha->sas_phy = arr_phy;
558         sha->sas_port = arr_port;
559         sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
560         if (!sha->lldd_ha)
561                 goto exit_free1;
562 
563         shost->transportt = pm8001_stt;
564         shost->max_id = PM8001_MAX_DEVICES;
565         shost->max_lun = 8;
566         shost->max_channel = 0;
567         shost->unique_id = pm8001_id;
568         shost->max_cmd_len = 16;
569         shost->can_queue = PM8001_CAN_QUEUE;
570         shost->cmd_per_lun = 32;
571         return 0;
572 exit_free1:
573         kfree(arr_port);
574 exit_free2:
575         kfree(arr_phy);
576 exit:
577         return -1;
578 }
579 
580 /**
581  * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
582  * @shost: scsi host which has been allocated outside
583  * @chip_info: our ha struct.
584  */
585 static void  pm8001_post_sas_ha_init(struct Scsi_Host *shost,
586                                      const struct pm8001_chip_info *chip_info)
587 {
588         int i = 0;
589         struct pm8001_hba_info *pm8001_ha;
590         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
591 
592         pm8001_ha = sha->lldd_ha;
593         for (i = 0; i < chip_info->n_phy; i++) {
594                 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
595                 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
596         }
597         sha->sas_ha_name = DRV_NAME;
598         sha->dev = pm8001_ha->dev;
599 
600         sha->lldd_module = THIS_MODULE;
601         sha->sas_addr = &pm8001_ha->sas_addr[0];
602         sha->num_phys = chip_info->n_phy;
603         sha->core.shost = shost;
604 }
605 
606 /**
607  * pm8001_init_sas_add - initialize sas address
608  * @chip_info: our ha struct.
609  *
610  * Currently we just set the fixed SAS address to our HBA,for manufacture,
611  * it should read from the EEPROM
612  */
613 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
614 {
615         u8 i, j;
616 #ifdef PM8001_READ_VPD
617         /* For new SPC controllers WWN is stored in flash vpd
618         *  For SPC/SPCve controllers WWN is stored in EEPROM
619         *  For Older SPC WWN is stored in NVMD
620         */
621         DECLARE_COMPLETION_ONSTACK(completion);
622         struct pm8001_ioctl_payload payload;
623         u16 deviceid;
624         int rc;
625 
626         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
627         pm8001_ha->nvmd_completion = &completion;
628 
629         if (pm8001_ha->chip_id == chip_8001) {
630                 if (deviceid == 0x8081 || deviceid == 0x0042) {
631                         payload.minor_function = 4;
632                         payload.length = 4096;
633                 } else {
634                         payload.minor_function = 0;
635                         payload.length = 128;
636                 }
637         } else {
638                 payload.minor_function = 1;
639                 payload.length = 4096;
640         }
641         payload.offset = 0;
642         payload.func_specific = kzalloc(payload.length, GFP_KERNEL);
643         if (!payload.func_specific) {
644                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("mem alloc fail\n"));
645                 return;
646         }
647         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
648         if (rc) {
649                 kfree(payload.func_specific);
650                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
651                 return;
652         }
653         wait_for_completion(&completion);
654 
655         for (i = 0, j = 0; i <= 7; i++, j++) {
656                 if (pm8001_ha->chip_id == chip_8001) {
657                         if (deviceid == 0x8081)
658                                 pm8001_ha->sas_addr[j] =
659                                         payload.func_specific[0x704 + i];
660                         else if (deviceid == 0x0042)
661                                 pm8001_ha->sas_addr[j] =
662                                         payload.func_specific[0x010 + i];
663                 } else
664                         pm8001_ha->sas_addr[j] =
665                                         payload.func_specific[0x804 + i];
666         }
667 
668         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
669                 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
670                         pm8001_ha->sas_addr, SAS_ADDR_SIZE);
671                 PM8001_INIT_DBG(pm8001_ha,
672                         pm8001_printk("phy %d sas_addr = %016llx\n", i,
673                         pm8001_ha->phy[i].dev_sas_addr));
674         }
675         kfree(payload.func_specific);
676 #else
677         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
678                 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
679                 pm8001_ha->phy[i].dev_sas_addr =
680                         cpu_to_be64((u64)
681                                 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
682         }
683         memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
684                 SAS_ADDR_SIZE);
685 #endif
686 }
687 
688 /*
689  * pm8001_get_phy_settings_info : Read phy setting values.
690  * @pm8001_ha : our hba.
691  */
692 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
693 {
694 
695 #ifdef PM8001_READ_VPD
696         /*OPTION ROM FLASH read for the SPC cards */
697         DECLARE_COMPLETION_ONSTACK(completion);
698         struct pm8001_ioctl_payload payload;
699         int rc;
700 
701         pm8001_ha->nvmd_completion = &completion;
702         /* SAS ADDRESS read from flash / EEPROM */
703         payload.minor_function = 6;
704         payload.offset = 0;
705         payload.length = 4096;
706         payload.func_specific = kzalloc(4096, GFP_KERNEL);
707         if (!payload.func_specific)
708                 return -ENOMEM;
709         /* Read phy setting values from flash */
710         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
711         if (rc) {
712                 kfree(payload.func_specific);
713                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
714                 return -ENOMEM;
715         }
716         wait_for_completion(&completion);
717         pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
718         kfree(payload.func_specific);
719 #endif
720         return 0;
721 }
722 
723 #ifdef PM8001_USE_MSIX
724 /**
725  * pm8001_setup_msix - enable MSI-X interrupt
726  * @chip_info: our ha struct.
727  * @irq_handler: irq_handler
728  */
729 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
730 {
731         u32 i = 0, j = 0;
732         u32 number_of_intr;
733         int flag = 0;
734         u32 max_entry;
735         int rc;
736         static char intr_drvname[PM8001_MAX_MSIX_VEC][sizeof(DRV_NAME)+3];
737 
738         /* SPCv controllers supports 64 msi-x */
739         if (pm8001_ha->chip_id == chip_8001) {
740                 number_of_intr = 1;
741         } else {
742                 number_of_intr = PM8001_MAX_MSIX_VEC;
743                 flag &= ~IRQF_SHARED;
744         }
745 
746         max_entry = sizeof(pm8001_ha->msix_entries) /
747                 sizeof(pm8001_ha->msix_entries[0]);
748         for (i = 0; i < max_entry ; i++)
749                 pm8001_ha->msix_entries[i].entry = i;
750         rc = pci_enable_msix_exact(pm8001_ha->pdev, pm8001_ha->msix_entries,
751                 number_of_intr);
752         pm8001_ha->number_of_intr = number_of_intr;
753         if (rc)
754                 return rc;
755 
756         PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
757                 "pci_enable_msix_exact request ret:%d no of intr %d\n",
758                                 rc, pm8001_ha->number_of_intr));
759 
760         for (i = 0; i < number_of_intr; i++) {
761                 snprintf(intr_drvname[i], sizeof(intr_drvname[0]),
762                                 DRV_NAME"%d", i);
763                 pm8001_ha->irq_vector[i].irq_id = i;
764                 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
765 
766                 rc = request_irq(pm8001_ha->msix_entries[i].vector,
767                         pm8001_interrupt_handler_msix, flag,
768                         intr_drvname[i], &(pm8001_ha->irq_vector[i]));
769                 if (rc) {
770                         for (j = 0; j < i; j++) {
771                                 free_irq(pm8001_ha->msix_entries[j].vector,
772                                         &(pm8001_ha->irq_vector[i]));
773                         }
774                         pci_disable_msix(pm8001_ha->pdev);
775                         break;
776                 }
777         }
778 
779         return rc;
780 }
781 #endif
782 
783 /**
784  * pm8001_request_irq - register interrupt
785  * @chip_info: our ha struct.
786  */
787 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
788 {
789         struct pci_dev *pdev;
790         int rc;
791 
792         pdev = pm8001_ha->pdev;
793 
794 #ifdef PM8001_USE_MSIX
795         if (pdev->msix_cap)
796                 return pm8001_setup_msix(pm8001_ha);
797         else {
798                 PM8001_INIT_DBG(pm8001_ha,
799                         pm8001_printk("MSIX not supported!!!\n"));
800                 goto intx;
801         }
802 #endif
803 
804 intx:
805         /* initialize the INT-X interrupt */
806         rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
807                 DRV_NAME, SHOST_TO_SAS_HA(pm8001_ha->shost));
808         return rc;
809 }
810 
811 /**
812  * pm8001_pci_probe - probe supported device
813  * @pdev: pci device which kernel has been prepared for.
814  * @ent: pci device id
815  *
816  * This function is the main initialization function, when register a new
817  * pci driver it is invoked, all struct an hardware initilization should be done
818  * here, also, register interrupt
819  */
820 static int pm8001_pci_probe(struct pci_dev *pdev,
821                             const struct pci_device_id *ent)
822 {
823         unsigned int rc;
824         u32     pci_reg;
825         u8      i = 0;
826         struct pm8001_hba_info *pm8001_ha;
827         struct Scsi_Host *shost = NULL;
828         const struct pm8001_chip_info *chip;
829 
830         dev_printk(KERN_INFO, &pdev->dev,
831                 "pm80xx: driver version %s\n", DRV_VERSION);
832         rc = pci_enable_device(pdev);
833         if (rc)
834                 goto err_out_enable;
835         pci_set_master(pdev);
836         /*
837          * Enable pci slot busmaster by setting pci command register.
838          * This is required by FW for Cyclone card.
839          */
840 
841         pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
842         pci_reg |= 0x157;
843         pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
844         rc = pci_request_regions(pdev, DRV_NAME);
845         if (rc)
846                 goto err_out_disable;
847         rc = pci_go_44(pdev);
848         if (rc)
849                 goto err_out_regions;
850 
851         shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
852         if (!shost) {
853                 rc = -ENOMEM;
854                 goto err_out_regions;
855         }
856         chip = &pm8001_chips[ent->driver_data];
857         SHOST_TO_SAS_HA(shost) =
858                 kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
859         if (!SHOST_TO_SAS_HA(shost)) {
860                 rc = -ENOMEM;
861                 goto err_out_free_host;
862         }
863 
864         rc = pm8001_prep_sas_ha_init(shost, chip);
865         if (rc) {
866                 rc = -ENOMEM;
867                 goto err_out_free;
868         }
869         pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
870         /* ent->driver variable is used to differentiate between controllers */
871         pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
872         if (!pm8001_ha) {
873                 rc = -ENOMEM;
874                 goto err_out_free;
875         }
876         list_add_tail(&pm8001_ha->list, &hba_list);
877         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
878         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
879         if (rc) {
880                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
881                         "chip_init failed [ret: %d]\n", rc));
882                 goto err_out_ha_free;
883         }
884 
885         rc = scsi_add_host(shost, &pdev->dev);
886         if (rc)
887                 goto err_out_ha_free;
888         rc = pm8001_request_irq(pm8001_ha);
889         if (rc) {
890                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
891                         "pm8001_request_irq failed [ret: %d]\n", rc));
892                 goto err_out_shost;
893         }
894 
895         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
896         if (pm8001_ha->chip_id != chip_8001) {
897                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
898                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
899                 /* setup thermal configuration. */
900                 pm80xx_set_thermal_config(pm8001_ha);
901         }
902 
903         pm8001_init_sas_add(pm8001_ha);
904         /* phy setting support for motherboard controller */
905         if (pdev->subsystem_vendor != PCI_VENDOR_ID_ADAPTEC2 &&
906                 pdev->subsystem_vendor != 0) {
907                 rc = pm8001_get_phy_settings_info(pm8001_ha);
908                 if (rc)
909                         goto err_out_shost;
910         }
911         pm8001_post_sas_ha_init(shost, chip);
912         rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
913         if (rc)
914                 goto err_out_shost;
915         scsi_scan_host(pm8001_ha->shost);
916         return 0;
917 
918 err_out_shost:
919         scsi_remove_host(pm8001_ha->shost);
920 err_out_ha_free:
921         pm8001_free(pm8001_ha);
922 err_out_free:
923         kfree(SHOST_TO_SAS_HA(shost));
924 err_out_free_host:
925         kfree(shost);
926 err_out_regions:
927         pci_release_regions(pdev);
928 err_out_disable:
929         pci_disable_device(pdev);
930 err_out_enable:
931         return rc;
932 }
933 
934 static void pm8001_pci_remove(struct pci_dev *pdev)
935 {
936         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
937         struct pm8001_hba_info *pm8001_ha;
938         int i, j;
939         pm8001_ha = sha->lldd_ha;
940         sas_unregister_ha(sha);
941         sas_remove_host(pm8001_ha->shost);
942         list_del(&pm8001_ha->list);
943         scsi_remove_host(pm8001_ha->shost);
944         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
945         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
946 
947 #ifdef PM8001_USE_MSIX
948         for (i = 0; i < pm8001_ha->number_of_intr; i++)
949                 synchronize_irq(pm8001_ha->msix_entries[i].vector);
950         for (i = 0; i < pm8001_ha->number_of_intr; i++)
951                 free_irq(pm8001_ha->msix_entries[i].vector,
952                                 &(pm8001_ha->irq_vector[i]));
953         pci_disable_msix(pdev);
954 #else
955         free_irq(pm8001_ha->irq, sha);
956 #endif
957 #ifdef PM8001_USE_TASKLET
958         /* For non-msix and msix interrupts */
959         if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
960                 tasklet_kill(&pm8001_ha->tasklet[0]);
961         else
962                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
963                         tasklet_kill(&pm8001_ha->tasklet[j]);
964 #endif
965         pm8001_free(pm8001_ha);
966         kfree(sha->sas_phy);
967         kfree(sha->sas_port);
968         kfree(sha);
969         pci_release_regions(pdev);
970         pci_disable_device(pdev);
971 }
972 
973 /**
974  * pm8001_pci_suspend - power management suspend main entry point
975  * @pdev: PCI device struct
976  * @state: PM state change to (usually PCI_D3)
977  *
978  * Returns 0 success, anything else error.
979  */
980 static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
981 {
982         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
983         struct pm8001_hba_info *pm8001_ha;
984         int  i, j;
985         u32 device_state;
986         pm8001_ha = sha->lldd_ha;
987         sas_suspend_ha(sha);
988         flush_workqueue(pm8001_wq);
989         scsi_block_requests(pm8001_ha->shost);
990         if (!pdev->pm_cap) {
991                 dev_err(&pdev->dev, " PCI PM not supported\n");
992                 return -ENODEV;
993         }
994         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
995         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
996 #ifdef PM8001_USE_MSIX
997         for (i = 0; i < pm8001_ha->number_of_intr; i++)
998                 synchronize_irq(pm8001_ha->msix_entries[i].vector);
999         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1000                 free_irq(pm8001_ha->msix_entries[i].vector,
1001                                 &(pm8001_ha->irq_vector[i]));
1002         pci_disable_msix(pdev);
1003 #else
1004         free_irq(pm8001_ha->irq, sha);
1005 #endif
1006 #ifdef PM8001_USE_TASKLET
1007         /* For non-msix and msix interrupts */
1008         if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
1009                 tasklet_kill(&pm8001_ha->tasklet[0]);
1010         else
1011                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1012                         tasklet_kill(&pm8001_ha->tasklet[j]);
1013 #endif
1014         device_state = pci_choose_state(pdev, state);
1015         pm8001_printk("pdev=0x%p, slot=%s, entering "
1016                       "operating state [D%d]\n", pdev,
1017                       pm8001_ha->name, device_state);
1018         pci_save_state(pdev);
1019         pci_disable_device(pdev);
1020         pci_set_power_state(pdev, device_state);
1021         return 0;
1022 }
1023 
1024 /**
1025  * pm8001_pci_resume - power management resume main entry point
1026  * @pdev: PCI device struct
1027  *
1028  * Returns 0 success, anything else error.
1029  */
1030 static int pm8001_pci_resume(struct pci_dev *pdev)
1031 {
1032         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1033         struct pm8001_hba_info *pm8001_ha;
1034         int rc;
1035         u8 i = 0, j;
1036         u32 device_state;
1037         DECLARE_COMPLETION_ONSTACK(completion);
1038         pm8001_ha = sha->lldd_ha;
1039         device_state = pdev->current_state;
1040 
1041         pm8001_printk("pdev=0x%p, slot=%s, resuming from previous "
1042                 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state);
1043 
1044         pci_set_power_state(pdev, PCI_D0);
1045         pci_enable_wake(pdev, PCI_D0, 0);
1046         pci_restore_state(pdev);
1047         rc = pci_enable_device(pdev);
1048         if (rc) {
1049                 pm8001_printk("slot=%s Enable device failed during resume\n",
1050                               pm8001_ha->name);
1051                 goto err_out_enable;
1052         }
1053 
1054         pci_set_master(pdev);
1055         rc = pci_go_44(pdev);
1056         if (rc)
1057                 goto err_out_disable;
1058         sas_prep_resume_ha(sha);
1059         /* chip soft rst only for spc */
1060         if (pm8001_ha->chip_id == chip_8001) {
1061                 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1062                 PM8001_INIT_DBG(pm8001_ha,
1063                         pm8001_printk("chip soft reset successful\n"));
1064         }
1065         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1066         if (rc)
1067                 goto err_out_disable;
1068 
1069         /* disable all the interrupt bits */
1070         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1071 
1072         rc = pm8001_request_irq(pm8001_ha);
1073         if (rc)
1074                 goto err_out_disable;
1075 #ifdef PM8001_USE_TASKLET
1076         /*  Tasklet for non msi-x interrupt handler */
1077         if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
1078                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1079                         (unsigned long)&(pm8001_ha->irq_vector[0]));
1080         else
1081                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1082                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1083                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
1084 #endif
1085         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1086         if (pm8001_ha->chip_id != chip_8001) {
1087                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1088                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1089         }
1090         pm8001_ha->flags = PM8001F_RUN_TIME;
1091         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1092                 pm8001_ha->phy[i].enable_completion = &completion;
1093                 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1094                 wait_for_completion(&completion);
1095         }
1096         sas_resume_ha(sha);
1097         return 0;
1098 
1099 err_out_disable:
1100         scsi_remove_host(pm8001_ha->shost);
1101         pci_disable_device(pdev);
1102 err_out_enable:
1103         return rc;
1104 }
1105 
1106 /* update of pci device, vendor id and driver data with
1107  * unique value for each of the controller
1108  */
1109 static struct pci_device_id pm8001_pci_table[] = {
1110         { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1111         { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1112         /* Support for SPC/SPCv/SPCve controllers */
1113         { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1114         { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1115         { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1116         { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1117         { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1118         { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1119         { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1120         { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1121         { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1122         { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1123         { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1124         { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1125         { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1126         { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1127         { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1128         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1129                 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1130         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1131                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1132         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1133                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1134         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1135                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1136         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1137                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1138         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1139                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1140         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1141                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1142         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1143                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1144         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1145                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1146         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1147                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1148         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1149                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1150         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1151                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1152         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1153                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1154         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1155                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1156         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1157                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1158         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1159                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1160         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1161                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1162         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1163                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1164         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1165                 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1166         {} /* terminate list */
1167 };
1168 
1169 static struct pci_driver pm8001_pci_driver = {
1170         .name           = DRV_NAME,
1171         .id_table       = pm8001_pci_table,
1172         .probe          = pm8001_pci_probe,
1173         .remove         = pm8001_pci_remove,
1174         .suspend        = pm8001_pci_suspend,
1175         .resume         = pm8001_pci_resume,
1176 };
1177 
1178 /**
1179  *      pm8001_init - initialize scsi transport template
1180  */
1181 static int __init pm8001_init(void)
1182 {
1183         int rc = -ENOMEM;
1184 
1185         pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1186         if (!pm8001_wq)
1187                 goto err;
1188 
1189         pm8001_id = 0;
1190         pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1191         if (!pm8001_stt)
1192                 goto err_wq;
1193         rc = pci_register_driver(&pm8001_pci_driver);
1194         if (rc)
1195                 goto err_tp;
1196         return 0;
1197 
1198 err_tp:
1199         sas_release_transport(pm8001_stt);
1200 err_wq:
1201         destroy_workqueue(pm8001_wq);
1202 err:
1203         return rc;
1204 }
1205 
1206 static void __exit pm8001_exit(void)
1207 {
1208         pci_unregister_driver(&pm8001_pci_driver);
1209         sas_release_transport(pm8001_stt);
1210         destroy_workqueue(pm8001_wq);
1211 }
1212 
1213 module_init(pm8001_init);
1214 module_exit(pm8001_exit);
1215 
1216 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1217 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1218 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1219 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1220 MODULE_DESCRIPTION(
1221                 "PMC-Sierra PM8001/8081/8088/8089/8074/8076/8077 "
1222                 "SAS/SATA controller driver");
1223 MODULE_VERSION(DRV_VERSION);
1224 MODULE_LICENSE("GPL");
1225 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1226 
1227 

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