Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/scsi/pm8001/pm8001_init.c

  1 /*
  2  * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
  3  *
  4  * Copyright (c) 2008-2009 USI Co., Ltd.
  5  * All rights reserved.
  6  *
  7  * Redistribution and use in source and binary forms, with or without
  8  * modification, are permitted provided that the following conditions
  9  * are met:
 10  * 1. Redistributions of source code must retain the above copyright
 11  *    notice, this list of conditions, and the following disclaimer,
 12  *    without modification.
 13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
 14  *    substantially similar to the "NO WARRANTY" disclaimer below
 15  *    ("Disclaimer") and any redistribution must be conditioned upon
 16  *    including a substantially similar Disclaimer requirement for further
 17  *    binary redistribution.
 18  * 3. Neither the names of the above-listed copyright holders nor the names
 19  *    of any contributors may be used to endorse or promote products derived
 20  *    from this software without specific prior written permission.
 21  *
 22  * Alternatively, this software may be distributed under the terms of the
 23  * GNU General Public License ("GPL") version 2 as published by the Free
 24  * Software Foundation.
 25  *
 26  * NO WARRANTY
 27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
 30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 37  * POSSIBILITY OF SUCH DAMAGES.
 38  *
 39  */
 40 
 41 #include <linux/slab.h>
 42 #include "pm8001_sas.h"
 43 #include "pm8001_chips.h"
 44 
 45 static struct scsi_transport_template *pm8001_stt;
 46 
 47 /**
 48  * chip info structure to identify chip key functionality as
 49  * encryption available/not, no of ports, hw specific function ref
 50  */
 51 static const struct pm8001_chip_info pm8001_chips[] = {
 52         [chip_8001] = {0,  8, &pm8001_8001_dispatch,},
 53         [chip_8008] = {0,  8, &pm8001_80xx_dispatch,},
 54         [chip_8009] = {1,  8, &pm8001_80xx_dispatch,},
 55         [chip_8018] = {0,  16, &pm8001_80xx_dispatch,},
 56         [chip_8019] = {1,  16, &pm8001_80xx_dispatch,},
 57         [chip_8074] = {0,  8, &pm8001_80xx_dispatch,},
 58         [chip_8076] = {0,  16, &pm8001_80xx_dispatch,},
 59         [chip_8077] = {0,  16, &pm8001_80xx_dispatch,},
 60 };
 61 static int pm8001_id;
 62 
 63 LIST_HEAD(hba_list);
 64 
 65 struct workqueue_struct *pm8001_wq;
 66 
 67 /**
 68  * The main structure which LLDD must register for scsi core.
 69  */
 70 static struct scsi_host_template pm8001_sht = {
 71         .module                 = THIS_MODULE,
 72         .name                   = DRV_NAME,
 73         .queuecommand           = sas_queuecommand,
 74         .target_alloc           = sas_target_alloc,
 75         .slave_configure        = sas_slave_configure,
 76         .scan_finished          = pm8001_scan_finished,
 77         .scan_start             = pm8001_scan_start,
 78         .change_queue_depth     = sas_change_queue_depth,
 79         .change_queue_type      = sas_change_queue_type,
 80         .bios_param             = sas_bios_param,
 81         .can_queue              = 1,
 82         .cmd_per_lun            = 1,
 83         .this_id                = -1,
 84         .sg_tablesize           = SG_ALL,
 85         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
 86         .use_clustering         = ENABLE_CLUSTERING,
 87         .eh_device_reset_handler = sas_eh_device_reset_handler,
 88         .eh_bus_reset_handler   = sas_eh_bus_reset_handler,
 89         .target_destroy         = sas_target_destroy,
 90         .ioctl                  = sas_ioctl,
 91         .shost_attrs            = pm8001_host_attrs,
 92 };
 93 
 94 /**
 95  * Sas layer call this function to execute specific task.
 96  */
 97 static struct sas_domain_function_template pm8001_transport_ops = {
 98         .lldd_dev_found         = pm8001_dev_found,
 99         .lldd_dev_gone          = pm8001_dev_gone,
100 
101         .lldd_execute_task      = pm8001_queue_command,
102         .lldd_control_phy       = pm8001_phy_control,
103 
104         .lldd_abort_task        = pm8001_abort_task,
105         .lldd_abort_task_set    = pm8001_abort_task_set,
106         .lldd_clear_aca         = pm8001_clear_aca,
107         .lldd_clear_task_set    = pm8001_clear_task_set,
108         .lldd_I_T_nexus_reset   = pm8001_I_T_nexus_reset,
109         .lldd_lu_reset          = pm8001_lu_reset,
110         .lldd_query_task        = pm8001_query_task,
111 };
112 
113 /**
114  *pm8001_phy_init - initiate our adapter phys
115  *@pm8001_ha: our hba structure.
116  *@phy_id: phy id.
117  */
118 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
119 {
120         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
121         struct asd_sas_phy *sas_phy = &phy->sas_phy;
122         phy->phy_state = 0;
123         phy->pm8001_ha = pm8001_ha;
124         sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
125         sas_phy->class = SAS;
126         sas_phy->iproto = SAS_PROTOCOL_ALL;
127         sas_phy->tproto = 0;
128         sas_phy->type = PHY_TYPE_PHYSICAL;
129         sas_phy->role = PHY_ROLE_INITIATOR;
130         sas_phy->oob_mode = OOB_NOT_CONNECTED;
131         sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
132         sas_phy->id = phy_id;
133         sas_phy->sas_addr = &pm8001_ha->sas_addr[0];
134         sas_phy->frame_rcvd = &phy->frame_rcvd[0];
135         sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
136         sas_phy->lldd_phy = phy;
137 }
138 
139 /**
140  *pm8001_free - free hba
141  *@pm8001_ha:   our hba structure.
142  *
143  */
144 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
145 {
146         int i;
147 
148         if (!pm8001_ha)
149                 return;
150 
151         for (i = 0; i < USI_MAX_MEMCNT; i++) {
152                 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
153                         pci_free_consistent(pm8001_ha->pdev,
154                                 (pm8001_ha->memoryMap.region[i].total_len +
155                                 pm8001_ha->memoryMap.region[i].alignment),
156                                 pm8001_ha->memoryMap.region[i].virt_ptr,
157                                 pm8001_ha->memoryMap.region[i].phys_addr);
158                         }
159         }
160         PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
161         if (pm8001_ha->shost)
162                 scsi_host_put(pm8001_ha->shost);
163         flush_workqueue(pm8001_wq);
164         kfree(pm8001_ha->tags);
165         kfree(pm8001_ha);
166 }
167 
168 #ifdef PM8001_USE_TASKLET
169 
170 /**
171  * tasklet for 64 msi-x interrupt handler
172  * @opaque: the passed general host adapter struct
173  * Note: pm8001_tasklet is common for pm8001 & pm80xx
174  */
175 static void pm8001_tasklet(unsigned long opaque)
176 {
177         struct pm8001_hba_info *pm8001_ha;
178         struct isr_param *irq_vector;
179 
180         irq_vector = (struct isr_param *)opaque;
181         pm8001_ha = irq_vector->drv_inst;
182         if (unlikely(!pm8001_ha))
183                 BUG_ON(1);
184         PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
185 }
186 #endif
187 
188 /**
189  * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
190  * It obtains the vector number and calls the equivalent bottom
191  * half or services directly.
192  * @opaque: the passed outbound queue/vector. Host structure is
193  * retrieved from the same.
194  */
195 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
196 {
197         struct isr_param *irq_vector;
198         struct pm8001_hba_info *pm8001_ha;
199         irqreturn_t ret = IRQ_HANDLED;
200         irq_vector = (struct isr_param *)opaque;
201         pm8001_ha = irq_vector->drv_inst;
202 
203         if (unlikely(!pm8001_ha))
204                 return IRQ_NONE;
205         if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
206                 return IRQ_NONE;
207 #ifdef PM8001_USE_TASKLET
208         tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
209 #else
210         ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
211 #endif
212         return ret;
213 }
214 
215 /**
216  * pm8001_interrupt_handler_intx - main INTx interrupt handler.
217  * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure.
218  */
219 
220 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
221 {
222         struct pm8001_hba_info *pm8001_ha;
223         irqreturn_t ret = IRQ_HANDLED;
224         struct sas_ha_struct *sha = dev_id;
225         pm8001_ha = sha->lldd_ha;
226         if (unlikely(!pm8001_ha))
227                 return IRQ_NONE;
228         if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
229                 return IRQ_NONE;
230 
231 #ifdef PM8001_USE_TASKLET
232         tasklet_schedule(&pm8001_ha->tasklet[0]);
233 #else
234         ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
235 #endif
236         return ret;
237 }
238 
239 /**
240  * pm8001_alloc - initiate our hba structure and 6 DMAs area.
241  * @pm8001_ha:our hba structure.
242  *
243  */
244 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
245                         const struct pci_device_id *ent)
246 {
247         int i;
248         spin_lock_init(&pm8001_ha->lock);
249         PM8001_INIT_DBG(pm8001_ha,
250                 pm8001_printk("pm8001_alloc: PHY:%x\n",
251                                 pm8001_ha->chip->n_phy));
252         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
253                 pm8001_phy_init(pm8001_ha, i);
254                 pm8001_ha->port[i].wide_port_phymap = 0;
255                 pm8001_ha->port[i].port_attached = 0;
256                 pm8001_ha->port[i].port_state = 0;
257                 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
258         }
259 
260         pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL);
261         if (!pm8001_ha->tags)
262                 goto err_out;
263         /* MPI Memory region 1 for AAP Event Log for fw */
264         pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
265         pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
266         pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
267         pm8001_ha->memoryMap.region[AAP1].alignment = 32;
268 
269         /* MPI Memory region 2 for IOP Event Log for fw */
270         pm8001_ha->memoryMap.region[IOP].num_elements = 1;
271         pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
272         pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
273         pm8001_ha->memoryMap.region[IOP].alignment = 32;
274 
275         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
276                 /* MPI Memory region 3 for consumer Index of inbound queues */
277                 pm8001_ha->memoryMap.region[CI+i].num_elements = 1;
278                 pm8001_ha->memoryMap.region[CI+i].element_size = 4;
279                 pm8001_ha->memoryMap.region[CI+i].total_len = 4;
280                 pm8001_ha->memoryMap.region[CI+i].alignment = 4;
281 
282                 if ((ent->driver_data) != chip_8001) {
283                         /* MPI Memory region 5 inbound queues */
284                         pm8001_ha->memoryMap.region[IB+i].num_elements =
285                                                 PM8001_MPI_QUEUE;
286                         pm8001_ha->memoryMap.region[IB+i].element_size = 128;
287                         pm8001_ha->memoryMap.region[IB+i].total_len =
288                                                 PM8001_MPI_QUEUE * 128;
289                         pm8001_ha->memoryMap.region[IB+i].alignment = 128;
290                 } else {
291                         pm8001_ha->memoryMap.region[IB+i].num_elements =
292                                                 PM8001_MPI_QUEUE;
293                         pm8001_ha->memoryMap.region[IB+i].element_size = 64;
294                         pm8001_ha->memoryMap.region[IB+i].total_len =
295                                                 PM8001_MPI_QUEUE * 64;
296                         pm8001_ha->memoryMap.region[IB+i].alignment = 64;
297                 }
298         }
299 
300         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
301                 /* MPI Memory region 4 for producer Index of outbound queues */
302                 pm8001_ha->memoryMap.region[PI+i].num_elements = 1;
303                 pm8001_ha->memoryMap.region[PI+i].element_size = 4;
304                 pm8001_ha->memoryMap.region[PI+i].total_len = 4;
305                 pm8001_ha->memoryMap.region[PI+i].alignment = 4;
306 
307                 if (ent->driver_data != chip_8001) {
308                         /* MPI Memory region 6 Outbound queues */
309                         pm8001_ha->memoryMap.region[OB+i].num_elements =
310                                                 PM8001_MPI_QUEUE;
311                         pm8001_ha->memoryMap.region[OB+i].element_size = 128;
312                         pm8001_ha->memoryMap.region[OB+i].total_len =
313                                                 PM8001_MPI_QUEUE * 128;
314                         pm8001_ha->memoryMap.region[OB+i].alignment = 128;
315                 } else {
316                         /* MPI Memory region 6 Outbound queues */
317                         pm8001_ha->memoryMap.region[OB+i].num_elements =
318                                                 PM8001_MPI_QUEUE;
319                         pm8001_ha->memoryMap.region[OB+i].element_size = 64;
320                         pm8001_ha->memoryMap.region[OB+i].total_len =
321                                                 PM8001_MPI_QUEUE * 64;
322                         pm8001_ha->memoryMap.region[OB+i].alignment = 64;
323                 }
324 
325         }
326         /* Memory region write DMA*/
327         pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
328         pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
329         pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
330         /* Memory region for devices*/
331         pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1;
332         pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES *
333                 sizeof(struct pm8001_device);
334         pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES *
335                 sizeof(struct pm8001_device);
336 
337         /* Memory region for ccb_info*/
338         pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1;
339         pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB *
340                 sizeof(struct pm8001_ccb_info);
341         pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB *
342                 sizeof(struct pm8001_ccb_info);
343 
344         /* Memory region for fw flash */
345         pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
346 
347         pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
348         pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
349         pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
350         pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
351         for (i = 0; i < USI_MAX_MEMCNT; i++) {
352                 if (pm8001_mem_alloc(pm8001_ha->pdev,
353                         &pm8001_ha->memoryMap.region[i].virt_ptr,
354                         &pm8001_ha->memoryMap.region[i].phys_addr,
355                         &pm8001_ha->memoryMap.region[i].phys_addr_hi,
356                         &pm8001_ha->memoryMap.region[i].phys_addr_lo,
357                         pm8001_ha->memoryMap.region[i].total_len,
358                         pm8001_ha->memoryMap.region[i].alignment) != 0) {
359                                 PM8001_FAIL_DBG(pm8001_ha,
360                                         pm8001_printk("Mem%d alloc failed\n",
361                                         i));
362                                 goto err_out;
363                 }
364         }
365 
366         pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr;
367         for (i = 0; i < PM8001_MAX_DEVICES; i++) {
368                 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
369                 pm8001_ha->devices[i].id = i;
370                 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
371                 pm8001_ha->devices[i].running_req = 0;
372         }
373         pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr;
374         for (i = 0; i < PM8001_MAX_CCB; i++) {
375                 pm8001_ha->ccb_info[i].ccb_dma_handle =
376                         pm8001_ha->memoryMap.region[CCB_MEM].phys_addr +
377                         i * sizeof(struct pm8001_ccb_info);
378                 pm8001_ha->ccb_info[i].task = NULL;
379                 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
380                 pm8001_ha->ccb_info[i].device = NULL;
381                 ++pm8001_ha->tags_num;
382         }
383         pm8001_ha->flags = PM8001F_INIT_TIME;
384         /* Initialize tags */
385         pm8001_tag_init(pm8001_ha);
386         return 0;
387 err_out:
388         return 1;
389 }
390 
391 /**
392  * pm8001_ioremap - remap the pci high physical address to kernal virtual
393  * address so that we can access them.
394  * @pm8001_ha:our hba structure.
395  */
396 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
397 {
398         u32 bar;
399         u32 logicalBar = 0;
400         struct pci_dev *pdev;
401 
402         pdev = pm8001_ha->pdev;
403         /* map pci mem (PMC pci base 0-3)*/
404         for (bar = 0; bar < 6; bar++) {
405                 /*
406                 ** logical BARs for SPC:
407                 ** bar 0 and 1 - logical BAR0
408                 ** bar 2 and 3 - logical BAR1
409                 ** bar4 - logical BAR2
410                 ** bar5 - logical BAR3
411                 ** Skip the appropriate assignments:
412                 */
413                 if ((bar == 1) || (bar == 3))
414                         continue;
415                 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
416                         pm8001_ha->io_mem[logicalBar].membase =
417                                 pci_resource_start(pdev, bar);
418                         pm8001_ha->io_mem[logicalBar].membase &=
419                                 (u32)PCI_BASE_ADDRESS_MEM_MASK;
420                         pm8001_ha->io_mem[logicalBar].memsize =
421                                 pci_resource_len(pdev, bar);
422                         pm8001_ha->io_mem[logicalBar].memvirtaddr =
423                                 ioremap(pm8001_ha->io_mem[logicalBar].membase,
424                                 pm8001_ha->io_mem[logicalBar].memsize);
425                         PM8001_INIT_DBG(pm8001_ha,
426                                 pm8001_printk("PCI: bar %d, logicalBar %d ",
427                                 bar, logicalBar));
428                         PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
429                                 "base addr %llx virt_addr=%llx len=%d\n",
430                                 (u64)pm8001_ha->io_mem[logicalBar].membase,
431                                 (u64)(unsigned long)
432                                 pm8001_ha->io_mem[logicalBar].memvirtaddr,
433                                 pm8001_ha->io_mem[logicalBar].memsize));
434                 } else {
435                         pm8001_ha->io_mem[logicalBar].membase   = 0;
436                         pm8001_ha->io_mem[logicalBar].memsize   = 0;
437                         pm8001_ha->io_mem[logicalBar].memvirtaddr = 0;
438                 }
439                 logicalBar++;
440         }
441         return 0;
442 }
443 
444 /**
445  * pm8001_pci_alloc - initialize our ha card structure
446  * @pdev: pci device.
447  * @ent: ent
448  * @shost: scsi host struct which has been initialized before.
449  */
450 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
451                                  const struct pci_device_id *ent,
452                                 struct Scsi_Host *shost)
453 
454 {
455         struct pm8001_hba_info *pm8001_ha;
456         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
457         int j;
458 
459         pm8001_ha = sha->lldd_ha;
460         if (!pm8001_ha)
461                 return NULL;
462 
463         pm8001_ha->pdev = pdev;
464         pm8001_ha->dev = &pdev->dev;
465         pm8001_ha->chip_id = ent->driver_data;
466         pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
467         pm8001_ha->irq = pdev->irq;
468         pm8001_ha->sas = sha;
469         pm8001_ha->shost = shost;
470         pm8001_ha->id = pm8001_id++;
471         pm8001_ha->logging_level = 0x01;
472         sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
473         /* IOMB size is 128 for 8088/89 controllers */
474         if (pm8001_ha->chip_id != chip_8001)
475                 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
476         else
477                 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
478 
479 #ifdef PM8001_USE_TASKLET
480         /* Tasklet for non msi-x interrupt handler */
481         if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
482                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
483                         (unsigned long)&(pm8001_ha->irq_vector[0]));
484         else
485                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
486                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
487                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
488 #endif
489         pm8001_ioremap(pm8001_ha);
490         if (!pm8001_alloc(pm8001_ha, ent))
491                 return pm8001_ha;
492         pm8001_free(pm8001_ha);
493         return NULL;
494 }
495 
496 /**
497  * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
498  * @pdev: pci device.
499  */
500 static int pci_go_44(struct pci_dev *pdev)
501 {
502         int rc;
503 
504         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(44))) {
505                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(44));
506                 if (rc) {
507                         rc = pci_set_consistent_dma_mask(pdev,
508                                 DMA_BIT_MASK(32));
509                         if (rc) {
510                                 dev_printk(KERN_ERR, &pdev->dev,
511                                         "44-bit DMA enable failed\n");
512                                 return rc;
513                         }
514                 }
515         } else {
516                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
517                 if (rc) {
518                         dev_printk(KERN_ERR, &pdev->dev,
519                                 "32-bit DMA enable failed\n");
520                         return rc;
521                 }
522                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
523                 if (rc) {
524                         dev_printk(KERN_ERR, &pdev->dev,
525                                 "32-bit consistent DMA enable failed\n");
526                         return rc;
527                 }
528         }
529         return rc;
530 }
531 
532 /**
533  * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
534  * @shost: scsi host which has been allocated outside.
535  * @chip_info: our ha struct.
536  */
537 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
538                                    const struct pm8001_chip_info *chip_info)
539 {
540         int phy_nr, port_nr;
541         struct asd_sas_phy **arr_phy;
542         struct asd_sas_port **arr_port;
543         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
544 
545         phy_nr = chip_info->n_phy;
546         port_nr = phy_nr;
547         memset(sha, 0x00, sizeof(*sha));
548         arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
549         if (!arr_phy)
550                 goto exit;
551         arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
552         if (!arr_port)
553                 goto exit_free2;
554 
555         sha->sas_phy = arr_phy;
556         sha->sas_port = arr_port;
557         sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
558         if (!sha->lldd_ha)
559                 goto exit_free1;
560 
561         shost->transportt = pm8001_stt;
562         shost->max_id = PM8001_MAX_DEVICES;
563         shost->max_lun = 8;
564         shost->max_channel = 0;
565         shost->unique_id = pm8001_id;
566         shost->max_cmd_len = 16;
567         shost->can_queue = PM8001_CAN_QUEUE;
568         shost->cmd_per_lun = 32;
569         return 0;
570 exit_free1:
571         kfree(arr_port);
572 exit_free2:
573         kfree(arr_phy);
574 exit:
575         return -1;
576 }
577 
578 /**
579  * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
580  * @shost: scsi host which has been allocated outside
581  * @chip_info: our ha struct.
582  */
583 static void  pm8001_post_sas_ha_init(struct Scsi_Host *shost,
584                                      const struct pm8001_chip_info *chip_info)
585 {
586         int i = 0;
587         struct pm8001_hba_info *pm8001_ha;
588         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
589 
590         pm8001_ha = sha->lldd_ha;
591         for (i = 0; i < chip_info->n_phy; i++) {
592                 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
593                 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
594         }
595         sha->sas_ha_name = DRV_NAME;
596         sha->dev = pm8001_ha->dev;
597 
598         sha->lldd_module = THIS_MODULE;
599         sha->sas_addr = &pm8001_ha->sas_addr[0];
600         sha->num_phys = chip_info->n_phy;
601         sha->lldd_max_execute_num = 1;
602         sha->lldd_queue_size = PM8001_CAN_QUEUE;
603         sha->core.shost = shost;
604 }
605 
606 /**
607  * pm8001_init_sas_add - initialize sas address
608  * @chip_info: our ha struct.
609  *
610  * Currently we just set the fixed SAS address to our HBA,for manufacture,
611  * it should read from the EEPROM
612  */
613 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
614 {
615         u8 i, j;
616 #ifdef PM8001_READ_VPD
617         /* For new SPC controllers WWN is stored in flash vpd
618         *  For SPC/SPCve controllers WWN is stored in EEPROM
619         *  For Older SPC WWN is stored in NVMD
620         */
621         DECLARE_COMPLETION_ONSTACK(completion);
622         struct pm8001_ioctl_payload payload;
623         u16 deviceid;
624         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
625         pm8001_ha->nvmd_completion = &completion;
626 
627         if (pm8001_ha->chip_id == chip_8001) {
628                 if (deviceid == 0x8081 || deviceid == 0x0042) {
629                         payload.minor_function = 4;
630                         payload.length = 4096;
631                 } else {
632                         payload.minor_function = 0;
633                         payload.length = 128;
634                 }
635         } else {
636                 payload.minor_function = 1;
637                 payload.length = 4096;
638         }
639         payload.offset = 0;
640         payload.func_specific = kzalloc(payload.length, GFP_KERNEL);
641         PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
642         wait_for_completion(&completion);
643 
644         for (i = 0, j = 0; i <= 7; i++, j++) {
645                 if (pm8001_ha->chip_id == chip_8001) {
646                         if (deviceid == 0x8081)
647                                 pm8001_ha->sas_addr[j] =
648                                         payload.func_specific[0x704 + i];
649                         else if (deviceid == 0x0042)
650                                 pm8001_ha->sas_addr[j] =
651                                         payload.func_specific[0x010 + i];
652                 } else
653                         pm8001_ha->sas_addr[j] =
654                                         payload.func_specific[0x804 + i];
655         }
656 
657         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
658                 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
659                         pm8001_ha->sas_addr, SAS_ADDR_SIZE);
660                 PM8001_INIT_DBG(pm8001_ha,
661                         pm8001_printk("phy %d sas_addr = %016llx\n", i,
662                         pm8001_ha->phy[i].dev_sas_addr));
663         }
664 #else
665         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
666                 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
667                 pm8001_ha->phy[i].dev_sas_addr =
668                         cpu_to_be64((u64)
669                                 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
670         }
671         memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
672                 SAS_ADDR_SIZE);
673 #endif
674 }
675 
676 /*
677  * pm8001_get_phy_settings_info : Read phy setting values.
678  * @pm8001_ha : our hba.
679  */
680 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
681 {
682 
683 #ifdef PM8001_READ_VPD
684         /*OPTION ROM FLASH read for the SPC cards */
685         DECLARE_COMPLETION_ONSTACK(completion);
686         struct pm8001_ioctl_payload payload;
687 
688         pm8001_ha->nvmd_completion = &completion;
689         /* SAS ADDRESS read from flash / EEPROM */
690         payload.minor_function = 6;
691         payload.offset = 0;
692         payload.length = 4096;
693         payload.func_specific = kzalloc(4096, GFP_KERNEL);
694         if (!payload.func_specific)
695                 return -ENOMEM;
696         /* Read phy setting values from flash */
697         PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
698         wait_for_completion(&completion);
699         pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
700         kfree(payload.func_specific);
701 #endif
702         return 0;
703 }
704 
705 #ifdef PM8001_USE_MSIX
706 /**
707  * pm8001_setup_msix - enable MSI-X interrupt
708  * @chip_info: our ha struct.
709  * @irq_handler: irq_handler
710  */
711 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
712 {
713         u32 i = 0, j = 0;
714         u32 number_of_intr;
715         int flag = 0;
716         u32 max_entry;
717         int rc;
718         static char intr_drvname[PM8001_MAX_MSIX_VEC][sizeof(DRV_NAME)+3];
719 
720         /* SPCv controllers supports 64 msi-x */
721         if (pm8001_ha->chip_id == chip_8001) {
722                 number_of_intr = 1;
723         } else {
724                 number_of_intr = PM8001_MAX_MSIX_VEC;
725                 flag &= ~IRQF_SHARED;
726         }
727 
728         max_entry = sizeof(pm8001_ha->msix_entries) /
729                 sizeof(pm8001_ha->msix_entries[0]);
730         for (i = 0; i < max_entry ; i++)
731                 pm8001_ha->msix_entries[i].entry = i;
732         rc = pci_enable_msix(pm8001_ha->pdev, pm8001_ha->msix_entries,
733                 number_of_intr);
734         pm8001_ha->number_of_intr = number_of_intr;
735         if (!rc) {
736                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
737                         "pci_enable_msix request ret:%d no of intr %d\n",
738                                         rc, pm8001_ha->number_of_intr));
739 
740 
741                 for (i = 0; i < number_of_intr; i++) {
742                         snprintf(intr_drvname[i], sizeof(intr_drvname[0]),
743                                         DRV_NAME"%d", i);
744                         pm8001_ha->irq_vector[i].irq_id = i;
745                         pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
746 
747                         if (request_irq(pm8001_ha->msix_entries[i].vector,
748                                 pm8001_interrupt_handler_msix, flag,
749                                 intr_drvname[i], &(pm8001_ha->irq_vector[i]))) {
750                                 for (j = 0; j < i; j++)
751                                         free_irq(
752                                         pm8001_ha->msix_entries[j].vector,
753                                         &(pm8001_ha->irq_vector[i]));
754                                 pci_disable_msix(pm8001_ha->pdev);
755                                 break;
756                         }
757                 }
758         }
759         return rc;
760 }
761 #endif
762 
763 /**
764  * pm8001_request_irq - register interrupt
765  * @chip_info: our ha struct.
766  */
767 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
768 {
769         struct pci_dev *pdev;
770         int rc;
771 
772         pdev = pm8001_ha->pdev;
773 
774 #ifdef PM8001_USE_MSIX
775         if (pdev->msix_cap)
776                 return pm8001_setup_msix(pm8001_ha);
777         else {
778                 PM8001_INIT_DBG(pm8001_ha,
779                         pm8001_printk("MSIX not supported!!!\n"));
780                 goto intx;
781         }
782 #endif
783 
784 intx:
785         /* initialize the INT-X interrupt */
786         rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
787                 DRV_NAME, SHOST_TO_SAS_HA(pm8001_ha->shost));
788         return rc;
789 }
790 
791 /**
792  * pm8001_pci_probe - probe supported device
793  * @pdev: pci device which kernel has been prepared for.
794  * @ent: pci device id
795  *
796  * This function is the main initialization function, when register a new
797  * pci driver it is invoked, all struct an hardware initilization should be done
798  * here, also, register interrupt
799  */
800 static int pm8001_pci_probe(struct pci_dev *pdev,
801                             const struct pci_device_id *ent)
802 {
803         unsigned int rc;
804         u32     pci_reg;
805         u8      i = 0;
806         struct pm8001_hba_info *pm8001_ha;
807         struct Scsi_Host *shost = NULL;
808         const struct pm8001_chip_info *chip;
809 
810         dev_printk(KERN_INFO, &pdev->dev,
811                 "pm80xx: driver version %s\n", DRV_VERSION);
812         rc = pci_enable_device(pdev);
813         if (rc)
814                 goto err_out_enable;
815         pci_set_master(pdev);
816         /*
817          * Enable pci slot busmaster by setting pci command register.
818          * This is required by FW for Cyclone card.
819          */
820 
821         pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
822         pci_reg |= 0x157;
823         pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
824         rc = pci_request_regions(pdev, DRV_NAME);
825         if (rc)
826                 goto err_out_disable;
827         rc = pci_go_44(pdev);
828         if (rc)
829                 goto err_out_regions;
830 
831         shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
832         if (!shost) {
833                 rc = -ENOMEM;
834                 goto err_out_regions;
835         }
836         chip = &pm8001_chips[ent->driver_data];
837         SHOST_TO_SAS_HA(shost) =
838                 kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
839         if (!SHOST_TO_SAS_HA(shost)) {
840                 rc = -ENOMEM;
841                 goto err_out_free_host;
842         }
843 
844         rc = pm8001_prep_sas_ha_init(shost, chip);
845         if (rc) {
846                 rc = -ENOMEM;
847                 goto err_out_free;
848         }
849         pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
850         /* ent->driver variable is used to differentiate between controllers */
851         pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
852         if (!pm8001_ha) {
853                 rc = -ENOMEM;
854                 goto err_out_free;
855         }
856         list_add_tail(&pm8001_ha->list, &hba_list);
857         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
858         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
859         if (rc) {
860                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
861                         "chip_init failed [ret: %d]\n", rc));
862                 goto err_out_ha_free;
863         }
864 
865         rc = scsi_add_host(shost, &pdev->dev);
866         if (rc)
867                 goto err_out_ha_free;
868         rc = pm8001_request_irq(pm8001_ha);
869         if (rc) {
870                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
871                         "pm8001_request_irq failed [ret: %d]\n", rc));
872                 goto err_out_shost;
873         }
874 
875         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
876         if (pm8001_ha->chip_id != chip_8001) {
877                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
878                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
879                 /* setup thermal configuration. */
880                 pm80xx_set_thermal_config(pm8001_ha);
881         }
882 
883         pm8001_init_sas_add(pm8001_ha);
884         /* phy setting support for motherboard controller */
885         if (pdev->subsystem_vendor != PCI_VENDOR_ID_ADAPTEC2 &&
886                 pdev->subsystem_vendor != 0) {
887                 rc = pm8001_get_phy_settings_info(pm8001_ha);
888                 if (rc)
889                         goto err_out_shost;
890         }
891         pm8001_post_sas_ha_init(shost, chip);
892         rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
893         if (rc)
894                 goto err_out_shost;
895         scsi_scan_host(pm8001_ha->shost);
896         return 0;
897 
898 err_out_shost:
899         scsi_remove_host(pm8001_ha->shost);
900 err_out_ha_free:
901         pm8001_free(pm8001_ha);
902 err_out_free:
903         kfree(SHOST_TO_SAS_HA(shost));
904 err_out_free_host:
905         kfree(shost);
906 err_out_regions:
907         pci_release_regions(pdev);
908 err_out_disable:
909         pci_disable_device(pdev);
910 err_out_enable:
911         return rc;
912 }
913 
914 static void pm8001_pci_remove(struct pci_dev *pdev)
915 {
916         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
917         struct pm8001_hba_info *pm8001_ha;
918         int i, j;
919         pm8001_ha = sha->lldd_ha;
920         sas_unregister_ha(sha);
921         sas_remove_host(pm8001_ha->shost);
922         list_del(&pm8001_ha->list);
923         scsi_remove_host(pm8001_ha->shost);
924         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
925         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
926 
927 #ifdef PM8001_USE_MSIX
928         for (i = 0; i < pm8001_ha->number_of_intr; i++)
929                 synchronize_irq(pm8001_ha->msix_entries[i].vector);
930         for (i = 0; i < pm8001_ha->number_of_intr; i++)
931                 free_irq(pm8001_ha->msix_entries[i].vector,
932                                 &(pm8001_ha->irq_vector[i]));
933         pci_disable_msix(pdev);
934 #else
935         free_irq(pm8001_ha->irq, sha);
936 #endif
937 #ifdef PM8001_USE_TASKLET
938         /* For non-msix and msix interrupts */
939         if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
940                 tasklet_kill(&pm8001_ha->tasklet[0]);
941         else
942                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
943                         tasklet_kill(&pm8001_ha->tasklet[j]);
944 #endif
945         pm8001_free(pm8001_ha);
946         kfree(sha->sas_phy);
947         kfree(sha->sas_port);
948         kfree(sha);
949         pci_release_regions(pdev);
950         pci_disable_device(pdev);
951 }
952 
953 /**
954  * pm8001_pci_suspend - power management suspend main entry point
955  * @pdev: PCI device struct
956  * @state: PM state change to (usually PCI_D3)
957  *
958  * Returns 0 success, anything else error.
959  */
960 static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
961 {
962         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
963         struct pm8001_hba_info *pm8001_ha;
964         int  i, j;
965         u32 device_state;
966         pm8001_ha = sha->lldd_ha;
967         flush_workqueue(pm8001_wq);
968         scsi_block_requests(pm8001_ha->shost);
969         if (!pdev->pm_cap) {
970                 dev_err(&pdev->dev, " PCI PM not supported\n");
971                 return -ENODEV;
972         }
973         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
974         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
975 #ifdef PM8001_USE_MSIX
976         for (i = 0; i < pm8001_ha->number_of_intr; i++)
977                 synchronize_irq(pm8001_ha->msix_entries[i].vector);
978         for (i = 0; i < pm8001_ha->number_of_intr; i++)
979                 free_irq(pm8001_ha->msix_entries[i].vector,
980                                 &(pm8001_ha->irq_vector[i]));
981         pci_disable_msix(pdev);
982 #else
983         free_irq(pm8001_ha->irq, sha);
984 #endif
985 #ifdef PM8001_USE_TASKLET
986         /* For non-msix and msix interrupts */
987         if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
988                 tasklet_kill(&pm8001_ha->tasklet[0]);
989         else
990                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
991                         tasklet_kill(&pm8001_ha->tasklet[j]);
992 #endif
993         device_state = pci_choose_state(pdev, state);
994         pm8001_printk("pdev=0x%p, slot=%s, entering "
995                       "operating state [D%d]\n", pdev,
996                       pm8001_ha->name, device_state);
997         pci_save_state(pdev);
998         pci_disable_device(pdev);
999         pci_set_power_state(pdev, device_state);
1000         return 0;
1001 }
1002 
1003 /**
1004  * pm8001_pci_resume - power management resume main entry point
1005  * @pdev: PCI device struct
1006  *
1007  * Returns 0 success, anything else error.
1008  */
1009 static int pm8001_pci_resume(struct pci_dev *pdev)
1010 {
1011         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1012         struct pm8001_hba_info *pm8001_ha;
1013         int rc;
1014         u8 i = 0, j;
1015         u32 device_state;
1016         pm8001_ha = sha->lldd_ha;
1017         device_state = pdev->current_state;
1018 
1019         pm8001_printk("pdev=0x%p, slot=%s, resuming from previous "
1020                 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state);
1021 
1022         pci_set_power_state(pdev, PCI_D0);
1023         pci_enable_wake(pdev, PCI_D0, 0);
1024         pci_restore_state(pdev);
1025         rc = pci_enable_device(pdev);
1026         if (rc) {
1027                 pm8001_printk("slot=%s Enable device failed during resume\n",
1028                               pm8001_ha->name);
1029                 goto err_out_enable;
1030         }
1031 
1032         pci_set_master(pdev);
1033         rc = pci_go_44(pdev);
1034         if (rc)
1035                 goto err_out_disable;
1036 
1037         /* chip soft rst only for spc */
1038         if (pm8001_ha->chip_id == chip_8001) {
1039                 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1040                 PM8001_INIT_DBG(pm8001_ha,
1041                         pm8001_printk("chip soft reset successful\n"));
1042         }
1043         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1044         if (rc)
1045                 goto err_out_disable;
1046 
1047         /* disable all the interrupt bits */
1048         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1049 
1050         rc = pm8001_request_irq(pm8001_ha);
1051         if (rc)
1052                 goto err_out_disable;
1053 #ifdef PM8001_USE_TASKLET
1054         /*  Tasklet for non msi-x interrupt handler */
1055         if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
1056                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1057                         (unsigned long)&(pm8001_ha->irq_vector[0]));
1058         else
1059                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1060                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1061                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
1062 #endif
1063         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1064         if (pm8001_ha->chip_id != chip_8001) {
1065                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1066                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1067         }
1068         scsi_unblock_requests(pm8001_ha->shost);
1069         return 0;
1070 
1071 err_out_disable:
1072         scsi_remove_host(pm8001_ha->shost);
1073         pci_disable_device(pdev);
1074 err_out_enable:
1075         return rc;
1076 }
1077 
1078 /* update of pci device, vendor id and driver data with
1079  * unique value for each of the controller
1080  */
1081 static struct pci_device_id pm8001_pci_table[] = {
1082         { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1083         { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1084         /* Support for SPC/SPCv/SPCve controllers */
1085         { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1086         { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1087         { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1088         { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1089         { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1090         { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1091         { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1092         { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1093         { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1094         { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1095         { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1096         { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1097         { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1098         { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1099         { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1100         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1101                 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1102         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1103                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1104         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1105                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1106         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1107                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1108         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1109                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1110         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1111                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1112         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1113                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1114         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1115                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1116         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1117                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1118         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1119                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1120         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1121                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1122         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1123                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1124         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1125                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1126         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1127                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1128         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1129                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1130         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1131                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1132         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1133                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1134         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1135                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1136         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1137                 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1138         {} /* terminate list */
1139 };
1140 
1141 static struct pci_driver pm8001_pci_driver = {
1142         .name           = DRV_NAME,
1143         .id_table       = pm8001_pci_table,
1144         .probe          = pm8001_pci_probe,
1145         .remove         = pm8001_pci_remove,
1146         .suspend        = pm8001_pci_suspend,
1147         .resume         = pm8001_pci_resume,
1148 };
1149 
1150 /**
1151  *      pm8001_init - initialize scsi transport template
1152  */
1153 static int __init pm8001_init(void)
1154 {
1155         int rc = -ENOMEM;
1156 
1157         pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1158         if (!pm8001_wq)
1159                 goto err;
1160 
1161         pm8001_id = 0;
1162         pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1163         if (!pm8001_stt)
1164                 goto err_wq;
1165         rc = pci_register_driver(&pm8001_pci_driver);
1166         if (rc)
1167                 goto err_tp;
1168         return 0;
1169 
1170 err_tp:
1171         sas_release_transport(pm8001_stt);
1172 err_wq:
1173         destroy_workqueue(pm8001_wq);
1174 err:
1175         return rc;
1176 }
1177 
1178 static void __exit pm8001_exit(void)
1179 {
1180         pci_unregister_driver(&pm8001_pci_driver);
1181         sas_release_transport(pm8001_stt);
1182         destroy_workqueue(pm8001_wq);
1183 }
1184 
1185 module_init(pm8001_init);
1186 module_exit(pm8001_exit);
1187 
1188 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1189 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1190 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1191 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1192 MODULE_DESCRIPTION(
1193                 "PMC-Sierra PM8001/8081/8088/8089/8074/8076/8077 "
1194                 "SAS/SATA controller driver");
1195 MODULE_VERSION(DRV_VERSION);
1196 MODULE_LICENSE("GPL");
1197 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1198 
1199 

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