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Linux/drivers/scsi/pm8001/pm8001_init.c

  1 /*
  2  * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
  3  *
  4  * Copyright (c) 2008-2009 USI Co., Ltd.
  5  * All rights reserved.
  6  *
  7  * Redistribution and use in source and binary forms, with or without
  8  * modification, are permitted provided that the following conditions
  9  * are met:
 10  * 1. Redistributions of source code must retain the above copyright
 11  *    notice, this list of conditions, and the following disclaimer,
 12  *    without modification.
 13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
 14  *    substantially similar to the "NO WARRANTY" disclaimer below
 15  *    ("Disclaimer") and any redistribution must be conditioned upon
 16  *    including a substantially similar Disclaimer requirement for further
 17  *    binary redistribution.
 18  * 3. Neither the names of the above-listed copyright holders nor the names
 19  *    of any contributors may be used to endorse or promote products derived
 20  *    from this software without specific prior written permission.
 21  *
 22  * Alternatively, this software may be distributed under the terms of the
 23  * GNU General Public License ("GPL") version 2 as published by the Free
 24  * Software Foundation.
 25  *
 26  * NO WARRANTY
 27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
 30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 37  * POSSIBILITY OF SUCH DAMAGES.
 38  *
 39  */
 40 
 41 #include <linux/slab.h>
 42 #include "pm8001_sas.h"
 43 #include "pm8001_chips.h"
 44 
 45 static struct scsi_transport_template *pm8001_stt;
 46 
 47 /**
 48  * chip info structure to identify chip key functionality as
 49  * encryption available/not, no of ports, hw specific function ref
 50  */
 51 static const struct pm8001_chip_info pm8001_chips[] = {
 52         [chip_8001] = {0,  8, &pm8001_8001_dispatch,},
 53         [chip_8008] = {0,  8, &pm8001_80xx_dispatch,},
 54         [chip_8009] = {1,  8, &pm8001_80xx_dispatch,},
 55         [chip_8018] = {0,  16, &pm8001_80xx_dispatch,},
 56         [chip_8019] = {1,  16, &pm8001_80xx_dispatch,},
 57         [chip_8074] = {0,  8, &pm8001_80xx_dispatch,},
 58         [chip_8076] = {0,  16, &pm8001_80xx_dispatch,},
 59         [chip_8077] = {0,  16, &pm8001_80xx_dispatch,},
 60         [chip_8006] = {0,  16, &pm8001_80xx_dispatch,},
 61         [chip_8070] = {0,  8, &pm8001_80xx_dispatch,},
 62         [chip_8072] = {0,  16, &pm8001_80xx_dispatch,},
 63 };
 64 static int pm8001_id;
 65 
 66 LIST_HEAD(hba_list);
 67 
 68 struct workqueue_struct *pm8001_wq;
 69 
 70 /**
 71  * The main structure which LLDD must register for scsi core.
 72  */
 73 static struct scsi_host_template pm8001_sht = {
 74         .module                 = THIS_MODULE,
 75         .name                   = DRV_NAME,
 76         .queuecommand           = sas_queuecommand,
 77         .target_alloc           = sas_target_alloc,
 78         .slave_configure        = sas_slave_configure,
 79         .scan_finished          = pm8001_scan_finished,
 80         .scan_start             = pm8001_scan_start,
 81         .change_queue_depth     = sas_change_queue_depth,
 82         .bios_param             = sas_bios_param,
 83         .can_queue              = 1,
 84         .this_id                = -1,
 85         .sg_tablesize           = SG_ALL,
 86         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
 87         .use_clustering         = ENABLE_CLUSTERING,
 88         .eh_device_reset_handler = sas_eh_device_reset_handler,
 89         .eh_bus_reset_handler   = sas_eh_bus_reset_handler,
 90         .target_destroy         = sas_target_destroy,
 91         .ioctl                  = sas_ioctl,
 92         .shost_attrs            = pm8001_host_attrs,
 93         .track_queue_depth      = 1,
 94 };
 95 
 96 /**
 97  * Sas layer call this function to execute specific task.
 98  */
 99 static struct sas_domain_function_template pm8001_transport_ops = {
100         .lldd_dev_found         = pm8001_dev_found,
101         .lldd_dev_gone          = pm8001_dev_gone,
102 
103         .lldd_execute_task      = pm8001_queue_command,
104         .lldd_control_phy       = pm8001_phy_control,
105 
106         .lldd_abort_task        = pm8001_abort_task,
107         .lldd_abort_task_set    = pm8001_abort_task_set,
108         .lldd_clear_aca         = pm8001_clear_aca,
109         .lldd_clear_task_set    = pm8001_clear_task_set,
110         .lldd_I_T_nexus_reset   = pm8001_I_T_nexus_reset,
111         .lldd_lu_reset          = pm8001_lu_reset,
112         .lldd_query_task        = pm8001_query_task,
113 };
114 
115 /**
116  *pm8001_phy_init - initiate our adapter phys
117  *@pm8001_ha: our hba structure.
118  *@phy_id: phy id.
119  */
120 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
121 {
122         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
123         struct asd_sas_phy *sas_phy = &phy->sas_phy;
124         phy->phy_state = 0;
125         phy->pm8001_ha = pm8001_ha;
126         sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
127         sas_phy->class = SAS;
128         sas_phy->iproto = SAS_PROTOCOL_ALL;
129         sas_phy->tproto = 0;
130         sas_phy->type = PHY_TYPE_PHYSICAL;
131         sas_phy->role = PHY_ROLE_INITIATOR;
132         sas_phy->oob_mode = OOB_NOT_CONNECTED;
133         sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
134         sas_phy->id = phy_id;
135         sas_phy->sas_addr = &pm8001_ha->sas_addr[0];
136         sas_phy->frame_rcvd = &phy->frame_rcvd[0];
137         sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
138         sas_phy->lldd_phy = phy;
139 }
140 
141 /**
142  *pm8001_free - free hba
143  *@pm8001_ha:   our hba structure.
144  *
145  */
146 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
147 {
148         int i;
149 
150         if (!pm8001_ha)
151                 return;
152 
153         for (i = 0; i < USI_MAX_MEMCNT; i++) {
154                 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
155                         pci_free_consistent(pm8001_ha->pdev,
156                                 (pm8001_ha->memoryMap.region[i].total_len +
157                                 pm8001_ha->memoryMap.region[i].alignment),
158                                 pm8001_ha->memoryMap.region[i].virt_ptr,
159                                 pm8001_ha->memoryMap.region[i].phys_addr);
160                         }
161         }
162         PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
163         if (pm8001_ha->shost)
164                 scsi_host_put(pm8001_ha->shost);
165         flush_workqueue(pm8001_wq);
166         kfree(pm8001_ha->tags);
167         kfree(pm8001_ha);
168 }
169 
170 #ifdef PM8001_USE_TASKLET
171 
172 /**
173  * tasklet for 64 msi-x interrupt handler
174  * @opaque: the passed general host adapter struct
175  * Note: pm8001_tasklet is common for pm8001 & pm80xx
176  */
177 static void pm8001_tasklet(unsigned long opaque)
178 {
179         struct pm8001_hba_info *pm8001_ha;
180         struct isr_param *irq_vector;
181 
182         irq_vector = (struct isr_param *)opaque;
183         pm8001_ha = irq_vector->drv_inst;
184         if (unlikely(!pm8001_ha))
185                 BUG_ON(1);
186         PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
187 }
188 #endif
189 
190 /**
191  * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
192  * It obtains the vector number and calls the equivalent bottom
193  * half or services directly.
194  * @opaque: the passed outbound queue/vector. Host structure is
195  * retrieved from the same.
196  */
197 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
198 {
199         struct isr_param *irq_vector;
200         struct pm8001_hba_info *pm8001_ha;
201         irqreturn_t ret = IRQ_HANDLED;
202         irq_vector = (struct isr_param *)opaque;
203         pm8001_ha = irq_vector->drv_inst;
204 
205         if (unlikely(!pm8001_ha))
206                 return IRQ_NONE;
207         if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
208                 return IRQ_NONE;
209 #ifdef PM8001_USE_TASKLET
210         tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
211 #else
212         ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
213 #endif
214         return ret;
215 }
216 
217 /**
218  * pm8001_interrupt_handler_intx - main INTx interrupt handler.
219  * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure.
220  */
221 
222 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
223 {
224         struct pm8001_hba_info *pm8001_ha;
225         irqreturn_t ret = IRQ_HANDLED;
226         struct sas_ha_struct *sha = dev_id;
227         pm8001_ha = sha->lldd_ha;
228         if (unlikely(!pm8001_ha))
229                 return IRQ_NONE;
230         if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
231                 return IRQ_NONE;
232 
233 #ifdef PM8001_USE_TASKLET
234         tasklet_schedule(&pm8001_ha->tasklet[0]);
235 #else
236         ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
237 #endif
238         return ret;
239 }
240 
241 /**
242  * pm8001_alloc - initiate our hba structure and 6 DMAs area.
243  * @pm8001_ha:our hba structure.
244  *
245  */
246 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
247                         const struct pci_device_id *ent)
248 {
249         int i;
250         spin_lock_init(&pm8001_ha->lock);
251         spin_lock_init(&pm8001_ha->bitmap_lock);
252         PM8001_INIT_DBG(pm8001_ha,
253                 pm8001_printk("pm8001_alloc: PHY:%x\n",
254                                 pm8001_ha->chip->n_phy));
255         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
256                 pm8001_phy_init(pm8001_ha, i);
257                 pm8001_ha->port[i].wide_port_phymap = 0;
258                 pm8001_ha->port[i].port_attached = 0;
259                 pm8001_ha->port[i].port_state = 0;
260                 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
261         }
262 
263         pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL);
264         if (!pm8001_ha->tags)
265                 goto err_out;
266         /* MPI Memory region 1 for AAP Event Log for fw */
267         pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
268         pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
269         pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
270         pm8001_ha->memoryMap.region[AAP1].alignment = 32;
271 
272         /* MPI Memory region 2 for IOP Event Log for fw */
273         pm8001_ha->memoryMap.region[IOP].num_elements = 1;
274         pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
275         pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
276         pm8001_ha->memoryMap.region[IOP].alignment = 32;
277 
278         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
279                 /* MPI Memory region 3 for consumer Index of inbound queues */
280                 pm8001_ha->memoryMap.region[CI+i].num_elements = 1;
281                 pm8001_ha->memoryMap.region[CI+i].element_size = 4;
282                 pm8001_ha->memoryMap.region[CI+i].total_len = 4;
283                 pm8001_ha->memoryMap.region[CI+i].alignment = 4;
284 
285                 if ((ent->driver_data) != chip_8001) {
286                         /* MPI Memory region 5 inbound queues */
287                         pm8001_ha->memoryMap.region[IB+i].num_elements =
288                                                 PM8001_MPI_QUEUE;
289                         pm8001_ha->memoryMap.region[IB+i].element_size = 128;
290                         pm8001_ha->memoryMap.region[IB+i].total_len =
291                                                 PM8001_MPI_QUEUE * 128;
292                         pm8001_ha->memoryMap.region[IB+i].alignment = 128;
293                 } else {
294                         pm8001_ha->memoryMap.region[IB+i].num_elements =
295                                                 PM8001_MPI_QUEUE;
296                         pm8001_ha->memoryMap.region[IB+i].element_size = 64;
297                         pm8001_ha->memoryMap.region[IB+i].total_len =
298                                                 PM8001_MPI_QUEUE * 64;
299                         pm8001_ha->memoryMap.region[IB+i].alignment = 64;
300                 }
301         }
302 
303         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
304                 /* MPI Memory region 4 for producer Index of outbound queues */
305                 pm8001_ha->memoryMap.region[PI+i].num_elements = 1;
306                 pm8001_ha->memoryMap.region[PI+i].element_size = 4;
307                 pm8001_ha->memoryMap.region[PI+i].total_len = 4;
308                 pm8001_ha->memoryMap.region[PI+i].alignment = 4;
309 
310                 if (ent->driver_data != chip_8001) {
311                         /* MPI Memory region 6 Outbound queues */
312                         pm8001_ha->memoryMap.region[OB+i].num_elements =
313                                                 PM8001_MPI_QUEUE;
314                         pm8001_ha->memoryMap.region[OB+i].element_size = 128;
315                         pm8001_ha->memoryMap.region[OB+i].total_len =
316                                                 PM8001_MPI_QUEUE * 128;
317                         pm8001_ha->memoryMap.region[OB+i].alignment = 128;
318                 } else {
319                         /* MPI Memory region 6 Outbound queues */
320                         pm8001_ha->memoryMap.region[OB+i].num_elements =
321                                                 PM8001_MPI_QUEUE;
322                         pm8001_ha->memoryMap.region[OB+i].element_size = 64;
323                         pm8001_ha->memoryMap.region[OB+i].total_len =
324                                                 PM8001_MPI_QUEUE * 64;
325                         pm8001_ha->memoryMap.region[OB+i].alignment = 64;
326                 }
327 
328         }
329         /* Memory region write DMA*/
330         pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
331         pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
332         pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
333         /* Memory region for devices*/
334         pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1;
335         pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES *
336                 sizeof(struct pm8001_device);
337         pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES *
338                 sizeof(struct pm8001_device);
339 
340         /* Memory region for ccb_info*/
341         pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1;
342         pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB *
343                 sizeof(struct pm8001_ccb_info);
344         pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB *
345                 sizeof(struct pm8001_ccb_info);
346 
347         /* Memory region for fw flash */
348         pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
349 
350         pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
351         pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
352         pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
353         pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
354         for (i = 0; i < USI_MAX_MEMCNT; i++) {
355                 if (pm8001_mem_alloc(pm8001_ha->pdev,
356                         &pm8001_ha->memoryMap.region[i].virt_ptr,
357                         &pm8001_ha->memoryMap.region[i].phys_addr,
358                         &pm8001_ha->memoryMap.region[i].phys_addr_hi,
359                         &pm8001_ha->memoryMap.region[i].phys_addr_lo,
360                         pm8001_ha->memoryMap.region[i].total_len,
361                         pm8001_ha->memoryMap.region[i].alignment) != 0) {
362                                 PM8001_FAIL_DBG(pm8001_ha,
363                                         pm8001_printk("Mem%d alloc failed\n",
364                                         i));
365                                 goto err_out;
366                 }
367         }
368 
369         pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr;
370         for (i = 0; i < PM8001_MAX_DEVICES; i++) {
371                 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
372                 pm8001_ha->devices[i].id = i;
373                 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
374                 pm8001_ha->devices[i].running_req = 0;
375         }
376         pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr;
377         for (i = 0; i < PM8001_MAX_CCB; i++) {
378                 pm8001_ha->ccb_info[i].ccb_dma_handle =
379                         pm8001_ha->memoryMap.region[CCB_MEM].phys_addr +
380                         i * sizeof(struct pm8001_ccb_info);
381                 pm8001_ha->ccb_info[i].task = NULL;
382                 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
383                 pm8001_ha->ccb_info[i].device = NULL;
384                 ++pm8001_ha->tags_num;
385         }
386         pm8001_ha->flags = PM8001F_INIT_TIME;
387         /* Initialize tags */
388         pm8001_tag_init(pm8001_ha);
389         return 0;
390 err_out:
391         return 1;
392 }
393 
394 /**
395  * pm8001_ioremap - remap the pci high physical address to kernal virtual
396  * address so that we can access them.
397  * @pm8001_ha:our hba structure.
398  */
399 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
400 {
401         u32 bar;
402         u32 logicalBar = 0;
403         struct pci_dev *pdev;
404 
405         pdev = pm8001_ha->pdev;
406         /* map pci mem (PMC pci base 0-3)*/
407         for (bar = 0; bar < 6; bar++) {
408                 /*
409                 ** logical BARs for SPC:
410                 ** bar 0 and 1 - logical BAR0
411                 ** bar 2 and 3 - logical BAR1
412                 ** bar4 - logical BAR2
413                 ** bar5 - logical BAR3
414                 ** Skip the appropriate assignments:
415                 */
416                 if ((bar == 1) || (bar == 3))
417                         continue;
418                 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
419                         pm8001_ha->io_mem[logicalBar].membase =
420                                 pci_resource_start(pdev, bar);
421                         pm8001_ha->io_mem[logicalBar].membase &=
422                                 (u32)PCI_BASE_ADDRESS_MEM_MASK;
423                         pm8001_ha->io_mem[logicalBar].memsize =
424                                 pci_resource_len(pdev, bar);
425                         pm8001_ha->io_mem[logicalBar].memvirtaddr =
426                                 ioremap(pm8001_ha->io_mem[logicalBar].membase,
427                                 pm8001_ha->io_mem[logicalBar].memsize);
428                         PM8001_INIT_DBG(pm8001_ha,
429                                 pm8001_printk("PCI: bar %d, logicalBar %d ",
430                                 bar, logicalBar));
431                         PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
432                                 "base addr %llx virt_addr=%llx len=%d\n",
433                                 (u64)pm8001_ha->io_mem[logicalBar].membase,
434                                 (u64)(unsigned long)
435                                 pm8001_ha->io_mem[logicalBar].memvirtaddr,
436                                 pm8001_ha->io_mem[logicalBar].memsize));
437                 } else {
438                         pm8001_ha->io_mem[logicalBar].membase   = 0;
439                         pm8001_ha->io_mem[logicalBar].memsize   = 0;
440                         pm8001_ha->io_mem[logicalBar].memvirtaddr = 0;
441                 }
442                 logicalBar++;
443         }
444         return 0;
445 }
446 
447 /**
448  * pm8001_pci_alloc - initialize our ha card structure
449  * @pdev: pci device.
450  * @ent: ent
451  * @shost: scsi host struct which has been initialized before.
452  */
453 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
454                                  const struct pci_device_id *ent,
455                                 struct Scsi_Host *shost)
456 
457 {
458         struct pm8001_hba_info *pm8001_ha;
459         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
460         int j;
461 
462         pm8001_ha = sha->lldd_ha;
463         if (!pm8001_ha)
464                 return NULL;
465 
466         pm8001_ha->pdev = pdev;
467         pm8001_ha->dev = &pdev->dev;
468         pm8001_ha->chip_id = ent->driver_data;
469         pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
470         pm8001_ha->irq = pdev->irq;
471         pm8001_ha->sas = sha;
472         pm8001_ha->shost = shost;
473         pm8001_ha->id = pm8001_id++;
474         pm8001_ha->logging_level = 0x01;
475         sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
476         /* IOMB size is 128 for 8088/89 controllers */
477         if (pm8001_ha->chip_id != chip_8001)
478                 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
479         else
480                 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
481 
482 #ifdef PM8001_USE_TASKLET
483         /* Tasklet for non msi-x interrupt handler */
484         if ((!pdev->msix_cap || !pci_msi_enabled())
485             || (pm8001_ha->chip_id == chip_8001))
486                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
487                         (unsigned long)&(pm8001_ha->irq_vector[0]));
488         else
489                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
490                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
491                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
492 #endif
493         pm8001_ioremap(pm8001_ha);
494         if (!pm8001_alloc(pm8001_ha, ent))
495                 return pm8001_ha;
496         pm8001_free(pm8001_ha);
497         return NULL;
498 }
499 
500 /**
501  * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
502  * @pdev: pci device.
503  */
504 static int pci_go_44(struct pci_dev *pdev)
505 {
506         int rc;
507 
508         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(44))) {
509                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(44));
510                 if (rc) {
511                         rc = pci_set_consistent_dma_mask(pdev,
512                                 DMA_BIT_MASK(32));
513                         if (rc) {
514                                 dev_printk(KERN_ERR, &pdev->dev,
515                                         "44-bit DMA enable failed\n");
516                                 return rc;
517                         }
518                 }
519         } else {
520                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
521                 if (rc) {
522                         dev_printk(KERN_ERR, &pdev->dev,
523                                 "32-bit DMA enable failed\n");
524                         return rc;
525                 }
526                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
527                 if (rc) {
528                         dev_printk(KERN_ERR, &pdev->dev,
529                                 "32-bit consistent DMA enable failed\n");
530                         return rc;
531                 }
532         }
533         return rc;
534 }
535 
536 /**
537  * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
538  * @shost: scsi host which has been allocated outside.
539  * @chip_info: our ha struct.
540  */
541 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
542                                    const struct pm8001_chip_info *chip_info)
543 {
544         int phy_nr, port_nr;
545         struct asd_sas_phy **arr_phy;
546         struct asd_sas_port **arr_port;
547         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
548 
549         phy_nr = chip_info->n_phy;
550         port_nr = phy_nr;
551         memset(sha, 0x00, sizeof(*sha));
552         arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
553         if (!arr_phy)
554                 goto exit;
555         arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
556         if (!arr_port)
557                 goto exit_free2;
558 
559         sha->sas_phy = arr_phy;
560         sha->sas_port = arr_port;
561         sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
562         if (!sha->lldd_ha)
563                 goto exit_free1;
564 
565         shost->transportt = pm8001_stt;
566         shost->max_id = PM8001_MAX_DEVICES;
567         shost->max_lun = 8;
568         shost->max_channel = 0;
569         shost->unique_id = pm8001_id;
570         shost->max_cmd_len = 16;
571         shost->can_queue = PM8001_CAN_QUEUE;
572         shost->cmd_per_lun = 32;
573         return 0;
574 exit_free1:
575         kfree(arr_port);
576 exit_free2:
577         kfree(arr_phy);
578 exit:
579         return -1;
580 }
581 
582 /**
583  * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
584  * @shost: scsi host which has been allocated outside
585  * @chip_info: our ha struct.
586  */
587 static void  pm8001_post_sas_ha_init(struct Scsi_Host *shost,
588                                      const struct pm8001_chip_info *chip_info)
589 {
590         int i = 0;
591         struct pm8001_hba_info *pm8001_ha;
592         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
593 
594         pm8001_ha = sha->lldd_ha;
595         for (i = 0; i < chip_info->n_phy; i++) {
596                 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
597                 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
598         }
599         sha->sas_ha_name = DRV_NAME;
600         sha->dev = pm8001_ha->dev;
601 
602         sha->lldd_module = THIS_MODULE;
603         sha->sas_addr = &pm8001_ha->sas_addr[0];
604         sha->num_phys = chip_info->n_phy;
605         sha->core.shost = shost;
606 }
607 
608 /**
609  * pm8001_init_sas_add - initialize sas address
610  * @chip_info: our ha struct.
611  *
612  * Currently we just set the fixed SAS address to our HBA,for manufacture,
613  * it should read from the EEPROM
614  */
615 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
616 {
617         u8 i, j;
618 #ifdef PM8001_READ_VPD
619         /* For new SPC controllers WWN is stored in flash vpd
620         *  For SPC/SPCve controllers WWN is stored in EEPROM
621         *  For Older SPC WWN is stored in NVMD
622         */
623         DECLARE_COMPLETION_ONSTACK(completion);
624         struct pm8001_ioctl_payload payload;
625         u16 deviceid;
626         int rc;
627 
628         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
629         pm8001_ha->nvmd_completion = &completion;
630 
631         if (pm8001_ha->chip_id == chip_8001) {
632                 if (deviceid == 0x8081 || deviceid == 0x0042) {
633                         payload.minor_function = 4;
634                         payload.length = 4096;
635                 } else {
636                         payload.minor_function = 0;
637                         payload.length = 128;
638                 }
639         } else if ((pm8001_ha->chip_id == chip_8070 ||
640                         pm8001_ha->chip_id == chip_8072) &&
641                         pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
642                 payload.minor_function = 4;
643                 payload.length = 4096;
644         } else {
645                 payload.minor_function = 1;
646                 payload.length = 4096;
647         }
648         payload.offset = 0;
649         payload.func_specific = kzalloc(payload.length, GFP_KERNEL);
650         if (!payload.func_specific) {
651                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("mem alloc fail\n"));
652                 return;
653         }
654         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
655         if (rc) {
656                 kfree(payload.func_specific);
657                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
658                 return;
659         }
660         wait_for_completion(&completion);
661 
662         for (i = 0, j = 0; i <= 7; i++, j++) {
663                 if (pm8001_ha->chip_id == chip_8001) {
664                         if (deviceid == 0x8081)
665                                 pm8001_ha->sas_addr[j] =
666                                         payload.func_specific[0x704 + i];
667                         else if (deviceid == 0x0042)
668                                 pm8001_ha->sas_addr[j] =
669                                         payload.func_specific[0x010 + i];
670                 } else if ((pm8001_ha->chip_id == chip_8070 ||
671                                 pm8001_ha->chip_id == chip_8072) &&
672                                 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
673                         pm8001_ha->sas_addr[j] =
674                                         payload.func_specific[0x010 + i];
675                 } else
676                         pm8001_ha->sas_addr[j] =
677                                         payload.func_specific[0x804 + i];
678         }
679 
680         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
681                 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
682                         pm8001_ha->sas_addr, SAS_ADDR_SIZE);
683                 PM8001_INIT_DBG(pm8001_ha,
684                         pm8001_printk("phy %d sas_addr = %016llx\n", i,
685                         pm8001_ha->phy[i].dev_sas_addr));
686         }
687         kfree(payload.func_specific);
688 #else
689         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
690                 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
691                 pm8001_ha->phy[i].dev_sas_addr =
692                         cpu_to_be64((u64)
693                                 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
694         }
695         memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
696                 SAS_ADDR_SIZE);
697 #endif
698 }
699 
700 /*
701  * pm8001_get_phy_settings_info : Read phy setting values.
702  * @pm8001_ha : our hba.
703  */
704 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
705 {
706 
707 #ifdef PM8001_READ_VPD
708         /*OPTION ROM FLASH read for the SPC cards */
709         DECLARE_COMPLETION_ONSTACK(completion);
710         struct pm8001_ioctl_payload payload;
711         int rc;
712 
713         pm8001_ha->nvmd_completion = &completion;
714         /* SAS ADDRESS read from flash / EEPROM */
715         payload.minor_function = 6;
716         payload.offset = 0;
717         payload.length = 4096;
718         payload.func_specific = kzalloc(4096, GFP_KERNEL);
719         if (!payload.func_specific)
720                 return -ENOMEM;
721         /* Read phy setting values from flash */
722         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
723         if (rc) {
724                 kfree(payload.func_specific);
725                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
726                 return -ENOMEM;
727         }
728         wait_for_completion(&completion);
729         pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
730         kfree(payload.func_specific);
731 #endif
732         return 0;
733 }
734 
735 struct pm8001_mpi3_phy_pg_trx_config {
736         u32 LaneLosCfg;
737         u32 LanePgaCfg1;
738         u32 LanePisoCfg1;
739         u32 LanePisoCfg2;
740         u32 LanePisoCfg3;
741         u32 LanePisoCfg4;
742         u32 LanePisoCfg5;
743         u32 LanePisoCfg6;
744         u32 LaneBctCtrl;
745 };
746 
747 /**
748  * pm8001_get_internal_phy_settings : Retrieves the internal PHY settings
749  * @pm8001_ha : our adapter
750  * @phycfg : PHY config page to populate
751  */
752 static
753 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
754                 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
755 {
756         phycfg->LaneLosCfg   = 0x00000132;
757         phycfg->LanePgaCfg1  = 0x00203949;
758         phycfg->LanePisoCfg1 = 0x000000FF;
759         phycfg->LanePisoCfg2 = 0xFF000001;
760         phycfg->LanePisoCfg3 = 0xE7011300;
761         phycfg->LanePisoCfg4 = 0x631C40C0;
762         phycfg->LanePisoCfg5 = 0xF8102036;
763         phycfg->LanePisoCfg6 = 0xF74A1000;
764         phycfg->LaneBctCtrl  = 0x00FB33F8;
765 }
766 
767 /**
768  * pm8001_get_external_phy_settings : Retrieves the external PHY settings
769  * @pm8001_ha : our adapter
770  * @phycfg : PHY config page to populate
771  */
772 static
773 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
774                 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
775 {
776         phycfg->LaneLosCfg   = 0x00000132;
777         phycfg->LanePgaCfg1  = 0x00203949;
778         phycfg->LanePisoCfg1 = 0x000000FF;
779         phycfg->LanePisoCfg2 = 0xFF000001;
780         phycfg->LanePisoCfg3 = 0xE7011300;
781         phycfg->LanePisoCfg4 = 0x63349140;
782         phycfg->LanePisoCfg5 = 0xF8102036;
783         phycfg->LanePisoCfg6 = 0xF80D9300;
784         phycfg->LaneBctCtrl  = 0x00FB33F8;
785 }
786 
787 /**
788  * pm8001_get_phy_mask : Retrieves the mask that denotes if a PHY is int/ext
789  * @pm8001_ha : our adapter
790  * @phymask : The PHY mask
791  */
792 static
793 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
794 {
795         switch (pm8001_ha->pdev->subsystem_device) {
796         case 0x0070: /* H1280 - 8 external 0 internal */
797         case 0x0072: /* H12F0 - 16 external 0 internal */
798                 *phymask = 0x0000;
799                 break;
800 
801         case 0x0071: /* H1208 - 0 external 8 internal */
802         case 0x0073: /* H120F - 0 external 16 internal */
803                 *phymask = 0xFFFF;
804                 break;
805 
806         case 0x0080: /* H1244 - 4 external 4 internal */
807                 *phymask = 0x00F0;
808                 break;
809 
810         case 0x0081: /* H1248 - 4 external 8 internal */
811                 *phymask = 0x0FF0;
812                 break;
813 
814         case 0x0082: /* H1288 - 8 external 8 internal */
815                 *phymask = 0xFF00;
816                 break;
817 
818         default:
819                 PM8001_INIT_DBG(pm8001_ha,
820                         pm8001_printk("Unknown subsystem device=0x%.04x",
821                                 pm8001_ha->pdev->subsystem_device));
822         }
823 }
824 
825 /**
826  * pm8001_set_phy_settings_ven_117c_12Gb : Configure ATTO 12Gb PHY settings
827  * @pm8001_ha : our adapter
828  */
829 static
830 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
831 {
832         struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
833         struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
834         int phymask = 0;
835         int i = 0;
836 
837         memset(&phycfg_int, 0, sizeof(phycfg_int));
838         memset(&phycfg_ext, 0, sizeof(phycfg_ext));
839 
840         pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
841         pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
842         pm8001_get_phy_mask(pm8001_ha, &phymask);
843 
844         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
845                 if (phymask & (1 << i)) {/* Internal PHY */
846                         pm8001_set_phy_profile_single(pm8001_ha, i,
847                                         sizeof(phycfg_int) / sizeof(u32),
848                                         (u32 *)&phycfg_int);
849 
850                 } else { /* External PHY */
851                         pm8001_set_phy_profile_single(pm8001_ha, i,
852                                         sizeof(phycfg_ext) / sizeof(u32),
853                                         (u32 *)&phycfg_ext);
854                 }
855         }
856 
857         return 0;
858 }
859 
860 /**
861  * pm8001_configure_phy_settings : Configures PHY settings based on vendor ID.
862  * @pm8001_ha : our hba.
863  */
864 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
865 {
866         switch (pm8001_ha->pdev->subsystem_vendor) {
867         case PCI_VENDOR_ID_ATTO:
868                 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */
869                         return 0;
870                 else
871                         return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
872 
873         case PCI_VENDOR_ID_ADAPTEC2:
874         case 0:
875                 return 0;
876 
877         default:
878                 return pm8001_get_phy_settings_info(pm8001_ha);
879         }
880 }
881 
882 #ifdef PM8001_USE_MSIX
883 /**
884  * pm8001_setup_msix - enable MSI-X interrupt
885  * @chip_info: our ha struct.
886  * @irq_handler: irq_handler
887  */
888 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
889 {
890         u32 i = 0, j = 0;
891         u32 number_of_intr;
892         int flag = 0;
893         u32 max_entry;
894         int rc;
895         static char intr_drvname[PM8001_MAX_MSIX_VEC][sizeof(DRV_NAME)+3];
896 
897         /* SPCv controllers supports 64 msi-x */
898         if (pm8001_ha->chip_id == chip_8001) {
899                 number_of_intr = 1;
900         } else {
901                 number_of_intr = PM8001_MAX_MSIX_VEC;
902                 flag &= ~IRQF_SHARED;
903         }
904 
905         max_entry = sizeof(pm8001_ha->msix_entries) /
906                 sizeof(pm8001_ha->msix_entries[0]);
907         for (i = 0; i < max_entry ; i++)
908                 pm8001_ha->msix_entries[i].entry = i;
909         rc = pci_enable_msix_exact(pm8001_ha->pdev, pm8001_ha->msix_entries,
910                 number_of_intr);
911         pm8001_ha->number_of_intr = number_of_intr;
912         if (rc)
913                 return rc;
914 
915         PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
916                 "pci_enable_msix_exact request ret:%d no of intr %d\n",
917                                 rc, pm8001_ha->number_of_intr));
918 
919         for (i = 0; i < number_of_intr; i++) {
920                 snprintf(intr_drvname[i], sizeof(intr_drvname[0]),
921                                 DRV_NAME"%d", i);
922                 pm8001_ha->irq_vector[i].irq_id = i;
923                 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
924 
925                 rc = request_irq(pm8001_ha->msix_entries[i].vector,
926                         pm8001_interrupt_handler_msix, flag,
927                         intr_drvname[i], &(pm8001_ha->irq_vector[i]));
928                 if (rc) {
929                         for (j = 0; j < i; j++) {
930                                 free_irq(pm8001_ha->msix_entries[j].vector,
931                                         &(pm8001_ha->irq_vector[i]));
932                         }
933                         pci_disable_msix(pm8001_ha->pdev);
934                         break;
935                 }
936         }
937 
938         return rc;
939 }
940 #endif
941 
942 /**
943  * pm8001_request_irq - register interrupt
944  * @chip_info: our ha struct.
945  */
946 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
947 {
948         struct pci_dev *pdev;
949         int rc;
950 
951         pdev = pm8001_ha->pdev;
952 
953 #ifdef PM8001_USE_MSIX
954         if (pdev->msix_cap && pci_msi_enabled())
955                 return pm8001_setup_msix(pm8001_ha);
956         else {
957                 PM8001_INIT_DBG(pm8001_ha,
958                         pm8001_printk("MSIX not supported!!!\n"));
959                 goto intx;
960         }
961 #endif
962 
963 intx:
964         /* initialize the INT-X interrupt */
965         pm8001_ha->irq_vector[0].irq_id = 0;
966         pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
967         rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
968                 DRV_NAME, SHOST_TO_SAS_HA(pm8001_ha->shost));
969         return rc;
970 }
971 
972 /**
973  * pm8001_pci_probe - probe supported device
974  * @pdev: pci device which kernel has been prepared for.
975  * @ent: pci device id
976  *
977  * This function is the main initialization function, when register a new
978  * pci driver it is invoked, all struct an hardware initilization should be done
979  * here, also, register interrupt
980  */
981 static int pm8001_pci_probe(struct pci_dev *pdev,
982                             const struct pci_device_id *ent)
983 {
984         unsigned int rc;
985         u32     pci_reg;
986         u8      i = 0;
987         struct pm8001_hba_info *pm8001_ha;
988         struct Scsi_Host *shost = NULL;
989         const struct pm8001_chip_info *chip;
990 
991         dev_printk(KERN_INFO, &pdev->dev,
992                 "pm80xx: driver version %s\n", DRV_VERSION);
993         rc = pci_enable_device(pdev);
994         if (rc)
995                 goto err_out_enable;
996         pci_set_master(pdev);
997         /*
998          * Enable pci slot busmaster by setting pci command register.
999          * This is required by FW for Cyclone card.
1000          */
1001 
1002         pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1003         pci_reg |= 0x157;
1004         pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1005         rc = pci_request_regions(pdev, DRV_NAME);
1006         if (rc)
1007                 goto err_out_disable;
1008         rc = pci_go_44(pdev);
1009         if (rc)
1010                 goto err_out_regions;
1011 
1012         shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1013         if (!shost) {
1014                 rc = -ENOMEM;
1015                 goto err_out_regions;
1016         }
1017         chip = &pm8001_chips[ent->driver_data];
1018         SHOST_TO_SAS_HA(shost) =
1019                 kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1020         if (!SHOST_TO_SAS_HA(shost)) {
1021                 rc = -ENOMEM;
1022                 goto err_out_free_host;
1023         }
1024 
1025         rc = pm8001_prep_sas_ha_init(shost, chip);
1026         if (rc) {
1027                 rc = -ENOMEM;
1028                 goto err_out_free;
1029         }
1030         pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1031         /* ent->driver variable is used to differentiate between controllers */
1032         pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1033         if (!pm8001_ha) {
1034                 rc = -ENOMEM;
1035                 goto err_out_free;
1036         }
1037         list_add_tail(&pm8001_ha->list, &hba_list);
1038         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1039         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1040         if (rc) {
1041                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1042                         "chip_init failed [ret: %d]\n", rc));
1043                 goto err_out_ha_free;
1044         }
1045 
1046         rc = scsi_add_host(shost, &pdev->dev);
1047         if (rc)
1048                 goto err_out_ha_free;
1049         rc = pm8001_request_irq(pm8001_ha);
1050         if (rc) {
1051                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1052                         "pm8001_request_irq failed [ret: %d]\n", rc));
1053                 goto err_out_shost;
1054         }
1055 
1056         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1057         if (pm8001_ha->chip_id != chip_8001) {
1058                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1059                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1060                 /* setup thermal configuration. */
1061                 pm80xx_set_thermal_config(pm8001_ha);
1062         }
1063 
1064         pm8001_init_sas_add(pm8001_ha);
1065         /* phy setting support for motherboard controller */
1066         if (pm8001_configure_phy_settings(pm8001_ha))
1067                 goto err_out_shost;
1068 
1069         pm8001_post_sas_ha_init(shost, chip);
1070         rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1071         if (rc)
1072                 goto err_out_shost;
1073         scsi_scan_host(pm8001_ha->shost);
1074         return 0;
1075 
1076 err_out_shost:
1077         scsi_remove_host(pm8001_ha->shost);
1078 err_out_ha_free:
1079         pm8001_free(pm8001_ha);
1080 err_out_free:
1081         kfree(SHOST_TO_SAS_HA(shost));
1082 err_out_free_host:
1083         kfree(shost);
1084 err_out_regions:
1085         pci_release_regions(pdev);
1086 err_out_disable:
1087         pci_disable_device(pdev);
1088 err_out_enable:
1089         return rc;
1090 }
1091 
1092 static void pm8001_pci_remove(struct pci_dev *pdev)
1093 {
1094         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1095         struct pm8001_hba_info *pm8001_ha;
1096         int i, j;
1097         pm8001_ha = sha->lldd_ha;
1098         scsi_remove_host(pm8001_ha->shost);
1099         sas_unregister_ha(sha);
1100         sas_remove_host(pm8001_ha->shost);
1101         list_del(&pm8001_ha->list);
1102         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1103         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1104 
1105 #ifdef PM8001_USE_MSIX
1106         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1107                 synchronize_irq(pm8001_ha->msix_entries[i].vector);
1108         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1109                 free_irq(pm8001_ha->msix_entries[i].vector,
1110                                 &(pm8001_ha->irq_vector[i]));
1111         pci_disable_msix(pdev);
1112 #else
1113         free_irq(pm8001_ha->irq, sha);
1114 #endif
1115 #ifdef PM8001_USE_TASKLET
1116         /* For non-msix and msix interrupts */
1117         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1118             (pm8001_ha->chip_id == chip_8001))
1119                 tasklet_kill(&pm8001_ha->tasklet[0]);
1120         else
1121                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1122                         tasklet_kill(&pm8001_ha->tasklet[j]);
1123 #endif
1124         pm8001_free(pm8001_ha);
1125         kfree(sha->sas_phy);
1126         kfree(sha->sas_port);
1127         kfree(sha);
1128         pci_release_regions(pdev);
1129         pci_disable_device(pdev);
1130 }
1131 
1132 /**
1133  * pm8001_pci_suspend - power management suspend main entry point
1134  * @pdev: PCI device struct
1135  * @state: PM state change to (usually PCI_D3)
1136  *
1137  * Returns 0 success, anything else error.
1138  */
1139 static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1140 {
1141         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1142         struct pm8001_hba_info *pm8001_ha;
1143         int  i, j;
1144         u32 device_state;
1145         pm8001_ha = sha->lldd_ha;
1146         sas_suspend_ha(sha);
1147         flush_workqueue(pm8001_wq);
1148         scsi_block_requests(pm8001_ha->shost);
1149         if (!pdev->pm_cap) {
1150                 dev_err(&pdev->dev, " PCI PM not supported\n");
1151                 return -ENODEV;
1152         }
1153         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1154         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1155 #ifdef PM8001_USE_MSIX
1156         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1157                 synchronize_irq(pm8001_ha->msix_entries[i].vector);
1158         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1159                 free_irq(pm8001_ha->msix_entries[i].vector,
1160                                 &(pm8001_ha->irq_vector[i]));
1161         pci_disable_msix(pdev);
1162 #else
1163         free_irq(pm8001_ha->irq, sha);
1164 #endif
1165 #ifdef PM8001_USE_TASKLET
1166         /* For non-msix and msix interrupts */
1167         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1168             (pm8001_ha->chip_id == chip_8001))
1169                 tasklet_kill(&pm8001_ha->tasklet[0]);
1170         else
1171                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1172                         tasklet_kill(&pm8001_ha->tasklet[j]);
1173 #endif
1174         device_state = pci_choose_state(pdev, state);
1175         pm8001_printk("pdev=0x%p, slot=%s, entering "
1176                       "operating state [D%d]\n", pdev,
1177                       pm8001_ha->name, device_state);
1178         pci_save_state(pdev);
1179         pci_disable_device(pdev);
1180         pci_set_power_state(pdev, device_state);
1181         return 0;
1182 }
1183 
1184 /**
1185  * pm8001_pci_resume - power management resume main entry point
1186  * @pdev: PCI device struct
1187  *
1188  * Returns 0 success, anything else error.
1189  */
1190 static int pm8001_pci_resume(struct pci_dev *pdev)
1191 {
1192         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1193         struct pm8001_hba_info *pm8001_ha;
1194         int rc;
1195         u8 i = 0, j;
1196         u32 device_state;
1197         DECLARE_COMPLETION_ONSTACK(completion);
1198         pm8001_ha = sha->lldd_ha;
1199         device_state = pdev->current_state;
1200 
1201         pm8001_printk("pdev=0x%p, slot=%s, resuming from previous "
1202                 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state);
1203 
1204         pci_set_power_state(pdev, PCI_D0);
1205         pci_enable_wake(pdev, PCI_D0, 0);
1206         pci_restore_state(pdev);
1207         rc = pci_enable_device(pdev);
1208         if (rc) {
1209                 pm8001_printk("slot=%s Enable device failed during resume\n",
1210                               pm8001_ha->name);
1211                 goto err_out_enable;
1212         }
1213 
1214         pci_set_master(pdev);
1215         rc = pci_go_44(pdev);
1216         if (rc)
1217                 goto err_out_disable;
1218         sas_prep_resume_ha(sha);
1219         /* chip soft rst only for spc */
1220         if (pm8001_ha->chip_id == chip_8001) {
1221                 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1222                 PM8001_INIT_DBG(pm8001_ha,
1223                         pm8001_printk("chip soft reset successful\n"));
1224         }
1225         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1226         if (rc)
1227                 goto err_out_disable;
1228 
1229         /* disable all the interrupt bits */
1230         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1231 
1232         rc = pm8001_request_irq(pm8001_ha);
1233         if (rc)
1234                 goto err_out_disable;
1235 #ifdef PM8001_USE_TASKLET
1236         /*  Tasklet for non msi-x interrupt handler */
1237         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1238             (pm8001_ha->chip_id == chip_8001))
1239                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1240                         (unsigned long)&(pm8001_ha->irq_vector[0]));
1241         else
1242                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1243                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1244                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
1245 #endif
1246         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1247         if (pm8001_ha->chip_id != chip_8001) {
1248                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1249                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1250         }
1251 
1252         /* Chip documentation for the 8070 and 8072 SPCv    */
1253         /* states that a 500ms minimum delay is required    */
1254         /* before issuing commands.  Otherwise, the firmare */
1255         /* will enter an unrecoverable state.               */
1256 
1257         if (pm8001_ha->chip_id == chip_8070 ||
1258                 pm8001_ha->chip_id == chip_8072) {
1259                 mdelay(500);
1260         }
1261 
1262         /* Spin up the PHYs */
1263 
1264         pm8001_ha->flags = PM8001F_RUN_TIME;
1265         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1266                 pm8001_ha->phy[i].enable_completion = &completion;
1267                 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1268                 wait_for_completion(&completion);
1269         }
1270         sas_resume_ha(sha);
1271         return 0;
1272 
1273 err_out_disable:
1274         scsi_remove_host(pm8001_ha->shost);
1275         pci_disable_device(pdev);
1276 err_out_enable:
1277         return rc;
1278 }
1279 
1280 /* update of pci device, vendor id and driver data with
1281  * unique value for each of the controller
1282  */
1283 static struct pci_device_id pm8001_pci_table[] = {
1284         { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1285         { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1286         { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1287         { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1288         /* Support for SPC/SPCv/SPCve controllers */
1289         { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1290         { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1291         { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1292         { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1293         { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1294         { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1295         { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1296         { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1297         { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1298         { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1299         { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1300         { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1301         { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1302         { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1303         { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1304         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1305                 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1306         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1307                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1308         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1309                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1310         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1311                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1312         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1313                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1314         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1315                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1316         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1317                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1318         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1319                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1320         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1321                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1322         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1323                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1324         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1325                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1326         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1327                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1328         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1329                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1330         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1331                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1332         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1333                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1334         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1335                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1336         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1337                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1338         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1339                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1340         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1341                 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1342         { PCI_VENDOR_ID_ATTO, 0x8070,
1343                 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1344         { PCI_VENDOR_ID_ATTO, 0x8070,
1345                 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1346         { PCI_VENDOR_ID_ATTO, 0x8072,
1347                 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1348         { PCI_VENDOR_ID_ATTO, 0x8072,
1349                 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1350         { PCI_VENDOR_ID_ATTO, 0x8070,
1351                 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1352         { PCI_VENDOR_ID_ATTO, 0x8072,
1353                 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1354         { PCI_VENDOR_ID_ATTO, 0x8072,
1355                 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1356         {} /* terminate list */
1357 };
1358 
1359 static struct pci_driver pm8001_pci_driver = {
1360         .name           = DRV_NAME,
1361         .id_table       = pm8001_pci_table,
1362         .probe          = pm8001_pci_probe,
1363         .remove         = pm8001_pci_remove,
1364         .suspend        = pm8001_pci_suspend,
1365         .resume         = pm8001_pci_resume,
1366 };
1367 
1368 /**
1369  *      pm8001_init - initialize scsi transport template
1370  */
1371 static int __init pm8001_init(void)
1372 {
1373         int rc = -ENOMEM;
1374 
1375         pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1376         if (!pm8001_wq)
1377                 goto err;
1378 
1379         pm8001_id = 0;
1380         pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1381         if (!pm8001_stt)
1382                 goto err_wq;
1383         rc = pci_register_driver(&pm8001_pci_driver);
1384         if (rc)
1385                 goto err_tp;
1386         return 0;
1387 
1388 err_tp:
1389         sas_release_transport(pm8001_stt);
1390 err_wq:
1391         destroy_workqueue(pm8001_wq);
1392 err:
1393         return rc;
1394 }
1395 
1396 static void __exit pm8001_exit(void)
1397 {
1398         pci_unregister_driver(&pm8001_pci_driver);
1399         sas_release_transport(pm8001_stt);
1400         destroy_workqueue(pm8001_wq);
1401 }
1402 
1403 module_init(pm8001_init);
1404 module_exit(pm8001_exit);
1405 
1406 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1407 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1408 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1409 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1410 MODULE_DESCRIPTION(
1411                 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1412                 "SAS/SATA controller driver");
1413 MODULE_VERSION(DRV_VERSION);
1414 MODULE_LICENSE("GPL");
1415 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1416 
1417 

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