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Linux/drivers/scsi/pm8001/pm8001_init.c

  1 /*
  2  * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
  3  *
  4  * Copyright (c) 2008-2009 USI Co., Ltd.
  5  * All rights reserved.
  6  *
  7  * Redistribution and use in source and binary forms, with or without
  8  * modification, are permitted provided that the following conditions
  9  * are met:
 10  * 1. Redistributions of source code must retain the above copyright
 11  *    notice, this list of conditions, and the following disclaimer,
 12  *    without modification.
 13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
 14  *    substantially similar to the "NO WARRANTY" disclaimer below
 15  *    ("Disclaimer") and any redistribution must be conditioned upon
 16  *    including a substantially similar Disclaimer requirement for further
 17  *    binary redistribution.
 18  * 3. Neither the names of the above-listed copyright holders nor the names
 19  *    of any contributors may be used to endorse or promote products derived
 20  *    from this software without specific prior written permission.
 21  *
 22  * Alternatively, this software may be distributed under the terms of the
 23  * GNU General Public License ("GPL") version 2 as published by the Free
 24  * Software Foundation.
 25  *
 26  * NO WARRANTY
 27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
 30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 37  * POSSIBILITY OF SUCH DAMAGES.
 38  *
 39  */
 40 
 41 #include <linux/slab.h>
 42 #include "pm8001_sas.h"
 43 #include "pm8001_chips.h"
 44 
 45 static struct scsi_transport_template *pm8001_stt;
 46 
 47 /**
 48  * chip info structure to identify chip key functionality as
 49  * encryption available/not, no of ports, hw specific function ref
 50  */
 51 static const struct pm8001_chip_info pm8001_chips[] = {
 52         [chip_8001] = {0,  8, &pm8001_8001_dispatch,},
 53         [chip_8008] = {0,  8, &pm8001_80xx_dispatch,},
 54         [chip_8009] = {1,  8, &pm8001_80xx_dispatch,},
 55         [chip_8018] = {0,  16, &pm8001_80xx_dispatch,},
 56         [chip_8019] = {1,  16, &pm8001_80xx_dispatch,},
 57         [chip_8074] = {0,  8, &pm8001_80xx_dispatch,},
 58         [chip_8076] = {0,  16, &pm8001_80xx_dispatch,},
 59         [chip_8077] = {0,  16, &pm8001_80xx_dispatch,},
 60 };
 61 static int pm8001_id;
 62 
 63 LIST_HEAD(hba_list);
 64 
 65 struct workqueue_struct *pm8001_wq;
 66 
 67 /**
 68  * The main structure which LLDD must register for scsi core.
 69  */
 70 static struct scsi_host_template pm8001_sht = {
 71         .module                 = THIS_MODULE,
 72         .name                   = DRV_NAME,
 73         .queuecommand           = sas_queuecommand,
 74         .target_alloc           = sas_target_alloc,
 75         .slave_configure        = sas_slave_configure,
 76         .scan_finished          = pm8001_scan_finished,
 77         .scan_start             = pm8001_scan_start,
 78         .change_queue_depth     = sas_change_queue_depth,
 79         .bios_param             = sas_bios_param,
 80         .can_queue              = 1,
 81         .this_id                = -1,
 82         .sg_tablesize           = SG_ALL,
 83         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
 84         .use_clustering         = ENABLE_CLUSTERING,
 85         .eh_device_reset_handler = sas_eh_device_reset_handler,
 86         .eh_bus_reset_handler   = sas_eh_bus_reset_handler,
 87         .target_destroy         = sas_target_destroy,
 88         .ioctl                  = sas_ioctl,
 89         .shost_attrs            = pm8001_host_attrs,
 90         .use_blk_tags           = 1,
 91         .track_queue_depth      = 1,
 92 };
 93 
 94 /**
 95  * Sas layer call this function to execute specific task.
 96  */
 97 static struct sas_domain_function_template pm8001_transport_ops = {
 98         .lldd_dev_found         = pm8001_dev_found,
 99         .lldd_dev_gone          = pm8001_dev_gone,
100 
101         .lldd_execute_task      = pm8001_queue_command,
102         .lldd_control_phy       = pm8001_phy_control,
103 
104         .lldd_abort_task        = pm8001_abort_task,
105         .lldd_abort_task_set    = pm8001_abort_task_set,
106         .lldd_clear_aca         = pm8001_clear_aca,
107         .lldd_clear_task_set    = pm8001_clear_task_set,
108         .lldd_I_T_nexus_reset   = pm8001_I_T_nexus_reset,
109         .lldd_lu_reset          = pm8001_lu_reset,
110         .lldd_query_task        = pm8001_query_task,
111 };
112 
113 /**
114  *pm8001_phy_init - initiate our adapter phys
115  *@pm8001_ha: our hba structure.
116  *@phy_id: phy id.
117  */
118 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
119 {
120         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
121         struct asd_sas_phy *sas_phy = &phy->sas_phy;
122         phy->phy_state = 0;
123         phy->pm8001_ha = pm8001_ha;
124         sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
125         sas_phy->class = SAS;
126         sas_phy->iproto = SAS_PROTOCOL_ALL;
127         sas_phy->tproto = 0;
128         sas_phy->type = PHY_TYPE_PHYSICAL;
129         sas_phy->role = PHY_ROLE_INITIATOR;
130         sas_phy->oob_mode = OOB_NOT_CONNECTED;
131         sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
132         sas_phy->id = phy_id;
133         sas_phy->sas_addr = &pm8001_ha->sas_addr[0];
134         sas_phy->frame_rcvd = &phy->frame_rcvd[0];
135         sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
136         sas_phy->lldd_phy = phy;
137 }
138 
139 /**
140  *pm8001_free - free hba
141  *@pm8001_ha:   our hba structure.
142  *
143  */
144 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
145 {
146         int i;
147 
148         if (!pm8001_ha)
149                 return;
150 
151         for (i = 0; i < USI_MAX_MEMCNT; i++) {
152                 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
153                         pci_free_consistent(pm8001_ha->pdev,
154                                 (pm8001_ha->memoryMap.region[i].total_len +
155                                 pm8001_ha->memoryMap.region[i].alignment),
156                                 pm8001_ha->memoryMap.region[i].virt_ptr,
157                                 pm8001_ha->memoryMap.region[i].phys_addr);
158                         }
159         }
160         PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
161         if (pm8001_ha->shost)
162                 scsi_host_put(pm8001_ha->shost);
163         flush_workqueue(pm8001_wq);
164         kfree(pm8001_ha->tags);
165         kfree(pm8001_ha);
166 }
167 
168 #ifdef PM8001_USE_TASKLET
169 
170 /**
171  * tasklet for 64 msi-x interrupt handler
172  * @opaque: the passed general host adapter struct
173  * Note: pm8001_tasklet is common for pm8001 & pm80xx
174  */
175 static void pm8001_tasklet(unsigned long opaque)
176 {
177         struct pm8001_hba_info *pm8001_ha;
178         struct isr_param *irq_vector;
179 
180         irq_vector = (struct isr_param *)opaque;
181         pm8001_ha = irq_vector->drv_inst;
182         if (unlikely(!pm8001_ha))
183                 BUG_ON(1);
184         PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
185 }
186 #endif
187 
188 /**
189  * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
190  * It obtains the vector number and calls the equivalent bottom
191  * half or services directly.
192  * @opaque: the passed outbound queue/vector. Host structure is
193  * retrieved from the same.
194  */
195 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
196 {
197         struct isr_param *irq_vector;
198         struct pm8001_hba_info *pm8001_ha;
199         irqreturn_t ret = IRQ_HANDLED;
200         irq_vector = (struct isr_param *)opaque;
201         pm8001_ha = irq_vector->drv_inst;
202 
203         if (unlikely(!pm8001_ha))
204                 return IRQ_NONE;
205         if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
206                 return IRQ_NONE;
207 #ifdef PM8001_USE_TASKLET
208         tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
209 #else
210         ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
211 #endif
212         return ret;
213 }
214 
215 /**
216  * pm8001_interrupt_handler_intx - main INTx interrupt handler.
217  * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure.
218  */
219 
220 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
221 {
222         struct pm8001_hba_info *pm8001_ha;
223         irqreturn_t ret = IRQ_HANDLED;
224         struct sas_ha_struct *sha = dev_id;
225         pm8001_ha = sha->lldd_ha;
226         if (unlikely(!pm8001_ha))
227                 return IRQ_NONE;
228         if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
229                 return IRQ_NONE;
230 
231 #ifdef PM8001_USE_TASKLET
232         tasklet_schedule(&pm8001_ha->tasklet[0]);
233 #else
234         ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
235 #endif
236         return ret;
237 }
238 
239 /**
240  * pm8001_alloc - initiate our hba structure and 6 DMAs area.
241  * @pm8001_ha:our hba structure.
242  *
243  */
244 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
245                         const struct pci_device_id *ent)
246 {
247         int i;
248         spin_lock_init(&pm8001_ha->lock);
249         spin_lock_init(&pm8001_ha->bitmap_lock);
250         PM8001_INIT_DBG(pm8001_ha,
251                 pm8001_printk("pm8001_alloc: PHY:%x\n",
252                                 pm8001_ha->chip->n_phy));
253         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
254                 pm8001_phy_init(pm8001_ha, i);
255                 pm8001_ha->port[i].wide_port_phymap = 0;
256                 pm8001_ha->port[i].port_attached = 0;
257                 pm8001_ha->port[i].port_state = 0;
258                 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
259         }
260 
261         pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL);
262         if (!pm8001_ha->tags)
263                 goto err_out;
264         /* MPI Memory region 1 for AAP Event Log for fw */
265         pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
266         pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
267         pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
268         pm8001_ha->memoryMap.region[AAP1].alignment = 32;
269 
270         /* MPI Memory region 2 for IOP Event Log for fw */
271         pm8001_ha->memoryMap.region[IOP].num_elements = 1;
272         pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
273         pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
274         pm8001_ha->memoryMap.region[IOP].alignment = 32;
275 
276         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
277                 /* MPI Memory region 3 for consumer Index of inbound queues */
278                 pm8001_ha->memoryMap.region[CI+i].num_elements = 1;
279                 pm8001_ha->memoryMap.region[CI+i].element_size = 4;
280                 pm8001_ha->memoryMap.region[CI+i].total_len = 4;
281                 pm8001_ha->memoryMap.region[CI+i].alignment = 4;
282 
283                 if ((ent->driver_data) != chip_8001) {
284                         /* MPI Memory region 5 inbound queues */
285                         pm8001_ha->memoryMap.region[IB+i].num_elements =
286                                                 PM8001_MPI_QUEUE;
287                         pm8001_ha->memoryMap.region[IB+i].element_size = 128;
288                         pm8001_ha->memoryMap.region[IB+i].total_len =
289                                                 PM8001_MPI_QUEUE * 128;
290                         pm8001_ha->memoryMap.region[IB+i].alignment = 128;
291                 } else {
292                         pm8001_ha->memoryMap.region[IB+i].num_elements =
293                                                 PM8001_MPI_QUEUE;
294                         pm8001_ha->memoryMap.region[IB+i].element_size = 64;
295                         pm8001_ha->memoryMap.region[IB+i].total_len =
296                                                 PM8001_MPI_QUEUE * 64;
297                         pm8001_ha->memoryMap.region[IB+i].alignment = 64;
298                 }
299         }
300 
301         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
302                 /* MPI Memory region 4 for producer Index of outbound queues */
303                 pm8001_ha->memoryMap.region[PI+i].num_elements = 1;
304                 pm8001_ha->memoryMap.region[PI+i].element_size = 4;
305                 pm8001_ha->memoryMap.region[PI+i].total_len = 4;
306                 pm8001_ha->memoryMap.region[PI+i].alignment = 4;
307 
308                 if (ent->driver_data != chip_8001) {
309                         /* MPI Memory region 6 Outbound queues */
310                         pm8001_ha->memoryMap.region[OB+i].num_elements =
311                                                 PM8001_MPI_QUEUE;
312                         pm8001_ha->memoryMap.region[OB+i].element_size = 128;
313                         pm8001_ha->memoryMap.region[OB+i].total_len =
314                                                 PM8001_MPI_QUEUE * 128;
315                         pm8001_ha->memoryMap.region[OB+i].alignment = 128;
316                 } else {
317                         /* MPI Memory region 6 Outbound queues */
318                         pm8001_ha->memoryMap.region[OB+i].num_elements =
319                                                 PM8001_MPI_QUEUE;
320                         pm8001_ha->memoryMap.region[OB+i].element_size = 64;
321                         pm8001_ha->memoryMap.region[OB+i].total_len =
322                                                 PM8001_MPI_QUEUE * 64;
323                         pm8001_ha->memoryMap.region[OB+i].alignment = 64;
324                 }
325 
326         }
327         /* Memory region write DMA*/
328         pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
329         pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
330         pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
331         /* Memory region for devices*/
332         pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1;
333         pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES *
334                 sizeof(struct pm8001_device);
335         pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES *
336                 sizeof(struct pm8001_device);
337 
338         /* Memory region for ccb_info*/
339         pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1;
340         pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB *
341                 sizeof(struct pm8001_ccb_info);
342         pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB *
343                 sizeof(struct pm8001_ccb_info);
344 
345         /* Memory region for fw flash */
346         pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
347 
348         pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
349         pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
350         pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
351         pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
352         for (i = 0; i < USI_MAX_MEMCNT; i++) {
353                 if (pm8001_mem_alloc(pm8001_ha->pdev,
354                         &pm8001_ha->memoryMap.region[i].virt_ptr,
355                         &pm8001_ha->memoryMap.region[i].phys_addr,
356                         &pm8001_ha->memoryMap.region[i].phys_addr_hi,
357                         &pm8001_ha->memoryMap.region[i].phys_addr_lo,
358                         pm8001_ha->memoryMap.region[i].total_len,
359                         pm8001_ha->memoryMap.region[i].alignment) != 0) {
360                                 PM8001_FAIL_DBG(pm8001_ha,
361                                         pm8001_printk("Mem%d alloc failed\n",
362                                         i));
363                                 goto err_out;
364                 }
365         }
366 
367         pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr;
368         for (i = 0; i < PM8001_MAX_DEVICES; i++) {
369                 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
370                 pm8001_ha->devices[i].id = i;
371                 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
372                 pm8001_ha->devices[i].running_req = 0;
373         }
374         pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr;
375         for (i = 0; i < PM8001_MAX_CCB; i++) {
376                 pm8001_ha->ccb_info[i].ccb_dma_handle =
377                         pm8001_ha->memoryMap.region[CCB_MEM].phys_addr +
378                         i * sizeof(struct pm8001_ccb_info);
379                 pm8001_ha->ccb_info[i].task = NULL;
380                 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
381                 pm8001_ha->ccb_info[i].device = NULL;
382                 ++pm8001_ha->tags_num;
383         }
384         pm8001_ha->flags = PM8001F_INIT_TIME;
385         /* Initialize tags */
386         pm8001_tag_init(pm8001_ha);
387         return 0;
388 err_out:
389         return 1;
390 }
391 
392 /**
393  * pm8001_ioremap - remap the pci high physical address to kernal virtual
394  * address so that we can access them.
395  * @pm8001_ha:our hba structure.
396  */
397 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
398 {
399         u32 bar;
400         u32 logicalBar = 0;
401         struct pci_dev *pdev;
402 
403         pdev = pm8001_ha->pdev;
404         /* map pci mem (PMC pci base 0-3)*/
405         for (bar = 0; bar < 6; bar++) {
406                 /*
407                 ** logical BARs for SPC:
408                 ** bar 0 and 1 - logical BAR0
409                 ** bar 2 and 3 - logical BAR1
410                 ** bar4 - logical BAR2
411                 ** bar5 - logical BAR3
412                 ** Skip the appropriate assignments:
413                 */
414                 if ((bar == 1) || (bar == 3))
415                         continue;
416                 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
417                         pm8001_ha->io_mem[logicalBar].membase =
418                                 pci_resource_start(pdev, bar);
419                         pm8001_ha->io_mem[logicalBar].membase &=
420                                 (u32)PCI_BASE_ADDRESS_MEM_MASK;
421                         pm8001_ha->io_mem[logicalBar].memsize =
422                                 pci_resource_len(pdev, bar);
423                         pm8001_ha->io_mem[logicalBar].memvirtaddr =
424                                 ioremap(pm8001_ha->io_mem[logicalBar].membase,
425                                 pm8001_ha->io_mem[logicalBar].memsize);
426                         PM8001_INIT_DBG(pm8001_ha,
427                                 pm8001_printk("PCI: bar %d, logicalBar %d ",
428                                 bar, logicalBar));
429                         PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
430                                 "base addr %llx virt_addr=%llx len=%d\n",
431                                 (u64)pm8001_ha->io_mem[logicalBar].membase,
432                                 (u64)(unsigned long)
433                                 pm8001_ha->io_mem[logicalBar].memvirtaddr,
434                                 pm8001_ha->io_mem[logicalBar].memsize));
435                 } else {
436                         pm8001_ha->io_mem[logicalBar].membase   = 0;
437                         pm8001_ha->io_mem[logicalBar].memsize   = 0;
438                         pm8001_ha->io_mem[logicalBar].memvirtaddr = 0;
439                 }
440                 logicalBar++;
441         }
442         return 0;
443 }
444 
445 /**
446  * pm8001_pci_alloc - initialize our ha card structure
447  * @pdev: pci device.
448  * @ent: ent
449  * @shost: scsi host struct which has been initialized before.
450  */
451 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
452                                  const struct pci_device_id *ent,
453                                 struct Scsi_Host *shost)
454 
455 {
456         struct pm8001_hba_info *pm8001_ha;
457         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
458         int j;
459 
460         pm8001_ha = sha->lldd_ha;
461         if (!pm8001_ha)
462                 return NULL;
463 
464         pm8001_ha->pdev = pdev;
465         pm8001_ha->dev = &pdev->dev;
466         pm8001_ha->chip_id = ent->driver_data;
467         pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
468         pm8001_ha->irq = pdev->irq;
469         pm8001_ha->sas = sha;
470         pm8001_ha->shost = shost;
471         pm8001_ha->id = pm8001_id++;
472         pm8001_ha->logging_level = 0x01;
473         sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
474         /* IOMB size is 128 for 8088/89 controllers */
475         if (pm8001_ha->chip_id != chip_8001)
476                 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
477         else
478                 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
479 
480 #ifdef PM8001_USE_TASKLET
481         /* Tasklet for non msi-x interrupt handler */
482         if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
483                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
484                         (unsigned long)&(pm8001_ha->irq_vector[0]));
485         else
486                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
487                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
488                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
489 #endif
490         pm8001_ioremap(pm8001_ha);
491         if (!pm8001_alloc(pm8001_ha, ent))
492                 return pm8001_ha;
493         pm8001_free(pm8001_ha);
494         return NULL;
495 }
496 
497 /**
498  * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
499  * @pdev: pci device.
500  */
501 static int pci_go_44(struct pci_dev *pdev)
502 {
503         int rc;
504 
505         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(44))) {
506                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(44));
507                 if (rc) {
508                         rc = pci_set_consistent_dma_mask(pdev,
509                                 DMA_BIT_MASK(32));
510                         if (rc) {
511                                 dev_printk(KERN_ERR, &pdev->dev,
512                                         "44-bit DMA enable failed\n");
513                                 return rc;
514                         }
515                 }
516         } else {
517                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
518                 if (rc) {
519                         dev_printk(KERN_ERR, &pdev->dev,
520                                 "32-bit DMA enable failed\n");
521                         return rc;
522                 }
523                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
524                 if (rc) {
525                         dev_printk(KERN_ERR, &pdev->dev,
526                                 "32-bit consistent DMA enable failed\n");
527                         return rc;
528                 }
529         }
530         return rc;
531 }
532 
533 /**
534  * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
535  * @shost: scsi host which has been allocated outside.
536  * @chip_info: our ha struct.
537  */
538 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
539                                    const struct pm8001_chip_info *chip_info)
540 {
541         int phy_nr, port_nr;
542         struct asd_sas_phy **arr_phy;
543         struct asd_sas_port **arr_port;
544         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
545 
546         phy_nr = chip_info->n_phy;
547         port_nr = phy_nr;
548         memset(sha, 0x00, sizeof(*sha));
549         arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
550         if (!arr_phy)
551                 goto exit;
552         arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
553         if (!arr_port)
554                 goto exit_free2;
555 
556         sha->sas_phy = arr_phy;
557         sha->sas_port = arr_port;
558         sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
559         if (!sha->lldd_ha)
560                 goto exit_free1;
561 
562         shost->transportt = pm8001_stt;
563         shost->max_id = PM8001_MAX_DEVICES;
564         shost->max_lun = 8;
565         shost->max_channel = 0;
566         shost->unique_id = pm8001_id;
567         shost->max_cmd_len = 16;
568         shost->can_queue = PM8001_CAN_QUEUE;
569         shost->cmd_per_lun = 32;
570         return 0;
571 exit_free1:
572         kfree(arr_port);
573 exit_free2:
574         kfree(arr_phy);
575 exit:
576         return -1;
577 }
578 
579 /**
580  * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
581  * @shost: scsi host which has been allocated outside
582  * @chip_info: our ha struct.
583  */
584 static void  pm8001_post_sas_ha_init(struct Scsi_Host *shost,
585                                      const struct pm8001_chip_info *chip_info)
586 {
587         int i = 0;
588         struct pm8001_hba_info *pm8001_ha;
589         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
590 
591         pm8001_ha = sha->lldd_ha;
592         for (i = 0; i < chip_info->n_phy; i++) {
593                 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
594                 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
595         }
596         sha->sas_ha_name = DRV_NAME;
597         sha->dev = pm8001_ha->dev;
598 
599         sha->lldd_module = THIS_MODULE;
600         sha->sas_addr = &pm8001_ha->sas_addr[0];
601         sha->num_phys = chip_info->n_phy;
602         sha->core.shost = shost;
603 }
604 
605 /**
606  * pm8001_init_sas_add - initialize sas address
607  * @chip_info: our ha struct.
608  *
609  * Currently we just set the fixed SAS address to our HBA,for manufacture,
610  * it should read from the EEPROM
611  */
612 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
613 {
614         u8 i, j;
615 #ifdef PM8001_READ_VPD
616         /* For new SPC controllers WWN is stored in flash vpd
617         *  For SPC/SPCve controllers WWN is stored in EEPROM
618         *  For Older SPC WWN is stored in NVMD
619         */
620         DECLARE_COMPLETION_ONSTACK(completion);
621         struct pm8001_ioctl_payload payload;
622         u16 deviceid;
623         int rc;
624 
625         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
626         pm8001_ha->nvmd_completion = &completion;
627 
628         if (pm8001_ha->chip_id == chip_8001) {
629                 if (deviceid == 0x8081 || deviceid == 0x0042) {
630                         payload.minor_function = 4;
631                         payload.length = 4096;
632                 } else {
633                         payload.minor_function = 0;
634                         payload.length = 128;
635                 }
636         } else {
637                 payload.minor_function = 1;
638                 payload.length = 4096;
639         }
640         payload.offset = 0;
641         payload.func_specific = kzalloc(payload.length, GFP_KERNEL);
642         if (!payload.func_specific) {
643                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("mem alloc fail\n"));
644                 return;
645         }
646         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
647         if (rc) {
648                 kfree(payload.func_specific);
649                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
650                 return;
651         }
652         wait_for_completion(&completion);
653 
654         for (i = 0, j = 0; i <= 7; i++, j++) {
655                 if (pm8001_ha->chip_id == chip_8001) {
656                         if (deviceid == 0x8081)
657                                 pm8001_ha->sas_addr[j] =
658                                         payload.func_specific[0x704 + i];
659                         else if (deviceid == 0x0042)
660                                 pm8001_ha->sas_addr[j] =
661                                         payload.func_specific[0x010 + i];
662                 } else
663                         pm8001_ha->sas_addr[j] =
664                                         payload.func_specific[0x804 + i];
665         }
666 
667         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
668                 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
669                         pm8001_ha->sas_addr, SAS_ADDR_SIZE);
670                 PM8001_INIT_DBG(pm8001_ha,
671                         pm8001_printk("phy %d sas_addr = %016llx\n", i,
672                         pm8001_ha->phy[i].dev_sas_addr));
673         }
674         kfree(payload.func_specific);
675 #else
676         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
677                 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
678                 pm8001_ha->phy[i].dev_sas_addr =
679                         cpu_to_be64((u64)
680                                 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
681         }
682         memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
683                 SAS_ADDR_SIZE);
684 #endif
685 }
686 
687 /*
688  * pm8001_get_phy_settings_info : Read phy setting values.
689  * @pm8001_ha : our hba.
690  */
691 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
692 {
693 
694 #ifdef PM8001_READ_VPD
695         /*OPTION ROM FLASH read for the SPC cards */
696         DECLARE_COMPLETION_ONSTACK(completion);
697         struct pm8001_ioctl_payload payload;
698         int rc;
699 
700         pm8001_ha->nvmd_completion = &completion;
701         /* SAS ADDRESS read from flash / EEPROM */
702         payload.minor_function = 6;
703         payload.offset = 0;
704         payload.length = 4096;
705         payload.func_specific = kzalloc(4096, GFP_KERNEL);
706         if (!payload.func_specific)
707                 return -ENOMEM;
708         /* Read phy setting values from flash */
709         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
710         if (rc) {
711                 kfree(payload.func_specific);
712                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
713                 return -ENOMEM;
714         }
715         wait_for_completion(&completion);
716         pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
717         kfree(payload.func_specific);
718 #endif
719         return 0;
720 }
721 
722 #ifdef PM8001_USE_MSIX
723 /**
724  * pm8001_setup_msix - enable MSI-X interrupt
725  * @chip_info: our ha struct.
726  * @irq_handler: irq_handler
727  */
728 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
729 {
730         u32 i = 0, j = 0;
731         u32 number_of_intr;
732         int flag = 0;
733         u32 max_entry;
734         int rc;
735         static char intr_drvname[PM8001_MAX_MSIX_VEC][sizeof(DRV_NAME)+3];
736 
737         /* SPCv controllers supports 64 msi-x */
738         if (pm8001_ha->chip_id == chip_8001) {
739                 number_of_intr = 1;
740         } else {
741                 number_of_intr = PM8001_MAX_MSIX_VEC;
742                 flag &= ~IRQF_SHARED;
743         }
744 
745         max_entry = sizeof(pm8001_ha->msix_entries) /
746                 sizeof(pm8001_ha->msix_entries[0]);
747         for (i = 0; i < max_entry ; i++)
748                 pm8001_ha->msix_entries[i].entry = i;
749         rc = pci_enable_msix_exact(pm8001_ha->pdev, pm8001_ha->msix_entries,
750                 number_of_intr);
751         pm8001_ha->number_of_intr = number_of_intr;
752         if (rc)
753                 return rc;
754 
755         PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
756                 "pci_enable_msix_exact request ret:%d no of intr %d\n",
757                                 rc, pm8001_ha->number_of_intr));
758 
759         for (i = 0; i < number_of_intr; i++) {
760                 snprintf(intr_drvname[i], sizeof(intr_drvname[0]),
761                                 DRV_NAME"%d", i);
762                 pm8001_ha->irq_vector[i].irq_id = i;
763                 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
764 
765                 rc = request_irq(pm8001_ha->msix_entries[i].vector,
766                         pm8001_interrupt_handler_msix, flag,
767                         intr_drvname[i], &(pm8001_ha->irq_vector[i]));
768                 if (rc) {
769                         for (j = 0; j < i; j++) {
770                                 free_irq(pm8001_ha->msix_entries[j].vector,
771                                         &(pm8001_ha->irq_vector[i]));
772                         }
773                         pci_disable_msix(pm8001_ha->pdev);
774                         break;
775                 }
776         }
777 
778         return rc;
779 }
780 #endif
781 
782 /**
783  * pm8001_request_irq - register interrupt
784  * @chip_info: our ha struct.
785  */
786 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
787 {
788         struct pci_dev *pdev;
789         int rc;
790 
791         pdev = pm8001_ha->pdev;
792 
793 #ifdef PM8001_USE_MSIX
794         if (pdev->msix_cap)
795                 return pm8001_setup_msix(pm8001_ha);
796         else {
797                 PM8001_INIT_DBG(pm8001_ha,
798                         pm8001_printk("MSIX not supported!!!\n"));
799                 goto intx;
800         }
801 #endif
802 
803 intx:
804         /* initialize the INT-X interrupt */
805         rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
806                 DRV_NAME, SHOST_TO_SAS_HA(pm8001_ha->shost));
807         return rc;
808 }
809 
810 /**
811  * pm8001_pci_probe - probe supported device
812  * @pdev: pci device which kernel has been prepared for.
813  * @ent: pci device id
814  *
815  * This function is the main initialization function, when register a new
816  * pci driver it is invoked, all struct an hardware initilization should be done
817  * here, also, register interrupt
818  */
819 static int pm8001_pci_probe(struct pci_dev *pdev,
820                             const struct pci_device_id *ent)
821 {
822         unsigned int rc;
823         u32     pci_reg;
824         u8      i = 0;
825         struct pm8001_hba_info *pm8001_ha;
826         struct Scsi_Host *shost = NULL;
827         const struct pm8001_chip_info *chip;
828 
829         dev_printk(KERN_INFO, &pdev->dev,
830                 "pm80xx: driver version %s\n", DRV_VERSION);
831         rc = pci_enable_device(pdev);
832         if (rc)
833                 goto err_out_enable;
834         pci_set_master(pdev);
835         /*
836          * Enable pci slot busmaster by setting pci command register.
837          * This is required by FW for Cyclone card.
838          */
839 
840         pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
841         pci_reg |= 0x157;
842         pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
843         rc = pci_request_regions(pdev, DRV_NAME);
844         if (rc)
845                 goto err_out_disable;
846         rc = pci_go_44(pdev);
847         if (rc)
848                 goto err_out_regions;
849 
850         shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
851         if (!shost) {
852                 rc = -ENOMEM;
853                 goto err_out_regions;
854         }
855         chip = &pm8001_chips[ent->driver_data];
856         SHOST_TO_SAS_HA(shost) =
857                 kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
858         if (!SHOST_TO_SAS_HA(shost)) {
859                 rc = -ENOMEM;
860                 goto err_out_free_host;
861         }
862 
863         rc = pm8001_prep_sas_ha_init(shost, chip);
864         if (rc) {
865                 rc = -ENOMEM;
866                 goto err_out_free;
867         }
868         pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
869         /* ent->driver variable is used to differentiate between controllers */
870         pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
871         if (!pm8001_ha) {
872                 rc = -ENOMEM;
873                 goto err_out_free;
874         }
875         list_add_tail(&pm8001_ha->list, &hba_list);
876         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
877         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
878         if (rc) {
879                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
880                         "chip_init failed [ret: %d]\n", rc));
881                 goto err_out_ha_free;
882         }
883 
884         rc = scsi_add_host(shost, &pdev->dev);
885         if (rc)
886                 goto err_out_ha_free;
887         rc = pm8001_request_irq(pm8001_ha);
888         if (rc) {
889                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
890                         "pm8001_request_irq failed [ret: %d]\n", rc));
891                 goto err_out_shost;
892         }
893 
894         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
895         if (pm8001_ha->chip_id != chip_8001) {
896                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
897                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
898                 /* setup thermal configuration. */
899                 pm80xx_set_thermal_config(pm8001_ha);
900         }
901 
902         pm8001_init_sas_add(pm8001_ha);
903         /* phy setting support for motherboard controller */
904         if (pdev->subsystem_vendor != PCI_VENDOR_ID_ADAPTEC2 &&
905                 pdev->subsystem_vendor != 0) {
906                 rc = pm8001_get_phy_settings_info(pm8001_ha);
907                 if (rc)
908                         goto err_out_shost;
909         }
910         pm8001_post_sas_ha_init(shost, chip);
911         rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
912         if (rc)
913                 goto err_out_shost;
914         scsi_scan_host(pm8001_ha->shost);
915         return 0;
916 
917 err_out_shost:
918         scsi_remove_host(pm8001_ha->shost);
919 err_out_ha_free:
920         pm8001_free(pm8001_ha);
921 err_out_free:
922         kfree(SHOST_TO_SAS_HA(shost));
923 err_out_free_host:
924         kfree(shost);
925 err_out_regions:
926         pci_release_regions(pdev);
927 err_out_disable:
928         pci_disable_device(pdev);
929 err_out_enable:
930         return rc;
931 }
932 
933 static void pm8001_pci_remove(struct pci_dev *pdev)
934 {
935         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
936         struct pm8001_hba_info *pm8001_ha;
937         int i, j;
938         pm8001_ha = sha->lldd_ha;
939         sas_unregister_ha(sha);
940         sas_remove_host(pm8001_ha->shost);
941         list_del(&pm8001_ha->list);
942         scsi_remove_host(pm8001_ha->shost);
943         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
944         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
945 
946 #ifdef PM8001_USE_MSIX
947         for (i = 0; i < pm8001_ha->number_of_intr; i++)
948                 synchronize_irq(pm8001_ha->msix_entries[i].vector);
949         for (i = 0; i < pm8001_ha->number_of_intr; i++)
950                 free_irq(pm8001_ha->msix_entries[i].vector,
951                                 &(pm8001_ha->irq_vector[i]));
952         pci_disable_msix(pdev);
953 #else
954         free_irq(pm8001_ha->irq, sha);
955 #endif
956 #ifdef PM8001_USE_TASKLET
957         /* For non-msix and msix interrupts */
958         if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
959                 tasklet_kill(&pm8001_ha->tasklet[0]);
960         else
961                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
962                         tasklet_kill(&pm8001_ha->tasklet[j]);
963 #endif
964         pm8001_free(pm8001_ha);
965         kfree(sha->sas_phy);
966         kfree(sha->sas_port);
967         kfree(sha);
968         pci_release_regions(pdev);
969         pci_disable_device(pdev);
970 }
971 
972 /**
973  * pm8001_pci_suspend - power management suspend main entry point
974  * @pdev: PCI device struct
975  * @state: PM state change to (usually PCI_D3)
976  *
977  * Returns 0 success, anything else error.
978  */
979 static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
980 {
981         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
982         struct pm8001_hba_info *pm8001_ha;
983         int  i, j;
984         u32 device_state;
985         pm8001_ha = sha->lldd_ha;
986         sas_suspend_ha(sha);
987         flush_workqueue(pm8001_wq);
988         scsi_block_requests(pm8001_ha->shost);
989         if (!pdev->pm_cap) {
990                 dev_err(&pdev->dev, " PCI PM not supported\n");
991                 return -ENODEV;
992         }
993         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
994         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
995 #ifdef PM8001_USE_MSIX
996         for (i = 0; i < pm8001_ha->number_of_intr; i++)
997                 synchronize_irq(pm8001_ha->msix_entries[i].vector);
998         for (i = 0; i < pm8001_ha->number_of_intr; i++)
999                 free_irq(pm8001_ha->msix_entries[i].vector,
1000                                 &(pm8001_ha->irq_vector[i]));
1001         pci_disable_msix(pdev);
1002 #else
1003         free_irq(pm8001_ha->irq, sha);
1004 #endif
1005 #ifdef PM8001_USE_TASKLET
1006         /* For non-msix and msix interrupts */
1007         if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
1008                 tasklet_kill(&pm8001_ha->tasklet[0]);
1009         else
1010                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1011                         tasklet_kill(&pm8001_ha->tasklet[j]);
1012 #endif
1013         device_state = pci_choose_state(pdev, state);
1014         pm8001_printk("pdev=0x%p, slot=%s, entering "
1015                       "operating state [D%d]\n", pdev,
1016                       pm8001_ha->name, device_state);
1017         pci_save_state(pdev);
1018         pci_disable_device(pdev);
1019         pci_set_power_state(pdev, device_state);
1020         return 0;
1021 }
1022 
1023 /**
1024  * pm8001_pci_resume - power management resume main entry point
1025  * @pdev: PCI device struct
1026  *
1027  * Returns 0 success, anything else error.
1028  */
1029 static int pm8001_pci_resume(struct pci_dev *pdev)
1030 {
1031         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1032         struct pm8001_hba_info *pm8001_ha;
1033         int rc;
1034         u8 i = 0, j;
1035         u32 device_state;
1036         DECLARE_COMPLETION_ONSTACK(completion);
1037         pm8001_ha = sha->lldd_ha;
1038         device_state = pdev->current_state;
1039 
1040         pm8001_printk("pdev=0x%p, slot=%s, resuming from previous "
1041                 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state);
1042 
1043         pci_set_power_state(pdev, PCI_D0);
1044         pci_enable_wake(pdev, PCI_D0, 0);
1045         pci_restore_state(pdev);
1046         rc = pci_enable_device(pdev);
1047         if (rc) {
1048                 pm8001_printk("slot=%s Enable device failed during resume\n",
1049                               pm8001_ha->name);
1050                 goto err_out_enable;
1051         }
1052 
1053         pci_set_master(pdev);
1054         rc = pci_go_44(pdev);
1055         if (rc)
1056                 goto err_out_disable;
1057         sas_prep_resume_ha(sha);
1058         /* chip soft rst only for spc */
1059         if (pm8001_ha->chip_id == chip_8001) {
1060                 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1061                 PM8001_INIT_DBG(pm8001_ha,
1062                         pm8001_printk("chip soft reset successful\n"));
1063         }
1064         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1065         if (rc)
1066                 goto err_out_disable;
1067 
1068         /* disable all the interrupt bits */
1069         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1070 
1071         rc = pm8001_request_irq(pm8001_ha);
1072         if (rc)
1073                 goto err_out_disable;
1074 #ifdef PM8001_USE_TASKLET
1075         /*  Tasklet for non msi-x interrupt handler */
1076         if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
1077                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1078                         (unsigned long)&(pm8001_ha->irq_vector[0]));
1079         else
1080                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1081                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1082                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
1083 #endif
1084         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1085         if (pm8001_ha->chip_id != chip_8001) {
1086                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1087                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1088         }
1089         pm8001_ha->flags = PM8001F_RUN_TIME;
1090         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1091                 pm8001_ha->phy[i].enable_completion = &completion;
1092                 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1093                 wait_for_completion(&completion);
1094         }
1095         sas_resume_ha(sha);
1096         return 0;
1097 
1098 err_out_disable:
1099         scsi_remove_host(pm8001_ha->shost);
1100         pci_disable_device(pdev);
1101 err_out_enable:
1102         return rc;
1103 }
1104 
1105 /* update of pci device, vendor id and driver data with
1106  * unique value for each of the controller
1107  */
1108 static struct pci_device_id pm8001_pci_table[] = {
1109         { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1110         { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1111         /* Support for SPC/SPCv/SPCve controllers */
1112         { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1113         { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1114         { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1115         { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1116         { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1117         { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1118         { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1119         { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1120         { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1121         { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1122         { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1123         { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1124         { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1125         { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1126         { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1127         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1128                 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1129         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1130                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1131         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1132                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1133         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1134                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1135         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1136                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1137         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1138                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1139         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1140                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1141         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1142                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1143         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1144                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1145         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1146                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1147         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1148                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1149         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1150                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1151         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1152                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1153         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1154                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1155         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1156                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1157         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1158                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1159         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1160                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1161         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1162                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1163         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1164                 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1165         {} /* terminate list */
1166 };
1167 
1168 static struct pci_driver pm8001_pci_driver = {
1169         .name           = DRV_NAME,
1170         .id_table       = pm8001_pci_table,
1171         .probe          = pm8001_pci_probe,
1172         .remove         = pm8001_pci_remove,
1173         .suspend        = pm8001_pci_suspend,
1174         .resume         = pm8001_pci_resume,
1175 };
1176 
1177 /**
1178  *      pm8001_init - initialize scsi transport template
1179  */
1180 static int __init pm8001_init(void)
1181 {
1182         int rc = -ENOMEM;
1183 
1184         pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1185         if (!pm8001_wq)
1186                 goto err;
1187 
1188         pm8001_id = 0;
1189         pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1190         if (!pm8001_stt)
1191                 goto err_wq;
1192         rc = pci_register_driver(&pm8001_pci_driver);
1193         if (rc)
1194                 goto err_tp;
1195         return 0;
1196 
1197 err_tp:
1198         sas_release_transport(pm8001_stt);
1199 err_wq:
1200         destroy_workqueue(pm8001_wq);
1201 err:
1202         return rc;
1203 }
1204 
1205 static void __exit pm8001_exit(void)
1206 {
1207         pci_unregister_driver(&pm8001_pci_driver);
1208         sas_release_transport(pm8001_stt);
1209         destroy_workqueue(pm8001_wq);
1210 }
1211 
1212 module_init(pm8001_init);
1213 module_exit(pm8001_exit);
1214 
1215 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1216 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1217 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1218 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1219 MODULE_DESCRIPTION(
1220                 "PMC-Sierra PM8001/8081/8088/8089/8074/8076/8077 "
1221                 "SAS/SATA controller driver");
1222 MODULE_VERSION(DRV_VERSION);
1223 MODULE_LICENSE("GPL");
1224 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1225 
1226 

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