Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4

Linux/drivers/scsi/mvsas/mv_init.c

  1 /*
  2  * Marvell 88SE64xx/88SE94xx pci init
  3  *
  4  * Copyright 2007 Red Hat, Inc.
  5  * Copyright 2008 Marvell. <kewei@marvell.com>
  6  * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
  7  *
  8  * This file is licensed under GPLv2.
  9  *
 10  * This program is free software; you can redistribute it and/or
 11  * modify it under the terms of the GNU General Public License as
 12  * published by the Free Software Foundation; version 2 of the
 13  * License.
 14  *
 15  * This program is distributed in the hope that it will be useful,
 16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 18  * General Public License for more details.
 19  *
 20  * You should have received a copy of the GNU General Public License
 21  * along with this program; if not, write to the Free Software
 22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
 23  * USA
 24 */
 25 
 26 
 27 #include "mv_sas.h"
 28 
 29 int interrupt_coalescing = 0x80;
 30 
 31 static struct scsi_transport_template *mvs_stt;
 32 static const struct mvs_chip_info mvs_chips[] = {
 33         [chip_6320] =   { 1, 2, 0x400, 17, 16, 6,  9, &mvs_64xx_dispatch, },
 34         [chip_6440] =   { 1, 4, 0x400, 17, 16, 6,  9, &mvs_64xx_dispatch, },
 35         [chip_6485] =   { 1, 8, 0x800, 33, 32, 6, 10, &mvs_64xx_dispatch, },
 36         [chip_9180] =   { 2, 4, 0x800, 17, 64, 8,  9, &mvs_94xx_dispatch, },
 37         [chip_9480] =   { 2, 4, 0x800, 17, 64, 8,  9, &mvs_94xx_dispatch, },
 38         [chip_9445] =   { 1, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
 39         [chip_9485] =   { 2, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
 40         [chip_1300] =   { 1, 4, 0x400, 17, 16, 6,  9, &mvs_64xx_dispatch, },
 41         [chip_1320] =   { 2, 4, 0x800, 17, 64, 8,  9, &mvs_94xx_dispatch, },
 42 };
 43 
 44 struct device_attribute *mvst_host_attrs[];
 45 
 46 #define SOC_SAS_NUM 2
 47 
 48 static struct scsi_host_template mvs_sht = {
 49         .module                 = THIS_MODULE,
 50         .name                   = DRV_NAME,
 51         .queuecommand           = sas_queuecommand,
 52         .target_alloc           = sas_target_alloc,
 53         .slave_configure        = sas_slave_configure,
 54         .scan_finished          = mvs_scan_finished,
 55         .scan_start             = mvs_scan_start,
 56         .change_queue_depth     = sas_change_queue_depth,
 57         .bios_param             = sas_bios_param,
 58         .can_queue              = 1,
 59         .this_id                = -1,
 60         .sg_tablesize           = SG_ALL,
 61         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
 62         .use_clustering         = ENABLE_CLUSTERING,
 63         .eh_device_reset_handler = sas_eh_device_reset_handler,
 64         .eh_bus_reset_handler   = sas_eh_bus_reset_handler,
 65         .target_destroy         = sas_target_destroy,
 66         .ioctl                  = sas_ioctl,
 67         .shost_attrs            = mvst_host_attrs,
 68         .track_queue_depth      = 1,
 69 };
 70 
 71 static struct sas_domain_function_template mvs_transport_ops = {
 72         .lldd_dev_found         = mvs_dev_found,
 73         .lldd_dev_gone          = mvs_dev_gone,
 74         .lldd_execute_task      = mvs_queue_command,
 75         .lldd_control_phy       = mvs_phy_control,
 76 
 77         .lldd_abort_task        = mvs_abort_task,
 78         .lldd_abort_task_set    = mvs_abort_task_set,
 79         .lldd_clear_aca         = mvs_clear_aca,
 80         .lldd_clear_task_set    = mvs_clear_task_set,
 81         .lldd_I_T_nexus_reset   = mvs_I_T_nexus_reset,
 82         .lldd_lu_reset          = mvs_lu_reset,
 83         .lldd_query_task        = mvs_query_task,
 84         .lldd_port_formed       = mvs_port_formed,
 85         .lldd_port_deformed     = mvs_port_deformed,
 86 
 87 };
 88 
 89 static void mvs_phy_init(struct mvs_info *mvi, int phy_id)
 90 {
 91         struct mvs_phy *phy = &mvi->phy[phy_id];
 92         struct asd_sas_phy *sas_phy = &phy->sas_phy;
 93 
 94         phy->mvi = mvi;
 95         phy->port = NULL;
 96         init_timer(&phy->timer);
 97         sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0;
 98         sas_phy->class = SAS;
 99         sas_phy->iproto = SAS_PROTOCOL_ALL;
100         sas_phy->tproto = 0;
101         sas_phy->type = PHY_TYPE_PHYSICAL;
102         sas_phy->role = PHY_ROLE_INITIATOR;
103         sas_phy->oob_mode = OOB_NOT_CONNECTED;
104         sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
105 
106         sas_phy->id = phy_id;
107         sas_phy->sas_addr = &mvi->sas_addr[0];
108         sas_phy->frame_rcvd = &phy->frame_rcvd[0];
109         sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata;
110         sas_phy->lldd_phy = phy;
111 }
112 
113 static void mvs_free(struct mvs_info *mvi)
114 {
115         struct mvs_wq *mwq;
116         int slot_nr;
117 
118         if (!mvi)
119                 return;
120 
121         if (mvi->flags & MVF_FLAG_SOC)
122                 slot_nr = MVS_SOC_SLOTS;
123         else
124                 slot_nr = MVS_CHIP_SLOT_SZ;
125 
126         if (mvi->dma_pool)
127                 pci_pool_destroy(mvi->dma_pool);
128 
129         if (mvi->tx)
130                 dma_free_coherent(mvi->dev,
131                                   sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
132                                   mvi->tx, mvi->tx_dma);
133         if (mvi->rx_fis)
134                 dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ,
135                                   mvi->rx_fis, mvi->rx_fis_dma);
136         if (mvi->rx)
137                 dma_free_coherent(mvi->dev,
138                                   sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
139                                   mvi->rx, mvi->rx_dma);
140         if (mvi->slot)
141                 dma_free_coherent(mvi->dev,
142                                   sizeof(*mvi->slot) * slot_nr,
143                                   mvi->slot, mvi->slot_dma);
144 
145         if (mvi->bulk_buffer)
146                 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
147                                   mvi->bulk_buffer, mvi->bulk_buffer_dma);
148         if (mvi->bulk_buffer1)
149                 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
150                                   mvi->bulk_buffer1, mvi->bulk_buffer_dma1);
151 
152         MVS_CHIP_DISP->chip_iounmap(mvi);
153         if (mvi->shost)
154                 scsi_host_put(mvi->shost);
155         list_for_each_entry(mwq, &mvi->wq_list, entry)
156                 cancel_delayed_work(&mwq->work_q);
157         kfree(mvi->tags);
158         kfree(mvi);
159 }
160 
161 #ifdef CONFIG_SCSI_MVSAS_TASKLET
162 static void mvs_tasklet(unsigned long opaque)
163 {
164         u32 stat;
165         u16 core_nr, i = 0;
166 
167         struct mvs_info *mvi;
168         struct sas_ha_struct *sha = (struct sas_ha_struct *)opaque;
169 
170         core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
171         mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
172 
173         if (unlikely(!mvi))
174                 BUG_ON(1);
175 
176         stat = MVS_CHIP_DISP->isr_status(mvi, mvi->pdev->irq);
177         if (!stat)
178                 goto out;
179 
180         for (i = 0; i < core_nr; i++) {
181                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
182                 MVS_CHIP_DISP->isr(mvi, mvi->pdev->irq, stat);
183         }
184 out:
185         MVS_CHIP_DISP->interrupt_enable(mvi);
186 
187 }
188 #endif
189 
190 static irqreturn_t mvs_interrupt(int irq, void *opaque)
191 {
192         u32 core_nr;
193         u32 stat;
194         struct mvs_info *mvi;
195         struct sas_ha_struct *sha = opaque;
196 #ifndef CONFIG_SCSI_MVSAS_TASKLET
197         u32 i;
198 #endif
199 
200         core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
201         mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
202 
203         if (unlikely(!mvi))
204                 return IRQ_NONE;
205 #ifdef CONFIG_SCSI_MVSAS_TASKLET
206         MVS_CHIP_DISP->interrupt_disable(mvi);
207 #endif
208 
209         stat = MVS_CHIP_DISP->isr_status(mvi, irq);
210         if (!stat) {
211         #ifdef CONFIG_SCSI_MVSAS_TASKLET
212                 MVS_CHIP_DISP->interrupt_enable(mvi);
213         #endif
214                 return IRQ_NONE;
215         }
216 
217 #ifdef CONFIG_SCSI_MVSAS_TASKLET
218         tasklet_schedule(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
219 #else
220         for (i = 0; i < core_nr; i++) {
221                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
222                 MVS_CHIP_DISP->isr(mvi, irq, stat);
223         }
224 #endif
225         return IRQ_HANDLED;
226 }
227 
228 static int mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost)
229 {
230         int i = 0, slot_nr;
231         char pool_name[32];
232 
233         if (mvi->flags & MVF_FLAG_SOC)
234                 slot_nr = MVS_SOC_SLOTS;
235         else
236                 slot_nr = MVS_CHIP_SLOT_SZ;
237 
238         spin_lock_init(&mvi->lock);
239         for (i = 0; i < mvi->chip->n_phy; i++) {
240                 mvs_phy_init(mvi, i);
241                 mvi->port[i].wide_port_phymap = 0;
242                 mvi->port[i].port_attached = 0;
243                 INIT_LIST_HEAD(&mvi->port[i].list);
244         }
245         for (i = 0; i < MVS_MAX_DEVICES; i++) {
246                 mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED;
247                 mvi->devices[i].dev_type = SAS_PHY_UNUSED;
248                 mvi->devices[i].device_id = i;
249                 mvi->devices[i].dev_status = MVS_DEV_NORMAL;
250                 init_timer(&mvi->devices[i].timer);
251         }
252 
253         /*
254          * alloc and init our DMA areas
255          */
256         mvi->tx = dma_alloc_coherent(mvi->dev,
257                                      sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
258                                      &mvi->tx_dma, GFP_KERNEL);
259         if (!mvi->tx)
260                 goto err_out;
261         memset(mvi->tx, 0, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ);
262         mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ,
263                                          &mvi->rx_fis_dma, GFP_KERNEL);
264         if (!mvi->rx_fis)
265                 goto err_out;
266         memset(mvi->rx_fis, 0, MVS_RX_FISL_SZ);
267 
268         mvi->rx = dma_alloc_coherent(mvi->dev,
269                                      sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
270                                      &mvi->rx_dma, GFP_KERNEL);
271         if (!mvi->rx)
272                 goto err_out;
273         memset(mvi->rx, 0, sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1));
274         mvi->rx[0] = cpu_to_le32(0xfff);
275         mvi->rx_cons = 0xfff;
276 
277         mvi->slot = dma_alloc_coherent(mvi->dev,
278                                        sizeof(*mvi->slot) * slot_nr,
279                                        &mvi->slot_dma, GFP_KERNEL);
280         if (!mvi->slot)
281                 goto err_out;
282         memset(mvi->slot, 0, sizeof(*mvi->slot) * slot_nr);
283 
284         mvi->bulk_buffer = dma_alloc_coherent(mvi->dev,
285                                        TRASH_BUCKET_SIZE,
286                                        &mvi->bulk_buffer_dma, GFP_KERNEL);
287         if (!mvi->bulk_buffer)
288                 goto err_out;
289 
290         mvi->bulk_buffer1 = dma_alloc_coherent(mvi->dev,
291                                        TRASH_BUCKET_SIZE,
292                                        &mvi->bulk_buffer_dma1, GFP_KERNEL);
293         if (!mvi->bulk_buffer1)
294                 goto err_out;
295 
296         sprintf(pool_name, "%s%d", "mvs_dma_pool", mvi->id);
297         mvi->dma_pool = pci_pool_create(pool_name, mvi->pdev, MVS_SLOT_BUF_SZ, 16, 0);
298         if (!mvi->dma_pool) {
299                         printk(KERN_DEBUG "failed to create dma pool %s.\n", pool_name);
300                         goto err_out;
301         }
302         mvi->tags_num = slot_nr;
303 
304         /* Initialize tags */
305         mvs_tag_init(mvi);
306         return 0;
307 err_out:
308         return 1;
309 }
310 
311 
312 int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex)
313 {
314         unsigned long res_start, res_len, res_flag, res_flag_ex = 0;
315         struct pci_dev *pdev = mvi->pdev;
316         if (bar_ex != -1) {
317                 /*
318                  * ioremap main and peripheral registers
319                  */
320                 res_start = pci_resource_start(pdev, bar_ex);
321                 res_len = pci_resource_len(pdev, bar_ex);
322                 if (!res_start || !res_len)
323                         goto err_out;
324 
325                 res_flag_ex = pci_resource_flags(pdev, bar_ex);
326                 if (res_flag_ex & IORESOURCE_MEM)
327                         mvi->regs_ex = ioremap(res_start, res_len);
328                 else
329                         mvi->regs_ex = (void *)res_start;
330                 if (!mvi->regs_ex)
331                         goto err_out;
332         }
333 
334         res_start = pci_resource_start(pdev, bar);
335         res_len = pci_resource_len(pdev, bar);
336         if (!res_start || !res_len) {
337                 iounmap(mvi->regs_ex);
338                 mvi->regs_ex = NULL;
339                 goto err_out;
340         }
341 
342         res_flag = pci_resource_flags(pdev, bar);
343         mvi->regs = ioremap(res_start, res_len);
344 
345         if (!mvi->regs) {
346                 if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM))
347                         iounmap(mvi->regs_ex);
348                 mvi->regs_ex = NULL;
349                 goto err_out;
350         }
351 
352         return 0;
353 err_out:
354         return -1;
355 }
356 
357 void mvs_iounmap(void __iomem *regs)
358 {
359         iounmap(regs);
360 }
361 
362 static struct mvs_info *mvs_pci_alloc(struct pci_dev *pdev,
363                                 const struct pci_device_id *ent,
364                                 struct Scsi_Host *shost, unsigned int id)
365 {
366         struct mvs_info *mvi = NULL;
367         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
368 
369         mvi = kzalloc(sizeof(*mvi) +
370                 (1L << mvs_chips[ent->driver_data].slot_width) *
371                 sizeof(struct mvs_slot_info), GFP_KERNEL);
372         if (!mvi)
373                 return NULL;
374 
375         mvi->pdev = pdev;
376         mvi->dev = &pdev->dev;
377         mvi->chip_id = ent->driver_data;
378         mvi->chip = &mvs_chips[mvi->chip_id];
379         INIT_LIST_HEAD(&mvi->wq_list);
380 
381         ((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi;
382         ((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy;
383 
384         mvi->id = id;
385         mvi->sas = sha;
386         mvi->shost = shost;
387 
388         mvi->tags = kzalloc(MVS_CHIP_SLOT_SZ>>3, GFP_KERNEL);
389         if (!mvi->tags)
390                 goto err_out;
391 
392         if (MVS_CHIP_DISP->chip_ioremap(mvi))
393                 goto err_out;
394         if (!mvs_alloc(mvi, shost))
395                 return mvi;
396 err_out:
397         mvs_free(mvi);
398         return NULL;
399 }
400 
401 static int pci_go_64(struct pci_dev *pdev)
402 {
403         int rc;
404 
405         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
406                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
407                 if (rc) {
408                         rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
409                         if (rc) {
410                                 dev_printk(KERN_ERR, &pdev->dev,
411                                            "64-bit DMA enable failed\n");
412                                 return rc;
413                         }
414                 }
415         } else {
416                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
417                 if (rc) {
418                         dev_printk(KERN_ERR, &pdev->dev,
419                                    "32-bit DMA enable failed\n");
420                         return rc;
421                 }
422                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
423                 if (rc) {
424                         dev_printk(KERN_ERR, &pdev->dev,
425                                    "32-bit consistent DMA enable failed\n");
426                         return rc;
427                 }
428         }
429 
430         return rc;
431 }
432 
433 static int mvs_prep_sas_ha_init(struct Scsi_Host *shost,
434                                 const struct mvs_chip_info *chip_info)
435 {
436         int phy_nr, port_nr; unsigned short core_nr;
437         struct asd_sas_phy **arr_phy;
438         struct asd_sas_port **arr_port;
439         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
440 
441         core_nr = chip_info->n_host;
442         phy_nr  = core_nr * chip_info->n_phy;
443         port_nr = phy_nr;
444 
445         memset(sha, 0x00, sizeof(struct sas_ha_struct));
446         arr_phy  = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
447         arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
448         if (!arr_phy || !arr_port)
449                 goto exit_free;
450 
451         sha->sas_phy = arr_phy;
452         sha->sas_port = arr_port;
453         sha->core.shost = shost;
454 
455         sha->lldd_ha = kzalloc(sizeof(struct mvs_prv_info), GFP_KERNEL);
456         if (!sha->lldd_ha)
457                 goto exit_free;
458 
459         ((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr;
460 
461         shost->transportt = mvs_stt;
462         shost->max_id = MVS_MAX_DEVICES;
463         shost->max_lun = ~0;
464         shost->max_channel = 1;
465         shost->max_cmd_len = 16;
466 
467         return 0;
468 exit_free:
469         kfree(arr_phy);
470         kfree(arr_port);
471         return -1;
472 
473 }
474 
475 static void  mvs_post_sas_ha_init(struct Scsi_Host *shost,
476                         const struct mvs_chip_info *chip_info)
477 {
478         int can_queue, i = 0, j = 0;
479         struct mvs_info *mvi = NULL;
480         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
481         unsigned short nr_core = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
482 
483         for (j = 0; j < nr_core; j++) {
484                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
485                 for (i = 0; i < chip_info->n_phy; i++) {
486                         sha->sas_phy[j * chip_info->n_phy  + i] =
487                                 &mvi->phy[i].sas_phy;
488                         sha->sas_port[j * chip_info->n_phy + i] =
489                                 &mvi->port[i].sas_port;
490                 }
491         }
492 
493         sha->sas_ha_name = DRV_NAME;
494         sha->dev = mvi->dev;
495         sha->lldd_module = THIS_MODULE;
496         sha->sas_addr = &mvi->sas_addr[0];
497 
498         sha->num_phys = nr_core * chip_info->n_phy;
499 
500         if (mvi->flags & MVF_FLAG_SOC)
501                 can_queue = MVS_SOC_CAN_QUEUE;
502         else
503                 can_queue = MVS_CHIP_SLOT_SZ;
504 
505         shost->sg_tablesize = min_t(u16, SG_ALL, MVS_MAX_SG);
506         shost->can_queue = can_queue;
507         mvi->shost->cmd_per_lun = MVS_QUEUE_SIZE;
508         sha->core.shost = mvi->shost;
509 }
510 
511 static void mvs_init_sas_add(struct mvs_info *mvi)
512 {
513         u8 i;
514         for (i = 0; i < mvi->chip->n_phy; i++) {
515                 mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL;
516                 mvi->phy[i].dev_sas_addr =
517                         cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr));
518         }
519 
520         memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE);
521 }
522 
523 static int mvs_pci_init(struct pci_dev *pdev, const struct pci_device_id *ent)
524 {
525         unsigned int rc, nhost = 0;
526         struct mvs_info *mvi;
527         struct mvs_prv_info *mpi;
528         irq_handler_t irq_handler = mvs_interrupt;
529         struct Scsi_Host *shost = NULL;
530         const struct mvs_chip_info *chip;
531 
532         dev_printk(KERN_INFO, &pdev->dev,
533                 "mvsas: driver version %s\n", DRV_VERSION);
534         rc = pci_enable_device(pdev);
535         if (rc)
536                 goto err_out_enable;
537 
538         pci_set_master(pdev);
539 
540         rc = pci_request_regions(pdev, DRV_NAME);
541         if (rc)
542                 goto err_out_disable;
543 
544         rc = pci_go_64(pdev);
545         if (rc)
546                 goto err_out_regions;
547 
548         shost = scsi_host_alloc(&mvs_sht, sizeof(void *));
549         if (!shost) {
550                 rc = -ENOMEM;
551                 goto err_out_regions;
552         }
553 
554         chip = &mvs_chips[ent->driver_data];
555         SHOST_TO_SAS_HA(shost) =
556                 kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL);
557         if (!SHOST_TO_SAS_HA(shost)) {
558                 kfree(shost);
559                 rc = -ENOMEM;
560                 goto err_out_regions;
561         }
562 
563         rc = mvs_prep_sas_ha_init(shost, chip);
564         if (rc) {
565                 kfree(shost);
566                 rc = -ENOMEM;
567                 goto err_out_regions;
568         }
569 
570         pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
571 
572         do {
573                 mvi = mvs_pci_alloc(pdev, ent, shost, nhost);
574                 if (!mvi) {
575                         rc = -ENOMEM;
576                         goto err_out_regions;
577                 }
578 
579                 memset(&mvi->hba_info_param, 0xFF,
580                         sizeof(struct hba_info_page));
581 
582                 mvs_init_sas_add(mvi);
583 
584                 mvi->instance = nhost;
585                 rc = MVS_CHIP_DISP->chip_init(mvi);
586                 if (rc) {
587                         mvs_free(mvi);
588                         goto err_out_regions;
589                 }
590                 nhost++;
591         } while (nhost < chip->n_host);
592         mpi = (struct mvs_prv_info *)(SHOST_TO_SAS_HA(shost)->lldd_ha);
593 #ifdef CONFIG_SCSI_MVSAS_TASKLET
594         tasklet_init(&(mpi->mv_tasklet), mvs_tasklet,
595                      (unsigned long)SHOST_TO_SAS_HA(shost));
596 #endif
597 
598         mvs_post_sas_ha_init(shost, chip);
599 
600         rc = scsi_add_host(shost, &pdev->dev);
601         if (rc)
602                 goto err_out_shost;
603 
604         rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
605         if (rc)
606                 goto err_out_shost;
607         rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED,
608                 DRV_NAME, SHOST_TO_SAS_HA(shost));
609         if (rc)
610                 goto err_not_sas;
611 
612         MVS_CHIP_DISP->interrupt_enable(mvi);
613 
614         scsi_scan_host(mvi->shost);
615 
616         return 0;
617 
618 err_not_sas:
619         sas_unregister_ha(SHOST_TO_SAS_HA(shost));
620 err_out_shost:
621         scsi_remove_host(mvi->shost);
622 err_out_regions:
623         pci_release_regions(pdev);
624 err_out_disable:
625         pci_disable_device(pdev);
626 err_out_enable:
627         return rc;
628 }
629 
630 static void mvs_pci_remove(struct pci_dev *pdev)
631 {
632         unsigned short core_nr, i = 0;
633         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
634         struct mvs_info *mvi = NULL;
635 
636         core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
637         mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
638 
639 #ifdef CONFIG_SCSI_MVSAS_TASKLET
640         tasklet_kill(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
641 #endif
642 
643         scsi_remove_host(mvi->shost);
644         sas_unregister_ha(sha);
645         sas_remove_host(mvi->shost);
646 
647         MVS_CHIP_DISP->interrupt_disable(mvi);
648         free_irq(mvi->pdev->irq, sha);
649         for (i = 0; i < core_nr; i++) {
650                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
651                 mvs_free(mvi);
652         }
653         kfree(sha->sas_phy);
654         kfree(sha->sas_port);
655         kfree(sha);
656         pci_release_regions(pdev);
657         pci_disable_device(pdev);
658         return;
659 }
660 
661 static struct pci_device_id mvs_pci_table[] = {
662         { PCI_VDEVICE(MARVELL, 0x6320), chip_6320 },
663         { PCI_VDEVICE(MARVELL, 0x6340), chip_6440 },
664         {
665                 .vendor         = PCI_VENDOR_ID_MARVELL,
666                 .device         = 0x6440,
667                 .subvendor      = PCI_ANY_ID,
668                 .subdevice      = 0x6480,
669                 .class          = 0,
670                 .class_mask     = 0,
671                 .driver_data    = chip_6485,
672         },
673         { PCI_VDEVICE(MARVELL, 0x6440), chip_6440 },
674         { PCI_VDEVICE(MARVELL, 0x6485), chip_6485 },
675         { PCI_VDEVICE(MARVELL, 0x9480), chip_9480 },
676         { PCI_VDEVICE(MARVELL, 0x9180), chip_9180 },
677         { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1300), chip_1300 },
678         { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1320), chip_1320 },
679         { PCI_VDEVICE(ADAPTEC2, 0x0450), chip_6440 },
680         { PCI_VDEVICE(TTI, 0x2710), chip_9480 },
681         { PCI_VDEVICE(TTI, 0x2720), chip_9480 },
682         { PCI_VDEVICE(TTI, 0x2721), chip_9480 },
683         { PCI_VDEVICE(TTI, 0x2722), chip_9480 },
684         { PCI_VDEVICE(TTI, 0x2740), chip_9480 },
685         { PCI_VDEVICE(TTI, 0x2744), chip_9480 },
686         { PCI_VDEVICE(TTI, 0x2760), chip_9480 },
687         {
688                 .vendor         = PCI_VENDOR_ID_MARVELL_EXT,
689                 .device         = 0x9480,
690                 .subvendor      = PCI_ANY_ID,
691                 .subdevice      = 0x9480,
692                 .class          = 0,
693                 .class_mask     = 0,
694                 .driver_data    = chip_9480,
695         },
696         {
697                 .vendor         = PCI_VENDOR_ID_MARVELL_EXT,
698                 .device         = 0x9445,
699                 .subvendor      = PCI_ANY_ID,
700                 .subdevice      = 0x9480,
701                 .class          = 0,
702                 .class_mask     = 0,
703                 .driver_data    = chip_9445,
704         },
705         {
706                 .vendor         = PCI_VENDOR_ID_MARVELL_EXT,
707                 .device         = 0x9485,
708                 .subvendor      = PCI_ANY_ID,
709                 .subdevice      = 0x9480,
710                 .class          = 0,
711                 .class_mask     = 0,
712                 .driver_data    = chip_9485,
713         },
714         {
715                 .vendor         = PCI_VENDOR_ID_MARVELL_EXT,
716                 .device         = 0x9485,
717                 .subvendor      = PCI_ANY_ID,
718                 .subdevice      = 0x9485,
719                 .class          = 0,
720                 .class_mask     = 0,
721                 .driver_data    = chip_9485,
722         },
723         { PCI_VDEVICE(OCZ, 0x1021), chip_9485}, /* OCZ RevoDrive3 */
724         { PCI_VDEVICE(OCZ, 0x1022), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
725         { PCI_VDEVICE(OCZ, 0x1040), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
726         { PCI_VDEVICE(OCZ, 0x1041), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
727         { PCI_VDEVICE(OCZ, 0x1042), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
728         { PCI_VDEVICE(OCZ, 0x1043), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
729         { PCI_VDEVICE(OCZ, 0x1044), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
730         { PCI_VDEVICE(OCZ, 0x1080), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
731         { PCI_VDEVICE(OCZ, 0x1083), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
732         { PCI_VDEVICE(OCZ, 0x1084), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
733 
734         { }     /* terminate list */
735 };
736 
737 static struct pci_driver mvs_pci_driver = {
738         .name           = DRV_NAME,
739         .id_table       = mvs_pci_table,
740         .probe          = mvs_pci_init,
741         .remove         = mvs_pci_remove,
742 };
743 
744 static ssize_t
745 mvs_show_driver_version(struct device *cdev,
746                 struct device_attribute *attr,  char *buffer)
747 {
748         return snprintf(buffer, PAGE_SIZE, "%s\n", DRV_VERSION);
749 }
750 
751 static DEVICE_ATTR(driver_version,
752                          S_IRUGO,
753                          mvs_show_driver_version,
754                          NULL);
755 
756 static ssize_t
757 mvs_store_interrupt_coalescing(struct device *cdev,
758                         struct device_attribute *attr,
759                         const char *buffer, size_t size)
760 {
761         unsigned int val = 0;
762         struct mvs_info *mvi = NULL;
763         struct Scsi_Host *shost = class_to_shost(cdev);
764         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
765         u8 i, core_nr;
766         if (buffer == NULL)
767                 return size;
768 
769         if (sscanf(buffer, "%u", &val) != 1)
770                 return -EINVAL;
771 
772         if (val >= 0x10000) {
773                 mv_dprintk("interrupt coalescing timer %d us is"
774                         "too long\n", val);
775                 return strlen(buffer);
776         }
777 
778         interrupt_coalescing = val;
779 
780         core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
781         mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
782 
783         if (unlikely(!mvi))
784                 return -EINVAL;
785 
786         for (i = 0; i < core_nr; i++) {
787                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
788                 if (MVS_CHIP_DISP->tune_interrupt)
789                         MVS_CHIP_DISP->tune_interrupt(mvi,
790                                 interrupt_coalescing);
791         }
792         mv_dprintk("set interrupt coalescing time to %d us\n",
793                 interrupt_coalescing);
794         return strlen(buffer);
795 }
796 
797 static ssize_t mvs_show_interrupt_coalescing(struct device *cdev,
798                         struct device_attribute *attr, char *buffer)
799 {
800         return snprintf(buffer, PAGE_SIZE, "%d\n", interrupt_coalescing);
801 }
802 
803 static DEVICE_ATTR(interrupt_coalescing,
804                          S_IRUGO|S_IWUSR,
805                          mvs_show_interrupt_coalescing,
806                          mvs_store_interrupt_coalescing);
807 
808 /* task handler */
809 struct task_struct *mvs_th;
810 static int __init mvs_init(void)
811 {
812         int rc;
813         mvs_stt = sas_domain_attach_transport(&mvs_transport_ops);
814         if (!mvs_stt)
815                 return -ENOMEM;
816 
817         rc = pci_register_driver(&mvs_pci_driver);
818         if (rc)
819                 goto err_out;
820 
821         return 0;
822 
823 err_out:
824         sas_release_transport(mvs_stt);
825         return rc;
826 }
827 
828 static void __exit mvs_exit(void)
829 {
830         pci_unregister_driver(&mvs_pci_driver);
831         sas_release_transport(mvs_stt);
832 }
833 
834 struct device_attribute *mvst_host_attrs[] = {
835         &dev_attr_driver_version,
836         &dev_attr_interrupt_coalescing,
837         NULL,
838 };
839 
840 module_init(mvs_init);
841 module_exit(mvs_exit);
842 
843 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
844 MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver");
845 MODULE_VERSION(DRV_VERSION);
846 MODULE_LICENSE("GPL");
847 #ifdef CONFIG_PCI
848 MODULE_DEVICE_TABLE(pci, mvs_pci_table);
849 #endif
850 

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