Version:  2.0.40 2.2.26 2.4.37 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6

Linux/drivers/scsi/advansys.c

  1 /*
  2  * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
  3  *
  4  * Copyright (c) 1995-2000 Advanced System Products, Inc.
  5  * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
  6  * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
  7  * Copyright (c) 2014 Hannes Reinecke <hare@suse.de>
  8  * All Rights Reserved.
  9  *
 10  * This program is free software; you can redistribute it and/or modify
 11  * it under the terms of the GNU General Public License as published by
 12  * the Free Software Foundation; either version 2 of the License, or
 13  * (at your option) any later version.
 14  */
 15 
 16 /*
 17  * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
 18  * changed its name to ConnectCom Solutions, Inc.
 19  * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
 20  */
 21 
 22 #include <linux/module.h>
 23 #include <linux/string.h>
 24 #include <linux/kernel.h>
 25 #include <linux/types.h>
 26 #include <linux/ioport.h>
 27 #include <linux/interrupt.h>
 28 #include <linux/delay.h>
 29 #include <linux/slab.h>
 30 #include <linux/mm.h>
 31 #include <linux/proc_fs.h>
 32 #include <linux/init.h>
 33 #include <linux/blkdev.h>
 34 #include <linux/isa.h>
 35 #include <linux/eisa.h>
 36 #include <linux/pci.h>
 37 #include <linux/spinlock.h>
 38 #include <linux/dma-mapping.h>
 39 #include <linux/firmware.h>
 40 #include <linux/dmapool.h>
 41 
 42 #include <asm/io.h>
 43 #include <asm/dma.h>
 44 
 45 #include <scsi/scsi_cmnd.h>
 46 #include <scsi/scsi_device.h>
 47 #include <scsi/scsi_tcq.h>
 48 #include <scsi/scsi.h>
 49 #include <scsi/scsi_host.h>
 50 
 51 #define DRV_NAME "advansys"
 52 #define ASC_VERSION "3.5"       /* AdvanSys Driver Version */
 53 
 54 /* FIXME:
 55  *
 56  *  1. Use scsi_transport_spi
 57  *  2. advansys_info is not safe against multiple simultaneous callers
 58  *  3. Add module_param to override ISA/VLB ioport array
 59  */
 60 
 61 /* Enable driver /proc statistics. */
 62 #define ADVANSYS_STATS
 63 
 64 /* Enable driver tracing. */
 65 #undef ADVANSYS_DEBUG
 66 
 67 typedef unsigned char uchar;
 68 
 69 #define isodd_word(val)   ((((uint)val) & (uint)0x0001) != 0)
 70 
 71 #define PCI_VENDOR_ID_ASP               0x10cd
 72 #define PCI_DEVICE_ID_ASP_1200A         0x1100
 73 #define PCI_DEVICE_ID_ASP_ABP940        0x1200
 74 #define PCI_DEVICE_ID_ASP_ABP940U       0x1300
 75 #define PCI_DEVICE_ID_ASP_ABP940UW      0x2300
 76 #define PCI_DEVICE_ID_38C0800_REV1      0x2500
 77 #define PCI_DEVICE_ID_38C1600_REV1      0x2700
 78 
 79 #define PortAddr                 unsigned int   /* port address size  */
 80 #define inp(port)                inb(port)
 81 #define outp(port, byte)         outb((byte), (port))
 82 
 83 #define inpw(port)               inw(port)
 84 #define outpw(port, word)        outw((word), (port))
 85 
 86 #define ASC_MAX_SG_QUEUE    7
 87 #define ASC_MAX_SG_LIST     255
 88 
 89 #define ASC_CS_TYPE  unsigned short
 90 
 91 #define ASC_IS_ISA          (0x0001)
 92 #define ASC_IS_ISAPNP       (0x0081)
 93 #define ASC_IS_EISA         (0x0002)
 94 #define ASC_IS_PCI          (0x0004)
 95 #define ASC_IS_PCI_ULTRA    (0x0104)
 96 #define ASC_IS_PCMCIA       (0x0008)
 97 #define ASC_IS_MCA          (0x0020)
 98 #define ASC_IS_VL           (0x0040)
 99 #define ASC_IS_WIDESCSI_16  (0x0100)
100 #define ASC_IS_WIDESCSI_32  (0x0200)
101 #define ASC_IS_BIG_ENDIAN   (0x8000)
102 
103 #define ASC_CHIP_MIN_VER_VL      (0x01)
104 #define ASC_CHIP_MAX_VER_VL      (0x07)
105 #define ASC_CHIP_MIN_VER_PCI     (0x09)
106 #define ASC_CHIP_MAX_VER_PCI     (0x0F)
107 #define ASC_CHIP_VER_PCI_BIT     (0x08)
108 #define ASC_CHIP_MIN_VER_ISA     (0x11)
109 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
110 #define ASC_CHIP_MAX_VER_ISA     (0x27)
111 #define ASC_CHIP_VER_ISA_BIT     (0x30)
112 #define ASC_CHIP_VER_ISAPNP_BIT  (0x20)
113 #define ASC_CHIP_VER_ASYN_BUG    (0x21)
114 #define ASC_CHIP_VER_PCI             0x08
115 #define ASC_CHIP_VER_PCI_ULTRA_3150  (ASC_CHIP_VER_PCI | 0x02)
116 #define ASC_CHIP_VER_PCI_ULTRA_3050  (ASC_CHIP_VER_PCI | 0x03)
117 #define ASC_CHIP_MIN_VER_EISA (0x41)
118 #define ASC_CHIP_MAX_VER_EISA (0x47)
119 #define ASC_CHIP_VER_EISA_BIT (0x40)
120 #define ASC_CHIP_LATEST_VER_EISA   ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
121 #define ASC_MAX_VL_DMA_COUNT    (0x07FFFFFFL)
122 #define ASC_MAX_PCI_DMA_COUNT   (0xFFFFFFFFL)
123 #define ASC_MAX_ISA_DMA_COUNT   (0x00FFFFFFL)
124 
125 #define ASC_SCSI_ID_BITS  3
126 #define ASC_SCSI_TIX_TYPE     uchar
127 #define ASC_ALL_DEVICE_BIT_SET  0xFF
128 #define ASC_SCSI_BIT_ID_TYPE  uchar
129 #define ASC_MAX_TID       7
130 #define ASC_MAX_LUN       7
131 #define ASC_SCSI_WIDTH_BIT_SET  0xFF
132 #define ASC_MAX_SENSE_LEN   32
133 #define ASC_MIN_SENSE_LEN   14
134 #define ASC_SCSI_RESET_HOLD_TIME_US  60
135 
136 /*
137  * Narrow boards only support 12-byte commands, while wide boards
138  * extend to 16-byte commands.
139  */
140 #define ASC_MAX_CDB_LEN     12
141 #define ADV_MAX_CDB_LEN     16
142 
143 #define MS_SDTR_LEN    0x03
144 #define MS_WDTR_LEN    0x02
145 
146 #define ASC_SG_LIST_PER_Q   7
147 #define QS_FREE        0x00
148 #define QS_READY       0x01
149 #define QS_DISC1       0x02
150 #define QS_DISC2       0x04
151 #define QS_BUSY        0x08
152 #define QS_ABORTED     0x40
153 #define QS_DONE        0x80
154 #define QC_NO_CALLBACK   0x01
155 #define QC_SG_SWAP_QUEUE 0x02
156 #define QC_SG_HEAD       0x04
157 #define QC_DATA_IN       0x08
158 #define QC_DATA_OUT      0x10
159 #define QC_URGENT        0x20
160 #define QC_MSG_OUT       0x40
161 #define QC_REQ_SENSE     0x80
162 #define QCSG_SG_XFER_LIST  0x02
163 #define QCSG_SG_XFER_MORE  0x04
164 #define QCSG_SG_XFER_END   0x08
165 #define QD_IN_PROGRESS       0x00
166 #define QD_NO_ERROR          0x01
167 #define QD_ABORTED_BY_HOST   0x02
168 #define QD_WITH_ERROR        0x04
169 #define QD_INVALID_REQUEST   0x80
170 #define QD_INVALID_HOST_NUM  0x81
171 #define QD_INVALID_DEVICE    0x82
172 #define QD_ERR_INTERNAL      0xFF
173 #define QHSTA_NO_ERROR               0x00
174 #define QHSTA_M_SEL_TIMEOUT          0x11
175 #define QHSTA_M_DATA_OVER_RUN        0x12
176 #define QHSTA_M_DATA_UNDER_RUN       0x12
177 #define QHSTA_M_UNEXPECTED_BUS_FREE  0x13
178 #define QHSTA_M_BAD_BUS_PHASE_SEQ    0x14
179 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
180 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET  0x22
181 #define QHSTA_D_HOST_ABORT_FAILED       0x23
182 #define QHSTA_D_EXE_SCSI_Q_FAILED       0x24
183 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
184 #define QHSTA_D_ASPI_NO_BUF_POOL        0x26
185 #define QHSTA_M_WTM_TIMEOUT         0x41
186 #define QHSTA_M_BAD_CMPL_STATUS_IN  0x42
187 #define QHSTA_M_NO_AUTO_REQ_SENSE   0x43
188 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
189 #define QHSTA_M_TARGET_STATUS_BUSY  0x45
190 #define QHSTA_M_BAD_TAG_CODE        0x46
191 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY  0x47
192 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
193 #define QHSTA_D_LRAM_CMP_ERROR        0x81
194 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
195 #define ASC_FLAG_SCSIQ_REQ        0x01
196 #define ASC_FLAG_BIOS_SCSIQ_REQ   0x02
197 #define ASC_FLAG_BIOS_ASYNC_IO    0x04
198 #define ASC_FLAG_SRB_LINEAR_ADDR  0x08
199 #define ASC_FLAG_WIN16            0x10
200 #define ASC_FLAG_WIN32            0x20
201 #define ASC_FLAG_ISA_OVER_16MB    0x40
202 #define ASC_FLAG_DOS_VM_CALLBACK  0x80
203 #define ASC_TAG_FLAG_EXTRA_BYTES               0x10
204 #define ASC_TAG_FLAG_DISABLE_DISCONNECT        0x04
205 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX  0x08
206 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
207 #define ASC_SCSIQ_CPY_BEG              4
208 #define ASC_SCSIQ_SGHD_CPY_BEG         2
209 #define ASC_SCSIQ_B_FWD                0
210 #define ASC_SCSIQ_B_BWD                1
211 #define ASC_SCSIQ_B_STATUS             2
212 #define ASC_SCSIQ_B_QNO                3
213 #define ASC_SCSIQ_B_CNTL               4
214 #define ASC_SCSIQ_B_SG_QUEUE_CNT       5
215 #define ASC_SCSIQ_D_DATA_ADDR          8
216 #define ASC_SCSIQ_D_DATA_CNT          12
217 #define ASC_SCSIQ_B_SENSE_LEN         20
218 #define ASC_SCSIQ_DONE_INFO_BEG       22
219 #define ASC_SCSIQ_D_SRBPTR            22
220 #define ASC_SCSIQ_B_TARGET_IX         26
221 #define ASC_SCSIQ_B_CDB_LEN           28
222 #define ASC_SCSIQ_B_TAG_CODE          29
223 #define ASC_SCSIQ_W_VM_ID             30
224 #define ASC_SCSIQ_DONE_STATUS         32
225 #define ASC_SCSIQ_HOST_STATUS         33
226 #define ASC_SCSIQ_SCSI_STATUS         34
227 #define ASC_SCSIQ_CDB_BEG             36
228 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
229 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT  60
230 #define ASC_SCSIQ_B_FIRST_SG_WK_QP    48
231 #define ASC_SCSIQ_B_SG_WK_QP          49
232 #define ASC_SCSIQ_B_SG_WK_IX          50
233 #define ASC_SCSIQ_W_ALT_DC1           52
234 #define ASC_SCSIQ_B_LIST_CNT          6
235 #define ASC_SCSIQ_B_CUR_LIST_CNT      7
236 #define ASC_SGQ_B_SG_CNTL             4
237 #define ASC_SGQ_B_SG_HEAD_QP          5
238 #define ASC_SGQ_B_SG_LIST_CNT         6
239 #define ASC_SGQ_B_SG_CUR_LIST_CNT     7
240 #define ASC_SGQ_LIST_BEG              8
241 #define ASC_DEF_SCSI1_QNG    4
242 #define ASC_MAX_SCSI1_QNG    4
243 #define ASC_DEF_SCSI2_QNG    16
244 #define ASC_MAX_SCSI2_QNG    32
245 #define ASC_TAG_CODE_MASK    0x23
246 #define ASC_STOP_REQ_RISC_STOP      0x01
247 #define ASC_STOP_ACK_RISC_STOP      0x03
248 #define ASC_STOP_CLEAN_UP_BUSY_Q    0x10
249 #define ASC_STOP_CLEAN_UP_DISC_Q    0x20
250 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
251 #define ASC_TIDLUN_TO_IX(tid, lun)  (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
252 #define ASC_TID_TO_TARGET_ID(tid)   (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
253 #define ASC_TIX_TO_TARGET_ID(tix)   (0x01 << ((tix) & ASC_MAX_TID))
254 #define ASC_TIX_TO_TID(tix)         ((tix) & ASC_MAX_TID)
255 #define ASC_TID_TO_TIX(tid)         ((tid) & ASC_MAX_TID)
256 #define ASC_TIX_TO_LUN(tix)         (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
257 #define ASC_QNO_TO_QADDR(q_no)      ((ASC_QADR_BEG)+((int)(q_no) << 6))
258 
259 typedef struct asc_scsiq_1 {
260         uchar status;
261         uchar q_no;
262         uchar cntl;
263         uchar sg_queue_cnt;
264         uchar target_id;
265         uchar target_lun;
266         __le32 data_addr;
267         __le32 data_cnt;
268         __le32 sense_addr;
269         uchar sense_len;
270         uchar extra_bytes;
271 } ASC_SCSIQ_1;
272 
273 typedef struct asc_scsiq_2 {
274         u32 srb_tag;
275         uchar target_ix;
276         uchar flag;
277         uchar cdb_len;
278         uchar tag_code;
279         ushort vm_id;
280 } ASC_SCSIQ_2;
281 
282 typedef struct asc_scsiq_3 {
283         uchar done_stat;
284         uchar host_stat;
285         uchar scsi_stat;
286         uchar scsi_msg;
287 } ASC_SCSIQ_3;
288 
289 typedef struct asc_scsiq_4 {
290         uchar cdb[ASC_MAX_CDB_LEN];
291         uchar y_first_sg_list_qp;
292         uchar y_working_sg_qp;
293         uchar y_working_sg_ix;
294         uchar y_res;
295         ushort x_req_count;
296         ushort x_reconnect_rtn;
297         __le32 x_saved_data_addr;
298         __le32 x_saved_data_cnt;
299 } ASC_SCSIQ_4;
300 
301 typedef struct asc_q_done_info {
302         ASC_SCSIQ_2 d2;
303         ASC_SCSIQ_3 d3;
304         uchar q_status;
305         uchar q_no;
306         uchar cntl;
307         uchar sense_len;
308         uchar extra_bytes;
309         uchar res;
310         u32 remain_bytes;
311 } ASC_QDONE_INFO;
312 
313 typedef struct asc_sg_list {
314         __le32 addr;
315         __le32 bytes;
316 } ASC_SG_LIST;
317 
318 typedef struct asc_sg_head {
319         ushort entry_cnt;
320         ushort queue_cnt;
321         ushort entry_to_copy;
322         ushort res;
323         ASC_SG_LIST sg_list[0];
324 } ASC_SG_HEAD;
325 
326 typedef struct asc_scsi_q {
327         ASC_SCSIQ_1 q1;
328         ASC_SCSIQ_2 q2;
329         uchar *cdbptr;
330         ASC_SG_HEAD *sg_head;
331         ushort remain_sg_entry_cnt;
332         ushort next_sg_index;
333 } ASC_SCSI_Q;
334 
335 typedef struct asc_scsi_bios_req_q {
336         ASC_SCSIQ_1 r1;
337         ASC_SCSIQ_2 r2;
338         uchar *cdbptr;
339         ASC_SG_HEAD *sg_head;
340         uchar *sense_ptr;
341         ASC_SCSIQ_3 r3;
342         uchar cdb[ASC_MAX_CDB_LEN];
343         uchar sense[ASC_MIN_SENSE_LEN];
344 } ASC_SCSI_BIOS_REQ_Q;
345 
346 typedef struct asc_risc_q {
347         uchar fwd;
348         uchar bwd;
349         ASC_SCSIQ_1 i1;
350         ASC_SCSIQ_2 i2;
351         ASC_SCSIQ_3 i3;
352         ASC_SCSIQ_4 i4;
353 } ASC_RISC_Q;
354 
355 typedef struct asc_sg_list_q {
356         uchar seq_no;
357         uchar q_no;
358         uchar cntl;
359         uchar sg_head_qp;
360         uchar sg_list_cnt;
361         uchar sg_cur_list_cnt;
362 } ASC_SG_LIST_Q;
363 
364 typedef struct asc_risc_sg_list_q {
365         uchar fwd;
366         uchar bwd;
367         ASC_SG_LIST_Q sg;
368         ASC_SG_LIST sg_list[7];
369 } ASC_RISC_SG_LIST_Q;
370 
371 #define ASCQ_ERR_Q_STATUS             0x0D
372 #define ASCQ_ERR_CUR_QNG              0x17
373 #define ASCQ_ERR_SG_Q_LINKS           0x18
374 #define ASCQ_ERR_ISR_RE_ENTRY         0x1A
375 #define ASCQ_ERR_CRITICAL_RE_ENTRY    0x1B
376 #define ASCQ_ERR_ISR_ON_CRITICAL      0x1C
377 
378 /*
379  * Warning code values are set in ASC_DVC_VAR  'warn_code'.
380  */
381 #define ASC_WARN_NO_ERROR             0x0000
382 #define ASC_WARN_IO_PORT_ROTATE       0x0001
383 #define ASC_WARN_EEPROM_CHKSUM        0x0002
384 #define ASC_WARN_IRQ_MODIFIED         0x0004
385 #define ASC_WARN_AUTO_CONFIG          0x0008
386 #define ASC_WARN_CMD_QNG_CONFLICT     0x0010
387 #define ASC_WARN_EEPROM_RECOVER       0x0020
388 #define ASC_WARN_CFG_MSW_RECOVER      0x0040
389 
390 /*
391  * Error code values are set in {ASC/ADV}_DVC_VAR  'err_code'.
392  */
393 #define ASC_IERR_NO_CARRIER             0x0001  /* No more carrier memory */
394 #define ASC_IERR_MCODE_CHKSUM           0x0002  /* micro code check sum error */
395 #define ASC_IERR_SET_PC_ADDR            0x0004
396 #define ASC_IERR_START_STOP_CHIP        0x0008  /* start/stop chip failed */
397 #define ASC_IERR_ILLEGAL_CONNECTION     0x0010  /* Illegal cable connection */
398 #define ASC_IERR_SINGLE_END_DEVICE      0x0020  /* SE device on DIFF bus */
399 #define ASC_IERR_REVERSED_CABLE         0x0040  /* Narrow flat cable reversed */
400 #define ASC_IERR_SET_SCSI_ID            0x0080  /* set SCSI ID failed */
401 #define ASC_IERR_HVD_DEVICE             0x0100  /* HVD device on LVD port */
402 #define ASC_IERR_BAD_SIGNATURE          0x0200  /* signature not found */
403 #define ASC_IERR_NO_BUS_TYPE            0x0400
404 #define ASC_IERR_BIST_PRE_TEST          0x0800  /* BIST pre-test error */
405 #define ASC_IERR_BIST_RAM_TEST          0x1000  /* BIST RAM test error */
406 #define ASC_IERR_BAD_CHIPTYPE           0x2000  /* Invalid chip_type setting */
407 
408 #define ASC_DEF_MAX_TOTAL_QNG   (0xF0)
409 #define ASC_MIN_TAG_Q_PER_DVC   (0x04)
410 #define ASC_MIN_FREE_Q        (0x02)
411 #define ASC_MIN_TOTAL_QNG     ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
412 #define ASC_MAX_TOTAL_QNG 240
413 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
414 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG   8
415 #define ASC_MAX_PCI_INRAM_TOTAL_QNG  20
416 #define ASC_MAX_INRAM_TAG_QNG   16
417 #define ASC_IOADR_GAP   0x10
418 #define ASC_SYN_MAX_OFFSET         0x0F
419 #define ASC_DEF_SDTR_OFFSET        0x0F
420 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX  0x02
421 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
422 
423 /* The narrow chip only supports a limited selection of transfer rates.
424  * These are encoded in the range 0..7 or 0..15 depending whether the chip
425  * is Ultra-capable or not.  These tables let us convert from one to the other.
426  */
427 static const unsigned char asc_syn_xfer_period[8] = {
428         25, 30, 35, 40, 50, 60, 70, 85
429 };
430 
431 static const unsigned char asc_syn_ultra_xfer_period[16] = {
432         12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
433 };
434 
435 typedef struct ext_msg {
436         uchar msg_type;
437         uchar msg_len;
438         uchar msg_req;
439         union {
440                 struct {
441                         uchar sdtr_xfer_period;
442                         uchar sdtr_req_ack_offset;
443                 } sdtr;
444                 struct {
445                         uchar wdtr_width;
446                 } wdtr;
447                 struct {
448                         uchar mdp_b3;
449                         uchar mdp_b2;
450                         uchar mdp_b1;
451                         uchar mdp_b0;
452                 } mdp;
453         } u_ext_msg;
454         uchar res;
455 } EXT_MSG;
456 
457 #define xfer_period     u_ext_msg.sdtr.sdtr_xfer_period
458 #define req_ack_offset  u_ext_msg.sdtr.sdtr_req_ack_offset
459 #define wdtr_width      u_ext_msg.wdtr.wdtr_width
460 #define mdp_b3          u_ext_msg.mdp_b3
461 #define mdp_b2          u_ext_msg.mdp_b2
462 #define mdp_b1          u_ext_msg.mdp_b1
463 #define mdp_b0          u_ext_msg.mdp_b0
464 
465 typedef struct asc_dvc_cfg {
466         ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
467         ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
468         ASC_SCSI_BIT_ID_TYPE disc_enable;
469         ASC_SCSI_BIT_ID_TYPE sdtr_enable;
470         uchar chip_scsi_id;
471         uchar isa_dma_speed;
472         uchar isa_dma_channel;
473         uchar chip_version;
474         ushort mcode_date;
475         ushort mcode_version;
476         uchar max_tag_qng[ASC_MAX_TID + 1];
477         uchar sdtr_period_offset[ASC_MAX_TID + 1];
478         uchar adapter_info[6];
479 } ASC_DVC_CFG;
480 
481 #define ASC_DEF_DVC_CNTL       0xFFFF
482 #define ASC_DEF_CHIP_SCSI_ID   7
483 #define ASC_DEF_ISA_DMA_SPEED  4
484 #define ASC_INIT_STATE_BEG_GET_CFG   0x0001
485 #define ASC_INIT_STATE_END_GET_CFG   0x0002
486 #define ASC_INIT_STATE_BEG_SET_CFG   0x0004
487 #define ASC_INIT_STATE_END_SET_CFG   0x0008
488 #define ASC_INIT_STATE_BEG_LOAD_MC   0x0010
489 #define ASC_INIT_STATE_END_LOAD_MC   0x0020
490 #define ASC_INIT_STATE_BEG_INQUIRY   0x0040
491 #define ASC_INIT_STATE_END_INQUIRY   0x0080
492 #define ASC_INIT_RESET_SCSI_DONE     0x0100
493 #define ASC_INIT_STATE_WITHOUT_EEP   0x8000
494 #define ASC_BUG_FIX_IF_NOT_DWB       0x0001
495 #define ASC_BUG_FIX_ASYN_USE_SYN     0x0002
496 #define ASC_MIN_TAGGED_CMD  7
497 #define ASC_MAX_SCSI_RESET_WAIT      30
498 #define ASC_OVERRUN_BSIZE               64
499 
500 struct asc_dvc_var;             /* Forward Declaration. */
501 
502 typedef struct asc_dvc_var {
503         PortAddr iop_base;
504         ushort err_code;
505         ushort dvc_cntl;
506         ushort bug_fix_cntl;
507         ushort bus_type;
508         ASC_SCSI_BIT_ID_TYPE init_sdtr;
509         ASC_SCSI_BIT_ID_TYPE sdtr_done;
510         ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
511         ASC_SCSI_BIT_ID_TYPE unit_not_ready;
512         ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
513         ASC_SCSI_BIT_ID_TYPE start_motor;
514         uchar *overrun_buf;
515         dma_addr_t overrun_dma;
516         uchar scsi_reset_wait;
517         uchar chip_no;
518         bool is_in_int;
519         uchar max_total_qng;
520         uchar cur_total_qng;
521         uchar in_critical_cnt;
522         uchar last_q_shortage;
523         ushort init_state;
524         uchar cur_dvc_qng[ASC_MAX_TID + 1];
525         uchar max_dvc_qng[ASC_MAX_TID + 1];
526         ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
527         ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
528         const uchar *sdtr_period_tbl;
529         ASC_DVC_CFG *cfg;
530         ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
531         char redo_scam;
532         ushort res2;
533         uchar dos_int13_table[ASC_MAX_TID + 1];
534         unsigned int max_dma_count;
535         ASC_SCSI_BIT_ID_TYPE no_scam;
536         ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
537         uchar min_sdtr_index;
538         uchar max_sdtr_index;
539         struct asc_board *drv_ptr;
540         unsigned int uc_break;
541 } ASC_DVC_VAR;
542 
543 typedef struct asc_dvc_inq_info {
544         uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
545 } ASC_DVC_INQ_INFO;
546 
547 typedef struct asc_cap_info {
548         u32 lba;
549         u32 blk_size;
550 } ASC_CAP_INFO;
551 
552 typedef struct asc_cap_info_array {
553         ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
554 } ASC_CAP_INFO_ARRAY;
555 
556 #define ASC_MCNTL_NO_SEL_TIMEOUT  (ushort)0x0001
557 #define ASC_MCNTL_NULL_TARGET     (ushort)0x0002
558 #define ASC_CNTL_INITIATOR         (ushort)0x0001
559 #define ASC_CNTL_BIOS_GT_1GB       (ushort)0x0002
560 #define ASC_CNTL_BIOS_GT_2_DISK    (ushort)0x0004
561 #define ASC_CNTL_BIOS_REMOVABLE    (ushort)0x0008
562 #define ASC_CNTL_NO_SCAM           (ushort)0x0010
563 #define ASC_CNTL_INT_MULTI_Q       (ushort)0x0080
564 #define ASC_CNTL_NO_LUN_SUPPORT    (ushort)0x0040
565 #define ASC_CNTL_NO_VERIFY_COPY    (ushort)0x0100
566 #define ASC_CNTL_RESET_SCSI        (ushort)0x0200
567 #define ASC_CNTL_INIT_INQUIRY      (ushort)0x0400
568 #define ASC_CNTL_INIT_VERBOSE      (ushort)0x0800
569 #define ASC_CNTL_SCSI_PARITY       (ushort)0x1000
570 #define ASC_CNTL_BURST_MODE        (ushort)0x2000
571 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
572 #define ASC_EEP_DVC_CFG_BEG_VL    2
573 #define ASC_EEP_MAX_DVC_ADDR_VL   15
574 #define ASC_EEP_DVC_CFG_BEG      32
575 #define ASC_EEP_MAX_DVC_ADDR     45
576 #define ASC_EEP_MAX_RETRY        20
577 
578 /*
579  * These macros keep the chip SCSI id and ISA DMA speed
580  * bitfields in board order. C bitfields aren't portable
581  * between big and little-endian platforms so they are
582  * not used.
583  */
584 
585 #define ASC_EEP_GET_CHIP_ID(cfg)    ((cfg)->id_speed & 0x0f)
586 #define ASC_EEP_GET_DMA_SPD(cfg)    (((cfg)->id_speed & 0xf0) >> 4)
587 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
588    ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
589 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
590    ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
591 
592 typedef struct asceep_config {
593         ushort cfg_lsw;
594         ushort cfg_msw;
595         uchar init_sdtr;
596         uchar disc_enable;
597         uchar use_cmd_qng;
598         uchar start_motor;
599         uchar max_total_qng;
600         uchar max_tag_qng;
601         uchar bios_scan;
602         uchar power_up_wait;
603         uchar no_scam;
604         uchar id_speed;         /* low order 4 bits is chip scsi id */
605         /* high order 4 bits is isa dma speed */
606         uchar dos_int13_table[ASC_MAX_TID + 1];
607         uchar adapter_info[6];
608         ushort cntl;
609         ushort chksum;
610 } ASCEEP_CONFIG;
611 
612 #define ASC_EEP_CMD_READ          0x80
613 #define ASC_EEP_CMD_WRITE         0x40
614 #define ASC_EEP_CMD_WRITE_ABLE    0x30
615 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
616 #define ASCV_MSGOUT_BEG         0x0000
617 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
618 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
619 #define ASCV_BREAK_SAVED_CODE   (ushort)0x0006
620 #define ASCV_MSGIN_BEG          (ASCV_MSGOUT_BEG+8)
621 #define ASCV_MSGIN_SDTR_PERIOD  (ASCV_MSGIN_BEG+3)
622 #define ASCV_MSGIN_SDTR_OFFSET  (ASCV_MSGIN_BEG+4)
623 #define ASCV_SDTR_DATA_BEG      (ASCV_MSGIN_BEG+8)
624 #define ASCV_SDTR_DONE_BEG      (ASCV_SDTR_DATA_BEG+8)
625 #define ASCV_MAX_DVC_QNG_BEG    (ushort)0x0020
626 #define ASCV_BREAK_ADDR           (ushort)0x0028
627 #define ASCV_BREAK_NOTIFY_COUNT   (ushort)0x002A
628 #define ASCV_BREAK_CONTROL        (ushort)0x002C
629 #define ASCV_BREAK_HIT_COUNT      (ushort)0x002E
630 
631 #define ASCV_ASCDVC_ERR_CODE_W  (ushort)0x0030
632 #define ASCV_MCODE_CHKSUM_W   (ushort)0x0032
633 #define ASCV_MCODE_SIZE_W     (ushort)0x0034
634 #define ASCV_STOP_CODE_B      (ushort)0x0036
635 #define ASCV_DVC_ERR_CODE_B   (ushort)0x0037
636 #define ASCV_OVERRUN_PADDR_D  (ushort)0x0038
637 #define ASCV_OVERRUN_BSIZE_D  (ushort)0x003C
638 #define ASCV_HALTCODE_W       (ushort)0x0040
639 #define ASCV_CHKSUM_W         (ushort)0x0042
640 #define ASCV_MC_DATE_W        (ushort)0x0044
641 #define ASCV_MC_VER_W         (ushort)0x0046
642 #define ASCV_NEXTRDY_B        (ushort)0x0048
643 #define ASCV_DONENEXT_B       (ushort)0x0049
644 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
645 #define ASCV_SCSIBUSY_B       (ushort)0x004B
646 #define ASCV_Q_DONE_IN_PROGRESS_B  (ushort)0x004C
647 #define ASCV_CURCDB_B         (ushort)0x004D
648 #define ASCV_RCLUN_B          (ushort)0x004E
649 #define ASCV_BUSY_QHEAD_B     (ushort)0x004F
650 #define ASCV_DISC1_QHEAD_B    (ushort)0x0050
651 #define ASCV_DISC_ENABLE_B    (ushort)0x0052
652 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
653 #define ASCV_HOSTSCSI_ID_B    (ushort)0x0055
654 #define ASCV_MCODE_CNTL_B     (ushort)0x0056
655 #define ASCV_NULL_TARGET_B    (ushort)0x0057
656 #define ASCV_FREE_Q_HEAD_W    (ushort)0x0058
657 #define ASCV_DONE_Q_TAIL_W    (ushort)0x005A
658 #define ASCV_FREE_Q_HEAD_B    (ushort)(ASCV_FREE_Q_HEAD_W+1)
659 #define ASCV_DONE_Q_TAIL_B    (ushort)(ASCV_DONE_Q_TAIL_W+1)
660 #define ASCV_HOST_FLAG_B      (ushort)0x005D
661 #define ASCV_TOTAL_READY_Q_B  (ushort)0x0064
662 #define ASCV_VER_SERIAL_B     (ushort)0x0065
663 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
664 #define ASCV_WTM_FLAG_B       (ushort)0x0068
665 #define ASCV_RISC_FLAG_B      (ushort)0x006A
666 #define ASCV_REQ_SG_LIST_QP   (ushort)0x006B
667 #define ASC_HOST_FLAG_IN_ISR        0x01
668 #define ASC_HOST_FLAG_ACK_INT       0x02
669 #define ASC_RISC_FLAG_GEN_INT      0x01
670 #define ASC_RISC_FLAG_REQ_SG_LIST  0x02
671 #define IOP_CTRL         (0x0F)
672 #define IOP_STATUS       (0x0E)
673 #define IOP_INT_ACK      IOP_STATUS
674 #define IOP_REG_IFC      (0x0D)
675 #define IOP_SYN_OFFSET    (0x0B)
676 #define IOP_EXTRA_CONTROL (0x0D)
677 #define IOP_REG_PC        (0x0C)
678 #define IOP_RAM_ADDR      (0x0A)
679 #define IOP_RAM_DATA      (0x08)
680 #define IOP_EEP_DATA      (0x06)
681 #define IOP_EEP_CMD       (0x07)
682 #define IOP_VERSION       (0x03)
683 #define IOP_CONFIG_HIGH   (0x04)
684 #define IOP_CONFIG_LOW    (0x02)
685 #define IOP_SIG_BYTE      (0x01)
686 #define IOP_SIG_WORD      (0x00)
687 #define IOP_REG_DC1      (0x0E)
688 #define IOP_REG_DC0      (0x0C)
689 #define IOP_REG_SB       (0x0B)
690 #define IOP_REG_DA1      (0x0A)
691 #define IOP_REG_DA0      (0x08)
692 #define IOP_REG_SC       (0x09)
693 #define IOP_DMA_SPEED    (0x07)
694 #define IOP_REG_FLAG     (0x07)
695 #define IOP_FIFO_H       (0x06)
696 #define IOP_FIFO_L       (0x04)
697 #define IOP_REG_ID       (0x05)
698 #define IOP_REG_QP       (0x03)
699 #define IOP_REG_IH       (0x02)
700 #define IOP_REG_IX       (0x01)
701 #define IOP_REG_AX       (0x00)
702 #define IFC_REG_LOCK      (0x00)
703 #define IFC_REG_UNLOCK    (0x09)
704 #define IFC_WR_EN_FILTER  (0x10)
705 #define IFC_RD_NO_EEPROM  (0x10)
706 #define IFC_SLEW_RATE     (0x20)
707 #define IFC_ACT_NEG       (0x40)
708 #define IFC_INP_FILTER    (0x80)
709 #define IFC_INIT_DEFAULT  (IFC_ACT_NEG | IFC_REG_UNLOCK)
710 #define SC_SEL   (uchar)(0x80)
711 #define SC_BSY   (uchar)(0x40)
712 #define SC_ACK   (uchar)(0x20)
713 #define SC_REQ   (uchar)(0x10)
714 #define SC_ATN   (uchar)(0x08)
715 #define SC_IO    (uchar)(0x04)
716 #define SC_CD    (uchar)(0x02)
717 #define SC_MSG   (uchar)(0x01)
718 #define SEC_SCSI_CTL         (uchar)(0x80)
719 #define SEC_ACTIVE_NEGATE    (uchar)(0x40)
720 #define SEC_SLEW_RATE        (uchar)(0x20)
721 #define SEC_ENABLE_FILTER    (uchar)(0x10)
722 #define ASC_HALT_EXTMSG_IN     (ushort)0x8000
723 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
724 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
725 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX  (ushort)0x8300
726 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX   (ushort)0x8400
727 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
728 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
729 #define ASC_MAX_QNO        0xF8
730 #define ASC_DATA_SEC_BEG   (ushort)0x0080
731 #define ASC_DATA_SEC_END   (ushort)0x0080
732 #define ASC_CODE_SEC_BEG   (ushort)0x0080
733 #define ASC_CODE_SEC_END   (ushort)0x0080
734 #define ASC_QADR_BEG       (0x4000)
735 #define ASC_QADR_USED      (ushort)(ASC_MAX_QNO * 64)
736 #define ASC_QADR_END       (ushort)0x7FFF
737 #define ASC_QLAST_ADR      (ushort)0x7FC0
738 #define ASC_QBLK_SIZE      0x40
739 #define ASC_BIOS_DATA_QBEG 0xF8
740 #define ASC_MIN_ACTIVE_QNO 0x01
741 #define ASC_QLINK_END      0xFF
742 #define ASC_EEPROM_WORDS   0x10
743 #define ASC_MAX_MGS_LEN    0x10
744 #define ASC_BIOS_ADDR_DEF  0xDC00
745 #define ASC_BIOS_SIZE      0x3800
746 #define ASC_BIOS_RAM_OFF   0x3800
747 #define ASC_BIOS_RAM_SIZE  0x800
748 #define ASC_BIOS_MIN_ADDR  0xC000
749 #define ASC_BIOS_MAX_ADDR  0xEC00
750 #define ASC_BIOS_BANK_SIZE 0x0400
751 #define ASC_MCODE_START_ADDR  0x0080
752 #define ASC_CFG0_HOST_INT_ON    0x0020
753 #define ASC_CFG0_BIOS_ON        0x0040
754 #define ASC_CFG0_VERA_BURST_ON  0x0080
755 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
756 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
757 #define ASC_CFG1_LRAM_8BITS_ON  0x0800
758 #define ASC_CFG_MSW_CLR_MASK    0x3080
759 #define CSW_TEST1             (ASC_CS_TYPE)0x8000
760 #define CSW_AUTO_CONFIG       (ASC_CS_TYPE)0x4000
761 #define CSW_RESERVED1         (ASC_CS_TYPE)0x2000
762 #define CSW_IRQ_WRITTEN       (ASC_CS_TYPE)0x1000
763 #define CSW_33MHZ_SELECTED    (ASC_CS_TYPE)0x0800
764 #define CSW_TEST2             (ASC_CS_TYPE)0x0400
765 #define CSW_TEST3             (ASC_CS_TYPE)0x0200
766 #define CSW_RESERVED2         (ASC_CS_TYPE)0x0100
767 #define CSW_DMA_DONE          (ASC_CS_TYPE)0x0080
768 #define CSW_FIFO_RDY          (ASC_CS_TYPE)0x0040
769 #define CSW_EEP_READ_DONE     (ASC_CS_TYPE)0x0020
770 #define CSW_HALTED            (ASC_CS_TYPE)0x0010
771 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
772 #define CSW_PARITY_ERR        (ASC_CS_TYPE)0x0004
773 #define CSW_SCSI_RESET_LATCH  (ASC_CS_TYPE)0x0002
774 #define CSW_INT_PENDING       (ASC_CS_TYPE)0x0001
775 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
776 #define CIW_INT_ACK      (ASC_CS_TYPE)0x0100
777 #define CIW_TEST1        (ASC_CS_TYPE)0x0200
778 #define CIW_TEST2        (ASC_CS_TYPE)0x0400
779 #define CIW_SEL_33MHZ    (ASC_CS_TYPE)0x0800
780 #define CIW_IRQ_ACT      (ASC_CS_TYPE)0x1000
781 #define CC_CHIP_RESET   (uchar)0x80
782 #define CC_SCSI_RESET   (uchar)0x40
783 #define CC_HALT         (uchar)0x20
784 #define CC_SINGLE_STEP  (uchar)0x10
785 #define CC_DMA_ABLE     (uchar)0x08
786 #define CC_TEST         (uchar)0x04
787 #define CC_BANK_ONE     (uchar)0x02
788 #define CC_DIAG         (uchar)0x01
789 #define ASC_1000_ID0W      0x04C1
790 #define ASC_1000_ID0W_FIX  0x00C1
791 #define ASC_1000_ID1B      0x25
792 #define ASC_EISA_REV_IOP_MASK  (0x0C83)
793 #define ASC_EISA_CFG_IOP_MASK  (0x0C86)
794 #define ASC_GET_EISA_SLOT(iop)  (PortAddr)((iop) & 0xF000)
795 #define INS_HALTINT        (ushort)0x6281
796 #define INS_HALT           (ushort)0x6280
797 #define INS_SINT           (ushort)0x6200
798 #define INS_RFLAG_WTM      (ushort)0x7380
799 #define ASC_MC_SAVE_CODE_WSIZE  0x500
800 #define ASC_MC_SAVE_DATA_WSIZE  0x40
801 
802 typedef struct asc_mc_saved {
803         ushort data[ASC_MC_SAVE_DATA_WSIZE];
804         ushort code[ASC_MC_SAVE_CODE_WSIZE];
805 } ASC_MC_SAVED;
806 
807 #define AscGetQDoneInProgress(port)         AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
808 #define AscPutQDoneInProgress(port, val)    AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
809 #define AscGetVarFreeQHead(port)            AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
810 #define AscGetVarDoneQTail(port)            AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
811 #define AscPutVarFreeQHead(port, val)       AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
812 #define AscPutVarDoneQTail(port, val)       AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
813 #define AscGetRiscVarFreeQHead(port)        AscReadLramByte((port), ASCV_NEXTRDY_B)
814 #define AscGetRiscVarDoneQTail(port)        AscReadLramByte((port), ASCV_DONENEXT_B)
815 #define AscPutRiscVarFreeQHead(port, val)   AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
816 #define AscPutRiscVarDoneQTail(port, val)   AscWriteLramByte((port), ASCV_DONENEXT_B, val)
817 #define AscPutMCodeSDTRDoneAtID(port, id, data)  AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
818 #define AscGetMCodeSDTRDoneAtID(port, id)        AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
819 #define AscPutMCodeInitSDTRAtID(port, id, data)  AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
820 #define AscGetMCodeInitSDTRAtID(port, id)        AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
821 #define AscGetChipSignatureByte(port)     (uchar)inp((port)+IOP_SIG_BYTE)
822 #define AscGetChipSignatureWord(port)     (ushort)inpw((port)+IOP_SIG_WORD)
823 #define AscGetChipVerNo(port)             (uchar)inp((port)+IOP_VERSION)
824 #define AscGetChipCfgLsw(port)            (ushort)inpw((port)+IOP_CONFIG_LOW)
825 #define AscGetChipCfgMsw(port)            (ushort)inpw((port)+IOP_CONFIG_HIGH)
826 #define AscSetChipCfgLsw(port, data)      outpw((port)+IOP_CONFIG_LOW, data)
827 #define AscSetChipCfgMsw(port, data)      outpw((port)+IOP_CONFIG_HIGH, data)
828 #define AscGetChipEEPCmd(port)            (uchar)inp((port)+IOP_EEP_CMD)
829 #define AscSetChipEEPCmd(port, data)      outp((port)+IOP_EEP_CMD, data)
830 #define AscGetChipEEPData(port)           (ushort)inpw((port)+IOP_EEP_DATA)
831 #define AscSetChipEEPData(port, data)     outpw((port)+IOP_EEP_DATA, data)
832 #define AscGetChipLramAddr(port)          (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
833 #define AscSetChipLramAddr(port, addr)    outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
834 #define AscGetChipLramData(port)          (ushort)inpw((port)+IOP_RAM_DATA)
835 #define AscSetChipLramData(port, data)    outpw((port)+IOP_RAM_DATA, data)
836 #define AscGetChipIFC(port)               (uchar)inp((port)+IOP_REG_IFC)
837 #define AscSetChipIFC(port, data)          outp((port)+IOP_REG_IFC, data)
838 #define AscGetChipStatus(port)            (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
839 #define AscSetChipStatus(port, cs_val)    outpw((port)+IOP_STATUS, cs_val)
840 #define AscGetChipControl(port)           (uchar)inp((port)+IOP_CTRL)
841 #define AscSetChipControl(port, cc_val)   outp((port)+IOP_CTRL, cc_val)
842 #define AscGetChipSyn(port)               (uchar)inp((port)+IOP_SYN_OFFSET)
843 #define AscSetChipSyn(port, data)         outp((port)+IOP_SYN_OFFSET, data)
844 #define AscSetPCAddr(port, data)          outpw((port)+IOP_REG_PC, data)
845 #define AscGetPCAddr(port)                (ushort)inpw((port)+IOP_REG_PC)
846 #define AscIsIntPending(port)             (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
847 #define AscGetChipScsiID(port)            ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
848 #define AscGetExtraControl(port)          (uchar)inp((port)+IOP_EXTRA_CONTROL)
849 #define AscSetExtraControl(port, data)    outp((port)+IOP_EXTRA_CONTROL, data)
850 #define AscReadChipAX(port)               (ushort)inpw((port)+IOP_REG_AX)
851 #define AscWriteChipAX(port, data)        outpw((port)+IOP_REG_AX, data)
852 #define AscReadChipIX(port)               (uchar)inp((port)+IOP_REG_IX)
853 #define AscWriteChipIX(port, data)        outp((port)+IOP_REG_IX, data)
854 #define AscReadChipIH(port)               (ushort)inpw((port)+IOP_REG_IH)
855 #define AscWriteChipIH(port, data)        outpw((port)+IOP_REG_IH, data)
856 #define AscReadChipQP(port)               (uchar)inp((port)+IOP_REG_QP)
857 #define AscWriteChipQP(port, data)        outp((port)+IOP_REG_QP, data)
858 #define AscReadChipFIFO_L(port)           (ushort)inpw((port)+IOP_REG_FIFO_L)
859 #define AscWriteChipFIFO_L(port, data)    outpw((port)+IOP_REG_FIFO_L, data)
860 #define AscReadChipFIFO_H(port)           (ushort)inpw((port)+IOP_REG_FIFO_H)
861 #define AscWriteChipFIFO_H(port, data)    outpw((port)+IOP_REG_FIFO_H, data)
862 #define AscReadChipDmaSpeed(port)         (uchar)inp((port)+IOP_DMA_SPEED)
863 #define AscWriteChipDmaSpeed(port, data)  outp((port)+IOP_DMA_SPEED, data)
864 #define AscReadChipDA0(port)              (ushort)inpw((port)+IOP_REG_DA0)
865 #define AscWriteChipDA0(port)             outpw((port)+IOP_REG_DA0, data)
866 #define AscReadChipDA1(port)              (ushort)inpw((port)+IOP_REG_DA1)
867 #define AscWriteChipDA1(port)             outpw((port)+IOP_REG_DA1, data)
868 #define AscReadChipDC0(port)              (ushort)inpw((port)+IOP_REG_DC0)
869 #define AscWriteChipDC0(port)             outpw((port)+IOP_REG_DC0, data)
870 #define AscReadChipDC1(port)              (ushort)inpw((port)+IOP_REG_DC1)
871 #define AscWriteChipDC1(port)             outpw((port)+IOP_REG_DC1, data)
872 #define AscReadChipDvcID(port)            (uchar)inp((port)+IOP_REG_ID)
873 #define AscWriteChipDvcID(port, data)     outp((port)+IOP_REG_ID, data)
874 
875 #define AdvPortAddr  void __iomem *     /* Virtual memory address size */
876 
877 /*
878  * Define Adv Library required memory access macros.
879  */
880 #define ADV_MEM_READB(addr) readb(addr)
881 #define ADV_MEM_READW(addr) readw(addr)
882 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
883 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
884 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
885 
886 /*
887  * Define total number of simultaneous maximum element scatter-gather
888  * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
889  * maximum number of outstanding commands per wide host adapter. Each
890  * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
891  * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
892  * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
893  * structures or 255 scatter-gather elements.
894  */
895 #define ADV_TOT_SG_BLOCK        ASC_DEF_MAX_HOST_QNG
896 
897 /*
898  * Define maximum number of scatter-gather elements per request.
899  */
900 #define ADV_MAX_SG_LIST         255
901 #define NO_OF_SG_PER_BLOCK              15
902 
903 #define ADV_EEP_DVC_CFG_BEGIN           (0x00)
904 #define ADV_EEP_DVC_CFG_END             (0x15)
905 #define ADV_EEP_DVC_CTL_BEGIN           (0x16)  /* location of OEM name */
906 #define ADV_EEP_MAX_WORD_ADDR           (0x1E)
907 
908 #define ADV_EEP_DELAY_MS                100
909 
910 #define ADV_EEPROM_BIG_ENDIAN          0x8000   /* EEPROM Bit 15 */
911 #define ADV_EEPROM_BIOS_ENABLE         0x4000   /* EEPROM Bit 14 */
912 /*
913  * For the ASC3550 Bit 13 is Termination Polarity control bit.
914  * For later ICs Bit 13 controls whether the CIS (Card Information
915  * Service Section) is loaded from EEPROM.
916  */
917 #define ADV_EEPROM_TERM_POL            0x2000   /* EEPROM Bit 13 */
918 #define ADV_EEPROM_CIS_LD              0x2000   /* EEPROM Bit 13 */
919 /*
920  * ASC38C1600 Bit 11
921  *
922  * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
923  * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
924  * Function 0 will specify INT B.
925  *
926  * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
927  * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
928  * Function 1 will specify INT A.
929  */
930 #define ADV_EEPROM_INTAB               0x0800   /* EEPROM Bit 11 */
931 
932 typedef struct adveep_3550_config {
933         /* Word Offset, Description */
934 
935         ushort cfg_lsw;         /* 00 power up initialization */
936         /*  bit 13 set - Term Polarity Control */
937         /*  bit 14 set - BIOS Enable */
938         /*  bit 15 set - Big Endian Mode */
939         ushort cfg_msw;         /* 01 unused      */
940         ushort disc_enable;     /* 02 disconnect enable */
941         ushort wdtr_able;       /* 03 Wide DTR able */
942         ushort sdtr_able;       /* 04 Synchronous DTR able */
943         ushort start_motor;     /* 05 send start up motor */
944         ushort tagqng_able;     /* 06 tag queuing able */
945         ushort bios_scan;       /* 07 BIOS device control */
946         ushort scam_tolerant;   /* 08 no scam */
947 
948         uchar adapter_scsi_id;  /* 09 Host Adapter ID */
949         uchar bios_boot_delay;  /*    power up wait */
950 
951         uchar scsi_reset_delay; /* 10 reset delay */
952         uchar bios_id_lun;      /*    first boot device scsi id & lun */
953         /*    high nibble is lun */
954         /*    low nibble is scsi id */
955 
956         uchar termination;      /* 11 0 - automatic */
957         /*    1 - low off / high off */
958         /*    2 - low off / high on */
959         /*    3 - low on  / high on */
960         /*    There is no low on  / high off */
961 
962         uchar reserved1;        /*    reserved byte (not used) */
963 
964         ushort bios_ctrl;       /* 12 BIOS control bits */
965         /*  bit 0  BIOS don't act as initiator. */
966         /*  bit 1  BIOS > 1 GB support */
967         /*  bit 2  BIOS > 2 Disk Support */
968         /*  bit 3  BIOS don't support removables */
969         /*  bit 4  BIOS support bootable CD */
970         /*  bit 5  BIOS scan enabled */
971         /*  bit 6  BIOS support multiple LUNs */
972         /*  bit 7  BIOS display of message */
973         /*  bit 8  SCAM disabled */
974         /*  bit 9  Reset SCSI bus during init. */
975         /*  bit 10 */
976         /*  bit 11 No verbose initialization. */
977         /*  bit 12 SCSI parity enabled */
978         /*  bit 13 */
979         /*  bit 14 */
980         /*  bit 15 */
981         ushort ultra_able;      /* 13 ULTRA speed able */
982         ushort reserved2;       /* 14 reserved */
983         uchar max_host_qng;     /* 15 maximum host queuing */
984         uchar max_dvc_qng;      /*    maximum per device queuing */
985         ushort dvc_cntl;        /* 16 control bit for driver */
986         ushort bug_fix;         /* 17 control bit for bug fix */
987         ushort serial_number_word1;     /* 18 Board serial number word 1 */
988         ushort serial_number_word2;     /* 19 Board serial number word 2 */
989         ushort serial_number_word3;     /* 20 Board serial number word 3 */
990         ushort check_sum;       /* 21 EEP check sum */
991         uchar oem_name[16];     /* 22 OEM name */
992         ushort dvc_err_code;    /* 30 last device driver error code */
993         ushort adv_err_code;    /* 31 last uc and Adv Lib error code */
994         ushort adv_err_addr;    /* 32 last uc error address */
995         ushort saved_dvc_err_code;      /* 33 saved last dev. driver error code   */
996         ushort saved_adv_err_code;      /* 34 saved last uc and Adv Lib error code */
997         ushort saved_adv_err_addr;      /* 35 saved last uc error address         */
998         ushort num_of_err;      /* 36 number of error */
999 } ADVEEP_3550_CONFIG;
1000 
1001 typedef struct adveep_38C0800_config {
1002         /* Word Offset, Description */
1003 
1004         ushort cfg_lsw;         /* 00 power up initialization */
1005         /*  bit 13 set - Load CIS */
1006         /*  bit 14 set - BIOS Enable */
1007         /*  bit 15 set - Big Endian Mode */
1008         ushort cfg_msw;         /* 01 unused      */
1009         ushort disc_enable;     /* 02 disconnect enable */
1010         ushort wdtr_able;       /* 03 Wide DTR able */
1011         ushort sdtr_speed1;     /* 04 SDTR Speed TID 0-3 */
1012         ushort start_motor;     /* 05 send start up motor */
1013         ushort tagqng_able;     /* 06 tag queuing able */
1014         ushort bios_scan;       /* 07 BIOS device control */
1015         ushort scam_tolerant;   /* 08 no scam */
1016 
1017         uchar adapter_scsi_id;  /* 09 Host Adapter ID */
1018         uchar bios_boot_delay;  /*    power up wait */
1019 
1020         uchar scsi_reset_delay; /* 10 reset delay */
1021         uchar bios_id_lun;      /*    first boot device scsi id & lun */
1022         /*    high nibble is lun */
1023         /*    low nibble is scsi id */
1024 
1025         uchar termination_se;   /* 11 0 - automatic */
1026         /*    1 - low off / high off */
1027         /*    2 - low off / high on */
1028         /*    3 - low on  / high on */
1029         /*    There is no low on  / high off */
1030 
1031         uchar termination_lvd;  /* 11 0 - automatic */
1032         /*    1 - low off / high off */
1033         /*    2 - low off / high on */
1034         /*    3 - low on  / high on */
1035         /*    There is no low on  / high off */
1036 
1037         ushort bios_ctrl;       /* 12 BIOS control bits */
1038         /*  bit 0  BIOS don't act as initiator. */
1039         /*  bit 1  BIOS > 1 GB support */
1040         /*  bit 2  BIOS > 2 Disk Support */
1041         /*  bit 3  BIOS don't support removables */
1042         /*  bit 4  BIOS support bootable CD */
1043         /*  bit 5  BIOS scan enabled */
1044         /*  bit 6  BIOS support multiple LUNs */
1045         /*  bit 7  BIOS display of message */
1046         /*  bit 8  SCAM disabled */
1047         /*  bit 9  Reset SCSI bus during init. */
1048         /*  bit 10 */
1049         /*  bit 11 No verbose initialization. */
1050         /*  bit 12 SCSI parity enabled */
1051         /*  bit 13 */
1052         /*  bit 14 */
1053         /*  bit 15 */
1054         ushort sdtr_speed2;     /* 13 SDTR speed TID 4-7 */
1055         ushort sdtr_speed3;     /* 14 SDTR speed TID 8-11 */
1056         uchar max_host_qng;     /* 15 maximum host queueing */
1057         uchar max_dvc_qng;      /*    maximum per device queuing */
1058         ushort dvc_cntl;        /* 16 control bit for driver */
1059         ushort sdtr_speed4;     /* 17 SDTR speed 4 TID 12-15 */
1060         ushort serial_number_word1;     /* 18 Board serial number word 1 */
1061         ushort serial_number_word2;     /* 19 Board serial number word 2 */
1062         ushort serial_number_word3;     /* 20 Board serial number word 3 */
1063         ushort check_sum;       /* 21 EEP check sum */
1064         uchar oem_name[16];     /* 22 OEM name */
1065         ushort dvc_err_code;    /* 30 last device driver error code */
1066         ushort adv_err_code;    /* 31 last uc and Adv Lib error code */
1067         ushort adv_err_addr;    /* 32 last uc error address */
1068         ushort saved_dvc_err_code;      /* 33 saved last dev. driver error code   */
1069         ushort saved_adv_err_code;      /* 34 saved last uc and Adv Lib error code */
1070         ushort saved_adv_err_addr;      /* 35 saved last uc error address         */
1071         ushort reserved36;      /* 36 reserved */
1072         ushort reserved37;      /* 37 reserved */
1073         ushort reserved38;      /* 38 reserved */
1074         ushort reserved39;      /* 39 reserved */
1075         ushort reserved40;      /* 40 reserved */
1076         ushort reserved41;      /* 41 reserved */
1077         ushort reserved42;      /* 42 reserved */
1078         ushort reserved43;      /* 43 reserved */
1079         ushort reserved44;      /* 44 reserved */
1080         ushort reserved45;      /* 45 reserved */
1081         ushort reserved46;      /* 46 reserved */
1082         ushort reserved47;      /* 47 reserved */
1083         ushort reserved48;      /* 48 reserved */
1084         ushort reserved49;      /* 49 reserved */
1085         ushort reserved50;      /* 50 reserved */
1086         ushort reserved51;      /* 51 reserved */
1087         ushort reserved52;      /* 52 reserved */
1088         ushort reserved53;      /* 53 reserved */
1089         ushort reserved54;      /* 54 reserved */
1090         ushort reserved55;      /* 55 reserved */
1091         ushort cisptr_lsw;      /* 56 CIS PTR LSW */
1092         ushort cisprt_msw;      /* 57 CIS PTR MSW */
1093         ushort subsysvid;       /* 58 SubSystem Vendor ID */
1094         ushort subsysid;        /* 59 SubSystem ID */
1095         ushort reserved60;      /* 60 reserved */
1096         ushort reserved61;      /* 61 reserved */
1097         ushort reserved62;      /* 62 reserved */
1098         ushort reserved63;      /* 63 reserved */
1099 } ADVEEP_38C0800_CONFIG;
1100 
1101 typedef struct adveep_38C1600_config {
1102         /* Word Offset, Description */
1103 
1104         ushort cfg_lsw;         /* 00 power up initialization */
1105         /*  bit 11 set - Func. 0 INTB, Func. 1 INTA */
1106         /*       clear - Func. 0 INTA, Func. 1 INTB */
1107         /*  bit 13 set - Load CIS */
1108         /*  bit 14 set - BIOS Enable */
1109         /*  bit 15 set - Big Endian Mode */
1110         ushort cfg_msw;         /* 01 unused */
1111         ushort disc_enable;     /* 02 disconnect enable */
1112         ushort wdtr_able;       /* 03 Wide DTR able */
1113         ushort sdtr_speed1;     /* 04 SDTR Speed TID 0-3 */
1114         ushort start_motor;     /* 05 send start up motor */
1115         ushort tagqng_able;     /* 06 tag queuing able */
1116         ushort bios_scan;       /* 07 BIOS device control */
1117         ushort scam_tolerant;   /* 08 no scam */
1118 
1119         uchar adapter_scsi_id;  /* 09 Host Adapter ID */
1120         uchar bios_boot_delay;  /*    power up wait */
1121 
1122         uchar scsi_reset_delay; /* 10 reset delay */
1123         uchar bios_id_lun;      /*    first boot device scsi id & lun */
1124         /*    high nibble is lun */
1125         /*    low nibble is scsi id */
1126 
1127         uchar termination_se;   /* 11 0 - automatic */
1128         /*    1 - low off / high off */
1129         /*    2 - low off / high on */
1130         /*    3 - low on  / high on */
1131         /*    There is no low on  / high off */
1132 
1133         uchar termination_lvd;  /* 11 0 - automatic */
1134         /*    1 - low off / high off */
1135         /*    2 - low off / high on */
1136         /*    3 - low on  / high on */
1137         /*    There is no low on  / high off */
1138 
1139         ushort bios_ctrl;       /* 12 BIOS control bits */
1140         /*  bit 0  BIOS don't act as initiator. */
1141         /*  bit 1  BIOS > 1 GB support */
1142         /*  bit 2  BIOS > 2 Disk Support */
1143         /*  bit 3  BIOS don't support removables */
1144         /*  bit 4  BIOS support bootable CD */
1145         /*  bit 5  BIOS scan enabled */
1146         /*  bit 6  BIOS support multiple LUNs */
1147         /*  bit 7  BIOS display of message */
1148         /*  bit 8  SCAM disabled */
1149         /*  bit 9  Reset SCSI bus during init. */
1150         /*  bit 10 Basic Integrity Checking disabled */
1151         /*  bit 11 No verbose initialization. */
1152         /*  bit 12 SCSI parity enabled */
1153         /*  bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1154         /*  bit 14 */
1155         /*  bit 15 */
1156         ushort sdtr_speed2;     /* 13 SDTR speed TID 4-7 */
1157         ushort sdtr_speed3;     /* 14 SDTR speed TID 8-11 */
1158         uchar max_host_qng;     /* 15 maximum host queueing */
1159         uchar max_dvc_qng;      /*    maximum per device queuing */
1160         ushort dvc_cntl;        /* 16 control bit for driver */
1161         ushort sdtr_speed4;     /* 17 SDTR speed 4 TID 12-15 */
1162         ushort serial_number_word1;     /* 18 Board serial number word 1 */
1163         ushort serial_number_word2;     /* 19 Board serial number word 2 */
1164         ushort serial_number_word3;     /* 20 Board serial number word 3 */
1165         ushort check_sum;       /* 21 EEP check sum */
1166         uchar oem_name[16];     /* 22 OEM name */
1167         ushort dvc_err_code;    /* 30 last device driver error code */
1168         ushort adv_err_code;    /* 31 last uc and Adv Lib error code */
1169         ushort adv_err_addr;    /* 32 last uc error address */
1170         ushort saved_dvc_err_code;      /* 33 saved last dev. driver error code   */
1171         ushort saved_adv_err_code;      /* 34 saved last uc and Adv Lib error code */
1172         ushort saved_adv_err_addr;      /* 35 saved last uc error address         */
1173         ushort reserved36;      /* 36 reserved */
1174         ushort reserved37;      /* 37 reserved */
1175         ushort reserved38;      /* 38 reserved */
1176         ushort reserved39;      /* 39 reserved */
1177         ushort reserved40;      /* 40 reserved */
1178         ushort reserved41;      /* 41 reserved */
1179         ushort reserved42;      /* 42 reserved */
1180         ushort reserved43;      /* 43 reserved */
1181         ushort reserved44;      /* 44 reserved */
1182         ushort reserved45;      /* 45 reserved */
1183         ushort reserved46;      /* 46 reserved */
1184         ushort reserved47;      /* 47 reserved */
1185         ushort reserved48;      /* 48 reserved */
1186         ushort reserved49;      /* 49 reserved */
1187         ushort reserved50;      /* 50 reserved */
1188         ushort reserved51;      /* 51 reserved */
1189         ushort reserved52;      /* 52 reserved */
1190         ushort reserved53;      /* 53 reserved */
1191         ushort reserved54;      /* 54 reserved */
1192         ushort reserved55;      /* 55 reserved */
1193         ushort cisptr_lsw;      /* 56 CIS PTR LSW */
1194         ushort cisprt_msw;      /* 57 CIS PTR MSW */
1195         ushort subsysvid;       /* 58 SubSystem Vendor ID */
1196         ushort subsysid;        /* 59 SubSystem ID */
1197         ushort reserved60;      /* 60 reserved */
1198         ushort reserved61;      /* 61 reserved */
1199         ushort reserved62;      /* 62 reserved */
1200         ushort reserved63;      /* 63 reserved */
1201 } ADVEEP_38C1600_CONFIG;
1202 
1203 /*
1204  * EEPROM Commands
1205  */
1206 #define ASC_EEP_CMD_DONE             0x0200
1207 
1208 /* bios_ctrl */
1209 #define BIOS_CTRL_BIOS               0x0001
1210 #define BIOS_CTRL_EXTENDED_XLAT      0x0002
1211 #define BIOS_CTRL_GT_2_DISK          0x0004
1212 #define BIOS_CTRL_BIOS_REMOVABLE     0x0008
1213 #define BIOS_CTRL_BOOTABLE_CD        0x0010
1214 #define BIOS_CTRL_MULTIPLE_LUN       0x0040
1215 #define BIOS_CTRL_DISPLAY_MSG        0x0080
1216 #define BIOS_CTRL_NO_SCAM            0x0100
1217 #define BIOS_CTRL_RESET_SCSI_BUS     0x0200
1218 #define BIOS_CTRL_INIT_VERBOSE       0x0800
1219 #define BIOS_CTRL_SCSI_PARITY        0x1000
1220 #define BIOS_CTRL_AIPP_DIS           0x2000
1221 
1222 #define ADV_3550_MEMSIZE   0x2000       /* 8 KB Internal Memory */
1223 
1224 #define ADV_38C0800_MEMSIZE  0x4000     /* 16 KB Internal Memory */
1225 
1226 /*
1227  * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1228  * a special 16K Adv Library and Microcode version. After the issue is
1229  * resolved, should restore 32K support.
1230  *
1231  * #define ADV_38C1600_MEMSIZE  0x8000L   * 32 KB Internal Memory *
1232  */
1233 #define ADV_38C1600_MEMSIZE  0x4000     /* 16 KB Internal Memory */
1234 
1235 /*
1236  * Byte I/O register address from base of 'iop_base'.
1237  */
1238 #define IOPB_INTR_STATUS_REG    0x00
1239 #define IOPB_CHIP_ID_1          0x01
1240 #define IOPB_INTR_ENABLES       0x02
1241 #define IOPB_CHIP_TYPE_REV      0x03
1242 #define IOPB_RES_ADDR_4         0x04
1243 #define IOPB_RES_ADDR_5         0x05
1244 #define IOPB_RAM_DATA           0x06
1245 #define IOPB_RES_ADDR_7         0x07
1246 #define IOPB_FLAG_REG           0x08
1247 #define IOPB_RES_ADDR_9         0x09
1248 #define IOPB_RISC_CSR           0x0A
1249 #define IOPB_RES_ADDR_B         0x0B
1250 #define IOPB_RES_ADDR_C         0x0C
1251 #define IOPB_RES_ADDR_D         0x0D
1252 #define IOPB_SOFT_OVER_WR       0x0E
1253 #define IOPB_RES_ADDR_F         0x0F
1254 #define IOPB_MEM_CFG            0x10
1255 #define IOPB_RES_ADDR_11        0x11
1256 #define IOPB_GPIO_DATA          0x12
1257 #define IOPB_RES_ADDR_13        0x13
1258 #define IOPB_FLASH_PAGE         0x14
1259 #define IOPB_RES_ADDR_15        0x15
1260 #define IOPB_GPIO_CNTL          0x16
1261 #define IOPB_RES_ADDR_17        0x17
1262 #define IOPB_FLASH_DATA         0x18
1263 #define IOPB_RES_ADDR_19        0x19
1264 #define IOPB_RES_ADDR_1A        0x1A
1265 #define IOPB_RES_ADDR_1B        0x1B
1266 #define IOPB_RES_ADDR_1C        0x1C
1267 #define IOPB_RES_ADDR_1D        0x1D
1268 #define IOPB_RES_ADDR_1E        0x1E
1269 #define IOPB_RES_ADDR_1F        0x1F
1270 #define IOPB_DMA_CFG0           0x20
1271 #define IOPB_DMA_CFG1           0x21
1272 #define IOPB_TICKLE             0x22
1273 #define IOPB_DMA_REG_WR         0x23
1274 #define IOPB_SDMA_STATUS        0x24
1275 #define IOPB_SCSI_BYTE_CNT      0x25
1276 #define IOPB_HOST_BYTE_CNT      0x26
1277 #define IOPB_BYTE_LEFT_TO_XFER  0x27
1278 #define IOPB_BYTE_TO_XFER_0     0x28
1279 #define IOPB_BYTE_TO_XFER_1     0x29
1280 #define IOPB_BYTE_TO_XFER_2     0x2A
1281 #define IOPB_BYTE_TO_XFER_3     0x2B
1282 #define IOPB_ACC_GRP            0x2C
1283 #define IOPB_RES_ADDR_2D        0x2D
1284 #define IOPB_DEV_ID             0x2E
1285 #define IOPB_RES_ADDR_2F        0x2F
1286 #define IOPB_SCSI_DATA          0x30
1287 #define IOPB_RES_ADDR_31        0x31
1288 #define IOPB_RES_ADDR_32        0x32
1289 #define IOPB_SCSI_DATA_HSHK     0x33
1290 #define IOPB_SCSI_CTRL          0x34
1291 #define IOPB_RES_ADDR_35        0x35
1292 #define IOPB_RES_ADDR_36        0x36
1293 #define IOPB_RES_ADDR_37        0x37
1294 #define IOPB_RAM_BIST           0x38
1295 #define IOPB_PLL_TEST           0x39
1296 #define IOPB_PCI_INT_CFG        0x3A
1297 #define IOPB_RES_ADDR_3B        0x3B
1298 #define IOPB_RFIFO_CNT          0x3C
1299 #define IOPB_RES_ADDR_3D        0x3D
1300 #define IOPB_RES_ADDR_3E        0x3E
1301 #define IOPB_RES_ADDR_3F        0x3F
1302 
1303 /*
1304  * Word I/O register address from base of 'iop_base'.
1305  */
1306 #define IOPW_CHIP_ID_0          0x00    /* CID0  */
1307 #define IOPW_CTRL_REG           0x02    /* CC    */
1308 #define IOPW_RAM_ADDR           0x04    /* LA    */
1309 #define IOPW_RAM_DATA           0x06    /* LD    */
1310 #define IOPW_RES_ADDR_08        0x08
1311 #define IOPW_RISC_CSR           0x0A    /* CSR   */
1312 #define IOPW_SCSI_CFG0          0x0C    /* CFG0  */
1313 #define IOPW_SCSI_CFG1          0x0E    /* CFG1  */
1314 #define IOPW_RES_ADDR_10        0x10
1315 #define IOPW_SEL_MASK           0x12    /* SM    */
1316 #define IOPW_RES_ADDR_14        0x14
1317 #define IOPW_FLASH_ADDR         0x16    /* FA    */
1318 #define IOPW_RES_ADDR_18        0x18
1319 #define IOPW_EE_CMD             0x1A    /* EC    */
1320 #define IOPW_EE_DATA            0x1C    /* ED    */
1321 #define IOPW_SFIFO_CNT          0x1E    /* SFC   */
1322 #define IOPW_RES_ADDR_20        0x20
1323 #define IOPW_Q_BASE             0x22    /* QB    */
1324 #define IOPW_QP                 0x24    /* QP    */
1325 #define IOPW_IX                 0x26    /* IX    */
1326 #define IOPW_SP                 0x28    /* SP    */
1327 #define IOPW_PC                 0x2A    /* PC    */
1328 #define IOPW_RES_ADDR_2C        0x2C
1329 #define IOPW_RES_ADDR_2E        0x2E
1330 #define IOPW_SCSI_DATA          0x30    /* SD    */
1331 #define IOPW_SCSI_DATA_HSHK     0x32    /* SDH   */
1332 #define IOPW_SCSI_CTRL          0x34    /* SC    */
1333 #define IOPW_HSHK_CFG           0x36    /* HCFG  */
1334 #define IOPW_SXFR_STATUS        0x36    /* SXS   */
1335 #define IOPW_SXFR_CNTL          0x38    /* SXL   */
1336 #define IOPW_SXFR_CNTH          0x3A    /* SXH   */
1337 #define IOPW_RES_ADDR_3C        0x3C
1338 #define IOPW_RFIFO_DATA         0x3E    /* RFD   */
1339 
1340 /*
1341  * Doubleword I/O register address from base of 'iop_base'.
1342  */
1343 #define IOPDW_RES_ADDR_0         0x00
1344 #define IOPDW_RAM_DATA           0x04
1345 #define IOPDW_RES_ADDR_8         0x08
1346 #define IOPDW_RES_ADDR_C         0x0C
1347 #define IOPDW_RES_ADDR_10        0x10
1348 #define IOPDW_COMMA              0x14
1349 #define IOPDW_COMMB              0x18
1350 #define IOPDW_RES_ADDR_1C        0x1C
1351 #define IOPDW_SDMA_ADDR0         0x20
1352 #define IOPDW_SDMA_ADDR1         0x24
1353 #define IOPDW_SDMA_COUNT         0x28
1354 #define IOPDW_SDMA_ERROR         0x2C
1355 #define IOPDW_RDMA_ADDR0         0x30
1356 #define IOPDW_RDMA_ADDR1         0x34
1357 #define IOPDW_RDMA_COUNT         0x38
1358 #define IOPDW_RDMA_ERROR         0x3C
1359 
1360 #define ADV_CHIP_ID_BYTE         0x25
1361 #define ADV_CHIP_ID_WORD         0x04C1
1362 
1363 #define ADV_INTR_ENABLE_HOST_INTR                   0x01
1364 #define ADV_INTR_ENABLE_SEL_INTR                    0x02
1365 #define ADV_INTR_ENABLE_DPR_INTR                    0x04
1366 #define ADV_INTR_ENABLE_RTA_INTR                    0x08
1367 #define ADV_INTR_ENABLE_RMA_INTR                    0x10
1368 #define ADV_INTR_ENABLE_RST_INTR                    0x20
1369 #define ADV_INTR_ENABLE_DPE_INTR                    0x40
1370 #define ADV_INTR_ENABLE_GLOBAL_INTR                 0x80
1371 
1372 #define ADV_INTR_STATUS_INTRA            0x01
1373 #define ADV_INTR_STATUS_INTRB            0x02
1374 #define ADV_INTR_STATUS_INTRC            0x04
1375 
1376 #define ADV_RISC_CSR_STOP           (0x0000)
1377 #define ADV_RISC_TEST_COND          (0x2000)
1378 #define ADV_RISC_CSR_RUN            (0x4000)
1379 #define ADV_RISC_CSR_SINGLE_STEP    (0x8000)
1380 
1381 #define ADV_CTRL_REG_HOST_INTR      0x0100
1382 #define ADV_CTRL_REG_SEL_INTR       0x0200
1383 #define ADV_CTRL_REG_DPR_INTR       0x0400
1384 #define ADV_CTRL_REG_RTA_INTR       0x0800
1385 #define ADV_CTRL_REG_RMA_INTR       0x1000
1386 #define ADV_CTRL_REG_RES_BIT14      0x2000
1387 #define ADV_CTRL_REG_DPE_INTR       0x4000
1388 #define ADV_CTRL_REG_POWER_DONE     0x8000
1389 #define ADV_CTRL_REG_ANY_INTR       0xFF00
1390 
1391 #define ADV_CTRL_REG_CMD_RESET             0x00C6
1392 #define ADV_CTRL_REG_CMD_WR_IO_REG         0x00C5
1393 #define ADV_CTRL_REG_CMD_RD_IO_REG         0x00C4
1394 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE  0x00C3
1395 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE  0x00C2
1396 
1397 #define ADV_TICKLE_NOP                      0x00
1398 #define ADV_TICKLE_A                        0x01
1399 #define ADV_TICKLE_B                        0x02
1400 #define ADV_TICKLE_C                        0x03
1401 
1402 #define AdvIsIntPending(port) \
1403     (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1404 
1405 /*
1406  * SCSI_CFG0 Register bit definitions
1407  */
1408 #define TIMER_MODEAB    0xC000  /* Watchdog, Second, and Select. Timer Ctrl. */
1409 #define PARITY_EN       0x2000  /* Enable SCSI Parity Error detection */
1410 #define EVEN_PARITY     0x1000  /* Select Even Parity */
1411 #define WD_LONG         0x0800  /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1412 #define QUEUE_128       0x0400  /* Queue Size, 1: 128 byte, 0: 64 byte */
1413 #define PRIM_MODE       0x0100  /* Primitive SCSI mode */
1414 #define SCAM_EN         0x0080  /* Enable SCAM selection */
1415 #define SEL_TMO_LONG    0x0040  /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1416 #define CFRM_ID         0x0020  /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1417 #define OUR_ID_EN       0x0010  /* Enable OUR_ID bits */
1418 #define OUR_ID          0x000F  /* SCSI ID */
1419 
1420 /*
1421  * SCSI_CFG1 Register bit definitions
1422  */
1423 #define BIG_ENDIAN      0x8000  /* Enable Big Endian Mode MIO:15, EEP:15 */
1424 #define TERM_POL        0x2000  /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1425 #define SLEW_RATE       0x1000  /* SCSI output buffer slew rate */
1426 #define FILTER_SEL      0x0C00  /* Filter Period Selection */
1427 #define  FLTR_DISABLE    0x0000 /* Input Filtering Disabled */
1428 #define  FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1429 #define  FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1430 #define ACTIVE_DBL      0x0200  /* Disable Active Negation */
1431 #define DIFF_MODE       0x0100  /* SCSI differential Mode (Read-Only) */
1432 #define DIFF_SENSE      0x0080  /* 1: No SE cables, 0: SE cable (Read-Only) */
1433 #define TERM_CTL_SEL    0x0040  /* Enable TERM_CTL_H and TERM_CTL_L */
1434 #define TERM_CTL        0x0030  /* External SCSI Termination Bits */
1435 #define  TERM_CTL_H      0x0020 /* Enable External SCSI Upper Termination */
1436 #define  TERM_CTL_L      0x0010 /* Enable External SCSI Lower Termination */
1437 #define CABLE_DETECT    0x000F  /* External SCSI Cable Connection Status */
1438 
1439 /*
1440  * Addendum for ASC-38C0800 Chip
1441  *
1442  * The ASC-38C1600 Chip uses the same definitions except that the
1443  * bus mode override bits [12:10] have been moved to byte register
1444  * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1445  * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1446  * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1447  * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1448  * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1449  */
1450 #define DIS_TERM_DRV    0x4000  /* 1: Read c_det[3:0], 0: cannot read */
1451 #define HVD_LVD_SE      0x1C00  /* Device Detect Bits */
1452 #define  HVD             0x1000 /* HVD Device Detect */
1453 #define  LVD             0x0800 /* LVD Device Detect */
1454 #define  SE              0x0400 /* SE Device Detect */
1455 #define TERM_LVD        0x00C0  /* LVD Termination Bits */
1456 #define  TERM_LVD_HI     0x0080 /* Enable LVD Upper Termination */
1457 #define  TERM_LVD_LO     0x0040 /* Enable LVD Lower Termination */
1458 #define TERM_SE         0x0030  /* SE Termination Bits */
1459 #define  TERM_SE_HI      0x0020 /* Enable SE Upper Termination */
1460 #define  TERM_SE_LO      0x0010 /* Enable SE Lower Termination */
1461 #define C_DET_LVD       0x000C  /* LVD Cable Detect Bits */
1462 #define  C_DET3          0x0008 /* Cable Detect for LVD External Wide */
1463 #define  C_DET2          0x0004 /* Cable Detect for LVD Internal Wide */
1464 #define C_DET_SE        0x0003  /* SE Cable Detect Bits */
1465 #define  C_DET1          0x0002 /* Cable Detect for SE Internal Wide */
1466 #define  C_DET0          0x0001 /* Cable Detect for SE Internal Narrow */
1467 
1468 #define CABLE_ILLEGAL_A 0x7
1469     /* x 0 0 0  | on  on | Illegal (all 3 connectors are used) */
1470 
1471 #define CABLE_ILLEGAL_B 0xB
1472     /* 0 x 0 0  | on  on | Illegal (all 3 connectors are used) */
1473 
1474 /*
1475  * MEM_CFG Register bit definitions
1476  */
1477 #define BIOS_EN         0x40    /* BIOS Enable MIO:14,EEP:14 */
1478 #define FAST_EE_CLK     0x20    /* Diagnostic Bit */
1479 #define RAM_SZ          0x1C    /* Specify size of RAM to RISC */
1480 #define  RAM_SZ_2KB      0x00   /* 2 KB */
1481 #define  RAM_SZ_4KB      0x04   /* 4 KB */
1482 #define  RAM_SZ_8KB      0x08   /* 8 KB */
1483 #define  RAM_SZ_16KB     0x0C   /* 16 KB */
1484 #define  RAM_SZ_32KB     0x10   /* 32 KB */
1485 #define  RAM_SZ_64KB     0x14   /* 64 KB */
1486 
1487 /*
1488  * DMA_CFG0 Register bit definitions
1489  *
1490  * This register is only accessible to the host.
1491  */
1492 #define BC_THRESH_ENB   0x80    /* PCI DMA Start Conditions */
1493 #define FIFO_THRESH     0x70    /* PCI DMA FIFO Threshold */
1494 #define  FIFO_THRESH_16B  0x00  /* 16 bytes */
1495 #define  FIFO_THRESH_32B  0x20  /* 32 bytes */
1496 #define  FIFO_THRESH_48B  0x30  /* 48 bytes */
1497 #define  FIFO_THRESH_64B  0x40  /* 64 bytes */
1498 #define  FIFO_THRESH_80B  0x50  /* 80 bytes (default) */
1499 #define  FIFO_THRESH_96B  0x60  /* 96 bytes */
1500 #define  FIFO_THRESH_112B 0x70  /* 112 bytes */
1501 #define START_CTL       0x0C    /* DMA start conditions */
1502 #define  START_CTL_TH    0x00   /* Wait threshold level (default) */
1503 #define  START_CTL_ID    0x04   /* Wait SDMA/SBUS idle */
1504 #define  START_CTL_THID  0x08   /* Wait threshold and SDMA/SBUS idle */
1505 #define  START_CTL_EMFU  0x0C   /* Wait SDMA FIFO empty/full */
1506 #define READ_CMD        0x03    /* Memory Read Method */
1507 #define  READ_CMD_MR     0x00   /* Memory Read */
1508 #define  READ_CMD_MRL    0x02   /* Memory Read Long */
1509 #define  READ_CMD_MRM    0x03   /* Memory Read Multiple (default) */
1510 
1511 /*
1512  * ASC-38C0800 RAM BIST Register bit definitions
1513  */
1514 #define RAM_TEST_MODE         0x80
1515 #define PRE_TEST_MODE         0x40
1516 #define NORMAL_MODE           0x00
1517 #define RAM_TEST_DONE         0x10
1518 #define RAM_TEST_STATUS       0x0F
1519 #define  RAM_TEST_HOST_ERROR   0x08
1520 #define  RAM_TEST_INTRAM_ERROR 0x04
1521 #define  RAM_TEST_RISC_ERROR   0x02
1522 #define  RAM_TEST_SCSI_ERROR   0x01
1523 #define  RAM_TEST_SUCCESS      0x00
1524 #define PRE_TEST_VALUE        0x05
1525 #define NORMAL_VALUE          0x00
1526 
1527 /*
1528  * ASC38C1600 Definitions
1529  *
1530  * IOPB_PCI_INT_CFG Bit Field Definitions
1531  */
1532 
1533 #define INTAB_LD        0x80    /* Value loaded from EEPROM Bit 11. */
1534 
1535 /*
1536  * Bit 1 can be set to change the interrupt for the Function to operate in
1537  * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1538  * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1539  * mode, otherwise the operating mode is undefined.
1540  */
1541 #define TOTEMPOLE       0x02
1542 
1543 /*
1544  * Bit 0 can be used to change the Int Pin for the Function. The value is
1545  * 0 by default for both Functions with Function 0 using INT A and Function
1546  * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1547  * INT A is used.
1548  *
1549  * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1550  * value specified in the PCI Configuration Space.
1551  */
1552 #define INTAB           0x01
1553 
1554 /*
1555  * Adv Library Status Definitions
1556  */
1557 #define ADV_TRUE        1
1558 #define ADV_FALSE       0
1559 #define ADV_SUCCESS     1
1560 #define ADV_BUSY        0
1561 #define ADV_ERROR       (-1)
1562 
1563 /*
1564  * ADV_DVC_VAR 'warn_code' values
1565  */
1566 #define ASC_WARN_BUSRESET_ERROR         0x0001  /* SCSI Bus Reset error */
1567 #define ASC_WARN_EEPROM_CHKSUM          0x0002  /* EEP check sum error */
1568 #define ASC_WARN_EEPROM_TERMINATION     0x0004  /* EEP termination bad field */
1569 #define ASC_WARN_ERROR                  0xFFFF  /* ADV_ERROR return */
1570 
1571 #define ADV_MAX_TID                     15      /* max. target identifier */
1572 #define ADV_MAX_LUN                     7       /* max. logical unit number */
1573 
1574 /*
1575  * Fixed locations of microcode operating variables.
1576  */
1577 #define ASC_MC_CODE_BEGIN_ADDR          0x0028  /* microcode start address */
1578 #define ASC_MC_CODE_END_ADDR            0x002A  /* microcode end address */
1579 #define ASC_MC_CODE_CHK_SUM             0x002C  /* microcode code checksum */
1580 #define ASC_MC_VERSION_DATE             0x0038  /* microcode version */
1581 #define ASC_MC_VERSION_NUM              0x003A  /* microcode number */
1582 #define ASC_MC_BIOSMEM                  0x0040  /* BIOS RISC Memory Start */
1583 #define ASC_MC_BIOSLEN                  0x0050  /* BIOS RISC Memory Length */
1584 #define ASC_MC_BIOS_SIGNATURE           0x0058  /* BIOS Signature 0x55AA */
1585 #define ASC_MC_BIOS_VERSION             0x005A  /* BIOS Version (2 bytes) */
1586 #define ASC_MC_SDTR_SPEED1              0x0090  /* SDTR Speed for TID 0-3 */
1587 #define ASC_MC_SDTR_SPEED2              0x0092  /* SDTR Speed for TID 4-7 */
1588 #define ASC_MC_SDTR_SPEED3              0x0094  /* SDTR Speed for TID 8-11 */
1589 #define ASC_MC_SDTR_SPEED4              0x0096  /* SDTR Speed for TID 12-15 */
1590 #define ASC_MC_CHIP_TYPE                0x009A
1591 #define ASC_MC_INTRB_CODE               0x009B
1592 #define ASC_MC_WDTR_ABLE                0x009C
1593 #define ASC_MC_SDTR_ABLE                0x009E
1594 #define ASC_MC_TAGQNG_ABLE              0x00A0
1595 #define ASC_MC_DISC_ENABLE              0x00A2
1596 #define ASC_MC_IDLE_CMD_STATUS          0x00A4
1597 #define ASC_MC_IDLE_CMD                 0x00A6
1598 #define ASC_MC_IDLE_CMD_PARAMETER       0x00A8
1599 #define ASC_MC_DEFAULT_SCSI_CFG0        0x00AC
1600 #define ASC_MC_DEFAULT_SCSI_CFG1        0x00AE
1601 #define ASC_MC_DEFAULT_MEM_CFG          0x00B0
1602 #define ASC_MC_DEFAULT_SEL_MASK         0x00B2
1603 #define ASC_MC_SDTR_DONE                0x00B6
1604 #define ASC_MC_NUMBER_OF_QUEUED_CMD     0x00C0
1605 #define ASC_MC_NUMBER_OF_MAX_CMD        0x00D0
1606 #define ASC_MC_DEVICE_HSHK_CFG_TABLE    0x0100
1607 #define ASC_MC_CONTROL_FLAG             0x0122  /* Microcode control flag. */
1608 #define ASC_MC_WDTR_DONE                0x0124
1609 #define ASC_MC_CAM_MODE_MASK            0x015E  /* CAM mode TID bitmask. */
1610 #define ASC_MC_ICQ                      0x0160
1611 #define ASC_MC_IRQ                      0x0164
1612 #define ASC_MC_PPR_ABLE                 0x017A
1613 
1614 /*
1615  * BIOS LRAM variable absolute offsets.
1616  */
1617 #define BIOS_CODESEG    0x54
1618 #define BIOS_CODELEN    0x56
1619 #define BIOS_SIGNATURE  0x58
1620 #define BIOS_VERSION    0x5A
1621 
1622 /*
1623  * Microcode Control Flags
1624  *
1625  * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1626  * and handled by the microcode.
1627  */
1628 #define CONTROL_FLAG_IGNORE_PERR        0x0001  /* Ignore DMA Parity Errors */
1629 #define CONTROL_FLAG_ENABLE_AIPP        0x0002  /* Enabled AIPP checking. */
1630 
1631 /*
1632  * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1633  */
1634 #define HSHK_CFG_WIDE_XFR       0x8000
1635 #define HSHK_CFG_RATE           0x0F00
1636 #define HSHK_CFG_OFFSET         0x001F
1637 
1638 #define ASC_DEF_MAX_HOST_QNG    0xFD    /* Max. number of host commands (253) */
1639 #define ASC_DEF_MIN_HOST_QNG    0x10    /* Min. number of host commands (16) */
1640 #define ASC_DEF_MAX_DVC_QNG     0x3F    /* Max. number commands per device (63) */
1641 #define ASC_DEF_MIN_DVC_QNG     0x04    /* Min. number commands per device (4) */
1642 
1643 #define ASC_QC_DATA_CHECK  0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1644 #define ASC_QC_DATA_OUT    0x02 /* Data out DMA transfer. */
1645 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1646 #define ASC_QC_NO_OVERRUN  0x08 /* Don't report overrun. */
1647 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1648 
1649 #define ASC_QSC_NO_DISC     0x01        /* Don't allow disconnect for request. */
1650 #define ASC_QSC_NO_TAGMSG   0x02        /* Don't allow tag queuing for request. */
1651 #define ASC_QSC_NO_SYNC     0x04        /* Don't use Synch. transfer on request. */
1652 #define ASC_QSC_NO_WIDE     0x08        /* Don't use Wide transfer on request. */
1653 #define ASC_QSC_REDO_DTR    0x10        /* Renegotiate WDTR/SDTR before request. */
1654 /*
1655  * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1656  * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1657  */
1658 #define ASC_QSC_HEAD_TAG    0x40        /* Use Head Tag Message (0x21). */
1659 #define ASC_QSC_ORDERED_TAG 0x80        /* Use Ordered Tag Message (0x22). */
1660 
1661 /*
1662  * All fields here are accessed by the board microcode and need to be
1663  * little-endian.
1664  */
1665 typedef struct adv_carr_t {
1666         __le32 carr_va; /* Carrier Virtual Address */
1667         __le32 carr_pa; /* Carrier Physical Address */
1668         __le32 areq_vpa;        /* ADV_SCSI_REQ_Q Virtual or Physical Address */
1669         /*
1670          * next_vpa [31:4]            Carrier Virtual or Physical Next Pointer
1671          *
1672          * next_vpa [3:1]             Reserved Bits
1673          * next_vpa [0]               Done Flag set in Response Queue.
1674          */
1675         __le32 next_vpa;
1676 } ADV_CARR_T;
1677 
1678 /*
1679  * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1680  */
1681 #define ADV_NEXT_VPA_MASK       0xFFFFFFF0
1682 
1683 #define ADV_RQ_DONE             0x00000001
1684 #define ADV_RQ_GOOD             0x00000002
1685 #define ADV_CQ_STOPPER          0x00000000
1686 
1687 #define ADV_GET_CARRP(carrp) ((carrp) & ADV_NEXT_VPA_MASK)
1688 
1689 /*
1690  * Each carrier is 64 bytes, and we need three additional
1691  * carrier for icq, irq, and the termination carrier.
1692  */
1693 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 3)
1694 
1695 #define ADV_CARRIER_BUFSIZE \
1696         (ADV_CARRIER_COUNT * sizeof(ADV_CARR_T))
1697 
1698 #define ADV_CHIP_ASC3550          0x01  /* Ultra-Wide IC */
1699 #define ADV_CHIP_ASC38C0800       0x02  /* Ultra2-Wide/LVD IC */
1700 #define ADV_CHIP_ASC38C1600       0x03  /* Ultra3-Wide/LVD2 IC */
1701 
1702 /*
1703  * Adapter temporary configuration structure
1704  *
1705  * This structure can be discarded after initialization. Don't add
1706  * fields here needed after initialization.
1707  *
1708  * Field naming convention:
1709  *
1710  *  *_enable indicates the field enables or disables a feature. The
1711  *  value of the field is never reset.
1712  */
1713 typedef struct adv_dvc_cfg {
1714         ushort disc_enable;     /* enable disconnection */
1715         uchar chip_version;     /* chip version */
1716         uchar termination;      /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
1717         ushort control_flag;    /* Microcode Control Flag */
1718         ushort mcode_date;      /* Microcode date */
1719         ushort mcode_version;   /* Microcode version */
1720         ushort serial1;         /* EEPROM serial number word 1 */
1721         ushort serial2;         /* EEPROM serial number word 2 */
1722         ushort serial3;         /* EEPROM serial number word 3 */
1723 } ADV_DVC_CFG;
1724 
1725 struct adv_dvc_var;
1726 struct adv_scsi_req_q;
1727 
1728 typedef struct adv_sg_block {
1729         uchar reserved1;
1730         uchar reserved2;
1731         uchar reserved3;
1732         uchar sg_cnt;           /* Valid entries in block. */
1733         __le32 sg_ptr;  /* Pointer to next sg block. */
1734         struct {
1735                 __le32 sg_addr; /* SG element address. */
1736                 __le32 sg_count;        /* SG element count. */
1737         } sg_list[NO_OF_SG_PER_BLOCK];
1738 } ADV_SG_BLOCK;
1739 
1740 /*
1741  * ADV_SCSI_REQ_Q - microcode request structure
1742  *
1743  * All fields in this structure up to byte 60 are used by the microcode.
1744  * The microcode makes assumptions about the size and ordering of fields
1745  * in this structure. Do not change the structure definition here without
1746  * coordinating the change with the microcode.
1747  *
1748  * All fields accessed by microcode must be maintained in little_endian
1749  * order.
1750  */
1751 typedef struct adv_scsi_req_q {
1752         uchar cntl;             /* Ucode flags and state (ASC_MC_QC_*). */
1753         uchar target_cmd;
1754         uchar target_id;        /* Device target identifier. */
1755         uchar target_lun;       /* Device target logical unit number. */
1756         __le32 data_addr;       /* Data buffer physical address. */
1757         __le32 data_cnt;        /* Data count. Ucode sets to residual. */
1758         __le32 sense_addr;
1759         __le32 carr_pa;
1760         uchar mflag;
1761         uchar sense_len;
1762         uchar cdb_len;          /* SCSI CDB length. Must <= 16 bytes. */
1763         uchar scsi_cntl;
1764         uchar done_status;      /* Completion status. */
1765         uchar scsi_status;      /* SCSI status byte. */
1766         uchar host_status;      /* Ucode host status. */
1767         uchar sg_working_ix;
1768         uchar cdb[12];          /* SCSI CDB bytes 0-11. */
1769         __le32 sg_real_addr;    /* SG list physical address. */
1770         __le32 scsiq_rptr;
1771         uchar cdb16[4];         /* SCSI CDB bytes 12-15. */
1772         __le32 scsiq_ptr;
1773         __le32 carr_va;
1774         /*
1775          * End of microcode structure - 60 bytes. The rest of the structure
1776          * is used by the Adv Library and ignored by the microcode.
1777          */
1778         u32 srb_tag;
1779         ADV_SG_BLOCK *sg_list_ptr;      /* SG list virtual address. */
1780 } ADV_SCSI_REQ_Q;
1781 
1782 /*
1783  * The following two structures are used to process Wide Board requests.
1784  *
1785  * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
1786  * and microcode with the ADV_SCSI_REQ_Q field 'srb_tag' set to the
1787  * SCSI request tag. The adv_req_t structure 'cmndp' field in turn points
1788  * to the Mid-Level SCSI request structure.
1789  *
1790  * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
1791  * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
1792  * up to 255 scatter-gather elements may be used per request or
1793  * ADV_SCSI_REQ_Q.
1794  *
1795  * Both structures must be 32 byte aligned.
1796  */
1797 typedef struct adv_sgblk {
1798         ADV_SG_BLOCK sg_block;  /* Sgblock structure. */
1799         dma_addr_t sg_addr;     /* Physical address */
1800         struct adv_sgblk *next_sgblkp;  /* Next scatter-gather structure. */
1801 } adv_sgblk_t;
1802 
1803 typedef struct adv_req {
1804         ADV_SCSI_REQ_Q scsi_req_q;      /* Adv Library request structure. */
1805         uchar align[24];        /* Request structure padding. */
1806         struct scsi_cmnd *cmndp;        /* Mid-Level SCSI command pointer. */
1807         dma_addr_t req_addr;
1808         adv_sgblk_t *sgblkp;    /* Adv Library scatter-gather pointer. */
1809 } adv_req_t __aligned(32);
1810 
1811 /*
1812  * Adapter operation variable structure.
1813  *
1814  * One structure is required per host adapter.
1815  *
1816  * Field naming convention:
1817  *
1818  *  *_able indicates both whether a feature should be enabled or disabled
1819  *  and whether a device isi capable of the feature. At initialization
1820  *  this field may be set, but later if a device is found to be incapable
1821  *  of the feature, the field is cleared.
1822  */
1823 typedef struct adv_dvc_var {
1824         AdvPortAddr iop_base;   /* I/O port address */
1825         ushort err_code;        /* fatal error code */
1826         ushort bios_ctrl;       /* BIOS control word, EEPROM word 12 */
1827         ushort wdtr_able;       /* try WDTR for a device */
1828         ushort sdtr_able;       /* try SDTR for a device */
1829         ushort ultra_able;      /* try SDTR Ultra speed for a device */
1830         ushort sdtr_speed1;     /* EEPROM SDTR Speed for TID 0-3   */
1831         ushort sdtr_speed2;     /* EEPROM SDTR Speed for TID 4-7   */
1832         ushort sdtr_speed3;     /* EEPROM SDTR Speed for TID 8-11  */
1833         ushort sdtr_speed4;     /* EEPROM SDTR Speed for TID 12-15 */
1834         ushort tagqng_able;     /* try tagged queuing with a device */
1835         ushort ppr_able;        /* PPR message capable per TID bitmask. */
1836         uchar max_dvc_qng;      /* maximum number of tagged commands per device */
1837         ushort start_motor;     /* start motor command allowed */
1838         uchar scsi_reset_wait;  /* delay in seconds after scsi bus reset */
1839         uchar chip_no;          /* should be assigned by caller */
1840         uchar max_host_qng;     /* maximum number of Q'ed command allowed */
1841         ushort no_scam;         /* scam_tolerant of EEPROM */
1842         struct asc_board *drv_ptr;      /* driver pointer to private structure */
1843         uchar chip_scsi_id;     /* chip SCSI target ID */
1844         uchar chip_type;
1845         uchar bist_err_code;
1846         ADV_CARR_T *carrier;
1847         ADV_CARR_T *carr_freelist;      /* Carrier free list. */
1848         dma_addr_t carrier_addr;
1849         ADV_CARR_T *icq_sp;     /* Initiator command queue stopper pointer. */
1850         ADV_CARR_T *irq_sp;     /* Initiator response queue stopper pointer. */
1851         ushort carr_pending_cnt;        /* Count of pending carriers. */
1852         /*
1853          * Note: The following fields will not be used after initialization. The
1854          * driver may discard the buffer after initialization is done.
1855          */
1856         ADV_DVC_CFG *cfg;       /* temporary configuration structure  */
1857 } ADV_DVC_VAR;
1858 
1859 /*
1860  * Microcode idle loop commands
1861  */
1862 #define IDLE_CMD_COMPLETED           0
1863 #define IDLE_CMD_STOP_CHIP           0x0001
1864 #define IDLE_CMD_STOP_CHIP_SEND_INT  0x0002
1865 #define IDLE_CMD_SEND_INT            0x0004
1866 #define IDLE_CMD_ABORT               0x0008
1867 #define IDLE_CMD_DEVICE_RESET        0x0010
1868 #define IDLE_CMD_SCSI_RESET_START    0x0020     /* Assert SCSI Bus Reset */
1869 #define IDLE_CMD_SCSI_RESET_END      0x0040     /* Deassert SCSI Bus Reset */
1870 #define IDLE_CMD_SCSIREQ             0x0080
1871 
1872 #define IDLE_CMD_STATUS_SUCCESS      0x0001
1873 #define IDLE_CMD_STATUS_FAILURE      0x0002
1874 
1875 /*
1876  * AdvSendIdleCmd() flag definitions.
1877  */
1878 #define ADV_NOWAIT     0x01
1879 
1880 /*
1881  * Wait loop time out values.
1882  */
1883 #define SCSI_WAIT_100_MSEC           100UL      /* 100 milliseconds */
1884 #define SCSI_US_PER_MSEC             1000       /* microseconds per millisecond */
1885 #define SCSI_MAX_RETRY               10 /* retry count */
1886 
1887 #define ADV_ASYNC_RDMA_FAILURE          0x01    /* Fatal RDMA failure. */
1888 #define ADV_ASYNC_SCSI_BUS_RESET_DET    0x02    /* Detected SCSI Bus Reset. */
1889 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03    /* Carrier Ready failure. */
1890 #define ADV_RDMA_IN_CARR_AND_Q_INVALID  0x04    /* RDMAed-in data invalid. */
1891 
1892 #define ADV_HOST_SCSI_BUS_RESET      0x80       /* Host Initiated SCSI Bus Reset. */
1893 
1894 /* Read byte from a register. */
1895 #define AdvReadByteRegister(iop_base, reg_off) \
1896      (ADV_MEM_READB((iop_base) + (reg_off)))
1897 
1898 /* Write byte to a register. */
1899 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
1900      (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
1901 
1902 /* Read word (2 bytes) from a register. */
1903 #define AdvReadWordRegister(iop_base, reg_off) \
1904      (ADV_MEM_READW((iop_base) + (reg_off)))
1905 
1906 /* Write word (2 bytes) to a register. */
1907 #define AdvWriteWordRegister(iop_base, reg_off, word) \
1908      (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
1909 
1910 /* Write dword (4 bytes) to a register. */
1911 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
1912      (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
1913 
1914 /* Read byte from LRAM. */
1915 #define AdvReadByteLram(iop_base, addr, byte) \
1916 do { \
1917     ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
1918     (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
1919 } while (0)
1920 
1921 /* Write byte to LRAM. */
1922 #define AdvWriteByteLram(iop_base, addr, byte) \
1923     (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1924      ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
1925 
1926 /* Read word (2 bytes) from LRAM. */
1927 #define AdvReadWordLram(iop_base, addr, word) \
1928 do { \
1929     ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
1930     (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
1931 } while (0)
1932 
1933 /* Write word (2 bytes) to LRAM. */
1934 #define AdvWriteWordLram(iop_base, addr, word) \
1935     (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1936      ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
1937 
1938 /* Write little-endian double word (4 bytes) to LRAM */
1939 /* Because of unspecified C language ordering don't use auto-increment. */
1940 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
1941     ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1942       ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
1943                      cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
1944      (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
1945       ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
1946                      cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
1947 
1948 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
1949 #define AdvReadWordAutoIncLram(iop_base) \
1950      (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
1951 
1952 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
1953 #define AdvWriteWordAutoIncLram(iop_base, word) \
1954      (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
1955 
1956 /*
1957  * Define macro to check for Condor signature.
1958  *
1959  * Evaluate to ADV_TRUE if a Condor chip is found the specified port
1960  * address 'iop_base'. Otherwise evalue to ADV_FALSE.
1961  */
1962 #define AdvFindSignature(iop_base) \
1963     (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
1964     ADV_CHIP_ID_BYTE) && \
1965      (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
1966     ADV_CHIP_ID_WORD)) ?  ADV_TRUE : ADV_FALSE)
1967 
1968 /*
1969  * Define macro to Return the version number of the chip at 'iop_base'.
1970  *
1971  * The second parameter 'bus_type' is currently unused.
1972  */
1973 #define AdvGetChipVersion(iop_base, bus_type) \
1974     AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
1975 
1976 /*
1977  * Abort an SRB in the chip's RISC Memory. The 'srb_tag' argument must
1978  * match the ADV_SCSI_REQ_Q 'srb_tag' field.
1979  *
1980  * If the request has not yet been sent to the device it will simply be
1981  * aborted from RISC memory. If the request is disconnected it will be
1982  * aborted on reselection by sending an Abort Message to the target ID.
1983  *
1984  * Return value:
1985  *      ADV_TRUE(1) - Queue was successfully aborted.
1986  *      ADV_FALSE(0) - Queue was not found on the active queue list.
1987  */
1988 #define AdvAbortQueue(asc_dvc, srb_tag) \
1989      AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
1990                     (ADV_DCNT) (srb_tag))
1991 
1992 /*
1993  * Send a Bus Device Reset Message to the specified target ID.
1994  *
1995  * All outstanding commands will be purged if sending the
1996  * Bus Device Reset Message is successful.
1997  *
1998  * Return Value:
1999  *      ADV_TRUE(1) - All requests on the target are purged.
2000  *      ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2001  *                     are not purged.
2002  */
2003 #define AdvResetDevice(asc_dvc, target_id) \
2004      AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET,  \
2005                     (ADV_DCNT) (target_id))
2006 
2007 /*
2008  * SCSI Wide Type definition.
2009  */
2010 #define ADV_SCSI_BIT_ID_TYPE   ushort
2011 
2012 /*
2013  * AdvInitScsiTarget() 'cntl_flag' options.
2014  */
2015 #define ADV_SCAN_LUN           0x01
2016 #define ADV_CAPINFO_NOLUN      0x02
2017 
2018 /*
2019  * Convert target id to target id bit mask.
2020  */
2021 #define ADV_TID_TO_TIDMASK(tid)   (0x01 << ((tid) & ADV_MAX_TID))
2022 
2023 /*
2024  * ADV_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2025  */
2026 
2027 #define QD_NO_STATUS         0x00       /* Request not completed yet. */
2028 #define QD_NO_ERROR          0x01
2029 #define QD_ABORTED_BY_HOST   0x02
2030 #define QD_WITH_ERROR        0x04
2031 
2032 #define QHSTA_NO_ERROR              0x00
2033 #define QHSTA_M_SEL_TIMEOUT         0x11
2034 #define QHSTA_M_DATA_OVER_RUN       0x12
2035 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2036 #define QHSTA_M_QUEUE_ABORTED       0x15
2037 #define QHSTA_M_SXFR_SDMA_ERR       0x16        /* SXFR_STATUS SCSI DMA Error */
2038 #define QHSTA_M_SXFR_SXFR_PERR      0x17        /* SXFR_STATUS SCSI Bus Parity Error */
2039 #define QHSTA_M_RDMA_PERR           0x18        /* RISC PCI DMA parity error */
2040 #define QHSTA_M_SXFR_OFF_UFLW       0x19        /* SXFR_STATUS Offset Underflow */
2041 #define QHSTA_M_SXFR_OFF_OFLW       0x20        /* SXFR_STATUS Offset Overflow */
2042 #define QHSTA_M_SXFR_WD_TMO         0x21        /* SXFR_STATUS Watchdog Timeout */
2043 #define QHSTA_M_SXFR_DESELECTED     0x22        /* SXFR_STATUS Deselected */
2044 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
2045 #define QHSTA_M_SXFR_XFR_OFLW       0x12        /* SXFR_STATUS Transfer Overflow */
2046 #define QHSTA_M_SXFR_XFR_PH_ERR     0x24        /* SXFR_STATUS Transfer Phase Error */
2047 #define QHSTA_M_SXFR_UNKNOWN_ERROR  0x25        /* SXFR_STATUS Unknown Error */
2048 #define QHSTA_M_SCSI_BUS_RESET      0x30        /* Request aborted from SBR */
2049 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31       /* Request aborted from unsol. SBR */
2050 #define QHSTA_M_BUS_DEVICE_RESET    0x32        /* Request aborted from BDR */
2051 #define QHSTA_M_DIRECTION_ERR       0x35        /* Data Phase mismatch */
2052 #define QHSTA_M_DIRECTION_ERR_HUNG  0x36        /* Data Phase mismatch and bus hang */
2053 #define QHSTA_M_WTM_TIMEOUT         0x41
2054 #define QHSTA_M_BAD_CMPL_STATUS_IN  0x42
2055 #define QHSTA_M_NO_AUTO_REQ_SENSE   0x43
2056 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
2057 #define QHSTA_M_INVALID_DEVICE      0x45        /* Bad target ID */
2058 #define QHSTA_M_FROZEN_TIDQ         0x46        /* TID Queue frozen. */
2059 #define QHSTA_M_SGBACKUP_ERROR      0x47        /* Scatter-Gather backup error */
2060 
2061 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
2062 #define ADV_32BALIGN(addr)     (((ulong) (addr) + 0x1F) & ~0x1F)
2063 
2064 /*
2065  * Total contiguous memory needed for driver SG blocks.
2066  *
2067  * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2068  * number of scatter-gather elements the driver supports in a
2069  * single request.
2070  */
2071 
2072 #define ADV_SG_LIST_MAX_BYTE_SIZE \
2073          (sizeof(ADV_SG_BLOCK) * \
2074           ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2075 
2076 /* struct asc_board flags */
2077 #define ASC_IS_WIDE_BOARD       0x04    /* AdvanSys Wide Board */
2078 
2079 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
2080 
2081 #define NO_ISA_DMA              0xff    /* No ISA DMA Channel Used */
2082 
2083 #define ASC_INFO_SIZE           128     /* advansys_info() line size */
2084 
2085 /* Asc Library return codes */
2086 #define ASC_TRUE        1
2087 #define ASC_FALSE       0
2088 #define ASC_NOERROR     1
2089 #define ASC_BUSY        0
2090 #define ASC_ERROR       (-1)
2091 
2092 /* struct scsi_cmnd function return codes */
2093 #define STATUS_BYTE(byte)   (byte)
2094 #define MSG_BYTE(byte)      ((byte) << 8)
2095 #define HOST_BYTE(byte)     ((byte) << 16)
2096 #define DRIVER_BYTE(byte)   ((byte) << 24)
2097 
2098 #define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
2099 #ifndef ADVANSYS_STATS
2100 #define ASC_STATS_ADD(shost, counter, count)
2101 #else /* ADVANSYS_STATS */
2102 #define ASC_STATS_ADD(shost, counter, count) \
2103         (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
2104 #endif /* ADVANSYS_STATS */
2105 
2106 /* If the result wraps when calculating tenths, return 0. */
2107 #define ASC_TENTHS(num, den) \
2108     (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2109     0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2110 
2111 /*
2112  * Display a message to the console.
2113  */
2114 #define ASC_PRINT(s) \
2115     { \
2116         printk("advansys: "); \
2117         printk(s); \
2118     }
2119 
2120 #define ASC_PRINT1(s, a1) \
2121     { \
2122         printk("advansys: "); \
2123         printk((s), (a1)); \
2124     }
2125 
2126 #define ASC_PRINT2(s, a1, a2) \
2127     { \
2128         printk("advansys: "); \
2129         printk((s), (a1), (a2)); \
2130     }
2131 
2132 #define ASC_PRINT3(s, a1, a2, a3) \
2133     { \
2134         printk("advansys: "); \
2135         printk((s), (a1), (a2), (a3)); \
2136     }
2137 
2138 #define ASC_PRINT4(s, a1, a2, a3, a4) \
2139     { \
2140         printk("advansys: "); \
2141         printk((s), (a1), (a2), (a3), (a4)); \
2142     }
2143 
2144 #ifndef ADVANSYS_DEBUG
2145 
2146 #define ASC_DBG(lvl, s...)
2147 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
2148 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2149 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2150 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2151 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2152 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
2153 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
2154 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
2155 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2156 
2157 #else /* ADVANSYS_DEBUG */
2158 
2159 /*
2160  * Debugging Message Levels:
2161  * 0: Errors Only
2162  * 1: High-Level Tracing
2163  * 2-N: Verbose Tracing
2164  */
2165 
2166 #define ASC_DBG(lvl, format, arg...) {                                  \
2167         if (asc_dbglvl >= (lvl))                                        \
2168                 printk(KERN_DEBUG "%s: %s: " format, DRV_NAME,          \
2169                         __func__ , ## arg);                             \
2170 }
2171 
2172 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2173     { \
2174         if (asc_dbglvl >= (lvl)) { \
2175             asc_prt_scsi_host(s); \
2176         } \
2177     }
2178 
2179 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2180     { \
2181         if (asc_dbglvl >= (lvl)) { \
2182             asc_prt_asc_scsi_q(scsiqp); \
2183         } \
2184     }
2185 
2186 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2187     { \
2188         if (asc_dbglvl >= (lvl)) { \
2189             asc_prt_asc_qdone_info(qdone); \
2190         } \
2191     }
2192 
2193 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2194     { \
2195         if (asc_dbglvl >= (lvl)) { \
2196             asc_prt_adv_scsi_req_q(scsiqp); \
2197         } \
2198     }
2199 
2200 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2201     { \
2202         if (asc_dbglvl >= (lvl)) { \
2203             asc_prt_hex((name), (start), (length)); \
2204         } \
2205     }
2206 
2207 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2208         ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2209 
2210 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2211         ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2212 
2213 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2214         ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2215 #endif /* ADVANSYS_DEBUG */
2216 
2217 #ifdef ADVANSYS_STATS
2218 
2219 /* Per board statistics structure */
2220 struct asc_stats {
2221         /* Driver Entrypoint Statistics */
2222         unsigned int queuecommand;      /* # calls to advansys_queuecommand() */
2223         unsigned int reset;             /* # calls to advansys_eh_bus_reset() */
2224         unsigned int biosparam; /* # calls to advansys_biosparam() */
2225         unsigned int interrupt; /* # advansys_interrupt() calls */
2226         unsigned int callback;  /* # calls to asc/adv_isr_callback() */
2227         unsigned int done;              /* # calls to request's scsi_done function */
2228         unsigned int build_error;       /* # asc/adv_build_req() ASC_ERROR returns. */
2229         unsigned int adv_build_noreq;   /* # adv_build_req() adv_req_t alloc. fail. */
2230         unsigned int adv_build_nosg;    /* # adv_build_req() adv_sgblk_t alloc. fail. */
2231         /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2232         unsigned int exe_noerror;       /* # ASC_NOERROR returns. */
2233         unsigned int exe_busy;  /* # ASC_BUSY returns. */
2234         unsigned int exe_error; /* # ASC_ERROR returns. */
2235         unsigned int exe_unknown;       /* # unknown returns. */
2236         /* Data Transfer Statistics */
2237         unsigned int xfer_cnt;  /* # I/O requests received */
2238         unsigned int xfer_elem; /* # scatter-gather elements */
2239         unsigned int xfer_sect; /* # 512-byte blocks */
2240 };
2241 #endif /* ADVANSYS_STATS */
2242 
2243 /*
2244  * Structure allocated for each board.
2245  *
2246  * This structure is allocated by scsi_host_alloc() at the end
2247  * of the 'Scsi_Host' structure starting at the 'hostdata'
2248  * field. It is guaranteed to be allocated from DMA-able memory.
2249  */
2250 struct asc_board {
2251         struct device *dev;
2252         struct Scsi_Host *shost;
2253         uint flags;             /* Board flags */
2254         unsigned int irq;
2255         union {
2256                 ASC_DVC_VAR asc_dvc_var;        /* Narrow board */
2257                 ADV_DVC_VAR adv_dvc_var;        /* Wide board */
2258         } dvc_var;
2259         union {
2260                 ASC_DVC_CFG asc_dvc_cfg;        /* Narrow board */
2261                 ADV_DVC_CFG adv_dvc_cfg;        /* Wide board */
2262         } dvc_cfg;
2263         ushort asc_n_io_port;   /* Number I/O ports. */
2264         ADV_SCSI_BIT_ID_TYPE init_tidmask;      /* Target init./valid mask */
2265         ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2266         ADV_SCSI_BIT_ID_TYPE queue_full;        /* Queue full mask */
2267         ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2268         union {
2269                 ASCEEP_CONFIG asc_eep;  /* Narrow EEPROM config. */
2270                 ADVEEP_3550_CONFIG adv_3550_eep;        /* 3550 EEPROM config. */
2271                 ADVEEP_38C0800_CONFIG adv_38C0800_eep;  /* 38C0800 EEPROM config. */
2272                 ADVEEP_38C1600_CONFIG adv_38C1600_eep;  /* 38C1600 EEPROM config. */
2273         } eep_config;
2274         /* /proc/scsi/advansys/[0...] */
2275 #ifdef ADVANSYS_STATS
2276         struct asc_stats asc_stats;     /* Board statistics */
2277 #endif                          /* ADVANSYS_STATS */
2278         /*
2279          * The following fields are used only for Narrow Boards.
2280          */
2281         uchar sdtr_data[ASC_MAX_TID + 1];       /* SDTR information */
2282         /*
2283          * The following fields are used only for Wide Boards.
2284          */
2285         void __iomem *ioremap_addr;     /* I/O Memory remap address. */
2286         ushort ioport;          /* I/O Port address. */
2287         adv_req_t *adv_reqp;    /* Request structures. */
2288         dma_addr_t adv_reqp_addr;
2289         size_t adv_reqp_size;
2290         struct dma_pool *adv_sgblk_pool;        /* Scatter-gather structures. */
2291         ushort bios_signature;  /* BIOS Signature. */
2292         ushort bios_version;    /* BIOS Version. */
2293         ushort bios_codeseg;    /* BIOS Code Segment. */
2294         ushort bios_codelen;    /* BIOS Code Segment Length. */
2295 };
2296 
2297 #define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \
2298                                                         dvc_var.asc_dvc_var)
2299 #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2300                                                         dvc_var.adv_dvc_var)
2301 #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2302 
2303 #ifdef ADVANSYS_DEBUG
2304 static int asc_dbglvl = 3;
2305 
2306 /*
2307  * asc_prt_asc_dvc_var()
2308  */
2309 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
2310 {
2311         printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
2312 
2313         printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2314                "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2315 
2316         printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2317                 (unsigned)h->init_sdtr);
2318 
2319         printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2320                "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2321                (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2322                (unsigned)h->chip_no);
2323 
2324         printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2325                "%u,\n", (unsigned)h->queue_full_or_busy,
2326                (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2327 
2328         printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2329                "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2330                (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2331                (unsigned)h->in_critical_cnt);
2332 
2333         printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2334                "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2335                (unsigned)h->init_state, (unsigned)h->no_scam,
2336                (unsigned)h->pci_fix_asyn_xfer);
2337 
2338         printk(" cfg 0x%lx\n", (ulong)h->cfg);
2339 }
2340 
2341 /*
2342  * asc_prt_asc_dvc_cfg()
2343  */
2344 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
2345 {
2346         printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
2347 
2348         printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2349                h->can_tagged_qng, h->cmd_qng_enabled);
2350         printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2351                h->disc_enable, h->sdtr_enable);
2352 
2353         printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
2354                 "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
2355                 h->isa_dma_channel, h->chip_version);
2356 
2357         printk(" mcode_date 0x%x, mcode_version %d\n",
2358                 h->mcode_date, h->mcode_version);
2359 }
2360 
2361 /*
2362  * asc_prt_adv_dvc_var()
2363  *
2364  * Display an ADV_DVC_VAR structure.
2365  */
2366 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
2367 {
2368         printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
2369 
2370         printk("  iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2371                (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
2372 
2373         printk("  sdtr_able 0x%x, wdtr_able 0x%x\n",
2374                (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
2375 
2376         printk("  start_motor 0x%x, scsi_reset_wait 0x%x\n",
2377                (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2378 
2379         printk("  max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%p\n",
2380                (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2381                h->carr_freelist);
2382 
2383         printk("  icq_sp 0x%p, irq_sp 0x%p\n", h->icq_sp, h->irq_sp);
2384 
2385         printk("  no_scam 0x%x, tagqng_able 0x%x\n",
2386                (unsigned)h->no_scam, (unsigned)h->tagqng_able);
2387 
2388         printk("  chip_scsi_id 0x%x, cfg 0x%lx\n",
2389                (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2390 }
2391 
2392 /*
2393  * asc_prt_adv_dvc_cfg()
2394  *
2395  * Display an ADV_DVC_CFG structure.
2396  */
2397 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2398 {
2399         printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
2400 
2401         printk("  disc_enable 0x%x, termination 0x%x\n",
2402                h->disc_enable, h->termination);
2403 
2404         printk("  chip_version 0x%x, mcode_date 0x%x\n",
2405                h->chip_version, h->mcode_date);
2406 
2407         printk("  mcode_version 0x%x, control_flag 0x%x\n",
2408                h->mcode_version, h->control_flag);
2409 }
2410 
2411 /*
2412  * asc_prt_scsi_host()
2413  */
2414 static void asc_prt_scsi_host(struct Scsi_Host *s)
2415 {
2416         struct asc_board *boardp = shost_priv(s);
2417 
2418         printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev));
2419         printk(" host_busy %u, host_no %d,\n",
2420                atomic_read(&s->host_busy), s->host_no);
2421 
2422         printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
2423                (ulong)s->base, (ulong)s->io_port, boardp->irq);
2424 
2425         printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2426                s->dma_channel, s->this_id, s->can_queue);
2427 
2428         printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2429                s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
2430 
2431         if (ASC_NARROW_BOARD(boardp)) {
2432                 asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
2433                 asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
2434         } else {
2435                 asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
2436                 asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
2437         }
2438 }
2439 
2440 /*
2441  * asc_prt_hex()
2442  *
2443  * Print hexadecimal output in 4 byte groupings 32 bytes
2444  * or 8 double-words per line.
2445  */
2446 static void asc_prt_hex(char *f, uchar *s, int l)
2447 {
2448         int i;
2449         int j;
2450         int k;
2451         int m;
2452 
2453         printk("%s: (%d bytes)\n", f, l);
2454 
2455         for (i = 0; i < l; i += 32) {
2456 
2457                 /* Display a maximum of 8 double-words per line. */
2458                 if ((k = (l - i) / 4) >= 8) {
2459                         k = 8;
2460                         m = 0;
2461                 } else {
2462                         m = (l - i) % 4;
2463                 }
2464 
2465                 for (j = 0; j < k; j++) {
2466                         printk(" %2.2X%2.2X%2.2X%2.2X",
2467                                (unsigned)s[i + (j * 4)],
2468                                (unsigned)s[i + (j * 4) + 1],
2469                                (unsigned)s[i + (j * 4) + 2],
2470                                (unsigned)s[i + (j * 4) + 3]);
2471                 }
2472 
2473                 switch (m) {
2474                 case 0:
2475                 default:
2476                         break;
2477                 case 1:
2478                         printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2479                         break;
2480                 case 2:
2481                         printk(" %2.2X%2.2X",
2482                                (unsigned)s[i + (j * 4)],
2483                                (unsigned)s[i + (j * 4) + 1]);
2484                         break;
2485                 case 3:
2486                         printk(" %2.2X%2.2X%2.2X",
2487                                (unsigned)s[i + (j * 4) + 1],
2488                                (unsigned)s[i + (j * 4) + 2],
2489                                (unsigned)s[i + (j * 4) + 3]);
2490                         break;
2491                 }
2492 
2493                 printk("\n");
2494         }
2495 }
2496 
2497 /*
2498  * asc_prt_asc_scsi_q()
2499  */
2500 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2501 {
2502         ASC_SG_HEAD *sgp;
2503         int i;
2504 
2505         printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2506 
2507         printk
2508             (" target_ix 0x%x, target_lun %u, srb_tag 0x%x, tag_code 0x%x,\n",
2509              q->q2.target_ix, q->q1.target_lun, q->q2.srb_tag,
2510              q->q2.tag_code);
2511 
2512         printk
2513             (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2514              (ulong)le32_to_cpu(q->q1.data_addr),
2515              (ulong)le32_to_cpu(q->q1.data_cnt),
2516              (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2517 
2518         printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2519                (ulong)q->cdbptr, q->q2.cdb_len,
2520                (ulong)q->sg_head, q->q1.sg_queue_cnt);
2521 
2522         if (q->sg_head) {
2523                 sgp = q->sg_head;
2524                 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2525                 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2526                        sgp->queue_cnt);
2527                 for (i = 0; i < sgp->entry_cnt; i++) {
2528                         printk(" [%u]: addr 0x%lx, bytes %lu\n",
2529                                i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2530                                (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2531                 }
2532 
2533         }
2534 }
2535 
2536 /*
2537  * asc_prt_asc_qdone_info()
2538  */
2539 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2540 {
2541         printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
2542         printk(" srb_tag 0x%x, target_ix %u, cdb_len %u, tag_code %u,\n",
2543                q->d2.srb_tag, q->d2.target_ix, q->d2.cdb_len,
2544                q->d2.tag_code);
2545         printk
2546             (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2547              q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2548 }
2549 
2550 /*
2551  * asc_prt_adv_sgblock()
2552  *
2553  * Display an ADV_SG_BLOCK structure.
2554  */
2555 static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2556 {
2557         int i;
2558 
2559         printk(" ADV_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2560                (ulong)b, sgblockno);
2561         printk("  sg_cnt %u, sg_ptr 0x%x\n",
2562                b->sg_cnt, (u32)le32_to_cpu(b->sg_ptr));
2563         BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2564         if (b->sg_ptr != 0)
2565                 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2566         for (i = 0; i < b->sg_cnt; i++) {
2567                 printk("  [%u]: sg_addr 0x%x, sg_count 0x%x\n",
2568                        i, (u32)le32_to_cpu(b->sg_list[i].sg_addr),
2569                        (u32)le32_to_cpu(b->sg_list[i].sg_count));
2570         }
2571 }
2572 
2573 /*
2574  * asc_prt_adv_scsi_req_q()
2575  *
2576  * Display an ADV_SCSI_REQ_Q structure.
2577  */
2578 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2579 {
2580         int sg_blk_cnt;
2581         struct adv_sg_block *sg_ptr;
2582         adv_sgblk_t *sgblkp;
2583 
2584         printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2585 
2586         printk("  target_id %u, target_lun %u, srb_tag 0x%x\n",
2587                q->target_id, q->target_lun, q->srb_tag);
2588 
2589         printk("  cntl 0x%x, data_addr 0x%lx\n",
2590                q->cntl, (ulong)le32_to_cpu(q->data_addr));
2591 
2592         printk("  data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2593                (ulong)le32_to_cpu(q->data_cnt),
2594                (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2595 
2596         printk
2597             ("  cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2598              q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2599 
2600         printk("  sg_working_ix 0x%x, target_cmd %u\n",
2601                q->sg_working_ix, q->target_cmd);
2602 
2603         printk("  scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2604                (ulong)le32_to_cpu(q->scsiq_rptr),
2605                (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2606 
2607         /* Display the request's ADV_SG_BLOCK structures. */
2608         if (q->sg_list_ptr != NULL) {
2609                 sgblkp = container_of(q->sg_list_ptr, adv_sgblk_t, sg_block);
2610                 sg_blk_cnt = 0;
2611                 while (sgblkp) {
2612                         sg_ptr = &sgblkp->sg_block;
2613                         asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2614                         if (sg_ptr->sg_ptr == 0) {
2615                                 break;
2616                         }
2617                         sgblkp = sgblkp->next_sgblkp;
2618                         sg_blk_cnt++;
2619                 }
2620         }
2621 }
2622 #endif /* ADVANSYS_DEBUG */
2623 
2624 /*
2625  * advansys_info()
2626  *
2627  * Return suitable for printing on the console with the argument
2628  * adapter's configuration information.
2629  *
2630  * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2631  * otherwise the static 'info' array will be overrun.
2632  */
2633 static const char *advansys_info(struct Scsi_Host *shost)
2634 {
2635         static char info[ASC_INFO_SIZE];
2636         struct asc_board *boardp = shost_priv(shost);
2637         ASC_DVC_VAR *asc_dvc_varp;
2638         ADV_DVC_VAR *adv_dvc_varp;
2639         char *busname;
2640         char *widename = NULL;
2641 
2642         if (ASC_NARROW_BOARD(boardp)) {
2643                 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2644                 ASC_DBG(1, "begin\n");
2645                 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2646                         if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2647                             ASC_IS_ISAPNP) {
2648                                 busname = "ISA PnP";
2649                         } else {
2650                                 busname = "ISA";
2651                         }
2652                         sprintf(info,
2653                                 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2654                                 ASC_VERSION, busname,
2655                                 (ulong)shost->io_port,
2656                                 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2657                                 boardp->irq, shost->dma_channel);
2658                 } else {
2659                         if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2660                                 busname = "VL";
2661                         } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2662                                 busname = "EISA";
2663                         } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2664                                 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2665                                     == ASC_IS_PCI_ULTRA) {
2666                                         busname = "PCI Ultra";
2667                                 } else {
2668                                         busname = "PCI";
2669                                 }
2670                         } else {
2671                                 busname = "?";
2672                                 shost_printk(KERN_ERR, shost, "unknown bus "
2673                                         "type %d\n", asc_dvc_varp->bus_type);
2674                         }
2675                         sprintf(info,
2676                                 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2677                                 ASC_VERSION, busname, (ulong)shost->io_port,
2678                                 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2679                                 boardp->irq);
2680                 }
2681         } else {
2682                 /*
2683                  * Wide Adapter Information
2684                  *
2685                  * Memory-mapped I/O is used instead of I/O space to access
2686                  * the adapter, but display the I/O Port range. The Memory
2687                  * I/O address is displayed through the driver /proc file.
2688                  */
2689                 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2690                 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2691                         widename = "Ultra-Wide";
2692                 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2693                         widename = "Ultra2-Wide";
2694                 } else {
2695                         widename = "Ultra3-Wide";
2696                 }
2697                 sprintf(info,
2698                         "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2699                         ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
2700                         (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
2701         }
2702         BUG_ON(strlen(info) >= ASC_INFO_SIZE);
2703         ASC_DBG(1, "end\n");
2704         return info;
2705 }
2706 
2707 #ifdef CONFIG_PROC_FS
2708 
2709 /*
2710  * asc_prt_board_devices()
2711  *
2712  * Print driver information for devices attached to the board.
2713  */
2714 static void asc_prt_board_devices(struct seq_file *m, struct Scsi_Host *shost)
2715 {
2716         struct asc_board *boardp = shost_priv(shost);
2717         int chip_scsi_id;
2718         int i;
2719 
2720         seq_printf(m,
2721                    "\nDevice Information for AdvanSys SCSI Host %d:\n",
2722                    shost->host_no);
2723 
2724         if (ASC_NARROW_BOARD(boardp)) {
2725                 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
2726         } else {
2727                 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
2728         }
2729 
2730         seq_puts(m, "Target IDs Detected:");
2731         for (i = 0; i <= ADV_MAX_TID; i++) {
2732                 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i))
2733                         seq_printf(m, " %X,", i);
2734         }
2735         seq_printf(m, " (%X=Host Adapter)\n", chip_scsi_id);
2736 }
2737 
2738 /*
2739  * Display Wide Board BIOS Information.
2740  */
2741 static void asc_prt_adv_bios(struct seq_file *m, struct Scsi_Host *shost)
2742 {
2743         struct asc_board *boardp = shost_priv(shost);
2744         ushort major, minor, letter;
2745 
2746         seq_puts(m, "\nROM BIOS Version: ");
2747 
2748         /*
2749          * If the BIOS saved a valid signature, then fill in
2750          * the BIOS code segment base address.
2751          */
2752         if (boardp->bios_signature != 0x55AA) {
2753                 seq_puts(m, "Disabled or Pre-3.1\n"
2754                         "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n"
2755                         "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
2756         } else {
2757                 major = (boardp->bios_version >> 12) & 0xF;
2758                 minor = (boardp->bios_version >> 8) & 0xF;
2759                 letter = (boardp->bios_version & 0xFF);
2760 
2761                 seq_printf(m, "%d.%d%c\n",
2762                                    major, minor,
2763                                    letter >= 26 ? '?' : letter + 'A');
2764                 /*
2765                  * Current available ROM BIOS release is 3.1I for UW
2766                  * and 3.2I for U2W. This code doesn't differentiate
2767                  * UW and U2W boards.
2768                  */
2769                 if (major < 3 || (major <= 3 && minor < 1) ||
2770                     (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
2771                         seq_puts(m, "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n"
2772                                 "ftp://ftp.connectcom.net/pub\n");
2773                 }
2774         }
2775 }
2776 
2777 /*
2778  * Add serial number to information bar if signature AAh
2779  * is found in at bit 15-9 (7 bits) of word 1.
2780  *
2781  * Serial Number consists fo 12 alpha-numeric digits.
2782  *
2783  *       1 - Product type (A,B,C,D..)  Word0: 15-13 (3 bits)
2784  *       2 - MFG Location (A,B,C,D..)  Word0: 12-10 (3 bits)
2785  *     3-4 - Product ID (0-99)         Word0: 9-0 (10 bits)
2786  *       5 - Product revision (A-J)    Word0:  "         "
2787  *
2788  *           Signature                 Word1: 15-9 (7 bits)
2789  *       6 - Year (0-9)                Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
2790  *     7-8 - Week of the year (1-52)   Word1: 5-0 (6 bits)
2791  *
2792  *    9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
2793  *
2794  * Note 1: Only production cards will have a serial number.
2795  *
2796  * Note 2: Signature is most significant 7 bits (0xFE).
2797  *
2798  * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
2799  */
2800 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
2801 {
2802         ushort w, num;
2803 
2804         if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
2805                 return ASC_FALSE;
2806         } else {
2807                 /*
2808                  * First word - 6 digits.
2809                  */
2810                 w = serialnum[0];
2811 
2812                 /* Product type - 1st digit. */
2813                 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
2814                         /* Product type is P=Prototype */
2815                         *cp += 0x8;
2816                 }
2817                 cp++;
2818 
2819                 /* Manufacturing location - 2nd digit. */
2820                 *cp++ = 'A' + ((w & 0x1C00) >> 10);
2821 
2822                 /* Product ID - 3rd, 4th digits. */
2823                 num = w & 0x3FF;
2824                 *cp++ = '' + (num / 100);
2825                 num %= 100;
2826                 *cp++ = '' + (num / 10);
2827 
2828                 /* Product revision - 5th digit. */
2829                 *cp++ = 'A' + (num % 10);
2830 
2831                 /*
2832                  * Second word
2833                  */
2834                 w = serialnum[1];
2835 
2836                 /*
2837                  * Year - 6th digit.
2838                  *
2839                  * If bit 15 of third word is set, then the
2840                  * last digit of the year is greater than 7.
2841                  */
2842                 if (serialnum[2] & 0x8000) {
2843                         *cp++ = '8' + ((w & 0x1C0) >> 6);
2844                 } else {
2845                         *cp++ = '' + ((w & 0x1C0) >> 6);
2846                 }
2847 
2848                 /* Week of year - 7th, 8th digits. */
2849                 num = w & 0x003F;
2850                 *cp++ = '' + num / 10;
2851                 num %= 10;
2852                 *cp++ = '' + num;
2853 
2854                 /*
2855                  * Third word
2856                  */
2857                 w = serialnum[2] & 0x7FFF;
2858 
2859                 /* Serial number - 9th digit. */
2860                 *cp++ = 'A' + (w / 1000);
2861 
2862                 /* 10th, 11th, 12th digits. */
2863                 num = w % 1000;
2864                 *cp++ = '' + num / 100;
2865                 num %= 100;
2866                 *cp++ = '' + num / 10;
2867                 num %= 10;
2868                 *cp++ = '' + num;
2869 
2870                 *cp = '\0';     /* Null Terminate the string. */
2871                 return ASC_TRUE;
2872         }
2873 }
2874 
2875 /*
2876  * asc_prt_asc_board_eeprom()
2877  *
2878  * Print board EEPROM configuration.
2879  */
2880 static void asc_prt_asc_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
2881 {
2882         struct asc_board *boardp = shost_priv(shost);
2883         ASC_DVC_VAR *asc_dvc_varp;
2884         ASCEEP_CONFIG *ep;
2885         int i;
2886 #ifdef CONFIG_ISA
2887         int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
2888 #endif /* CONFIG_ISA */
2889         uchar serialstr[13];
2890 
2891         asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2892         ep = &boardp->eep_config.asc_eep;
2893 
2894         seq_printf(m,
2895                    "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
2896                    shost->host_no);
2897 
2898         if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
2899             == ASC_TRUE)
2900                 seq_printf(m, " Serial Number: %s\n", serialstr);
2901         else if (ep->adapter_info[5] == 0xBB)
2902                 seq_puts(m,
2903                          " Default Settings Used for EEPROM-less Adapter.\n");
2904         else
2905                 seq_puts(m, " Serial Number Signature Not Present.\n");
2906 
2907         seq_printf(m,
2908                    " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
2909                    ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
2910                    ep->max_tag_qng);
2911 
2912         seq_printf(m,
2913                    " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
2914 
2915         seq_puts(m, " Target ID:           ");
2916         for (i = 0; i <= ASC_MAX_TID; i++)
2917                 seq_printf(m, " %d", i);
2918 
2919         seq_puts(m, "\n Disconnects:         ");
2920         for (i = 0; i <= ASC_MAX_TID; i++)
2921                 seq_printf(m, " %c",
2922                            (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2923 
2924         seq_puts(m, "\n Command Queuing:     ");
2925         for (i = 0; i <= ASC_MAX_TID; i++)
2926                 seq_printf(m, " %c",
2927                            (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2928 
2929         seq_puts(m, "\n Start Motor:         ");
2930         for (i = 0; i <= ASC_MAX_TID; i++)
2931                 seq_printf(m, " %c",
2932                            (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2933 
2934         seq_puts(m, "\n Synchronous Transfer:");
2935         for (i = 0; i <= ASC_MAX_TID; i++)
2936                 seq_printf(m, " %c",
2937                            (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2938         seq_putc(m, '\n');
2939 
2940 #ifdef CONFIG_ISA
2941         if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2942                 seq_printf(m,
2943                            " Host ISA DMA speed:   %d MB/S\n",
2944                            isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
2945         }
2946 #endif /* CONFIG_ISA */
2947 }
2948 
2949 /*
2950  * asc_prt_adv_board_eeprom()
2951  *
2952  * Print board EEPROM configuration.
2953  */
2954 static void asc_prt_adv_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
2955 {
2956         struct asc_board *boardp = shost_priv(shost);
2957         ADV_DVC_VAR *adv_dvc_varp;
2958         int i;
2959         char *termstr;
2960         uchar serialstr[13];
2961         ADVEEP_3550_CONFIG *ep_3550 = NULL;
2962         ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
2963         ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
2964         ushort word;
2965         ushort *wordp;
2966         ushort sdtr_speed = 0;
2967 
2968         adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2969         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2970                 ep_3550 = &boardp->eep_config.adv_3550_eep;
2971         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2972                 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
2973         } else {
2974                 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
2975         }
2976 
2977         seq_printf(m,
2978                    "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
2979                    shost->host_no);
2980 
2981         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2982                 wordp = &ep_3550->serial_number_word1;
2983         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2984                 wordp = &ep_38C0800->serial_number_word1;
2985         } else {
2986                 wordp = &ep_38C1600->serial_number_word1;
2987         }
2988 
2989         if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE)
2990                 seq_printf(m, " Serial Number: %s\n", serialstr);
2991         else
2992                 seq_puts(m, " Serial Number Signature Not Present.\n");
2993 
2994         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
2995                 seq_printf(m,
2996                            " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
2997                            ep_3550->adapter_scsi_id,
2998                            ep_3550->max_host_qng, ep_3550->max_dvc_qng);
2999         else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3000                 seq_printf(m,
3001                            " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3002                            ep_38C0800->adapter_scsi_id,
3003                            ep_38C0800->max_host_qng,
3004                            ep_38C0800->max_dvc_qng);
3005         else
3006                 seq_printf(m,
3007                            " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3008                            ep_38C1600->adapter_scsi_id,
3009                            ep_38C1600->max_host_qng,
3010                            ep_38C1600->max_dvc_qng);
3011         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3012                 word = ep_3550->termination;
3013         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3014                 word = ep_38C0800->termination_lvd;
3015         } else {
3016                 word = ep_38C1600->termination_lvd;
3017         }
3018         switch (word) {
3019         case 1:
3020                 termstr = "Low Off/High Off";
3021                 break;
3022         case 2:
3023                 termstr = "Low Off/High On";
3024                 break;
3025         case 3:
3026                 termstr = "Low On/High On";
3027                 break;
3028         default:
3029         case 0:
3030                 termstr = "Automatic";
3031                 break;
3032         }
3033 
3034         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3035                 seq_printf(m,
3036                            " termination: %u (%s), bios_ctrl: 0x%x\n",
3037                            ep_3550->termination, termstr,
3038                            ep_3550->bios_ctrl);
3039         else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3040                 seq_printf(m,
3041                            " termination: %u (%s), bios_ctrl: 0x%x\n",
3042                            ep_38C0800->termination_lvd, termstr,
3043                            ep_38C0800->bios_ctrl);
3044         else
3045                 seq_printf(m,
3046                            " termination: %u (%s), bios_ctrl: 0x%x\n",
3047                            ep_38C1600->termination_lvd, termstr,
3048                            ep_38C1600->bios_ctrl);
3049 
3050         seq_puts(m, " Target ID:           ");
3051         for (i = 0; i <= ADV_MAX_TID; i++)
3052                 seq_printf(m, " %X", i);
3053         seq_putc(m, '\n');
3054 
3055         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3056                 word = ep_3550->disc_enable;
3057         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3058                 word = ep_38C0800->disc_enable;
3059         } else {
3060                 word = ep_38C1600->disc_enable;
3061         }
3062         seq_puts(m, " Disconnects:         ");
3063         for (i = 0; i <= ADV_MAX_TID; i++)
3064                 seq_printf(m, " %c",
3065                            (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3066         seq_putc(m, '\n');
3067 
3068         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3069                 word = ep_3550->tagqng_able;
3070         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3071                 word = ep_38C0800->tagqng_able;
3072         } else {
3073                 word = ep_38C1600->tagqng_able;
3074         }
3075         seq_puts(m, " Command Queuing:     ");
3076         for (i = 0; i <= ADV_MAX_TID; i++)
3077                 seq_printf(m, " %c",
3078                            (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3079         seq_putc(m, '\n');
3080 
3081         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3082                 word = ep_3550->start_motor;
3083         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3084                 word = ep_38C0800->start_motor;
3085         } else {
3086                 word = ep_38C1600->start_motor;
3087         }
3088         seq_puts(m, " Start Motor:         ");
3089         for (i = 0; i <= ADV_MAX_TID; i++)
3090                 seq_printf(m, " %c",
3091                            (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3092         seq_putc(m, '\n');
3093 
3094         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3095                 seq_puts(m, " Synchronous Transfer:");
3096                 for (i = 0; i <= ADV_MAX_TID; i++)
3097                         seq_printf(m, " %c",
3098                                    (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3099                                    'Y' : 'N');
3100                 seq_putc(m, '\n');
3101         }
3102 
3103         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3104                 seq_puts(m, " Ultra Transfer:      ");
3105                 for (i = 0; i <= ADV_MAX_TID; i++)
3106                         seq_printf(m, " %c",
3107                                    (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i))
3108                                    ? 'Y' : 'N');
3109                 seq_putc(m, '\n');
3110         }
3111 
3112         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3113                 word = ep_3550->wdtr_able;
3114         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3115                 word = ep_38C0800->wdtr_able;
3116         } else {
3117                 word = ep_38C1600->wdtr_able;
3118         }
3119         seq_puts(m, " Wide Transfer:       ");
3120         for (i = 0; i <= ADV_MAX_TID; i++)
3121                 seq_printf(m, " %c",
3122                            (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3123         seq_putc(m, '\n');
3124 
3125         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3126             adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
3127                 seq_puts(m, " Synchronous Transfer Speed (Mhz):\n  ");
3128                 for (i = 0; i <= ADV_MAX_TID; i++) {
3129                         char *speed_str;
3130 
3131                         if (i == 0) {
3132                                 sdtr_speed = adv_dvc_varp->sdtr_speed1;
3133                         } else if (i == 4) {
3134                                 sdtr_speed = adv_dvc_varp->sdtr_speed2;
3135                         } else if (i == 8) {
3136                                 sdtr_speed = adv_dvc_varp->sdtr_speed3;
3137                         } else if (i == 12) {
3138                                 sdtr_speed = adv_dvc_varp->sdtr_speed4;
3139                         }
3140                         switch (sdtr_speed & ADV_MAX_TID) {
3141                         case 0:
3142                                 speed_str = "Off";
3143                                 break;
3144                         case 1:
3145                                 speed_str = "  5";
3146                                 break;
3147                         case 2:
3148                                 speed_str = " 10";
3149                                 break;
3150                         case 3:
3151                                 speed_str = " 20";
3152                                 break;
3153                         case 4:
3154                                 speed_str = " 40";
3155                                 break;
3156                         case 5:
3157                                 speed_str = " 80";
3158                                 break;
3159                         default:
3160                                 speed_str = "Unk";
3161                                 break;
3162                         }
3163                         seq_printf(m, "%X:%s ", i, speed_str);
3164                         if (i == 7)
3165                                 seq_puts(m, "\n  ");
3166                         sdtr_speed >>= 4;
3167                 }
3168                 seq_putc(m, '\n');
3169         }
3170 }
3171 
3172 /*
3173  * asc_prt_driver_conf()
3174  */
3175 static void asc_prt_driver_conf(struct seq_file *m, struct Scsi_Host *shost)
3176 {
3177         struct asc_board *boardp = shost_priv(shost);
3178         int chip_scsi_id;
3179 
3180         seq_printf(m,
3181                 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3182                 shost->host_no);
3183 
3184         seq_printf(m,
3185                    " host_busy %u, max_id %u, max_lun %llu, max_channel %u\n",
3186                    atomic_read(&shost->host_busy), shost->max_id,
3187                    shost->max_lun, shost->max_channel);
3188 
3189         seq_printf(m,
3190                    " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3191                    shost->unique_id, shost->can_queue, shost->this_id,
3192                    shost->sg_tablesize, shost->cmd_per_lun);
3193 
3194         seq_printf(m,
3195                    " unchecked_isa_dma %d, use_clustering %d\n",
3196                    shost->unchecked_isa_dma, shost->use_clustering);
3197 
3198         seq_printf(m,
3199                    " flags 0x%x, last_reset 0x%lx, jiffies 0x%lx, asc_n_io_port 0x%x\n",
3200                    boardp->flags, shost->last_reset, jiffies,
3201                    boardp->asc_n_io_port);
3202 
3203         seq_printf(m, " io_port 0x%lx\n", shost->io_port);
3204 
3205         if (ASC_NARROW_BOARD(boardp)) {
3206                 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3207         } else {
3208                 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
3209         }
3210 }
3211 
3212 /*
3213  * asc_prt_asc_board_info()
3214  *
3215  * Print dynamic board configuration information.
3216  */
3217 static void asc_prt_asc_board_info(struct seq_file *m, struct Scsi_Host *shost)
3218 {
3219         struct asc_board *boardp = shost_priv(shost);
3220         int chip_scsi_id;
3221         ASC_DVC_VAR *v;
3222         ASC_DVC_CFG *c;
3223         int i;
3224         int renegotiate = 0;
3225 
3226         v = &boardp->dvc_var.asc_dvc_var;
3227         c = &boardp->dvc_cfg.asc_dvc_cfg;
3228         chip_scsi_id = c->chip_scsi_id;
3229 
3230         seq_printf(m,
3231                    "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3232                    shost->host_no);
3233 
3234         seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3235                    "mcode_version 0x%x, err_code %u\n",
3236                    c->chip_version, c->mcode_date, c->mcode_version,
3237                    v->err_code);
3238 
3239         /* Current number of commands waiting for the host. */
3240         seq_printf(m,
3241                    " Total Command Pending: %d\n", v->cur_total_qng);
3242 
3243         seq_puts(m, " Command Queuing:");
3244         for (i = 0; i <= ASC_MAX_TID; i++) {
3245                 if ((chip_scsi_id == i) ||
3246                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3247                         continue;
3248                 }
3249                 seq_printf(m, " %X:%c",
3250                            i,
3251                            (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3252         }
3253 
3254         /* Current number of commands waiting for a device. */
3255         seq_puts(m, "\n Command Queue Pending:");
3256         for (i = 0; i <= ASC_MAX_TID; i++) {
3257                 if ((chip_scsi_id == i) ||
3258                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3259                         continue;
3260                 }
3261                 seq_printf(m, " %X:%u", i, v->cur_dvc_qng[i]);
3262         }
3263 
3264         /* Current limit on number of commands that can be sent to a device. */
3265         seq_puts(m, "\n Command Queue Limit:");
3266         for (i = 0; i <= ASC_MAX_TID; i++) {
3267                 if ((chip_scsi_id == i) ||
3268                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3269                         continue;
3270                 }
3271                 seq_printf(m, " %X:%u", i, v->max_dvc_qng[i]);
3272         }
3273 
3274         /* Indicate whether the device has returned queue full status. */
3275         seq_puts(m, "\n Command Queue Full:");
3276         for (i = 0; i <= ASC_MAX_TID; i++) {
3277                 if ((chip_scsi_id == i) ||
3278                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3279                         continue;
3280                 }
3281                 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i))
3282                         seq_printf(m, " %X:Y-%d",
3283                                    i, boardp->queue_full_cnt[i]);
3284                 else
3285                         seq_printf(m, " %X:N", i);
3286         }
3287 
3288         seq_puts(m, "\n Synchronous Transfer:");
3289         for (i = 0; i <= ASC_MAX_TID; i++) {
3290                 if ((chip_scsi_id == i) ||
3291                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3292                         continue;
3293                 }
3294                 seq_printf(m, " %X:%c",
3295                            i,
3296                            (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3297         }
3298         seq_putc(m, '\n');
3299 
3300         for (i = 0; i <= ASC_MAX_TID; i++) {
3301                 uchar syn_period_ix;
3302 
3303                 if ((chip_scsi_id == i) ||
3304                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3305                     ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3306                         continue;
3307                 }
3308 
3309                 seq_printf(m, "  %X:", i);
3310 
3311                 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
3312                         seq_puts(m, " Asynchronous");
3313                 } else {
3314                         syn_period_ix =
3315                             (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3316                                                            1);
3317 
3318                         seq_printf(m,
3319                                    " Transfer Period Factor: %d (%d.%d Mhz),",
3320                                    v->sdtr_period_tbl[syn_period_ix],
3321                                    250 / v->sdtr_period_tbl[syn_period_ix],
3322                                    ASC_TENTHS(250,
3323                                               v->sdtr_period_tbl[syn_period_ix]));
3324 
3325                         seq_printf(m, " REQ/ACK Offset: %d",
3326                                    boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET);
3327                 }
3328 
3329                 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3330                         seq_puts(m, "*\n");
3331                         renegotiate = 1;
3332                 } else {
3333                         seq_putc(m, '\n');
3334                 }
3335         }
3336 
3337         if (renegotiate) {
3338                 seq_puts(m, " * = Re-negotiation pending before next command.\n");
3339         }
3340 }
3341 
3342 /*
3343  * asc_prt_adv_board_info()
3344  *
3345  * Print dynamic board configuration information.
3346  */
3347 static void asc_prt_adv_board_info(struct seq_file *m, struct Scsi_Host *shost)
3348 {
3349         struct asc_board *boardp = shost_priv(shost);
3350         int i;
3351         ADV_DVC_VAR *v;
3352         ADV_DVC_CFG *c;
3353         AdvPortAddr iop_base;
3354         ushort chip_scsi_id;
3355         ushort lramword;
3356         uchar lrambyte;
3357         ushort tagqng_able;
3358         ushort sdtr_able, wdtr_able;
3359         ushort wdtr_done, sdtr_done;
3360         ushort period = 0;
3361         int renegotiate = 0;
3362 
3363         v = &boardp->dvc_var.adv_dvc_var;
3364         c = &boardp->dvc_cfg.adv_dvc_cfg;
3365         iop_base = v->iop_base;
3366         chip_scsi_id = v->chip_scsi_id;
3367 
3368         seq_printf(m,
3369                    "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3370                    shost->host_no);
3371 
3372         seq_printf(m,
3373                    " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
3374                    (unsigned long)v->iop_base,
3375                    AdvReadWordRegister(iop_base,IOPW_SCSI_CFG1) & CABLE_DETECT,
3376                    v->err_code);
3377 
3378         seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3379                    "mcode_version 0x%x\n", c->chip_version,
3380                    c->mcode_date, c->mcode_version);
3381 
3382         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
3383         seq_puts(m, " Queuing Enabled:");
3384         for (i = 0; i <= ADV_MAX_TID; i++) {
3385                 if ((chip_scsi_id == i) ||
3386                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3387                         continue;
3388                 }
3389 
3390                 seq_printf(m, " %X:%c",
3391                            i,
3392                            (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3393         }
3394 
3395         seq_puts(m, "\n Queue Limit:");
3396         for (i = 0; i <= ADV_MAX_TID; i++) {
3397                 if ((chip_scsi_id == i) ||
3398                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3399                         continue;
3400                 }
3401 
3402                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
3403                                 lrambyte);
3404 
3405                 seq_printf(m, " %X:%d", i, lrambyte);
3406         }
3407 
3408         seq_puts(m, "\n Command Pending:");
3409         for (i = 0; i <= ADV_MAX_TID; i++) {
3410                 if ((chip_scsi_id == i) ||
3411                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3412                         continue;
3413                 }
3414 
3415                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
3416                                 lrambyte);
3417 
3418                 seq_printf(m, " %X:%d", i, lrambyte);
3419         }
3420         seq_putc(m, '\n');
3421 
3422         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
3423         seq_puts(m, " Wide Enabled:");
3424         for (i = 0; i <= ADV_MAX_TID; i++) {
3425                 if ((chip_scsi_id == i) ||
3426                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3427                         continue;
3428                 }
3429 
3430                 seq_printf(m, " %X:%c",
3431                            i,
3432                            (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3433         }
3434         seq_putc(m, '\n');
3435 
3436         AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
3437         seq_puts(m, " Transfer Bit Width:");
3438         for (i = 0; i <= ADV_MAX_TID; i++) {
3439                 if ((chip_scsi_id == i) ||
3440                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3441                         continue;
3442                 }
3443 
3444                 AdvReadWordLram(iop_base,
3445                                 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3446                                 lramword);
3447 
3448                 seq_printf(m, " %X:%d",
3449                            i, (lramword & 0x8000) ? 16 : 8);
3450 
3451                 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
3452                     (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3453                         seq_putc(m, '*');
3454                         renegotiate = 1;
3455                 }
3456         }
3457         seq_putc(m, '\n');
3458 
3459         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
3460         seq_puts(m, " Synchronous Enabled:");
3461         for (i = 0; i <= ADV_MAX_TID; i++) {
3462                 if ((chip_scsi_id == i) ||
3463                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3464                         continue;
3465                 }
3466 
3467                 seq_printf(m, " %X:%c",
3468                            i,
3469                            (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3470         }
3471         seq_putc(m, '\n');
3472 
3473         AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
3474         for (i = 0; i <= ADV_MAX_TID; i++) {
3475 
3476                 AdvReadWordLram(iop_base,
3477                                 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3478                                 lramword);
3479                 lramword &= ~0x8000;
3480 
3481                 if ((chip_scsi_id == i) ||
3482                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3483                     ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
3484                         continue;
3485                 }
3486 
3487                 seq_printf(m, "  %X:", i);
3488 
3489                 if ((lramword & 0x1F) == 0) {   /* Check for REQ/ACK Offset 0. */
3490                         seq_puts(m, " Asynchronous");
3491                 } else {
3492                         seq_puts(m, " Transfer Period Factor: ");
3493 
3494                         if ((lramword & 0x1F00) == 0x1100) {    /* 80 Mhz */
3495                                 seq_puts(m, "9 (80.0 Mhz),");
3496                         } else if ((lramword & 0x1F00) == 0x1000) {     /* 40 Mhz */
3497                                 seq_puts(m, "10 (40.0 Mhz),");
3498                         } else {        /* 20 Mhz or below. */
3499 
3500                                 period = (((lramword >> 8) * 25) + 50) / 4;
3501 
3502                                 if (period == 0) {      /* Should never happen. */
3503                                         seq_printf(m, "%d (? Mhz), ", period);
3504                                 } else {
3505                                         seq_printf(m,
3506                                                    "%d (%d.%d Mhz),",
3507                                                    period, 250 / period,
3508                                                    ASC_TENTHS(250, period));
3509                                 }
3510                         }
3511 
3512                         seq_printf(m, " REQ/ACK Offset: %d",
3513                                    lramword & 0x1F);
3514                 }
3515 
3516                 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3517                         seq_puts(m, "*\n");
3518                         renegotiate = 1;
3519                 } else {
3520                         seq_putc(m, '\n');
3521                 }
3522         }
3523 
3524         if (renegotiate) {
3525                 seq_puts(m, " * = Re-negotiation pending before next command.\n");
3526         }
3527 }
3528 
3529 #ifdef ADVANSYS_STATS
3530 /*
3531  * asc_prt_board_stats()
3532  */
3533 static void asc_prt_board_stats(struct seq_file *m, struct Scsi_Host *shost)
3534 {
3535         struct asc_board *boardp = shost_priv(shost);
3536         struct asc_stats *s = &boardp->asc_stats;
3537 
3538         seq_printf(m,
3539                    "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
3540                    shost->host_no);
3541 
3542         seq_printf(m,
3543                    " queuecommand %u, reset %u, biosparam %u, interrupt %u\n",
3544                    s->queuecommand, s->reset, s->biosparam,
3545                    s->interrupt);
3546 
3547         seq_printf(m,
3548                    " callback %u, done %u, build_error %u, build_noreq %u, build_nosg %u\n",
3549                    s->callback, s->done, s->build_error,
3550                    s->adv_build_noreq, s->adv_build_nosg);
3551 
3552         seq_printf(m,
3553                    " exe_noerror %u, exe_busy %u, exe_error %u, exe_unknown %u\n",
3554                    s->exe_noerror, s->exe_busy, s->exe_error,
3555                    s->exe_unknown);
3556 
3557         /*
3558          * Display data transfer statistics.
3559          */
3560         if (s->xfer_cnt > 0) {
3561                 seq_printf(m, " xfer_cnt %u, xfer_elem %u, ",
3562                            s->xfer_cnt, s->xfer_elem);
3563 
3564                 seq_printf(m, "xfer_bytes %u.%01u kb\n",
3565                            s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2));
3566 
3567                 /* Scatter gather transfer statistics */
3568                 seq_printf(m, " avg_num_elem %u.%01u, ",
3569                            s->xfer_elem / s->xfer_cnt,
3570                            ASC_TENTHS(s->xfer_elem, s->xfer_cnt));
3571 
3572                 seq_printf(m, "avg_elem_size %u.%01u kb, ",
3573                            (s->xfer_sect / 2) / s->xfer_elem,
3574                            ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem));
3575 
3576                 seq_printf(m, "avg_xfer_size %u.%01u kb\n",
3577                            (s->xfer_sect / 2) / s->xfer_cnt,
3578                            ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt));
3579         }
3580 }
3581 #endif /* ADVANSYS_STATS */
3582 
3583 /*
3584  * advansys_show_info() - /proc/scsi/advansys/{0,1,2,3,...}
3585  *
3586  * m: seq_file to print into
3587  * shost: Scsi_Host
3588  *
3589  * Return the number of bytes read from or written to a
3590  * /proc/scsi/advansys/[0...] file.
3591  */
3592 static int
3593 advansys_show_info(struct seq_file *m, struct Scsi_Host *shost)
3594 {
3595         struct asc_board *boardp = shost_priv(shost);
3596 
3597         ASC_DBG(1, "begin\n");
3598 
3599         /*
3600          * User read of /proc/scsi/advansys/[0...] file.
3601          */
3602 
3603         /*
3604          * Get board configuration information.
3605          *
3606          * advansys_info() returns the board string from its own static buffer.
3607          */
3608         /* Copy board information. */
3609         seq_printf(m, "%s\n", (char *)advansys_info(shost));
3610         /*
3611          * Display Wide Board BIOS Information.
3612          */
3613         if (!ASC_NARROW_BOARD(boardp))
3614                 asc_prt_adv_bios(m, shost);
3615 
3616         /*
3617          * Display driver information for each device attached to the board.
3618          */
3619         asc_prt_board_devices(m, shost);
3620 
3621         /*
3622          * Display EEPROM configuration for the board.
3623          */
3624         if (ASC_NARROW_BOARD(boardp))
3625                 asc_prt_asc_board_eeprom(m, shost);
3626         else
3627                 asc_prt_adv_board_eeprom(m, shost);
3628 
3629         /*
3630          * Display driver configuration and information for the board.
3631          */
3632         asc_prt_driver_conf(m, shost);
3633 
3634 #ifdef ADVANSYS_STATS
3635         /*
3636          * Display driver statistics for the board.
3637          */
3638         asc_prt_board_stats(m, shost);
3639 #endif /* ADVANSYS_STATS */
3640 
3641         /*
3642          * Display Asc Library dynamic configuration information
3643          * for the board.
3644          */
3645         if (ASC_NARROW_BOARD(boardp))
3646                 asc_prt_asc_board_info(m, shost);
3647         else
3648                 asc_prt_adv_board_info(m, shost);
3649         return 0;
3650 }
3651 #endif /* CONFIG_PROC_FS */
3652 
3653 static void asc_scsi_done(struct scsi_cmnd *scp)
3654 {
3655         scsi_dma_unmap(scp);
3656         ASC_STATS(scp->device->host, done);
3657         scp->scsi_done(scp);
3658 }
3659 
3660 static void AscSetBank(PortAddr iop_base, uchar bank)
3661 {
3662         uchar val;
3663 
3664         val = AscGetChipControl(iop_base) &
3665             (~
3666              (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
3667               CC_CHIP_RESET));
3668         if (bank == 1) {
3669                 val |= CC_BANK_ONE;
3670         } else if (bank == 2) {
3671                 val |= CC_DIAG | CC_BANK_ONE;
3672         } else {
3673                 val &= ~CC_BANK_ONE;
3674         }
3675         AscSetChipControl(iop_base, val);
3676 }
3677 
3678 static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
3679 {
3680         AscSetBank(iop_base, 1);
3681         AscWriteChipIH(iop_base, ins_code);
3682         AscSetBank(iop_base, 0);
3683 }
3684 
3685 static int AscStartChip(PortAddr iop_base)
3686 {
3687         AscSetChipControl(iop_base, 0);
3688         if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3689                 return (0);
3690         }
3691         return (1);
3692 }
3693 
3694 static bool AscStopChip(PortAddr iop_base)
3695 {
3696         uchar cc_val;
3697 
3698         cc_val =
3699             AscGetChipControl(iop_base) &
3700             (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
3701         AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
3702         AscSetChipIH(iop_base, INS_HALT);
3703         AscSetChipIH(iop_base, INS_RFLAG_WTM);
3704         if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
3705                 return false;
3706         }
3707         return true;
3708 }
3709 
3710 static bool AscIsChipHalted(PortAddr iop_base)
3711 {
3712         if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3713                 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
3714                         return true;
3715                 }
3716         }
3717         return false;
3718 }
3719 
3720 static bool AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
3721 {
3722         PortAddr iop_base;
3723         int i = 10;
3724 
3725         iop_base = asc_dvc->iop_base;
3726         while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
3727                && (i-- > 0)) {
3728                 mdelay(100);
3729         }
3730         AscStopChip(iop_base);
3731         AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
3732         udelay(60);
3733         AscSetChipIH(iop_base, INS_RFLAG_WTM);
3734         AscSetChipIH(iop_base, INS_HALT);
3735         AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
3736         AscSetChipControl(iop_base, CC_HALT);
3737         mdelay(200);
3738         AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
3739         AscSetChipStatus(iop_base, 0);
3740         return (AscIsChipHalted(iop_base));
3741 }
3742 
3743 static int AscFindSignature(PortAddr iop_base)
3744 {
3745         ushort sig_word;
3746 
3747         ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
3748                  iop_base, AscGetChipSignatureByte(iop_base));
3749         if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
3750                 ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
3751                          iop_base, AscGetChipSignatureWord(iop_base));
3752                 sig_word = AscGetChipSignatureWord(iop_base);
3753                 if ((sig_word == (ushort)ASC_1000_ID0W) ||
3754                     (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
3755                         return (1);
3756                 }
3757         }
3758         return (0);
3759 }
3760 
3761 static void AscEnableInterrupt(PortAddr iop_base)
3762 {
3763         ushort cfg;
3764 
3765         cfg = AscGetChipCfgLsw(iop_base);
3766         AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
3767 }
3768 
3769 static void AscDisableInterrupt(PortAddr iop_base)
3770 {
3771         ushort cfg;
3772 
3773         cfg = AscGetChipCfgLsw(iop_base);
3774         AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
3775 }
3776 
3777 static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
3778 {
3779         unsigned char byte_data;
3780         unsigned short word_data;
3781 
3782         if (isodd_word(addr)) {
3783                 AscSetChipLramAddr(iop_base, addr - 1);
3784                 word_data = AscGetChipLramData(iop_base);
3785                 byte_data = (word_data >> 8) & 0xFF;
3786         } else {
3787                 AscSetChipLramAddr(iop_base, addr);
3788                 word_data = AscGetChipLramData(iop_base);
3789                 byte_data = word_data & 0xFF;
3790         }
3791         return byte_data;
3792 }
3793 
3794 static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
3795 {
3796         ushort word_data;
3797 
3798         AscSetChipLramAddr(iop_base, addr);
3799         word_data = AscGetChipLramData(iop_base);
3800         return (word_data);
3801 }
3802 
3803 static void
3804 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
3805 {
3806         int i;
3807 
3808         AscSetChipLramAddr(iop_base, s_addr);
3809         for (i = 0; i < words; i++) {
3810                 AscSetChipLramData(iop_base, set_wval);
3811         }
3812 }
3813 
3814 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
3815 {
3816         AscSetChipLramAddr(iop_base, addr);
3817         AscSetChipLramData(iop_base, word_val);
3818 }
3819 
3820 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
3821 {
3822         ushort word_data;
3823 
3824         if (isodd_word(addr)) {
3825                 addr--;
3826                 word_data = AscReadLramWord(iop_base, addr);
3827                 word_data &= 0x00FF;
3828                 word_data |= (((ushort)byte_val << 8) & 0xFF00);
3829         } else {
3830                 word_data = AscReadLramWord(iop_base, addr);
3831                 word_data &= 0xFF00;
3832                 word_data |= ((ushort)byte_val & 0x00FF);
3833         }
3834         AscWriteLramWord(iop_base, addr, word_data);
3835 }
3836 
3837 /*
3838  * Copy 2 bytes to LRAM.
3839  *
3840  * The source data is assumed to be in little-endian order in memory
3841  * and is maintained in little-endian order when written to LRAM.
3842  */
3843 static void
3844 AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr,
3845                         const uchar *s_buffer, int words)
3846 {
3847         int i;
3848 
3849         AscSetChipLramAddr(iop_base, s_addr);
3850         for (i = 0; i < 2 * words; i += 2) {
3851                 /*
3852                  * On a little-endian system the second argument below
3853                  * produces a little-endian ushort which is written to
3854                  * LRAM in little-endian order. On a big-endian system
3855                  * the second argument produces a big-endian ushort which
3856                  * is "transparently" byte-swapped by outpw() and written
3857                  * in little-endian order to LRAM.
3858                  */
3859                 outpw(iop_base + IOP_RAM_DATA,
3860                       ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
3861         }
3862 }
3863 
3864 /*
3865  * Copy 4 bytes to LRAM.
3866  *
3867  * The source data is assumed to be in little-endian order in memory
3868  * and is maintained in little-endian order when written to LRAM.
3869  */
3870 static void
3871 AscMemDWordCopyPtrToLram(PortAddr iop_base,
3872                          ushort s_addr, uchar *s_buffer, int dwords)
3873 {
3874         int i;
3875 
3876         AscSetChipLramAddr(iop_base, s_addr);
3877         for (i = 0; i < 4 * dwords; i += 4) {
3878                 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);   /* LSW */
3879                 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]);       /* MSW */
3880         }
3881 }
3882 
3883 /*
3884  * Copy 2 bytes from LRAM.
3885  *
3886  * The source data is assumed to be in little-endian order in LRAM
3887  * and is maintained in little-endian order when written to memory.
3888  */
3889 static void
3890 AscMemWordCopyPtrFromLram(PortAddr iop_base,
3891                           ushort s_addr, uchar *d_buffer, int words)
3892 {
3893         int i;
3894         ushort word;
3895 
3896         AscSetChipLramAddr(iop_base, s_addr);
3897         for (i = 0; i < 2 * words; i += 2) {
3898                 word = inpw(iop_base + IOP_RAM_DATA);
3899                 d_buffer[i] = word & 0xff;
3900                 d_buffer[i + 1] = (word >> 8) & 0xff;
3901         }
3902 }
3903 
3904 static u32 AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
3905 {
3906         u32 sum = 0;
3907         int i;
3908 
3909         for (i = 0; i < words; i++, s_addr += 2) {
3910                 sum += AscReadLramWord(iop_base, s_addr);
3911         }
3912         return (sum);
3913 }
3914 
3915 static void AscInitLram(ASC_DVC_VAR *asc_dvc)
3916 {
3917         uchar i;
3918         ushort s_addr;
3919         PortAddr iop_base;
3920 
3921         iop_base = asc_dvc->iop_base;
3922         AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
3923                           (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
3924                                     64) >> 1));
3925         i = ASC_MIN_ACTIVE_QNO;
3926         s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
3927         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
3928                          (uchar)(i + 1));
3929         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
3930                          (uchar)(asc_dvc->max_total_qng));
3931         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
3932                          (uchar)i);
3933         i++;
3934         s_addr += ASC_QBLK_SIZE;
3935         for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
3936                 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
3937                                  (uchar)(i + 1));
3938                 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
3939                                  (uchar)(i - 1));
3940                 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
3941                                  (uchar)i);
3942         }
3943         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
3944                          (uchar)ASC_QLINK_END);
3945         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
3946                          (uchar)(asc_dvc->max_total_qng - 1));
3947         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
3948                          (uchar)asc_dvc->max_total_qng);
3949         i++;
3950         s_addr += ASC_QBLK_SIZE;
3951         for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
3952              i++, s_addr += ASC_QBLK_SIZE) {
3953                 AscWriteLramByte(iop_base,
3954                                  (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
3955                 AscWriteLramByte(iop_base,
3956                                  (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
3957                 AscWriteLramByte(iop_base,
3958                                  (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
3959         }
3960 }
3961 
3962 static u32
3963 AscLoadMicroCode(PortAddr iop_base, ushort s_addr,
3964                  const uchar *mcode_buf, ushort mcode_size)
3965 {
3966         u32 chksum;
3967         ushort mcode_word_size;
3968         ushort mcode_chksum;
3969 
3970         /* Write the microcode buffer starting at LRAM address 0. */
3971         mcode_word_size = (ushort)(mcode_size >> 1);
3972         AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
3973         AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
3974 
3975         chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
3976         ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum);
3977         mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
3978                                                  (ushort)ASC_CODE_SEC_BEG,
3979                                                  (ushort)((mcode_size -
3980                                                            s_addr - (ushort)
3981                                                            ASC_CODE_SEC_BEG) /
3982                                                           2));
3983         ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum);
3984         AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
3985         AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
3986         return chksum;
3987 }
3988 
3989 static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
3990 {
3991         PortAddr iop_base;
3992         int i;
3993         ushort lram_addr;
3994 
3995         iop_base = asc_dvc->iop_base;
3996         AscPutRiscVarFreeQHead(iop_base, 1);
3997         AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
3998         AscPutVarFreeQHead(iop_base, 1);
3999         AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4000         AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
4001                          (uchar)((int)asc_dvc->max_total_qng + 1));
4002         AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
4003                          (uchar)((int)asc_dvc->max_total_qng + 2));
4004         AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
4005                          asc_dvc->max_total_qng);
4006         AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
4007         AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
4008         AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
4009         AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
4010         AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
4011         AscPutQDoneInProgress(iop_base, 0);
4012         lram_addr = ASC_QADR_BEG;
4013         for (i = 0; i < 32; i++, lram_addr += 2) {
4014                 AscWriteLramWord(iop_base, lram_addr, 0);
4015         }
4016 }
4017 
4018 static int AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
4019 {
4020         int i;
4021         int warn_code;
4022         PortAddr iop_base;
4023         __le32 phy_addr;
4024         __le32 phy_size;
4025         struct asc_board *board = asc_dvc_to_board(asc_dvc);
4026 
4027         iop_base = asc_dvc->iop_base;
4028         warn_code = 0;
4029         for (i = 0; i <= ASC_MAX_TID; i++) {
4030                 AscPutMCodeInitSDTRAtID(iop_base, i,
4031                                         asc_dvc->cfg->sdtr_period_offset[i]);
4032         }
4033 
4034         AscInitQLinkVar(asc_dvc);
4035         AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
4036                          asc_dvc->cfg->disc_enable);
4037         AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
4038                          ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
4039 
4040         /* Ensure overrun buffer is aligned on an 8 byte boundary. */
4041         BUG_ON((unsigned long)asc_dvc->overrun_buf & 7);
4042         asc_dvc->overrun_dma = dma_map_single(board->dev, asc_dvc->overrun_buf,
4043                                         ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4044         if (dma_mapping_error(board->dev, asc_dvc->overrun_dma)) {
4045                 warn_code = -ENOMEM;
4046                 goto err_dma_map;
4047         }
4048         phy_addr = cpu_to_le32(asc_dvc->overrun_dma);
4049         AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
4050                                  (uchar *)&phy_addr, 1);
4051         phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE);
4052         AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
4053                                  (uchar *)&phy_size, 1);
4054 
4055         asc_dvc->cfg->mcode_date =
4056             AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
4057         asc_dvc->cfg->mcode_version =
4058             AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
4059 
4060         AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
4061         if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
4062                 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
4063                 warn_code = -EINVAL;
4064                 goto err_mcode_start;
4065         }
4066         if (AscStartChip(iop_base) != 1) {
4067                 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
4068                 warn_code = -EIO;
4069                 goto err_mcode_start;
4070         }
4071 
4072         return warn_code;
4073 
4074 err_mcode_start:
4075         dma_unmap_single(board->dev, asc_dvc->overrun_dma,
4076                          ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4077 err_dma_map:
4078         asc_dvc->overrun_dma = 0;
4079         return warn_code;
4080 }
4081 
4082 static int AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
4083 {
4084         const struct firmware *fw;
4085         const char fwname[] = "advansys/mcode.bin";
4086         int err;
4087         unsigned long chksum;
4088         int warn_code;
4089         PortAddr iop_base;
4090 
4091         iop_base = asc_dvc->iop_base;
4092         warn_code = 0;
4093         if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
4094             !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
4095                 AscResetChipAndScsiBus(asc_dvc);
4096                 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4097         }
4098         asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
4099         if (asc_dvc->err_code != 0)
4100                 return ASC_ERROR;
4101         if (!AscFindSignature(asc_dvc->iop_base)) {
4102                 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
4103                 return warn_code;
4104         }
4105         AscDisableInterrupt(iop_base);
4106         AscInitLram(asc_dvc);
4107 
4108         err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4109         if (err) {
4110                 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4111                        fwname, err);
4112                 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4113                 return err;
4114         }
4115         if (fw->size < 4) {
4116                 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4117                        fw->size, fwname);
4118                 release_firmware(fw);
4119                 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4120                 return -EINVAL;
4121         }
4122         chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4123                  (fw->data[1] << 8) | fw->data[0];
4124         ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)chksum);
4125         if (AscLoadMicroCode(iop_base, 0, &fw->data[4],
4126                              fw->size - 4) != chksum) {
4127                 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4128                 release_firmware(fw);
4129                 return warn_code;
4130         }
4131         release_firmware(fw);
4132         warn_code |= AscInitMicroCodeVar(asc_dvc);
4133         if (!asc_dvc->overrun_dma)
4134                 return warn_code;
4135         asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
4136         AscEnableInterrupt(iop_base);
4137         return warn_code;
4138 }
4139 
4140 /*
4141  * Load the Microcode
4142  *
4143  * Write the microcode image to RISC memory starting at address 0.
4144  *
4145  * The microcode is stored compressed in the following format:
4146  *
4147  *  254 word (508 byte) table indexed by byte code followed
4148  *  by the following byte codes:
4149  *
4150  *    1-Byte Code:
4151  *      00: Emit word 0 in table.
4152  *      01: Emit word 1 in table.
4153  *      .
4154  *      FD: Emit word 253 in table.
4155  *
4156  *    Multi-Byte Code:
4157  *      FE WW WW: (3 byte code) Word to emit is the next word WW WW.
4158  *      FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
4159  *
4160  * Returns 0 or an error if the checksum doesn't match
4161  */
4162 static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf,
4163                             int size, int memsize, int chksum)
4164 {
4165         int i, j, end, len = 0;
4166         u32 sum;
4167 
4168         AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4169 
4170         for (i = 253 * 2; i < size; i++) {
4171                 if (buf[i] == 0xff) {
4172                         unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
4173                         for (j = 0; j < buf[i + 1]; j++) {
4174                                 AdvWriteWordAutoIncLram(iop_base, word);
4175                                 len += 2;
4176                         }
4177                         i += 3;
4178                 } else if (buf[i] == 0xfe) {
4179                         unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
4180                         AdvWriteWordAutoIncLram(iop_base, word);
4181                         i += 2;
4182                         len += 2;
4183                 } else {
4184                         unsigned int off = buf[i] * 2;
4185                         unsigned short word = (buf[off + 1] << 8) | buf[off];
4186                         AdvWriteWordAutoIncLram(iop_base, word);
4187                         len += 2;
4188                 }
4189         }
4190 
4191         end = len;
4192 
4193         while (len < memsize) {
4194                 AdvWriteWordAutoIncLram(iop_base, 0);
4195                 len += 2;
4196         }
4197 
4198         /* Verify the microcode checksum. */
4199         sum = 0;
4200         AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4201 
4202         for (len = 0; len < end; len += 2) {
4203                 sum += AdvReadWordAutoIncLram(iop_base);
4204         }
4205 
4206         if (sum != chksum)
4207                 return ASC_IERR_MCODE_CHKSUM;
4208 
4209         return 0;
4210 }
4211 
4212 static void AdvBuildCarrierFreelist(struct adv_dvc_var *adv_dvc)
4213 {
4214         off_t carr_offset = 0, next_offset;
4215         dma_addr_t carr_paddr;
4216         int carr_num = ADV_CARRIER_BUFSIZE / sizeof(ADV_CARR_T), i;
4217 
4218         for (i = 0; i < carr_num; i++) {
4219                 carr_offset = i * sizeof(ADV_CARR_T);
4220                 /* Get physical address of the carrier 'carrp'. */
4221                 carr_paddr = adv_dvc->carrier_addr + carr_offset;
4222 
4223                 adv_dvc->carrier[i].carr_pa = cpu_to_le32(carr_paddr);
4224                 adv_dvc->carrier[i].carr_va = cpu_to_le32(carr_offset);
4225                 adv_dvc->carrier[i].areq_vpa = 0;
4226                 next_offset = carr_offset + sizeof(ADV_CARR_T);
4227                 if (i == carr_num)
4228                         next_offset = ~0;
4229                 adv_dvc->carrier[i].next_vpa = cpu_to_le32(next_offset);
4230         }
4231         /*
4232          * We cannot have a carrier with 'carr_va' of '', as
4233          * a reference to this carrier would be interpreted as
4234          * list termination.
4235          * So start at carrier 1 with the freelist.
4236          */
4237         adv_dvc->carr_freelist = &adv_dvc->carrier[1];
4238 }
4239 
4240 static ADV_CARR_T *adv_get_carrier(struct adv_dvc_var *adv_dvc, u32 offset)
4241 {
4242         int index;
4243 
4244         BUG_ON(offset > ADV_CARRIER_BUFSIZE);
4245 
4246         index = offset / sizeof(ADV_CARR_T);
4247         return &adv_dvc->carrier[index];
4248 }
4249 
4250 static ADV_CARR_T *adv_get_next_carrier(struct adv_dvc_var *adv_dvc)
4251 {
4252         ADV_CARR_T *carrp = adv_dvc->carr_freelist;
4253         u32 next_vpa = le32_to_cpu(carrp->next_vpa);
4254 
4255         if (next_vpa == 0 || next_vpa == ~0) {
4256                 ASC_DBG(1, "invalid vpa offset 0x%x\n", next_vpa);
4257                 return NULL;
4258         }
4259 
4260         adv_dvc->carr_freelist = adv_get_carrier(adv_dvc, next_vpa);
4261         /*
4262          * insert stopper carrier to terminate list
4263          */
4264         carrp->next_vpa = cpu_to_le32(ADV_CQ_STOPPER);
4265 
4266         return carrp;
4267 }
4268 
4269 /*
4270  * 'offset' is the index in the request pointer array
4271  */
4272 static adv_req_t * adv_get_reqp(struct adv_dvc_var *adv_dvc, u32 offset)
4273 {
4274         struct asc_board *boardp = adv_dvc->drv_ptr;
4275 
4276         BUG_ON(offset > adv_dvc->max_host_qng);
4277         return &boardp->adv_reqp[offset];
4278 }
4279 
4280 /*
4281  * Send an idle command to the chip and wait for completion.
4282  *
4283  * Command completion is polled for once per microsecond.
4284  *
4285  * The function can be called from anywhere including an interrupt handler.
4286  * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
4287  * functions to prevent reentrancy.
4288  *
4289  * Return Values:
4290  *   ADV_TRUE - command completed successfully
4291  *   ADV_FALSE - command failed
4292  *   ADV_ERROR - command timed out
4293  */
4294 static int
4295 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
4296                ushort idle_cmd, u32 idle_cmd_parameter)
4297 {
4298         int result, i, j;
4299         AdvPortAddr iop_base;
4300 
4301         iop_base = asc_dvc->iop_base;
4302 
4303         /*
4304          * Clear the idle command status which is set by the microcode
4305          * to a non-zero value to indicate when the command is completed.
4306          * The non-zero result is one of the IDLE_CMD_STATUS_* values
4307          */
4308         AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
4309 
4310         /*
4311          * Write the idle command value after the idle command parameter
4312          * has been written to avoid a race condition. If the order is not
4313          * followed, the microcode may process the idle command before the
4314          * parameters have been written to LRAM.
4315          */
4316         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
4317                                 cpu_to_le32(idle_cmd_parameter));
4318         AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
4319 
4320         /*
4321          * Tickle the RISC to tell it to process the idle command.
4322          */
4323         AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
4324         if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
4325                 /*
4326                  * Clear the tickle value. In the ASC-3550 the RISC flag
4327                  * command 'clr_tickle_b' does not work unless the host
4328                  * value is cleared.
4329                  */
4330                 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
4331         }
4332 
4333         /* Wait for up to 100 millisecond for the idle command to timeout. */
4334         for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
4335                 /* Poll once each microsecond for command completion. */
4336                 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
4337                         AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
4338                                         result);
4339                         if (result != 0)
4340                                 return result;
4341                         udelay(1);
4342                 }
4343         }
4344 
4345         BUG();          /* The idle command should never timeout. */
4346         return ADV_ERROR;
4347 }
4348 
4349 /*
4350  * Reset SCSI Bus and purge all outstanding requests.
4351  *
4352  * Return Value:
4353  *      ADV_TRUE(1) -   All requests are purged and SCSI Bus is reset.
4354  *      ADV_FALSE(0) -  Microcode command failed.
4355  *      ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
4356  *                      may be hung which requires driver recovery.
4357  */
4358 static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
4359 {
4360         int status;
4361 
4362         /*
4363          * Send the SCSI Bus Reset idle start idle command which asserts
4364          * the SCSI Bus Reset signal.
4365          */
4366         status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
4367         if (status != ADV_TRUE) {
4368                 return status;
4369         }
4370 
4371         /*
4372          * Delay for the specified SCSI Bus Reset hold time.
4373          *
4374          * The hold time delay is done on the host because the RISC has no
4375          * microsecond accurate timer.
4376          */
4377         udelay(ASC_SCSI_RESET_HOLD_TIME_US);
4378 
4379         /*
4380          * Send the SCSI Bus Reset end idle command which de-asserts
4381          * the SCSI Bus Reset signal and purges any pending requests.
4382          */
4383         status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
4384         if (status != ADV_TRUE) {
4385                 return status;
4386         }
4387 
4388         mdelay(asc_dvc->scsi_reset_wait * 1000);        /* XXX: msleep? */
4389 
4390         return status;
4391 }
4392 
4393 /*
4394  * Initialize the ASC-3550.
4395  *
4396  * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4397  *
4398  * For a non-fatal error return a warning code. If there are no warnings
4399  * then 0 is returned.
4400  *
4401  * Needed after initialization for error recovery.
4402  */
4403 static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
4404 {
4405         const struct firmware *fw;
4406         const char fwname[] = "advansys/3550.bin";
4407         AdvPortAddr iop_base;
4408         ushort warn_code;
4409         int begin_addr;
4410         int end_addr;
4411         ushort code_sum;
4412         int word;
4413         int i;
4414         int err;
4415         unsigned long chksum;
4416         ushort scsi_cfg1;
4417         uchar tid;
4418         ushort bios_mem[ASC_MC_BIOSLEN / 2];    /* BIOS RISC Memory 0x40-0x8F. */
4419         ushort wdtr_able = 0, sdtr_able, tagqng_able;
4420         uchar max_cmd[ADV_MAX_TID + 1];
4421 
4422         /* If there is already an error, don't continue. */
4423         if (asc_dvc->err_code != 0)
4424                 return ADV_ERROR;
4425 
4426         /*
4427          * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
4428          */
4429         if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
4430                 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4431                 return ADV_ERROR;
4432         }
4433 
4434         warn_code = 0;
4435         iop_base = asc_dvc->iop_base;
4436 
4437         /*
4438          * Save the RISC memory BIOS region before writing the microcode.
4439          * The BIOS may already be loaded and using its RISC LRAM region
4440          * so its region must be saved and restored.
4441          *
4442          * Note: This code makes the assumption, which is currently true,
4443          * that a chip reset does not clear RISC LRAM.
4444          */
4445         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4446                 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4447                                 bios_mem[i]);
4448         }
4449 
4450         /*
4451          * Save current per TID negotiated values.
4452          */
4453         if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
4454                 ushort bios_version, major, minor;
4455 
4456                 bios_version =
4457                     bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
4458                 major = (bios_version >> 12) & 0xF;
4459                 minor = (bios_version >> 8) & 0xF;
4460                 if (major < 3 || (major == 3 && minor == 1)) {
4461                         /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
4462                         AdvReadWordLram(iop_base, 0x120, wdtr_able);
4463                 } else {
4464                         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4465                 }
4466         }
4467         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4468         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4469         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4470                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4471                                 max_cmd[tid]);
4472         }
4473 
4474         err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4475         if (err) {
4476                 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4477                        fwname, err);
4478                 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4479                 return err;
4480         }
4481         if (fw->size < 4) {
4482                 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4483                        fw->size, fwname);
4484                 release_firmware(fw);
4485                 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4486                 return -EINVAL;
4487         }
4488         chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4489                  (fw->data[1] << 8) | fw->data[0];
4490         asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
4491                                              fw->size - 4, ADV_3550_MEMSIZE,
4492                                              chksum);
4493         release_firmware(fw);
4494         if (asc_dvc->err_code)
4495                 return ADV_ERROR;
4496 
4497         /*
4498          * Restore the RISC memory BIOS region.
4499          */
4500         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4501                 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4502                                  bios_mem[i]);
4503         }
4504 
4505         /*
4506          * Calculate and write the microcode code checksum to the microcode
4507          * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
4508          */
4509         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
4510         AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
4511         code_sum = 0;
4512         AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
4513         for (word = begin_addr; word < end_addr; word += 2) {
4514                 code_sum += AdvReadWordAutoIncLram(iop_base);
4515         }
4516         AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
4517 
4518         /*
4519          * Read and save microcode version and date.
4520          */
4521         AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
4522                         asc_dvc->cfg->mcode_date);
4523         AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
4524                         asc_dvc->cfg->mcode_version);
4525 
4526         /*
4527          * Set the chip type to indicate the ASC3550.
4528          */
4529         AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
4530 
4531         /*
4532          * If the PCI Configuration Command Register "Parity Error Response
4533          * Control" Bit was clear (0), then set the microcode variable
4534          * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
4535          * to ignore DMA parity errors.
4536          */
4537         if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
4538                 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4539                 word |= CONTROL_FLAG_IGNORE_PERR;
4540                 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4541         }
4542 
4543         /*
4544          * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
4545          * threshold of 128 bytes. This register is only accessible to the host.
4546          */
4547         AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
4548                              START_CTL_EMFU | READ_CMD_MRM);
4549 
4550         /*
4551          * Microcode operating variables for WDTR, SDTR, and command tag
4552          * queuing will be set in slave_configure() based on what a
4553          * device reports it is capable of in Inquiry byte 7.
4554          *
4555          * If SCSI Bus Resets have been disabled, then directly set
4556          * SDTR and WDTR from the EEPROM configuration. This will allow
4557          * the BIOS and warm boot to work without a SCSI bus hang on
4558          * the Inquiry caused by host and target mismatched DTR values.
4559          * Without the SCSI Bus Reset, before an Inquiry a device can't
4560          * be assumed to be in Asynchronous, Narrow mode.
4561          */
4562         if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
4563                 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
4564                                  asc_dvc->wdtr_able);
4565                 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
4566                                  asc_dvc->sdtr_able);
4567         }
4568 
4569         /*
4570          * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
4571          * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
4572          * bitmask. These values determine the maximum SDTR speed negotiated
4573          * with a device.
4574          *
4575          * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
4576          * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
4577          * without determining here whether the device supports SDTR.
4578          *
4579          * 4-bit speed  SDTR speed name
4580          * ===========  ===============
4581          * 0000b (0x0)  SDTR disabled
4582          * 0001b (0x1)  5 Mhz
4583          * 0010b (0x2)  10 Mhz
4584          * 0011b (0x3)  20 Mhz (Ultra)
4585          * 0100b (0x4)  40 Mhz (LVD/Ultra2)
4586          * 0101b (0x5)  80 Mhz (LVD2/Ultra3)
4587          * 0110b (0x6)  Undefined
4588          * .
4589          * 1111b (0xF)  Undefined
4590          */
4591         word = 0;
4592         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4593                 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
4594                         /* Set Ultra speed for TID 'tid'. */
4595                         word |= (0x3 << (4 * (tid % 4)));
4596                 } else {
4597                         /* Set Fast speed for TID 'tid'. */
4598                         word |= (0x2 << (4 * (tid % 4)));
4599                 }
4600                 if (tid == 3) { /* Check if done with sdtr_speed1. */
4601                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
4602                         word = 0;
4603                 } else if (tid == 7) {  /* Check if done with sdtr_speed2. */
4604                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
4605                         word = 0;
4606                 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
4607                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
4608                         word = 0;
4609                 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
4610                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
4611                         /* End of loop. */
4612                 }
4613         }
4614 
4615         /*
4616          * Set microcode operating variable for the disconnect per TID bitmask.
4617          */
4618         AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
4619                          asc_dvc->cfg->disc_enable);
4620 
4621         /*
4622          * Set SCSI_CFG0 Microcode Default Value.
4623          *
4624          * The microcode will set the SCSI_CFG0 register using this value
4625          * after it is started below.
4626          */
4627         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
4628                          PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
4629                          asc_dvc->chip_scsi_id);
4630 
4631         /*
4632          * Determine SCSI_CFG1 Microcode Default Value.
4633          *
4634          * The microcode will set the SCSI_CFG1 register using this value
4635          * after it is started below.
4636          */
4637 
4638         /* Read current SCSI_CFG1 Register value. */
4639         scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
4640 
4641         /*
4642          * If all three connectors are in use, return an error.
4643          */
4644         if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
4645             (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
4646                 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
4647                 return ADV_ERROR;
4648         }
4649 
4650         /*
4651          * If the internal narrow cable is reversed all of the SCSI_CTRL
4652          * register signals will be set. Check for and return an error if
4653          * this condition is found.
4654          */
4655         if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
4656                 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
4657                 return ADV_ERROR;
4658         }
4659 
4660         /*
4661          * If this is a differential board and a single-ended device
4662          * is attached to one of the connectors, return an error.
4663          */
4664         if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
4665                 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
4666                 return ADV_ERROR;
4667         }
4668 
4669         /*
4670          * If automatic termination control is enabled, then set the
4671          * termination value based on a table listed in a_condor.h.
4672          *
4673          * If manual termination was specified with an EEPROM setting
4674          * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
4675          * is ready to be 'ored' into SCSI_CFG1.
4676          */
4677         if (asc_dvc->cfg->termination == 0) {
4678                 /*
4679                  * The software always controls termination by setting TERM_CTL_SEL.
4680                  * If TERM_CTL_SEL were set to 0, the hardware would set termination.
4681                  */
4682                 asc_dvc->cfg->termination |= TERM_CTL_SEL;
4683 
4684                 switch (scsi_cfg1 & CABLE_DETECT) {
4685                         /* TERM_CTL_H: on, TERM_CTL_L: on */
4686                 case 0x3:
4687                 case 0x7:
4688                 case 0xB:
4689                 case 0xD:
4690                 case 0xE:
4691                 case 0xF:
4692                         asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
4693                         break;
4694 
4695                         /* TERM_CTL_H: on, TERM_CTL_L: off */
4696                 case 0x1:
4697                 case 0x5:
4698                 case 0x9:
4699                 case 0xA:
4700                 case 0xC:
4701                         asc_dvc->cfg->termination |= TERM_CTL_H;
4702                         break;
4703 
4704                         /* TERM_CTL_H: off, TERM_CTL_L: off */
4705                 case 0x2:
4706                 case 0x6:
4707                         break;
4708                 }
4709         }
4710 
4711         /*
4712          * Clear any set TERM_CTL_H and TERM_CTL_L bits.
4713          */
4714         scsi_cfg1 &= ~TERM_CTL;
4715 
4716         /*
4717          * Invert the TERM_CTL_H and TERM_CTL_L bits and then
4718          * set 'scsi_cfg1'. The TERM_POL bit does not need to be
4719          * referenced, because the hardware internally inverts
4720          * the Termination High and Low bits if TERM_POL is set.
4721          */
4722         scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
4723 
4724         /*
4725          * Set SCSI_CFG1 Microcode Default Value
4726          *
4727          * Set filter value and possibly modified termination control
4728          * bits in the Microcode SCSI_CFG1 Register Value.
4729          *
4730          * The microcode will set the SCSI_CFG1 register using this value
4731          * after it is started below.
4732          */
4733         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
4734                          FLTR_DISABLE | scsi_cfg1);
4735 
4736         /*
4737          * Set MEM_CFG Microcode Default Value
4738          *
4739          * The microcode will set the MEM_CFG register using this value
4740          * after it is started below.
4741          *
4742          * MEM_CFG may be accessed as a word or byte, but only bits 0-7
4743          * are defined.
4744          *
4745          * ASC-3550 has 8KB internal memory.
4746          */
4747         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
4748                          BIOS_EN | RAM_SZ_8KB);
4749 
4750         /*
4751          * Set SEL_MASK Microcode Default Value
4752          *
4753          * The microcode will set the SEL_MASK register using this value
4754          * after it is started below.
4755          */
4756         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
4757                          ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
4758 
4759         AdvBuildCarrierFreelist(asc_dvc);
4760 
4761         /*
4762          * Set-up the Host->RISC Initiator Command Queue (ICQ).
4763          */
4764 
4765         asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
4766         if (!asc_dvc->icq_sp) {
4767                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4768                 return ADV_ERROR;
4769         }
4770 
4771         /*
4772          * Set RISC ICQ physical address start value.
4773          */
4774         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
4775 
4776         /*
4777          * Set-up the RISC->Host Initiator Response Queue (IRQ).
4778          */
4779         asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
4780         if (!asc_dvc->irq_sp) {
4781                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4782                 return ADV_ERROR;
4783         }
4784 
4785         /*
4786          * Set RISC IRQ physical address start value.
4787          */
4788         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
4789         asc_dvc->carr_pending_cnt = 0;
4790 
4791         AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
4792                              (ADV_INTR_ENABLE_HOST_INTR |
4793                               ADV_INTR_ENABLE_GLOBAL_INTR));
4794 
4795         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
4796         AdvWriteWordRegister(iop_base, IOPW_PC, word);
4797 
4798         /* finally, finally, gentlemen, start your engine */
4799         AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
4800 
4801         /*
4802          * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
4803          * Resets should be performed. The RISC has to be running
4804          * to issue a SCSI Bus Reset.
4805          */
4806         if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
4807                 /*
4808                  * If the BIOS Signature is present in memory, restore the
4809                  * BIOS Handshake Configuration Table and do not perform
4810                  * a SCSI Bus Reset.
4811                  */
4812                 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
4813                     0x55AA) {
4814                         /*
4815                          * Restore per TID negotiated values.
4816                          */
4817                         AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4818                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4819                         AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
4820                                          tagqng_able);
4821                         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4822                                 AdvWriteByteLram(iop_base,
4823                                                  ASC_MC_NUMBER_OF_MAX_CMD + tid,
4824                                                  max_cmd[tid]);
4825                         }
4826                 } else {
4827                         if (AdvResetSB(asc_dvc) != ADV_TRUE) {
4828                                 warn_code = ASC_WARN_BUSRESET_ERROR;
4829                         }
4830                 }
4831         }
4832 
4833         return warn_code;
4834 }
4835 
4836 /*
4837  * Initialize the ASC-38C0800.
4838  *
4839  * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4840  *
4841  * For a non-fatal error return a warning code. If there are no warnings
4842  * then 0 is returned.
4843  *
4844  * Needed after initialization for error recovery.
4845  */
4846 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
4847 {
4848         const struct firmware *fw;
4849         const char fwname[] = "advansys/38C0800.bin";
4850         AdvPortAddr iop_base;
4851         ushort warn_code;
4852         int begin_addr;
4853         int end_addr;
4854         ushort code_sum;
4855         int word;
4856         int i;
4857         int err;
4858         unsigned long chksum;
4859         ushort scsi_cfg1;
4860         uchar byte;
4861         uchar tid;
4862         ushort bios_mem[ASC_MC_BIOSLEN / 2];    /* BIOS RISC Memory 0x40-0x8F. */
4863         ushort wdtr_able, sdtr_able, tagqng_able;
4864         uchar max_cmd[ADV_MAX_TID + 1];
4865 
4866         /* If there is already an error, don't continue. */
4867         if (asc_dvc->err_code != 0)
4868                 return ADV_ERROR;
4869 
4870         /*
4871          * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
4872          */
4873         if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
4874                 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4875                 return ADV_ERROR;
4876         }
4877 
4878         warn_code = 0;
4879         iop_base = asc_dvc->iop_base;
4880 
4881         /*
4882          * Save the RISC memory BIOS region before writing the microcode.
4883          * The BIOS may already be loaded and using its RISC LRAM region
4884          * so its region must be saved and restored.
4885          *
4886          * Note: This code makes the assumption, which is currently true,
4887          * that a chip reset does not clear RISC LRAM.
4888          */
4889         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4890                 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4891                                 bios_mem[i]);
4892         }
4893 
4894         /*
4895          * Save current per TID negotiated values.
4896          */
4897         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4898         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4899         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4900         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4901                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4902                                 max_cmd[tid]);
4903         }
4904 
4905         /*
4906          * RAM BIST (RAM Built-In Self Test)
4907          *
4908          * Address : I/O base + offset 0x38h register (byte).
4909          * Function: Bit 7-6(RW) : RAM mode
4910          *                          Normal Mode   : 0x00
4911          *                          Pre-test Mode : 0x40
4912          *                          RAM Test Mode : 0x80
4913          *           Bit 5       : unused
4914          *           Bit 4(RO)   : Done bit
4915          *           Bit 3-0(RO) : Status
4916          *                          Host Error    : 0x08
4917          *                          Int_RAM Error : 0x04
4918          *                          RISC Error    : 0x02
4919          *                          SCSI Error    : 0x01
4920          *                          No Error      : 0x00
4921          *
4922          * Note: RAM BIST code should be put right here, before loading the
4923          * microcode and after saving the RISC memory BIOS region.
4924          */
4925 
4926         /*
4927          * LRAM Pre-test
4928          *
4929          * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
4930          * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
4931          * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
4932          * to NORMAL_MODE, return an error too.
4933          */
4934         for (i = 0; i < 2; i++) {
4935                 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
4936                 mdelay(10);     /* Wait for 10ms before reading back. */
4937                 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
4938                 if ((byte & RAM_TEST_DONE) == 0
4939                     || (byte & 0x0F) != PRE_TEST_VALUE) {
4940                         asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
4941                         return ADV_ERROR;
4942                 }
4943 
4944                 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
4945                 mdelay(10);     /* Wait for 10ms before reading back. */
4946                 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
4947                     != NORMAL_VALUE) {
4948                         asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
4949                         return ADV_ERROR;
4950                 }
4951         }
4952 
4953         /*
4954          * LRAM Test - It takes about 1.5 ms to run through the test.
4955          *
4956          * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
4957          * If Done bit not set or Status not 0, save register byte, set the
4958          * err_code, and return an error.
4959          */
4960         AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
4961         mdelay(10);     /* Wait for 10ms before checking status. */
4962 
4963         byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
4964         if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
4965                 /* Get here if Done bit not set or Status not 0. */
4966                 asc_dvc->bist_err_code = byte;  /* for BIOS display message */
4967                 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
4968                 return ADV_ERROR;
4969         }
4970 
4971         /* We need to reset back to normal mode after LRAM test passes. */
4972         AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
4973 
4974         err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4975         if (err) {
4976                 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4977                        fwname, err);
4978                 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4979                 return err;
4980         }
4981         if (fw->size < 4) {
4982                 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4983                        fw->size, fwname);
4984                 release_firmware(fw);
4985                 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4986                 return -EINVAL;
4987         }
4988         chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4989                  (fw->data[1] << 8) | fw->data[0];
4990         asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
4991                                              fw->size - 4, ADV_38C0800_MEMSIZE,
4992                                              chksum);
4993         release_firmware(fw);
4994         if (asc_dvc->err_code)
4995                 return ADV_ERROR;
4996 
4997         /*
4998          * Restore the RISC memory BIOS region.
4999          */
5000         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5001                 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5002                                  bios_mem[i]);
5003         }
5004 
5005         /*
5006          * Calculate and write the microcode code checksum to the microcode
5007          * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5008          */
5009         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5010         AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5011         code_sum = 0;
5012         AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5013         for (word = begin_addr; word < end_addr; word += 2) {
5014                 code_sum += AdvReadWordAutoIncLram(iop_base);
5015         }
5016         AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5017 
5018         /*
5019          * Read microcode version and date.
5020          */
5021         AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5022                         asc_dvc->cfg->mcode_date);
5023         AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5024                         asc_dvc->cfg->mcode_version);
5025 
5026         /*
5027          * Set the chip type to indicate the ASC38C0800.
5028          */
5029         AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
5030 
5031         /*
5032          * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5033          * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5034          * cable detection and then we are able to read C_DET[3:0].
5035          *
5036          * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5037          * Microcode Default Value' section below.
5038          */
5039         scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5040         AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5041                              scsi_cfg1 | DIS_TERM_DRV);
5042 
5043         /*
5044          * If the PCI Configuration Command Register "Parity Error Response
5045          * Control" Bit was clear (0), then set the microcode variable
5046          * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5047          * to ignore DMA parity errors.
5048          */
5049         if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5050                 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5051                 word |= CONTROL_FLAG_IGNORE_PERR;
5052                 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5053         }
5054 
5055         /*
5056          * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
5057          * bits for the default FIFO threshold.
5058          *
5059          * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
5060          *
5061          * For DMA Errata #4 set the BC_THRESH_ENB bit.
5062          */
5063         AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5064                              BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
5065                              READ_CMD_MRM);
5066 
5067         /*
5068          * Microcode operating variables for WDTR, SDTR, and command tag
5069          * queuing will be set in slave_configure() based on what a
5070          * device reports it is capable of in Inquiry byte 7.
5071          *
5072          * If SCSI Bus Resets have been disabled, then directly set
5073          * SDTR and WDTR from the EEPROM configuration. This will allow
5074          * the BIOS and warm boot to work without a SCSI bus hang on
5075          * the Inquiry caused by host and target mismatched DTR values.
5076          * Without the SCSI Bus Reset, before an Inquiry a device can't
5077          * be assumed to be in Asynchronous, Narrow mode.
5078          */
5079         if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5080                 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5081                                  asc_dvc->wdtr_able);
5082                 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5083                                  asc_dvc->sdtr_able);
5084         }
5085 
5086         /*
5087          * Set microcode operating variables for DISC and SDTR_SPEED1,
5088          * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5089          * configuration values.
5090          *
5091          * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5092          * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5093          * without determining here whether the device supports SDTR.
5094          */
5095         AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5096                          asc_dvc->cfg->disc_enable);
5097         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5098         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5099         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5100         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5101 
5102         /*
5103          * Set SCSI_CFG0 Microcode Default Value.
5104          *
5105          * The microcode will set the SCSI_CFG0 register using this value
5106          * after it is started below.
5107          */
5108         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5109                          PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5110                          asc_dvc->chip_scsi_id);
5111 
5112         /*
5113          * Determine SCSI_CFG1 Microcode Default Value.
5114          *
5115          * The microcode will set the SCSI_CFG1 register using this value
5116          * after it is started below.
5117          */
5118 
5119         /* Read current SCSI_CFG1 Register value. */
5120         scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5121 
5122         /*
5123          * If the internal narrow cable is reversed all of the SCSI_CTRL
5124          * register signals will be set. Check for and return an error if
5125          * this condition is found.
5126          */
5127         if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5128                 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5129                 return ADV_ERROR;
5130         }
5131 
5132         /*
5133          * All kind of combinations of devices attached to one of four
5134          * connectors are acceptable except HVD device attached. For example,
5135          * LVD device can be attached to SE connector while SE device attached
5136          * to LVD connector.  If LVD device attached to SE connector, it only
5137          * runs up to Ultra speed.
5138          *
5139          * If an HVD device is attached to one of LVD connectors, return an
5140          * error.  However, there is no way to detect HVD device attached to
5141          * SE connectors.
5142          */
5143         if (scsi_cfg1 & HVD) {
5144                 asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
5145                 return ADV_ERROR;
5146         }
5147 
5148         /*
5149          * If either SE or LVD automatic termination control is enabled, then
5150          * set the termination value based on a table listed in a_condor.h.
5151          *
5152          * If manual termination was specified with an EEPROM setting then
5153          * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
5154          * to be 'ored' into SCSI_CFG1.
5155          */
5156         if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5157                 /* SE automatic termination control is enabled. */
5158                 switch (scsi_cfg1 & C_DET_SE) {
5159                         /* TERM_SE_HI: on, TERM_SE_LO: on */
5160                 case 0x1:
5161                 case 0x2:
5162                 case 0x3:
5163                         asc_dvc->cfg->termination |= TERM_SE;
5164                         break;
5165 
5166                         /* TERM_SE_HI: on, TERM_SE_LO: off */
5167                 case 0x0:
5168                         asc_dvc->cfg->termination |= TERM_SE_HI;
5169                         break;
5170                 }
5171         }
5172 
5173         if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
5174                 /* LVD automatic termination control is enabled. */
5175                 switch (scsi_cfg1 & C_DET_LVD) {
5176                         /* TERM_LVD_HI: on, TERM_LVD_LO: on */
5177                 case 0x4:
5178                 case 0x8:
5179                 case 0xC:
5180                         asc_dvc->cfg->termination |= TERM_LVD;
5181                         break;
5182 
5183                         /* TERM_LVD_HI: off, TERM_LVD_LO: off */
5184                 case 0x0:
5185                         break;
5186                 }
5187         }
5188 
5189         /*
5190          * Clear any set TERM_SE and TERM_LVD bits.
5191          */
5192         scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
5193 
5194         /*
5195          * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
5196          */
5197         scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
5198 
5199         /*
5200          * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
5201          * bits and set possibly modified termination control bits in the
5202          * Microcode SCSI_CFG1 Register Value.
5203          */
5204         scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
5205 
5206         /*
5207          * Set SCSI_CFG1 Microcode Default Value
5208          *
5209          * Set possibly modified termination control and reset DIS_TERM_DRV
5210          * bits in the Microcode SCSI_CFG1 Register Value.
5211          *
5212          * The microcode will set the SCSI_CFG1 register using this value
5213          * after it is started below.
5214          */
5215         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5216 
5217         /*
5218          * Set MEM_CFG Microcode Default Value
5219          *
5220          * The microcode will set the MEM_CFG register using this value
5221          * after it is started below.
5222          *
5223          * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5224          * are defined.
5225          *
5226          * ASC-38C0800 has 16KB internal memory.
5227          */
5228         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5229                          BIOS_EN | RAM_SZ_16KB);
5230 
5231         /*
5232          * Set SEL_MASK Microcode Default Value
5233          *
5234          * The microcode will set the SEL_MASK register using this value
5235          * after it is started below.
5236          */
5237         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5238                          ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5239 
5240         AdvBuildCarrierFreelist(asc_dvc);
5241 
5242         /*
5243          * Set-up the Host->RISC Initiator Command Queue (ICQ).
5244          */
5245 
5246         asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
5247         if (!asc_dvc->icq_sp) {
5248                 ASC_DBG(0, "Failed to get ICQ carrier\n");
5249                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5250                 return ADV_ERROR;
5251         }
5252 
5253         /*
5254          * Set RISC ICQ physical address start value.
5255          * carr_pa is LE, must be native before write
5256          */
5257         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5258 
5259         /*
5260          * Set-up the RISC->Host Initiator Response Queue (IRQ).
5261          */
5262         asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
5263         if (!asc_dvc->irq_sp) {
5264                 ASC_DBG(0, "Failed to get IRQ carrier\n");
5265                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5266                 return ADV_ERROR;
5267         }
5268 
5269         /*
5270          * Set RISC IRQ physical address start value.
5271          *
5272          * carr_pa is LE, must be native before write *
5273          */
5274         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5275         asc_dvc->carr_pending_cnt = 0;
5276 
5277         AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5278                              (ADV_INTR_ENABLE_HOST_INTR |
5279                               ADV_INTR_ENABLE_GLOBAL_INTR));
5280 
5281         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5282         AdvWriteWordRegister(iop_base, IOPW_PC, word);
5283 
5284         /* finally, finally, gentlemen, start your engine */
5285         AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5286 
5287         /*
5288          * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5289          * Resets should be performed. The RISC has to be running
5290          * to issue a SCSI Bus Reset.
5291          */
5292         if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5293                 /*
5294                  * If the BIOS Signature is present in memory, restore the
5295                  * BIOS Handshake Configuration Table and do not perform
5296                  * a SCSI Bus Reset.
5297                  */
5298                 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5299                     0x55AA) {
5300                         /*
5301                          * Restore per TID negotiated values.
5302                          */
5303                         AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5304                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5305                         AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5306                                          tagqng_able);
5307                         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5308                                 AdvWriteByteLram(iop_base,
5309                                                  ASC_MC_NUMBER_OF_MAX_CMD + tid,
5310                                                  max_cmd[tid]);
5311                         }
5312                 } else {
5313                         if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5314                                 warn_code = ASC_WARN_BUSRESET_ERROR;
5315                         }
5316                 }
5317         }
5318 
5319         return warn_code;
5320 }
5321 
5322 /*
5323  * Initialize the ASC-38C1600.
5324  *
5325  * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
5326  *
5327  * For a non-fatal error return a warning code. If there are no warnings
5328  * then 0 is returned.
5329  *
5330  * Needed after initialization for error recovery.
5331  */
5332 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
5333 {
5334         const struct firmware *fw;
5335         const char fwname[] = "advansys/38C1600.bin";
5336         AdvPortAddr iop_base;
5337         ushort warn_code;
5338         int begin_addr;
5339         int end_addr;
5340         ushort code_sum;
5341         long word;
5342         int i;
5343         int err;
5344         unsigned long chksum;
5345         ushort scsi_cfg1;
5346         uchar byte;
5347         uchar tid;
5348         ushort bios_mem[ASC_MC_BIOSLEN / 2];    /* BIOS RISC Memory 0x40-0x8F. */
5349         ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
5350         uchar max_cmd[ASC_MAX_TID + 1];
5351 
5352         /* If there is already an error, don't continue. */
5353         if (asc_dvc->err_code != 0) {
5354                 return ADV_ERROR;
5355         }
5356 
5357         /*
5358          * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
5359          */
5360         if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
5361                 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
5362                 return ADV_ERROR;
5363         }
5364 
5365         warn_code = 0;
5366         iop_base = asc_dvc->iop_base;
5367 
5368         /*
5369          * Save the RISC memory BIOS region before writing the microcode.
5370          * The BIOS may already be loaded and using its RISC LRAM region
5371          * so its region must be saved and restored.
5372          *
5373          * Note: This code makes the assumption, which is currently true,
5374          * that a chip reset does not clear RISC LRAM.
5375          */
5376         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5377                 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5378                                 bios_mem[i]);
5379         }
5380 
5381         /*
5382          * Save current per TID negotiated values.
5383          */
5384         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5385         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5386         AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5387         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5388         for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5389                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5390                                 max_cmd[tid]);
5391         }
5392 
5393         /*
5394          * RAM BIST (Built-In Self Test)
5395          *
5396          * Address : I/O base + offset 0x38h register (byte).
5397          * Function: Bit 7-6(RW) : RAM mode
5398          *                          Normal Mode   : 0x00
5399          *                          Pre-test Mode : 0x40
5400          *                          RAM Test Mode : 0x80
5401          *           Bit 5       : unused
5402          *           Bit 4(RO)   : Done bit
5403          *           Bit 3-0(RO) : Status
5404          *                          Host Error    : 0x08
5405          *                          Int_RAM Error : 0x04
5406          *                          RISC Error    : 0x02
5407          *                          SCSI Error    : 0x01
5408          *                          No Error      : 0x00
5409          *
5410          * Note: RAM BIST code should be put right here, before loading the
5411          * microcode and after saving the RISC memory BIOS region.
5412          */
5413 
5414         /*
5415          * LRAM Pre-test
5416          *
5417          * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5418          * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5419          * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5420          * to NORMAL_MODE, return an error too.
5421          */
5422         for (i = 0; i < 2; i++) {
5423                 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5424                 mdelay(10);     /* Wait for 10ms before reading back. */
5425                 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5426                 if ((byte & RAM_TEST_DONE) == 0
5427                     || (byte & 0x0F) != PRE_TEST_VALUE) {
5428                         asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5429                         return ADV_ERROR;
5430                 }
5431 
5432                 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5433                 mdelay(10);     /* Wait for 10ms before reading back. */
5434                 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5435                     != NORMAL_VALUE) {
5436                         asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5437                         return ADV_ERROR;
5438                 }
5439         }
5440 
5441         /*
5442          * LRAM Test - It takes about 1.5 ms to run through the test.
5443          *
5444          * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5445          * If Done bit not set or Status not 0, save register byte, set the
5446          * err_code, and return an error.
5447          */
5448         AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5449         mdelay(10);     /* Wait for 10ms before checking status. */
5450 
5451         byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5452         if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5453                 /* Get here if Done bit not set or Status not 0. */
5454                 asc_dvc->bist_err_code = byte;  /* for BIOS display message */
5455                 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5456                 return ADV_ERROR;
5457         }
5458 
5459         /* We need to reset back to normal mode after LRAM test passes. */
5460         AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5461 
5462         err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5463         if (err) {
5464                 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5465                        fwname, err);
5466                 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5467                 return err;
5468         }
5469         if (fw->size < 4) {
5470                 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5471                        fw->size, fwname);
5472                 release_firmware(fw);
5473                 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5474                 return -EINVAL;
5475         }
5476         chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5477                  (fw->data[1] << 8) | fw->data[0];
5478         asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5479                                              fw->size - 4, ADV_38C1600_MEMSIZE,
5480                                              chksum);
5481         release_firmware(fw);
5482         if (asc_dvc->err_code)
5483                 return ADV_ERROR;
5484 
5485         /*
5486          * Restore the RISC memory BIOS region.
5487          */
5488         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5489                 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5490                                  bios_mem[i]);
5491         }
5492 
5493         /*
5494          * Calculate and write the microcode code checksum to the microcode
5495          * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5496          */
5497         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5498         AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5499         code_sum = 0;
5500         AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5501         for (word = begin_addr; word < end_addr; word += 2) {
5502                 code_sum += AdvReadWordAutoIncLram(iop_base);
5503         }
5504         AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5505 
5506         /*
5507          * Read microcode version and date.
5508          */
5509         AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5510                         asc_dvc->cfg->mcode_date);
5511         AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5512                         asc_dvc->cfg->mcode_version);
5513 
5514         /*
5515          * Set the chip type to indicate the ASC38C1600.
5516          */
5517         AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
5518 
5519         /*
5520          * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5521          * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5522          * cable detection and then we are able to read C_DET[3:0].
5523          *
5524          * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5525          * Microcode Default Value' section below.
5526          */
5527         scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5528         AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5529                              scsi_cfg1 | DIS_TERM_DRV);
5530 
5531         /*
5532          * If the PCI Configuration Command Register "Parity Error Response
5533          * Control" Bit was clear (0), then set the microcode variable
5534          * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5535          * to ignore DMA parity errors.
5536          */
5537         if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5538                 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5539                 word |= CONTROL_FLAG_IGNORE_PERR;
5540                 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5541         }
5542 
5543         /*
5544          * If the BIOS control flag AIPP (Asynchronous Information
5545          * Phase Protection) disable bit is not set, then set the firmware
5546          * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
5547          * AIPP checking and encoding.
5548          */
5549         if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
5550                 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5551                 word |= CONTROL_FLAG_ENABLE_AIPP;
5552                 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5553         }
5554 
5555         /*
5556          * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
5557          * and START_CTL_TH [3:2].
5558          */
5559         AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5560                              FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
5561 
5562         /*
5563          * Microcode operating variables for WDTR, SDTR, and command tag
5564          * queuing will be set in slave_configure() based on what a
5565          * device reports it is capable of in Inquiry byte 7.
5566          *
5567          * If SCSI Bus Resets have been disabled, then directly set
5568          * SDTR and WDTR from the EEPROM configuration. This will allow
5569          * the BIOS and warm boot to work without a SCSI bus hang on
5570          * the Inquiry caused by host and target mismatched DTR values.
5571          * Without the SCSI Bus Reset, before an Inquiry a device can't
5572          * be assumed to be in Asynchronous, Narrow mode.
5573          */
5574         if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5575                 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5576                                  asc_dvc->wdtr_able);
5577                 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5578                                  asc_dvc->sdtr_able);
5579         }
5580 
5581         /*
5582          * Set microcode operating variables for DISC and SDTR_SPEED1,
5583          * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5584          * configuration values.
5585          *
5586          * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5587          * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5588          * without determining here whether the device supports SDTR.
5589          */
5590         AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5591                          asc_dvc->cfg->disc_enable);
5592         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5593         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5594         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5595         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5596 
5597         /*
5598          * Set SCSI_CFG0 Microcode Default Value.
5599          *
5600          * The microcode will set the SCSI_CFG0 register using this value
5601          * after it is started below.
5602          */
5603         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5604                          PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5605                          asc_dvc->chip_scsi_id);
5606 
5607         /*
5608          * Calculate SCSI_CFG1 Microcode Default Value.
5609          *
5610          * The microcode will set the SCSI_CFG1 register using this value
5611          * after it is started below.
5612          *
5613          * Each ASC-38C1600 function has only two cable detect bits.
5614          * The bus mode override bits are in IOPB_SOFT_OVER_WR.
5615          */
5616         scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5617 
5618         /*
5619          * If the cable is reversed all of the SCSI_CTRL register signals
5620          * will be set. Check for and return an error if this condition is
5621          * found.
5622          */
5623         if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5624                 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5625                 return ADV_ERROR;
5626         }
5627 
5628         /*
5629          * Each ASC-38C1600 function has two connectors. Only an HVD device
5630          * can not be connected to either connector. An LVD device or SE device
5631          * may be connected to either connecor. If an SE device is connected,
5632          * then at most Ultra speed (20 Mhz) can be used on both connectors.
5633          *
5634          * If an HVD device is attached, return an error.
5635          */
5636         if (scsi_cfg1 & HVD) {
5637                 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
5638                 return ADV_ERROR;
5639         }
5640 
5641         /*
5642          * Each function in the ASC-38C1600 uses only the SE cable detect and
5643          * termination because there are two connectors for each function. Each
5644          * function may use either LVD or SE mode. Corresponding the SE automatic
5645          * termination control EEPROM bits are used for each function. Each
5646          * function has its own EEPROM. If SE automatic control is enabled for
5647          * the function, then set the termination value based on a table listed
5648          * in a_condor.h.
5649          *
5650          * If manual termination is specified in the EEPROM for the function,
5651          * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
5652          * ready to be 'ored' into SCSI_CFG1.
5653          */
5654         if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5655                 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
5656                 /* SE automatic termination control is enabled. */
5657                 switch (scsi_cfg1 & C_DET_SE) {
5658                         /* TERM_SE_HI: on, TERM_SE_LO: on */
5659                 case 0x1:
5660                 case 0x2:
5661                 case 0x3:
5662                         asc_dvc->cfg->termination |= TERM_SE;
5663                         break;
5664 
5665                 case 0x0:
5666                         if (PCI_FUNC(pdev->devfn) == 0) {
5667                                 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
5668                         } else {
5669                                 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
5670                                 asc_dvc->cfg->termination |= TERM_SE_HI;
5671                         }
5672                         break;
5673                 }
5674         }
5675 
5676         /*
5677          * Clear any set TERM_SE bits.
5678          */
5679         scsi_cfg1 &= ~TERM_SE;
5680 
5681         /*
5682          * Invert the TERM_SE bits and then set 'scsi_cfg1'.
5683          */
5684         scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
5685 
5686         /*
5687          * Clear Big Endian and Terminator Polarity bits and set possibly
5688          * modified termination control bits in the Microcode SCSI_CFG1
5689          * Register Value.
5690          *
5691          * Big Endian bit is not used even on big endian machines.
5692          */
5693         scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
5694 
5695         /*
5696          * Set SCSI_CFG1 Microcode Default Value
5697          *
5698          * Set possibly modified termination control bits in the Microcode
5699          * SCSI_CFG1 Register Value.
5700          *
5701          * The microcode will set the SCSI_CFG1 register using this value
5702          * after it is started below.
5703          */
5704         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5705 
5706         /*
5707          * Set MEM_CFG Microcode Default Value
5708          *
5709          * The microcode will set the MEM_CFG register using this value
5710          * after it is started below.
5711          *
5712          * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5713          * are defined.
5714          *
5715          * ASC-38C1600 has 32KB internal memory.
5716          *
5717          * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
5718          * out a special 16K Adv Library and Microcode version. After the issue
5719          * resolved, we should turn back to the 32K support. Both a_condor.h and
5720          * mcode.sas files also need to be updated.
5721          *
5722          * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5723          *  BIOS_EN | RAM_SZ_32KB);
5724          */
5725         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5726                          BIOS_EN | RAM_SZ_16KB);
5727 
5728         /*
5729          * Set SEL_MASK Microcode Default Value
5730          *
5731          * The microcode will set the SEL_MASK register using this value
5732          * after it is started below.
5733          */
5734         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5735                          ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5736 
5737         AdvBuildCarrierFreelist(asc_dvc);
5738 
5739         /*
5740          * Set-up the Host->RISC Initiator Command Queue (ICQ).
5741          */
5742         asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
5743         if (!asc_dvc->icq_sp) {
5744                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5745                 return ADV_ERROR;
5746         }
5747 
5748         /*
5749          * Set RISC ICQ physical address start value. Initialize the
5750          * COMMA register to the same value otherwise the RISC will
5751          * prematurely detect a command is available.
5752          */
5753         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5754         AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
5755                               le32_to_cpu(asc_dvc->icq_sp->carr_pa));
5756 
5757         /*
5758          * Set-up the RISC->Host Initiator Response Queue (IRQ).
5759          */
5760         asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
5761         if (!asc_dvc->irq_sp) {
5762                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5763                 return ADV_ERROR;
5764         }
5765 
5766         /*
5767          * Set RISC IRQ physical address start value.
5768          */
5769         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5770         asc_dvc->carr_pending_cnt = 0;
5771 
5772         AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5773                              (ADV_INTR_ENABLE_HOST_INTR |
5774                               ADV_INTR_ENABLE_GLOBAL_INTR));
5775         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5776         AdvWriteWordRegister(iop_base, IOPW_PC, word);
5777 
5778         /* finally, finally, gentlemen, start your engine */
5779         AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5780 
5781         /*
5782          * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5783          * Resets should be performed. The RISC has to be running
5784          * to issue a SCSI Bus Reset.
5785          */
5786         if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5787                 /*
5788                  * If the BIOS Signature is present in memory, restore the
5789                  * per TID microcode operating variables.
5790                  */
5791                 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5792                     0x55AA) {
5793                         /*
5794                          * Restore per TID negotiated values.
5795                          */
5796                         AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5797                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5798                         AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5799                         AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5800                                          tagqng_able);
5801                         for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5802                                 AdvWriteByteLram(iop_base,
5803                                                  ASC_MC_NUMBER_OF_MAX_CMD + tid,
5804                                                  max_cmd[tid]);
5805                         }
5806                 } else {
5807                         if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5808                                 warn_code = ASC_WARN_BUSRESET_ERROR;
5809                         }
5810                 }
5811         }
5812 
5813         return warn_code;
5814 }
5815 
5816 /*
5817  * Reset chip and SCSI Bus.
5818  *
5819  * Return Value:
5820  *      ADV_TRUE(1) -   Chip re-initialization and SCSI Bus Reset successful.
5821  *      ADV_FALSE(0) -  Chip re-initialization and SCSI Bus Reset failure.
5822  */
5823 static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
5824 {
5825         int status;
5826         ushort wdtr_able, sdtr_able, tagqng_able;
5827         ushort ppr_able = 0;
5828         uchar tid, max_cmd[ADV_MAX_TID + 1];
5829         AdvPortAddr iop_base;
5830         ushort bios_sig;
5831 
5832         iop_base = asc_dvc->iop_base;
5833 
5834         /*
5835          * Save current per TID negotiated values.
5836          */
5837         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5838         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5839         if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5840                 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5841         }
5842         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5843         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5844                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5845                                 max_cmd[tid]);
5846         }
5847 
5848         /*
5849          * Force the AdvInitAsc3550/38C0800Driver() function to
5850          * perform a SCSI Bus Reset by clearing the BIOS signature word.
5851          * The initialization functions assumes a SCSI Bus Reset is not
5852          * needed if the BIOS signature word is present.
5853          */
5854         AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
5855         AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
5856 
5857         /*
5858          * Stop chip and reset it.
5859          */
5860         AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
5861         AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
5862         mdelay(100);
5863         AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
5864                              ADV_CTRL_REG_CMD_WR_IO_REG);
5865 
5866         /*
5867          * Reset Adv Library error code, if any, and try
5868          * re-initializing the chip.
5869          */
5870         asc_dvc->err_code = 0;
5871         if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5872                 status = AdvInitAsc38C1600Driver(asc_dvc);
5873         } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
5874                 status = AdvInitAsc38C0800Driver(asc_dvc);
5875         } else {
5876                 status = AdvInitAsc3550Driver(asc_dvc);
5877         }
5878 
5879         /* Translate initialization return value to status value. */
5880         if (status == 0) {
5881                 status = ADV_TRUE;
5882         } else {
5883                 status = ADV_FALSE;
5884         }
5885 
5886         /*
5887          * Restore the BIOS signature word.
5888          */
5889         AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
5890 
5891         /*
5892          * Restore per TID negotiated values.
5893          */
5894         AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5895         AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5896         if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5897                 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5898         }
5899         AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5900         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5901                 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5902                                  max_cmd[tid]);
5903         }
5904 
5905         return status;
5906 }
5907 
5908 /*
5909  * adv_async_callback() - Adv Library asynchronous event callback function.
5910  */
5911 static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
5912 {
5913         switch (code) {
5914         case ADV_ASYNC_SCSI_BUS_RESET_DET:
5915                 /*
5916                  * The firmware detected a SCSI Bus reset.
5917                  */
5918                 ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n");
5919                 break;
5920 
5921         case ADV_ASYNC_RDMA_FAILURE:
5922                 /*
5923                  * Handle RDMA failure by resetting the SCSI Bus and
5924                  * possibly the chip if it is unresponsive. Log the error
5925                  * with a unique code.
5926                  */
5927                 ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n");
5928                 AdvResetChipAndSB(adv_dvc_varp);
5929                 break;
5930 
5931         case ADV_HOST_SCSI_BUS_RESET:
5932                 /*
5933                  * Host generated SCSI bus reset occurred.
5934                  */
5935                 ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n");
5936                 break;
5937 
5938         default:
5939                 ASC_DBG(0, "unknown code 0x%x\n", code);
5940                 break;
5941         }
5942 }
5943 
5944 /*
5945  * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
5946  *
5947  * Callback function for the Wide SCSI Adv Library.
5948  */
5949 static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
5950 {
5951         struct asc_board *boardp = adv_dvc_varp->drv_ptr;
5952         u32 srb_tag;
5953         adv_req_t *reqp;
5954         adv_sgblk_t *sgblkp;
5955         struct scsi_cmnd *scp;
5956         u32 resid_cnt;
5957         dma_addr_t sense_addr;
5958 
5959         ASC_DBG(1, "adv_dvc_varp 0x%p, scsiqp 0x%p\n",
5960                 adv_dvc_varp, scsiqp);
5961         ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
5962 
5963         /*
5964          * Get the adv_req_t structure for the command that has been
5965          * completed. The adv_req_t structure actually contains the
5966          * completed ADV_SCSI_REQ_Q structure.
5967          */
5968         srb_tag = le32_to_cpu(scsiqp->srb_tag);
5969         scp = scsi_host_find_tag(boardp->shost, scsiqp->srb_tag);
5970 
5971         ASC_DBG(1, "scp 0x%p\n", scp);
5972         if (scp == NULL) {
5973                 ASC_PRINT
5974                     ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
5975                 return;
5976         }
5977         ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
5978 
5979         reqp = (adv_req_t *)scp->host_scribble;
5980         ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp);
5981         if (reqp == NULL) {
5982                 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
5983                 return;
5984         }
5985         /*
5986          * Remove backreferences to avoid duplicate
5987          * command completions.
5988          */
5989         scp->host_scribble = NULL;
5990         reqp->cmndp = NULL;
5991 
5992         ASC_STATS(boardp->shost, callback);
5993         ASC_DBG(1, "shost 0x%p\n", boardp->shost);
5994 
5995         sense_addr = le32_to_cpu(scsiqp->sense_addr);
5996         dma_unmap_single(boardp->dev, sense_addr,
5997                          SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
5998 
5999         /*
6000          * 'done_status' contains the command's ending status.
6001          */
6002         switch (scsiqp->done_status) {
6003         case QD_NO_ERROR:
6004                 ASC_DBG(2, "QD_NO_ERROR\n");
6005                 scp->result = 0;
6006 
6007                 /*
6008                  * Check for an underrun condition.
6009                  *
6010                  * If there was no error and an underrun condition, then
6011                  * then return the number of underrun bytes.
6012                  */
6013                 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
6014                 if (scsi_bufflen(scp) != 0 && resid_cnt != 0 &&
6015                     resid_cnt <= scsi_bufflen(scp)) {
6016                         ASC_DBG(1, "underrun condition %lu bytes\n",
6017                                  (ulong)resid_cnt);
6018                         scsi_set_resid(scp, resid_cnt);
6019                 }
6020                 break;
6021 
6022         case QD_WITH_ERROR:
6023                 ASC_DBG(2, "QD_WITH_ERROR\n");
6024                 switch (scsiqp->host_status) {
6025                 case QHSTA_NO_ERROR:
6026                         if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
6027                                 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
6028                                 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
6029                                                   SCSI_SENSE_BUFFERSIZE);
6030                                 /*
6031                                  * Note: The 'status_byte()' macro used by
6032                                  * target drivers defined in scsi.h shifts the
6033                                  * status byte returned by host drivers right
6034                                  * by 1 bit.  This is why target drivers also
6035                                  * use right shifted status byte definitions.
6036                                  * For instance target drivers use
6037                                  * CHECK_CONDITION, defined to 0x1, instead of
6038                                  * the SCSI defined check condition value of
6039                                  * 0x2. Host drivers are supposed to return
6040                                  * the status byte as it is defined by SCSI.
6041                                  */
6042                                 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
6043                                     STATUS_BYTE(scsiqp->scsi_status);
6044                         } else {
6045                                 scp->result = STATUS_BYTE(scsiqp->scsi_status);
6046                         }
6047                         break;
6048 
6049                 default:
6050                         /* Some other QHSTA error occurred. */
6051                         ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status);
6052                         scp->result = HOST_BYTE(DID_BAD_TARGET);
6053                         break;
6054                 }
6055                 break;
6056 
6057         case QD_ABORTED_BY_HOST:
6058                 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
6059                 scp->result =
6060                     HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
6061                 break;
6062 
6063         default:
6064                 ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status);
6065                 scp->result =
6066                     HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
6067                 break;
6068         }
6069 
6070         /*
6071          * If the 'init_tidmask' bit isn't already set for the target and the
6072          * current request finished normally, then set the bit for the target
6073          * to indicate that a device is present.
6074          */
6075         if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6076             scsiqp->done_status == QD_NO_ERROR &&
6077             scsiqp->host_status == QHSTA_NO_ERROR) {
6078                 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6079         }
6080 
6081         asc_scsi_done(scp);
6082 
6083         /*
6084          * Free all 'adv_sgblk_t' structures allocated for the request.
6085          */
6086         while ((sgblkp = reqp->sgblkp) != NULL) {
6087                 /* Remove 'sgblkp' from the request list. */
6088                 reqp->sgblkp = sgblkp->next_sgblkp;
6089 
6090                 dma_pool_free(boardp->adv_sgblk_pool, sgblkp,
6091                               sgblkp->sg_addr);
6092         }
6093 
6094         ASC_DBG(1, "done\n");
6095 }
6096 
6097 /*
6098  * Adv Library Interrupt Service Routine
6099  *
6100  *  This function is called by a driver's interrupt service routine.
6101  *  The function disables and re-enables interrupts.
6102  *
6103  *  When a microcode idle command is completed, the ADV_DVC_VAR
6104  *  'idle_cmd_done' field is set to ADV_TRUE.
6105  *
6106  *  Note: AdvISR() can be called when interrupts are disabled or even
6107  *  when there is no hardware interrupt condition present. It will
6108  *  always check for completed idle commands and microcode requests.
6109  *  This is an important feature that shouldn't be changed because it
6110  *  allows commands to be completed from polling mode loops.
6111  *
6112  * Return:
6113  *   ADV_TRUE(1) - interrupt was pending
6114  *   ADV_FALSE(0) - no interrupt was pending
6115  */
6116 static int AdvISR(ADV_DVC_VAR *asc_dvc)
6117 {
6118         AdvPortAddr iop_base;
6119         uchar int_stat;
6120         ushort target_bit;
6121         ADV_CARR_T *free_carrp;
6122         __le32 irq_next_vpa;
6123         ADV_SCSI_REQ_Q *scsiq;
6124         adv_req_t *reqp;
6125 
6126         iop_base = asc_dvc->iop_base;
6127 
6128         /* Reading the register clears the interrupt. */
6129         int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
6130 
6131         if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
6132                          ADV_INTR_STATUS_INTRC)) == 0) {
6133                 return ADV_FALSE;
6134         }
6135 
6136         /*
6137          * Notify the driver of an asynchronous microcode condition by
6138          * calling the adv_async_callback function. The function
6139          * is passed the microcode ASC_MC_INTRB_CODE byte value.
6140          */
6141         if (int_stat & ADV_INTR_STATUS_INTRB) {
6142                 uchar intrb_code;
6143 
6144                 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
6145 
6146                 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
6147                     asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
6148                         if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
6149                             asc_dvc->carr_pending_cnt != 0) {
6150                                 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
6151                                                      ADV_TICKLE_A);
6152                                 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
6153                                         AdvWriteByteRegister(iop_base,
6154                                                              IOPB_TICKLE,
6155                                                              ADV_TICKLE_NOP);
6156                                 }
6157                         }
6158                 }
6159 
6160                 adv_async_callback(asc_dvc, intrb_code);
6161         }
6162 
6163         /*
6164          * Check if the IRQ stopper carrier contains a completed request.
6165          */
6166         while (((irq_next_vpa =
6167                  le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ADV_RQ_DONE) != 0) {
6168                 /*
6169                  * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
6170                  * The RISC will have set 'areq_vpa' to a virtual address.
6171                  *
6172                  * The firmware will have copied the ADV_SCSI_REQ_Q.scsiq_ptr
6173                  * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
6174                  * below complements the conversion of ADV_SCSI_REQ_Q.scsiq_ptr'
6175                  * in AdvExeScsiQueue().
6176                  */
6177                 u32 pa_offset = le32_to_cpu(asc_dvc->irq_sp->areq_vpa);
6178                 ASC_DBG(1, "irq_sp %p areq_vpa %u\n",
6179                         asc_dvc->irq_sp, pa_offset);
6180                 reqp = adv_get_reqp(asc_dvc, pa_offset);
6181                 scsiq = &reqp->scsi_req_q;
6182 
6183                 /*
6184                  * Request finished with good status and the queue was not
6185                  * DMAed to host memory by the firmware. Set all status fields
6186                  * to indicate good status.
6187                  */
6188                 if ((irq_next_vpa & ADV_RQ_GOOD) != 0) {
6189                         scsiq->done_status = QD_NO_ERROR;
6190                         scsiq->host_status = scsiq->scsi_status = 0;
6191                         scsiq->data_cnt = 0L;
6192                 }
6193 
6194                 /*
6195                  * Advance the stopper pointer to the next carrier
6196                  * ignoring the lower four bits. Free the previous
6197                  * stopper carrier.
6198                  */
6199                 free_carrp = asc_dvc->irq_sp;
6200                 asc_dvc->irq_sp = adv_get_carrier(asc_dvc,
6201                                                   ADV_GET_CARRP(irq_next_vpa));
6202 
6203                 free_carrp->next_vpa = asc_dvc->carr_freelist->carr_va;
6204                 asc_dvc->carr_freelist = free_carrp;
6205                 asc_dvc->carr_pending_cnt--;
6206 
6207                 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
6208 
6209                 /*
6210                  * Clear request microcode control flag.
6211                  */
6212                 scsiq->cntl = 0;
6213 
6214                 /*
6215                  * Notify the driver of the completed request by passing
6216                  * the ADV_SCSI_REQ_Q pointer to its callback function.
6217                  */
6218                 adv_isr_callback(asc_dvc, scsiq);
6219                 /*
6220                  * Note: After the driver callback function is called, 'scsiq'
6221                  * can no longer be referenced.
6222                  *
6223                  * Fall through and continue processing other completed
6224                  * requests...
6225                  */
6226         }
6227         return ADV_TRUE;
6228 }
6229 
6230 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
6231 {
6232         if (asc_dvc->err_code == 0) {
6233                 asc_dvc->err_code = err_code;
6234                 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
6235                                  err_code);
6236         }
6237         return err_code;
6238 }
6239 
6240 static void AscAckInterrupt(PortAddr iop_base)
6241 {
6242         uchar host_flag;
6243         uchar risc_flag;
6244         ushort loop;
6245 
6246         loop = 0;
6247         do {
6248                 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
6249                 if (loop++ > 0x7FFF) {
6250                         break;
6251                 }
6252         } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
6253         host_flag =
6254             AscReadLramByte(iop_base,
6255                             ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
6256         AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
6257                          (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
6258         AscSetChipStatus(iop_base, CIW_INT_ACK);
6259         loop = 0;
6260         while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
6261                 AscSetChipStatus(iop_base, CIW_INT_ACK);
6262                 if (loop++ > 3) {
6263                         break;
6264                 }
6265         }
6266         AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
6267 }
6268 
6269 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
6270 {
6271         const uchar *period_table;
6272         int max_index;
6273         int min_index;
6274         int i;
6275 
6276         period_table = asc_dvc->sdtr_period_tbl;
6277         max_index = (int)asc_dvc->max_sdtr_index;
6278         min_index = (int)asc_dvc->min_sdtr_index;
6279         if ((syn_time <= period_table[max_index])) {
6280                 for (i = min_index; i < (max_index - 1); i++) {
6281                         if (syn_time <= period_table[i]) {
6282                                 return (uchar)i;
6283                         }
6284                 }
6285                 return (uchar)max_index;
6286         } else {
6287                 return (uchar)(max_index + 1);
6288         }
6289 }
6290 
6291 static uchar
6292 AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
6293 {
6294         EXT_MSG sdtr_buf;
6295         uchar sdtr_period_index;
6296         PortAddr iop_base;
6297 
6298         iop_base = asc_dvc->iop_base;
6299         sdtr_buf.msg_type = EXTENDED_MESSAGE;
6300         sdtr_buf.msg_len = MS_SDTR_LEN;
6301         sdtr_buf.msg_req = EXTENDED_SDTR;
6302         sdtr_buf.xfer_period = sdtr_period;
6303         sdtr_offset &= ASC_SYN_MAX_OFFSET;
6304         sdtr_buf.req_ack_offset = sdtr_offset;
6305         sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6306         if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
6307                 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6308                                         (uchar *)&sdtr_buf,
6309                                         sizeof(EXT_MSG) >> 1);
6310                 return ((sdtr_period_index << 4) | sdtr_offset);
6311         } else {
6312                 sdtr_buf.req_ack_offset = 0;
6313                 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6314                                         (uchar *)&sdtr_buf,
6315                                         sizeof(EXT_MSG) >> 1);
6316                 return 0;
6317         }
6318 }
6319 
6320 static uchar
6321 AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
6322 {
6323         uchar byte;
6324         uchar sdtr_period_ix;
6325 
6326         sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6327         if (sdtr_period_ix > asc_dvc->max_sdtr_index)
6328                 return 0xFF;
6329         byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
6330         return byte;
6331 }
6332 
6333 static bool AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
6334 {
6335         ASC_SCSI_BIT_ID_TYPE org_id;
6336         int i;
6337         bool sta = true;
6338 
6339         AscSetBank(iop_base, 1);
6340         org_id = AscReadChipDvcID(iop_base);
6341         for (i = 0; i <= ASC_MAX_TID; i++) {
6342                 if (org_id == (0x01 << i))
6343                         break;
6344         }
6345         org_id = (ASC_SCSI_BIT_ID_TYPE) i;
6346         AscWriteChipDvcID(iop_base, id);
6347         if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
6348                 AscSetBank(iop_base, 0);
6349                 AscSetChipSyn(iop_base, sdtr_data);
6350                 if (AscGetChipSyn(iop_base) != sdtr_data) {
6351                         sta = false;
6352                 }
6353         } else {
6354                 sta = false;
6355         }
6356         AscSetBank(iop_base, 1);
6357         AscWriteChipDvcID(iop_base, org_id);
6358         AscSetBank(iop_base, 0);
6359         return (sta);
6360 }
6361 
6362 static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
6363 {
6364         AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
6365         AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
6366 }
6367 
6368 static void AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
6369 {
6370         EXT_MSG ext_msg;
6371         EXT_MSG out_msg;
6372         ushort halt_q_addr;
6373         bool sdtr_accept;
6374         ushort int_halt_code;
6375         ASC_SCSI_BIT_ID_TYPE scsi_busy;
6376         ASC_SCSI_BIT_ID_TYPE target_id;
6377         PortAddr iop_base;
6378         uchar tag_code;
6379         uchar q_status;
6380         uchar halt_qp;
6381         uchar sdtr_data;
6382         uchar target_ix;
6383         uchar q_cntl, tid_no;
6384         uchar cur_dvc_qng;
6385         uchar asyn_sdtr;
6386         uchar scsi_status;
6387         struct asc_board *boardp;
6388 
6389         BUG_ON(!asc_dvc->drv_ptr);
6390         boardp = asc_dvc->drv_ptr;
6391 
6392         iop_base = asc_dvc->iop_base;
6393         int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
6394 
6395         halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
6396         halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
6397         target_ix = AscReadLramByte(iop_base,
6398                                     (ushort)(halt_q_addr +
6399                                              (ushort)ASC_SCSIQ_B_TARGET_IX));
6400         q_cntl = AscReadLramByte(iop_base,
6401                             (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6402         tid_no = ASC_TIX_TO_TID(target_ix);
6403         target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
6404         if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6405                 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
6406         } else {
6407                 asyn_sdtr = 0;
6408         }
6409         if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
6410                 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6411                         AscSetChipSDTR(iop_base, 0, tid_no);
6412                         boardp->sdtr_data[tid_no] = 0;
6413                 }
6414                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6415                 return;
6416         } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
6417                 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6418                         AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6419                         boardp->sdtr_data[tid_no] = asyn_sdtr;
6420                 }
6421                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6422                 return;
6423         } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
6424                 AscMemWordCopyPtrFromLram(iop_base,
6425                                           ASCV_MSGIN_BEG,
6426                                           (uchar *)&ext_msg,
6427                                           sizeof(EXT_MSG) >> 1);
6428 
6429                 if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6430                     ext_msg.msg_req == EXTENDED_SDTR &&
6431                     ext_msg.msg_len == MS_SDTR_LEN) {
6432                         sdtr_accept = true;
6433                         if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
6434 
6435                                 sdtr_accept = false;
6436                                 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
6437                         }
6438                         if ((ext_msg.xfer_period <
6439                              asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index])
6440                             || (ext_msg.xfer_period >
6441                                 asc_dvc->sdtr_period_tbl[asc_dvc->
6442                                                          max_sdtr_index])) {
6443                                 sdtr_accept = false;
6444                                 ext_msg.xfer_period =
6445                                     asc_dvc->sdtr_period_tbl[asc_dvc->
6446                                                              min_sdtr_index];
6447                         }
6448                         if (sdtr_accept) {
6449                                 sdtr_data =
6450                                     AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
6451                                                    ext_msg.req_ack_offset);
6452                                 if ((sdtr_data == 0xFF)) {
6453 
6454                                         q_cntl |= QC_MSG_OUT;
6455                                         asc_dvc->init_sdtr &= ~target_id;
6456                                         asc_dvc->sdtr_done &= ~target_id;
6457                                         AscSetChipSDTR(iop_base, asyn_sdtr,
6458                                                        tid_no);
6459                                         boardp->sdtr_data[tid_no] = asyn_sdtr;
6460                                 }
6461                         }
6462                         if (ext_msg.req_ack_offset == 0) {
6463 
6464                                 q_cntl &= ~QC_MSG_OUT;
6465                                 asc_dvc->init_sdtr &= ~target_id;
6466                                 asc_dvc->sdtr_done &= ~target_id;
6467                                 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6468                         } else {
6469                                 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
6470                                         q_cntl &= ~QC_MSG_OUT;
6471                                         asc_dvc->sdtr_done |= target_id;
6472                                         asc_dvc->init_sdtr |= target_id;
6473                                         asc_dvc->pci_fix_asyn_xfer &=
6474                                             ~target_id;
6475                                         sdtr_data =
6476                                             AscCalSDTRData(asc_dvc,
6477                                                            ext_msg.xfer_period,
6478                                                            ext_msg.
6479                                                            req_ack_offset);
6480                                         AscSetChipSDTR(iop_base, sdtr_data,
6481                                                        tid_no);
6482                                         boardp->sdtr_data[tid_no] = sdtr_data;
6483                                 } else {
6484                                         q_cntl |= QC_MSG_OUT;
6485                                         AscMsgOutSDTR(asc_dvc,
6486                                                       ext_msg.xfer_period,
6487                                                       ext_msg.req_ack_offset);
6488                                         asc_dvc->pci_fix_asyn_xfer &=
6489                                             ~target_id;
6490                                         sdtr_data =
6491                                             AscCalSDTRData(asc_dvc,
6492                                                            ext_msg.xfer_period,
6493                                                            ext_msg.
6494                                                            req_ack_offset);
6495                                         AscSetChipSDTR(iop_base, sdtr_data,
6496                                                        tid_no);
6497                                         boardp->sdtr_data[tid_no] = sdtr_data;
6498                                         asc_dvc->sdtr_done |= target_id;
6499                                         asc_dvc->init_sdtr |= target_id;
6500                                 }
6501                         }
6502 
6503                         AscWriteLramByte(iop_base,
6504                                          (ushort)(halt_q_addr +
6505                                                   (ushort)ASC_SCSIQ_B_CNTL),
6506                                          q_cntl);
6507                         AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6508                         return;
6509                 } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6510                            ext_msg.msg_req == EXTENDED_WDTR &&
6511                            ext_msg.msg_len == MS_WDTR_LEN) {
6512 
6513                         ext_msg.wdtr_width = 0;
6514                         AscMemWordCopyPtrToLram(iop_base,
6515                                                 ASCV_MSGOUT_BEG,
6516                                                 (uchar *)&ext_msg,
6517                                                 sizeof(EXT_MSG) >> 1);
6518                         q_cntl |= QC_MSG_OUT;
6519                         AscWriteLramByte(iop_base,
6520                                          (ushort)(halt_q_addr +
6521                                                   (ushort)ASC_SCSIQ_B_CNTL),
6522                                          q_cntl);
6523                         AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6524                         return;
6525                 } else {
6526 
6527                         ext_msg.msg_type = MESSAGE_REJECT;
6528                         AscMemWordCopyPtrToLram(iop_base,
6529                                                 ASCV_MSGOUT_BEG,
6530                                                 (uchar *)&ext_msg,
6531                                                 sizeof(EXT_MSG) >> 1);
6532                         q_cntl |= QC_MSG_OUT;
6533                         AscWriteLramByte(iop_base,
6534                                          (ushort)(halt_q_addr +
6535                                                   (ushort)ASC_SCSIQ_B_CNTL),
6536                                          q_cntl);
6537                         AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6538                         return;
6539                 }
6540         } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
6541 
6542                 q_cntl |= QC_REQ_SENSE;
6543 
6544                 if ((asc_dvc->init_sdtr & target_id) != 0) {
6545 
6546                         asc_dvc->sdtr_done &= ~target_id;
6547 
6548                         sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
6549                         q_cntl |= QC_MSG_OUT;
6550                         AscMsgOutSDTR(asc_dvc,
6551                                       asc_dvc->
6552                                       sdtr_period_tbl[(sdtr_data >> 4) &
6553                                                       (uchar)(asc_dvc->
6554                                                               max_sdtr_index -
6555                                                               1)],
6556                                       (uchar)(sdtr_data & (uchar)
6557                                               ASC_SYN_MAX_OFFSET));
6558                 }
6559 
6560                 AscWriteLramByte(iop_base,
6561                                  (ushort)(halt_q_addr +
6562                                           (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6563 
6564                 tag_code = AscReadLramByte(iop_base,
6565                                            (ushort)(halt_q_addr + (ushort)
6566                                                     ASC_SCSIQ_B_TAG_CODE));
6567                 tag_code &= 0xDC;
6568                 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
6569                     && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
6570                     ) {
6571 
6572                         tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
6573                                      | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
6574 
6575                 }
6576                 AscWriteLramByte(iop_base,
6577                                  (ushort)(halt_q_addr +
6578                                           (ushort)ASC_SCSIQ_B_TAG_CODE),
6579                                  tag_code);
6580 
6581                 q_status = AscReadLramByte(iop_base,
6582                                            (ushort)(halt_q_addr + (ushort)
6583                                                     ASC_SCSIQ_B_STATUS));
6584                 q_status |= (QS_READY | QS_BUSY);
6585                 AscWriteLramByte(iop_base,
6586                                  (ushort)(halt_q_addr +
6587                                           (ushort)ASC_SCSIQ_B_STATUS),
6588                                  q_status);
6589 
6590                 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
6591                 scsi_busy &= ~target_id;
6592                 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6593 
6594                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6595                 return;
6596         } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
6597 
6598                 AscMemWordCopyPtrFromLram(iop_base,
6599                                           ASCV_MSGOUT_BEG,
6600                                           (uchar *)&out_msg,
6601                                           sizeof(EXT_MSG) >> 1);
6602 
6603                 if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
6604                     (out_msg.msg_len == MS_SDTR_LEN) &&
6605                     (out_msg.msg_req == EXTENDED_SDTR)) {
6606 
6607                         asc_dvc->init_sdtr &= ~target_id;
6608                         asc_dvc->sdtr_done &= ~target_id;
6609                         AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6610                         boardp->sdtr_data[tid_no] = asyn_sdtr;
6611                 }
6612                 q_cntl &= ~QC_MSG_OUT;
6613                 AscWriteLramByte(iop_base,
6614                                  (ushort)(halt_q_addr +
6615                                           (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6616                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6617                 return;
6618         } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
6619 
6620                 scsi_status = AscReadLramByte(iop_base,
6621                                               (ushort)((ushort)halt_q_addr +
6622                                                        (ushort)
6623                                                        ASC_SCSIQ_SCSI_STATUS));
6624                 cur_dvc_qng =
6625                     AscReadLramByte(iop_base,
6626                                     (ushort)((ushort)ASC_QADR_BEG +
6627                                              (ushort)target_ix));
6628                 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
6629 
6630                         scsi_busy = AscReadLramByte(iop_base,
6631                                                     (ushort)ASCV_SCSIBUSY_B);
6632                         scsi_busy |= target_id;
6633                         AscWriteLramByte(iop_base,
6634                                          (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6635                         asc_dvc->queue_full_or_busy |= target_id;
6636 
6637                         if (scsi_status == SAM_STAT_TASK_SET_FULL) {
6638                                 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
6639                                         cur_dvc_qng -= 1;
6640                                         asc_dvc->max_dvc_qng[tid_no] =
6641                                             cur_dvc_qng;
6642 
6643                                         AscWriteLramByte(iop_base,
6644                                                          (ushort)((ushort)
6645                                                                   ASCV_MAX_DVC_QNG_BEG
6646                                                                   + (ushort)
6647                                                                   tid_no),
6648                                                          cur_dvc_qng);
6649 
6650                                         /*
6651                                          * Set the device queue depth to the
6652                                          * number of active requests when the
6653                                          * QUEUE FULL condition was encountered.
6654                                          */
6655                                         boardp->queue_full |= target_id;
6656                                         boardp->queue_full_cnt[tid_no] =
6657                                             cur_dvc_qng;
6658                                 }
6659                         }
6660                 }
6661                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6662                 return;
6663         }
6664         return;
6665 }
6666 
6667 /*
6668  * void
6669  * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
6670  *
6671  * Calling/Exit State:
6672  *    none
6673  *
6674  * Description:
6675  *     Input an ASC_QDONE_INFO structure from the chip
6676  */
6677 static void
6678 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
6679 {
6680         int i;
6681         ushort word;
6682 
6683         AscSetChipLramAddr(iop_base, s_addr);
6684         for (i = 0; i < 2 * words; i += 2) {
6685                 if (i == 10) {
6686                         continue;
6687                 }
6688                 word = inpw(iop_base + IOP_RAM_DATA);
6689                 inbuf[i] = word & 0xff;
6690                 inbuf[i + 1] = (word >> 8) & 0xff;
6691         }
6692         ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
6693 }
6694 
6695 static uchar
6696 _AscCopyLramScsiDoneQ(PortAddr iop_base,
6697                       ushort q_addr,
6698                       ASC_QDONE_INFO *scsiq, unsigned int max_dma_count)
6699 {
6700         ushort _val;
6701         uchar sg_queue_cnt;
6702 
6703         DvcGetQinfo(iop_base,
6704                     q_addr + ASC_SCSIQ_DONE_INFO_BEG,
6705                     (uchar *)scsiq,
6706                     (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
6707 
6708         _val = AscReadLramWord(iop_base,
6709                                (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
6710         scsiq->q_status = (uchar)_val;
6711         scsiq->q_no = (uchar)(_val >> 8);
6712         _val = AscReadLramWord(iop_base,
6713                                (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6714         scsiq->cntl = (uchar)_val;
6715         sg_queue_cnt = (uchar)(_val >> 8);
6716         _val = AscReadLramWord(iop_base,
6717                                (ushort)(q_addr +
6718                                         (ushort)ASC_SCSIQ_B_SENSE_LEN));
6719         scsiq->sense_len = (uchar)_val;
6720         scsiq->extra_bytes = (uchar)(_val >> 8);
6721 
6722         /*
6723          * Read high word of remain bytes from alternate location.
6724          */
6725         scsiq->remain_bytes = (((u32)AscReadLramWord(iop_base,
6726                                                      (ushort)(q_addr +
6727                                                               (ushort)
6728                                                               ASC_SCSIQ_W_ALT_DC1)))
6729                                << 16);
6730         /*
6731          * Read low word of remain bytes from original location.
6732          */
6733         scsiq->remain_bytes += AscReadLramWord(iop_base,
6734                                                (ushort)(q_addr + (ushort)
6735                                                         ASC_SCSIQ_DW_REMAIN_XFER_CNT));
6736 
6737         scsiq->remain_bytes &= max_dma_count;
6738         return sg_queue_cnt;
6739 }
6740 
6741 /*
6742  * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
6743  *
6744  * Interrupt callback function for the Narrow SCSI Asc Library.
6745  */
6746 static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
6747 {
6748         struct asc_board *boardp = asc_dvc_varp->drv_ptr;
6749         u32 srb_tag;
6750         struct scsi_cmnd *scp;
6751 
6752         ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep);
6753         ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
6754 
6755         /*
6756          * Decrease the srb_tag by 1 to find the SCSI command
6757          */
6758         srb_tag = qdonep->d2.srb_tag - 1;
6759         scp = scsi_host_find_tag(boardp->shost, srb_tag);
6760         if (!scp)
6761                 return;
6762 
6763         ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6764 
6765         ASC_STATS(boardp->shost, callback);
6766 
6767         dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
6768                          SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
6769         /*
6770          * 'qdonep' contains the command's ending status.
6771          */
6772         switch (qdonep->d3.done_stat) {
6773         case QD_NO_ERROR:
6774                 ASC_DBG(2, "QD_NO_ERROR\n");
6775                 scp->result = 0;
6776 
6777                 /*
6778                  * Check for an underrun condition.
6779                  *
6780                  * If there was no error and an underrun condition, then
6781                  * return the number of underrun bytes.
6782                  */
6783                 if (scsi_bufflen(scp) != 0 && qdonep->remain_bytes != 0 &&
6784                     qdonep->remain_bytes <= scsi_bufflen(scp)) {
6785                         ASC_DBG(1, "underrun condition %u bytes\n",
6786                                  (unsigned)qdonep->remain_bytes);
6787                         scsi_set_resid(scp, qdonep->remain_bytes);
6788                 }
6789                 break;
6790 
6791         case QD_WITH_ERROR:
6792                 ASC_DBG(2, "QD_WITH_ERROR\n");
6793                 switch (qdonep->d3.host_stat) {
6794                 case QHSTA_NO_ERROR:
6795                         if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
6796                                 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
6797                                 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
6798                                                   SCSI_SENSE_BUFFERSIZE);
6799                                 /*
6800                                  * Note: The 'status_byte()' macro used by
6801                                  * target drivers defined in scsi.h shifts the
6802                                  * status byte returned by host drivers right
6803                                  * by 1 bit.  This is why target drivers also
6804                                  * use right shifted status byte definitions.
6805                                  * For instance target drivers use
6806                                  * CHECK_CONDITION, defined to 0x1, instead of
6807                                  * the SCSI defined check condition value of
6808                                  * 0x2. Host drivers are supposed to return
6809                                  * the status byte as it is defined by SCSI.
6810                                  */
6811                                 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
6812                                     STATUS_BYTE(qdonep->d3.scsi_stat);
6813                         } else {
6814                                 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
6815                         }
6816                         break;
6817 
6818                 default:
6819                         /* QHSTA error occurred */
6820                         ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat);
6821                         scp->result = HOST_BYTE(DID_BAD_TARGET);
6822                         break;
6823                 }
6824                 break;
6825 
6826         case QD_ABORTED_BY_HOST:
6827                 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
6828                 scp->result =
6829                     HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
6830                                                     scsi_msg) |
6831                     STATUS_BYTE(qdonep->d3.scsi_stat);
6832                 break;
6833 
6834         default:
6835                 ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat);
6836                 scp->result =
6837                     HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
6838                                                     scsi_msg) |
6839                     STATUS_BYTE(qdonep->d3.scsi_stat);
6840                 break;
6841         }
6842 
6843         /*
6844          * If the 'init_tidmask' bit isn't already set for the target and the
6845          * current request finished normally, then set the bit for the target
6846          * to indicate that a device is present.
6847          */
6848         if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6849             qdonep->d3.done_stat == QD_NO_ERROR &&
6850             qdonep->d3.host_stat == QHSTA_NO_ERROR) {
6851                 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6852         }
6853 
6854         asc_scsi_done(scp);
6855 }
6856 
6857 static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
6858 {
6859         uchar next_qp;
6860         uchar n_q_used;
6861         uchar sg_list_qp;
6862         uchar sg_queue_cnt;
6863         uchar q_cnt;
6864         uchar done_q_tail;
6865         uchar tid_no;
6866         ASC_SCSI_BIT_ID_TYPE scsi_busy;
6867         ASC_SCSI_BIT_ID_TYPE target_id;
6868         PortAddr iop_base;
6869         ushort q_addr;
6870         ushort sg_q_addr;
6871         uchar cur_target_qng;
6872         ASC_QDONE_INFO scsiq_buf;
6873         ASC_QDONE_INFO *scsiq;
6874         bool false_overrun;
6875 
6876         iop_base = asc_dvc->iop_base;
6877         n_q_used = 1;
6878         scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
6879         done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
6880         q_addr = ASC_QNO_TO_QADDR(done_q_tail);
6881         next_qp = AscReadLramByte(iop_base,
6882                                   (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
6883         if (next_qp != ASC_QLINK_END) {
6884                 AscPutVarDoneQTail(iop_base, next_qp);
6885                 q_addr = ASC_QNO_TO_QADDR(next_qp);
6886                 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
6887                                                      asc_dvc->max_dma_count);
6888                 AscWriteLramByte(iop_base,
6889                                  (ushort)(q_addr +
6890                                           (ushort)ASC_SCSIQ_B_STATUS),
6891                                  (uchar)(scsiq->
6892                                          q_status & (uchar)~(QS_READY |
6893                                                              QS_ABORTED)));
6894                 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
6895                 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
6896                 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
6897                         sg_q_addr = q_addr;
6898                         sg_list_qp = next_qp;
6899                         for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
6900                                 sg_list_qp = AscReadLramByte(iop_base,
6901                                                              (ushort)(sg_q_addr
6902                                                                       + (ushort)
6903                                                                       ASC_SCSIQ_B_FWD));
6904                                 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
6905                                 if (sg_list_qp == ASC_QLINK_END) {
6906                                         AscSetLibErrorCode(asc_dvc,
6907                                                            ASCQ_ERR_SG_Q_LINKS);
6908                                         scsiq->d3.done_stat = QD_WITH_ERROR;
6909                                         scsiq->d3.host_stat =
6910                                             QHSTA_D_QDONE_SG_LIST_CORRUPTED;
6911                                         goto FATAL_ERR_QDONE;
6912                                 }
6913                                 AscWriteLramByte(iop_base,
6914                                                  (ushort)(sg_q_addr + (ushort)
6915                                                           ASC_SCSIQ_B_STATUS),
6916                                                  QS_FREE);
6917                         }
6918                         n_q_used = sg_queue_cnt + 1;
6919                         AscPutVarDoneQTail(iop_base, sg_list_qp);
6920                 }
6921                 if (asc_dvc->queue_full_or_busy & target_id) {
6922                         cur_target_qng = AscReadLramByte(iop_base,
6923                                                          (ushort)((ushort)
6924                                                                   ASC_QADR_BEG
6925                                                                   + (ushort)
6926                                                                   scsiq->d2.
6927                                                                   target_ix));
6928                         if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
6929                                 scsi_busy = AscReadLramByte(iop_base, (ushort)
6930                                                             ASCV_SCSIBUSY_B);
6931                                 scsi_busy &= ~target_id;
6932                                 AscWriteLramByte(iop_base,
6933                                                  (ushort)ASCV_SCSIBUSY_B,
6934                                                  scsi_busy);
6935                                 asc_dvc->queue_full_or_busy &= ~target_id;
6936                         }
6937                 }
6938                 if (asc_dvc->cur_total_qng >= n_q_used) {
6939                         asc_dvc->cur_total_qng -= n_q_used;
6940                         if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
6941                                 asc_dvc->cur_dvc_qng[tid_no]--;
6942                         }
6943                 } else {
6944                         AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
6945                         scsiq->d3.done_stat = QD_WITH_ERROR;
6946                         goto FATAL_ERR_QDONE;
6947                 }
6948                 if ((scsiq->d2.srb_tag == 0UL) ||
6949                     ((scsiq->q_status & QS_ABORTED) != 0)) {
6950                         return (0x11);
6951                 } else if (scsiq->q_status == QS_DONE) {
6952                         /*
6953                          * This is also curious.
6954                          * false_overrun will _always_ be set to 'false'
6955                          */
6956                         false_overrun = false;
6957                         if (scsiq->extra_bytes != 0) {
6958                                 scsiq->remain_bytes += scsiq->extra_bytes;
6959                         }
6960                         if (scsiq->d3.done_stat == QD_WITH_ERROR) {
6961                                 if (scsiq->d3.host_stat ==
6962                                     QHSTA_M_DATA_OVER_RUN) {
6963                                         if ((scsiq->
6964                                              cntl & (QC_DATA_IN | QC_DATA_OUT))
6965                                             == 0) {
6966                                                 scsiq->d3.done_stat =
6967                                                     QD_NO_ERROR;
6968                                                 scsiq->d3.host_stat =
6969                                                     QHSTA_NO_ERROR;
6970                                         } else if (false_overrun) {
6971                                                 scsiq->d3.done_stat =
6972                                                     QD_NO_ERROR;
6973                                                 scsiq->d3.host_stat =
6974                                                     QHSTA_NO_ERROR;
6975                                         }
6976                                 } else if (scsiq->d3.host_stat ==
6977                                            QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
6978                                         AscStopChip(iop_base);
6979                                         AscSetChipControl(iop_base,
6980                                                           (uchar)(CC_SCSI_RESET
6981                                                                   | CC_HALT));
6982                                         udelay(60);
6983                                         AscSetChipControl(iop_base, CC_HALT);
6984                                         AscSetChipStatus(iop_base,
6985                                                          CIW_CLR_SCSI_RESET_INT);
6986                                         AscSetChipStatus(iop_base, 0);
6987                                         AscSetChipControl(iop_base, 0);
6988                                 }
6989                         }
6990                         if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
6991                                 asc_isr_callback(asc_dvc, scsiq);
6992                         } else {
6993                                 if ((AscReadLramByte(iop_base,
6994                                                      (ushort)(q_addr + (ushort)
6995                                                               ASC_SCSIQ_CDB_BEG))
6996                                      == START_STOP)) {
6997                                         asc_dvc->unit_not_ready &= ~target_id;
6998                                         if (scsiq->d3.done_stat != QD_NO_ERROR) {
6999                                                 asc_dvc->start_motor &=
7000                                                     ~target_id;
7001                                         }
7002                                 }
7003                         }
7004                         return (1);
7005                 } else {
7006                         AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
7007  FATAL_ERR_QDONE:
7008                         if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7009                                 asc_isr_callback(asc_dvc, scsiq);
7010                         }
7011                         return (0x80);
7012                 }
7013         }
7014         return (0);
7015 }
7016 
7017 static int AscISR(ASC_DVC_VAR *asc_dvc)
7018 {
7019         ASC_CS_TYPE chipstat;
7020         PortAddr iop_base;
7021         ushort saved_ram_addr;
7022         uchar ctrl_reg;
7023         uchar saved_ctrl_reg;
7024         int int_pending;
7025         int status;
7026         uchar host_flag;
7027 
7028         iop_base = asc_dvc->iop_base;
7029         int_pending = ASC_FALSE;
7030 
7031         if (AscIsIntPending(iop_base) == 0)
7032                 return int_pending;
7033 
7034         if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
7035                 return ASC_ERROR;
7036         }
7037         if (asc_dvc->in_critical_cnt != 0) {
7038                 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
7039                 return ASC_ERROR;
7040         }
7041         if (asc_dvc->is_in_int) {
7042                 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
7043                 return ASC_ERROR;
7044         }
7045         asc_dvc->is_in_int = true;
7046         ctrl_reg = AscGetChipControl(iop_base);
7047         saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
7048                                        CC_SINGLE_STEP | CC_DIAG | CC_TEST));
7049         chipstat = AscGetChipStatus(iop_base);
7050         if (chipstat & CSW_SCSI_RESET_LATCH) {
7051                 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
7052                         int i = 10;
7053                         int_pending = ASC_TRUE;
7054                         asc_dvc->sdtr_done = 0;
7055                         saved_ctrl_reg &= (uchar)(~CC_HALT);
7056                         while ((AscGetChipStatus(iop_base) &
7057                                 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
7058                                 mdelay(100);
7059                         }
7060                         AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
7061                         AscSetChipControl(iop_base, CC_HALT);
7062                         AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
7063                         AscSetChipStatus(iop_base, 0);
7064                         chipstat = AscGetChipStatus(iop_base);
7065                 }
7066         }
7067         saved_ram_addr = AscGetChipLramAddr(iop_base);
7068         host_flag = AscReadLramByte(iop_base,
7069                                     ASCV_HOST_FLAG_B) &
7070             (uchar)(~ASC_HOST_FLAG_IN_ISR);
7071         AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
7072                          (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
7073         if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
7074                 AscAckInterrupt(iop_base);
7075                 int_pending = ASC_TRUE;
7076                 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
7077                         AscIsrChipHalted(asc_dvc);
7078                         saved_ctrl_reg &= (uchar)(~CC_HALT);
7079                 } else {
7080                         if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
7081                                 while (((status =
7082                                          AscIsrQDone(asc_dvc)) & 0x01) != 0) {
7083                                 }
7084                         } else {
7085                                 do {
7086                                         if ((status =
7087                                              AscIsrQDone(asc_dvc)) == 1) {
7088                                                 break;
7089                                         }
7090                                 } while (status == 0x11);
7091                         }
7092                         if ((status & 0x80) != 0)
7093                                 int_pending = ASC_ERROR;
7094                 }
7095         }
7096         AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
7097         AscSetChipLramAddr(iop_base, saved_ram_addr);
7098         AscSetChipControl(iop_base, saved_ctrl_reg);
7099         asc_dvc->is_in_int = false;
7100         return int_pending;
7101 }
7102 
7103 /*
7104  * advansys_reset()
7105  *
7106  * Reset the host associated with the command 'scp'.
7107  *
7108  * This function runs its own thread. Interrupts must be blocked but
7109  * sleeping is allowed and no locking other than for host structures is
7110  * required. Returns SUCCESS or FAILED.
7111  */
7112 static int advansys_reset(struct scsi_cmnd *scp)
7113 {
7114         struct Scsi_Host *shost = scp->device->host;
7115         struct asc_board *boardp = shost_priv(shost);
7116         unsigned long flags;
7117         int status;
7118         int ret = SUCCESS;
7119 
7120         ASC_DBG(1, "0x%p\n", scp);
7121 
7122         ASC_STATS(shost, reset);
7123 
7124         scmd_printk(KERN_INFO, scp, "SCSI host reset started...\n");
7125 
7126         if (ASC_NARROW_BOARD(boardp)) {
7127                 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
7128 
7129                 /* Reset the chip and SCSI bus. */
7130                 ASC_DBG(1, "before AscInitAsc1000Driver()\n");
7131                 status = AscInitAsc1000Driver(asc_dvc);
7132 
7133                 /* Refer to ASC_IERR_* definitions for meaning of 'err_code'. */
7134                 if (asc_dvc->err_code || !asc_dvc->overrun_dma) {
7135                         scmd_printk(KERN_INFO, scp, "SCSI host reset error: "
7136                                     "0x%x, status: 0x%x\n", asc_dvc->err_code,
7137                                     status);
7138                         ret = FAILED;
7139                 } else if (status) {
7140                         scmd_printk(KERN_INFO, scp, "SCSI host reset warning: "
7141                                     "0x%x\n", status);
7142                 } else {
7143                         scmd_printk(KERN_INFO, scp, "SCSI host reset "
7144                                     "successful\n");
7145                 }
7146 
7147                 ASC_DBG(1, "after AscInitAsc1000Driver()\n");
7148         } else {
7149                 /*
7150                  * If the suggest reset bus flags are set, then reset the bus.
7151                  * Otherwise only reset the device.
7152                  */
7153                 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
7154 
7155                 /*
7156                  * Reset the chip and SCSI bus.
7157                  */
7158                 ASC_DBG(1, "before AdvResetChipAndSB()\n");
7159                 switch (AdvResetChipAndSB(adv_dvc)) {
7160                 case ASC_TRUE:
7161                         scmd_printk(KERN_INFO, scp, "SCSI host reset "
7162                                     "successful\n");
7163                         break;
7164                 case ASC_FALSE:
7165                 default:
7166                         scmd_printk(KERN_INFO, scp, "SCSI host reset error\n");
7167                         ret = FAILED;
7168                         break;
7169                 }
7170                 spin_lock_irqsave(shost->host_lock, flags);
7171                 AdvISR(adv_dvc);
7172                 spin_unlock_irqrestore(shost->host_lock, flags);
7173         }
7174 
7175         ASC_DBG(1, "ret %d\n", ret);
7176 
7177         return ret;
7178 }
7179 
7180 /*
7181  * advansys_biosparam()
7182  *
7183  * Translate disk drive geometry if the "BIOS greater than 1 GB"
7184  * support is enabled for a drive.
7185  *
7186  * ip (information pointer) is an int array with the following definition:
7187  * ip[0]: heads
7188  * ip[1]: sectors
7189  * ip[2]: cylinders
7190  */
7191 static int
7192 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
7193                    sector_t capacity, int ip[])
7194 {
7195         struct asc_board *boardp = shost_priv(sdev->host);
7196 
7197         ASC_DBG(1, "begin\n");
7198         ASC_STATS(sdev->host, biosparam);
7199         if (ASC_NARROW_BOARD(boardp)) {
7200                 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
7201                      ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
7202                         ip[0] = 255;
7203                         ip[1] = 63;
7204                 } else {
7205                         ip[0] = 64;
7206                         ip[1] = 32;
7207                 }
7208         } else {
7209                 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
7210                      BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
7211                         ip[0] = 255;
7212                         ip[1] = 63;
7213                 } else {
7214                         ip[0] = 64;
7215                         ip[1] = 32;
7216                 }
7217         }
7218         ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
7219         ASC_DBG(1, "end\n");
7220         return 0;
7221 }
7222 
7223 /*
7224  * First-level interrupt handler.
7225  *
7226  * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
7227  */
7228 static irqreturn_t advansys_interrupt(int irq, void *dev_id)
7229 {
7230         struct Scsi_Host *shost = dev_id;
7231         struct asc_board *boardp = shost_priv(shost);
7232         irqreturn_t result = IRQ_NONE;
7233         unsigned long flags;
7234 
7235         ASC_DBG(2, "boardp 0x%p\n", boardp);
7236         spin_lock_irqsave(shost->host_lock, flags);
7237         if (ASC_NARROW_BOARD(boardp)) {
7238                 if (AscIsIntPending(shost->io_port)) {
7239                         result = IRQ_HANDLED;
7240                         ASC_STATS(shost, interrupt);
7241                         ASC_DBG(1, "before AscISR()\n");
7242                         AscISR(&boardp->dvc_var.asc_dvc_var);
7243                 }
7244         } else {
7245                 ASC_DBG(1, "before AdvISR()\n");
7246                 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
7247                         result = IRQ_HANDLED;
7248                         ASC_STATS(shost, interrupt);
7249                 }
7250         }
7251         spin_unlock_irqrestore(shost->host_lock, flags);
7252 
7253         ASC_DBG(1, "end\n");
7254         return result;
7255 }
7256 
7257 static bool AscHostReqRiscHalt(PortAddr iop_base)
7258 {
7259         int count = 0;
7260         bool sta = false;
7261         uchar saved_stop_code;
7262 
7263         if (AscIsChipHalted(iop_base))