Version:  2.0.40 2.2.26 2.4.37 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0

Linux/drivers/scsi/advansys.c

  1 #define DRV_NAME "advansys"
  2 #define ASC_VERSION "3.4"       /* AdvanSys Driver Version */
  3 
  4 /*
  5  * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
  6  *
  7  * Copyright (c) 1995-2000 Advanced System Products, Inc.
  8  * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
  9  * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
 10  * All Rights Reserved.
 11  *
 12  * This program is free software; you can redistribute it and/or modify
 13  * it under the terms of the GNU General Public License as published by
 14  * the Free Software Foundation; either version 2 of the License, or
 15  * (at your option) any later version.
 16  */
 17 
 18 /*
 19  * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
 20  * changed its name to ConnectCom Solutions, Inc.
 21  * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
 22  */
 23 
 24 #include <linux/module.h>
 25 #include <linux/string.h>
 26 #include <linux/kernel.h>
 27 #include <linux/types.h>
 28 #include <linux/ioport.h>
 29 #include <linux/interrupt.h>
 30 #include <linux/delay.h>
 31 #include <linux/slab.h>
 32 #include <linux/mm.h>
 33 #include <linux/proc_fs.h>
 34 #include <linux/init.h>
 35 #include <linux/blkdev.h>
 36 #include <linux/isa.h>
 37 #include <linux/eisa.h>
 38 #include <linux/pci.h>
 39 #include <linux/spinlock.h>
 40 #include <linux/dma-mapping.h>
 41 #include <linux/firmware.h>
 42 
 43 #include <asm/io.h>
 44 #include <asm/dma.h>
 45 
 46 #include <scsi/scsi_cmnd.h>
 47 #include <scsi/scsi_device.h>
 48 #include <scsi/scsi_tcq.h>
 49 #include <scsi/scsi.h>
 50 #include <scsi/scsi_host.h>
 51 
 52 /* FIXME:
 53  *
 54  *  1. Although all of the necessary command mapping places have the
 55  *     appropriate dma_map.. APIs, the driver still processes its internal
 56  *     queue using bus_to_virt() and virt_to_bus() which are illegal under
 57  *     the API.  The entire queue processing structure will need to be
 58  *     altered to fix this.
 59  *  2. Need to add memory mapping workaround. Test the memory mapping.
 60  *     If it doesn't work revert to I/O port access. Can a test be done
 61  *     safely?
 62  *  3. Handle an interrupt not working. Keep an interrupt counter in
 63  *     the interrupt handler. In the timeout function if the interrupt
 64  *     has not occurred then print a message and run in polled mode.
 65  *  4. Need to add support for target mode commands, cf. CAM XPT.
 66  *  5. check DMA mapping functions for failure
 67  *  6. Use scsi_transport_spi
 68  *  7. advansys_info is not safe against multiple simultaneous callers
 69  *  8. Add module_param to override ISA/VLB ioport array
 70  */
 71 #warning this driver is still not properly converted to the DMA API
 72 
 73 /* Enable driver /proc statistics. */
 74 #define ADVANSYS_STATS
 75 
 76 /* Enable driver tracing. */
 77 #undef ADVANSYS_DEBUG
 78 
 79 /*
 80  * Portable Data Types
 81  *
 82  * Any instance where a 32-bit long or pointer type is assumed
 83  * for precision or HW defined structures, the following define
 84  * types must be used. In Linux the char, short, and int types
 85  * are all consistent at 8, 16, and 32 bits respectively. Pointers
 86  * and long types are 64 bits on Alpha and UltraSPARC.
 87  */
 88 #define ASC_PADDR __u32         /* Physical/Bus address data type. */
 89 #define ASC_VADDR __u32         /* Virtual address data type. */
 90 #define ASC_DCNT  __u32         /* Unsigned Data count type. */
 91 #define ASC_SDCNT __s32         /* Signed Data count type. */
 92 
 93 typedef unsigned char uchar;
 94 
 95 #ifndef TRUE
 96 #define TRUE     (1)
 97 #endif
 98 #ifndef FALSE
 99 #define FALSE    (0)
100 #endif
101 
102 #define ERR      (-1)
103 #define UW_ERR   (uint)(0xFFFF)
104 #define isodd_word(val)   ((((uint)val) & (uint)0x0001) != 0)
105 
106 #define PCI_VENDOR_ID_ASP               0x10cd
107 #define PCI_DEVICE_ID_ASP_1200A         0x1100
108 #define PCI_DEVICE_ID_ASP_ABP940        0x1200
109 #define PCI_DEVICE_ID_ASP_ABP940U       0x1300
110 #define PCI_DEVICE_ID_ASP_ABP940UW      0x2300
111 #define PCI_DEVICE_ID_38C0800_REV1      0x2500
112 #define PCI_DEVICE_ID_38C1600_REV1      0x2700
113 
114 /*
115  * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
116  * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
117  * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
118  * SRB structure.
119  */
120 #define CC_VERY_LONG_SG_LIST 0
121 #define ASC_SRB2SCSIQ(srb_ptr)  (srb_ptr)
122 
123 #define PortAddr                 unsigned int   /* port address size  */
124 #define inp(port)                inb(port)
125 #define outp(port, byte)         outb((byte), (port))
126 
127 #define inpw(port)               inw(port)
128 #define outpw(port, word)        outw((word), (port))
129 
130 #define ASC_MAX_SG_QUEUE    7
131 #define ASC_MAX_SG_LIST     255
132 
133 #define ASC_CS_TYPE  unsigned short
134 
135 #define ASC_IS_ISA          (0x0001)
136 #define ASC_IS_ISAPNP       (0x0081)
137 #define ASC_IS_EISA         (0x0002)
138 #define ASC_IS_PCI          (0x0004)
139 #define ASC_IS_PCI_ULTRA    (0x0104)
140 #define ASC_IS_PCMCIA       (0x0008)
141 #define ASC_IS_MCA          (0x0020)
142 #define ASC_IS_VL           (0x0040)
143 #define ASC_IS_WIDESCSI_16  (0x0100)
144 #define ASC_IS_WIDESCSI_32  (0x0200)
145 #define ASC_IS_BIG_ENDIAN   (0x8000)
146 
147 #define ASC_CHIP_MIN_VER_VL      (0x01)
148 #define ASC_CHIP_MAX_VER_VL      (0x07)
149 #define ASC_CHIP_MIN_VER_PCI     (0x09)
150 #define ASC_CHIP_MAX_VER_PCI     (0x0F)
151 #define ASC_CHIP_VER_PCI_BIT     (0x08)
152 #define ASC_CHIP_MIN_VER_ISA     (0x11)
153 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
154 #define ASC_CHIP_MAX_VER_ISA     (0x27)
155 #define ASC_CHIP_VER_ISA_BIT     (0x30)
156 #define ASC_CHIP_VER_ISAPNP_BIT  (0x20)
157 #define ASC_CHIP_VER_ASYN_BUG    (0x21)
158 #define ASC_CHIP_VER_PCI             0x08
159 #define ASC_CHIP_VER_PCI_ULTRA_3150  (ASC_CHIP_VER_PCI | 0x02)
160 #define ASC_CHIP_VER_PCI_ULTRA_3050  (ASC_CHIP_VER_PCI | 0x03)
161 #define ASC_CHIP_MIN_VER_EISA (0x41)
162 #define ASC_CHIP_MAX_VER_EISA (0x47)
163 #define ASC_CHIP_VER_EISA_BIT (0x40)
164 #define ASC_CHIP_LATEST_VER_EISA   ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
165 #define ASC_MAX_VL_DMA_COUNT    (0x07FFFFFFL)
166 #define ASC_MAX_PCI_DMA_COUNT   (0xFFFFFFFFL)
167 #define ASC_MAX_ISA_DMA_COUNT   (0x00FFFFFFL)
168 
169 #define ASC_SCSI_ID_BITS  3
170 #define ASC_SCSI_TIX_TYPE     uchar
171 #define ASC_ALL_DEVICE_BIT_SET  0xFF
172 #define ASC_SCSI_BIT_ID_TYPE  uchar
173 #define ASC_MAX_TID       7
174 #define ASC_MAX_LUN       7
175 #define ASC_SCSI_WIDTH_BIT_SET  0xFF
176 #define ASC_MAX_SENSE_LEN   32
177 #define ASC_MIN_SENSE_LEN   14
178 #define ASC_SCSI_RESET_HOLD_TIME_US  60
179 
180 /*
181  * Narrow boards only support 12-byte commands, while wide boards
182  * extend to 16-byte commands.
183  */
184 #define ASC_MAX_CDB_LEN     12
185 #define ADV_MAX_CDB_LEN     16
186 
187 #define MS_SDTR_LEN    0x03
188 #define MS_WDTR_LEN    0x02
189 
190 #define ASC_SG_LIST_PER_Q   7
191 #define QS_FREE        0x00
192 #define QS_READY       0x01
193 #define QS_DISC1       0x02
194 #define QS_DISC2       0x04
195 #define QS_BUSY        0x08
196 #define QS_ABORTED     0x40
197 #define QS_DONE        0x80
198 #define QC_NO_CALLBACK   0x01
199 #define QC_SG_SWAP_QUEUE 0x02
200 #define QC_SG_HEAD       0x04
201 #define QC_DATA_IN       0x08
202 #define QC_DATA_OUT      0x10
203 #define QC_URGENT        0x20
204 #define QC_MSG_OUT       0x40
205 #define QC_REQ_SENSE     0x80
206 #define QCSG_SG_XFER_LIST  0x02
207 #define QCSG_SG_XFER_MORE  0x04
208 #define QCSG_SG_XFER_END   0x08
209 #define QD_IN_PROGRESS       0x00
210 #define QD_NO_ERROR          0x01
211 #define QD_ABORTED_BY_HOST   0x02
212 #define QD_WITH_ERROR        0x04
213 #define QD_INVALID_REQUEST   0x80
214 #define QD_INVALID_HOST_NUM  0x81
215 #define QD_INVALID_DEVICE    0x82
216 #define QD_ERR_INTERNAL      0xFF
217 #define QHSTA_NO_ERROR               0x00
218 #define QHSTA_M_SEL_TIMEOUT          0x11
219 #define QHSTA_M_DATA_OVER_RUN        0x12
220 #define QHSTA_M_DATA_UNDER_RUN       0x12
221 #define QHSTA_M_UNEXPECTED_BUS_FREE  0x13
222 #define QHSTA_M_BAD_BUS_PHASE_SEQ    0x14
223 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
224 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET  0x22
225 #define QHSTA_D_HOST_ABORT_FAILED       0x23
226 #define QHSTA_D_EXE_SCSI_Q_FAILED       0x24
227 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
228 #define QHSTA_D_ASPI_NO_BUF_POOL        0x26
229 #define QHSTA_M_WTM_TIMEOUT         0x41
230 #define QHSTA_M_BAD_CMPL_STATUS_IN  0x42
231 #define QHSTA_M_NO_AUTO_REQ_SENSE   0x43
232 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
233 #define QHSTA_M_TARGET_STATUS_BUSY  0x45
234 #define QHSTA_M_BAD_TAG_CODE        0x46
235 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY  0x47
236 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
237 #define QHSTA_D_LRAM_CMP_ERROR        0x81
238 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
239 #define ASC_FLAG_SCSIQ_REQ        0x01
240 #define ASC_FLAG_BIOS_SCSIQ_REQ   0x02
241 #define ASC_FLAG_BIOS_ASYNC_IO    0x04
242 #define ASC_FLAG_SRB_LINEAR_ADDR  0x08
243 #define ASC_FLAG_WIN16            0x10
244 #define ASC_FLAG_WIN32            0x20
245 #define ASC_FLAG_ISA_OVER_16MB    0x40
246 #define ASC_FLAG_DOS_VM_CALLBACK  0x80
247 #define ASC_TAG_FLAG_EXTRA_BYTES               0x10
248 #define ASC_TAG_FLAG_DISABLE_DISCONNECT        0x04
249 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX  0x08
250 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
251 #define ASC_SCSIQ_CPY_BEG              4
252 #define ASC_SCSIQ_SGHD_CPY_BEG         2
253 #define ASC_SCSIQ_B_FWD                0
254 #define ASC_SCSIQ_B_BWD                1
255 #define ASC_SCSIQ_B_STATUS             2
256 #define ASC_SCSIQ_B_QNO                3
257 #define ASC_SCSIQ_B_CNTL               4
258 #define ASC_SCSIQ_B_SG_QUEUE_CNT       5
259 #define ASC_SCSIQ_D_DATA_ADDR          8
260 #define ASC_SCSIQ_D_DATA_CNT          12
261 #define ASC_SCSIQ_B_SENSE_LEN         20
262 #define ASC_SCSIQ_DONE_INFO_BEG       22
263 #define ASC_SCSIQ_D_SRBPTR            22
264 #define ASC_SCSIQ_B_TARGET_IX         26
265 #define ASC_SCSIQ_B_CDB_LEN           28
266 #define ASC_SCSIQ_B_TAG_CODE          29
267 #define ASC_SCSIQ_W_VM_ID             30
268 #define ASC_SCSIQ_DONE_STATUS         32
269 #define ASC_SCSIQ_HOST_STATUS         33
270 #define ASC_SCSIQ_SCSI_STATUS         34
271 #define ASC_SCSIQ_CDB_BEG             36
272 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
273 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT  60
274 #define ASC_SCSIQ_B_FIRST_SG_WK_QP    48
275 #define ASC_SCSIQ_B_SG_WK_QP          49
276 #define ASC_SCSIQ_B_SG_WK_IX          50
277 #define ASC_SCSIQ_W_ALT_DC1           52
278 #define ASC_SCSIQ_B_LIST_CNT          6
279 #define ASC_SCSIQ_B_CUR_LIST_CNT      7
280 #define ASC_SGQ_B_SG_CNTL             4
281 #define ASC_SGQ_B_SG_HEAD_QP          5
282 #define ASC_SGQ_B_SG_LIST_CNT         6
283 #define ASC_SGQ_B_SG_CUR_LIST_CNT     7
284 #define ASC_SGQ_LIST_BEG              8
285 #define ASC_DEF_SCSI1_QNG    4
286 #define ASC_MAX_SCSI1_QNG    4
287 #define ASC_DEF_SCSI2_QNG    16
288 #define ASC_MAX_SCSI2_QNG    32
289 #define ASC_TAG_CODE_MASK    0x23
290 #define ASC_STOP_REQ_RISC_STOP      0x01
291 #define ASC_STOP_ACK_RISC_STOP      0x03
292 #define ASC_STOP_CLEAN_UP_BUSY_Q    0x10
293 #define ASC_STOP_CLEAN_UP_DISC_Q    0x20
294 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
295 #define ASC_TIDLUN_TO_IX(tid, lun)  (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
296 #define ASC_TID_TO_TARGET_ID(tid)   (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
297 #define ASC_TIX_TO_TARGET_ID(tix)   (0x01 << ((tix) & ASC_MAX_TID))
298 #define ASC_TIX_TO_TID(tix)         ((tix) & ASC_MAX_TID)
299 #define ASC_TID_TO_TIX(tid)         ((tid) & ASC_MAX_TID)
300 #define ASC_TIX_TO_LUN(tix)         (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
301 #define ASC_QNO_TO_QADDR(q_no)      ((ASC_QADR_BEG)+((int)(q_no) << 6))
302 
303 typedef struct asc_scsiq_1 {
304         uchar status;
305         uchar q_no;
306         uchar cntl;
307         uchar sg_queue_cnt;
308         uchar target_id;
309         uchar target_lun;
310         ASC_PADDR data_addr;
311         ASC_DCNT data_cnt;
312         ASC_PADDR sense_addr;
313         uchar sense_len;
314         uchar extra_bytes;
315 } ASC_SCSIQ_1;
316 
317 typedef struct asc_scsiq_2 {
318         ASC_VADDR srb_ptr;
319         uchar target_ix;
320         uchar flag;
321         uchar cdb_len;
322         uchar tag_code;
323         ushort vm_id;
324 } ASC_SCSIQ_2;
325 
326 typedef struct asc_scsiq_3 {
327         uchar done_stat;
328         uchar host_stat;
329         uchar scsi_stat;
330         uchar scsi_msg;
331 } ASC_SCSIQ_3;
332 
333 typedef struct asc_scsiq_4 {
334         uchar cdb[ASC_MAX_CDB_LEN];
335         uchar y_first_sg_list_qp;
336         uchar y_working_sg_qp;
337         uchar y_working_sg_ix;
338         uchar y_res;
339         ushort x_req_count;
340         ushort x_reconnect_rtn;
341         ASC_PADDR x_saved_data_addr;
342         ASC_DCNT x_saved_data_cnt;
343 } ASC_SCSIQ_4;
344 
345 typedef struct asc_q_done_info {
346         ASC_SCSIQ_2 d2;
347         ASC_SCSIQ_3 d3;
348         uchar q_status;
349         uchar q_no;
350         uchar cntl;
351         uchar sense_len;
352         uchar extra_bytes;
353         uchar res;
354         ASC_DCNT remain_bytes;
355 } ASC_QDONE_INFO;
356 
357 typedef struct asc_sg_list {
358         ASC_PADDR addr;
359         ASC_DCNT bytes;
360 } ASC_SG_LIST;
361 
362 typedef struct asc_sg_head {
363         ushort entry_cnt;
364         ushort queue_cnt;
365         ushort entry_to_copy;
366         ushort res;
367         ASC_SG_LIST sg_list[0];
368 } ASC_SG_HEAD;
369 
370 typedef struct asc_scsi_q {
371         ASC_SCSIQ_1 q1;
372         ASC_SCSIQ_2 q2;
373         uchar *cdbptr;
374         ASC_SG_HEAD *sg_head;
375         ushort remain_sg_entry_cnt;
376         ushort next_sg_index;
377 } ASC_SCSI_Q;
378 
379 typedef struct asc_scsi_req_q {
380         ASC_SCSIQ_1 r1;
381         ASC_SCSIQ_2 r2;
382         uchar *cdbptr;
383         ASC_SG_HEAD *sg_head;
384         uchar *sense_ptr;
385         ASC_SCSIQ_3 r3;
386         uchar cdb[ASC_MAX_CDB_LEN];
387         uchar sense[ASC_MIN_SENSE_LEN];
388 } ASC_SCSI_REQ_Q;
389 
390 typedef struct asc_scsi_bios_req_q {
391         ASC_SCSIQ_1 r1;
392         ASC_SCSIQ_2 r2;
393         uchar *cdbptr;
394         ASC_SG_HEAD *sg_head;
395         uchar *sense_ptr;
396         ASC_SCSIQ_3 r3;
397         uchar cdb[ASC_MAX_CDB_LEN];
398         uchar sense[ASC_MIN_SENSE_LEN];
399 } ASC_SCSI_BIOS_REQ_Q;
400 
401 typedef struct asc_risc_q {
402         uchar fwd;
403         uchar bwd;
404         ASC_SCSIQ_1 i1;
405         ASC_SCSIQ_2 i2;
406         ASC_SCSIQ_3 i3;
407         ASC_SCSIQ_4 i4;
408 } ASC_RISC_Q;
409 
410 typedef struct asc_sg_list_q {
411         uchar seq_no;
412         uchar q_no;
413         uchar cntl;
414         uchar sg_head_qp;
415         uchar sg_list_cnt;
416         uchar sg_cur_list_cnt;
417 } ASC_SG_LIST_Q;
418 
419 typedef struct asc_risc_sg_list_q {
420         uchar fwd;
421         uchar bwd;
422         ASC_SG_LIST_Q sg;
423         ASC_SG_LIST sg_list[7];
424 } ASC_RISC_SG_LIST_Q;
425 
426 #define ASCQ_ERR_Q_STATUS             0x0D
427 #define ASCQ_ERR_CUR_QNG              0x17
428 #define ASCQ_ERR_SG_Q_LINKS           0x18
429 #define ASCQ_ERR_ISR_RE_ENTRY         0x1A
430 #define ASCQ_ERR_CRITICAL_RE_ENTRY    0x1B
431 #define ASCQ_ERR_ISR_ON_CRITICAL      0x1C
432 
433 /*
434  * Warning code values are set in ASC_DVC_VAR  'warn_code'.
435  */
436 #define ASC_WARN_NO_ERROR             0x0000
437 #define ASC_WARN_IO_PORT_ROTATE       0x0001
438 #define ASC_WARN_EEPROM_CHKSUM        0x0002
439 #define ASC_WARN_IRQ_MODIFIED         0x0004
440 #define ASC_WARN_AUTO_CONFIG          0x0008
441 #define ASC_WARN_CMD_QNG_CONFLICT     0x0010
442 #define ASC_WARN_EEPROM_RECOVER       0x0020
443 #define ASC_WARN_CFG_MSW_RECOVER      0x0040
444 
445 /*
446  * Error code values are set in {ASC/ADV}_DVC_VAR  'err_code'.
447  */
448 #define ASC_IERR_NO_CARRIER             0x0001  /* No more carrier memory */
449 #define ASC_IERR_MCODE_CHKSUM           0x0002  /* micro code check sum error */
450 #define ASC_IERR_SET_PC_ADDR            0x0004
451 #define ASC_IERR_START_STOP_CHIP        0x0008  /* start/stop chip failed */
452 #define ASC_IERR_ILLEGAL_CONNECTION     0x0010  /* Illegal cable connection */
453 #define ASC_IERR_SINGLE_END_DEVICE      0x0020  /* SE device on DIFF bus */
454 #define ASC_IERR_REVERSED_CABLE         0x0040  /* Narrow flat cable reversed */
455 #define ASC_IERR_SET_SCSI_ID            0x0080  /* set SCSI ID failed */
456 #define ASC_IERR_HVD_DEVICE             0x0100  /* HVD device on LVD port */
457 #define ASC_IERR_BAD_SIGNATURE          0x0200  /* signature not found */
458 #define ASC_IERR_NO_BUS_TYPE            0x0400
459 #define ASC_IERR_BIST_PRE_TEST          0x0800  /* BIST pre-test error */
460 #define ASC_IERR_BIST_RAM_TEST          0x1000  /* BIST RAM test error */
461 #define ASC_IERR_BAD_CHIPTYPE           0x2000  /* Invalid chip_type setting */
462 
463 #define ASC_DEF_MAX_TOTAL_QNG   (0xF0)
464 #define ASC_MIN_TAG_Q_PER_DVC   (0x04)
465 #define ASC_MIN_FREE_Q        (0x02)
466 #define ASC_MIN_TOTAL_QNG     ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
467 #define ASC_MAX_TOTAL_QNG 240
468 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
469 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG   8
470 #define ASC_MAX_PCI_INRAM_TOTAL_QNG  20
471 #define ASC_MAX_INRAM_TAG_QNG   16
472 #define ASC_IOADR_GAP   0x10
473 #define ASC_SYN_MAX_OFFSET         0x0F
474 #define ASC_DEF_SDTR_OFFSET        0x0F
475 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX  0x02
476 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
477 
478 /* The narrow chip only supports a limited selection of transfer rates.
479  * These are encoded in the range 0..7 or 0..15 depending whether the chip
480  * is Ultra-capable or not.  These tables let us convert from one to the other.
481  */
482 static const unsigned char asc_syn_xfer_period[8] = {
483         25, 30, 35, 40, 50, 60, 70, 85
484 };
485 
486 static const unsigned char asc_syn_ultra_xfer_period[16] = {
487         12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
488 };
489 
490 typedef struct ext_msg {
491         uchar msg_type;
492         uchar msg_len;
493         uchar msg_req;
494         union {
495                 struct {
496                         uchar sdtr_xfer_period;
497                         uchar sdtr_req_ack_offset;
498                 } sdtr;
499                 struct {
500                         uchar wdtr_width;
501                 } wdtr;
502                 struct {
503                         uchar mdp_b3;
504                         uchar mdp_b2;
505                         uchar mdp_b1;
506                         uchar mdp_b0;
507                 } mdp;
508         } u_ext_msg;
509         uchar res;
510 } EXT_MSG;
511 
512 #define xfer_period     u_ext_msg.sdtr.sdtr_xfer_period
513 #define req_ack_offset  u_ext_msg.sdtr.sdtr_req_ack_offset
514 #define wdtr_width      u_ext_msg.wdtr.wdtr_width
515 #define mdp_b3          u_ext_msg.mdp_b3
516 #define mdp_b2          u_ext_msg.mdp_b2
517 #define mdp_b1          u_ext_msg.mdp_b1
518 #define mdp_b0          u_ext_msg.mdp_b0
519 
520 typedef struct asc_dvc_cfg {
521         ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
522         ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
523         ASC_SCSI_BIT_ID_TYPE disc_enable;
524         ASC_SCSI_BIT_ID_TYPE sdtr_enable;
525         uchar chip_scsi_id;
526         uchar isa_dma_speed;
527         uchar isa_dma_channel;
528         uchar chip_version;
529         ushort mcode_date;
530         ushort mcode_version;
531         uchar max_tag_qng[ASC_MAX_TID + 1];
532         uchar sdtr_period_offset[ASC_MAX_TID + 1];
533         uchar adapter_info[6];
534 } ASC_DVC_CFG;
535 
536 #define ASC_DEF_DVC_CNTL       0xFFFF
537 #define ASC_DEF_CHIP_SCSI_ID   7
538 #define ASC_DEF_ISA_DMA_SPEED  4
539 #define ASC_INIT_STATE_BEG_GET_CFG   0x0001
540 #define ASC_INIT_STATE_END_GET_CFG   0x0002
541 #define ASC_INIT_STATE_BEG_SET_CFG   0x0004
542 #define ASC_INIT_STATE_END_SET_CFG   0x0008
543 #define ASC_INIT_STATE_BEG_LOAD_MC   0x0010
544 #define ASC_INIT_STATE_END_LOAD_MC   0x0020
545 #define ASC_INIT_STATE_BEG_INQUIRY   0x0040
546 #define ASC_INIT_STATE_END_INQUIRY   0x0080
547 #define ASC_INIT_RESET_SCSI_DONE     0x0100
548 #define ASC_INIT_STATE_WITHOUT_EEP   0x8000
549 #define ASC_BUG_FIX_IF_NOT_DWB       0x0001
550 #define ASC_BUG_FIX_ASYN_USE_SYN     0x0002
551 #define ASC_MIN_TAGGED_CMD  7
552 #define ASC_MAX_SCSI_RESET_WAIT      30
553 #define ASC_OVERRUN_BSIZE               64
554 
555 struct asc_dvc_var;             /* Forward Declaration. */
556 
557 typedef struct asc_dvc_var {
558         PortAddr iop_base;
559         ushort err_code;
560         ushort dvc_cntl;
561         ushort bug_fix_cntl;
562         ushort bus_type;
563         ASC_SCSI_BIT_ID_TYPE init_sdtr;
564         ASC_SCSI_BIT_ID_TYPE sdtr_done;
565         ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
566         ASC_SCSI_BIT_ID_TYPE unit_not_ready;
567         ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
568         ASC_SCSI_BIT_ID_TYPE start_motor;
569         uchar *overrun_buf;
570         dma_addr_t overrun_dma;
571         uchar scsi_reset_wait;
572         uchar chip_no;
573         char is_in_int;
574         uchar max_total_qng;
575         uchar cur_total_qng;
576         uchar in_critical_cnt;
577         uchar last_q_shortage;
578         ushort init_state;
579         uchar cur_dvc_qng[ASC_MAX_TID + 1];
580         uchar max_dvc_qng[ASC_MAX_TID + 1];
581         ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
582         ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
583         const uchar *sdtr_period_tbl;
584         ASC_DVC_CFG *cfg;
585         ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
586         char redo_scam;
587         ushort res2;
588         uchar dos_int13_table[ASC_MAX_TID + 1];
589         ASC_DCNT max_dma_count;
590         ASC_SCSI_BIT_ID_TYPE no_scam;
591         ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
592         uchar min_sdtr_index;
593         uchar max_sdtr_index;
594         struct asc_board *drv_ptr;
595         int ptr_map_count;
596         void **ptr_map;
597         ASC_DCNT uc_break;
598 } ASC_DVC_VAR;
599 
600 typedef struct asc_dvc_inq_info {
601         uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
602 } ASC_DVC_INQ_INFO;
603 
604 typedef struct asc_cap_info {
605         ASC_DCNT lba;
606         ASC_DCNT blk_size;
607 } ASC_CAP_INFO;
608 
609 typedef struct asc_cap_info_array {
610         ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
611 } ASC_CAP_INFO_ARRAY;
612 
613 #define ASC_MCNTL_NO_SEL_TIMEOUT  (ushort)0x0001
614 #define ASC_MCNTL_NULL_TARGET     (ushort)0x0002
615 #define ASC_CNTL_INITIATOR         (ushort)0x0001
616 #define ASC_CNTL_BIOS_GT_1GB       (ushort)0x0002
617 #define ASC_CNTL_BIOS_GT_2_DISK    (ushort)0x0004
618 #define ASC_CNTL_BIOS_REMOVABLE    (ushort)0x0008
619 #define ASC_CNTL_NO_SCAM           (ushort)0x0010
620 #define ASC_CNTL_INT_MULTI_Q       (ushort)0x0080
621 #define ASC_CNTL_NO_LUN_SUPPORT    (ushort)0x0040
622 #define ASC_CNTL_NO_VERIFY_COPY    (ushort)0x0100
623 #define ASC_CNTL_RESET_SCSI        (ushort)0x0200
624 #define ASC_CNTL_INIT_INQUIRY      (ushort)0x0400
625 #define ASC_CNTL_INIT_VERBOSE      (ushort)0x0800
626 #define ASC_CNTL_SCSI_PARITY       (ushort)0x1000
627 #define ASC_CNTL_BURST_MODE        (ushort)0x2000
628 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
629 #define ASC_EEP_DVC_CFG_BEG_VL    2
630 #define ASC_EEP_MAX_DVC_ADDR_VL   15
631 #define ASC_EEP_DVC_CFG_BEG      32
632 #define ASC_EEP_MAX_DVC_ADDR     45
633 #define ASC_EEP_MAX_RETRY        20
634 
635 /*
636  * These macros keep the chip SCSI id and ISA DMA speed
637  * bitfields in board order. C bitfields aren't portable
638  * between big and little-endian platforms so they are
639  * not used.
640  */
641 
642 #define ASC_EEP_GET_CHIP_ID(cfg)    ((cfg)->id_speed & 0x0f)
643 #define ASC_EEP_GET_DMA_SPD(cfg)    (((cfg)->id_speed & 0xf0) >> 4)
644 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
645    ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
646 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
647    ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
648 
649 typedef struct asceep_config {
650         ushort cfg_lsw;
651         ushort cfg_msw;
652         uchar init_sdtr;
653         uchar disc_enable;
654         uchar use_cmd_qng;
655         uchar start_motor;
656         uchar max_total_qng;
657         uchar max_tag_qng;
658         uchar bios_scan;
659         uchar power_up_wait;
660         uchar no_scam;
661         uchar id_speed;         /* low order 4 bits is chip scsi id */
662         /* high order 4 bits is isa dma speed */
663         uchar dos_int13_table[ASC_MAX_TID + 1];
664         uchar adapter_info[6];
665         ushort cntl;
666         ushort chksum;
667 } ASCEEP_CONFIG;
668 
669 #define ASC_EEP_CMD_READ          0x80
670 #define ASC_EEP_CMD_WRITE         0x40
671 #define ASC_EEP_CMD_WRITE_ABLE    0x30
672 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
673 #define ASCV_MSGOUT_BEG         0x0000
674 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
675 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
676 #define ASCV_BREAK_SAVED_CODE   (ushort)0x0006
677 #define ASCV_MSGIN_BEG          (ASCV_MSGOUT_BEG+8)
678 #define ASCV_MSGIN_SDTR_PERIOD  (ASCV_MSGIN_BEG+3)
679 #define ASCV_MSGIN_SDTR_OFFSET  (ASCV_MSGIN_BEG+4)
680 #define ASCV_SDTR_DATA_BEG      (ASCV_MSGIN_BEG+8)
681 #define ASCV_SDTR_DONE_BEG      (ASCV_SDTR_DATA_BEG+8)
682 #define ASCV_MAX_DVC_QNG_BEG    (ushort)0x0020
683 #define ASCV_BREAK_ADDR           (ushort)0x0028
684 #define ASCV_BREAK_NOTIFY_COUNT   (ushort)0x002A
685 #define ASCV_BREAK_CONTROL        (ushort)0x002C
686 #define ASCV_BREAK_HIT_COUNT      (ushort)0x002E
687 
688 #define ASCV_ASCDVC_ERR_CODE_W  (ushort)0x0030
689 #define ASCV_MCODE_CHKSUM_W   (ushort)0x0032
690 #define ASCV_MCODE_SIZE_W     (ushort)0x0034
691 #define ASCV_STOP_CODE_B      (ushort)0x0036
692 #define ASCV_DVC_ERR_CODE_B   (ushort)0x0037
693 #define ASCV_OVERRUN_PADDR_D  (ushort)0x0038
694 #define ASCV_OVERRUN_BSIZE_D  (ushort)0x003C
695 #define ASCV_HALTCODE_W       (ushort)0x0040
696 #define ASCV_CHKSUM_W         (ushort)0x0042
697 #define ASCV_MC_DATE_W        (ushort)0x0044
698 #define ASCV_MC_VER_W         (ushort)0x0046
699 #define ASCV_NEXTRDY_B        (ushort)0x0048
700 #define ASCV_DONENEXT_B       (ushort)0x0049
701 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
702 #define ASCV_SCSIBUSY_B       (ushort)0x004B
703 #define ASCV_Q_DONE_IN_PROGRESS_B  (ushort)0x004C
704 #define ASCV_CURCDB_B         (ushort)0x004D
705 #define ASCV_RCLUN_B          (ushort)0x004E
706 #define ASCV_BUSY_QHEAD_B     (ushort)0x004F
707 #define ASCV_DISC1_QHEAD_B    (ushort)0x0050
708 #define ASCV_DISC_ENABLE_B    (ushort)0x0052
709 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
710 #define ASCV_HOSTSCSI_ID_B    (ushort)0x0055
711 #define ASCV_MCODE_CNTL_B     (ushort)0x0056
712 #define ASCV_NULL_TARGET_B    (ushort)0x0057
713 #define ASCV_FREE_Q_HEAD_W    (ushort)0x0058
714 #define ASCV_DONE_Q_TAIL_W    (ushort)0x005A
715 #define ASCV_FREE_Q_HEAD_B    (ushort)(ASCV_FREE_Q_HEAD_W+1)
716 #define ASCV_DONE_Q_TAIL_B    (ushort)(ASCV_DONE_Q_TAIL_W+1)
717 #define ASCV_HOST_FLAG_B      (ushort)0x005D
718 #define ASCV_TOTAL_READY_Q_B  (ushort)0x0064
719 #define ASCV_VER_SERIAL_B     (ushort)0x0065
720 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
721 #define ASCV_WTM_FLAG_B       (ushort)0x0068
722 #define ASCV_RISC_FLAG_B      (ushort)0x006A
723 #define ASCV_REQ_SG_LIST_QP   (ushort)0x006B
724 #define ASC_HOST_FLAG_IN_ISR        0x01
725 #define ASC_HOST_FLAG_ACK_INT       0x02
726 #define ASC_RISC_FLAG_GEN_INT      0x01
727 #define ASC_RISC_FLAG_REQ_SG_LIST  0x02
728 #define IOP_CTRL         (0x0F)
729 #define IOP_STATUS       (0x0E)
730 #define IOP_INT_ACK      IOP_STATUS
731 #define IOP_REG_IFC      (0x0D)
732 #define IOP_SYN_OFFSET    (0x0B)
733 #define IOP_EXTRA_CONTROL (0x0D)
734 #define IOP_REG_PC        (0x0C)
735 #define IOP_RAM_ADDR      (0x0A)
736 #define IOP_RAM_DATA      (0x08)
737 #define IOP_EEP_DATA      (0x06)
738 #define IOP_EEP_CMD       (0x07)
739 #define IOP_VERSION       (0x03)
740 #define IOP_CONFIG_HIGH   (0x04)
741 #define IOP_CONFIG_LOW    (0x02)
742 #define IOP_SIG_BYTE      (0x01)
743 #define IOP_SIG_WORD      (0x00)
744 #define IOP_REG_DC1      (0x0E)
745 #define IOP_REG_DC0      (0x0C)
746 #define IOP_REG_SB       (0x0B)
747 #define IOP_REG_DA1      (0x0A)
748 #define IOP_REG_DA0      (0x08)
749 #define IOP_REG_SC       (0x09)
750 #define IOP_DMA_SPEED    (0x07)
751 #define IOP_REG_FLAG     (0x07)
752 #define IOP_FIFO_H       (0x06)
753 #define IOP_FIFO_L       (0x04)
754 #define IOP_REG_ID       (0x05)
755 #define IOP_REG_QP       (0x03)
756 #define IOP_REG_IH       (0x02)
757 #define IOP_REG_IX       (0x01)
758 #define IOP_REG_AX       (0x00)
759 #define IFC_REG_LOCK      (0x00)
760 #define IFC_REG_UNLOCK    (0x09)
761 #define IFC_WR_EN_FILTER  (0x10)
762 #define IFC_RD_NO_EEPROM  (0x10)
763 #define IFC_SLEW_RATE     (0x20)
764 #define IFC_ACT_NEG       (0x40)
765 #define IFC_INP_FILTER    (0x80)
766 #define IFC_INIT_DEFAULT  (IFC_ACT_NEG | IFC_REG_UNLOCK)
767 #define SC_SEL   (uchar)(0x80)
768 #define SC_BSY   (uchar)(0x40)
769 #define SC_ACK   (uchar)(0x20)
770 #define SC_REQ   (uchar)(0x10)
771 #define SC_ATN   (uchar)(0x08)
772 #define SC_IO    (uchar)(0x04)
773 #define SC_CD    (uchar)(0x02)
774 #define SC_MSG   (uchar)(0x01)
775 #define SEC_SCSI_CTL         (uchar)(0x80)
776 #define SEC_ACTIVE_NEGATE    (uchar)(0x40)
777 #define SEC_SLEW_RATE        (uchar)(0x20)
778 #define SEC_ENABLE_FILTER    (uchar)(0x10)
779 #define ASC_HALT_EXTMSG_IN     (ushort)0x8000
780 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
781 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
782 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX  (ushort)0x8300
783 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX   (ushort)0x8400
784 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
785 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
786 #define ASC_MAX_QNO        0xF8
787 #define ASC_DATA_SEC_BEG   (ushort)0x0080
788 #define ASC_DATA_SEC_END   (ushort)0x0080
789 #define ASC_CODE_SEC_BEG   (ushort)0x0080
790 #define ASC_CODE_SEC_END   (ushort)0x0080
791 #define ASC_QADR_BEG       (0x4000)
792 #define ASC_QADR_USED      (ushort)(ASC_MAX_QNO * 64)
793 #define ASC_QADR_END       (ushort)0x7FFF
794 #define ASC_QLAST_ADR      (ushort)0x7FC0
795 #define ASC_QBLK_SIZE      0x40
796 #define ASC_BIOS_DATA_QBEG 0xF8
797 #define ASC_MIN_ACTIVE_QNO 0x01
798 #define ASC_QLINK_END      0xFF
799 #define ASC_EEPROM_WORDS   0x10
800 #define ASC_MAX_MGS_LEN    0x10
801 #define ASC_BIOS_ADDR_DEF  0xDC00
802 #define ASC_BIOS_SIZE      0x3800
803 #define ASC_BIOS_RAM_OFF   0x3800
804 #define ASC_BIOS_RAM_SIZE  0x800
805 #define ASC_BIOS_MIN_ADDR  0xC000
806 #define ASC_BIOS_MAX_ADDR  0xEC00
807 #define ASC_BIOS_BANK_SIZE 0x0400
808 #define ASC_MCODE_START_ADDR  0x0080
809 #define ASC_CFG0_HOST_INT_ON    0x0020
810 #define ASC_CFG0_BIOS_ON        0x0040
811 #define ASC_CFG0_VERA_BURST_ON  0x0080
812 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
813 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
814 #define ASC_CFG1_LRAM_8BITS_ON  0x0800
815 #define ASC_CFG_MSW_CLR_MASK    0x3080
816 #define CSW_TEST1             (ASC_CS_TYPE)0x8000
817 #define CSW_AUTO_CONFIG       (ASC_CS_TYPE)0x4000
818 #define CSW_RESERVED1         (ASC_CS_TYPE)0x2000
819 #define CSW_IRQ_WRITTEN       (ASC_CS_TYPE)0x1000
820 #define CSW_33MHZ_SELECTED    (ASC_CS_TYPE)0x0800
821 #define CSW_TEST2             (ASC_CS_TYPE)0x0400
822 #define CSW_TEST3             (ASC_CS_TYPE)0x0200
823 #define CSW_RESERVED2         (ASC_CS_TYPE)0x0100
824 #define CSW_DMA_DONE          (ASC_CS_TYPE)0x0080
825 #define CSW_FIFO_RDY          (ASC_CS_TYPE)0x0040
826 #define CSW_EEP_READ_DONE     (ASC_CS_TYPE)0x0020
827 #define CSW_HALTED            (ASC_CS_TYPE)0x0010
828 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
829 #define CSW_PARITY_ERR        (ASC_CS_TYPE)0x0004
830 #define CSW_SCSI_RESET_LATCH  (ASC_CS_TYPE)0x0002
831 #define CSW_INT_PENDING       (ASC_CS_TYPE)0x0001
832 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
833 #define CIW_INT_ACK      (ASC_CS_TYPE)0x0100
834 #define CIW_TEST1        (ASC_CS_TYPE)0x0200
835 #define CIW_TEST2        (ASC_CS_TYPE)0x0400
836 #define CIW_SEL_33MHZ    (ASC_CS_TYPE)0x0800
837 #define CIW_IRQ_ACT      (ASC_CS_TYPE)0x1000
838 #define CC_CHIP_RESET   (uchar)0x80
839 #define CC_SCSI_RESET   (uchar)0x40
840 #define CC_HALT         (uchar)0x20
841 #define CC_SINGLE_STEP  (uchar)0x10
842 #define CC_DMA_ABLE     (uchar)0x08
843 #define CC_TEST         (uchar)0x04
844 #define CC_BANK_ONE     (uchar)0x02
845 #define CC_DIAG         (uchar)0x01
846 #define ASC_1000_ID0W      0x04C1
847 #define ASC_1000_ID0W_FIX  0x00C1
848 #define ASC_1000_ID1B      0x25
849 #define ASC_EISA_REV_IOP_MASK  (0x0C83)
850 #define ASC_EISA_CFG_IOP_MASK  (0x0C86)
851 #define ASC_GET_EISA_SLOT(iop)  (PortAddr)((iop) & 0xF000)
852 #define INS_HALTINT        (ushort)0x6281
853 #define INS_HALT           (ushort)0x6280
854 #define INS_SINT           (ushort)0x6200
855 #define INS_RFLAG_WTM      (ushort)0x7380
856 #define ASC_MC_SAVE_CODE_WSIZE  0x500
857 #define ASC_MC_SAVE_DATA_WSIZE  0x40
858 
859 typedef struct asc_mc_saved {
860         ushort data[ASC_MC_SAVE_DATA_WSIZE];
861         ushort code[ASC_MC_SAVE_CODE_WSIZE];
862 } ASC_MC_SAVED;
863 
864 #define AscGetQDoneInProgress(port)         AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
865 #define AscPutQDoneInProgress(port, val)    AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
866 #define AscGetVarFreeQHead(port)            AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
867 #define AscGetVarDoneQTail(port)            AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
868 #define AscPutVarFreeQHead(port, val)       AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
869 #define AscPutVarDoneQTail(port, val)       AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
870 #define AscGetRiscVarFreeQHead(port)        AscReadLramByte((port), ASCV_NEXTRDY_B)
871 #define AscGetRiscVarDoneQTail(port)        AscReadLramByte((port), ASCV_DONENEXT_B)
872 #define AscPutRiscVarFreeQHead(port, val)   AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
873 #define AscPutRiscVarDoneQTail(port, val)   AscWriteLramByte((port), ASCV_DONENEXT_B, val)
874 #define AscPutMCodeSDTRDoneAtID(port, id, data)  AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
875 #define AscGetMCodeSDTRDoneAtID(port, id)        AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
876 #define AscPutMCodeInitSDTRAtID(port, id, data)  AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
877 #define AscGetMCodeInitSDTRAtID(port, id)        AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
878 #define AscGetChipSignatureByte(port)     (uchar)inp((port)+IOP_SIG_BYTE)
879 #define AscGetChipSignatureWord(port)     (ushort)inpw((port)+IOP_SIG_WORD)
880 #define AscGetChipVerNo(port)             (uchar)inp((port)+IOP_VERSION)
881 #define AscGetChipCfgLsw(port)            (ushort)inpw((port)+IOP_CONFIG_LOW)
882 #define AscGetChipCfgMsw(port)            (ushort)inpw((port)+IOP_CONFIG_HIGH)
883 #define AscSetChipCfgLsw(port, data)      outpw((port)+IOP_CONFIG_LOW, data)
884 #define AscSetChipCfgMsw(port, data)      outpw((port)+IOP_CONFIG_HIGH, data)
885 #define AscGetChipEEPCmd(port)            (uchar)inp((port)+IOP_EEP_CMD)
886 #define AscSetChipEEPCmd(port, data)      outp((port)+IOP_EEP_CMD, data)
887 #define AscGetChipEEPData(port)           (ushort)inpw((port)+IOP_EEP_DATA)
888 #define AscSetChipEEPData(port, data)     outpw((port)+IOP_EEP_DATA, data)
889 #define AscGetChipLramAddr(port)          (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
890 #define AscSetChipLramAddr(port, addr)    outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
891 #define AscGetChipLramData(port)          (ushort)inpw((port)+IOP_RAM_DATA)
892 #define AscSetChipLramData(port, data)    outpw((port)+IOP_RAM_DATA, data)
893 #define AscGetChipIFC(port)               (uchar)inp((port)+IOP_REG_IFC)
894 #define AscSetChipIFC(port, data)          outp((port)+IOP_REG_IFC, data)
895 #define AscGetChipStatus(port)            (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
896 #define AscSetChipStatus(port, cs_val)    outpw((port)+IOP_STATUS, cs_val)
897 #define AscGetChipControl(port)           (uchar)inp((port)+IOP_CTRL)
898 #define AscSetChipControl(port, cc_val)   outp((port)+IOP_CTRL, cc_val)
899 #define AscGetChipSyn(port)               (uchar)inp((port)+IOP_SYN_OFFSET)
900 #define AscSetChipSyn(port, data)         outp((port)+IOP_SYN_OFFSET, data)
901 #define AscSetPCAddr(port, data)          outpw((port)+IOP_REG_PC, data)
902 #define AscGetPCAddr(port)                (ushort)inpw((port)+IOP_REG_PC)
903 #define AscIsIntPending(port)             (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
904 #define AscGetChipScsiID(port)            ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
905 #define AscGetExtraControl(port)          (uchar)inp((port)+IOP_EXTRA_CONTROL)
906 #define AscSetExtraControl(port, data)    outp((port)+IOP_EXTRA_CONTROL, data)
907 #define AscReadChipAX(port)               (ushort)inpw((port)+IOP_REG_AX)
908 #define AscWriteChipAX(port, data)        outpw((port)+IOP_REG_AX, data)
909 #define AscReadChipIX(port)               (uchar)inp((port)+IOP_REG_IX)
910 #define AscWriteChipIX(port, data)        outp((port)+IOP_REG_IX, data)
911 #define AscReadChipIH(port)               (ushort)inpw((port)+IOP_REG_IH)
912 #define AscWriteChipIH(port, data)        outpw((port)+IOP_REG_IH, data)
913 #define AscReadChipQP(port)               (uchar)inp((port)+IOP_REG_QP)
914 #define AscWriteChipQP(port, data)        outp((port)+IOP_REG_QP, data)
915 #define AscReadChipFIFO_L(port)           (ushort)inpw((port)+IOP_REG_FIFO_L)
916 #define AscWriteChipFIFO_L(port, data)    outpw((port)+IOP_REG_FIFO_L, data)
917 #define AscReadChipFIFO_H(port)           (ushort)inpw((port)+IOP_REG_FIFO_H)
918 #define AscWriteChipFIFO_H(port, data)    outpw((port)+IOP_REG_FIFO_H, data)
919 #define AscReadChipDmaSpeed(port)         (uchar)inp((port)+IOP_DMA_SPEED)
920 #define AscWriteChipDmaSpeed(port, data)  outp((port)+IOP_DMA_SPEED, data)
921 #define AscReadChipDA0(port)              (ushort)inpw((port)+IOP_REG_DA0)
922 #define AscWriteChipDA0(port)             outpw((port)+IOP_REG_DA0, data)
923 #define AscReadChipDA1(port)              (ushort)inpw((port)+IOP_REG_DA1)
924 #define AscWriteChipDA1(port)             outpw((port)+IOP_REG_DA1, data)
925 #define AscReadChipDC0(port)              (ushort)inpw((port)+IOP_REG_DC0)
926 #define AscWriteChipDC0(port)             outpw((port)+IOP_REG_DC0, data)
927 #define AscReadChipDC1(port)              (ushort)inpw((port)+IOP_REG_DC1)
928 #define AscWriteChipDC1(port)             outpw((port)+IOP_REG_DC1, data)
929 #define AscReadChipDvcID(port)            (uchar)inp((port)+IOP_REG_ID)
930 #define AscWriteChipDvcID(port, data)     outp((port)+IOP_REG_ID, data)
931 
932 /*
933  * Portable Data Types
934  *
935  * Any instance where a 32-bit long or pointer type is assumed
936  * for precision or HW defined structures, the following define
937  * types must be used. In Linux the char, short, and int types
938  * are all consistent at 8, 16, and 32 bits respectively. Pointers
939  * and long types are 64 bits on Alpha and UltraSPARC.
940  */
941 #define ADV_PADDR __u32         /* Physical address data type. */
942 #define ADV_VADDR __u32         /* Virtual address data type. */
943 #define ADV_DCNT  __u32         /* Unsigned Data count type. */
944 #define ADV_SDCNT __s32         /* Signed Data count type. */
945 
946 /*
947  * These macros are used to convert a virtual address to a
948  * 32-bit value. This currently can be used on Linux Alpha
949  * which uses 64-bit virtual address but a 32-bit bus address.
950  * This is likely to break in the future, but doing this now
951  * will give us time to change the HW and FW to handle 64-bit
952  * addresses.
953  */
954 #define ADV_VADDR_TO_U32   virt_to_bus
955 #define ADV_U32_TO_VADDR   bus_to_virt
956 
957 #define AdvPortAddr  void __iomem *     /* Virtual memory address size */
958 
959 /*
960  * Define Adv Library required memory access macros.
961  */
962 #define ADV_MEM_READB(addr) readb(addr)
963 #define ADV_MEM_READW(addr) readw(addr)
964 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
965 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
966 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
967 
968 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
969 
970 /*
971  * Define total number of simultaneous maximum element scatter-gather
972  * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
973  * maximum number of outstanding commands per wide host adapter. Each
974  * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
975  * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
976  * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
977  * structures or 255 scatter-gather elements.
978  */
979 #define ADV_TOT_SG_BLOCK        ASC_DEF_MAX_HOST_QNG
980 
981 /*
982  * Define maximum number of scatter-gather elements per request.
983  */
984 #define ADV_MAX_SG_LIST         255
985 #define NO_OF_SG_PER_BLOCK              15
986 
987 #define ADV_EEP_DVC_CFG_BEGIN           (0x00)
988 #define ADV_EEP_DVC_CFG_END             (0x15)
989 #define ADV_EEP_DVC_CTL_BEGIN           (0x16)  /* location of OEM name */
990 #define ADV_EEP_MAX_WORD_ADDR           (0x1E)
991 
992 #define ADV_EEP_DELAY_MS                100
993 
994 #define ADV_EEPROM_BIG_ENDIAN          0x8000   /* EEPROM Bit 15 */
995 #define ADV_EEPROM_BIOS_ENABLE         0x4000   /* EEPROM Bit 14 */
996 /*
997  * For the ASC3550 Bit 13 is Termination Polarity control bit.
998  * For later ICs Bit 13 controls whether the CIS (Card Information
999  * Service Section) is loaded from EEPROM.
1000  */
1001 #define ADV_EEPROM_TERM_POL            0x2000   /* EEPROM Bit 13 */
1002 #define ADV_EEPROM_CIS_LD              0x2000   /* EEPROM Bit 13 */
1003 /*
1004  * ASC38C1600 Bit 11
1005  *
1006  * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
1007  * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
1008  * Function 0 will specify INT B.
1009  *
1010  * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
1011  * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
1012  * Function 1 will specify INT A.
1013  */
1014 #define ADV_EEPROM_INTAB               0x0800   /* EEPROM Bit 11 */
1015 
1016 typedef struct adveep_3550_config {
1017         /* Word Offset, Description */
1018 
1019         ushort cfg_lsw;         /* 00 power up initialization */
1020         /*  bit 13 set - Term Polarity Control */
1021         /*  bit 14 set - BIOS Enable */
1022         /*  bit 15 set - Big Endian Mode */
1023         ushort cfg_msw;         /* 01 unused      */
1024         ushort disc_enable;     /* 02 disconnect enable */
1025         ushort wdtr_able;       /* 03 Wide DTR able */
1026         ushort sdtr_able;       /* 04 Synchronous DTR able */
1027         ushort start_motor;     /* 05 send start up motor */
1028         ushort tagqng_able;     /* 06 tag queuing able */
1029         ushort bios_scan;       /* 07 BIOS device control */
1030         ushort scam_tolerant;   /* 08 no scam */
1031 
1032         uchar adapter_scsi_id;  /* 09 Host Adapter ID */
1033         uchar bios_boot_delay;  /*    power up wait */
1034 
1035         uchar scsi_reset_delay; /* 10 reset delay */
1036         uchar bios_id_lun;      /*    first boot device scsi id & lun */
1037         /*    high nibble is lun */
1038         /*    low nibble is scsi id */
1039 
1040         uchar termination;      /* 11 0 - automatic */
1041         /*    1 - low off / high off */
1042         /*    2 - low off / high on */
1043         /*    3 - low on  / high on */
1044         /*    There is no low on  / high off */
1045 
1046         uchar reserved1;        /*    reserved byte (not used) */
1047 
1048         ushort bios_ctrl;       /* 12 BIOS control bits */
1049         /*  bit 0  BIOS don't act as initiator. */
1050         /*  bit 1  BIOS > 1 GB support */
1051         /*  bit 2  BIOS > 2 Disk Support */
1052         /*  bit 3  BIOS don't support removables */
1053         /*  bit 4  BIOS support bootable CD */
1054         /*  bit 5  BIOS scan enabled */
1055         /*  bit 6  BIOS support multiple LUNs */
1056         /*  bit 7  BIOS display of message */
1057         /*  bit 8  SCAM disabled */
1058         /*  bit 9  Reset SCSI bus during init. */
1059         /*  bit 10 */
1060         /*  bit 11 No verbose initialization. */
1061         /*  bit 12 SCSI parity enabled */
1062         /*  bit 13 */
1063         /*  bit 14 */
1064         /*  bit 15 */
1065         ushort ultra_able;      /* 13 ULTRA speed able */
1066         ushort reserved2;       /* 14 reserved */
1067         uchar max_host_qng;     /* 15 maximum host queuing */
1068         uchar max_dvc_qng;      /*    maximum per device queuing */
1069         ushort dvc_cntl;        /* 16 control bit for driver */
1070         ushort bug_fix;         /* 17 control bit for bug fix */
1071         ushort serial_number_word1;     /* 18 Board serial number word 1 */
1072         ushort serial_number_word2;     /* 19 Board serial number word 2 */
1073         ushort serial_number_word3;     /* 20 Board serial number word 3 */
1074         ushort check_sum;       /* 21 EEP check sum */
1075         uchar oem_name[16];     /* 22 OEM name */
1076         ushort dvc_err_code;    /* 30 last device driver error code */
1077         ushort adv_err_code;    /* 31 last uc and Adv Lib error code */
1078         ushort adv_err_addr;    /* 32 last uc error address */
1079         ushort saved_dvc_err_code;      /* 33 saved last dev. driver error code   */
1080         ushort saved_adv_err_code;      /* 34 saved last uc and Adv Lib error code */
1081         ushort saved_adv_err_addr;      /* 35 saved last uc error address         */
1082         ushort num_of_err;      /* 36 number of error */
1083 } ADVEEP_3550_CONFIG;
1084 
1085 typedef struct adveep_38C0800_config {
1086         /* Word Offset, Description */
1087 
1088         ushort cfg_lsw;         /* 00 power up initialization */
1089         /*  bit 13 set - Load CIS */
1090         /*  bit 14 set - BIOS Enable */
1091         /*  bit 15 set - Big Endian Mode */
1092         ushort cfg_msw;         /* 01 unused      */
1093         ushort disc_enable;     /* 02 disconnect enable */
1094         ushort wdtr_able;       /* 03 Wide DTR able */
1095         ushort sdtr_speed1;     /* 04 SDTR Speed TID 0-3 */
1096         ushort start_motor;     /* 05 send start up motor */
1097         ushort tagqng_able;     /* 06 tag queuing able */
1098         ushort bios_scan;       /* 07 BIOS device control */
1099         ushort scam_tolerant;   /* 08 no scam */
1100 
1101         uchar adapter_scsi_id;  /* 09 Host Adapter ID */
1102         uchar bios_boot_delay;  /*    power up wait */
1103 
1104         uchar scsi_reset_delay; /* 10 reset delay */
1105         uchar bios_id_lun;      /*    first boot device scsi id & lun */
1106         /*    high nibble is lun */
1107         /*    low nibble is scsi id */
1108 
1109         uchar termination_se;   /* 11 0 - automatic */
1110         /*    1 - low off / high off */
1111         /*    2 - low off / high on */
1112         /*    3 - low on  / high on */
1113         /*    There is no low on  / high off */
1114 
1115         uchar termination_lvd;  /* 11 0 - automatic */
1116         /*    1 - low off / high off */
1117         /*    2 - low off / high on */
1118         /*    3 - low on  / high on */
1119         /*    There is no low on  / high off */
1120 
1121         ushort bios_ctrl;       /* 12 BIOS control bits */
1122         /*  bit 0  BIOS don't act as initiator. */
1123         /*  bit 1  BIOS > 1 GB support */
1124         /*  bit 2  BIOS > 2 Disk Support */
1125         /*  bit 3  BIOS don't support removables */
1126         /*  bit 4  BIOS support bootable CD */
1127         /*  bit 5  BIOS scan enabled */
1128         /*  bit 6  BIOS support multiple LUNs */
1129         /*  bit 7  BIOS display of message */
1130         /*  bit 8  SCAM disabled */
1131         /*  bit 9  Reset SCSI bus during init. */
1132         /*  bit 10 */
1133         /*  bit 11 No verbose initialization. */
1134         /*  bit 12 SCSI parity enabled */
1135         /*  bit 13 */
1136         /*  bit 14 */
1137         /*  bit 15 */
1138         ushort sdtr_speed2;     /* 13 SDTR speed TID 4-7 */
1139         ushort sdtr_speed3;     /* 14 SDTR speed TID 8-11 */
1140         uchar max_host_qng;     /* 15 maximum host queueing */
1141         uchar max_dvc_qng;      /*    maximum per device queuing */
1142         ushort dvc_cntl;        /* 16 control bit for driver */
1143         ushort sdtr_speed4;     /* 17 SDTR speed 4 TID 12-15 */
1144         ushort serial_number_word1;     /* 18 Board serial number word 1 */
1145         ushort serial_number_word2;     /* 19 Board serial number word 2 */
1146         ushort serial_number_word3;     /* 20 Board serial number word 3 */
1147         ushort check_sum;       /* 21 EEP check sum */
1148         uchar oem_name[16];     /* 22 OEM name */
1149         ushort dvc_err_code;    /* 30 last device driver error code */
1150         ushort adv_err_code;    /* 31 last uc and Adv Lib error code */
1151         ushort adv_err_addr;    /* 32 last uc error address */
1152         ushort saved_dvc_err_code;      /* 33 saved last dev. driver error code   */
1153         ushort saved_adv_err_code;      /* 34 saved last uc and Adv Lib error code */
1154         ushort saved_adv_err_addr;      /* 35 saved last uc error address         */
1155         ushort reserved36;      /* 36 reserved */
1156         ushort reserved37;      /* 37 reserved */
1157         ushort reserved38;      /* 38 reserved */
1158         ushort reserved39;      /* 39 reserved */
1159         ushort reserved40;      /* 40 reserved */
1160         ushort reserved41;      /* 41 reserved */
1161         ushort reserved42;      /* 42 reserved */
1162         ushort reserved43;      /* 43 reserved */
1163         ushort reserved44;      /* 44 reserved */
1164         ushort reserved45;      /* 45 reserved */
1165         ushort reserved46;      /* 46 reserved */
1166         ushort reserved47;      /* 47 reserved */
1167         ushort reserved48;      /* 48 reserved */
1168         ushort reserved49;      /* 49 reserved */
1169         ushort reserved50;      /* 50 reserved */
1170         ushort reserved51;      /* 51 reserved */
1171         ushort reserved52;      /* 52 reserved */
1172         ushort reserved53;      /* 53 reserved */
1173         ushort reserved54;      /* 54 reserved */
1174         ushort reserved55;      /* 55 reserved */
1175         ushort cisptr_lsw;      /* 56 CIS PTR LSW */
1176         ushort cisprt_msw;      /* 57 CIS PTR MSW */
1177         ushort subsysvid;       /* 58 SubSystem Vendor ID */
1178         ushort subsysid;        /* 59 SubSystem ID */
1179         ushort reserved60;      /* 60 reserved */
1180         ushort reserved61;      /* 61 reserved */
1181         ushort reserved62;      /* 62 reserved */
1182         ushort reserved63;      /* 63 reserved */
1183 } ADVEEP_38C0800_CONFIG;
1184 
1185 typedef struct adveep_38C1600_config {
1186         /* Word Offset, Description */
1187 
1188         ushort cfg_lsw;         /* 00 power up initialization */
1189         /*  bit 11 set - Func. 0 INTB, Func. 1 INTA */
1190         /*       clear - Func. 0 INTA, Func. 1 INTB */
1191         /*  bit 13 set - Load CIS */
1192         /*  bit 14 set - BIOS Enable */
1193         /*  bit 15 set - Big Endian Mode */
1194         ushort cfg_msw;         /* 01 unused */
1195         ushort disc_enable;     /* 02 disconnect enable */
1196         ushort wdtr_able;       /* 03 Wide DTR able */
1197         ushort sdtr_speed1;     /* 04 SDTR Speed TID 0-3 */
1198         ushort start_motor;     /* 05 send start up motor */
1199         ushort tagqng_able;     /* 06 tag queuing able */
1200         ushort bios_scan;       /* 07 BIOS device control */
1201         ushort scam_tolerant;   /* 08 no scam */
1202 
1203         uchar adapter_scsi_id;  /* 09 Host Adapter ID */
1204         uchar bios_boot_delay;  /*    power up wait */
1205 
1206         uchar scsi_reset_delay; /* 10 reset delay */
1207         uchar bios_id_lun;      /*    first boot device scsi id & lun */
1208         /*    high nibble is lun */
1209         /*    low nibble is scsi id */
1210 
1211         uchar termination_se;   /* 11 0 - automatic */
1212         /*    1 - low off / high off */
1213         /*    2 - low off / high on */
1214         /*    3 - low on  / high on */
1215         /*    There is no low on  / high off */
1216 
1217         uchar termination_lvd;  /* 11 0 - automatic */
1218         /*    1 - low off / high off */
1219         /*    2 - low off / high on */
1220         /*    3 - low on  / high on */
1221         /*    There is no low on  / high off */
1222 
1223         ushort bios_ctrl;       /* 12 BIOS control bits */
1224         /*  bit 0  BIOS don't act as initiator. */
1225         /*  bit 1  BIOS > 1 GB support */
1226         /*  bit 2  BIOS > 2 Disk Support */
1227         /*  bit 3  BIOS don't support removables */
1228         /*  bit 4  BIOS support bootable CD */
1229         /*  bit 5  BIOS scan enabled */
1230         /*  bit 6  BIOS support multiple LUNs */
1231         /*  bit 7  BIOS display of message */
1232         /*  bit 8  SCAM disabled */
1233         /*  bit 9  Reset SCSI bus during init. */
1234         /*  bit 10 Basic Integrity Checking disabled */
1235         /*  bit 11 No verbose initialization. */
1236         /*  bit 12 SCSI parity enabled */
1237         /*  bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1238         /*  bit 14 */
1239         /*  bit 15 */
1240         ushort sdtr_speed2;     /* 13 SDTR speed TID 4-7 */
1241         ushort sdtr_speed3;     /* 14 SDTR speed TID 8-11 */
1242         uchar max_host_qng;     /* 15 maximum host queueing */
1243         uchar max_dvc_qng;      /*    maximum per device queuing */
1244         ushort dvc_cntl;        /* 16 control bit for driver */
1245         ushort sdtr_speed4;     /* 17 SDTR speed 4 TID 12-15 */
1246         ushort serial_number_word1;     /* 18 Board serial number word 1 */
1247         ushort serial_number_word2;     /* 19 Board serial number word 2 */
1248         ushort serial_number_word3;     /* 20 Board serial number word 3 */
1249         ushort check_sum;       /* 21 EEP check sum */
1250         uchar oem_name[16];     /* 22 OEM name */
1251         ushort dvc_err_code;    /* 30 last device driver error code */
1252         ushort adv_err_code;    /* 31 last uc and Adv Lib error code */
1253         ushort adv_err_addr;    /* 32 last uc error address */
1254         ushort saved_dvc_err_code;      /* 33 saved last dev. driver error code   */
1255         ushort saved_adv_err_code;      /* 34 saved last uc and Adv Lib error code */
1256         ushort saved_adv_err_addr;      /* 35 saved last uc error address         */
1257         ushort reserved36;      /* 36 reserved */
1258         ushort reserved37;      /* 37 reserved */
1259         ushort reserved38;      /* 38 reserved */
1260         ushort reserved39;      /* 39 reserved */
1261         ushort reserved40;      /* 40 reserved */
1262         ushort reserved41;      /* 41 reserved */
1263         ushort reserved42;      /* 42 reserved */
1264         ushort reserved43;      /* 43 reserved */
1265         ushort reserved44;      /* 44 reserved */
1266         ushort reserved45;      /* 45 reserved */
1267         ushort reserved46;      /* 46 reserved */
1268         ushort reserved47;      /* 47 reserved */
1269         ushort reserved48;      /* 48 reserved */
1270         ushort reserved49;      /* 49 reserved */
1271         ushort reserved50;      /* 50 reserved */
1272         ushort reserved51;      /* 51 reserved */
1273         ushort reserved52;      /* 52 reserved */
1274         ushort reserved53;      /* 53 reserved */
1275         ushort reserved54;      /* 54 reserved */
1276         ushort reserved55;      /* 55 reserved */
1277         ushort cisptr_lsw;      /* 56 CIS PTR LSW */
1278         ushort cisprt_msw;      /* 57 CIS PTR MSW */
1279         ushort subsysvid;       /* 58 SubSystem Vendor ID */
1280         ushort subsysid;        /* 59 SubSystem ID */
1281         ushort reserved60;      /* 60 reserved */
1282         ushort reserved61;      /* 61 reserved */
1283         ushort reserved62;      /* 62 reserved */
1284         ushort reserved63;      /* 63 reserved */
1285 } ADVEEP_38C1600_CONFIG;
1286 
1287 /*
1288  * EEPROM Commands
1289  */
1290 #define ASC_EEP_CMD_DONE             0x0200
1291 
1292 /* bios_ctrl */
1293 #define BIOS_CTRL_BIOS               0x0001
1294 #define BIOS_CTRL_EXTENDED_XLAT      0x0002
1295 #define BIOS_CTRL_GT_2_DISK          0x0004
1296 #define BIOS_CTRL_BIOS_REMOVABLE     0x0008
1297 #define BIOS_CTRL_BOOTABLE_CD        0x0010
1298 #define BIOS_CTRL_MULTIPLE_LUN       0x0040
1299 #define BIOS_CTRL_DISPLAY_MSG        0x0080
1300 #define BIOS_CTRL_NO_SCAM            0x0100
1301 #define BIOS_CTRL_RESET_SCSI_BUS     0x0200
1302 #define BIOS_CTRL_INIT_VERBOSE       0x0800
1303 #define BIOS_CTRL_SCSI_PARITY        0x1000
1304 #define BIOS_CTRL_AIPP_DIS           0x2000
1305 
1306 #define ADV_3550_MEMSIZE   0x2000       /* 8 KB Internal Memory */
1307 
1308 #define ADV_38C0800_MEMSIZE  0x4000     /* 16 KB Internal Memory */
1309 
1310 /*
1311  * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1312  * a special 16K Adv Library and Microcode version. After the issue is
1313  * resolved, should restore 32K support.
1314  *
1315  * #define ADV_38C1600_MEMSIZE  0x8000L   * 32 KB Internal Memory *
1316  */
1317 #define ADV_38C1600_MEMSIZE  0x4000     /* 16 KB Internal Memory */
1318 
1319 /*
1320  * Byte I/O register address from base of 'iop_base'.
1321  */
1322 #define IOPB_INTR_STATUS_REG    0x00
1323 #define IOPB_CHIP_ID_1          0x01
1324 #define IOPB_INTR_ENABLES       0x02
1325 #define IOPB_CHIP_TYPE_REV      0x03
1326 #define IOPB_RES_ADDR_4         0x04
1327 #define IOPB_RES_ADDR_5         0x05
1328 #define IOPB_RAM_DATA           0x06
1329 #define IOPB_RES_ADDR_7         0x07
1330 #define IOPB_FLAG_REG           0x08
1331 #define IOPB_RES_ADDR_9         0x09
1332 #define IOPB_RISC_CSR           0x0A
1333 #define IOPB_RES_ADDR_B         0x0B
1334 #define IOPB_RES_ADDR_C         0x0C
1335 #define IOPB_RES_ADDR_D         0x0D
1336 #define IOPB_SOFT_OVER_WR       0x0E
1337 #define IOPB_RES_ADDR_F         0x0F
1338 #define IOPB_MEM_CFG            0x10
1339 #define IOPB_RES_ADDR_11        0x11
1340 #define IOPB_GPIO_DATA          0x12
1341 #define IOPB_RES_ADDR_13        0x13
1342 #define IOPB_FLASH_PAGE         0x14
1343 #define IOPB_RES_ADDR_15        0x15
1344 #define IOPB_GPIO_CNTL          0x16
1345 #define IOPB_RES_ADDR_17        0x17
1346 #define IOPB_FLASH_DATA         0x18
1347 #define IOPB_RES_ADDR_19        0x19
1348 #define IOPB_RES_ADDR_1A        0x1A
1349 #define IOPB_RES_ADDR_1B        0x1B
1350 #define IOPB_RES_ADDR_1C        0x1C
1351 #define IOPB_RES_ADDR_1D        0x1D
1352 #define IOPB_RES_ADDR_1E        0x1E
1353 #define IOPB_RES_ADDR_1F        0x1F
1354 #define IOPB_DMA_CFG0           0x20
1355 #define IOPB_DMA_CFG1           0x21
1356 #define IOPB_TICKLE             0x22
1357 #define IOPB_DMA_REG_WR         0x23
1358 #define IOPB_SDMA_STATUS        0x24
1359 #define IOPB_SCSI_BYTE_CNT      0x25
1360 #define IOPB_HOST_BYTE_CNT      0x26
1361 #define IOPB_BYTE_LEFT_TO_XFER  0x27
1362 #define IOPB_BYTE_TO_XFER_0     0x28
1363 #define IOPB_BYTE_TO_XFER_1     0x29
1364 #define IOPB_BYTE_TO_XFER_2     0x2A
1365 #define IOPB_BYTE_TO_XFER_3     0x2B
1366 #define IOPB_ACC_GRP            0x2C
1367 #define IOPB_RES_ADDR_2D        0x2D
1368 #define IOPB_DEV_ID             0x2E
1369 #define IOPB_RES_ADDR_2F        0x2F
1370 #define IOPB_SCSI_DATA          0x30
1371 #define IOPB_RES_ADDR_31        0x31
1372 #define IOPB_RES_ADDR_32        0x32
1373 #define IOPB_SCSI_DATA_HSHK     0x33
1374 #define IOPB_SCSI_CTRL          0x34
1375 #define IOPB_RES_ADDR_35        0x35
1376 #define IOPB_RES_ADDR_36        0x36
1377 #define IOPB_RES_ADDR_37        0x37
1378 #define IOPB_RAM_BIST           0x38
1379 #define IOPB_PLL_TEST           0x39
1380 #define IOPB_PCI_INT_CFG        0x3A
1381 #define IOPB_RES_ADDR_3B        0x3B
1382 #define IOPB_RFIFO_CNT          0x3C
1383 #define IOPB_RES_ADDR_3D        0x3D
1384 #define IOPB_RES_ADDR_3E        0x3E
1385 #define IOPB_RES_ADDR_3F        0x3F
1386 
1387 /*
1388  * Word I/O register address from base of 'iop_base'.
1389  */
1390 #define IOPW_CHIP_ID_0          0x00    /* CID0  */
1391 #define IOPW_CTRL_REG           0x02    /* CC    */
1392 #define IOPW_RAM_ADDR           0x04    /* LA    */
1393 #define IOPW_RAM_DATA           0x06    /* LD    */
1394 #define IOPW_RES_ADDR_08        0x08
1395 #define IOPW_RISC_CSR           0x0A    /* CSR   */
1396 #define IOPW_SCSI_CFG0          0x0C    /* CFG0  */
1397 #define IOPW_SCSI_CFG1          0x0E    /* CFG1  */
1398 #define IOPW_RES_ADDR_10        0x10
1399 #define IOPW_SEL_MASK           0x12    /* SM    */
1400 #define IOPW_RES_ADDR_14        0x14
1401 #define IOPW_FLASH_ADDR         0x16    /* FA    */
1402 #define IOPW_RES_ADDR_18        0x18
1403 #define IOPW_EE_CMD             0x1A    /* EC    */
1404 #define IOPW_EE_DATA            0x1C    /* ED    */
1405 #define IOPW_SFIFO_CNT          0x1E    /* SFC   */
1406 #define IOPW_RES_ADDR_20        0x20
1407 #define IOPW_Q_BASE             0x22    /* QB    */
1408 #define IOPW_QP                 0x24    /* QP    */
1409 #define IOPW_IX                 0x26    /* IX    */
1410 #define IOPW_SP                 0x28    /* SP    */
1411 #define IOPW_PC                 0x2A    /* PC    */
1412 #define IOPW_RES_ADDR_2C        0x2C
1413 #define IOPW_RES_ADDR_2E        0x2E
1414 #define IOPW_SCSI_DATA          0x30    /* SD    */
1415 #define IOPW_SCSI_DATA_HSHK     0x32    /* SDH   */
1416 #define IOPW_SCSI_CTRL          0x34    /* SC    */
1417 #define IOPW_HSHK_CFG           0x36    /* HCFG  */
1418 #define IOPW_SXFR_STATUS        0x36    /* SXS   */
1419 #define IOPW_SXFR_CNTL          0x38    /* SXL   */
1420 #define IOPW_SXFR_CNTH          0x3A    /* SXH   */
1421 #define IOPW_RES_ADDR_3C        0x3C
1422 #define IOPW_RFIFO_DATA         0x3E    /* RFD   */
1423 
1424 /*
1425  * Doubleword I/O register address from base of 'iop_base'.
1426  */
1427 #define IOPDW_RES_ADDR_0         0x00
1428 #define IOPDW_RAM_DATA           0x04
1429 #define IOPDW_RES_ADDR_8         0x08
1430 #define IOPDW_RES_ADDR_C         0x0C
1431 #define IOPDW_RES_ADDR_10        0x10
1432 #define IOPDW_COMMA              0x14
1433 #define IOPDW_COMMB              0x18
1434 #define IOPDW_RES_ADDR_1C        0x1C
1435 #define IOPDW_SDMA_ADDR0         0x20
1436 #define IOPDW_SDMA_ADDR1         0x24
1437 #define IOPDW_SDMA_COUNT         0x28
1438 #define IOPDW_SDMA_ERROR         0x2C
1439 #define IOPDW_RDMA_ADDR0         0x30
1440 #define IOPDW_RDMA_ADDR1         0x34
1441 #define IOPDW_RDMA_COUNT         0x38
1442 #define IOPDW_RDMA_ERROR         0x3C
1443 
1444 #define ADV_CHIP_ID_BYTE         0x25
1445 #define ADV_CHIP_ID_WORD         0x04C1
1446 
1447 #define ADV_INTR_ENABLE_HOST_INTR                   0x01
1448 #define ADV_INTR_ENABLE_SEL_INTR                    0x02
1449 #define ADV_INTR_ENABLE_DPR_INTR                    0x04
1450 #define ADV_INTR_ENABLE_RTA_INTR                    0x08
1451 #define ADV_INTR_ENABLE_RMA_INTR                    0x10
1452 #define ADV_INTR_ENABLE_RST_INTR                    0x20
1453 #define ADV_INTR_ENABLE_DPE_INTR                    0x40
1454 #define ADV_INTR_ENABLE_GLOBAL_INTR                 0x80
1455 
1456 #define ADV_INTR_STATUS_INTRA            0x01
1457 #define ADV_INTR_STATUS_INTRB            0x02
1458 #define ADV_INTR_STATUS_INTRC            0x04
1459 
1460 #define ADV_RISC_CSR_STOP           (0x0000)
1461 #define ADV_RISC_TEST_COND          (0x2000)
1462 #define ADV_RISC_CSR_RUN            (0x4000)
1463 #define ADV_RISC_CSR_SINGLE_STEP    (0x8000)
1464 
1465 #define ADV_CTRL_REG_HOST_INTR      0x0100
1466 #define ADV_CTRL_REG_SEL_INTR       0x0200
1467 #define ADV_CTRL_REG_DPR_INTR       0x0400
1468 #define ADV_CTRL_REG_RTA_INTR       0x0800
1469 #define ADV_CTRL_REG_RMA_INTR       0x1000
1470 #define ADV_CTRL_REG_RES_BIT14      0x2000
1471 #define ADV_CTRL_REG_DPE_INTR       0x4000
1472 #define ADV_CTRL_REG_POWER_DONE     0x8000
1473 #define ADV_CTRL_REG_ANY_INTR       0xFF00
1474 
1475 #define ADV_CTRL_REG_CMD_RESET             0x00C6
1476 #define ADV_CTRL_REG_CMD_WR_IO_REG         0x00C5
1477 #define ADV_CTRL_REG_CMD_RD_IO_REG         0x00C4
1478 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE  0x00C3
1479 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE  0x00C2
1480 
1481 #define ADV_TICKLE_NOP                      0x00
1482 #define ADV_TICKLE_A                        0x01
1483 #define ADV_TICKLE_B                        0x02
1484 #define ADV_TICKLE_C                        0x03
1485 
1486 #define AdvIsIntPending(port) \
1487     (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1488 
1489 /*
1490  * SCSI_CFG0 Register bit definitions
1491  */
1492 #define TIMER_MODEAB    0xC000  /* Watchdog, Second, and Select. Timer Ctrl. */
1493 #define PARITY_EN       0x2000  /* Enable SCSI Parity Error detection */
1494 #define EVEN_PARITY     0x1000  /* Select Even Parity */
1495 #define WD_LONG         0x0800  /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1496 #define QUEUE_128       0x0400  /* Queue Size, 1: 128 byte, 0: 64 byte */
1497 #define PRIM_MODE       0x0100  /* Primitive SCSI mode */
1498 #define SCAM_EN         0x0080  /* Enable SCAM selection */
1499 #define SEL_TMO_LONG    0x0040  /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1500 #define CFRM_ID         0x0020  /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1501 #define OUR_ID_EN       0x0010  /* Enable OUR_ID bits */
1502 #define OUR_ID          0x000F  /* SCSI ID */
1503 
1504 /*
1505  * SCSI_CFG1 Register bit definitions
1506  */
1507 #define BIG_ENDIAN      0x8000  /* Enable Big Endian Mode MIO:15, EEP:15 */
1508 #define TERM_POL        0x2000  /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1509 #define SLEW_RATE       0x1000  /* SCSI output buffer slew rate */
1510 #define FILTER_SEL      0x0C00  /* Filter Period Selection */
1511 #define  FLTR_DISABLE    0x0000 /* Input Filtering Disabled */
1512 #define  FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1513 #define  FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1514 #define ACTIVE_DBL      0x0200  /* Disable Active Negation */
1515 #define DIFF_MODE       0x0100  /* SCSI differential Mode (Read-Only) */
1516 #define DIFF_SENSE      0x0080  /* 1: No SE cables, 0: SE cable (Read-Only) */
1517 #define TERM_CTL_SEL    0x0040  /* Enable TERM_CTL_H and TERM_CTL_L */
1518 #define TERM_CTL        0x0030  /* External SCSI Termination Bits */
1519 #define  TERM_CTL_H      0x0020 /* Enable External SCSI Upper Termination */
1520 #define  TERM_CTL_L      0x0010 /* Enable External SCSI Lower Termination */
1521 #define CABLE_DETECT    0x000F  /* External SCSI Cable Connection Status */
1522 
1523 /*
1524  * Addendum for ASC-38C0800 Chip
1525  *
1526  * The ASC-38C1600 Chip uses the same definitions except that the
1527  * bus mode override bits [12:10] have been moved to byte register
1528  * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1529  * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1530  * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1531  * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1532  * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1533  */
1534 #define DIS_TERM_DRV    0x4000  /* 1: Read c_det[3:0], 0: cannot read */
1535 #define HVD_LVD_SE      0x1C00  /* Device Detect Bits */
1536 #define  HVD             0x1000 /* HVD Device Detect */
1537 #define  LVD             0x0800 /* LVD Device Detect */
1538 #define  SE              0x0400 /* SE Device Detect */
1539 #define TERM_LVD        0x00C0  /* LVD Termination Bits */
1540 #define  TERM_LVD_HI     0x0080 /* Enable LVD Upper Termination */
1541 #define  TERM_LVD_LO     0x0040 /* Enable LVD Lower Termination */
1542 #define TERM_SE         0x0030  /* SE Termination Bits */
1543 #define  TERM_SE_HI      0x0020 /* Enable SE Upper Termination */
1544 #define  TERM_SE_LO      0x0010 /* Enable SE Lower Termination */
1545 #define C_DET_LVD       0x000C  /* LVD Cable Detect Bits */
1546 #define  C_DET3          0x0008 /* Cable Detect for LVD External Wide */
1547 #define  C_DET2          0x0004 /* Cable Detect for LVD Internal Wide */
1548 #define C_DET_SE        0x0003  /* SE Cable Detect Bits */
1549 #define  C_DET1          0x0002 /* Cable Detect for SE Internal Wide */
1550 #define  C_DET0          0x0001 /* Cable Detect for SE Internal Narrow */
1551 
1552 #define CABLE_ILLEGAL_A 0x7
1553     /* x 0 0 0  | on  on | Illegal (all 3 connectors are used) */
1554 
1555 #define CABLE_ILLEGAL_B 0xB
1556     /* 0 x 0 0  | on  on | Illegal (all 3 connectors are used) */
1557 
1558 /*
1559  * MEM_CFG Register bit definitions
1560  */
1561 #define BIOS_EN         0x40    /* BIOS Enable MIO:14,EEP:14 */
1562 #define FAST_EE_CLK     0x20    /* Diagnostic Bit */
1563 #define RAM_SZ          0x1C    /* Specify size of RAM to RISC */
1564 #define  RAM_SZ_2KB      0x00   /* 2 KB */
1565 #define  RAM_SZ_4KB      0x04   /* 4 KB */
1566 #define  RAM_SZ_8KB      0x08   /* 8 KB */
1567 #define  RAM_SZ_16KB     0x0C   /* 16 KB */
1568 #define  RAM_SZ_32KB     0x10   /* 32 KB */
1569 #define  RAM_SZ_64KB     0x14   /* 64 KB */
1570 
1571 /*
1572  * DMA_CFG0 Register bit definitions
1573  *
1574  * This register is only accessible to the host.
1575  */
1576 #define BC_THRESH_ENB   0x80    /* PCI DMA Start Conditions */
1577 #define FIFO_THRESH     0x70    /* PCI DMA FIFO Threshold */
1578 #define  FIFO_THRESH_16B  0x00  /* 16 bytes */
1579 #define  FIFO_THRESH_32B  0x20  /* 32 bytes */
1580 #define  FIFO_THRESH_48B  0x30  /* 48 bytes */
1581 #define  FIFO_THRESH_64B  0x40  /* 64 bytes */
1582 #define  FIFO_THRESH_80B  0x50  /* 80 bytes (default) */
1583 #define  FIFO_THRESH_96B  0x60  /* 96 bytes */
1584 #define  FIFO_THRESH_112B 0x70  /* 112 bytes */
1585 #define START_CTL       0x0C    /* DMA start conditions */
1586 #define  START_CTL_TH    0x00   /* Wait threshold level (default) */
1587 #define  START_CTL_ID    0x04   /* Wait SDMA/SBUS idle */
1588 #define  START_CTL_THID  0x08   /* Wait threshold and SDMA/SBUS idle */
1589 #define  START_CTL_EMFU  0x0C   /* Wait SDMA FIFO empty/full */
1590 #define READ_CMD        0x03    /* Memory Read Method */
1591 #define  READ_CMD_MR     0x00   /* Memory Read */
1592 #define  READ_CMD_MRL    0x02   /* Memory Read Long */
1593 #define  READ_CMD_MRM    0x03   /* Memory Read Multiple (default) */
1594 
1595 /*
1596  * ASC-38C0800 RAM BIST Register bit definitions
1597  */
1598 #define RAM_TEST_MODE         0x80
1599 #define PRE_TEST_MODE         0x40
1600 #define NORMAL_MODE           0x00
1601 #define RAM_TEST_DONE         0x10
1602 #define RAM_TEST_STATUS       0x0F
1603 #define  RAM_TEST_HOST_ERROR   0x08
1604 #define  RAM_TEST_INTRAM_ERROR 0x04
1605 #define  RAM_TEST_RISC_ERROR   0x02
1606 #define  RAM_TEST_SCSI_ERROR   0x01
1607 #define  RAM_TEST_SUCCESS      0x00
1608 #define PRE_TEST_VALUE        0x05
1609 #define NORMAL_VALUE          0x00
1610 
1611 /*
1612  * ASC38C1600 Definitions
1613  *
1614  * IOPB_PCI_INT_CFG Bit Field Definitions
1615  */
1616 
1617 #define INTAB_LD        0x80    /* Value loaded from EEPROM Bit 11. */
1618 
1619 /*
1620  * Bit 1 can be set to change the interrupt for the Function to operate in
1621  * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1622  * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1623  * mode, otherwise the operating mode is undefined.
1624  */
1625 #define TOTEMPOLE       0x02
1626 
1627 /*
1628  * Bit 0 can be used to change the Int Pin for the Function. The value is
1629  * 0 by default for both Functions with Function 0 using INT A and Function
1630  * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1631  * INT A is used.
1632  *
1633  * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1634  * value specified in the PCI Configuration Space.
1635  */
1636 #define INTAB           0x01
1637 
1638 /*
1639  * Adv Library Status Definitions
1640  */
1641 #define ADV_TRUE        1
1642 #define ADV_FALSE       0
1643 #define ADV_SUCCESS     1
1644 #define ADV_BUSY        0
1645 #define ADV_ERROR       (-1)
1646 
1647 /*
1648  * ADV_DVC_VAR 'warn_code' values
1649  */
1650 #define ASC_WARN_BUSRESET_ERROR         0x0001  /* SCSI Bus Reset error */
1651 #define ASC_WARN_EEPROM_CHKSUM          0x0002  /* EEP check sum error */
1652 #define ASC_WARN_EEPROM_TERMINATION     0x0004  /* EEP termination bad field */
1653 #define ASC_WARN_ERROR                  0xFFFF  /* ADV_ERROR return */
1654 
1655 #define ADV_MAX_TID                     15      /* max. target identifier */
1656 #define ADV_MAX_LUN                     7       /* max. logical unit number */
1657 
1658 /*
1659  * Fixed locations of microcode operating variables.
1660  */
1661 #define ASC_MC_CODE_BEGIN_ADDR          0x0028  /* microcode start address */
1662 #define ASC_MC_CODE_END_ADDR            0x002A  /* microcode end address */
1663 #define ASC_MC_CODE_CHK_SUM             0x002C  /* microcode code checksum */
1664 #define ASC_MC_VERSION_DATE             0x0038  /* microcode version */
1665 #define ASC_MC_VERSION_NUM              0x003A  /* microcode number */
1666 #define ASC_MC_BIOSMEM                  0x0040  /* BIOS RISC Memory Start */
1667 #define ASC_MC_BIOSLEN                  0x0050  /* BIOS RISC Memory Length */
1668 #define ASC_MC_BIOS_SIGNATURE           0x0058  /* BIOS Signature 0x55AA */
1669 #define ASC_MC_BIOS_VERSION             0x005A  /* BIOS Version (2 bytes) */
1670 #define ASC_MC_SDTR_SPEED1              0x0090  /* SDTR Speed for TID 0-3 */
1671 #define ASC_MC_SDTR_SPEED2              0x0092  /* SDTR Speed for TID 4-7 */
1672 #define ASC_MC_SDTR_SPEED3              0x0094  /* SDTR Speed for TID 8-11 */
1673 #define ASC_MC_SDTR_SPEED4              0x0096  /* SDTR Speed for TID 12-15 */
1674 #define ASC_MC_CHIP_TYPE                0x009A
1675 #define ASC_MC_INTRB_CODE               0x009B
1676 #define ASC_MC_WDTR_ABLE                0x009C
1677 #define ASC_MC_SDTR_ABLE                0x009E
1678 #define ASC_MC_TAGQNG_ABLE              0x00A0
1679 #define ASC_MC_DISC_ENABLE              0x00A2
1680 #define ASC_MC_IDLE_CMD_STATUS          0x00A4
1681 #define ASC_MC_IDLE_CMD                 0x00A6
1682 #define ASC_MC_IDLE_CMD_PARAMETER       0x00A8
1683 #define ASC_MC_DEFAULT_SCSI_CFG0        0x00AC
1684 #define ASC_MC_DEFAULT_SCSI_CFG1        0x00AE
1685 #define ASC_MC_DEFAULT_MEM_CFG          0x00B0
1686 #define ASC_MC_DEFAULT_SEL_MASK         0x00B2
1687 #define ASC_MC_SDTR_DONE                0x00B6
1688 #define ASC_MC_NUMBER_OF_QUEUED_CMD     0x00C0
1689 #define ASC_MC_NUMBER_OF_MAX_CMD        0x00D0
1690 #define ASC_MC_DEVICE_HSHK_CFG_TABLE    0x0100
1691 #define ASC_MC_CONTROL_FLAG             0x0122  /* Microcode control flag. */
1692 #define ASC_MC_WDTR_DONE                0x0124
1693 #define ASC_MC_CAM_MODE_MASK            0x015E  /* CAM mode TID bitmask. */
1694 #define ASC_MC_ICQ                      0x0160
1695 #define ASC_MC_IRQ                      0x0164
1696 #define ASC_MC_PPR_ABLE                 0x017A
1697 
1698 /*
1699  * BIOS LRAM variable absolute offsets.
1700  */
1701 #define BIOS_CODESEG    0x54
1702 #define BIOS_CODELEN    0x56
1703 #define BIOS_SIGNATURE  0x58
1704 #define BIOS_VERSION    0x5A
1705 
1706 /*
1707  * Microcode Control Flags
1708  *
1709  * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1710  * and handled by the microcode.
1711  */
1712 #define CONTROL_FLAG_IGNORE_PERR        0x0001  /* Ignore DMA Parity Errors */
1713 #define CONTROL_FLAG_ENABLE_AIPP        0x0002  /* Enabled AIPP checking. */
1714 
1715 /*
1716  * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1717  */
1718 #define HSHK_CFG_WIDE_XFR       0x8000
1719 #define HSHK_CFG_RATE           0x0F00
1720 #define HSHK_CFG_OFFSET         0x001F
1721 
1722 #define ASC_DEF_MAX_HOST_QNG    0xFD    /* Max. number of host commands (253) */
1723 #define ASC_DEF_MIN_HOST_QNG    0x10    /* Min. number of host commands (16) */
1724 #define ASC_DEF_MAX_DVC_QNG     0x3F    /* Max. number commands per device (63) */
1725 #define ASC_DEF_MIN_DVC_QNG     0x04    /* Min. number commands per device (4) */
1726 
1727 #define ASC_QC_DATA_CHECK  0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1728 #define ASC_QC_DATA_OUT    0x02 /* Data out DMA transfer. */
1729 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1730 #define ASC_QC_NO_OVERRUN  0x08 /* Don't report overrun. */
1731 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1732 
1733 #define ASC_QSC_NO_DISC     0x01        /* Don't allow disconnect for request. */
1734 #define ASC_QSC_NO_TAGMSG   0x02        /* Don't allow tag queuing for request. */
1735 #define ASC_QSC_NO_SYNC     0x04        /* Don't use Synch. transfer on request. */
1736 #define ASC_QSC_NO_WIDE     0x08        /* Don't use Wide transfer on request. */
1737 #define ASC_QSC_REDO_DTR    0x10        /* Renegotiate WDTR/SDTR before request. */
1738 /*
1739  * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1740  * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1741  */
1742 #define ASC_QSC_HEAD_TAG    0x40        /* Use Head Tag Message (0x21). */
1743 #define ASC_QSC_ORDERED_TAG 0x80        /* Use Ordered Tag Message (0x22). */
1744 
1745 /*
1746  * All fields here are accessed by the board microcode and need to be
1747  * little-endian.
1748  */
1749 typedef struct adv_carr_t {
1750         ADV_VADDR carr_va;      /* Carrier Virtual Address */
1751         ADV_PADDR carr_pa;      /* Carrier Physical Address */
1752         ADV_VADDR areq_vpa;     /* ASC_SCSI_REQ_Q Virtual or Physical Address */
1753         /*
1754          * next_vpa [31:4]            Carrier Virtual or Physical Next Pointer
1755          *
1756          * next_vpa [3:1]             Reserved Bits
1757          * next_vpa [0]               Done Flag set in Response Queue.
1758          */
1759         ADV_VADDR next_vpa;
1760 } ADV_CARR_T;
1761 
1762 /*
1763  * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1764  */
1765 #define ASC_NEXT_VPA_MASK       0xFFFFFFF0
1766 
1767 #define ASC_RQ_DONE             0x00000001
1768 #define ASC_RQ_GOOD             0x00000002
1769 #define ASC_CQ_STOPPER          0x00000000
1770 
1771 #define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
1772 
1773 #define ADV_CARRIER_NUM_PAGE_CROSSING \
1774     (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + (PAGE_SIZE - 1))/PAGE_SIZE)
1775 
1776 #define ADV_CARRIER_BUFSIZE \
1777     ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
1778 
1779 /*
1780  * ASC_SCSI_REQ_Q 'a_flag' definitions
1781  *
1782  * The Adv Library should limit use to the lower nibble (4 bits) of
1783  * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
1784  */
1785 #define ADV_POLL_REQUEST                0x01    /* poll for request completion */
1786 #define ADV_SCSIQ_DONE                  0x02    /* request done */
1787 #define ADV_DONT_RETRY                  0x08    /* don't do retry */
1788 
1789 #define ADV_CHIP_ASC3550          0x01  /* Ultra-Wide IC */
1790 #define ADV_CHIP_ASC38C0800       0x02  /* Ultra2-Wide/LVD IC */
1791 #define ADV_CHIP_ASC38C1600       0x03  /* Ultra3-Wide/LVD2 IC */
1792 
1793 /*
1794  * Adapter temporary configuration structure
1795  *
1796  * This structure can be discarded after initialization. Don't add
1797  * fields here needed after initialization.
1798  *
1799  * Field naming convention:
1800  *
1801  *  *_enable indicates the field enables or disables a feature. The
1802  *  value of the field is never reset.
1803  */
1804 typedef struct adv_dvc_cfg {
1805         ushort disc_enable;     /* enable disconnection */
1806         uchar chip_version;     /* chip version */
1807         uchar termination;      /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
1808         ushort control_flag;    /* Microcode Control Flag */
1809         ushort mcode_date;      /* Microcode date */
1810         ushort mcode_version;   /* Microcode version */
1811         ushort serial1;         /* EEPROM serial number word 1 */
1812         ushort serial2;         /* EEPROM serial number word 2 */
1813         ushort serial3;         /* EEPROM serial number word 3 */
1814 } ADV_DVC_CFG;
1815 
1816 struct adv_dvc_var;
1817 struct adv_scsi_req_q;
1818 
1819 typedef struct asc_sg_block {
1820         uchar reserved1;
1821         uchar reserved2;
1822         uchar reserved3;
1823         uchar sg_cnt;           /* Valid entries in block. */
1824         ADV_PADDR sg_ptr;       /* Pointer to next sg block. */
1825         struct {
1826                 ADV_PADDR sg_addr;      /* SG element address. */
1827                 ADV_DCNT sg_count;      /* SG element count. */
1828         } sg_list[NO_OF_SG_PER_BLOCK];
1829 } ADV_SG_BLOCK;
1830 
1831 /*
1832  * ADV_SCSI_REQ_Q - microcode request structure
1833  *
1834  * All fields in this structure up to byte 60 are used by the microcode.
1835  * The microcode makes assumptions about the size and ordering of fields
1836  * in this structure. Do not change the structure definition here without
1837  * coordinating the change with the microcode.
1838  *
1839  * All fields accessed by microcode must be maintained in little_endian
1840  * order.
1841  */
1842 typedef struct adv_scsi_req_q {
1843         uchar cntl;             /* Ucode flags and state (ASC_MC_QC_*). */
1844         uchar target_cmd;
1845         uchar target_id;        /* Device target identifier. */
1846         uchar target_lun;       /* Device target logical unit number. */
1847         ADV_PADDR data_addr;    /* Data buffer physical address. */
1848         ADV_DCNT data_cnt;      /* Data count. Ucode sets to residual. */
1849         ADV_PADDR sense_addr;
1850         ADV_PADDR carr_pa;
1851         uchar mflag;
1852         uchar sense_len;
1853         uchar cdb_len;          /* SCSI CDB length. Must <= 16 bytes. */
1854         uchar scsi_cntl;
1855         uchar done_status;      /* Completion status. */
1856         uchar scsi_status;      /* SCSI status byte. */
1857         uchar host_status;      /* Ucode host status. */
1858         uchar sg_working_ix;
1859         uchar cdb[12];          /* SCSI CDB bytes 0-11. */
1860         ADV_PADDR sg_real_addr; /* SG list physical address. */
1861         ADV_PADDR scsiq_rptr;
1862         uchar cdb16[4];         /* SCSI CDB bytes 12-15. */
1863         ADV_VADDR scsiq_ptr;
1864         ADV_VADDR carr_va;
1865         /*
1866          * End of microcode structure - 60 bytes. The rest of the structure
1867          * is used by the Adv Library and ignored by the microcode.
1868          */
1869         ADV_VADDR srb_ptr;
1870         ADV_SG_BLOCK *sg_list_ptr;      /* SG list virtual address. */
1871         char *vdata_addr;       /* Data buffer virtual address. */
1872         uchar a_flag;
1873         uchar pad[2];           /* Pad out to a word boundary. */
1874 } ADV_SCSI_REQ_Q;
1875 
1876 /*
1877  * The following two structures are used to process Wide Board requests.
1878  *
1879  * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
1880  * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the
1881  * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the
1882  * Mid-Level SCSI request structure.
1883  *
1884  * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
1885  * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
1886  * up to 255 scatter-gather elements may be used per request or
1887  * ADV_SCSI_REQ_Q.
1888  *
1889  * Both structures must be 32 byte aligned.
1890  */
1891 typedef struct adv_sgblk {
1892         ADV_SG_BLOCK sg_block;  /* Sgblock structure. */
1893         uchar align[32];        /* Sgblock structure padding. */
1894         struct adv_sgblk *next_sgblkp;  /* Next scatter-gather structure. */
1895 } adv_sgblk_t;
1896 
1897 typedef struct adv_req {
1898         ADV_SCSI_REQ_Q scsi_req_q;      /* Adv Library request structure. */
1899         uchar align[32];        /* Request structure padding. */
1900         struct scsi_cmnd *cmndp;        /* Mid-Level SCSI command pointer. */
1901         adv_sgblk_t *sgblkp;    /* Adv Library scatter-gather pointer. */
1902         struct adv_req *next_reqp;      /* Next Request Structure. */
1903 } adv_req_t;
1904 
1905 /*
1906  * Adapter operation variable structure.
1907  *
1908  * One structure is required per host adapter.
1909  *
1910  * Field naming convention:
1911  *
1912  *  *_able indicates both whether a feature should be enabled or disabled
1913  *  and whether a device isi capable of the feature. At initialization
1914  *  this field may be set, but later if a device is found to be incapable
1915  *  of the feature, the field is cleared.
1916  */
1917 typedef struct adv_dvc_var {
1918         AdvPortAddr iop_base;   /* I/O port address */
1919         ushort err_code;        /* fatal error code */
1920         ushort bios_ctrl;       /* BIOS control word, EEPROM word 12 */
1921         ushort wdtr_able;       /* try WDTR for a device */
1922         ushort sdtr_able;       /* try SDTR for a device */
1923         ushort ultra_able;      /* try SDTR Ultra speed for a device */
1924         ushort sdtr_speed1;     /* EEPROM SDTR Speed for TID 0-3   */
1925         ushort sdtr_speed2;     /* EEPROM SDTR Speed for TID 4-7   */
1926         ushort sdtr_speed3;     /* EEPROM SDTR Speed for TID 8-11  */
1927         ushort sdtr_speed4;     /* EEPROM SDTR Speed for TID 12-15 */
1928         ushort tagqng_able;     /* try tagged queuing with a device */
1929         ushort ppr_able;        /* PPR message capable per TID bitmask. */
1930         uchar max_dvc_qng;      /* maximum number of tagged commands per device */
1931         ushort start_motor;     /* start motor command allowed */
1932         uchar scsi_reset_wait;  /* delay in seconds after scsi bus reset */
1933         uchar chip_no;          /* should be assigned by caller */
1934         uchar max_host_qng;     /* maximum number of Q'ed command allowed */
1935         ushort no_scam;         /* scam_tolerant of EEPROM */
1936         struct asc_board *drv_ptr;      /* driver pointer to private structure */
1937         uchar chip_scsi_id;     /* chip SCSI target ID */
1938         uchar chip_type;
1939         uchar bist_err_code;
1940         ADV_CARR_T *carrier_buf;
1941         ADV_CARR_T *carr_freelist;      /* Carrier free list. */
1942         ADV_CARR_T *icq_sp;     /* Initiator command queue stopper pointer. */
1943         ADV_CARR_T *irq_sp;     /* Initiator response queue stopper pointer. */
1944         ushort carr_pending_cnt;        /* Count of pending carriers. */
1945         struct adv_req *orig_reqp;      /* adv_req_t memory block. */
1946         /*
1947          * Note: The following fields will not be used after initialization. The
1948          * driver may discard the buffer after initialization is done.
1949          */
1950         ADV_DVC_CFG *cfg;       /* temporary configuration structure  */
1951 } ADV_DVC_VAR;
1952 
1953 /*
1954  * Microcode idle loop commands
1955  */
1956 #define IDLE_CMD_COMPLETED           0
1957 #define IDLE_CMD_STOP_CHIP           0x0001
1958 #define IDLE_CMD_STOP_CHIP_SEND_INT  0x0002
1959 #define IDLE_CMD_SEND_INT            0x0004
1960 #define IDLE_CMD_ABORT               0x0008
1961 #define IDLE_CMD_DEVICE_RESET        0x0010
1962 #define IDLE_CMD_SCSI_RESET_START    0x0020     /* Assert SCSI Bus Reset */
1963 #define IDLE_CMD_SCSI_RESET_END      0x0040     /* Deassert SCSI Bus Reset */
1964 #define IDLE_CMD_SCSIREQ             0x0080
1965 
1966 #define IDLE_CMD_STATUS_SUCCESS      0x0001
1967 #define IDLE_CMD_STATUS_FAILURE      0x0002
1968 
1969 /*
1970  * AdvSendIdleCmd() flag definitions.
1971  */
1972 #define ADV_NOWAIT     0x01
1973 
1974 /*
1975  * Wait loop time out values.
1976  */
1977 #define SCSI_WAIT_100_MSEC           100UL      /* 100 milliseconds */
1978 #define SCSI_US_PER_MSEC             1000       /* microseconds per millisecond */
1979 #define SCSI_MAX_RETRY               10 /* retry count */
1980 
1981 #define ADV_ASYNC_RDMA_FAILURE          0x01    /* Fatal RDMA failure. */
1982 #define ADV_ASYNC_SCSI_BUS_RESET_DET    0x02    /* Detected SCSI Bus Reset. */
1983 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03    /* Carrier Ready failure. */
1984 #define ADV_RDMA_IN_CARR_AND_Q_INVALID  0x04    /* RDMAed-in data invalid. */
1985 
1986 #define ADV_HOST_SCSI_BUS_RESET      0x80       /* Host Initiated SCSI Bus Reset. */
1987 
1988 /* Read byte from a register. */
1989 #define AdvReadByteRegister(iop_base, reg_off) \
1990      (ADV_MEM_READB((iop_base) + (reg_off)))
1991 
1992 /* Write byte to a register. */
1993 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
1994      (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
1995 
1996 /* Read word (2 bytes) from a register. */
1997 #define AdvReadWordRegister(iop_base, reg_off) \
1998      (ADV_MEM_READW((iop_base) + (reg_off)))
1999 
2000 /* Write word (2 bytes) to a register. */
2001 #define AdvWriteWordRegister(iop_base, reg_off, word) \
2002      (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
2003 
2004 /* Write dword (4 bytes) to a register. */
2005 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
2006      (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
2007 
2008 /* Read byte from LRAM. */
2009 #define AdvReadByteLram(iop_base, addr, byte) \
2010 do { \
2011     ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2012     (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
2013 } while (0)
2014 
2015 /* Write byte to LRAM. */
2016 #define AdvWriteByteLram(iop_base, addr, byte) \
2017     (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2018      ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
2019 
2020 /* Read word (2 bytes) from LRAM. */
2021 #define AdvReadWordLram(iop_base, addr, word) \
2022 do { \
2023     ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2024     (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
2025 } while (0)
2026 
2027 /* Write word (2 bytes) to LRAM. */
2028 #define AdvWriteWordLram(iop_base, addr, word) \
2029     (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2030      ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2031 
2032 /* Write little-endian double word (4 bytes) to LRAM */
2033 /* Because of unspecified C language ordering don't use auto-increment. */
2034 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
2035     ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2036       ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2037                      cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
2038      (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
2039       ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2040                      cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
2041 
2042 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
2043 #define AdvReadWordAutoIncLram(iop_base) \
2044      (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
2045 
2046 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
2047 #define AdvWriteWordAutoIncLram(iop_base, word) \
2048      (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2049 
2050 /*
2051  * Define macro to check for Condor signature.
2052  *
2053  * Evaluate to ADV_TRUE if a Condor chip is found the specified port
2054  * address 'iop_base'. Otherwise evalue to ADV_FALSE.
2055  */
2056 #define AdvFindSignature(iop_base) \
2057     (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
2058     ADV_CHIP_ID_BYTE) && \
2059      (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
2060     ADV_CHIP_ID_WORD)) ?  ADV_TRUE : ADV_FALSE)
2061 
2062 /*
2063  * Define macro to Return the version number of the chip at 'iop_base'.
2064  *
2065  * The second parameter 'bus_type' is currently unused.
2066  */
2067 #define AdvGetChipVersion(iop_base, bus_type) \
2068     AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
2069 
2070 /*
2071  * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
2072  * match the ASC_SCSI_REQ_Q 'srb_ptr' field.
2073  *
2074  * If the request has not yet been sent to the device it will simply be
2075  * aborted from RISC memory. If the request is disconnected it will be
2076  * aborted on reselection by sending an Abort Message to the target ID.
2077  *
2078  * Return value:
2079  *      ADV_TRUE(1) - Queue was successfully aborted.
2080  *      ADV_FALSE(0) - Queue was not found on the active queue list.
2081  */
2082 #define AdvAbortQueue(asc_dvc, scsiq) \
2083         AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2084                        (ADV_DCNT) (scsiq))
2085 
2086 /*
2087  * Send a Bus Device Reset Message to the specified target ID.
2088  *
2089  * All outstanding commands will be purged if sending the
2090  * Bus Device Reset Message is successful.
2091  *
2092  * Return Value:
2093  *      ADV_TRUE(1) - All requests on the target are purged.
2094  *      ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2095  *                     are not purged.
2096  */
2097 #define AdvResetDevice(asc_dvc, target_id) \
2098         AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2099                     (ADV_DCNT) (target_id))
2100 
2101 /*
2102  * SCSI Wide Type definition.
2103  */
2104 #define ADV_SCSI_BIT_ID_TYPE   ushort
2105 
2106 /*
2107  * AdvInitScsiTarget() 'cntl_flag' options.
2108  */
2109 #define ADV_SCAN_LUN           0x01
2110 #define ADV_CAPINFO_NOLUN      0x02
2111 
2112 /*
2113  * Convert target id to target id bit mask.
2114  */
2115 #define ADV_TID_TO_TIDMASK(tid)   (0x01 << ((tid) & ADV_MAX_TID))
2116 
2117 /*
2118  * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2119  */
2120 
2121 #define QD_NO_STATUS         0x00       /* Request not completed yet. */
2122 #define QD_NO_ERROR          0x01
2123 #define QD_ABORTED_BY_HOST   0x02
2124 #define QD_WITH_ERROR        0x04
2125 
2126 #define QHSTA_NO_ERROR              0x00
2127 #define QHSTA_M_SEL_TIMEOUT         0x11
2128 #define QHSTA_M_DATA_OVER_RUN       0x12
2129 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2130 #define QHSTA_M_QUEUE_ABORTED       0x15
2131 #define QHSTA_M_SXFR_SDMA_ERR       0x16        /* SXFR_STATUS SCSI DMA Error */
2132 #define QHSTA_M_SXFR_SXFR_PERR      0x17        /* SXFR_STATUS SCSI Bus Parity Error */
2133 #define QHSTA_M_RDMA_PERR           0x18        /* RISC PCI DMA parity error */
2134 #define QHSTA_M_SXFR_OFF_UFLW       0x19        /* SXFR_STATUS Offset Underflow */
2135 #define QHSTA_M_SXFR_OFF_OFLW       0x20        /* SXFR_STATUS Offset Overflow */
2136 #define QHSTA_M_SXFR_WD_TMO         0x21        /* SXFR_STATUS Watchdog Timeout */
2137 #define QHSTA_M_SXFR_DESELECTED     0x22        /* SXFR_STATUS Deselected */
2138 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
2139 #define QHSTA_M_SXFR_XFR_OFLW       0x12        /* SXFR_STATUS Transfer Overflow */
2140 #define QHSTA_M_SXFR_XFR_PH_ERR     0x24        /* SXFR_STATUS Transfer Phase Error */
2141 #define QHSTA_M_SXFR_UNKNOWN_ERROR  0x25        /* SXFR_STATUS Unknown Error */
2142 #define QHSTA_M_SCSI_BUS_RESET      0x30        /* Request aborted from SBR */
2143 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31       /* Request aborted from unsol. SBR */
2144 #define QHSTA_M_BUS_DEVICE_RESET    0x32        /* Request aborted from BDR */
2145 #define QHSTA_M_DIRECTION_ERR       0x35        /* Data Phase mismatch */
2146 #define QHSTA_M_DIRECTION_ERR_HUNG  0x36        /* Data Phase mismatch and bus hang */
2147 #define QHSTA_M_WTM_TIMEOUT         0x41
2148 #define QHSTA_M_BAD_CMPL_STATUS_IN  0x42
2149 #define QHSTA_M_NO_AUTO_REQ_SENSE   0x43
2150 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
2151 #define QHSTA_M_INVALID_DEVICE      0x45        /* Bad target ID */
2152 #define QHSTA_M_FROZEN_TIDQ         0x46        /* TID Queue frozen. */
2153 #define QHSTA_M_SGBACKUP_ERROR      0x47        /* Scatter-Gather backup error */
2154 
2155 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
2156 #define ADV_8BALIGN(addr)      (((ulong) (addr) + 0x7) & ~0x7)
2157 #define ADV_16BALIGN(addr)     (((ulong) (addr) + 0xF) & ~0xF)
2158 #define ADV_32BALIGN(addr)     (((ulong) (addr) + 0x1F) & ~0x1F)
2159 
2160 /*
2161  * Total contiguous memory needed for driver SG blocks.
2162  *
2163  * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2164  * number of scatter-gather elements the driver supports in a
2165  * single request.
2166  */
2167 
2168 #define ADV_SG_LIST_MAX_BYTE_SIZE \
2169          (sizeof(ADV_SG_BLOCK) * \
2170           ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2171 
2172 /* struct asc_board flags */
2173 #define ASC_IS_WIDE_BOARD       0x04    /* AdvanSys Wide Board */
2174 
2175 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
2176 
2177 #define NO_ISA_DMA              0xff    /* No ISA DMA Channel Used */
2178 
2179 #define ASC_INFO_SIZE           128     /* advansys_info() line size */
2180 
2181 /* Asc Library return codes */
2182 #define ASC_TRUE        1
2183 #define ASC_FALSE       0
2184 #define ASC_NOERROR     1
2185 #define ASC_BUSY        0
2186 #define ASC_ERROR       (-1)
2187 
2188 /* struct scsi_cmnd function return codes */
2189 #define STATUS_BYTE(byte)   (byte)
2190 #define MSG_BYTE(byte)      ((byte) << 8)
2191 #define HOST_BYTE(byte)     ((byte) << 16)
2192 #define DRIVER_BYTE(byte)   ((byte) << 24)
2193 
2194 #define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
2195 #ifndef ADVANSYS_STATS
2196 #define ASC_STATS_ADD(shost, counter, count)
2197 #else /* ADVANSYS_STATS */
2198 #define ASC_STATS_ADD(shost, counter, count) \
2199         (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
2200 #endif /* ADVANSYS_STATS */
2201 
2202 /* If the result wraps when calculating tenths, return 0. */
2203 #define ASC_TENTHS(num, den) \
2204     (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2205     0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2206 
2207 /*
2208  * Display a message to the console.
2209  */
2210 #define ASC_PRINT(s) \
2211     { \
2212         printk("advansys: "); \
2213         printk(s); \
2214     }
2215 
2216 #define ASC_PRINT1(s, a1) \
2217     { \
2218         printk("advansys: "); \
2219         printk((s), (a1)); \
2220     }
2221 
2222 #define ASC_PRINT2(s, a1, a2) \
2223     { \
2224         printk("advansys: "); \
2225         printk((s), (a1), (a2)); \
2226     }
2227 
2228 #define ASC_PRINT3(s, a1, a2, a3) \
2229     { \
2230         printk("advansys: "); \
2231         printk((s), (a1), (a2), (a3)); \
2232     }
2233 
2234 #define ASC_PRINT4(s, a1, a2, a3, a4) \
2235     { \
2236         printk("advansys: "); \
2237         printk((s), (a1), (a2), (a3), (a4)); \
2238     }
2239 
2240 #ifndef ADVANSYS_DEBUG
2241 
2242 #define ASC_DBG(lvl, s...)
2243 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
2244 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2245 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2246 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2247 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2248 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
2249 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
2250 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
2251 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2252 
2253 #else /* ADVANSYS_DEBUG */
2254 
2255 /*
2256  * Debugging Message Levels:
2257  * 0: Errors Only
2258  * 1: High-Level Tracing
2259  * 2-N: Verbose Tracing
2260  */
2261 
2262 #define ASC_DBG(lvl, format, arg...) {                                  \
2263         if (asc_dbglvl >= (lvl))                                        \
2264                 printk(KERN_DEBUG "%s: %s: " format, DRV_NAME,          \
2265                         __func__ , ## arg);                             \
2266 }
2267 
2268 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2269     { \
2270         if (asc_dbglvl >= (lvl)) { \
2271             asc_prt_scsi_host(s); \
2272         } \
2273     }
2274 
2275 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2276     { \
2277         if (asc_dbglvl >= (lvl)) { \
2278             asc_prt_asc_scsi_q(scsiqp); \
2279         } \
2280     }
2281 
2282 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2283     { \
2284         if (asc_dbglvl >= (lvl)) { \
2285             asc_prt_asc_qdone_info(qdone); \
2286         } \
2287     }
2288 
2289 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2290     { \
2291         if (asc_dbglvl >= (lvl)) { \
2292             asc_prt_adv_scsi_req_q(scsiqp); \
2293         } \
2294     }
2295 
2296 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2297     { \
2298         if (asc_dbglvl >= (lvl)) { \
2299             asc_prt_hex((name), (start), (length)); \
2300         } \
2301     }
2302 
2303 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2304         ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2305 
2306 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2307         ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2308 
2309 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2310         ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2311 #endif /* ADVANSYS_DEBUG */
2312 
2313 #ifdef ADVANSYS_STATS
2314 
2315 /* Per board statistics structure */
2316 struct asc_stats {
2317         /* Driver Entrypoint Statistics */
2318         ADV_DCNT queuecommand;  /* # calls to advansys_queuecommand() */
2319         ADV_DCNT reset;         /* # calls to advansys_eh_bus_reset() */
2320         ADV_DCNT biosparam;     /* # calls to advansys_biosparam() */
2321         ADV_DCNT interrupt;     /* # advansys_interrupt() calls */
2322         ADV_DCNT callback;      /* # calls to asc/adv_isr_callback() */
2323         ADV_DCNT done;          /* # calls to request's scsi_done function */
2324         ADV_DCNT build_error;   /* # asc/adv_build_req() ASC_ERROR returns. */
2325         ADV_DCNT adv_build_noreq;       /* # adv_build_req() adv_req_t alloc. fail. */
2326         ADV_DCNT adv_build_nosg;        /* # adv_build_req() adv_sgblk_t alloc. fail. */
2327         /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2328         ADV_DCNT exe_noerror;   /* # ASC_NOERROR returns. */
2329         ADV_DCNT exe_busy;      /* # ASC_BUSY returns. */
2330         ADV_DCNT exe_error;     /* # ASC_ERROR returns. */
2331         ADV_DCNT exe_unknown;   /* # unknown returns. */
2332         /* Data Transfer Statistics */
2333         ADV_DCNT xfer_cnt;      /* # I/O requests received */
2334         ADV_DCNT xfer_elem;     /* # scatter-gather elements */
2335         ADV_DCNT xfer_sect;     /* # 512-byte blocks */
2336 };
2337 #endif /* ADVANSYS_STATS */
2338 
2339 /*
2340  * Structure allocated for each board.
2341  *
2342  * This structure is allocated by scsi_host_alloc() at the end
2343  * of the 'Scsi_Host' structure starting at the 'hostdata'
2344  * field. It is guaranteed to be allocated from DMA-able memory.
2345  */
2346 struct asc_board {
2347         struct device *dev;
2348         uint flags;             /* Board flags */
2349         unsigned int irq;
2350         union {
2351                 ASC_DVC_VAR asc_dvc_var;        /* Narrow board */
2352                 ADV_DVC_VAR adv_dvc_var;        /* Wide board */
2353         } dvc_var;
2354         union {
2355                 ASC_DVC_CFG asc_dvc_cfg;        /* Narrow board */
2356                 ADV_DVC_CFG adv_dvc_cfg;        /* Wide board */
2357         } dvc_cfg;
2358         ushort asc_n_io_port;   /* Number I/O ports. */
2359         ADV_SCSI_BIT_ID_TYPE init_tidmask;      /* Target init./valid mask */
2360         ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2361         ADV_SCSI_BIT_ID_TYPE queue_full;        /* Queue full mask */
2362         ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2363         union {
2364                 ASCEEP_CONFIG asc_eep;  /* Narrow EEPROM config. */
2365                 ADVEEP_3550_CONFIG adv_3550_eep;        /* 3550 EEPROM config. */
2366                 ADVEEP_38C0800_CONFIG adv_38C0800_eep;  /* 38C0800 EEPROM config. */
2367                 ADVEEP_38C1600_CONFIG adv_38C1600_eep;  /* 38C1600 EEPROM config. */
2368         } eep_config;
2369         ulong last_reset;       /* Saved last reset time */
2370         /* /proc/scsi/advansys/[0...] */
2371 #ifdef ADVANSYS_STATS
2372         struct asc_stats asc_stats;     /* Board statistics */
2373 #endif                          /* ADVANSYS_STATS */
2374         /*
2375          * The following fields are used only for Narrow Boards.
2376          */
2377         uchar sdtr_data[ASC_MAX_TID + 1];       /* SDTR information */
2378         /*
2379          * The following fields are used only for Wide Boards.
2380          */
2381         void __iomem *ioremap_addr;     /* I/O Memory remap address. */
2382         ushort ioport;          /* I/O Port address. */
2383         adv_req_t *adv_reqp;    /* Request structures. */
2384         adv_sgblk_t *adv_sgblkp;        /* Scatter-gather structures. */
2385         ushort bios_signature;  /* BIOS Signature. */
2386         ushort bios_version;    /* BIOS Version. */
2387         ushort bios_codeseg;    /* BIOS Code Segment. */
2388         ushort bios_codelen;    /* BIOS Code Segment Length. */
2389 };
2390 
2391 #define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \
2392                                                         dvc_var.asc_dvc_var)
2393 #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2394                                                         dvc_var.adv_dvc_var)
2395 #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2396 
2397 #ifdef ADVANSYS_DEBUG
2398 static int asc_dbglvl = 3;
2399 
2400 /*
2401  * asc_prt_asc_dvc_var()
2402  */
2403 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
2404 {
2405         printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
2406 
2407         printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2408                "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2409 
2410         printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2411                 (unsigned)h->init_sdtr);
2412 
2413         printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2414                "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2415                (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2416                (unsigned)h->chip_no);
2417 
2418         printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2419                "%u,\n", (unsigned)h->queue_full_or_busy,
2420                (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2421 
2422         printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2423                "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2424                (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2425                (unsigned)h->in_critical_cnt);
2426 
2427         printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2428                "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2429                (unsigned)h->init_state, (unsigned)h->no_scam,
2430                (unsigned)h->pci_fix_asyn_xfer);
2431 
2432         printk(" cfg 0x%lx\n", (ulong)h->cfg);
2433 }
2434 
2435 /*
2436  * asc_prt_asc_dvc_cfg()
2437  */
2438 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
2439 {
2440         printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
2441 
2442         printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2443                h->can_tagged_qng, h->cmd_qng_enabled);
2444         printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2445                h->disc_enable, h->sdtr_enable);
2446 
2447         printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
2448                 "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
2449                 h->isa_dma_channel, h->chip_version);
2450 
2451         printk(" mcode_date 0x%x, mcode_version %d\n",
2452                 h->mcode_date, h->mcode_version);
2453 }
2454 
2455 /*
2456  * asc_prt_adv_dvc_var()
2457  *
2458  * Display an ADV_DVC_VAR structure.
2459  */
2460 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
2461 {
2462         printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
2463 
2464         printk("  iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2465                (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
2466 
2467         printk("  sdtr_able 0x%x, wdtr_able 0x%x\n",
2468                (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
2469 
2470         printk("  start_motor 0x%x, scsi_reset_wait 0x%x\n",
2471                (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2472 
2473         printk("  max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n",
2474                (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2475                (ulong)h->carr_freelist);
2476 
2477         printk("  icq_sp 0x%lx, irq_sp 0x%lx\n",
2478                (ulong)h->icq_sp, (ulong)h->irq_sp);
2479 
2480         printk("  no_scam 0x%x, tagqng_able 0x%x\n",
2481                (unsigned)h->no_scam, (unsigned)h->tagqng_able);
2482 
2483         printk("  chip_scsi_id 0x%x, cfg 0x%lx\n",
2484                (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2485 }
2486 
2487 /*
2488  * asc_prt_adv_dvc_cfg()
2489  *
2490  * Display an ADV_DVC_CFG structure.
2491  */
2492 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2493 {
2494         printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
2495 
2496         printk("  disc_enable 0x%x, termination 0x%x\n",
2497                h->disc_enable, h->termination);
2498 
2499         printk("  chip_version 0x%x, mcode_date 0x%x\n",
2500                h->chip_version, h->mcode_date);
2501 
2502         printk("  mcode_version 0x%x, control_flag 0x%x\n",
2503                h->mcode_version, h->control_flag);
2504 }
2505 
2506 /*
2507  * asc_prt_scsi_host()
2508  */
2509 static void asc_prt_scsi_host(struct Scsi_Host *s)
2510 {
2511         struct asc_board *boardp = shost_priv(s);
2512 
2513         printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev));
2514         printk(" host_busy %u, host_no %d,\n",
2515                atomic_read(&s->host_busy), s->host_no);
2516 
2517         printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
2518                (ulong)s->base, (ulong)s->io_port, boardp->irq);
2519 
2520         printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2521                s->dma_channel, s->this_id, s->can_queue);
2522 
2523         printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2524                s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
2525 
2526         if (ASC_NARROW_BOARD(boardp)) {
2527                 asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
2528                 asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
2529         } else {
2530                 asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
2531                 asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
2532         }
2533 }
2534 
2535 /*
2536  * asc_prt_hex()
2537  *
2538  * Print hexadecimal output in 4 byte groupings 32 bytes
2539  * or 8 double-words per line.
2540  */
2541 static void asc_prt_hex(char *f, uchar *s, int l)
2542 {
2543         int i;
2544         int j;
2545         int k;
2546         int m;
2547 
2548         printk("%s: (%d bytes)\n", f, l);
2549 
2550         for (i = 0; i < l; i += 32) {
2551 
2552                 /* Display a maximum of 8 double-words per line. */
2553                 if ((k = (l - i) / 4) >= 8) {
2554                         k = 8;
2555                         m = 0;
2556                 } else {
2557                         m = (l - i) % 4;
2558                 }
2559 
2560                 for (j = 0; j < k; j++) {
2561                         printk(" %2.2X%2.2X%2.2X%2.2X",
2562                                (unsigned)s[i + (j * 4)],
2563                                (unsigned)s[i + (j * 4) + 1],
2564                                (unsigned)s[i + (j * 4) + 2],
2565                                (unsigned)s[i + (j * 4) + 3]);
2566                 }
2567 
2568                 switch (m) {
2569                 case 0:
2570                 default:
2571                         break;
2572                 case 1:
2573                         printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2574                         break;
2575                 case 2:
2576                         printk(" %2.2X%2.2X",
2577                                (unsigned)s[i + (j * 4)],
2578                                (unsigned)s[i + (j * 4) + 1]);
2579                         break;
2580                 case 3:
2581                         printk(" %2.2X%2.2X%2.2X",
2582                                (unsigned)s[i + (j * 4) + 1],
2583                                (unsigned)s[i + (j * 4) + 2],
2584                                (unsigned)s[i + (j * 4) + 3]);
2585                         break;
2586                 }
2587 
2588                 printk("\n");
2589         }
2590 }
2591 
2592 /*
2593  * asc_prt_asc_scsi_q()
2594  */
2595 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2596 {
2597         ASC_SG_HEAD *sgp;
2598         int i;
2599 
2600         printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2601 
2602         printk
2603             (" target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n",
2604              q->q2.target_ix, q->q1.target_lun, (ulong)q->q2.srb_ptr,
2605              q->q2.tag_code);
2606 
2607         printk
2608             (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2609              (ulong)le32_to_cpu(q->q1.data_addr),
2610              (ulong)le32_to_cpu(q->q1.data_cnt),
2611              (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2612 
2613         printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2614                (ulong)q->cdbptr, q->q2.cdb_len,
2615                (ulong)q->sg_head, q->q1.sg_queue_cnt);
2616 
2617         if (q->sg_head) {
2618                 sgp = q->sg_head;
2619                 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2620                 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2621                        sgp->queue_cnt);
2622                 for (i = 0; i < sgp->entry_cnt; i++) {
2623                         printk(" [%u]: addr 0x%lx, bytes %lu\n",
2624                                i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2625                                (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2626                 }
2627 
2628         }
2629 }
2630 
2631 /*
2632  * asc_prt_asc_qdone_info()
2633  */
2634 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2635 {
2636         printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
2637         printk(" srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n",
2638                (ulong)q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len,
2639                q->d2.tag_code);
2640         printk
2641             (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2642              q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2643 }
2644 
2645 /*
2646  * asc_prt_adv_sgblock()
2647  *
2648  * Display an ADV_SG_BLOCK structure.
2649  */
2650 static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2651 {
2652         int i;
2653 
2654         printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2655                (ulong)b, sgblockno);
2656         printk("  sg_cnt %u, sg_ptr 0x%lx\n",
2657                b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
2658         BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2659         if (b->sg_ptr != 0)
2660                 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2661         for (i = 0; i < b->sg_cnt; i++) {
2662                 printk("  [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
2663                        i, (ulong)b->sg_list[i].sg_addr,
2664                        (ulong)b->sg_list[i].sg_count);
2665         }
2666 }
2667 
2668 /*
2669  * asc_prt_adv_scsi_req_q()
2670  *
2671  * Display an ADV_SCSI_REQ_Q structure.
2672  */
2673 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2674 {
2675         int sg_blk_cnt;
2676         struct asc_sg_block *sg_ptr;
2677 
2678         printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2679 
2680         printk("  target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n",
2681                q->target_id, q->target_lun, (ulong)q->srb_ptr, q->a_flag);
2682 
2683         printk("  cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
2684                q->cntl, (ulong)le32_to_cpu(q->data_addr), (ulong)q->vdata_addr);
2685 
2686         printk("  data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2687                (ulong)le32_to_cpu(q->data_cnt),
2688                (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2689 
2690         printk
2691             ("  cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2692              q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2693 
2694         printk("  sg_working_ix 0x%x, target_cmd %u\n",
2695                q->sg_working_ix, q->target_cmd);
2696 
2697         printk("  scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2698                (ulong)le32_to_cpu(q->scsiq_rptr),
2699                (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2700 
2701         /* Display the request's ADV_SG_BLOCK structures. */
2702         if (q->sg_list_ptr != NULL) {
2703                 sg_blk_cnt = 0;
2704                 while (1) {
2705                         /*
2706                          * 'sg_ptr' is a physical address. Convert it to a virtual
2707                          * address by indexing 'sg_blk_cnt' into the virtual address
2708                          * array 'sg_list_ptr'.
2709                          *
2710                          * XXX - Assumes all SG physical blocks are virtually contiguous.
2711                          */
2712                         sg_ptr =
2713                             &(((ADV_SG_BLOCK *)(q->sg_list_ptr))[sg_blk_cnt]);
2714                         asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2715                         if (sg_ptr->sg_ptr == 0) {
2716                                 break;
2717                         }
2718                         sg_blk_cnt++;
2719                 }
2720         }
2721 }
2722 #endif /* ADVANSYS_DEBUG */
2723 
2724 /*
2725  * The advansys chip/microcode contains a 32-bit identifier for each command
2726  * known as the 'srb'.  I don't know what it stands for.  The driver used
2727  * to encode the scsi_cmnd pointer by calling virt_to_bus and retrieve it
2728  * with bus_to_virt.  Now the driver keeps a per-host map of integers to
2729  * pointers.  It auto-expands when full, unless it can't allocate memory.
2730  * Note that an srb of 0 is treated specially by the chip/firmware, hence
2731  * the return of i+1 in this routine, and the corresponding subtraction in
2732  * the inverse routine.
2733  */
2734 #define BAD_SRB 0
2735 static u32 advansys_ptr_to_srb(struct asc_dvc_var *asc_dvc, void *ptr)
2736 {
2737         int i;
2738         void **new_ptr;
2739 
2740         for (i = 0; i < asc_dvc->ptr_map_count; i++) {
2741                 if (!asc_dvc->ptr_map[i])
2742                         goto out;
2743         }
2744 
2745         if (asc_dvc->ptr_map_count == 0)
2746                 asc_dvc->ptr_map_count = 1;
2747         else
2748                 asc_dvc->ptr_map_count *= 2;
2749 
2750         new_ptr = krealloc(asc_dvc->ptr_map,
2751                         asc_dvc->ptr_map_count * sizeof(void *), GFP_ATOMIC);
2752         if (!new_ptr)
2753                 return BAD_SRB;
2754         asc_dvc->ptr_map = new_ptr;
2755  out:
2756         ASC_DBG(3, "Putting ptr %p into array offset %d\n", ptr, i);
2757         asc_dvc->ptr_map[i] = ptr;
2758         return i + 1;
2759 }
2760 
2761 static void * advansys_srb_to_ptr(struct asc_dvc_var *asc_dvc, u32 srb)
2762 {
2763         void *ptr;
2764 
2765         srb--;
2766         if (srb >= asc_dvc->ptr_map_count) {
2767                 printk("advansys: bad SRB %u, max %u\n", srb,
2768                                                         asc_dvc->ptr_map_count);
2769                 return NULL;
2770         }
2771         ptr = asc_dvc->ptr_map[srb];
2772         asc_dvc->ptr_map[srb] = NULL;
2773         ASC_DBG(3, "Returning ptr %p from array offset %d\n", ptr, srb);
2774         return ptr;
2775 }
2776 
2777 /*
2778  * advansys_info()
2779  *
2780  * Return suitable for printing on the console with the argument
2781  * adapter's configuration information.
2782  *
2783  * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2784  * otherwise the static 'info' array will be overrun.
2785  */
2786 static const char *advansys_info(struct Scsi_Host *shost)
2787 {
2788         static char info[ASC_INFO_SIZE];
2789         struct asc_board *boardp = shost_priv(shost);
2790         ASC_DVC_VAR *asc_dvc_varp;
2791         ADV_DVC_VAR *adv_dvc_varp;
2792         char *busname;
2793         char *widename = NULL;
2794 
2795         if (ASC_NARROW_BOARD(boardp)) {
2796                 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2797                 ASC_DBG(1, "begin\n");
2798                 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2799                         if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2800                             ASC_IS_ISAPNP) {
2801                                 busname = "ISA PnP";
2802                         } else {
2803                                 busname = "ISA";
2804                         }
2805                         sprintf(info,
2806                                 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2807                                 ASC_VERSION, busname,
2808                                 (ulong)shost->io_port,
2809                                 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2810                                 boardp->irq, shost->dma_channel);
2811                 } else {
2812                         if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2813                                 busname = "VL";
2814                         } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2815                                 busname = "EISA";
2816                         } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2817                                 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2818                                     == ASC_IS_PCI_ULTRA) {
2819                                         busname = "PCI Ultra";
2820                                 } else {
2821                                         busname = "PCI";
2822                                 }
2823                         } else {
2824                                 busname = "?";
2825                                 shost_printk(KERN_ERR, shost, "unknown bus "
2826                                         "type %d\n", asc_dvc_varp->bus_type);
2827                         }
2828                         sprintf(info,
2829                                 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2830                                 ASC_VERSION, busname, (ulong)shost->io_port,
2831                                 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2832                                 boardp->irq);
2833                 }
2834         } else {
2835                 /*
2836                  * Wide Adapter Information
2837                  *
2838                  * Memory-mapped I/O is used instead of I/O space to access
2839                  * the adapter, but display the I/O Port range. The Memory
2840                  * I/O address is displayed through the driver /proc file.
2841                  */
2842                 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2843                 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2844                         widename = "Ultra-Wide";
2845                 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2846                         widename = "Ultra2-Wide";
2847                 } else {
2848                         widename = "Ultra3-Wide";
2849                 }
2850                 sprintf(info,
2851                         "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2852                         ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
2853                         (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
2854         }
2855         BUG_ON(strlen(info) >= ASC_INFO_SIZE);
2856         ASC_DBG(1, "end\n");
2857         return info;
2858 }
2859 
2860 #ifdef CONFIG_PROC_FS
2861 
2862 /*
2863  * asc_prt_board_devices()
2864  *
2865  * Print driver information for devices attached to the board.
2866  */
2867 static void asc_prt_board_devices(struct seq_file *m, struct Scsi_Host *shost)
2868 {
2869         struct asc_board *boardp = shost_priv(shost);
2870         int chip_scsi_id;
2871         int i;
2872 
2873         seq_printf(m,
2874                    "\nDevice Information for AdvanSys SCSI Host %d:\n",
2875                    shost->host_no);
2876 
2877         if (ASC_NARROW_BOARD(boardp)) {
2878                 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
2879         } else {
2880                 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
2881         }
2882 
2883         seq_puts(m, "Target IDs Detected:");
2884         for (i = 0; i <= ADV_MAX_TID; i++) {
2885                 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i))
2886                         seq_printf(m, " %X,", i);
2887         }
2888         seq_printf(m, " (%X=Host Adapter)\n", chip_scsi_id);
2889 }
2890 
2891 /*
2892  * Display Wide Board BIOS Information.
2893  */
2894 static void asc_prt_adv_bios(struct seq_file *m, struct Scsi_Host *shost)
2895 {
2896         struct asc_board *boardp = shost_priv(shost);
2897         ushort major, minor, letter;
2898 
2899         seq_puts(m, "\nROM BIOS Version: ");
2900 
2901         /*
2902          * If the BIOS saved a valid signature, then fill in
2903          * the BIOS code segment base address.
2904          */
2905         if (boardp->bios_signature != 0x55AA) {
2906                 seq_puts(m, "Disabled or Pre-3.1\n"
2907                         "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n"
2908                         "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
2909         } else {
2910                 major = (boardp->bios_version >> 12) & 0xF;
2911                 minor = (boardp->bios_version >> 8) & 0xF;
2912                 letter = (boardp->bios_version & 0xFF);
2913 
2914                 seq_printf(m, "%d.%d%c\n",
2915                                    major, minor,
2916                                    letter >= 26 ? '?' : letter + 'A');
2917                 /*
2918                  * Current available ROM BIOS release is 3.1I for UW
2919                  * and 3.2I for U2W. This code doesn't differentiate
2920                  * UW and U2W boards.
2921                  */
2922                 if (major < 3 || (major <= 3 && minor < 1) ||
2923                     (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
2924                         seq_puts(m, "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n"
2925                                 "ftp://ftp.connectcom.net/pub\n");
2926                 }
2927         }
2928 }
2929 
2930 /*
2931  * Add serial number to information bar if signature AAh
2932  * is found in at bit 15-9 (7 bits) of word 1.
2933  *
2934  * Serial Number consists fo 12 alpha-numeric digits.
2935  *
2936  *       1 - Product type (A,B,C,D..)  Word0: 15-13 (3 bits)
2937  *       2 - MFG Location (A,B,C,D..)  Word0: 12-10 (3 bits)
2938  *     3-4 - Product ID (0-99)         Word0: 9-0 (10 bits)
2939  *       5 - Product revision (A-J)    Word0:  "         "
2940  *
2941  *           Signature                 Word1: 15-9 (7 bits)
2942  *       6 - Year (0-9)                Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
2943  *     7-8 - Week of the year (1-52)   Word1: 5-0 (6 bits)
2944  *
2945  *    9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
2946  *
2947  * Note 1: Only production cards will have a serial number.
2948  *
2949  * Note 2: Signature is most significant 7 bits (0xFE).
2950  *
2951  * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
2952  */
2953 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
2954 {
2955         ushort w, num;
2956 
2957         if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
2958                 return ASC_FALSE;
2959         } else {
2960                 /*
2961                  * First word - 6 digits.
2962                  */
2963                 w = serialnum[0];
2964 
2965                 /* Product type - 1st digit. */
2966                 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
2967                         /* Product type is P=Prototype */
2968                         *cp += 0x8;
2969                 }
2970                 cp++;
2971 
2972                 /* Manufacturing location - 2nd digit. */
2973                 *cp++ = 'A' + ((w & 0x1C00) >> 10);
2974 
2975                 /* Product ID - 3rd, 4th digits. */
2976                 num = w & 0x3FF;
2977                 *cp++ = '' + (num / 100);
2978                 num %= 100;
2979                 *cp++ = '' + (num / 10);
2980 
2981                 /* Product revision - 5th digit. */
2982                 *cp++ = 'A' + (num % 10);
2983 
2984                 /*
2985                  * Second word
2986                  */
2987                 w = serialnum[1];
2988 
2989                 /*
2990                  * Year - 6th digit.
2991                  *
2992                  * If bit 15 of third word is set, then the
2993                  * last digit of the year is greater than 7.
2994                  */
2995                 if (serialnum[2] & 0x8000) {
2996                         *cp++ = '8' + ((w & 0x1C0) >> 6);
2997                 } else {
2998                         *cp++ = '' + ((w & 0x1C0) >> 6);
2999                 }
3000 
3001                 /* Week of year - 7th, 8th digits. */
3002                 num = w & 0x003F;
3003                 *cp++ = '' + num / 10;
3004                 num %= 10;
3005                 *cp++ = '' + num;
3006 
3007                 /*
3008                  * Third word
3009                  */
3010                 w = serialnum[2] & 0x7FFF;
3011 
3012                 /* Serial number - 9th digit. */
3013                 *cp++ = 'A' + (w / 1000);
3014 
3015                 /* 10th, 11th, 12th digits. */
3016                 num = w % 1000;
3017                 *cp++ = '' + num / 100;
3018                 num %= 100;
3019                 *cp++ = '' + num / 10;
3020                 num %= 10;
3021                 *cp++ = '' + num;
3022 
3023                 *cp = '\0';     /* Null Terminate the string. */
3024                 return ASC_TRUE;
3025         }
3026 }
3027 
3028 /*
3029  * asc_prt_asc_board_eeprom()
3030  *
3031  * Print board EEPROM configuration.
3032  */
3033 static void asc_prt_asc_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
3034 {
3035         struct asc_board *boardp = shost_priv(shost);
3036         ASC_DVC_VAR *asc_dvc_varp;
3037         ASCEEP_CONFIG *ep;
3038         int i;
3039 #ifdef CONFIG_ISA
3040         int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
3041 #endif /* CONFIG_ISA */
3042         uchar serialstr[13];
3043 
3044         asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
3045         ep = &boardp->eep_config.asc_eep;
3046 
3047         seq_printf(m,
3048                    "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3049                    shost->host_no);
3050 
3051         if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
3052             == ASC_TRUE)
3053                 seq_printf(m, " Serial Number: %s\n", serialstr);
3054         else if (ep->adapter_info[5] == 0xBB)
3055                 seq_puts(m,
3056                          " Default Settings Used for EEPROM-less Adapter.\n");
3057         else
3058                 seq_puts(m, " Serial Number Signature Not Present.\n");
3059 
3060         seq_printf(m,
3061                    " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3062                    ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
3063                    ep->max_tag_qng);
3064 
3065         seq_printf(m,
3066                    " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
3067 
3068         seq_puts(m, " Target ID:           ");
3069         for (i = 0; i <= ASC_MAX_TID; i++)
3070                 seq_printf(m, " %d", i);
3071 
3072         seq_puts(m, "\n Disconnects:         ");
3073         for (i = 0; i <= ASC_MAX_TID; i++)
3074                 seq_printf(m, " %c",
3075                            (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3076 
3077         seq_puts(m, "\n Command Queuing:     ");
3078         for (i = 0; i <= ASC_MAX_TID; i++)
3079                 seq_printf(m, " %c",
3080                            (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3081 
3082         seq_puts(m, "\n Start Motor:         ");
3083         for (i = 0; i <= ASC_MAX_TID; i++)
3084                 seq_printf(m, " %c",
3085                            (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3086 
3087         seq_puts(m, "\n Synchronous Transfer:");
3088         for (i = 0; i <= ASC_MAX_TID; i++)
3089                 seq_printf(m, " %c",
3090                            (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3091         seq_putc(m, '\n');
3092 
3093 #ifdef CONFIG_ISA
3094         if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
3095                 seq_printf(m,
3096                            " Host ISA DMA speed:   %d MB/S\n",
3097                            isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
3098         }
3099 #endif /* CONFIG_ISA */
3100 }
3101 
3102 /*
3103  * asc_prt_adv_board_eeprom()
3104  *
3105  * Print board EEPROM configuration.
3106  */
3107 static void asc_prt_adv_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
3108 {
3109         struct asc_board *boardp = shost_priv(shost);
3110         ADV_DVC_VAR *adv_dvc_varp;
3111         int i;
3112         char *termstr;
3113         uchar serialstr[13];
3114         ADVEEP_3550_CONFIG *ep_3550 = NULL;
3115         ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
3116         ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
3117         ushort word;
3118         ushort *wordp;
3119         ushort sdtr_speed = 0;
3120 
3121         adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3122         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3123                 ep_3550 = &boardp->eep_config.adv_3550_eep;
3124         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3125                 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
3126         } else {
3127                 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
3128         }
3129 
3130         seq_printf(m,
3131                    "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3132                    shost->host_no);
3133 
3134         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3135                 wordp = &ep_3550->serial_number_word1;
3136         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3137                 wordp = &ep_38C0800->serial_number_word1;
3138         } else {
3139                 wordp = &ep_38C1600->serial_number_word1;
3140         }
3141 
3142         if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE)
3143                 seq_printf(m, " Serial Number: %s\n", serialstr);
3144         else
3145                 seq_puts(m, " Serial Number Signature Not Present.\n");
3146 
3147         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3148                 seq_printf(m,
3149                            " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3150                            ep_3550->adapter_scsi_id,
3151                            ep_3550->max_host_qng, ep_3550->max_dvc_qng);
3152         else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3153                 seq_printf(m,
3154                            " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3155                            ep_38C0800->adapter_scsi_id,
3156                            ep_38C0800->max_host_qng,
3157                            ep_38C0800->max_dvc_qng);
3158         else
3159                 seq_printf(m,
3160                            " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3161                            ep_38C1600->adapter_scsi_id,
3162                            ep_38C1600->max_host_qng,
3163                            ep_38C1600->max_dvc_qng);
3164         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3165                 word = ep_3550->termination;
3166         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3167                 word = ep_38C0800->termination_lvd;
3168         } else {
3169                 word = ep_38C1600->termination_lvd;
3170         }
3171         switch (word) {
3172         case 1:
3173                 termstr = "Low Off/High Off";
3174                 break;
3175         case 2:
3176                 termstr = "Low Off/High On";
3177                 break;
3178         case 3:
3179                 termstr = "Low On/High On";
3180                 break;
3181         default:
3182         case 0:
3183                 termstr = "Automatic";
3184                 break;
3185         }
3186 
3187         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3188                 seq_printf(m,
3189                            " termination: %u (%s), bios_ctrl: 0x%x\n",
3190                            ep_3550->termination, termstr,
3191                            ep_3550->bios_ctrl);
3192         else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3193                 seq_printf(m,
3194                            " termination: %u (%s), bios_ctrl: 0x%x\n",
3195                            ep_38C0800->termination_lvd, termstr,
3196                            ep_38C0800->bios_ctrl);
3197         else
3198                 seq_printf(m,
3199                            " termination: %u (%s), bios_ctrl: 0x%x\n",
3200                            ep_38C1600->termination_lvd, termstr,
3201                            ep_38C1600->bios_ctrl);
3202 
3203         seq_puts(m, " Target ID:           ");
3204         for (i = 0; i <= ADV_MAX_TID; i++)
3205                 seq_printf(m, " %X", i);
3206         seq_putc(m, '\n');
3207 
3208         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3209                 word = ep_3550->disc_enable;
3210         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3211                 word = ep_38C0800->disc_enable;
3212         } else {
3213                 word = ep_38C1600->disc_enable;
3214         }
3215         seq_puts(m, " Disconnects:         ");
3216         for (i = 0; i <= ADV_MAX_TID; i++)
3217                 seq_printf(m, " %c",
3218                            (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3219         seq_putc(m, '\n');
3220 
3221         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3222                 word = ep_3550->tagqng_able;
3223         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3224                 word = ep_38C0800->tagqng_able;
3225         } else {
3226                 word = ep_38C1600->tagqng_able;
3227         }
3228         seq_puts(m, " Command Queuing:     ");
3229         for (i = 0; i <= ADV_MAX_TID; i++)
3230                 seq_printf(m, " %c",
3231                            (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3232         seq_putc(m, '\n');
3233 
3234         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3235                 word = ep_3550->start_motor;
3236         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3237                 word = ep_38C0800->start_motor;
3238         } else {
3239                 word = ep_38C1600->start_motor;
3240         }
3241         seq_puts(m, " Start Motor:         ");
3242         for (i = 0; i <= ADV_MAX_TID; i++)
3243                 seq_printf(m, " %c",
3244                            (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3245         seq_putc(m, '\n');
3246 
3247         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3248                 seq_puts(m, " Synchronous Transfer:");
3249                 for (i = 0; i <= ADV_MAX_TID; i++)
3250                         seq_printf(m, " %c",
3251                                    (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3252                                    'Y' : 'N');
3253                 seq_putc(m, '\n');
3254         }
3255 
3256         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3257                 seq_puts(m, " Ultra Transfer:      ");
3258                 for (i = 0; i <= ADV_MAX_TID; i++)
3259                         seq_printf(m, " %c",
3260                                    (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i))
3261                                    ? 'Y' : 'N');
3262                 seq_putc(m, '\n');
3263         }
3264 
3265         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3266                 word = ep_3550->wdtr_able;
3267         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3268                 word = ep_38C0800->wdtr_able;
3269         } else {
3270                 word = ep_38C1600->wdtr_able;
3271         }
3272         seq_puts(m, " Wide Transfer:       ");
3273         for (i = 0; i <= ADV_MAX_TID; i++)
3274                 seq_printf(m, " %c",
3275                            (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3276         seq_putc(m, '\n');
3277 
3278         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3279             adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
3280                 seq_puts(m, " Synchronous Transfer Speed (Mhz):\n  ");
3281                 for (i = 0; i <= ADV_MAX_TID; i++) {
3282                         char *speed_str;
3283 
3284                         if (i == 0) {
3285                                 sdtr_speed = adv_dvc_varp->sdtr_speed1;
3286                         } else if (i == 4) {
3287                                 sdtr_speed = adv_dvc_varp->sdtr_speed2;
3288                         } else if (i == 8) {
3289                                 sdtr_speed = adv_dvc_varp->sdtr_speed3;
3290                         } else if (i == 12) {
3291                                 sdtr_speed = adv_dvc_varp->sdtr_speed4;
3292                         }
3293                         switch (sdtr_speed & ADV_MAX_TID) {
3294                         case 0:
3295                                 speed_str = "Off";
3296                                 break;
3297                         case 1:
3298                                 speed_str = "  5";
3299                                 break;
3300                         case 2:
3301                                 speed_str = " 10";
3302                                 break;
3303                         case 3:
3304                                 speed_str = " 20";
3305                                 break;
3306                         case 4:
3307                                 speed_str = " 40";
3308                                 break;
3309                         case 5:
3310                                 speed_str = " 80";
3311                                 break;
3312                         default:
3313                                 speed_str = "Unk";
3314                                 break;
3315                         }
3316                         seq_printf(m, "%X:%s ", i, speed_str);
3317                         if (i == 7)
3318                                 seq_puts(m, "\n  ");
3319                         sdtr_speed >>= 4;
3320                 }
3321                 seq_putc(m, '\n');
3322         }
3323 }
3324 
3325 /*
3326  * asc_prt_driver_conf()
3327  */
3328 static void asc_prt_driver_conf(struct seq_file *m, struct Scsi_Host *shost)
3329 {
3330         struct asc_board *boardp = shost_priv(shost);
3331         int chip_scsi_id;
3332 
3333         seq_printf(m,
3334                 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3335                 shost->host_no);
3336 
3337         seq_printf(m,
3338                    " host_busy %u, max_id %u, max_lun %llu, max_channel %u\n",
3339                    atomic_read(&shost->host_busy), shost->max_id,
3340                    shost->max_lun, shost->max_channel);
3341 
3342         seq_printf(m,
3343                    " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3344                    shost->unique_id, shost->can_queue, shost->this_id,
3345                    shost->sg_tablesize, shost->cmd_per_lun);
3346 
3347         seq_printf(m,
3348                    " unchecked_isa_dma %d, use_clustering %d\n",
3349                    shost->unchecked_isa_dma, shost->use_clustering);
3350 
3351         seq_printf(m,
3352                    " flags 0x%x, last_reset 0x%lx, jiffies 0x%lx, asc_n_io_port 0x%x\n",
3353                    boardp->flags, boardp->last_reset, jiffies,
3354                    boardp->asc_n_io_port);
3355 
3356         seq_printf(m, " io_port 0x%lx\n", shost->io_port);
3357 
3358         if (ASC_NARROW_BOARD(boardp)) {
3359                 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3360         } else {
3361                 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
3362         }
3363 }
3364 
3365 /*
3366  * asc_prt_asc_board_info()
3367  *
3368  * Print dynamic board configuration information.
3369  */
3370 static void asc_prt_asc_board_info(struct seq_file *m, struct Scsi_Host *shost)
3371 {
3372         struct asc_board *boardp = shost_priv(shost);
3373         int chip_scsi_id;
3374         ASC_DVC_VAR *v;
3375         ASC_DVC_CFG *c;
3376         int i;
3377         int renegotiate = 0;
3378 
3379         v = &boardp->dvc_var.asc_dvc_var;
3380         c = &boardp->dvc_cfg.asc_dvc_cfg;
3381         chip_scsi_id = c->chip_scsi_id;
3382 
3383         seq_printf(m,
3384                    "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3385                    shost->host_no);
3386 
3387         seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3388                    "mcode_version 0x%x, err_code %u\n",
3389                    c->chip_version, c->mcode_date, c->mcode_version,
3390                    v->err_code);
3391 
3392         /* Current number of commands waiting for the host. */
3393         seq_printf(m,
3394                    " Total Command Pending: %d\n", v->cur_total_qng);
3395 
3396         seq_puts(m, " Command Queuing:");
3397         for (i = 0; i <= ASC_MAX_TID; i++) {
3398                 if ((chip_scsi_id == i) ||
3399                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3400                         continue;
3401                 }
3402                 seq_printf(m, " %X:%c",
3403                            i,
3404                            (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3405         }
3406 
3407         /* Current number of commands waiting for a device. */
3408         seq_puts(m, "\n Command Queue Pending:");
3409         for (i = 0; i <= ASC_MAX_TID; i++) {
3410                 if ((chip_scsi_id == i) ||
3411                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3412                         continue;
3413                 }
3414                 seq_printf(m, " %X:%u", i, v->cur_dvc_qng[i]);
3415         }
3416 
3417         /* Current limit on number of commands that can be sent to a device. */
3418         seq_puts(m, "\n Command Queue Limit:");
3419         for (i = 0; i <= ASC_MAX_TID; i++) {
3420                 if ((chip_scsi_id == i) ||
3421                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3422                         continue;
3423                 }
3424                 seq_printf(m, " %X:%u", i, v->max_dvc_qng[i]);
3425         }
3426 
3427         /* Indicate whether the device has returned queue full status. */
3428         seq_puts(m, "\n Command Queue Full:");
3429         for (i = 0; i <= ASC_MAX_TID; i++) {
3430                 if ((chip_scsi_id == i) ||
3431                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3432                         continue;
3433                 }
3434                 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i))
3435                         seq_printf(m, " %X:Y-%d",
3436                                    i, boardp->queue_full_cnt[i]);
3437                 else
3438                         seq_printf(m, " %X:N", i);
3439         }
3440 
3441         seq_puts(m, "\n Synchronous Transfer:");
3442         for (i = 0; i <= ASC_MAX_TID; i++) {
3443                 if ((chip_scsi_id == i) ||
3444                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3445                         continue;
3446                 }
3447                 seq_printf(m, " %X:%c",
3448                            i,
3449                            (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3450         }
3451         seq_putc(m, '\n');
3452 
3453         for (i = 0; i <= ASC_MAX_TID; i++) {
3454                 uchar syn_period_ix;
3455 
3456                 if ((chip_scsi_id == i) ||
3457                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3458                     ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3459                         continue;
3460                 }
3461 
3462                 seq_printf(m, "  %X:", i);
3463 
3464                 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
3465                         seq_puts(m, " Asynchronous");
3466                 } else {
3467                         syn_period_ix =
3468                             (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3469                                                            1);
3470 
3471                         seq_printf(m,
3472                                    " Transfer Period Factor: %d (%d.%d Mhz),",
3473                                    v->sdtr_period_tbl[syn_period_ix],
3474                                    250 / v->sdtr_period_tbl[syn_period_ix],
3475                                    ASC_TENTHS(250,
3476                                               v->sdtr_period_tbl[syn_period_ix]));
3477 
3478                         seq_printf(m, " REQ/ACK Offset: %d",
3479                                    boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET);
3480                 }
3481 
3482                 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3483                         seq_puts(m, "*\n");
3484                         renegotiate = 1;
3485                 } else {
3486                         seq_putc(m, '\n');
3487                 }
3488         }
3489 
3490         if (renegotiate) {
3491                 seq_puts(m, " * = Re-negotiation pending before next command.\n");
3492         }
3493 }
3494 
3495 /*
3496  * asc_prt_adv_board_info()
3497  *
3498  * Print dynamic board configuration information.
3499  */
3500 static void asc_prt_adv_board_info(struct seq_file *m, struct Scsi_Host *shost)
3501 {
3502         struct asc_board *boardp = shost_priv(shost);
3503         int i;
3504         ADV_DVC_VAR *v;
3505         ADV_DVC_CFG *c;
3506         AdvPortAddr iop_base;
3507         ushort chip_scsi_id;
3508         ushort lramword;
3509         uchar lrambyte;
3510         ushort tagqng_able;
3511         ushort sdtr_able, wdtr_able;
3512         ushort wdtr_done, sdtr_done;
3513         ushort period = 0;
3514         int renegotiate = 0;
3515 
3516         v = &boardp->dvc_var.adv_dvc_var;
3517         c = &boardp->dvc_cfg.adv_dvc_cfg;
3518         iop_base = v->iop_base;
3519         chip_scsi_id = v->chip_scsi_id;
3520 
3521         seq_printf(m,
3522                    "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3523                    shost->host_no);
3524 
3525         seq_printf(m,
3526                    " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
3527                    (unsigned long)v->iop_base,
3528                    AdvReadWordRegister(iop_base,IOPW_SCSI_CFG1) & CABLE_DETECT,
3529                    v->err_code);
3530 
3531         seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3532                    "mcode_version 0x%x\n", c->chip_version,
3533                    c->mcode_date, c->mcode_version);
3534 
3535         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
3536         seq_puts(m, " Queuing Enabled:");
3537         for (i = 0; i <= ADV_MAX_TID; i++) {
3538                 if ((chip_scsi_id == i) ||
3539                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3540                         continue;
3541                 }
3542 
3543                 seq_printf(m, " %X:%c",
3544                            i,
3545                            (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3546         }
3547 
3548         seq_puts(m, "\n Queue Limit:");
3549         for (i = 0; i <= ADV_MAX_TID; i++) {
3550                 if ((chip_scsi_id == i) ||
3551                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3552                         continue;
3553                 }
3554 
3555                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
3556                                 lrambyte);
3557 
3558                 seq_printf(m, " %X:%d", i, lrambyte);
3559         }
3560 
3561         seq_puts(m, "\n Command Pending:");
3562         for (i = 0; i <= ADV_MAX_TID; i++) {
3563                 if ((chip_scsi_id == i) ||
3564                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3565                         continue;
3566                 }
3567 
3568                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
3569                                 lrambyte);
3570 
3571                 seq_printf(m, " %X:%d", i, lrambyte);
3572         }
3573         seq_putc(m, '\n');
3574 
3575         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
3576         seq_puts(m, " Wide Enabled:");
3577         for (i = 0; i <= ADV_MAX_TID; i++) {
3578                 if ((chip_scsi_id == i) ||
3579                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3580                         continue;
3581                 }
3582 
3583                 seq_printf(m, " %X:%c",
3584                            i,
3585                            (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3586         }
3587         seq_putc(m, '\n');
3588 
3589         AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
3590         seq_puts(m, " Transfer Bit Width:");
3591         for (i = 0; i <= ADV_MAX_TID; i++) {
3592                 if ((chip_scsi_id == i) ||
3593                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3594                         continue;
3595                 }
3596 
3597                 AdvReadWordLram(iop_base,
3598                                 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3599                                 lramword);
3600 
3601                 seq_printf(m, " %X:%d",
3602                            i, (lramword & 0x8000) ? 16 : 8);
3603 
3604                 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
3605                     (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3606                         seq_putc(m, '*');
3607                         renegotiate = 1;
3608                 }
3609         }
3610         seq_putc(m, '\n');
3611 
3612         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
3613         seq_puts(m, " Synchronous Enabled:");
3614         for (i = 0; i <= ADV_MAX_TID; i++) {
3615                 if ((chip_scsi_id == i) ||
3616                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3617                         continue;
3618                 }
3619 
3620                 seq_printf(m, " %X:%c",
3621                            i,
3622                            (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3623         }
3624         seq_putc(m, '\n');
3625 
3626         AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
3627         for (i = 0; i <= ADV_MAX_TID; i++) {
3628 
3629                 AdvReadWordLram(iop_base,
3630                                 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3631                                 lramword);
3632                 lramword &= ~0x8000;
3633 
3634                 if ((chip_scsi_id == i) ||
3635                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3636                     ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
3637                         continue;
3638                 }
3639 
3640                 seq_printf(m, "  %X:", i);
3641 
3642                 if ((lramword & 0x1F) == 0) {   /* Check for REQ/ACK Offset 0. */
3643                         seq_puts(m, " Asynchronous");
3644                 } else {
3645                         seq_puts(m, " Transfer Period Factor: ");
3646 
3647                         if ((lramword & 0x1F00) == 0x1100) {    /* 80 Mhz */
3648                                 seq_puts(m, "9 (80.0 Mhz),");
3649                         } else if ((lramword & 0x1F00) == 0x1000) {     /* 40 Mhz */
3650                                 seq_puts(m, "10 (40.0 Mhz),");
3651                         } else {        /* 20 Mhz or below. */
3652 
3653                                 period = (((lramword >> 8) * 25) + 50) / 4;
3654 
3655                                 if (period == 0) {      /* Should never happen. */
3656                                         seq_printf(m, "%d (? Mhz), ", period);
3657                                 } else {
3658                                         seq_printf(m,
3659                                                    "%d (%d.%d Mhz),",
3660                                                    period, 250 / period,
3661                                                    ASC_TENTHS(250, period));
3662                                 }
3663                         }
3664 
3665                         seq_printf(m, " REQ/ACK Offset: %d",
3666                                    lramword & 0x1F);
3667                 }
3668 
3669                 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3670                         seq_puts(m, "*\n");
3671                         renegotiate = 1;
3672                 } else {
3673                         seq_putc(m, '\n');
3674                 }
3675         }
3676 
3677         if (renegotiate) {
3678                 seq_puts(m, " * = Re-negotiation pending before next command.\n");
3679         }
3680 }
3681 
3682 #ifdef ADVANSYS_STATS
3683 /*
3684  * asc_prt_board_stats()
3685  */
3686 static void asc_prt_board_stats(struct seq_file *m, struct Scsi_Host *shost)
3687 {
3688         struct asc_board *boardp = shost_priv(shost);
3689         struct asc_stats *s = &boardp->asc_stats;
3690 
3691         seq_printf(m,
3692                    "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
3693                    shost->host_no);
3694 
3695         seq_printf(m,
3696                    " queuecommand %u, reset %u, biosparam %u, interrupt %u\n",
3697                    s->queuecommand, s->reset, s->biosparam,
3698                    s->interrupt);
3699 
3700         seq_printf(m,
3701                    " callback %u, done %u, build_error %u, build_noreq %u, build_nosg %u\n",
3702                    s->callback, s->done, s->build_error,
3703                    s->adv_build_noreq, s->adv_build_nosg);
3704 
3705         seq_printf(m,
3706                    " exe_noerror %u, exe_busy %u, exe_error %u, exe_unknown %u\n",
3707                    s->exe_noerror, s->exe_busy, s->exe_error,
3708                    s->exe_unknown);
3709 
3710         /*
3711          * Display data transfer statistics.
3712          */
3713         if (s->xfer_cnt > 0) {
3714                 seq_printf(m, " xfer_cnt %u, xfer_elem %u, ",
3715                            s->xfer_cnt, s->xfer_elem);
3716 
3717                 seq_printf(m, "xfer_bytes %u.%01u kb\n",
3718                            s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2));
3719 
3720                 /* Scatter gather transfer statistics */
3721                 seq_printf(m, " avg_num_elem %u.%01u, ",
3722                            s->xfer_elem / s->xfer_cnt,
3723                            ASC_TENTHS(s->xfer_elem, s->xfer_cnt));
3724 
3725                 seq_printf(m, "avg_elem_size %u.%01u kb, ",
3726                            (s->xfer_sect / 2) / s->xfer_elem,
3727                            ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem));
3728 
3729                 seq_printf(m, "avg_xfer_size %u.%01u kb\n",
3730                            (s->xfer_sect / 2) / s->xfer_cnt,
3731                            ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt));
3732         }
3733 }
3734 #endif /* ADVANSYS_STATS */
3735 
3736 /*
3737  * advansys_show_info() - /proc/scsi/advansys/{0,1,2,3,...}
3738  *
3739  * m: seq_file to print into
3740  * shost: Scsi_Host
3741  *
3742  * Return the number of bytes read from or written to a
3743  * /proc/scsi/advansys/[0...] file.
3744  */
3745 static int
3746 advansys_show_info(struct seq_file *m, struct Scsi_Host *shost)
3747 {
3748         struct asc_board *boardp = shost_priv(shost);
3749 
3750         ASC_DBG(1, "begin\n");
3751 
3752         /*
3753          * User read of /proc/scsi/advansys/[0...] file.
3754          */
3755 
3756         /*
3757          * Get board configuration information.
3758          *
3759          * advansys_info() returns the board string from its own static buffer.
3760          */
3761         /* Copy board information. */
3762         seq_printf(m, "%s\n", (char *)advansys_info(shost));
3763         /*
3764          * Display Wide Board BIOS Information.
3765          */
3766         if (!ASC_NARROW_BOARD(boardp))
3767                 asc_prt_adv_bios(m, shost);
3768 
3769         /*
3770          * Display driver information for each device attached to the board.
3771          */
3772         asc_prt_board_devices(m, shost);
3773 
3774         /*
3775          * Display EEPROM configuration for the board.
3776          */
3777         if (ASC_NARROW_BOARD(boardp))
3778                 asc_prt_asc_board_eeprom(m, shost);
3779         else
3780                 asc_prt_adv_board_eeprom(m, shost);
3781 
3782         /*
3783          * Display driver configuration and information for the board.
3784          */
3785         asc_prt_driver_conf(m, shost);
3786 
3787 #ifdef ADVANSYS_STATS
3788         /*
3789          * Display driver statistics for the board.
3790          */
3791         asc_prt_board_stats(m, shost);
3792 #endif /* ADVANSYS_STATS */
3793 
3794         /*
3795          * Display Asc Library dynamic configuration information
3796          * for the board.
3797          */
3798         if (ASC_NARROW_BOARD(boardp))
3799                 asc_prt_asc_board_info(m, shost);
3800         else
3801                 asc_prt_adv_board_info(m, shost);
3802         return 0;
3803 }
3804 #endif /* CONFIG_PROC_FS */
3805 
3806 static void asc_scsi_done(struct scsi_cmnd *scp)
3807 {
3808         scsi_dma_unmap(scp);
3809         ASC_STATS(scp->device->host, done);
3810         scp->scsi_done(scp);
3811 }
3812 
3813 static void AscSetBank(PortAddr iop_base, uchar bank)
3814 {
3815         uchar val;
3816 
3817         val = AscGetChipControl(iop_base) &
3818             (~
3819              (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
3820               CC_CHIP_RESET));
3821         if (bank == 1) {
3822                 val |= CC_BANK_ONE;
3823         } else if (bank == 2) {
3824                 val |= CC_DIAG | CC_BANK_ONE;
3825         } else {
3826                 val &= ~CC_BANK_ONE;
3827         }
3828         AscSetChipControl(iop_base, val);
3829 }
3830 
3831 static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
3832 {
3833         AscSetBank(iop_base, 1);
3834         AscWriteChipIH(iop_base, ins_code);
3835         AscSetBank(iop_base, 0);
3836 }
3837 
3838 static int AscStartChip(PortAddr iop_base)
3839 {
3840         AscSetChipControl(iop_base, 0);
3841         if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3842                 return (0);
3843         }
3844         return (1);
3845 }
3846 
3847 static int AscStopChip(PortAddr iop_base)
3848 {
3849         uchar cc_val;
3850 
3851         cc_val =
3852             AscGetChipControl(iop_base) &
3853             (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
3854         AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
3855         AscSetChipIH(iop_base, INS_HALT);
3856         AscSetChipIH(iop_base, INS_RFLAG_WTM);
3857         if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
3858                 return (0);
3859         }
3860         return (1);
3861 }
3862 
3863 static int AscIsChipHalted(PortAddr iop_base)
3864 {
3865         if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3866                 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
3867                         return (1);
3868                 }
3869         }
3870         return (0);
3871 }
3872 
3873 static int AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
3874 {
3875         PortAddr iop_base;
3876         int i = 10;
3877 
3878         iop_base = asc_dvc->iop_base;
3879         while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
3880                && (i-- > 0)) {
3881                 mdelay(100);
3882         }
3883         AscStopChip(iop_base);
3884         AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
3885         udelay(60);
3886         AscSetChipIH(iop_base, INS_RFLAG_WTM);
3887         AscSetChipIH(iop_base, INS_HALT);
3888         AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
3889         AscSetChipControl(iop_base, CC_HALT);
3890         mdelay(200);
3891         AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
3892         AscSetChipStatus(iop_base, 0);
3893         return (AscIsChipHalted(iop_base));
3894 }
3895 
3896 static int AscFindSignature(PortAddr iop_base)
3897 {
3898         ushort sig_word;
3899 
3900         ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
3901                  iop_base, AscGetChipSignatureByte(iop_base));
3902         if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
3903                 ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
3904                          iop_base, AscGetChipSignatureWord(iop_base));
3905                 sig_word = AscGetChipSignatureWord(iop_base);
3906                 if ((sig_word == (ushort)ASC_1000_ID0W) ||
3907                     (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
3908                         return (1);
3909                 }
3910         }
3911         return (0);
3912 }
3913 
3914 static void AscEnableInterrupt(PortAddr iop_base)
3915 {
3916         ushort cfg;
3917 
3918         cfg = AscGetChipCfgLsw(iop_base);
3919         AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
3920 }
3921 
3922 static void AscDisableInterrupt(PortAddr iop_base)
3923 {
3924         ushort cfg;
3925 
3926         cfg = AscGetChipCfgLsw(iop_base);
3927         AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
3928 }
3929 
3930 static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
3931 {
3932         unsigned char byte_data;
3933         unsigned short word_data;
3934 
3935         if (isodd_word(addr)) {
3936                 AscSetChipLramAddr(iop_base, addr - 1);
3937                 word_data = AscGetChipLramData(iop_base);
3938                 byte_data = (word_data >> 8) & 0xFF;
3939         } else {
3940                 AscSetChipLramAddr(iop_base, addr);
3941                 word_data = AscGetChipLramData(iop_base);
3942                 byte_data = word_data & 0xFF;
3943         }
3944         return byte_data;
3945 }
3946 
3947 static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
3948 {
3949         ushort word_data;
3950 
3951         AscSetChipLramAddr(iop_base, addr);
3952         word_data = AscGetChipLramData(iop_base);
3953         return (word_data);
3954 }
3955 
3956 #if CC_VERY_LONG_SG_LIST
3957 static ASC_DCNT AscReadLramDWord(PortAddr iop_base, ushort addr)
3958 {
3959         ushort val_low, val_high;
3960         ASC_DCNT dword_data;
3961 
3962         AscSetChipLramAddr(iop_base, addr);
3963         val_low = AscGetChipLramData(iop_base);
3964         val_high = AscGetChipLramData(iop_base);
3965         dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
3966         return (dword_data);
3967 }
3968 #endif /* CC_VERY_LONG_SG_LIST */
3969 
3970 static void
3971 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
3972 {
3973         int i;
3974 
3975         AscSetChipLramAddr(iop_base, s_addr);
3976         for (i = 0; i < words; i++) {
3977                 AscSetChipLramData(iop_base, set_wval);
3978         }
3979 }
3980 
3981 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
3982 {
3983         AscSetChipLramAddr(iop_base, addr);
3984         AscSetChipLramData(iop_base, word_val);
3985 }
3986 
3987 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
3988 {
3989         ushort word_data;
3990 
3991         if (isodd_word(addr)) {
3992                 addr--;
3993                 word_data = AscReadLramWord(iop_base, addr);
3994                 word_data &= 0x00FF;
3995                 word_data |= (((ushort)byte_val << 8) & 0xFF00);
3996         } else {
3997                 word_data = AscReadLramWord(iop_base, addr);
3998                 word_data &= 0xFF00;
3999                 word_data |= ((ushort)byte_val & 0x00FF);
4000         }
4001         AscWriteLramWord(iop_base, addr, word_data);
4002 }
4003 
4004 /*
4005  * Copy 2 bytes to LRAM.
4006  *
4007  * The source data is assumed to be in little-endian order in memory
4008  * and is maintained in little-endian order when written to LRAM.
4009  */
4010 static void
4011 AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr,
4012                         const uchar *s_buffer, int words)
4013 {
4014         int i;
4015 
4016         AscSetChipLramAddr(iop_base, s_addr);
4017         for (i = 0; i < 2 * words; i += 2) {
4018                 /*
4019                  * On a little-endian system the second argument below
4020                  * produces a little-endian ushort which is written to
4021                  * LRAM in little-endian order. On a big-endian system
4022                  * the second argument produces a big-endian ushort which
4023                  * is "transparently" byte-swapped by outpw() and written
4024                  * in little-endian order to LRAM.
4025                  */
4026                 outpw(iop_base + IOP_RAM_DATA,
4027                       ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
4028         }
4029 }
4030 
4031 /*
4032  * Copy 4 bytes to LRAM.
4033  *
4034  * The source data is assumed to be in little-endian order in memory
4035  * and is maintained in little-endian order when written to LRAM.
4036  */
4037 static void
4038 AscMemDWordCopyPtrToLram(PortAddr iop_base,
4039                          ushort s_addr, uchar *s_buffer, int dwords)
4040 {
4041         int i;
4042 
4043         AscSetChipLramAddr(iop_base, s_addr);
4044         for (i = 0; i < 4 * dwords; i += 4) {
4045                 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);   /* LSW */
4046                 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]);       /* MSW */
4047         }
4048 }
4049 
4050 /*
4051  * Copy 2 bytes from LRAM.
4052  *
4053  * The source data is assumed to be in little-endian order in LRAM
4054  * and is maintained in little-endian order when written to memory.
4055  */
4056 static void
4057 AscMemWordCopyPtrFromLram(PortAddr iop_base,
4058                           ushort s_addr, uchar *d_buffer, int words)
4059 {
4060         int i;
4061         ushort word;
4062 
4063         AscSetChipLramAddr(iop_base, s_addr);
4064         for (i = 0; i < 2 * words; i += 2) {
4065                 word = inpw(iop_base + IOP_RAM_DATA);
4066                 d_buffer[i] = word & 0xff;
4067                 d_buffer[i + 1] = (word >> 8) & 0xff;
4068         }
4069 }
4070 
4071 static ASC_DCNT AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
4072 {
4073         ASC_DCNT sum;
4074         int i;
4075 
4076         sum = 0L;
4077         for (i = 0; i < words; i++, s_addr += 2) {
4078                 sum += AscReadLramWord(iop_base, s_addr);
4079         }
4080         return (sum);
4081 }
4082 
4083 static ushort AscInitLram(ASC_DVC_VAR *asc_dvc)
4084 {
4085         uchar i;
4086         ushort s_addr;
4087         PortAddr iop_base;
4088         ushort warn_code;
4089 
4090         iop_base = asc_dvc->iop_base;
4091         warn_code = 0;
4092         AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
4093                           (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
4094                                     64) >> 1));
4095         i = ASC_MIN_ACTIVE_QNO;
4096         s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
4097         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4098                          (uchar)(i + 1));
4099         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4100                          (uchar)(asc_dvc->max_total_qng));
4101         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4102                          (uchar)i);
4103         i++;
4104         s_addr += ASC_QBLK_SIZE;
4105         for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
4106                 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4107                                  (uchar)(i + 1));
4108                 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4109                                  (uchar)(i - 1));
4110                 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4111                                  (uchar)i);
4112         }
4113         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4114                          (uchar)ASC_QLINK_END);
4115         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4116                          (uchar)(asc_dvc->max_total_qng - 1));
4117         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4118                          (uchar)asc_dvc->max_total_qng);
4119         i++;
4120         s_addr += ASC_QBLK_SIZE;
4121         for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
4122              i++, s_addr += ASC_QBLK_SIZE) {
4123                 AscWriteLramByte(iop_base,
4124                                  (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
4125                 AscWriteLramByte(iop_base,
4126                                  (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
4127                 AscWriteLramByte(iop_base,
4128                                  (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
4129         }
4130         return warn_code;
4131 }
4132 
4133 static ASC_DCNT
4134 AscLoadMicroCode(PortAddr iop_base, ushort s_addr,
4135                  const uchar *mcode_buf, ushort mcode_size)
4136 {
4137         ASC_DCNT chksum;
4138         ushort mcode_word_size;
4139         ushort mcode_chksum;
4140 
4141         /* Write the microcode buffer starting at LRAM address 0. */
4142         mcode_word_size = (ushort)(mcode_size >> 1);
4143         AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
4144         AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
4145 
4146         chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
4147         ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum);
4148         mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
4149                                                  (ushort)ASC_CODE_SEC_BEG,
4150                                                  (ushort)((mcode_size -
4151                                                            s_addr - (ushort)
4152                                                            ASC_CODE_SEC_BEG) /
4153                                                           2));
4154         ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum);
4155         AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
4156         AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
4157         return chksum;
4158 }
4159 
4160 static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
4161 {
4162         PortAddr iop_base;
4163         int i;
4164         ushort lram_addr;
4165 
4166         iop_base = asc_dvc->iop_base;
4167         AscPutRiscVarFreeQHead(iop_base, 1);
4168         AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4169         AscPutVarFreeQHead(iop_base, 1);
4170         AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4171         AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
4172                          (uchar)((int)asc_dvc->max_total_qng + 1));
4173         AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
4174                          (uchar)((int)asc_dvc->max_total_qng + 2));
4175         AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
4176                          asc_dvc->max_total_qng);
4177         AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
4178         AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
4179         AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
4180         AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
4181         AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
4182         AscPutQDoneInProgress(iop_base, 0);
4183         lram_addr = ASC_QADR_BEG;
4184         for (i = 0; i < 32; i++, lram_addr += 2) {
4185                 AscWriteLramWord(iop_base, lram_addr, 0);
4186         }
4187 }
4188 
4189 static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
4190 {
4191         int i;
4192         ushort warn_code;
4193         PortAddr iop_base;
4194         ASC_PADDR phy_addr;
4195         ASC_DCNT phy_size;
4196         struct asc_board *board = asc_dvc_to_board(asc_dvc);
4197 
4198         iop_base = asc_dvc->iop_base;
4199         warn_code = 0;
4200         for (i = 0; i <= ASC_MAX_TID; i++) {
4201                 AscPutMCodeInitSDTRAtID(iop_base, i,
4202                                         asc_dvc->cfg->sdtr_period_offset[i]);
4203         }
4204 
4205         AscInitQLinkVar(asc_dvc);
4206         AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
4207                          asc_dvc->cfg->disc_enable);
4208         AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
4209                          ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
4210 
4211         /* Ensure overrun buffer is aligned on an 8 byte boundary. */
4212         BUG_ON((unsigned long)asc_dvc->overrun_buf & 7);
4213         asc_dvc->overrun_dma = dma_map_single(board->dev, asc_dvc->overrun_buf,
4214                                         ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4215         if (dma_mapping_error(board->dev, asc_dvc->overrun_dma)) {
4216                 warn_code = -ENOMEM;
4217                 goto err_dma_map;
4218         }
4219         phy_addr = cpu_to_le32(asc_dvc->overrun_dma);
4220         AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
4221                                  (uchar *)&phy_addr, 1);
4222         phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE);
4223         AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
4224                                  (uchar *)&phy_size, 1);
4225 
4226         asc_dvc->cfg->mcode_date =
4227             AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
4228         asc_dvc->cfg->mcode_version =
4229             AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
4230 
4231         AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
4232         if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
4233                 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
4234                 warn_code = UW_ERR;
4235                 goto err_mcode_start;
4236         }
4237         if (AscStartChip(iop_base) != 1) {
4238                 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
4239                 warn_code = UW_ERR;
4240                 goto err_mcode_start;
4241         }
4242 
4243         return warn_code;
4244 
4245 err_mcode_start:
4246         dma_unmap_single(board->dev, asc_dvc->overrun_dma,
4247                          ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4248 err_dma_map:
4249         asc_dvc->overrun_dma = 0;
4250         return warn_code;
4251 }
4252 
4253 static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
4254 {
4255         const struct firmware *fw;
4256         const char fwname[] = "advansys/mcode.bin";
4257         int err;
4258         unsigned long chksum;
4259         ushort warn_code;
4260         PortAddr iop_base;
4261 
4262         iop_base = asc_dvc->iop_base;
4263         warn_code = 0;
4264         if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
4265             !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
4266                 AscResetChipAndScsiBus(asc_dvc);
4267                 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4268         }
4269         asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
4270         if (asc_dvc->err_code != 0)
4271                 return UW_ERR;
4272         if (!AscFindSignature(asc_dvc->iop_base)) {
4273                 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
4274                 return warn_code;
4275         }
4276         AscDisableInterrupt(iop_base);
4277         warn_code |= AscInitLram(asc_dvc);
4278         if (asc_dvc->err_code != 0)
4279                 return UW_ERR;
4280 
4281         err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4282         if (err) {
4283                 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4284                        fwname, err);
4285                 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4286                 return err;
4287         }
4288         if (fw->size < 4) {
4289                 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4290                        fw->size, fwname);
4291                 release_firmware(fw);
4292                 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4293                 return -EINVAL;
4294         }
4295         chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4296                  (fw->data[1] << 8) | fw->data[0];
4297         ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)chksum);
4298         if (AscLoadMicroCode(iop_base, 0, &fw->data[4],
4299                              fw->size - 4) != chksum) {
4300                 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4301                 release_firmware(fw);
4302                 return warn_code;
4303         }
4304         release_firmware(fw);
4305         warn_code |= AscInitMicroCodeVar(asc_dvc);
4306         if (!asc_dvc->overrun_dma)
4307                 return warn_code;
4308         asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
4309         AscEnableInterrupt(iop_base);
4310         return warn_code;
4311 }
4312 
4313 /*
4314  * Load the Microcode
4315  *
4316  * Write the microcode image to RISC memory starting at address 0.
4317  *
4318  * The microcode is stored compressed in the following format:
4319  *
4320  *  254 word (508 byte) table indexed by byte code followed
4321  *  by the following byte codes:
4322  *
4323  *    1-Byte Code:
4324  *      00: Emit word 0 in table.
4325  *      01: Emit word 1 in table.
4326  *      .
4327  *      FD: Emit word 253 in table.
4328  *
4329  *    Multi-Byte Code:
4330  *      FE WW WW: (3 byte code) Word to emit is the next word WW WW.
4331  *      FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
4332  *
4333  * Returns 0 or an error if the checksum doesn't match
4334  */
4335 static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf,
4336                             int size, int memsize, int chksum)
4337 {
4338         int i, j, end, len = 0;
4339         ADV_DCNT sum;
4340 
4341         AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4342 
4343         for (i = 253 * 2; i < size; i++) {
4344                 if (buf[i] == 0xff) {
4345                         unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
4346                         for (j = 0; j < buf[i + 1]; j++) {
4347                                 AdvWriteWordAutoIncLram(iop_base, word);
4348                                 len += 2;
4349                         }
4350                         i += 3;
4351                 } else if (buf[i] == 0xfe) {
4352                         unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
4353                         AdvWriteWordAutoIncLram(iop_base, word);
4354                         i += 2;
4355                         len += 2;
4356                 } else {
4357                         unsigned int off = buf[i] * 2;
4358                         unsigned short word = (buf[off + 1] << 8) | buf[off];
4359                         AdvWriteWordAutoIncLram(iop_base, word);
4360                         len += 2;
4361                 }
4362         }
4363 
4364         end = len;
4365 
4366         while (len < memsize) {
4367                 AdvWriteWordAutoIncLram(iop_base, 0);
4368                 len += 2;
4369         }
4370 
4371         /* Verify the microcode checksum. */
4372         sum = 0;
4373         AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4374 
4375         for (len = 0; len < end; len += 2) {
4376                 sum += AdvReadWordAutoIncLram(iop_base);
4377         }
4378 
4379         if (sum != chksum)
4380                 return ASC_IERR_MCODE_CHKSUM;
4381 
4382         return 0;
4383 }
4384 
4385 static void AdvBuildCarrierFreelist(struct adv_dvc_var *asc_dvc)
4386 {
4387         ADV_CARR_T *carrp;
4388         ADV_SDCNT buf_size;
4389         ADV_PADDR carr_paddr;
4390 
4391         carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
4392         asc_dvc->carr_freelist = NULL;
4393         if (carrp == asc_dvc->carrier_buf) {
4394                 buf_size = ADV_CARRIER_BUFSIZE;
4395         } else {
4396                 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
4397         }
4398 
4399         do {
4400                 /* Get physical address of the carrier 'carrp'. */
4401                 carr_paddr = cpu_to_le32(virt_to_bus(carrp));
4402 
4403                 buf_size -= sizeof(ADV_CARR_T);
4404 
4405                 carrp->carr_pa = carr_paddr;
4406                 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
4407 
4408                 /*
4409                  * Insert the carrier at the beginning of the freelist.
4410                  */
4411                 carrp->next_vpa =
4412                         cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
4413                 asc_dvc->carr_freelist = carrp;
4414 
4415                 carrp++;
4416         } while (buf_size > 0);
4417 }
4418 
4419 /*
4420  * Send an idle command to the chip and wait for completion.
4421  *
4422  * Command completion is polled for once per microsecond.
4423  *
4424  * The function can be called from anywhere including an interrupt handler.
4425  * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
4426  * functions to prevent reentrancy.
4427  *
4428  * Return Values:
4429  *   ADV_TRUE - command completed successfully
4430  *   ADV_FALSE - command failed
4431  *   ADV_ERROR - command timed out
4432  */
4433 static int
4434 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
4435                ushort idle_cmd, ADV_DCNT idle_cmd_parameter)
4436 {
4437         int result;
4438         ADV_DCNT i, j;
4439         AdvPortAddr iop_base;
4440 
4441         iop_base = asc_dvc->iop_base;
4442 
4443         /*
4444          * Clear the idle command status which is set by the microcode
4445          * to a non-zero value to indicate when the command is completed.
4446          * The non-zero result is one of the IDLE_CMD_STATUS_* values
4447          */
4448         AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
4449 
4450         /*
4451          * Write the idle command value after the idle command parameter
4452          * has been written to avoid a race condition. If the order is not
4453          * followed, the microcode may process the idle command before the
4454          * parameters have been written to LRAM.
4455          */
4456         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
4457                                 cpu_to_le32(idle_cmd_parameter));
4458         AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
4459 
4460         /*
4461          * Tickle the RISC to tell it to process the idle command.
4462          */
4463         AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
4464         if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
4465                 /*
4466                  * Clear the tickle value. In the ASC-3550 the RISC flag
4467                  * command 'clr_tickle_b' does not work unless the host
4468                  * value is cleared.
4469                  */
4470                 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
4471         }
4472 
4473         /* Wait for up to 100 millisecond for the idle command to timeout. */
4474         for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
4475                 /* Poll once each microsecond for command completion. */
4476                 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
4477                         AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
4478                                         result);
4479                         if (result != 0)
4480                                 return result;
4481                         udelay(1);
4482                 }
4483         }
4484 
4485         BUG();          /* The idle command should never timeout. */
4486         return ADV_ERROR;
4487 }
4488 
4489 /*
4490  * Reset SCSI Bus and purge all outstanding requests.
4491  *
4492  * Return Value:
4493  *      ADV_TRUE(1) -   All requests are purged and SCSI Bus is reset.
4494  *      ADV_FALSE(0) -  Microcode command failed.
4495  *      ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
4496  *                      may be hung which requires driver recovery.
4497  */
4498 static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
4499 {
4500         int status;
4501 
4502         /*
4503          * Send the SCSI Bus Reset idle start idle command which asserts
4504          * the SCSI Bus Reset signal.
4505          */
4506         status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
4507         if (status != ADV_TRUE) {
4508                 return status;
4509         }
4510 
4511         /*
4512          * Delay for the specified SCSI Bus Reset hold time.
4513          *
4514          * The hold time delay is done on the host because the RISC has no
4515          * microsecond accurate timer.
4516          */
4517         udelay(ASC_SCSI_RESET_HOLD_TIME_US);
4518 
4519         /*
4520          * Send the SCSI Bus Reset end idle command which de-asserts
4521          * the SCSI Bus Reset signal and purges any pending requests.
4522          */
4523         status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
4524         if (status != ADV_TRUE) {
4525                 return status;
4526         }
4527 
4528         mdelay(asc_dvc->scsi_reset_wait * 1000);        /* XXX: msleep? */
4529 
4530         return status;
4531 }
4532 
4533 /*
4534  * Initialize the ASC-3550.
4535  *
4536  * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4537  *
4538  * For a non-fatal error return a warning code. If there are no warnings
4539  * then 0 is returned.
4540  *
4541  * Needed after initialization for error recovery.
4542  */
4543 static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
4544 {
4545         const struct firmware *fw;
4546         const char fwname[] = "advansys/3550.bin";
4547         AdvPortAddr iop_base;
4548         ushort warn_code;
4549         int begin_addr;
4550         int end_addr;
4551         ushort code_sum;
4552         int word;
4553         int i;
4554         int err;
4555         unsigned long chksum;
4556         ushort scsi_cfg1;
4557         uchar tid;
4558         ushort bios_mem[ASC_MC_BIOSLEN / 2];    /* BIOS RISC Memory 0x40-0x8F. */
4559         ushort wdtr_able = 0, sdtr_able, tagqng_able;
4560         uchar max_cmd[ADV_MAX_TID + 1];
4561 
4562         /* If there is already an error, don't continue. */
4563         if (asc_dvc->err_code != 0)
4564                 return ADV_ERROR;
4565 
4566         /*
4567          * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
4568          */
4569         if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
4570                 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4571                 return ADV_ERROR;
4572         }
4573 
4574         warn_code = 0;
4575         iop_base = asc_dvc->iop_base;
4576 
4577         /*
4578          * Save the RISC memory BIOS region before writing the microcode.
4579          * The BIOS may already be loaded and using its RISC LRAM region
4580          * so its region must be saved and restored.
4581          *
4582          * Note: This code makes the assumption, which is currently true,
4583          * that a chip reset does not clear RISC LRAM.
4584          */
4585         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4586                 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4587                                 bios_mem[i]);
4588         }
4589 
4590         /*
4591          * Save current per TID negotiated values.
4592          */
4593         if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
4594                 ushort bios_version, major, minor;
4595 
4596                 bios_version =
4597                     bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
4598                 major = (bios_version >> 12) & 0xF;
4599                 minor = (bios_version >> 8) & 0xF;
4600                 if (major < 3 || (major == 3 && minor == 1)) {
4601                         /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
4602                         AdvReadWordLram(iop_base, 0x120, wdtr_able);
4603                 } else {
4604                         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4605                 }
4606         }
4607         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4608         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4609         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4610                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4611                                 max_cmd[tid]);
4612         }
4613 
4614         err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4615         if (err) {
4616                 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4617                        fwname, err);
4618                 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4619                 return err;
4620         }
4621         if (fw->size < 4) {
4622                 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4623                        fw->size, fwname);
4624                 release_firmware(fw);
4625                 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4626                 return -EINVAL;
4627         }
4628         chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4629                  (fw->data[1] << 8) | fw->data[0];
4630         asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
4631                                              fw->size - 4, ADV_3550_MEMSIZE,
4632                                              chksum);
4633         release_firmware(fw);
4634         if (asc_dvc->err_code)
4635                 return ADV_ERROR;
4636 
4637         /*
4638          * Restore the RISC memory BIOS region.
4639          */
4640         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4641                 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4642                                  bios_mem[i]);
4643         }
4644 
4645         /*
4646          * Calculate and write the microcode code checksum to the microcode
4647          * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
4648          */
4649         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
4650         AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
4651         code_sum = 0;
4652         AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
4653         for (word = begin_addr; word < end_addr; word += 2) {
4654                 code_sum += AdvReadWordAutoIncLram(iop_base);
4655         }
4656         AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
4657 
4658         /*
4659          * Read and save microcode version and date.
4660          */
4661         AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
4662                         asc_dvc->cfg->mcode_date);
4663         AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
4664                         asc_dvc->cfg->mcode_version);
4665 
4666         /*
4667          * Set the chip type to indicate the ASC3550.
4668          */
4669         AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
4670 
4671         /*
4672          * If the PCI Configuration Command Register "Parity Error Response
4673          * Control" Bit was clear (0), then set the microcode variable
4674          * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
4675          * to ignore DMA parity errors.
4676          */
4677         if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
4678                 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4679                 word |= CONTROL_FLAG_IGNORE_PERR;
4680                 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4681         }
4682 
4683         /*
4684          * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
4685          * threshold of 128 bytes. This register is only accessible to the host.
4686          */
4687         AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
4688                              START_CTL_EMFU | READ_CMD_MRM);
4689 
4690         /*
4691          * Microcode operating variables for WDTR, SDTR, and command tag
4692          * queuing will be set in slave_configure() based on what a
4693          * device reports it is capable of in Inquiry byte 7.
4694          *
4695          * If SCSI Bus Resets have been disabled, then directly set
4696          * SDTR and WDTR from the EEPROM configuration. This will allow
4697          * the BIOS and warm boot to work without a SCSI bus hang on
4698          * the Inquiry caused by host and target mismatched DTR values.
4699          * Without the SCSI Bus Reset, before an Inquiry a device can't
4700          * be assumed to be in Asynchronous, Narrow mode.
4701          */
4702         if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
4703                 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
4704                                  asc_dvc->wdtr_able);
4705                 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
4706                                  asc_dvc->sdtr_able);
4707         }
4708 
4709         /*
4710          * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
4711          * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
4712          * bitmask. These values determine the maximum SDTR speed negotiated
4713          * with a device.
4714          *
4715          * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
4716          * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
4717          * without determining here whether the device supports SDTR.
4718          *
4719          * 4-bit speed  SDTR speed name
4720          * ===========  ===============
4721          * 0000b (0x0)  SDTR disabled
4722          * 0001b (0x1)  5 Mhz
4723          * 0010b (0x2)  10 Mhz
4724          * 0011b (0x3)  20 Mhz (Ultra)
4725          * 0100b (0x4)  40 Mhz (LVD/Ultra2)
4726          * 0101b (0x5)  80 Mhz (LVD2/Ultra3)
4727          * 0110b (0x6)  Undefined
4728          * .
4729          * 1111b (0xF)  Undefined
4730          */
4731         word = 0;
4732         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4733                 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
4734                         /* Set Ultra speed for TID 'tid'. */
4735                         word |= (0x3 << (4 * (tid % 4)));
4736                 } else {
4737                         /* Set Fast speed for TID 'tid'. */
4738                         word |= (0x2 << (4 * (tid % 4)));
4739                 }
4740                 if (tid == 3) { /* Check if done with sdtr_speed1. */
4741                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
4742                         word = 0;
4743                 } else if (tid == 7) {  /* Check if done with sdtr_speed2. */
4744                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
4745                         word = 0;
4746                 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
4747                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
4748                         word = 0;
4749                 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
4750                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
4751                         /* End of loop. */
4752                 }
4753         }
4754 
4755         /*
4756          * Set microcode operating variable for the disconnect per TID bitmask.
4757          */
4758         AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
4759                          asc_dvc->cfg->disc_enable);
4760 
4761         /*
4762          * Set SCSI_CFG0 Microcode Default Value.
4763          *
4764          * The microcode will set the SCSI_CFG0 register using this value
4765          * after it is started below.
4766          */
4767         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
4768                          PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
4769                          asc_dvc->chip_scsi_id);
4770 
4771         /*
4772          * Determine SCSI_CFG1 Microcode Default Value.
4773          *
4774          * The microcode will set the SCSI_CFG1 register using this value
4775          * after it is started below.
4776          */
4777 
4778         /* Read current SCSI_CFG1 Register value. */
4779         scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
4780 
4781         /*
4782          * If all three connectors are in use, return an error.
4783          */
4784         if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
4785             (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
4786                 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
4787                 return ADV_ERROR;
4788         }
4789 
4790         /*
4791          * If the internal narrow cable is reversed all of the SCSI_CTRL
4792          * register signals will be set. Check for and return an error if
4793          * this condition is found.
4794          */
4795         if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
4796                 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
4797                 return ADV_ERROR;
4798         }
4799 
4800         /*
4801          * If this is a differential board and a single-ended device
4802          * is attached to one of the connectors, return an error.
4803          */
4804         if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
4805                 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
4806                 return ADV_ERROR;
4807         }
4808 
4809         /*
4810          * If automatic termination control is enabled, then set the
4811          * termination value based on a table listed in a_condor.h.
4812          *
4813          * If manual termination was specified with an EEPROM setting
4814          * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
4815          * is ready to be 'ored' into SCSI_CFG1.
4816          */
4817         if (asc_dvc->cfg->termination == 0) {
4818                 /*
4819                  * The software always controls termination by setting TERM_CTL_SEL.
4820                  * If TERM_CTL_SEL were set to 0, the hardware would set termination.
4821                  */
4822                 asc_dvc->cfg->termination |= TERM_CTL_SEL;
4823 
4824                 switch (scsi_cfg1 & CABLE_DETECT) {
4825                         /* TERM_CTL_H: on, TERM_CTL_L: on */
4826                 case 0x3:
4827                 case 0x7:
4828                 case 0xB:
4829                 case 0xD:
4830                 case 0xE:
4831                 case 0xF:
4832                         asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
4833                         break;
4834 
4835                         /* TERM_CTL_H: on, TERM_CTL_L: off */
4836                 case 0x1:
4837                 case 0x5:
4838                 case 0x9:
4839                 case 0xA:
4840                 case 0xC:
4841                         asc_dvc->cfg->termination |= TERM_CTL_H;
4842                         break;
4843 
4844                         /* TERM_CTL_H: off, TERM_CTL_L: off */
4845                 case 0x2:
4846                 case 0x6:
4847                         break;
4848                 }
4849         }
4850 
4851         /*
4852          * Clear any set TERM_CTL_H and TERM_CTL_L bits.
4853          */
4854         scsi_cfg1 &= ~TERM_CTL;
4855 
4856         /*
4857          * Invert the TERM_CTL_H and TERM_CTL_L bits and then
4858          * set 'scsi_cfg1'. The TERM_POL bit does not need to be
4859          * referenced, because the hardware internally inverts
4860          * the Termination High and Low bits if TERM_POL is set.
4861          */
4862         scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
4863 
4864         /*
4865          * Set SCSI_CFG1 Microcode Default Value
4866          *
4867          * Set filter value and possibly modified termination control
4868          * bits in the Microcode SCSI_CFG1 Register Value.
4869          *
4870          * The microcode will set the SCSI_CFG1 register using this value
4871          * after it is started below.
4872          */
4873         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
4874                          FLTR_DISABLE | scsi_cfg1);
4875 
4876         /*
4877          * Set MEM_CFG Microcode Default Value
4878          *
4879          * The microcode will set the MEM_CFG register using this value
4880          * after it is started below.
4881          *
4882          * MEM_CFG may be accessed as a word or byte, but only bits 0-7
4883          * are defined.
4884          *
4885          * ASC-3550 has 8KB internal memory.
4886          */
4887         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
4888                          BIOS_EN | RAM_SZ_8KB);
4889 
4890         /*
4891          * Set SEL_MASK Microcode Default Value
4892          *
4893          * The microcode will set the SEL_MASK register using this value
4894          * after it is started below.
4895          */
4896         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
4897                          ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
4898 
4899         AdvBuildCarrierFreelist(asc_dvc);
4900 
4901         /*
4902          * Set-up the Host->RISC Initiator Command Queue (ICQ).
4903          */
4904 
4905         if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
4906                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4907                 return ADV_ERROR;
4908         }
4909         asc_dvc->carr_freelist = (ADV_CARR_T *)
4910             ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
4911 
4912         /*
4913          * The first command issued will be placed in the stopper carrier.
4914          */
4915         asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
4916 
4917         /*
4918          * Set RISC ICQ physical address start value.
4919          */
4920         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
4921 
4922         /*
4923          * Set-up the RISC->Host Initiator Response Queue (IRQ).
4924          */
4925         if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
4926                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4927                 return ADV_ERROR;
4928         }
4929         asc_dvc->carr_freelist = (ADV_CARR_T *)
4930             ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
4931 
4932         /*
4933          * The first command completed by the RISC will be placed in
4934          * the stopper.
4935          *
4936          * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
4937          * completed the RISC will set the ASC_RQ_STOPPER bit.
4938          */
4939         asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
4940 
4941         /*
4942          * Set RISC IRQ physical address start value.
4943          */
4944         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
4945         asc_dvc->carr_pending_cnt = 0;
4946 
4947         AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
4948                              (ADV_INTR_ENABLE_HOST_INTR |
4949                               ADV_INTR_ENABLE_GLOBAL_INTR));
4950 
4951         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
4952         AdvWriteWordRegister(iop_base, IOPW_PC, word);
4953 
4954         /* finally, finally, gentlemen, start your engine */
4955         AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
4956 
4957         /*
4958          * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
4959          * Resets should be performed. The RISC has to be running
4960          * to issue a SCSI Bus Reset.
4961          */
4962         if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
4963                 /*
4964                  * If the BIOS Signature is present in memory, restore the
4965                  * BIOS Handshake Configuration Table and do not perform
4966                  * a SCSI Bus Reset.
4967                  */
4968                 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
4969                     0x55AA) {
4970                         /*
4971                          * Restore per TID negotiated values.
4972                          */
4973                         AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4974                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4975                         AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
4976                                          tagqng_able);
4977                         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4978                                 AdvWriteByteLram(iop_base,
4979                                                  ASC_MC_NUMBER_OF_MAX_CMD + tid,
4980                                                  max_cmd[tid]);
4981                         }
4982                 } else {
4983                         if (AdvResetSB(asc_dvc) != ADV_TRUE) {
4984                                 warn_code = ASC_WARN_BUSRESET_ERROR;
4985                         }
4986                 }
4987         }
4988 
4989         return warn_code;
4990 }
4991 
4992 /*
4993  * Initialize the ASC-38C0800.
4994  *
4995  * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4996  *
4997  * For a non-fatal error return a warning code. If there are no warnings
4998  * then 0 is returned.
4999  *
5000  * Needed after initialization for error recovery.
5001  */
5002 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
5003 {
5004         const struct firmware *fw;
5005         const char fwname[] = "advansys/38C0800.bin";
5006         AdvPortAddr iop_base;
5007         ushort warn_code;
5008         int begin_addr;
5009         int end_addr;
5010         ushort code_sum;
5011         int word;
5012         int i;
5013         int err;
5014         unsigned long chksum;
5015         ushort scsi_cfg1;
5016         uchar byte;
5017         uchar tid;
5018         ushort bios_mem[ASC_MC_BIOSLEN / 2];    /* BIOS RISC Memory 0x40-0x8F. */
5019         ushort wdtr_able, sdtr_able, tagqng_able;
5020         uchar max_cmd[ADV_MAX_TID + 1];
5021 
5022         /* If there is already an error, don't continue. */
5023         if (asc_dvc->err_code != 0)
5024                 return ADV_ERROR;
5025 
5026         /*
5027          * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
5028          */
5029         if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
5030                 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
5031                 return ADV_ERROR;
5032         }
5033 
5034         warn_code = 0;
5035         iop_base = asc_dvc->iop_base;
5036 
5037         /*
5038          * Save the RISC memory BIOS region before writing the microcode.
5039          * The BIOS may already be loaded and using its RISC LRAM region
5040          * so its region must be saved and restored.
5041          *
5042          * Note: This code makes the assumption, which is currently true,
5043          * that a chip reset does not clear RISC LRAM.
5044          */
5045         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5046                 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5047                                 bios_mem[i]);
5048         }
5049 
5050         /*
5051          * Save current per TID negotiated values.
5052          */
5053         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5054         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5055         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5056         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5057                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5058                                 max_cmd[tid]);
5059         }
5060 
5061         /*
5062          * RAM BIST (RAM Built-In Self Test)
5063          *
5064          * Address : I/O base + offset 0x38h register (byte).
5065          * Function: Bit 7-6(RW) : RAM mode
5066          *                          Normal Mode   : 0x00
5067          *                          Pre-test Mode : 0x40
5068          *                          RAM Test Mode : 0x80
5069          *           Bit 5       : unused
5070          *           Bit 4(RO)   : Done bit
5071          *           Bit 3-0(RO) : Status
5072          *                          Host Error    : 0x08
5073          *                          Int_RAM Error : 0x04
5074          *                          RISC Error    : 0x02
5075          *                          SCSI Error    : 0x01
5076          *                          No Error      : 0x00
5077          *
5078          * Note: RAM BIST code should be put right here, before loading the
5079          * microcode and after saving the RISC memory BIOS region.
5080          */
5081 
5082         /*
5083          * LRAM Pre-test
5084          *
5085          * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5086          * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5087          * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5088          * to NORMAL_MODE, return an error too.
5089          */
5090         for (i = 0; i < 2; i++) {
5091                 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5092                 mdelay(10);     /* Wait for 10ms before reading back. */
5093                 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5094                 if ((byte & RAM_TEST_DONE) == 0
5095                     || (byte & 0x0F) != PRE_TEST_VALUE) {
5096                         asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5097                         return ADV_ERROR;
5098                 }
5099 
5100                 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5101                 mdelay(10);     /* Wait for 10ms before reading back. */
5102                 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5103                     != NORMAL_VALUE) {
5104                         asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5105                         return ADV_ERROR;
5106                 }
5107         }
5108 
5109         /*
5110          * LRAM Test - It takes about 1.5 ms to run through the test.
5111          *
5112          * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5113          * If Done bit not set or Status not 0, save register byte, set the
5114          * err_code, and return an error.
5115          */
5116         AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5117         mdelay(10);     /* Wait for 10ms before checking status. */
5118 
5119         byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5120         if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5121                 /* Get here if Done bit not set or Status not 0. */
5122                 asc_dvc->bist_err_code = byte;  /* for BIOS display message */
5123                 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5124                 return ADV_ERROR;
5125         }
5126 
5127         /* We need to reset back to normal mode after LRAM test passes. */
5128         AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5129 
5130         err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5131         if (err) {
5132                 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5133                        fwname, err);
5134                 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5135                 return err;
5136         }
5137         if (fw->size < 4) {
5138                 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5139                        fw->size, fwname);
5140                 release_firmware(fw);
5141                 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5142                 return -EINVAL;
5143         }
5144         chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5145                  (fw->data[1] << 8) | fw->data[0];
5146         asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5147                                              fw->size - 4, ADV_38C0800_MEMSIZE,
5148                                              chksum);
5149         release_firmware(fw);
5150         if (asc_dvc->err_code)
5151                 return ADV_ERROR;
5152 
5153         /*
5154          * Restore the RISC memory BIOS region.
5155          */
5156         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5157                 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5158                                  bios_mem[i]);
5159         }
5160 
5161         /*
5162          * Calculate and write the microcode code checksum to the microcode
5163          * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5164          */
5165         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5166         AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5167         code_sum = 0;
5168         AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5169         for (word = begin_addr; word < end_addr; word += 2) {
5170                 code_sum += AdvReadWordAutoIncLram(iop_base);
5171         }
5172         AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5173 
5174         /*
5175          * Read microcode version and date.
5176          */
5177         AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5178                         asc_dvc->cfg->mcode_date);
5179         AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5180                         asc_dvc->cfg->mcode_version);
5181 
5182         /*
5183          * Set the chip type to indicate the ASC38C0800.
5184          */
5185         AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
5186 
5187         /*
5188          * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5189          * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5190          * cable detection and then we are able to read C_DET[3:0].
5191          *
5192          * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5193          * Microcode Default Value' section below.
5194          */
5195         scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5196         AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5197                              scsi_cfg1 | DIS_TERM_DRV);
5198 
5199         /*
5200          * If the PCI Configuration Command Register "Parity Error Response
5201          * Control" Bit was clear (0), then set the microcode variable
5202          * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5203          * to ignore DMA parity errors.
5204          */
5205         if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5206                 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5207                 word |= CONTROL_FLAG_IGNORE_PERR;
5208                 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5209         }
5210 
5211         /*
5212          * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
5213          * bits for the default FIFO threshold.
5214          *
5215          * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
5216          *
5217          * For DMA Errata #4 set the BC_THRESH_ENB bit.
5218          */
5219         AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5220                              BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
5221                              READ_CMD_MRM);
5222 
5223         /*
5224          * Microcode operating variables for WDTR, SDTR, and command tag
5225          * queuing will be set in slave_configure() based on what a
5226          * device reports it is capable of in Inquiry byte 7.
5227          *
5228          * If SCSI Bus Resets have been disabled, then directly set
5229          * SDTR and WDTR from the EEPROM configuration. This will allow
5230          * the BIOS and warm boot to work without a SCSI bus hang on
5231          * the Inquiry caused by host and target mismatched DTR values.
5232          * Without the SCSI Bus Reset, before an Inquiry a device can't
5233          * be assumed to be in Asynchronous, Narrow mode.
5234          */
5235         if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5236                 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5237                                  asc_dvc->wdtr_able);
5238                 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5239                                  asc_dvc->sdtr_able);
5240         }
5241 
5242         /*
5243          * Set microcode operating variables for DISC and SDTR_SPEED1,
5244          * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5245          * configuration values.
5246          *
5247          * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5248          * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5249          * without determining here whether the device supports SDTR.
5250          */
5251         AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5252                          asc_dvc->cfg->disc_enable);
5253         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5254         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5255         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5256         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5257 
5258         /*
5259          * Set SCSI_CFG0 Microcode Default Value.
5260          *
5261          * The microcode will set the SCSI_CFG0 register using this value
5262          * after it is started below.
5263          */
5264         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5265                          PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5266                          asc_dvc->chip_scsi_id);
5267 
5268         /*
5269          * Determine SCSI_CFG1 Microcode Default Value.
5270          *
5271          * The microcode will set the SCSI_CFG1 register using this value
5272          * after it is started below.
5273          */
5274 
5275         /* Read current SCSI_CFG1 Register value. */
5276         scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5277 
5278         /*
5279          * If the internal narrow cable is reversed all of the SCSI_CTRL
5280          * register signals will be set. Check for and return an error if
5281          * this condition is found.
5282          */
5283         if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5284                 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5285                 return ADV_ERROR;
5286         }
5287 
5288         /*
5289          * All kind of combinations of devices attached to one of four
5290          * connectors are acceptable except HVD device attached. For example,
5291          * LVD device can be attached to SE connector while SE device attached
5292          * to LVD connector.  If LVD device attached to SE connector, it only
5293          * runs up to Ultra speed.
5294          *
5295          * If an HVD device is attached to one of LVD connectors, return an
5296          * error.  However, there is no way to detect HVD device attached to
5297          * SE connectors.
5298          */
5299         if (scsi_cfg1 & HVD) {
5300                 asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
5301                 return ADV_ERROR;
5302         }
5303 
5304         /*
5305          * If either SE or LVD automatic termination control is enabled, then
5306          * set the termination value based on a table listed in a_condor.h.
5307          *
5308          * If manual termination was specified with an EEPROM setting then
5309          * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
5310          * to be 'ored' into SCSI_CFG1.
5311          */
5312         if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5313                 /* SE automatic termination control is enabled. */
5314                 switch (scsi_cfg1 & C_DET_SE) {
5315                         /* TERM_SE_HI: on, TERM_SE_LO: on */
5316                 case 0x1:
5317                 case 0x2:
5318                 case 0x3:
5319                         asc_dvc->cfg->termination |= TERM_SE;
5320                         break;
5321 
5322                         /* TERM_SE_HI: on, TERM_SE_LO: off */
5323                 case 0x0:
5324                         asc_dvc->cfg->termination |= TERM_SE_HI;
5325                         break;
5326                 }
5327         }
5328 
5329         if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
5330                 /* LVD automatic termination control is enabled. */
5331                 switch (scsi_cfg1 & C_DET_LVD) {
5332                         /* TERM_LVD_HI: on, TERM_LVD_LO: on */
5333                 case 0x4:
5334                 case 0x8:
5335                 case 0xC:
5336                         asc_dvc->cfg->termination |= TERM_LVD;
5337                         break;
5338 
5339                         /* TERM_LVD_HI: off, TERM_LVD_LO: off */
5340                 case 0x0:
5341                         break;
5342                 }
5343         }
5344 
5345         /*
5346          * Clear any set TERM_SE and TERM_LVD bits.
5347          */
5348         scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
5349 
5350         /*
5351          * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
5352          */
5353         scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
5354 
5355         /*
5356          * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
5357          * bits and set possibly modified termination control bits in the
5358          * Microcode SCSI_CFG1 Register Value.
5359          */
5360         scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
5361 
5362         /*
5363          * Set SCSI_CFG1 Microcode Default Value
5364          *
5365          * Set possibly modified termination control and reset DIS_TERM_DRV
5366          * bits in the Microcode SCSI_CFG1 Register Value.
5367          *
5368          * The microcode will set the SCSI_CFG1 register using this value
5369          * after it is started below.
5370          */
5371         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5372 
5373         /*
5374          * Set MEM_CFG Microcode Default Value
5375          *
5376          * The microcode will set the MEM_CFG register using this value
5377          * after it is started below.
5378          *
5379          * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5380          * are defined.
5381          *
5382          * ASC-38C0800 has 16KB internal memory.
5383          */
5384         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5385                          BIOS_EN | RAM_SZ_16KB);
5386 
5387         /*
5388          * Set SEL_MASK Microcode Default Value
5389          *
5390          * The microcode will set the SEL_MASK register using this value
5391          * after it is started below.
5392          */
5393         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5394                          ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5395 
5396         AdvBuildCarrierFreelist(asc_dvc);
5397 
5398         /*
5399          * Set-up the Host->RISC Initiator Command Queue (ICQ).
5400          */
5401 
5402         if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
5403                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5404                 return ADV_ERROR;
5405         }
5406         asc_dvc->carr_freelist = (ADV_CARR_T *)
5407             ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
5408 
5409         /*
5410          * The first command issued will be placed in the stopper carrier.
5411          */
5412         asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5413 
5414         /*
5415          * Set RISC ICQ physical address start value.
5416          * carr_pa is LE, must be native before write
5417          */
5418         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5419 
5420         /*
5421          * Set-up the RISC->Host Initiator Response Queue (IRQ).
5422          */
5423         if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
5424                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5425                 return ADV_ERROR;
5426         }
5427         asc_dvc->carr_freelist = (ADV_CARR_T *)
5428             ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
5429 
5430         /*
5431          * The first command completed by the RISC will be placed in
5432          * the stopper.
5433          *
5434          * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
5435          * completed the RISC will set the ASC_RQ_STOPPER bit.
5436          */
5437         asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5438 
5439         /*
5440          * Set RISC IRQ physical address start value.
5441          *
5442          * carr_pa is LE, must be native before write *
5443          */
5444         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5445         asc_dvc->carr_pending_cnt = 0;
5446 
5447         AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5448                              (ADV_INTR_ENABLE_HOST_INTR |
5449                               ADV_INTR_ENABLE_GLOBAL_INTR));
5450 
5451         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5452         AdvWriteWordRegister(iop_base, IOPW_PC, word);
5453 
5454         /* finally, finally, gentlemen, start your engine */
5455         AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5456 
5457         /*
5458          * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5459          * Resets should be performed. The RISC has to be running
5460          * to issue a SCSI Bus Reset.
5461          */
5462         if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5463                 /*
5464                  * If the BIOS Signature is present in memory, restore the
5465                  * BIOS Handshake Configuration Table and do not perform
5466                  * a SCSI Bus Reset.
5467                  */
5468                 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5469                     0x55AA) {
5470                         /*
5471                          * Restore per TID negotiated values.
5472                          */
5473                         AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5474                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5475                         AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5476                                          tagqng_able);
5477                         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5478                                 AdvWriteByteLram(iop_base,
5479                                                  ASC_MC_NUMBER_OF_MAX_CMD + tid,
5480                                                  max_cmd[tid]);
5481                         }
5482                 } else {
5483                         if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5484                                 warn_code = ASC_WARN_BUSRESET_ERROR;
5485                         }
5486                 }
5487         }
5488 
5489         return warn_code;
5490 }
5491 
5492 /*
5493  * Initialize the ASC-38C1600.
5494  *
5495  * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
5496  *
5497  * For a non-fatal error return a warning code. If there are no warnings
5498  * then 0 is returned.
5499  *
5500  * Needed after initialization for error recovery.
5501  */
5502 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
5503 {
5504         const struct firmware *fw;
5505         const char fwname[] = "advansys/38C1600.bin";
5506         AdvPortAddr iop_base;
5507         ushort warn_code;
5508         int begin_addr;
5509         int end_addr;
5510         ushort code_sum;
5511         long word;
5512         int i;
5513         int err;
5514         unsigned long chksum;
5515         ushort scsi_cfg1;
5516         uchar byte;
5517         uchar tid;
5518         ushort bios_mem[ASC_MC_BIOSLEN / 2];    /* BIOS RISC Memory 0x40-0x8F. */
5519         ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
5520         uchar max_cmd[ASC_MAX_TID + 1];
5521 
5522         /* If there is already an error, don't continue. */
5523         if (asc_dvc->err_code != 0) {
5524                 return ADV_ERROR;
5525         }
5526 
5527         /*
5528          * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
5529          */
5530         if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
5531                 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
5532                 return ADV_ERROR;
5533         }
5534 
5535         warn_code = 0;
5536         iop_base = asc_dvc->iop_base;
5537 
5538         /*
5539          * Save the RISC memory BIOS region before writing the microcode.
5540          * The BIOS may already be loaded and using its RISC LRAM region
5541          * so its region must be saved and restored.
5542          *
5543          * Note: This code makes the assumption, which is currently true,
5544          * that a chip reset does not clear RISC LRAM.
5545          */
5546         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5547                 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5548                                 bios_mem[i]);
5549         }
5550 
5551         /*
5552          * Save current per TID negotiated values.
5553          */
5554         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5555         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5556         AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5557         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5558         for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5559                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5560                                 max_cmd[tid]);
5561         }
5562 
5563         /*
5564          * RAM BIST (Built-In Self Test)
5565          *
5566          * Address : I/O base + offset 0x38h register (byte).
5567          * Function: Bit 7-6(RW) : RAM mode
5568          *                          Normal Mode   : 0x00
5569          *                          Pre-test Mode : 0x40
5570          *                          RAM Test Mode : 0x80
5571          *           Bit 5       : unused
5572          *           Bit 4(RO)   : Done bit
5573          *           Bit 3-0(RO) : Status
5574          *                          Host Error    : 0x08
5575          *                          Int_RAM Error : 0x04
5576          *                          RISC Error    : 0x02
5577          *                          SCSI Error    : 0x01
5578          *                          No Error      : 0x00
5579          *
5580          * Note: RAM BIST code should be put right here, before loading the
5581          * microcode and after saving the RISC memory BIOS region.
5582          */
5583 
5584         /*
5585          * LRAM Pre-test
5586          *
5587          * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5588          * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5589          * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5590          * to NORMAL_MODE, return an error too.
5591          */
5592         for (i = 0; i < 2; i++) {
5593                 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5594                 mdelay(10);     /* Wait for 10ms before reading back. */
5595                 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5596                 if ((byte & RAM_TEST_DONE) == 0
5597                     || (byte & 0x0F) != PRE_TEST_VALUE) {
5598                         asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5599                         return ADV_ERROR;
5600                 }
5601 
5602                 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5603                 mdelay(10);     /* Wait for 10ms before reading back. */
5604                 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5605                     != NORMAL_VALUE) {
5606                         asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5607                         return ADV_ERROR;
5608                 }
5609         }
5610 
5611         /*
5612          * LRAM Test - It takes about 1.5 ms to run through the test.
5613          *
5614          * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5615          * If Done bit not set or Status not 0, save register byte, set the
5616          * err_code, and return an error.
5617          */
5618         AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5619         mdelay(10);     /* Wait for 10ms before checking status. */
5620 
5621         byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5622         if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5623                 /* Get here if Done bit not set or Status not 0. */
5624                 asc_dvc->bist_err_code = byte;  /* for BIOS display message */
5625                 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5626                 return ADV_ERROR;
5627         }
5628 
5629         /* We need to reset back to normal mode after LRAM test passes. */
5630         AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5631 
5632         err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5633         if (err) {
5634                 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5635                        fwname, err);
5636                 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5637                 return err;
5638         }
5639         if (fw->size < 4) {
5640                 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5641                        fw->size, fwname);
5642                 release_firmware(fw);
5643                 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5644                 return -EINVAL;
5645         }
5646         chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5647                  (fw->data[1] << 8) | fw->data[0];
5648         asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5649                                              fw->size - 4, ADV_38C1600_MEMSIZE,
5650                                              chksum);
5651         release_firmware(fw);
5652         if (asc_dvc->err_code)
5653                 return ADV_ERROR;
5654 
5655         /*
5656          * Restore the RISC memory BIOS region.
5657          */
5658         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5659                 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5660                                  bios_mem[i]);
5661         }
5662 
5663         /*
5664          * Calculate and write the microcode code checksum to the microcode
5665          * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5666          */
5667         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5668         AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5669         code_sum = 0;
5670         AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5671         for (word = begin_addr; word < end_addr; word += 2) {
5672                 code_sum += AdvReadWordAutoIncLram(iop_base);
5673         }
5674         AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5675 
5676         /*
5677          * Read microcode version and date.
5678          */
5679         AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5680                         asc_dvc->cfg->mcode_date);
5681         AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5682                         asc_dvc->cfg->mcode_version);
5683 
5684         /*
5685          * Set the chip type to indicate the ASC38C1600.
5686          */
5687         AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
5688 
5689         /*
5690          * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5691          * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5692          * cable detection and then we are able to read C_DET[3:0].
5693          *
5694          * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5695          * Microcode Default Value' section below.
5696          */
5697         scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5698         AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5699                              scsi_cfg1 | DIS_TERM_DRV);
5700 
5701         /*
5702          * If the PCI Configuration Command Register "Parity Error Response
5703          * Control" Bit was clear (0), then set the microcode variable
5704          * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5705          * to ignore DMA parity errors.
5706          */
5707         if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5708                 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5709                 word |= CONTROL_FLAG_IGNORE_PERR;
5710                 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5711         }
5712 
5713         /*
5714          * If the BIOS control flag AIPP (Asynchronous Information
5715          * Phase Protection) disable bit is not set, then set the firmware
5716          * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
5717          * AIPP checking and encoding.
5718          */
5719         if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
5720                 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5721                 word |= CONTROL_FLAG_ENABLE_AIPP;
5722                 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5723         }
5724 
5725         /*
5726          * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
5727          * and START_CTL_TH [3:2].
5728          */
5729         AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5730                              FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
5731 
5732         /*
5733          * Microcode operating variables for WDTR, SDTR, and command tag
5734          * queuing will be set in slave_configure() based on what a
5735          * device reports it is capable of in Inquiry byte 7.
5736          *
5737          * If SCSI Bus Resets have been disabled, then directly set
5738          * SDTR and WDTR from the EEPROM configuration. This will allow
5739          * the BIOS and warm boot to work without a SCSI bus hang on
5740          * the Inquiry caused by host and target mismatched DTR values.
5741          * Without the SCSI Bus Reset, before an Inquiry a device can't
5742          * be assumed to be in Asynchronous, Narrow mode.
5743          */
5744         if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5745                 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5746                                  asc_dvc->wdtr_able);
5747                 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5748                                  asc_dvc->sdtr_able);
5749         }
5750 
5751         /*
5752          * Set microcode operating variables for DISC and SDTR_SPEED1,
5753          * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5754          * configuration values.
5755          *
5756          * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5757          * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5758          * without determining here whether the device supports SDTR.
5759          */
5760         AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5761                          asc_dvc->cfg->disc_enable);
5762         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5763         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5764         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5765         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5766 
5767         /*
5768          * Set SCSI_CFG0 Microcode Default Value.
5769          *
5770          * The microcode will set the SCSI_CFG0 register using this value
5771          * after it is started below.
5772          */
5773         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5774                          PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5775                          asc_dvc->chip_scsi_id);
5776 
5777         /*
5778          * Calculate SCSI_CFG1 Microcode Default Value.
5779          *
5780          * The microcode will set the SCSI_CFG1 register using this value
5781          * after it is started below.
5782          *
5783          * Each ASC-38C1600 function has only two cable detect bits.
5784          * The bus mode override bits are in IOPB_SOFT_OVER_WR.
5785          */
5786         scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5787 
5788         /*
5789          * If the cable is reversed all of the SCSI_CTRL register signals
5790          * will be set. Check for and return an error if this condition is
5791          * found.
5792          */
5793         if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5794                 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5795                 return ADV_ERROR;
5796         }
5797 
5798         /*
5799          * Each ASC-38C1600 function has two connectors. Only an HVD device
5800          * can not be connected to either connector. An LVD device or SE device
5801          * may be connected to either connecor. If an SE device is connected,
5802          * then at most Ultra speed (20 Mhz) can be used on both connectors.
5803          *
5804          * If an HVD device is attached, return an error.
5805          */
5806         if (scsi_cfg1 & HVD) {
5807                 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
5808                 return ADV_ERROR;
5809         }
5810 
5811         /*
5812          * Each function in the ASC-38C1600 uses only the SE cable detect and
5813          * termination because there are two connectors for each function. Each
5814          * function may use either LVD or SE mode. Corresponding the SE automatic
5815          * termination control EEPROM bits are used for each function. Each
5816          * function has its own EEPROM. If SE automatic control is enabled for
5817          * the function, then set the termination value based on a table listed
5818          * in a_condor.h.
5819          *
5820          * If manual termination is specified in the EEPROM for the function,
5821          * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
5822          * ready to be 'ored' into SCSI_CFG1.
5823          */
5824         if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5825                 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
5826                 /* SE automatic termination control is enabled. */
5827                 switch (scsi_cfg1 & C_DET_SE) {
5828                         /* TERM_SE_HI: on, TERM_SE_LO: on */
5829                 case 0x1:
5830                 case 0x2:
5831                 case 0x3:
5832                         asc_dvc->cfg->termination |= TERM_SE;
5833                         break;
5834 
5835                 case 0x0:
5836                         if (PCI_FUNC(pdev->devfn) == 0) {
5837                                 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
5838                         } else {
5839                                 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
5840                                 asc_dvc->cfg->termination |= TERM_SE_HI;
5841                         }
5842                         break;
5843                 }
5844         }
5845 
5846         /*
5847          * Clear any set TERM_SE bits.
5848          */
5849         scsi_cfg1 &= ~TERM_SE;
5850 
5851         /*
5852          * Invert the TERM_SE bits and then set 'scsi_cfg1'.
5853          */
5854         scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
5855 
5856         /*
5857          * Clear Big Endian and Terminator Polarity bits and set possibly
5858          * modified termination control bits in the Microcode SCSI_CFG1
5859          * Register Value.
5860          *
5861          * Big Endian bit is not used even on big endian machines.
5862          */
5863         scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
5864 
5865         /*
5866          * Set SCSI_CFG1 Microcode Default Value
5867          *
5868          * Set possibly modified termination control bits in the Microcode
5869          * SCSI_CFG1 Register Value.
5870          *
5871          * The microcode will set the SCSI_CFG1 register using this value
5872          * after it is started below.
5873          */
5874         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5875 
5876         /*
5877          * Set MEM_CFG Microcode Default Value
5878          *
5879          * The microcode will set the MEM_CFG register using this value
5880          * after it is started below.
5881          *
5882          * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5883          * are defined.
5884          *
5885          * ASC-38C1600 has 32KB internal memory.
5886          *
5887          * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
5888          * out a special 16K Adv Library and Microcode version. After the issue
5889          * resolved, we should turn back to the 32K support. Both a_condor.h and
5890          * mcode.sas files also need to be updated.
5891          *
5892          * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5893          *  BIOS_EN | RAM_SZ_32KB);
5894          */
5895         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5896                          BIOS_EN | RAM_SZ_16KB);
5897 
5898         /*
5899          * Set SEL_MASK Microcode Default Value
5900          *
5901          * The microcode will set the SEL_MASK register using this value
5902          * after it is started below.
5903          */
5904         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5905                          ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5906 
5907         AdvBuildCarrierFreelist(asc_dvc);
5908 
5909         /*
5910          * Set-up the Host->RISC Initiator Command Queue (ICQ).
5911          */
5912         if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
5913                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5914                 return ADV_ERROR;
5915         }
5916         asc_dvc->carr_freelist = (ADV_CARR_T *)
5917             ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
5918 
5919         /*
5920          * The first command issued will be placed in the stopper carrier.
5921          */
5922         asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5923 
5924         /*
5925          * Set RISC ICQ physical address start value. Initialize the
5926          * COMMA register to the same value otherwise the RISC will
5927          * prematurely detect a command is available.
5928          */
5929         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5930         AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
5931                               le32_to_cpu(asc_dvc->icq_sp->carr_pa));
5932 
5933         /*
5934          * Set-up the RISC->Host Initiator Response Queue (IRQ).
5935          */
5936         if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
5937                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5938                 return ADV_ERROR;
5939         }
5940         asc_dvc->carr_freelist = (ADV_CARR_T *)
5941             ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
5942 
5943         /*
5944          * The first command completed by the RISC will be placed in
5945          * the stopper.
5946          *
5947          * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
5948          * completed the RISC will set the ASC_RQ_STOPPER bit.
5949          */
5950         asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5951 
5952         /*
5953          * Set RISC IRQ physical address start value.
5954          */
5955         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5956         asc_dvc->carr_pending_cnt = 0;
5957 
5958         AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5959                              (ADV_INTR_ENABLE_HOST_INTR |
5960                               ADV_INTR_ENABLE_GLOBAL_INTR));
5961         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5962         AdvWriteWordRegister(iop_base, IOPW_PC, word);
5963 
5964         /* finally, finally, gentlemen, start your engine */
5965         AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5966 
5967         /*
5968          * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5969          * Resets should be performed. The RISC has to be running
5970          * to issue a SCSI Bus Reset.
5971          */
5972         if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5973                 /*
5974                  * If the BIOS Signature is present in memory, restore the
5975                  * per TID microcode operating variables.
5976                  */
5977                 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5978                     0x55AA) {
5979                         /*
5980                          * Restore per TID negotiated values.
5981                          */
5982                         AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5983                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5984                         AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5985                         AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5986                                          tagqng_able);
5987                         for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5988                                 AdvWriteByteLram(iop_base,
5989                                                  ASC_MC_NUMBER_OF_MAX_CMD + tid,
5990                                                  max_cmd[tid]);
5991                         }
5992                 } else {
5993                         if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5994                                 warn_code = ASC_WARN_BUSRESET_ERROR;
5995                         }
5996                 }
5997         }
5998 
5999         return warn_code;
6000 }
6001 
6002 /*
6003  * Reset chip and SCSI Bus.
6004  *
6005  * Return Value:
6006  *      ADV_TRUE(1) -   Chip re-initialization and SCSI Bus Reset successful.
6007  *      ADV_FALSE(0) -  Chip re-initialization and SCSI Bus Reset failure.
6008  */
6009 static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
6010 {
6011         int status;
6012         ushort wdtr_able, sdtr_able, tagqng_able;
6013         ushort ppr_able = 0;
6014         uchar tid, max_cmd[ADV_MAX_TID + 1];
6015         AdvPortAddr iop_base;
6016         ushort bios_sig;
6017 
6018         iop_base = asc_dvc->iop_base;
6019 
6020         /*
6021          * Save current per TID negotiated values.
6022          */
6023         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6024         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6025         if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
6026                 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
6027         }
6028         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
6029         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6030                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
6031                                 max_cmd[tid]);
6032         }
6033 
6034         /*
6035          * Force the AdvInitAsc3550/38C0800Driver() function to
6036          * perform a SCSI Bus Reset by clearing the BIOS signature word.
6037          * The initialization functions assumes a SCSI Bus Reset is not
6038          * needed if the BIOS signature word is present.
6039          */
6040         AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
6041         AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
6042 
6043         /*
6044          * Stop chip and reset it.
6045          */
6046         AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
6047         AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
6048         mdelay(100);
6049         AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
6050                              ADV_CTRL_REG_CMD_WR_IO_REG);
6051 
6052         /*
6053          * Reset Adv Library error code, if any, and try
6054          * re-initializing the chip.
6055          */
6056         asc_dvc->err_code = 0;
6057         if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
6058                 status = AdvInitAsc38C1600Driver(asc_dvc);
6059         } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
6060                 status = AdvInitAsc38C0800Driver(asc_dvc);
6061         } else {
6062                 status = AdvInitAsc3550Driver(asc_dvc);
6063         }
6064 
6065         /* Translate initialization return value to status value. */
6066         if (status == 0) {
6067                 status = ADV_TRUE;
6068         } else {
6069                 status = ADV_FALSE;
6070         }
6071 
6072         /*
6073          * Restore the BIOS signature word.
6074          */
6075         AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
6076 
6077         /*
6078          * Restore per TID negotiated values.
6079          */
6080         AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6081         AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6082         if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
6083                 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
6084         }
6085         AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
6086         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6087                 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
6088                                  max_cmd[tid]);
6089         }
6090 
6091         return status;
6092 }
6093 
6094 /*
6095  * adv_async_callback() - Adv Library asynchronous event callback function.
6096  */
6097 static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
6098 {
6099         switch (code) {
6100         case ADV_ASYNC_SCSI_BUS_RESET_DET:
6101                 /*
6102                  * The firmware detected a SCSI Bus reset.
6103                  */
6104                 ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n");
6105                 break;
6106 
6107         case ADV_ASYNC_RDMA_FAILURE:
6108                 /*
6109                  * Handle RDMA failure by resetting the SCSI Bus and
6110                  * possibly the chip if it is unresponsive. Log the error
6111                  * with a unique code.
6112                  */
6113                 ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n");
6114                 AdvResetChipAndSB(adv_dvc_varp);
6115                 break;
6116 
6117         case ADV_HOST_SCSI_BUS_RESET:
6118                 /*
6119                  * Host generated SCSI bus reset occurred.
6120                  */
6121                 ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n");
6122                 break;
6123 
6124         default:
6125                 ASC_DBG(0, "unknown code 0x%x\n", code);
6126                 break;
6127         }
6128 }
6129 
6130 /*
6131  * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
6132  *
6133  * Callback function for the Wide SCSI Adv Library.
6134  */
6135 static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
6136 {
6137         struct asc_board *boardp;
6138         adv_req_t *reqp;
6139         adv_sgblk_t *sgblkp;
6140         struct scsi_cmnd *scp;
6141         struct Scsi_Host *shost;
6142         ADV_DCNT resid_cnt;
6143 
6144         ASC_DBG(1, "adv_dvc_varp 0x%lx, scsiqp 0x%lx\n",
6145                  (ulong)adv_dvc_varp, (ulong)scsiqp);
6146         ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
6147 
6148         /*
6149          * Get the adv_req_t structure for the command that has been
6150          * completed. The adv_req_t structure actually contains the
6151          * completed ADV_SCSI_REQ_Q structure.
6152          */
6153         reqp = (adv_req_t *)ADV_U32_TO_VADDR(scsiqp->srb_ptr);
6154         ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp);
6155         if (reqp == NULL) {
6156                 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
6157                 return;
6158         }
6159 
6160         /*
6161          * Get the struct scsi_cmnd structure and Scsi_Host structure for the
6162          * command that has been completed.
6163          *
6164          * Note: The adv_req_t request structure and adv_sgblk_t structure,
6165          * if any, are dropped, because a board structure pointer can not be
6166          * determined.
6167          */
6168         scp = reqp->cmndp;
6169         ASC_DBG(1, "scp 0x%p\n", scp);
6170         if (scp == NULL) {
6171                 ASC_PRINT
6172                     ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
6173                 return;
6174         }
6175         ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6176 
6177         shost = scp->device->host;
6178         ASC_STATS(shost, callback);
6179         ASC_DBG(1, "shost 0x%p\n", shost);
6180 
6181         boardp = shost_priv(shost);
6182         BUG_ON(adv_dvc_varp != &boardp->dvc_var.adv_dvc_var);
6183 
6184         /*
6185          * 'done_status' contains the command's ending status.
6186          */
6187         switch (scsiqp->done_status) {
6188         case QD_NO_ERROR:
6189                 ASC_DBG(2, "QD_NO_ERROR\n");
6190                 scp->result = 0;
6191 
6192                 /*
6193                  * Check for an underrun condition.
6194                  *
6195                  * If there was no error and an underrun condition, then
6196                  * then return the number of underrun bytes.
6197                  */
6198                 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
6199                 if (scsi_bufflen(scp) != 0 && resid_cnt != 0 &&
6200                     resid_cnt <= scsi_bufflen(scp)) {
6201                         ASC_DBG(1, "underrun condition %lu bytes\n",
6202                                  (ulong)resid_cnt);
6203                         scsi_set_resid(scp, resid_cnt);
6204                 }
6205                 break;
6206 
6207         case QD_WITH_ERROR:
6208                 ASC_DBG(2, "QD_WITH_ERROR\n");
6209                 switch (scsiqp->host_status) {
6210                 case QHSTA_NO_ERROR:
6211                         if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
6212                                 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
6213                                 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
6214                                                   SCSI_SENSE_BUFFERSIZE);
6215                                 /*
6216                                  * Note: The 'status_byte()' macro used by
6217                                  * target drivers defined in scsi.h shifts the
6218                                  * status byte returned by host drivers right
6219                                  * by 1 bit.  This is why target drivers also
6220                                  * use right shifted status byte definitions.
6221                                  * For instance target drivers use
6222                                  * CHECK_CONDITION, defined to 0x1, instead of
6223                                  * the SCSI defined check condition value of
6224                                  * 0x2. Host drivers are supposed to return
6225                                  * the status byte as it is defined by SCSI.
6226                                  */
6227                                 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
6228                                     STATUS_BYTE(scsiqp->scsi_status);
6229                         } else {
6230                                 scp->result = STATUS_BYTE(scsiqp->scsi_status);
6231                         }
6232                         break;
6233 
6234                 default:
6235                         /* Some other QHSTA error occurred. */
6236                         ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status);
6237                         scp->result = HOST_BYTE(DID_BAD_TARGET);
6238                         break;
6239                 }
6240                 break;
6241 
6242         case QD_ABORTED_BY_HOST:
6243                 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
6244                 scp->result =
6245                     HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
6246                 break;
6247 
6248         default:
6249                 ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status);
6250                 scp->result =
6251                     HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
6252                 break;
6253         }
6254 
6255         /*
6256          * If the 'init_tidmask' bit isn't already set for the target and the
6257          * current request finished normally, then set the bit for the target
6258          * to indicate that a device is present.
6259          */
6260         if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6261             scsiqp->done_status == QD_NO_ERROR &&
6262             scsiqp->host_status == QHSTA_NO_ERROR) {
6263                 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6264         }
6265 
6266         asc_scsi_done(scp);
6267 
6268         /*
6269          * Free all 'adv_sgblk_t' structures allocated for the request.
6270          */
6271         while ((sgblkp = reqp->sgblkp) != NULL) {
6272                 /* Remove 'sgblkp' from the request list. */
6273                 reqp->sgblkp = sgblkp->next_sgblkp;
6274 
6275                 /* Add 'sgblkp' to the board free list. */
6276                 sgblkp->next_sgblkp = boardp->adv_sgblkp;
6277                 boardp->adv_sgblkp = sgblkp;
6278         }
6279 
6280         /*
6281          * Free the adv_req_t structure used with the command by adding
6282          * it back to the board free list.
6283          */
6284         reqp->next_reqp = boardp->adv_reqp;
6285         boardp->adv_reqp = reqp;
6286 
6287         ASC_DBG(1, "done\n");
6288 }
6289 
6290 /*
6291  * Adv Library Interrupt Service Routine
6292  *
6293  *  This function is called by a driver's interrupt service routine.
6294  *  The function disables and re-enables interrupts.
6295  *
6296  *  When a microcode idle command is completed, the ADV_DVC_VAR
6297  *  'idle_cmd_done' field is set to ADV_TRUE.
6298  *
6299  *  Note: AdvISR() can be called when interrupts are disabled or even
6300  *  when there is no hardware interrupt condition present. It will
6301  *  always check for completed idle commands and microcode requests.
6302  *  This is an important feature that shouldn't be changed because it
6303  *  allows commands to be completed from polling mode loops.
6304  *
6305  * Return:
6306  *   ADV_TRUE(1) - interrupt was pending
6307  *   ADV_FALSE(0) - no interrupt was pending
6308  */
6309 static int AdvISR(ADV_DVC_VAR *asc_dvc)
6310 {
6311         AdvPortAddr iop_base;
6312         uchar int_stat;
6313         ushort target_bit;
6314         ADV_CARR_T *free_carrp;
6315         ADV_VADDR irq_next_vpa;
6316         ADV_SCSI_REQ_Q *scsiq;
6317 
6318         iop_base = asc_dvc->iop_base;
6319 
6320         /* Reading the register clears the interrupt. */
6321         int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
6322 
6323         if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
6324                          ADV_INTR_STATUS_INTRC)) == 0) {
6325                 return ADV_FALSE;
6326         }
6327 
6328         /*
6329          * Notify the driver of an asynchronous microcode condition by
6330          * calling the adv_async_callback function. The function
6331          * is passed the microcode ASC_MC_INTRB_CODE byte value.
6332          */
6333         if (int_stat & ADV_INTR_STATUS_INTRB) {
6334                 uchar intrb_code;
6335 
6336                 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
6337 
6338                 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
6339                     asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
6340                         if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
6341                             asc_dvc->carr_pending_cnt != 0) {
6342                                 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
6343                                                      ADV_TICKLE_A);
6344                                 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
6345                                         AdvWriteByteRegister(iop_base,
6346                                                              IOPB_TICKLE,
6347                                                              ADV_TICKLE_NOP);
6348                                 }
6349                         }
6350                 }
6351 
6352                 adv_async_callback(asc_dvc, intrb_code);
6353         }
6354 
6355         /*
6356          * Check if the IRQ stopper carrier contains a completed request.
6357          */
6358         while (((irq_next_vpa =
6359                  le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) {
6360                 /*
6361                  * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
6362                  * The RISC will have set 'areq_vpa' to a virtual address.
6363                  *
6364                  * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
6365                  * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
6366                  * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
6367                  * in AdvExeScsiQueue().
6368                  */
6369                 scsiq = (ADV_SCSI_REQ_Q *)
6370                     ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->areq_vpa));
6371 
6372                 /*
6373                  * Request finished with good status and the queue was not
6374                  * DMAed to host memory by the firmware. Set all status fields
6375                  * to indicate good status.
6376                  */
6377                 if ((irq_next_vpa & ASC_RQ_GOOD) != 0) {
6378                         scsiq->done_status = QD_NO_ERROR;
6379                         scsiq->host_status = scsiq->scsi_status = 0;
6380                         scsiq->data_cnt = 0L;
6381                 }
6382 
6383                 /*
6384                  * Advance the stopper pointer to the next carrier
6385                  * ignoring the lower four bits. Free the previous
6386                  * stopper carrier.
6387                  */
6388                 free_carrp = asc_dvc->irq_sp;
6389                 asc_dvc->irq_sp = (ADV_CARR_T *)
6390                     ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa));
6391 
6392                 free_carrp->next_vpa =
6393                     cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
6394                 asc_dvc->carr_freelist = free_carrp;
6395                 asc_dvc->carr_pending_cnt--;
6396 
6397                 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
6398 
6399                 /*
6400                  * Clear request microcode control flag.
6401                  */
6402                 scsiq->cntl = 0;
6403 
6404                 /*
6405                  * Notify the driver of the completed request by passing
6406                  * the ADV_SCSI_REQ_Q pointer to its callback function.
6407                  */
6408                 scsiq->a_flag |= ADV_SCSIQ_DONE;
6409                 adv_isr_callback(asc_dvc, scsiq);
6410                 /*
6411                  * Note: After the driver callback function is called, 'scsiq'
6412                  * can no longer be referenced.
6413                  *
6414                  * Fall through and continue processing other completed
6415                  * requests...
6416                  */
6417         }
6418         return ADV_TRUE;
6419 }
6420 
6421 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
6422 {
6423         if (asc_dvc->err_code == 0) {
6424                 asc_dvc->err_code = err_code;
6425                 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
6426                                  err_code);
6427         }
6428         return err_code;
6429 }
6430 
6431 static void AscAckInterrupt(PortAddr iop_base)
6432 {
6433         uchar host_flag;
6434         uchar risc_flag;
6435         ushort loop;
6436 
6437         loop = 0;
6438         do {
6439                 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
6440                 if (loop++ > 0x7FFF) {
6441                         break;
6442                 }
6443         } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
6444         host_flag =
6445             AscReadLramByte(iop_base,
6446                             ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
6447         AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
6448                          (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
6449         AscSetChipStatus(iop_base, CIW_INT_ACK);
6450         loop = 0;
6451         while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
6452                 AscSetChipStatus(iop_base, CIW_INT_ACK);
6453                 if (loop++ > 3) {
6454                         break;
6455                 }
6456         }
6457         AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
6458 }
6459 
6460 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
6461 {
6462         const uchar *period_table;
6463         int max_index;
6464         int min_index;
6465         int i;
6466 
6467         period_table = asc_dvc->sdtr_period_tbl;
6468         max_index = (int)asc_dvc->max_sdtr_index;
6469         min_index = (int)asc_dvc->min_sdtr_index;
6470         if ((syn_time <= period_table[max_index])) {
6471                 for (i = min_index; i < (max_index - 1); i++) {
6472                         if (syn_time <= period_table[i]) {
6473                                 return (uchar)i;
6474                         }
6475                 }
6476                 return (uchar)max_index;
6477         } else {
6478                 return (uchar)(max_index + 1);
6479         }
6480 }
6481 
6482 static uchar
6483 AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
6484 {
6485         EXT_MSG sdtr_buf;
6486         uchar sdtr_period_index;
6487         PortAddr iop_base;
6488 
6489         iop_base = asc_dvc->iop_base;
6490         sdtr_buf.msg_type = EXTENDED_MESSAGE;
6491         sdtr_buf.msg_len = MS_SDTR_LEN;
6492         sdtr_buf.msg_req = EXTENDED_SDTR;
6493         sdtr_buf.xfer_period = sdtr_period;
6494         sdtr_offset &= ASC_SYN_MAX_OFFSET;
6495         sdtr_buf.req_ack_offset = sdtr_offset;
6496         sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6497         if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
6498                 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6499                                         (uchar *)&sdtr_buf,
6500                                         sizeof(EXT_MSG) >> 1);
6501                 return ((sdtr_period_index << 4) | sdtr_offset);
6502         } else {
6503                 sdtr_buf.req_ack_offset = 0;
6504                 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6505                                         (uchar *)&sdtr_buf,
6506                                         sizeof(EXT_MSG) >> 1);
6507                 return 0;
6508         }
6509 }
6510 
6511 static uchar
6512 AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
6513 {
6514         uchar byte;
6515         uchar sdtr_period_ix;
6516 
6517         sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6518         if (sdtr_period_ix > asc_dvc->max_sdtr_index)
6519                 return 0xFF;
6520         byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
6521         return byte;
6522 }
6523 
6524 static int AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
6525 {
6526         ASC_SCSI_BIT_ID_TYPE org_id;
6527         int i;
6528         int sta = TRUE;
6529 
6530         AscSetBank(iop_base, 1);
6531         org_id = AscReadChipDvcID(iop_base);
6532         for (i = 0; i <= ASC_MAX_TID; i++) {
6533                 if (org_id == (0x01 << i))
6534                         break;
6535         }
6536         org_id = (ASC_SCSI_BIT_ID_TYPE) i;
6537         AscWriteChipDvcID(iop_base, id);
6538         if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
6539                 AscSetBank(iop_base, 0);
6540                 AscSetChipSyn(iop_base, sdtr_data);
6541                 if (AscGetChipSyn(iop_base) != sdtr_data) {
6542                         sta = FALSE;
6543                 }
6544         } else {
6545                 sta = FALSE;
6546         }
6547         AscSetBank(iop_base, 1);
6548         AscWriteChipDvcID(iop_base, org_id);
6549         AscSetBank(iop_base, 0);
6550         return (sta);
6551 }
6552 
6553 static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
6554 {
6555         AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
6556         AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
6557 }
6558 
6559 static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
6560 {
6561         EXT_MSG ext_msg;
6562         EXT_MSG out_msg;
6563         ushort halt_q_addr;
6564         int sdtr_accept;
6565         ushort int_halt_code;
6566         ASC_SCSI_BIT_ID_TYPE scsi_busy;
6567         ASC_SCSI_BIT_ID_TYPE target_id;
6568         PortAddr iop_base;
6569         uchar tag_code;
6570         uchar q_status;
6571         uchar halt_qp;
6572         uchar sdtr_data;
6573         uchar target_ix;
6574         uchar q_cntl, tid_no;
6575         uchar cur_dvc_qng;
6576         uchar asyn_sdtr;
6577         uchar scsi_status;
6578         struct asc_board *boardp;
6579 
6580         BUG_ON(!asc_dvc->drv_ptr);
6581         boardp = asc_dvc->drv_ptr;
6582 
6583         iop_base = asc_dvc->iop_base;
6584         int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
6585 
6586         halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
6587         halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
6588         target_ix = AscReadLramByte(iop_base,
6589                                     (ushort)(halt_q_addr +
6590                                              (ushort)ASC_SCSIQ_B_TARGET_IX));
6591         q_cntl = AscReadLramByte(iop_base,
6592                             (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6593         tid_no = ASC_TIX_TO_TID(target_ix);
6594         target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
6595         if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6596                 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
6597         } else {
6598                 asyn_sdtr = 0;
6599         }
6600         if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
6601                 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6602                         AscSetChipSDTR(iop_base, 0, tid_no);
6603                         boardp->sdtr_data[tid_no] = 0;
6604                 }
6605                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6606                 return (0);
6607         } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
6608                 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6609                         AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6610                         boardp->sdtr_data[tid_no] = asyn_sdtr;
6611                 }
6612                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6613                 return (0);
6614         } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
6615                 AscMemWordCopyPtrFromLram(iop_base,
6616                                           ASCV_MSGIN_BEG,
6617                                           (uchar *)&ext_msg,
6618                                           sizeof(EXT_MSG) >> 1);
6619 
6620                 if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6621                     ext_msg.msg_req == EXTENDED_SDTR &&
6622                     ext_msg.msg_len == MS_SDTR_LEN) {
6623                         sdtr_accept = TRUE;
6624                         if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
6625 
6626                                 sdtr_accept = FALSE;
6627                                 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
6628                         }
6629                         if ((ext_msg.xfer_period <
6630                              asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index])
6631                             || (ext_msg.xfer_period >
6632                                 asc_dvc->sdtr_period_tbl[asc_dvc->
6633                                                          max_sdtr_index])) {
6634                                 sdtr_accept = FALSE;
6635                                 ext_msg.xfer_period =
6636                                     asc_dvc->sdtr_period_tbl[asc_dvc->
6637                                                              min_sdtr_index];
6638                         }
6639                         if (sdtr_accept) {
6640                                 sdtr_data =
6641                                     AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
6642                                                    ext_msg.req_ack_offset);
6643                                 if ((sdtr_data == 0xFF)) {
6644 
6645                                         q_cntl |= QC_MSG_OUT;
6646                                         asc_dvc->init_sdtr &= ~target_id;
6647                                         asc_dvc->sdtr_done &= ~target_id;
6648                                         AscSetChipSDTR(iop_base, asyn_sdtr,
6649                                                        tid_no);
6650                                         boardp->sdtr_data[tid_no] = asyn_sdtr;
6651                                 }
6652                         }
6653                         if (ext_msg.req_ack_offset == 0) {
6654 
6655                                 q_cntl &= ~QC_MSG_OUT;
6656                                 asc_dvc->init_sdtr &= ~target_id;
6657                                 asc_dvc->sdtr_done &= ~target_id;
6658                                 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6659                         } else {
6660                                 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
6661                                         q_cntl &= ~QC_MSG_OUT;
6662                                         asc_dvc->sdtr_done |= target_id;
6663                                         asc_dvc->init_sdtr |= target_id;
6664                                         asc_dvc->pci_fix_asyn_xfer &=
6665                                             ~target_id;
6666                                         sdtr_data =
6667                                             AscCalSDTRData(asc_dvc,
6668                                                            ext_msg.xfer_period,
6669                                                            ext_msg.
6670                                                            req_ack_offset);
6671                                         AscSetChipSDTR(iop_base, sdtr_data,
6672                                                        tid_no);
6673                                         boardp->sdtr_data[tid_no] = sdtr_data;
6674                                 } else {
6675                                         q_cntl |= QC_MSG_OUT;
6676                                         AscMsgOutSDTR(asc_dvc,
6677                                                       ext_msg.xfer_period,
6678                                                       ext_msg.req_ack_offset);
6679                                         asc_dvc->pci_fix_asyn_xfer &=
6680                                             ~target_id;
6681                                         sdtr_data =
6682                                             AscCalSDTRData(asc_dvc,
6683                                                            ext_msg.xfer_period,
6684                                                            ext_msg.
6685                                                            req_ack_offset);
6686                                         AscSetChipSDTR(iop_base, sdtr_data,
6687                                                        tid_no);
6688                                         boardp->sdtr_data[tid_no] = sdtr_data;
6689                                         asc_dvc->sdtr_done |= target_id;
6690                                         asc_dvc->init_sdtr |= target_id;
6691                                 }
6692                         }
6693 
6694                         AscWriteLramByte(iop_base,
6695                                          (ushort)(halt_q_addr +
6696                                                   (ushort)ASC_SCSIQ_B_CNTL),
6697                                          q_cntl);
6698                         AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6699                         return (0);
6700                 } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6701                            ext_msg.msg_req == EXTENDED_WDTR &&
6702                            ext_msg.msg_len == MS_WDTR_LEN) {
6703 
6704                         ext_msg.wdtr_width = 0;
6705                         AscMemWordCopyPtrToLram(iop_base,
6706                                                 ASCV_MSGOUT_BEG,
6707                                                 (uchar *)&ext_msg,
6708                                                 sizeof(EXT_MSG) >> 1);
6709                         q_cntl |= QC_MSG_OUT;
6710                         AscWriteLramByte(iop_base,
6711                                          (ushort)(halt_q_addr +
6712                                                   (ushort)ASC_SCSIQ_B_CNTL),
6713                                          q_cntl);
6714                         AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6715                         return (0);
6716                 } else {
6717 
6718                         ext_msg.msg_type = MESSAGE_REJECT;
6719                         AscMemWordCopyPtrToLram(iop_base,
6720                                                 ASCV_MSGOUT_BEG,
6721                                                 (uchar *)&ext_msg,
6722                                                 sizeof(EXT_MSG) >> 1);
6723                         q_cntl |= QC_MSG_OUT;
6724                         AscWriteLramByte(iop_base,
6725                                          (ushort)(halt_q_addr +
6726                                                   (ushort)ASC_SCSIQ_B_CNTL),
6727                                          q_cntl);
6728                         AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6729                         return (0);
6730                 }
6731         } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
6732 
6733                 q_cntl |= QC_REQ_SENSE;
6734 
6735                 if ((asc_dvc->init_sdtr & target_id) != 0) {
6736 
6737                         asc_dvc->sdtr_done &= ~target_id;
6738 
6739                         sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
6740                         q_cntl |= QC_MSG_OUT;
6741                         AscMsgOutSDTR(asc_dvc,
6742                                       asc_dvc->
6743                                       sdtr_period_tbl[(sdtr_data >> 4) &
6744                                                       (uchar)(asc_dvc->
6745                                                               max_sdtr_index -
6746                                                               1)],
6747                                       (uchar)(sdtr_data & (uchar)
6748                                               ASC_SYN_MAX_OFFSET));
6749                 }
6750 
6751                 AscWriteLramByte(iop_base,
6752                                  (ushort)(halt_q_addr +
6753                                           (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6754 
6755                 tag_code = AscReadLramByte(iop_base,
6756                                            (ushort)(halt_q_addr + (ushort)
6757                                                     ASC_SCSIQ_B_TAG_CODE));
6758                 tag_code &= 0xDC;
6759                 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
6760                     && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
6761                     ) {
6762 
6763                         tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
6764                                      | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
6765 
6766                 }
6767                 AscWriteLramByte(iop_base,
6768                                  (ushort)(halt_q_addr +
6769                                           (ushort)ASC_SCSIQ_B_TAG_CODE),
6770                                  tag_code);
6771 
6772                 q_status = AscReadLramByte(iop_base,
6773                                            (ushort)(halt_q_addr + (ushort)
6774                                                     ASC_SCSIQ_B_STATUS));
6775                 q_status |= (QS_READY | QS_BUSY);
6776                 AscWriteLramByte(iop_base,
6777                                  (ushort)(halt_q_addr +
6778                                           (ushort)ASC_SCSIQ_B_STATUS),
6779                                  q_status);
6780 
6781                 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
6782                 scsi_busy &= ~target_id;
6783                 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6784 
6785                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6786                 return (0);
6787         } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
6788 
6789                 AscMemWordCopyPtrFromLram(iop_base,
6790                                           ASCV_MSGOUT_BEG,
6791                                           (uchar *)&out_msg,
6792                                           sizeof(EXT_MSG) >> 1);
6793 
6794                 if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
6795                     (out_msg.msg_len == MS_SDTR_LEN) &&
6796                     (out_msg.msg_req == EXTENDED_SDTR)) {
6797 
6798                         asc_dvc->init_sdtr &= ~target_id;
6799                         asc_dvc->sdtr_done &= ~target_id;
6800                         AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6801                         boardp->sdtr_data[tid_no] = asyn_sdtr;
6802                 }
6803                 q_cntl &= ~QC_MSG_OUT;
6804                 AscWriteLramByte(iop_base,
6805                                  (ushort)(halt_q_addr +
6806                                           (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6807                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6808                 return (0);
6809         } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
6810 
6811                 scsi_status = AscReadLramByte(iop_base,
6812                                               (ushort)((ushort)halt_q_addr +
6813                                                        (ushort)
6814                                                        ASC_SCSIQ_SCSI_STATUS));
6815                 cur_dvc_qng =
6816                     AscReadLramByte(iop_base,
6817                                     (ushort)((ushort)ASC_QADR_BEG +
6818                                              (ushort)target_ix));
6819                 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
6820 
6821                         scsi_busy = AscReadLramByte(iop_base,
6822                                                     (ushort)ASCV_SCSIBUSY_B);
6823                         scsi_busy |= target_id;
6824                         AscWriteLramByte(iop_base,
6825                                          (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6826                         asc_dvc->queue_full_or_busy |= target_id;
6827 
6828                         if (scsi_status == SAM_STAT_TASK_SET_FULL) {
6829                                 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
6830                                         cur_dvc_qng -= 1;
6831                                         asc_dvc->max_dvc_qng[tid_no] =
6832                                             cur_dvc_qng;
6833 
6834                                         AscWriteLramByte(iop_base,
6835                                                          (ushort)((ushort)
6836                                                                   ASCV_MAX_DVC_QNG_BEG
6837                                                                   + (ushort)
6838                                                                   tid_no),
6839                                                          cur_dvc_qng);
6840 
6841                                         /*
6842                                          * Set the device queue depth to the
6843                                          * number of active requests when the
6844                                          * QUEUE FULL condition was encountered.
6845                                          */
6846                                         boardp->queue_full |= target_id;
6847                                         boardp->queue_full_cnt[tid_no] =
6848                                             cur_dvc_qng;
6849                                 }
6850                         }
6851                 }
6852                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6853                 return (0);
6854         }
6855 #if CC_VERY_LONG_SG_LIST
6856         else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC) {
6857                 uchar q_no;
6858                 ushort q_addr;
6859                 uchar sg_wk_q_no;
6860                 uchar first_sg_wk_q_no;
6861                 ASC_SCSI_Q *scsiq;      /* Ptr to driver request. */
6862                 ASC_SG_HEAD *sg_head;   /* Ptr to driver SG request. */
6863                 ASC_SG_LIST_Q scsi_sg_q;        /* Structure written to queue. */
6864                 ushort sg_list_dwords;
6865                 ushort sg_entry_cnt;
6866                 uchar next_qp;
6867                 int i;
6868 
6869                 q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP);
6870                 if (q_no == ASC_QLINK_END)
6871                         return 0;
6872 
6873                 q_addr = ASC_QNO_TO_QADDR(q_no);
6874 
6875                 /*
6876                  * Convert the request's SRB pointer to a host ASC_SCSI_REQ
6877                  * structure pointer using a macro provided by the driver.
6878                  * The ASC_SCSI_REQ pointer provides a pointer to the
6879                  * host ASC_SG_HEAD structure.
6880                  */
6881                 /* Read request's SRB pointer. */
6882                 scsiq = (ASC_SCSI_Q *)
6883                     ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
6884                                                                     (ushort)
6885                                                                     (q_addr +
6886                                                                      ASC_SCSIQ_D_SRBPTR))));
6887 
6888                 /*
6889                  * Get request's first and working SG queue.
6890                  */
6891                 sg_wk_q_no = AscReadLramByte(iop_base,
6892                                              (ushort)(q_addr +
6893                                                       ASC_SCSIQ_B_SG_WK_QP));
6894 
6895                 first_sg_wk_q_no = AscReadLramByte(iop_base,
6896                                                    (ushort)(q_addr +
6897                                                             ASC_SCSIQ_B_FIRST_SG_WK_QP));
6898 
6899                 /*
6900                  * Reset request's working SG queue back to the
6901                  * first SG queue.
6902                  */
6903                 AscWriteLramByte(iop_base,
6904                                  (ushort)(q_addr +
6905                                           (ushort)ASC_SCSIQ_B_SG_WK_QP),
6906                                  first_sg_wk_q_no);
6907 
6908                 sg_head = scsiq->sg_head;
6909 
6910                 /*
6911                  * Set sg_entry_cnt to the number of SG elements
6912                  * that will be completed on this interrupt.
6913                  *
6914                  * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
6915                  * SG elements. The data_cnt and data_addr fields which
6916                  * add 1 to the SG element capacity are not used when
6917                  * restarting SG handling after a halt.
6918                  */
6919                 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1)) {
6920                         sg_entry_cnt = ASC_MAX_SG_LIST - 1;
6921 
6922                         /*
6923                          * Keep track of remaining number of SG elements that
6924                          * will need to be handled on the next interrupt.
6925                          */
6926                         scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
6927                 } else {
6928                         sg_entry_cnt = scsiq->remain_sg_entry_cnt;
6929                         scsiq->remain_sg_entry_cnt = 0;
6930                 }
6931 
6932                 /*
6933                  * Copy SG elements into the list of allocated SG queues.
6934                  *
6935                  * Last index completed is saved in scsiq->next_sg_index.
6936                  */
6937                 next_qp = first_sg_wk_q_no;
6938                 q_addr = ASC_QNO_TO_QADDR(next_qp);
6939                 scsi_sg_q.sg_head_qp = q_no;
6940                 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
6941                 for (i = 0; i < sg_head->queue_cnt; i++) {
6942                         scsi_sg_q.seq_no = i + 1;
6943                         if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
6944                                 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
6945                                 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
6946                                 /*
6947                                  * After very first SG queue RISC FW uses next
6948                                  * SG queue first element then checks sg_list_cnt
6949                                  * against zero and then decrements, so set
6950                                  * sg_list_cnt 1 less than number of SG elements
6951                                  * in each SG queue.
6952                                  */
6953                                 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
6954                                 scsi_sg_q.sg_cur_list_cnt =
6955                                     ASC_SG_LIST_PER_Q - 1;
6956                         } else {
6957                                 /*
6958                                  * This is the last SG queue in the list of
6959                                  * allocated SG queues. If there are more
6960                                  * SG elements than will fit in the allocated
6961                                  * queues, then set the QCSG_SG_XFER_MORE flag.
6962                                  */
6963                                 if (scsiq->remain_sg_entry_cnt != 0) {
6964                                         scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
6965                                 } else {
6966                                         scsi_sg_q.cntl |= QCSG_SG_XFER_END;
6967                                 }
6968                                 /* equals sg_entry_cnt * 2 */
6969                                 sg_list_dwords = sg_entry_cnt << 1;
6970                                 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
6971                                 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
6972                                 sg_entry_cnt = 0;
6973                         }
6974 
6975                         scsi_sg_q.q_no = next_qp;
6976                         AscMemWordCopyPtrToLram(iop_base,
6977                                                 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
6978                                                 (uchar *)&scsi_sg_q,
6979                                                 sizeof(ASC_SG_LIST_Q) >> 1);
6980 
6981                         AscMemDWordCopyPtrToLram(iop_base,
6982                                                  q_addr + ASC_SGQ_LIST_BEG,
6983                                                  (uchar *)&sg_head->
6984                                                  sg_list[scsiq->next_sg_index],
6985                                                  sg_list_dwords);
6986 
6987                         scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
6988 
6989                         /*
6990                          * If the just completed SG queue contained the
6991                          * last SG element, then no more SG queues need
6992                          * to be written.
6993                          */
6994                         if (scsi_sg_q.cntl & QCSG_SG_XFER_END) {
6995                                 break;
6996                         }
6997 
6998                         next_qp = AscReadLramByte(iop_base,
6999                                                   (ushort)(q_addr +
7000                                                            ASC_SCSIQ_B_FWD));
7001                         q_addr = ASC_QNO_TO_QADDR(next_qp);
7002                 }
7003 
7004                 /*
7005                  * Clear the halt condition so the RISC will be restarted
7006                  * after the return.
7007                  */
7008                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
7009                 return (0);
7010         }
7011 #endif /* CC_VERY_LONG_SG_LIST */
7012         return (0);
7013 }
7014 
7015 /*
7016  * void
7017  * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
7018  *
7019  * Calling/Exit State:
7020  *    none
7021  *
7022  * Description:
7023  *     Input an ASC_QDONE_INFO structure from the chip
7024  */
7025 static void
7026 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
7027 {
7028         int i;
7029         ushort word;
7030 
7031         AscSetChipLramAddr(iop_base, s_addr);
7032         for (i = 0; i < 2 * words; i += 2) {
7033                 if (i == 10) {
7034                         continue;
7035                 }
7036                 word = inpw(iop_base + IOP_RAM_DATA);
7037                 inbuf[i] = word & 0xff;
7038                 inbuf[i + 1] = (word >> 8) & 0xff;
7039         }
7040         ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
7041 }
7042 
7043 static uchar
7044 _AscCopyLramScsiDoneQ(PortAddr iop_base,
7045                       ushort q_addr,
7046                       ASC_QDONE_INFO *scsiq, ASC_DCNT max_dma_count)
7047 {
7048         ushort _val;
7049         uchar sg_queue_cnt;
7050 
7051         DvcGetQinfo(iop_base,
7052                     q_addr + ASC_SCSIQ_DONE_INFO_BEG,
7053                     (uchar *)scsiq,
7054                     (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
7055 
7056         _val = AscReadLramWord(iop_base,
7057                                (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
7058         scsiq->q_status = (uchar)_val;
7059         scsiq->q_no = (uchar)(_val >> 8);
7060         _val = AscReadLramWord(iop_base,
7061                                (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
7062         scsiq->cntl = (uchar)_val;
7063         sg_queue_cnt = (uchar)(_val >> 8);
7064         _val = AscReadLramWord(iop_base,
7065                                (ushort)(q_addr +
7066                                         (ushort)ASC_SCSIQ_B_SENSE_LEN));
7067         scsiq->sense_len = (uchar)_val;
7068         scsiq->extra_bytes = (uchar)(_val >> 8);
7069 
7070         /*
7071          * Read high word of remain bytes from alternate location.
7072          */
7073         scsiq->remain_bytes = (((ADV_DCNT)AscReadLramWord(iop_base,
7074                                                           (ushort)(q_addr +
7075                                                                    (ushort)
7076                                                                    ASC_SCSIQ_W_ALT_DC1)))
7077                                << 16);
7078         /*
7079          * Read low word of remain bytes from original location.
7080          */
7081         scsiq->remain_bytes += AscReadLramWord(iop_base,
7082                                                (ushort)(q_addr + (ushort)
7083                                                         ASC_SCSIQ_DW_REMAIN_XFER_CNT));
7084 
7085         scsiq->remain_bytes &= max_dma_count;
7086         return sg_queue_cnt;
7087 }
7088 
7089 /*
7090  * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
7091  *
7092  * Interrupt callback function for the Narrow SCSI Asc Library.
7093  */
7094 static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
7095 {
7096         struct asc_board *boardp;
7097         struct scsi_cmnd *scp;
7098         struct Scsi_Host *shost;
7099 
7100         ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep);
7101         ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
7102 
7103         scp = advansys_srb_to_ptr(asc_dvc_varp, qdonep->d2.srb_ptr);
7104         if (!scp)
7105                 return;
7106 
7107         ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
7108 
7109         shost = scp->device->host;
7110         ASC_STATS(shost, callback);
7111         ASC_DBG(1, "shost 0x%p\n", shost);
7112 
7113         boardp = shost_priv(shost);
7114         BUG_ON(asc_dvc_varp != &boardp->dvc_var.asc_dvc_var);
7115 
7116         dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
7117                          SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7118         /*
7119          * 'qdonep' contains the command's ending status.
7120          */
7121         switch (qdonep->d3.done_stat) {
7122         case QD_NO_ERROR:
7123                 ASC_DBG(2, "QD_NO_ERROR\n");
7124                 scp->result = 0;
7125 
7126                 /*
7127                  * Check for an underrun condition.
7128                  *
7129                  * If there was no error and an underrun condition, then
7130                  * return the number of underrun bytes.
7131                  */
7132                 if (scsi_bufflen(scp) != 0 && qdonep->remain_bytes != 0 &&
7133                     qdonep->remain_bytes <= scsi_bufflen(scp)) {
7134                         ASC_DBG(1, "underrun condition %u bytes\n",
7135                                  (unsigned)qdonep->remain_bytes);
7136                         scsi_set_resid(scp, qdonep->remain_bytes);
7137                 }
7138                 break;
7139 
7140         case QD_WITH_ERROR:
7141                 ASC_DBG(2, "QD_WITH_ERROR\n");
7142                 switch (qdonep->d3.host_stat) {
7143                 case QHSTA_NO_ERROR:
7144                         if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
7145                                 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
7146                                 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
7147                                                   SCSI_SENSE_BUFFERSIZE);
7148                                 /*
7149                                  * Note: The 'status_byte()' macro used by
7150                                  * target drivers defined in scsi.h shifts the
7151                                  * status byte returned by host drivers right
7152                                  * by 1 bit.  This is why target drivers also
7153                                  * use right shifted status byte definitions.
7154                                  * For instance target drivers use
7155                                  * CHECK_CONDITION, defined to 0x1, instead of
7156                                  * the SCSI defined check condition value of
7157                                  * 0x2. Host drivers are supposed to return
7158                                  * the status byte as it is defined by SCSI.
7159                                  */
7160                                 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
7161                                     STATUS_BYTE(qdonep->d3.scsi_stat);
7162                         } else {
7163                                 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
7164                         }
7165                         break;
7166 
7167                 default:
7168                         /* QHSTA error occurred */
7169                         ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat);
7170                         scp->result = HOST_BYTE(DID_BAD_TARGET);
7171                         break;
7172                 }
7173                 break;
7174 
7175         case QD_ABORTED_BY_HOST:
7176                 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
7177                 scp->result =
7178                     HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
7179                                                     scsi_msg) |
7180                     STATUS_BYTE(qdonep->d3.scsi_stat);
7181                 break;
7182 
7183         default:
7184                 ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat);
7185                 scp->result =
7186                     HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
7187                                                     scsi_msg) |
7188                     STATUS_BYTE(qdonep->d3.scsi_stat);
7189                 break;
7190         }
7191 
7192         /*
7193          * If the 'init_tidmask' bit isn't already set for the target and the
7194          * current request finished normally, then set the bit for the target
7195          * to indicate that a device is present.
7196          */
7197         if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
7198             qdonep->d3.done_stat == QD_NO_ERROR &&
7199             qdonep->d3.host_stat == QHSTA_NO_ERROR) {
7200                 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
7201         }
7202 
7203         asc_scsi_done(scp);
7204 }
7205 
7206 static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
7207 {
7208         uchar next_qp;
7209         uchar n_q_used;
7210         uchar sg_list_qp;
7211         uchar sg_queue_cnt;
7212         uchar q_cnt;
7213         uchar done_q_tail;
7214         uchar tid_no;
7215         ASC_SCSI_BIT_ID_TYPE scsi_busy;
7216         ASC_SCSI_BIT_ID_TYPE target_id;
7217         PortAddr iop_base;
7218         ushort q_addr;
7219         ushort sg_q_addr;
7220         uchar cur_target_qng;
7221         ASC_QDONE_INFO scsiq_buf;
7222         ASC_QDONE_INFO *scsiq;
7223         int false_overrun;
7224 
7225         iop_base = asc_dvc->iop_base;
7226         n_q_used = 1;
7227         scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
7228         done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
7229         q_addr = ASC_QNO_TO_QADDR(done_q_tail);
7230         next_qp = AscReadLramByte(iop_base,
7231                                   (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
7232         if (next_qp != ASC_QLINK_END) {
7233                 AscPutVarDoneQTail(iop_base, next_qp);
7234                 q_addr = ASC_QNO_TO_QADDR(next_qp);
7235                 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
7236                                                      asc_dvc->max_dma_count);
7237                 AscWriteLramByte(iop_base,
7238                                  (ushort)(q_addr +
7239                                           (ushort)ASC_SCSIQ_B_STATUS),
7240                                  (uchar)(scsiq->
7241                                          q_status & (uchar)~(QS_READY |
7242                                                              QS_ABORTED)));
7243                 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
7244                 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
7245                 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
7246                         sg_q_addr = q_addr;
7247                         sg_list_qp = next_qp;
7248                         for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
7249                                 sg_list_qp = AscReadLramByte(iop_base,
7250                                                              (ushort)(sg_q_addr
7251                                                                       + (ushort)
7252                                                                       ASC_SCSIQ_B_FWD));
7253                                 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
7254                                 if (sg_list_qp == ASC_QLINK_END) {
7255                                         AscSetLibErrorCode(asc_dvc,
7256                                                            ASCQ_ERR_SG_Q_LINKS);
7257                                         scsiq->d3.done_stat = QD_WITH_ERROR;
7258                                         scsiq->d3.host_stat =
7259                                             QHSTA_D_QDONE_SG_LIST_CORRUPTED;
7260                                         goto FATAL_ERR_QDONE;
7261                                 }
7262                                 AscWriteLramByte(iop_base,
7263                                                  (ushort)(sg_q_addr + (ushort)
7264                                                           ASC_SCSIQ_B_STATUS),
7265                                                  QS_FREE);
7266                         }
7267                         n_q_used = sg_queue_cnt + 1;
7268                         AscPutVarDoneQTail(iop_base, sg_list_qp);
7269                 }
7270                 if (asc_dvc->queue_full_or_busy & target_id) {
7271                         cur_target_qng = AscReadLramByte(iop_base,
7272                                                          (ushort)((ushort)
7273                                                                   ASC_QADR_BEG
7274                                                                   + (ushort)
7275                                                                   scsiq->d2.
7276                                                                   target_ix));
7277                         if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
7278                                 scsi_busy = AscReadLramByte(iop_base, (ushort)
7279                                                             ASCV_SCSIBUSY_B);
7280                                 scsi_busy &= ~target_id;
7281                                 AscWriteLramByte(iop_base,
7282                                                  (ushort)ASCV_SCSIBUSY_B,
7283                                                  scsi_busy);
7284                                 asc_dvc->queue_full_or_busy &= ~target_id;
7285                         }
7286                 }
7287                 if (asc_dvc->cur_total_qng >= n_q_used) {
7288                         asc_dvc->cur_total_qng -= n_q_used;
7289                         if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
7290                                 asc_dvc->cur_dvc_qng[tid_no]--;
7291                         }
7292                 } else {
7293                         AscSetLibErrorCode(asc_dvc, ASCQ_E