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Linux/drivers/rtc/rtc-rs5c313.c

  1 /*
  2  * Ricoh RS5C313 RTC device/driver
  3  *  Copyright (C) 2007 Nobuhiro Iwamatsu
  4  *
  5  *  2005-09-19 modifed by kogiidena
  6  *
  7  * Based on the old drivers/char/rs5c313_rtc.c  by:
  8  *  Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
  9  *  Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
 10  *
 11  * Based on code written by Paul Gortmaker.
 12  *  Copyright (C) 1996 Paul Gortmaker
 13  *
 14  * This file is subject to the terms and conditions of the GNU General Public
 15  * License.  See the file "COPYING" in the main directory of this archive
 16  * for more details.
 17  *
 18  * Based on other minimal char device drivers, like Alan's
 19  * watchdog, Ted's random, etc. etc.
 20  *
 21  *      1.07    Paul Gortmaker.
 22  *      1.08    Miquel van Smoorenburg: disallow certain things on the
 23  *              DEC Alpha as the CMOS clock is also used for other things.
 24  *      1.09    Nikita Schmidt: epoch support and some Alpha cleanup.
 25  *      1.09a   Pete Zaitcev: Sun SPARC
 26  *      1.09b   Jeff Garzik: Modularize, init cleanup
 27  *      1.09c   Jeff Garzik: SMP cleanup
 28  *      1.10    Paul Barton-Davis: add support for async I/O
 29  *      1.10a   Andrea Arcangeli: Alpha updates
 30  *      1.10b   Andrew Morton: SMP lock fix
 31  *      1.10c   Cesar Barros: SMP locking fixes and cleanup
 32  *      1.10d   Paul Gortmaker: delete paranoia check in rtc_exit
 33  *      1.10e   Maciej W. Rozycki: Handle DECstation's year weirdness.
 34  *      1.11    Takashi Iwai: Kernel access functions
 35  *                            rtc_register/rtc_unregister/rtc_control
 36  *      1.11a   Daniele Bellucci: Audit create_proc_read_entry in rtc_init
 37  *      1.12    Venkatesh Pallipadi: Hooks for emulating rtc on HPET base-timer
 38  *              CONFIG_HPET_EMULATE_RTC
 39  *      1.13    Nobuhiro Iwamatsu: Updata driver.
 40  */
 41 
 42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 43 
 44 #include <linux/module.h>
 45 #include <linux/err.h>
 46 #include <linux/rtc.h>
 47 #include <linux/platform_device.h>
 48 #include <linux/bcd.h>
 49 #include <linux/delay.h>
 50 #include <linux/io.h>
 51 
 52 #define DRV_NAME        "rs5c313"
 53 #define DRV_VERSION     "1.13"
 54 
 55 #ifdef CONFIG_SH_LANDISK
 56 /*****************************************************/
 57 /* LANDISK dependence part of RS5C313                */
 58 /*****************************************************/
 59 
 60 #define SCSMR1          0xFFE00000
 61 #define SCSCR1          0xFFE00008
 62 #define SCSMR1_CA       0x80
 63 #define SCSCR1_CKE      0x03
 64 #define SCSPTR1         0xFFE0001C
 65 #define SCSPTR1_EIO     0x80
 66 #define SCSPTR1_SPB1IO  0x08
 67 #define SCSPTR1_SPB1DT  0x04
 68 #define SCSPTR1_SPB0IO  0x02
 69 #define SCSPTR1_SPB0DT  0x01
 70 
 71 #define SDA_OEN         SCSPTR1_SPB1IO
 72 #define SDA             SCSPTR1_SPB1DT
 73 #define SCL_OEN         SCSPTR1_SPB0IO
 74 #define SCL             SCSPTR1_SPB0DT
 75 
 76 /* RICOH RS5C313 CE port */
 77 #define RS5C313_CE      0xB0000003
 78 
 79 /* RICOH RS5C313 CE port bit */
 80 #define RS5C313_CE_RTCCE        0x02
 81 
 82 /* SCSPTR1 data */
 83 unsigned char scsptr1_data;
 84 
 85 #define RS5C313_CEENABLE    __raw_writeb(RS5C313_CE_RTCCE, RS5C313_CE);
 86 #define RS5C313_CEDISABLE   __raw_writeb(0x00, RS5C313_CE)
 87 #define RS5C313_MISCOP      __raw_writeb(0x02, 0xB0000008)
 88 
 89 static void rs5c313_init_port(void)
 90 {
 91         /* Set SCK as I/O port and Initialize SCSPTR1 data & I/O port. */
 92         __raw_writeb(__raw_readb(SCSMR1) & ~SCSMR1_CA, SCSMR1);
 93         __raw_writeb(__raw_readb(SCSCR1) & ~SCSCR1_CKE, SCSCR1);
 94 
 95         /* And Initialize SCL for RS5C313 clock */
 96         scsptr1_data = __raw_readb(SCSPTR1) | SCL;      /* SCL:H */
 97         __raw_writeb(scsptr1_data, SCSPTR1);
 98         scsptr1_data = __raw_readb(SCSPTR1) | SCL_OEN;  /* SCL output enable */
 99         __raw_writeb(scsptr1_data, SCSPTR1);
100         RS5C313_CEDISABLE;      /* CE:L */
101 }
102 
103 static void rs5c313_write_data(unsigned char data)
104 {
105         int i;
106 
107         for (i = 0; i < 8; i++) {
108                 /* SDA:Write Data */
109                 scsptr1_data = (scsptr1_data & ~SDA) |
110                                 ((((0x80 >> i) & data) >> (7 - i)) << 2);
111                 __raw_writeb(scsptr1_data, SCSPTR1);
112                 if (i == 0) {
113                         scsptr1_data |= SDA_OEN;        /* SDA:output enable */
114                         __raw_writeb(scsptr1_data, SCSPTR1);
115                 }
116                 ndelay(700);
117                 scsptr1_data &= ~SCL;   /* SCL:L */
118                 __raw_writeb(scsptr1_data, SCSPTR1);
119                 ndelay(700);
120                 scsptr1_data |= SCL;    /* SCL:H */
121                 __raw_writeb(scsptr1_data, SCSPTR1);
122         }
123 
124         scsptr1_data &= ~SDA_OEN;       /* SDA:output disable */
125         __raw_writeb(scsptr1_data, SCSPTR1);
126 }
127 
128 static unsigned char rs5c313_read_data(void)
129 {
130         int i;
131         unsigned char data = 0;
132 
133         for (i = 0; i < 8; i++) {
134                 ndelay(700);
135                 /* SDA:Read Data */
136                 data |= ((__raw_readb(SCSPTR1) & SDA) >> 2) << (7 - i);
137                 scsptr1_data &= ~SCL;   /* SCL:L */
138                 __raw_writeb(scsptr1_data, SCSPTR1);
139                 ndelay(700);
140                 scsptr1_data |= SCL;    /* SCL:H */
141                 __raw_writeb(scsptr1_data, SCSPTR1);
142         }
143         return data & 0x0F;
144 }
145 
146 #endif /* CONFIG_SH_LANDISK */
147 
148 /*****************************************************/
149 /* machine independence part of RS5C313              */
150 /*****************************************************/
151 
152 /* RICOH RS5C313 address */
153 #define RS5C313_ADDR_SEC        0x00
154 #define RS5C313_ADDR_SEC10      0x01
155 #define RS5C313_ADDR_MIN        0x02
156 #define RS5C313_ADDR_MIN10      0x03
157 #define RS5C313_ADDR_HOUR       0x04
158 #define RS5C313_ADDR_HOUR10     0x05
159 #define RS5C313_ADDR_WEEK       0x06
160 #define RS5C313_ADDR_INTINTVREG 0x07
161 #define RS5C313_ADDR_DAY        0x08
162 #define RS5C313_ADDR_DAY10      0x09
163 #define RS5C313_ADDR_MON        0x0A
164 #define RS5C313_ADDR_MON10      0x0B
165 #define RS5C313_ADDR_YEAR       0x0C
166 #define RS5C313_ADDR_YEAR10     0x0D
167 #define RS5C313_ADDR_CNTREG     0x0E
168 #define RS5C313_ADDR_TESTREG    0x0F
169 
170 /* RICOH RS5C313 control register */
171 #define RS5C313_CNTREG_ADJ_BSY  0x01
172 #define RS5C313_CNTREG_WTEN_XSTP        0x02
173 #define RS5C313_CNTREG_12_24    0x04
174 #define RS5C313_CNTREG_CTFG     0x08
175 
176 /* RICOH RS5C313 test register */
177 #define RS5C313_TESTREG_TEST    0x01
178 
179 /* RICOH RS5C313 control bit */
180 #define RS5C313_CNTBIT_READ     0x40
181 #define RS5C313_CNTBIT_AD       0x20
182 #define RS5C313_CNTBIT_DT       0x10
183 
184 static unsigned char rs5c313_read_reg(unsigned char addr)
185 {
186 
187         rs5c313_write_data(addr | RS5C313_CNTBIT_READ | RS5C313_CNTBIT_AD);
188         return rs5c313_read_data();
189 }
190 
191 static void rs5c313_write_reg(unsigned char addr, unsigned char data)
192 {
193         data &= 0x0f;
194         rs5c313_write_data(addr | RS5C313_CNTBIT_AD);
195         rs5c313_write_data(data | RS5C313_CNTBIT_DT);
196         return;
197 }
198 
199 static inline unsigned char rs5c313_read_cntreg(void)
200 {
201         return rs5c313_read_reg(RS5C313_ADDR_CNTREG);
202 }
203 
204 static inline void rs5c313_write_cntreg(unsigned char data)
205 {
206         rs5c313_write_reg(RS5C313_ADDR_CNTREG, data);
207 }
208 
209 static inline void rs5c313_write_intintvreg(unsigned char data)
210 {
211         rs5c313_write_reg(RS5C313_ADDR_INTINTVREG, data);
212 }
213 
214 static int rs5c313_rtc_read_time(struct device *dev, struct rtc_time *tm)
215 {
216         int data;
217         int cnt;
218 
219         cnt = 0;
220         while (1) {
221                 RS5C313_CEENABLE;       /* CE:H */
222 
223                 /* Initialize control reg. 24 hour */
224                 rs5c313_write_cntreg(0x04);
225 
226                 if (!(rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY))
227                         break;
228 
229                 RS5C313_CEDISABLE;
230                 ndelay(700);    /* CE:L */
231 
232                 if (cnt++ > 100) {
233                         dev_err(dev, "%s: timeout error\n", __func__);
234                         return -EIO;
235                 }
236         }
237 
238         data = rs5c313_read_reg(RS5C313_ADDR_SEC);
239         data |= (rs5c313_read_reg(RS5C313_ADDR_SEC10) << 4);
240         tm->tm_sec = bcd2bin(data);
241 
242         data = rs5c313_read_reg(RS5C313_ADDR_MIN);
243         data |= (rs5c313_read_reg(RS5C313_ADDR_MIN10) << 4);
244         tm->tm_min = bcd2bin(data);
245 
246         data = rs5c313_read_reg(RS5C313_ADDR_HOUR);
247         data |= (rs5c313_read_reg(RS5C313_ADDR_HOUR10) << 4);
248         tm->tm_hour = bcd2bin(data);
249 
250         data = rs5c313_read_reg(RS5C313_ADDR_DAY);
251         data |= (rs5c313_read_reg(RS5C313_ADDR_DAY10) << 4);
252         tm->tm_mday = bcd2bin(data);
253 
254         data = rs5c313_read_reg(RS5C313_ADDR_MON);
255         data |= (rs5c313_read_reg(RS5C313_ADDR_MON10) << 4);
256         tm->tm_mon = bcd2bin(data) - 1;
257 
258         data = rs5c313_read_reg(RS5C313_ADDR_YEAR);
259         data |= (rs5c313_read_reg(RS5C313_ADDR_YEAR10) << 4);
260         tm->tm_year = bcd2bin(data);
261 
262         if (tm->tm_year < 70)
263                 tm->tm_year += 100;
264 
265         data = rs5c313_read_reg(RS5C313_ADDR_WEEK);
266         tm->tm_wday = bcd2bin(data);
267 
268         RS5C313_CEDISABLE;
269         ndelay(700);            /* CE:L */
270 
271         return 0;
272 }
273 
274 static int rs5c313_rtc_set_time(struct device *dev, struct rtc_time *tm)
275 {
276         int data;
277         int cnt;
278 
279         cnt = 0;
280         /* busy check. */
281         while (1) {
282                 RS5C313_CEENABLE;       /* CE:H */
283 
284                 /* Initiatlize control reg. 24 hour */
285                 rs5c313_write_cntreg(0x04);
286 
287                 if (!(rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY))
288                         break;
289                 RS5C313_MISCOP;
290                 RS5C313_CEDISABLE;
291                 ndelay(700);    /* CE:L */
292 
293                 if (cnt++ > 100) {
294                         dev_err(dev, "%s: timeout error\n", __func__);
295                         return -EIO;
296                 }
297         }
298 
299         data = bin2bcd(tm->tm_sec);
300         rs5c313_write_reg(RS5C313_ADDR_SEC, data);
301         rs5c313_write_reg(RS5C313_ADDR_SEC10, (data >> 4));
302 
303         data = bin2bcd(tm->tm_min);
304         rs5c313_write_reg(RS5C313_ADDR_MIN, data);
305         rs5c313_write_reg(RS5C313_ADDR_MIN10, (data >> 4));
306 
307         data = bin2bcd(tm->tm_hour);
308         rs5c313_write_reg(RS5C313_ADDR_HOUR, data);
309         rs5c313_write_reg(RS5C313_ADDR_HOUR10, (data >> 4));
310 
311         data = bin2bcd(tm->tm_mday);
312         rs5c313_write_reg(RS5C313_ADDR_DAY, data);
313         rs5c313_write_reg(RS5C313_ADDR_DAY10, (data >> 4));
314 
315         data = bin2bcd(tm->tm_mon + 1);
316         rs5c313_write_reg(RS5C313_ADDR_MON, data);
317         rs5c313_write_reg(RS5C313_ADDR_MON10, (data >> 4));
318 
319         data = bin2bcd(tm->tm_year % 100);
320         rs5c313_write_reg(RS5C313_ADDR_YEAR, data);
321         rs5c313_write_reg(RS5C313_ADDR_YEAR10, (data >> 4));
322 
323         data = bin2bcd(tm->tm_wday);
324         rs5c313_write_reg(RS5C313_ADDR_WEEK, data);
325 
326         RS5C313_CEDISABLE;      /* CE:H */
327         ndelay(700);
328 
329         return 0;
330 }
331 
332 static void rs5c313_check_xstp_bit(void)
333 {
334         struct rtc_time tm;
335         int cnt;
336 
337         RS5C313_CEENABLE;       /* CE:H */
338         if (rs5c313_read_cntreg() & RS5C313_CNTREG_WTEN_XSTP) {
339                 /* INT interval reg. OFF */
340                 rs5c313_write_intintvreg(0x00);
341                 /* Initialize control reg. 24 hour & adjust */
342                 rs5c313_write_cntreg(0x07);
343 
344                 /* busy check. */
345                 for (cnt = 0; cnt < 100; cnt++) {
346                         if (!(rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY))
347                                 break;
348                         RS5C313_MISCOP;
349                 }
350 
351                 memset(&tm, 0, sizeof(struct rtc_time));
352                 tm.tm_mday      = 1;
353                 tm.tm_mon       = 1 - 1;
354                 tm.tm_year      = 2000 - 1900;
355 
356                 rs5c313_rtc_set_time(NULL, &tm);
357                 pr_err("invalid value, resetting to 1 Jan 2000\n");
358         }
359         RS5C313_CEDISABLE;
360         ndelay(700);            /* CE:L */
361 }
362 
363 static const struct rtc_class_ops rs5c313_rtc_ops = {
364         .read_time = rs5c313_rtc_read_time,
365         .set_time = rs5c313_rtc_set_time,
366 };
367 
368 static int rs5c313_rtc_probe(struct platform_device *pdev)
369 {
370         struct rtc_device *rtc = devm_rtc_device_register(&pdev->dev, "rs5c313",
371                                 &rs5c313_rtc_ops, THIS_MODULE);
372 
373         if (IS_ERR(rtc))
374                 return PTR_ERR(rtc);
375 
376         platform_set_drvdata(pdev, rtc);
377 
378         return 0;
379 }
380 
381 static struct platform_driver rs5c313_rtc_platform_driver = {
382         .driver         = {
383                 .name   = DRV_NAME,
384                 .owner  = THIS_MODULE,
385         },
386         .probe  = rs5c313_rtc_probe,
387 };
388 
389 static int __init rs5c313_rtc_init(void)
390 {
391         int err;
392 
393         err = platform_driver_register(&rs5c313_rtc_platform_driver);
394         if (err)
395                 return err;
396 
397         rs5c313_init_port();
398         rs5c313_check_xstp_bit();
399 
400         return 0;
401 }
402 
403 static void __exit rs5c313_rtc_exit(void)
404 {
405         platform_driver_unregister(&rs5c313_rtc_platform_driver);
406 }
407 
408 module_init(rs5c313_rtc_init);
409 module_exit(rs5c313_rtc_exit);
410 
411 MODULE_VERSION(DRV_VERSION);
412 MODULE_AUTHOR("kogiidena , Nobuhiro Iwamatsu <iwamatsu@nigauri.org>");
413 MODULE_DESCRIPTION("Ricoh RS5C313 RTC device driver");
414 MODULE_LICENSE("GPL");
415 MODULE_ALIAS("platform:" DRV_NAME);
416 

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