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Linux/drivers/rtc/rtc-omap.c

  1 /*
  2  * TI OMAP Real Time Clock interface for Linux
  3  *
  4  * Copyright (C) 2003 MontaVista Software, Inc.
  5  * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
  6  *
  7  * Copyright (C) 2006 David Brownell (new RTC framework)
  8  * Copyright (C) 2014 Johan Hovold <johan@kernel.org>
  9  *
 10  * This program is free software; you can redistribute it and/or
 11  * modify it under the terms of the GNU General Public License
 12  * as published by the Free Software Foundation; either version
 13  * 2 of the License, or (at your option) any later version.
 14  */
 15 
 16 #include <linux/kernel.h>
 17 #include <linux/init.h>
 18 #include <linux/module.h>
 19 #include <linux/ioport.h>
 20 #include <linux/delay.h>
 21 #include <linux/rtc.h>
 22 #include <linux/bcd.h>
 23 #include <linux/platform_device.h>
 24 #include <linux/of.h>
 25 #include <linux/of_device.h>
 26 #include <linux/pm_runtime.h>
 27 #include <linux/io.h>
 28 #include <linux/clk.h>
 29 
 30 /*
 31  * The OMAP RTC is a year/month/day/hours/minutes/seconds BCD clock
 32  * with century-range alarm matching, driven by the 32kHz clock.
 33  *
 34  * The main user-visible ways it differs from PC RTCs are by omitting
 35  * "don't care" alarm fields and sub-second periodic IRQs, and having
 36  * an autoadjust mechanism to calibrate to the true oscillator rate.
 37  *
 38  * Board-specific wiring options include using split power mode with
 39  * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset),
 40  * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from
 41  * low power modes) for OMAP1 boards (OMAP-L138 has this built into
 42  * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
 43  */
 44 
 45 /* RTC registers */
 46 #define OMAP_RTC_SECONDS_REG            0x00
 47 #define OMAP_RTC_MINUTES_REG            0x04
 48 #define OMAP_RTC_HOURS_REG              0x08
 49 #define OMAP_RTC_DAYS_REG               0x0C
 50 #define OMAP_RTC_MONTHS_REG             0x10
 51 #define OMAP_RTC_YEARS_REG              0x14
 52 #define OMAP_RTC_WEEKS_REG              0x18
 53 
 54 #define OMAP_RTC_ALARM_SECONDS_REG      0x20
 55 #define OMAP_RTC_ALARM_MINUTES_REG      0x24
 56 #define OMAP_RTC_ALARM_HOURS_REG        0x28
 57 #define OMAP_RTC_ALARM_DAYS_REG         0x2c
 58 #define OMAP_RTC_ALARM_MONTHS_REG       0x30
 59 #define OMAP_RTC_ALARM_YEARS_REG        0x34
 60 
 61 #define OMAP_RTC_CTRL_REG               0x40
 62 #define OMAP_RTC_STATUS_REG             0x44
 63 #define OMAP_RTC_INTERRUPTS_REG         0x48
 64 
 65 #define OMAP_RTC_COMP_LSB_REG           0x4c
 66 #define OMAP_RTC_COMP_MSB_REG           0x50
 67 #define OMAP_RTC_OSC_REG                0x54
 68 
 69 #define OMAP_RTC_KICK0_REG              0x6c
 70 #define OMAP_RTC_KICK1_REG              0x70
 71 
 72 #define OMAP_RTC_IRQWAKEEN              0x7c
 73 
 74 #define OMAP_RTC_ALARM2_SECONDS_REG     0x80
 75 #define OMAP_RTC_ALARM2_MINUTES_REG     0x84
 76 #define OMAP_RTC_ALARM2_HOURS_REG       0x88
 77 #define OMAP_RTC_ALARM2_DAYS_REG        0x8c
 78 #define OMAP_RTC_ALARM2_MONTHS_REG      0x90
 79 #define OMAP_RTC_ALARM2_YEARS_REG       0x94
 80 
 81 #define OMAP_RTC_PMIC_REG               0x98
 82 
 83 /* OMAP_RTC_CTRL_REG bit fields: */
 84 #define OMAP_RTC_CTRL_SPLIT             BIT(7)
 85 #define OMAP_RTC_CTRL_DISABLE           BIT(6)
 86 #define OMAP_RTC_CTRL_SET_32_COUNTER    BIT(5)
 87 #define OMAP_RTC_CTRL_TEST              BIT(4)
 88 #define OMAP_RTC_CTRL_MODE_12_24        BIT(3)
 89 #define OMAP_RTC_CTRL_AUTO_COMP         BIT(2)
 90 #define OMAP_RTC_CTRL_ROUND_30S         BIT(1)
 91 #define OMAP_RTC_CTRL_STOP              BIT(0)
 92 
 93 /* OMAP_RTC_STATUS_REG bit fields: */
 94 #define OMAP_RTC_STATUS_POWER_UP        BIT(7)
 95 #define OMAP_RTC_STATUS_ALARM2          BIT(7)
 96 #define OMAP_RTC_STATUS_ALARM           BIT(6)
 97 #define OMAP_RTC_STATUS_1D_EVENT        BIT(5)
 98 #define OMAP_RTC_STATUS_1H_EVENT        BIT(4)
 99 #define OMAP_RTC_STATUS_1M_EVENT        BIT(3)
100 #define OMAP_RTC_STATUS_1S_EVENT        BIT(2)
101 #define OMAP_RTC_STATUS_RUN             BIT(1)
102 #define OMAP_RTC_STATUS_BUSY            BIT(0)
103 
104 /* OMAP_RTC_INTERRUPTS_REG bit fields: */
105 #define OMAP_RTC_INTERRUPTS_IT_ALARM2   BIT(4)
106 #define OMAP_RTC_INTERRUPTS_IT_ALARM    BIT(3)
107 #define OMAP_RTC_INTERRUPTS_IT_TIMER    BIT(2)
108 
109 /* OMAP_RTC_OSC_REG bit fields: */
110 #define OMAP_RTC_OSC_32KCLK_EN          BIT(6)
111 #define OMAP_RTC_OSC_SEL_32KCLK_SRC     BIT(3)
112 
113 /* OMAP_RTC_IRQWAKEEN bit fields: */
114 #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1)
115 
116 /* OMAP_RTC_PMIC bit fields: */
117 #define OMAP_RTC_PMIC_POWER_EN_EN       BIT(16)
118 
119 /* OMAP_RTC_KICKER values */
120 #define KICK0_VALUE                     0x83e70b13
121 #define KICK1_VALUE                     0x95a4f1e0
122 
123 struct omap_rtc;
124 
125 struct omap_rtc_device_type {
126         bool has_32kclk_en;
127         bool has_irqwakeen;
128         bool has_pmic_mode;
129         bool has_power_up_reset;
130         void (*lock)(struct omap_rtc *rtc);
131         void (*unlock)(struct omap_rtc *rtc);
132 };
133 
134 struct omap_rtc {
135         struct rtc_device *rtc;
136         void __iomem *base;
137         struct clk *clk;
138         int irq_alarm;
139         int irq_timer;
140         u8 interrupts_reg;
141         bool is_pmic_controller;
142         bool has_ext_clk;
143         const struct omap_rtc_device_type *type;
144 };
145 
146 static inline u8 rtc_read(struct omap_rtc *rtc, unsigned int reg)
147 {
148         return readb(rtc->base + reg);
149 }
150 
151 static inline u32 rtc_readl(struct omap_rtc *rtc, unsigned int reg)
152 {
153         return readl(rtc->base + reg);
154 }
155 
156 static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val)
157 {
158         writeb(val, rtc->base + reg);
159 }
160 
161 static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val)
162 {
163         writel(val, rtc->base + reg);
164 }
165 
166 static void am3352_rtc_unlock(struct omap_rtc *rtc)
167 {
168         rtc_writel(rtc, OMAP_RTC_KICK0_REG, KICK0_VALUE);
169         rtc_writel(rtc, OMAP_RTC_KICK1_REG, KICK1_VALUE);
170 }
171 
172 static void am3352_rtc_lock(struct omap_rtc *rtc)
173 {
174         rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0);
175         rtc_writel(rtc, OMAP_RTC_KICK1_REG, 0);
176 }
177 
178 static void default_rtc_unlock(struct omap_rtc *rtc)
179 {
180 }
181 
182 static void default_rtc_lock(struct omap_rtc *rtc)
183 {
184 }
185 
186 /*
187  * We rely on the rtc framework to handle locking (rtc->ops_lock),
188  * so the only other requirement is that register accesses which
189  * require BUSY to be clear are made with IRQs locally disabled
190  */
191 static void rtc_wait_not_busy(struct omap_rtc *rtc)
192 {
193         int count;
194         u8 status;
195 
196         /* BUSY may stay active for 1/32768 second (~30 usec) */
197         for (count = 0; count < 50; count++) {
198                 status = rtc_read(rtc, OMAP_RTC_STATUS_REG);
199                 if (!(status & OMAP_RTC_STATUS_BUSY))
200                         break;
201                 udelay(1);
202         }
203         /* now we have ~15 usec to read/write various registers */
204 }
205 
206 static irqreturn_t rtc_irq(int irq, void *dev_id)
207 {
208         struct omap_rtc *rtc = dev_id;
209         unsigned long events = 0;
210         u8 irq_data;
211 
212         irq_data = rtc_read(rtc, OMAP_RTC_STATUS_REG);
213 
214         /* alarm irq? */
215         if (irq_data & OMAP_RTC_STATUS_ALARM) {
216                 rtc->type->unlock(rtc);
217                 rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM);
218                 rtc->type->lock(rtc);
219                 events |= RTC_IRQF | RTC_AF;
220         }
221 
222         /* 1/sec periodic/update irq? */
223         if (irq_data & OMAP_RTC_STATUS_1S_EVENT)
224                 events |= RTC_IRQF | RTC_UF;
225 
226         rtc_update_irq(rtc->rtc, 1, events);
227 
228         return IRQ_HANDLED;
229 }
230 
231 static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
232 {
233         struct omap_rtc *rtc = dev_get_drvdata(dev);
234         u8 reg, irqwake_reg = 0;
235 
236         local_irq_disable();
237         rtc_wait_not_busy(rtc);
238         reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
239         if (rtc->type->has_irqwakeen)
240                 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
241 
242         if (enabled) {
243                 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
244                 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
245         } else {
246                 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
247                 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
248         }
249         rtc_wait_not_busy(rtc);
250         rtc->type->unlock(rtc);
251         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
252         if (rtc->type->has_irqwakeen)
253                 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
254         rtc->type->lock(rtc);
255         local_irq_enable();
256 
257         return 0;
258 }
259 
260 /* this hardware doesn't support "don't care" alarm fields */
261 static int tm2bcd(struct rtc_time *tm)
262 {
263         if (rtc_valid_tm(tm) != 0)
264                 return -EINVAL;
265 
266         tm->tm_sec = bin2bcd(tm->tm_sec);
267         tm->tm_min = bin2bcd(tm->tm_min);
268         tm->tm_hour = bin2bcd(tm->tm_hour);
269         tm->tm_mday = bin2bcd(tm->tm_mday);
270 
271         tm->tm_mon = bin2bcd(tm->tm_mon + 1);
272 
273         /* epoch == 1900 */
274         if (tm->tm_year < 100 || tm->tm_year > 199)
275                 return -EINVAL;
276         tm->tm_year = bin2bcd(tm->tm_year - 100);
277 
278         return 0;
279 }
280 
281 static void bcd2tm(struct rtc_time *tm)
282 {
283         tm->tm_sec = bcd2bin(tm->tm_sec);
284         tm->tm_min = bcd2bin(tm->tm_min);
285         tm->tm_hour = bcd2bin(tm->tm_hour);
286         tm->tm_mday = bcd2bin(tm->tm_mday);
287         tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
288         /* epoch == 1900 */
289         tm->tm_year = bcd2bin(tm->tm_year) + 100;
290 }
291 
292 static void omap_rtc_read_time_raw(struct omap_rtc *rtc, struct rtc_time *tm)
293 {
294         tm->tm_sec = rtc_read(rtc, OMAP_RTC_SECONDS_REG);
295         tm->tm_min = rtc_read(rtc, OMAP_RTC_MINUTES_REG);
296         tm->tm_hour = rtc_read(rtc, OMAP_RTC_HOURS_REG);
297         tm->tm_mday = rtc_read(rtc, OMAP_RTC_DAYS_REG);
298         tm->tm_mon = rtc_read(rtc, OMAP_RTC_MONTHS_REG);
299         tm->tm_year = rtc_read(rtc, OMAP_RTC_YEARS_REG);
300 }
301 
302 static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm)
303 {
304         struct omap_rtc *rtc = dev_get_drvdata(dev);
305 
306         /* we don't report wday/yday/isdst ... */
307         local_irq_disable();
308         rtc_wait_not_busy(rtc);
309         omap_rtc_read_time_raw(rtc, tm);
310         local_irq_enable();
311 
312         bcd2tm(tm);
313 
314         return 0;
315 }
316 
317 static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm)
318 {
319         struct omap_rtc *rtc = dev_get_drvdata(dev);
320 
321         if (tm2bcd(tm) < 0)
322                 return -EINVAL;
323 
324         local_irq_disable();
325         rtc_wait_not_busy(rtc);
326 
327         rtc->type->unlock(rtc);
328         rtc_write(rtc, OMAP_RTC_YEARS_REG, tm->tm_year);
329         rtc_write(rtc, OMAP_RTC_MONTHS_REG, tm->tm_mon);
330         rtc_write(rtc, OMAP_RTC_DAYS_REG, tm->tm_mday);
331         rtc_write(rtc, OMAP_RTC_HOURS_REG, tm->tm_hour);
332         rtc_write(rtc, OMAP_RTC_MINUTES_REG, tm->tm_min);
333         rtc_write(rtc, OMAP_RTC_SECONDS_REG, tm->tm_sec);
334         rtc->type->lock(rtc);
335 
336         local_irq_enable();
337 
338         return 0;
339 }
340 
341 static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
342 {
343         struct omap_rtc *rtc = dev_get_drvdata(dev);
344         u8 interrupts;
345 
346         local_irq_disable();
347         rtc_wait_not_busy(rtc);
348 
349         alm->time.tm_sec = rtc_read(rtc, OMAP_RTC_ALARM_SECONDS_REG);
350         alm->time.tm_min = rtc_read(rtc, OMAP_RTC_ALARM_MINUTES_REG);
351         alm->time.tm_hour = rtc_read(rtc, OMAP_RTC_ALARM_HOURS_REG);
352         alm->time.tm_mday = rtc_read(rtc, OMAP_RTC_ALARM_DAYS_REG);
353         alm->time.tm_mon = rtc_read(rtc, OMAP_RTC_ALARM_MONTHS_REG);
354         alm->time.tm_year = rtc_read(rtc, OMAP_RTC_ALARM_YEARS_REG);
355 
356         local_irq_enable();
357 
358         bcd2tm(&alm->time);
359 
360         interrupts = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
361         alm->enabled = !!(interrupts & OMAP_RTC_INTERRUPTS_IT_ALARM);
362 
363         return 0;
364 }
365 
366 static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
367 {
368         struct omap_rtc *rtc = dev_get_drvdata(dev);
369         u8 reg, irqwake_reg = 0;
370 
371         if (tm2bcd(&alm->time) < 0)
372                 return -EINVAL;
373 
374         local_irq_disable();
375         rtc_wait_not_busy(rtc);
376 
377         rtc->type->unlock(rtc);
378         rtc_write(rtc, OMAP_RTC_ALARM_YEARS_REG, alm->time.tm_year);
379         rtc_write(rtc, OMAP_RTC_ALARM_MONTHS_REG, alm->time.tm_mon);
380         rtc_write(rtc, OMAP_RTC_ALARM_DAYS_REG, alm->time.tm_mday);
381         rtc_write(rtc, OMAP_RTC_ALARM_HOURS_REG, alm->time.tm_hour);
382         rtc_write(rtc, OMAP_RTC_ALARM_MINUTES_REG, alm->time.tm_min);
383         rtc_write(rtc, OMAP_RTC_ALARM_SECONDS_REG, alm->time.tm_sec);
384 
385         reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
386         if (rtc->type->has_irqwakeen)
387                 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
388 
389         if (alm->enabled) {
390                 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
391                 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
392         } else {
393                 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
394                 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
395         }
396         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
397         if (rtc->type->has_irqwakeen)
398                 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
399         rtc->type->lock(rtc);
400 
401         local_irq_enable();
402 
403         return 0;
404 }
405 
406 static struct omap_rtc *omap_rtc_power_off_rtc;
407 
408 /*
409  * omap_rtc_poweroff: RTC-controlled power off
410  *
411  * The RTC can be used to control an external PMIC via the pmic_power_en pin,
412  * which can be configured to transition to OFF on ALARM2 events.
413  *
414  * Notes:
415  * The two-second alarm offset is the shortest offset possible as the alarm
416  * registers must be set before the next timer update and the offset
417  * calculation is too heavy for everything to be done within a single access
418  * period (~15 us).
419  *
420  * Called with local interrupts disabled.
421  */
422 static void omap_rtc_power_off(void)
423 {
424         struct omap_rtc *rtc = omap_rtc_power_off_rtc;
425         struct rtc_time tm;
426         unsigned long now;
427         u32 val;
428 
429         rtc->type->unlock(rtc);
430         /* enable pmic_power_en control */
431         val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
432         rtc_writel(rtc, OMAP_RTC_PMIC_REG, val | OMAP_RTC_PMIC_POWER_EN_EN);
433 
434         /* set alarm two seconds from now */
435         omap_rtc_read_time_raw(rtc, &tm);
436         bcd2tm(&tm);
437         rtc_tm_to_time(&tm, &now);
438         rtc_time_to_tm(now + 2, &tm);
439 
440         if (tm2bcd(&tm) < 0) {
441                 dev_err(&rtc->rtc->dev, "power off failed\n");
442                 return;
443         }
444 
445         rtc_wait_not_busy(rtc);
446 
447         rtc_write(rtc, OMAP_RTC_ALARM2_SECONDS_REG, tm.tm_sec);
448         rtc_write(rtc, OMAP_RTC_ALARM2_MINUTES_REG, tm.tm_min);
449         rtc_write(rtc, OMAP_RTC_ALARM2_HOURS_REG, tm.tm_hour);
450         rtc_write(rtc, OMAP_RTC_ALARM2_DAYS_REG, tm.tm_mday);
451         rtc_write(rtc, OMAP_RTC_ALARM2_MONTHS_REG, tm.tm_mon);
452         rtc_write(rtc, OMAP_RTC_ALARM2_YEARS_REG, tm.tm_year);
453 
454         /*
455          * enable ALARM2 interrupt
456          *
457          * NOTE: this fails on AM3352 if rtc_write (writeb) is used
458          */
459         val = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
460         rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG,
461                         val | OMAP_RTC_INTERRUPTS_IT_ALARM2);
462         rtc->type->lock(rtc);
463 
464         /*
465          * Wait for alarm to trigger (within two seconds) and external PMIC to
466          * power off the system. Add a 500 ms margin for external latencies
467          * (e.g. debounce circuits).
468          */
469         mdelay(2500);
470 }
471 
472 static struct rtc_class_ops omap_rtc_ops = {
473         .read_time      = omap_rtc_read_time,
474         .set_time       = omap_rtc_set_time,
475         .read_alarm     = omap_rtc_read_alarm,
476         .set_alarm      = omap_rtc_set_alarm,
477         .alarm_irq_enable = omap_rtc_alarm_irq_enable,
478 };
479 
480 static const struct omap_rtc_device_type omap_rtc_default_type = {
481         .has_power_up_reset = true,
482         .lock           = default_rtc_lock,
483         .unlock         = default_rtc_unlock,
484 };
485 
486 static const struct omap_rtc_device_type omap_rtc_am3352_type = {
487         .has_32kclk_en  = true,
488         .has_irqwakeen  = true,
489         .has_pmic_mode  = true,
490         .lock           = am3352_rtc_lock,
491         .unlock         = am3352_rtc_unlock,
492 };
493 
494 static const struct omap_rtc_device_type omap_rtc_da830_type = {
495         .lock           = am3352_rtc_lock,
496         .unlock         = am3352_rtc_unlock,
497 };
498 
499 static const struct platform_device_id omap_rtc_id_table[] = {
500         {
501                 .name   = "omap_rtc",
502                 .driver_data = (kernel_ulong_t)&omap_rtc_default_type,
503         }, {
504                 .name   = "am3352-rtc",
505                 .driver_data = (kernel_ulong_t)&omap_rtc_am3352_type,
506         }, {
507                 .name   = "da830-rtc",
508                 .driver_data = (kernel_ulong_t)&omap_rtc_da830_type,
509         }, {
510                 /* sentinel */
511         }
512 };
513 MODULE_DEVICE_TABLE(platform, omap_rtc_id_table);
514 
515 static const struct of_device_id omap_rtc_of_match[] = {
516         {
517                 .compatible     = "ti,am3352-rtc",
518                 .data           = &omap_rtc_am3352_type,
519         }, {
520                 .compatible     = "ti,da830-rtc",
521                 .data           = &omap_rtc_da830_type,
522         }, {
523                 /* sentinel */
524         }
525 };
526 MODULE_DEVICE_TABLE(of, omap_rtc_of_match);
527 
528 static int omap_rtc_probe(struct platform_device *pdev)
529 {
530         struct omap_rtc *rtc;
531         struct resource *res;
532         u8 reg, mask, new_ctrl;
533         const struct platform_device_id *id_entry;
534         const struct of_device_id *of_id;
535         int ret;
536 
537         rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
538         if (!rtc)
539                 return -ENOMEM;
540 
541         of_id = of_match_device(omap_rtc_of_match, &pdev->dev);
542         if (of_id) {
543                 rtc->type = of_id->data;
544                 rtc->is_pmic_controller = rtc->type->has_pmic_mode &&
545                                 of_property_read_bool(pdev->dev.of_node,
546                                                 "system-power-controller");
547         } else {
548                 id_entry = platform_get_device_id(pdev);
549                 rtc->type = (void *)id_entry->driver_data;
550         }
551 
552         rtc->irq_timer = platform_get_irq(pdev, 0);
553         if (rtc->irq_timer <= 0)
554                 return -ENOENT;
555 
556         rtc->irq_alarm = platform_get_irq(pdev, 1);
557         if (rtc->irq_alarm <= 0)
558                 return -ENOENT;
559 
560         rtc->clk = devm_clk_get(&pdev->dev, "ext-clk");
561         if (!IS_ERR(rtc->clk))
562                 rtc->has_ext_clk = true;
563         else
564                 rtc->clk = devm_clk_get(&pdev->dev, "int-clk");
565 
566         if (!IS_ERR(rtc->clk))
567                 clk_prepare_enable(rtc->clk);
568 
569         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
570         rtc->base = devm_ioremap_resource(&pdev->dev, res);
571         if (IS_ERR(rtc->base))
572                 return PTR_ERR(rtc->base);
573 
574         platform_set_drvdata(pdev, rtc);
575 
576         /* Enable the clock/module so that we can access the registers */
577         pm_runtime_enable(&pdev->dev);
578         pm_runtime_get_sync(&pdev->dev);
579 
580         rtc->type->unlock(rtc);
581 
582         /*
583          * disable interrupts
584          *
585          * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used
586          */
587         rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
588 
589         /* enable RTC functional clock */
590         if (rtc->type->has_32kclk_en) {
591                 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
592                 rtc_writel(rtc, OMAP_RTC_OSC_REG,
593                                 reg | OMAP_RTC_OSC_32KCLK_EN);
594         }
595 
596         /* clear old status */
597         reg = rtc_read(rtc, OMAP_RTC_STATUS_REG);
598 
599         mask = OMAP_RTC_STATUS_ALARM;
600 
601         if (rtc->type->has_pmic_mode)
602                 mask |= OMAP_RTC_STATUS_ALARM2;
603 
604         if (rtc->type->has_power_up_reset) {
605                 mask |= OMAP_RTC_STATUS_POWER_UP;
606                 if (reg & OMAP_RTC_STATUS_POWER_UP)
607                         dev_info(&pdev->dev, "RTC power up reset detected\n");
608         }
609 
610         if (reg & mask)
611                 rtc_write(rtc, OMAP_RTC_STATUS_REG, reg & mask);
612 
613         /* On boards with split power, RTC_ON_NOFF won't reset the RTC */
614         reg = rtc_read(rtc, OMAP_RTC_CTRL_REG);
615         if (reg & OMAP_RTC_CTRL_STOP)
616                 dev_info(&pdev->dev, "already running\n");
617 
618         /* force to 24 hour mode */
619         new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP);
620         new_ctrl |= OMAP_RTC_CTRL_STOP;
621 
622         /*
623          * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
624          *
625          *  - Device wake-up capability setting should come through chip
626          *    init logic. OMAP1 boards should initialize the "wakeup capable"
627          *    flag in the platform device if the board is wired right for
628          *    being woken up by RTC alarm. For OMAP-L138, this capability
629          *    is built into the SoC by the "Deep Sleep" capability.
630          *
631          *  - Boards wired so RTC_ON_nOFF is used as the reset signal,
632          *    rather than nPWRON_RESET, should forcibly enable split
633          *    power mode.  (Some chip errata report that RTC_CTRL_SPLIT
634          *    is write-only, and always reads as zero...)
635          */
636 
637         if (new_ctrl & OMAP_RTC_CTRL_SPLIT)
638                 dev_info(&pdev->dev, "split power mode\n");
639 
640         if (reg != new_ctrl)
641                 rtc_write(rtc, OMAP_RTC_CTRL_REG, new_ctrl);
642 
643         /*
644          * If we have the external clock then switch to it so we can keep
645          * ticking across suspend.
646          */
647         if (rtc->has_ext_clk) {
648                 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
649                 rtc_write(rtc, OMAP_RTC_OSC_REG,
650                           reg | OMAP_RTC_OSC_SEL_32KCLK_SRC);
651         }
652 
653         rtc->type->lock(rtc);
654 
655         device_init_wakeup(&pdev->dev, true);
656 
657         rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
658                         &omap_rtc_ops, THIS_MODULE);
659         if (IS_ERR(rtc->rtc)) {
660                 ret = PTR_ERR(rtc->rtc);
661                 goto err;
662         }
663 
664         /* handle periodic and alarm irqs */
665         ret = devm_request_irq(&pdev->dev, rtc->irq_timer, rtc_irq, 0,
666                         dev_name(&rtc->rtc->dev), rtc);
667         if (ret)
668                 goto err;
669 
670         if (rtc->irq_timer != rtc->irq_alarm) {
671                 ret = devm_request_irq(&pdev->dev, rtc->irq_alarm, rtc_irq, 0,
672                                 dev_name(&rtc->rtc->dev), rtc);
673                 if (ret)
674                         goto err;
675         }
676 
677         if (rtc->is_pmic_controller) {
678                 if (!pm_power_off) {
679                         omap_rtc_power_off_rtc = rtc;
680                         pm_power_off = omap_rtc_power_off;
681                 }
682         }
683 
684         return 0;
685 
686 err:
687         device_init_wakeup(&pdev->dev, false);
688         rtc->type->lock(rtc);
689         pm_runtime_put_sync(&pdev->dev);
690         pm_runtime_disable(&pdev->dev);
691 
692         return ret;
693 }
694 
695 static int __exit omap_rtc_remove(struct platform_device *pdev)
696 {
697         struct omap_rtc *rtc = platform_get_drvdata(pdev);
698         u8 reg;
699 
700         if (pm_power_off == omap_rtc_power_off &&
701                         omap_rtc_power_off_rtc == rtc) {
702                 pm_power_off = NULL;
703                 omap_rtc_power_off_rtc = NULL;
704         }
705 
706         device_init_wakeup(&pdev->dev, 0);
707 
708         if (!IS_ERR(rtc->clk))
709                 clk_disable_unprepare(rtc->clk);
710 
711         rtc->type->unlock(rtc);
712         /* leave rtc running, but disable irqs */
713         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
714 
715         if (rtc->has_ext_clk) {
716                 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
717                 reg &= ~OMAP_RTC_OSC_SEL_32KCLK_SRC;
718                 rtc_write(rtc, OMAP_RTC_OSC_REG, reg);
719         }
720 
721         rtc->type->lock(rtc);
722 
723         /* Disable the clock/module */
724         pm_runtime_put_sync(&pdev->dev);
725         pm_runtime_disable(&pdev->dev);
726 
727         return 0;
728 }
729 
730 #ifdef CONFIG_PM_SLEEP
731 static int omap_rtc_suspend(struct device *dev)
732 {
733         struct omap_rtc *rtc = dev_get_drvdata(dev);
734 
735         rtc->interrupts_reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
736 
737         rtc->type->unlock(rtc);
738         /*
739          * FIXME: the RTC alarm is not currently acting as a wakeup event
740          * source on some platforms, and in fact this enable() call is just
741          * saving a flag that's never used...
742          */
743         if (device_may_wakeup(dev))
744                 enable_irq_wake(rtc->irq_alarm);
745         else
746                 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
747         rtc->type->lock(rtc);
748 
749         /* Disable the clock/module */
750         pm_runtime_put_sync(dev);
751 
752         return 0;
753 }
754 
755 static int omap_rtc_resume(struct device *dev)
756 {
757         struct omap_rtc *rtc = dev_get_drvdata(dev);
758 
759         /* Enable the clock/module so that we can access the registers */
760         pm_runtime_get_sync(dev);
761 
762         rtc->type->unlock(rtc);
763         if (device_may_wakeup(dev))
764                 disable_irq_wake(rtc->irq_alarm);
765         else
766                 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, rtc->interrupts_reg);
767         rtc->type->lock(rtc);
768 
769         return 0;
770 }
771 #endif
772 
773 static SIMPLE_DEV_PM_OPS(omap_rtc_pm_ops, omap_rtc_suspend, omap_rtc_resume);
774 
775 static void omap_rtc_shutdown(struct platform_device *pdev)
776 {
777         struct omap_rtc *rtc = platform_get_drvdata(pdev);
778         u8 mask;
779 
780         /*
781          * Keep the ALARM interrupt enabled to allow the system to power up on
782          * alarm events.
783          */
784         rtc->type->unlock(rtc);
785         mask = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
786         mask &= OMAP_RTC_INTERRUPTS_IT_ALARM;
787         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, mask);
788         rtc->type->lock(rtc);
789 }
790 
791 static struct platform_driver omap_rtc_driver = {
792         .probe          = omap_rtc_probe,
793         .remove         = __exit_p(omap_rtc_remove),
794         .shutdown       = omap_rtc_shutdown,
795         .driver         = {
796                 .name   = "omap_rtc",
797                 .pm     = &omap_rtc_pm_ops,
798                 .of_match_table = omap_rtc_of_match,
799         },
800         .id_table       = omap_rtc_id_table,
801 };
802 
803 module_platform_driver(omap_rtc_driver);
804 
805 MODULE_ALIAS("platform:omap_rtc");
806 MODULE_AUTHOR("George G. Davis (and others)");
807 MODULE_LICENSE("GPL");
808 

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