Version:  2.0.40 2.2.26 2.4.37 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2

Linux/drivers/rtc/rtc-omap.c

  1 /*
  2  * TI OMAP Real Time Clock interface for Linux
  3  *
  4  * Copyright (C) 2003 MontaVista Software, Inc.
  5  * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
  6  *
  7  * Copyright (C) 2006 David Brownell (new RTC framework)
  8  * Copyright (C) 2014 Johan Hovold <johan@kernel.org>
  9  *
 10  * This program is free software; you can redistribute it and/or
 11  * modify it under the terms of the GNU General Public License
 12  * as published by the Free Software Foundation; either version
 13  * 2 of the License, or (at your option) any later version.
 14  */
 15 
 16 #include <linux/kernel.h>
 17 #include <linux/init.h>
 18 #include <linux/module.h>
 19 #include <linux/ioport.h>
 20 #include <linux/delay.h>
 21 #include <linux/rtc.h>
 22 #include <linux/bcd.h>
 23 #include <linux/platform_device.h>
 24 #include <linux/of.h>
 25 #include <linux/of_device.h>
 26 #include <linux/pm_runtime.h>
 27 #include <linux/io.h>
 28 
 29 /*
 30  * The OMAP RTC is a year/month/day/hours/minutes/seconds BCD clock
 31  * with century-range alarm matching, driven by the 32kHz clock.
 32  *
 33  * The main user-visible ways it differs from PC RTCs are by omitting
 34  * "don't care" alarm fields and sub-second periodic IRQs, and having
 35  * an autoadjust mechanism to calibrate to the true oscillator rate.
 36  *
 37  * Board-specific wiring options include using split power mode with
 38  * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset),
 39  * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from
 40  * low power modes) for OMAP1 boards (OMAP-L138 has this built into
 41  * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
 42  */
 43 
 44 /* RTC registers */
 45 #define OMAP_RTC_SECONDS_REG            0x00
 46 #define OMAP_RTC_MINUTES_REG            0x04
 47 #define OMAP_RTC_HOURS_REG              0x08
 48 #define OMAP_RTC_DAYS_REG               0x0C
 49 #define OMAP_RTC_MONTHS_REG             0x10
 50 #define OMAP_RTC_YEARS_REG              0x14
 51 #define OMAP_RTC_WEEKS_REG              0x18
 52 
 53 #define OMAP_RTC_ALARM_SECONDS_REG      0x20
 54 #define OMAP_RTC_ALARM_MINUTES_REG      0x24
 55 #define OMAP_RTC_ALARM_HOURS_REG        0x28
 56 #define OMAP_RTC_ALARM_DAYS_REG         0x2c
 57 #define OMAP_RTC_ALARM_MONTHS_REG       0x30
 58 #define OMAP_RTC_ALARM_YEARS_REG        0x34
 59 
 60 #define OMAP_RTC_CTRL_REG               0x40
 61 #define OMAP_RTC_STATUS_REG             0x44
 62 #define OMAP_RTC_INTERRUPTS_REG         0x48
 63 
 64 #define OMAP_RTC_COMP_LSB_REG           0x4c
 65 #define OMAP_RTC_COMP_MSB_REG           0x50
 66 #define OMAP_RTC_OSC_REG                0x54
 67 
 68 #define OMAP_RTC_KICK0_REG              0x6c
 69 #define OMAP_RTC_KICK1_REG              0x70
 70 
 71 #define OMAP_RTC_IRQWAKEEN              0x7c
 72 
 73 #define OMAP_RTC_ALARM2_SECONDS_REG     0x80
 74 #define OMAP_RTC_ALARM2_MINUTES_REG     0x84
 75 #define OMAP_RTC_ALARM2_HOURS_REG       0x88
 76 #define OMAP_RTC_ALARM2_DAYS_REG        0x8c
 77 #define OMAP_RTC_ALARM2_MONTHS_REG      0x90
 78 #define OMAP_RTC_ALARM2_YEARS_REG       0x94
 79 
 80 #define OMAP_RTC_PMIC_REG               0x98
 81 
 82 /* OMAP_RTC_CTRL_REG bit fields: */
 83 #define OMAP_RTC_CTRL_SPLIT             BIT(7)
 84 #define OMAP_RTC_CTRL_DISABLE           BIT(6)
 85 #define OMAP_RTC_CTRL_SET_32_COUNTER    BIT(5)
 86 #define OMAP_RTC_CTRL_TEST              BIT(4)
 87 #define OMAP_RTC_CTRL_MODE_12_24        BIT(3)
 88 #define OMAP_RTC_CTRL_AUTO_COMP         BIT(2)
 89 #define OMAP_RTC_CTRL_ROUND_30S         BIT(1)
 90 #define OMAP_RTC_CTRL_STOP              BIT(0)
 91 
 92 /* OMAP_RTC_STATUS_REG bit fields: */
 93 #define OMAP_RTC_STATUS_POWER_UP        BIT(7)
 94 #define OMAP_RTC_STATUS_ALARM2          BIT(7)
 95 #define OMAP_RTC_STATUS_ALARM           BIT(6)
 96 #define OMAP_RTC_STATUS_1D_EVENT        BIT(5)
 97 #define OMAP_RTC_STATUS_1H_EVENT        BIT(4)
 98 #define OMAP_RTC_STATUS_1M_EVENT        BIT(3)
 99 #define OMAP_RTC_STATUS_1S_EVENT        BIT(2)
100 #define OMAP_RTC_STATUS_RUN             BIT(1)
101 #define OMAP_RTC_STATUS_BUSY            BIT(0)
102 
103 /* OMAP_RTC_INTERRUPTS_REG bit fields: */
104 #define OMAP_RTC_INTERRUPTS_IT_ALARM2   BIT(4)
105 #define OMAP_RTC_INTERRUPTS_IT_ALARM    BIT(3)
106 #define OMAP_RTC_INTERRUPTS_IT_TIMER    BIT(2)
107 
108 /* OMAP_RTC_OSC_REG bit fields: */
109 #define OMAP_RTC_OSC_32KCLK_EN          BIT(6)
110 
111 /* OMAP_RTC_IRQWAKEEN bit fields: */
112 #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1)
113 
114 /* OMAP_RTC_PMIC bit fields: */
115 #define OMAP_RTC_PMIC_POWER_EN_EN       BIT(16)
116 
117 /* OMAP_RTC_KICKER values */
118 #define KICK0_VALUE                     0x83e70b13
119 #define KICK1_VALUE                     0x95a4f1e0
120 
121 struct omap_rtc;
122 
123 struct omap_rtc_device_type {
124         bool has_32kclk_en;
125         bool has_irqwakeen;
126         bool has_pmic_mode;
127         bool has_power_up_reset;
128         void (*lock)(struct omap_rtc *rtc);
129         void (*unlock)(struct omap_rtc *rtc);
130 };
131 
132 struct omap_rtc {
133         struct rtc_device *rtc;
134         void __iomem *base;
135         int irq_alarm;
136         int irq_timer;
137         u8 interrupts_reg;
138         bool is_pmic_controller;
139         const struct omap_rtc_device_type *type;
140 };
141 
142 static inline u8 rtc_read(struct omap_rtc *rtc, unsigned int reg)
143 {
144         return readb(rtc->base + reg);
145 }
146 
147 static inline u32 rtc_readl(struct omap_rtc *rtc, unsigned int reg)
148 {
149         return readl(rtc->base + reg);
150 }
151 
152 static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val)
153 {
154         writeb(val, rtc->base + reg);
155 }
156 
157 static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val)
158 {
159         writel(val, rtc->base + reg);
160 }
161 
162 static void am3352_rtc_unlock(struct omap_rtc *rtc)
163 {
164         rtc_writel(rtc, OMAP_RTC_KICK0_REG, KICK0_VALUE);
165         rtc_writel(rtc, OMAP_RTC_KICK1_REG, KICK1_VALUE);
166 }
167 
168 static void am3352_rtc_lock(struct omap_rtc *rtc)
169 {
170         rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0);
171         rtc_writel(rtc, OMAP_RTC_KICK1_REG, 0);
172 }
173 
174 static void default_rtc_unlock(struct omap_rtc *rtc)
175 {
176 }
177 
178 static void default_rtc_lock(struct omap_rtc *rtc)
179 {
180 }
181 
182 /*
183  * We rely on the rtc framework to handle locking (rtc->ops_lock),
184  * so the only other requirement is that register accesses which
185  * require BUSY to be clear are made with IRQs locally disabled
186  */
187 static void rtc_wait_not_busy(struct omap_rtc *rtc)
188 {
189         int count;
190         u8 status;
191 
192         /* BUSY may stay active for 1/32768 second (~30 usec) */
193         for (count = 0; count < 50; count++) {
194                 status = rtc_read(rtc, OMAP_RTC_STATUS_REG);
195                 if (!(status & OMAP_RTC_STATUS_BUSY))
196                         break;
197                 udelay(1);
198         }
199         /* now we have ~15 usec to read/write various registers */
200 }
201 
202 static irqreturn_t rtc_irq(int irq, void *dev_id)
203 {
204         struct omap_rtc *rtc = dev_id;
205         unsigned long events = 0;
206         u8 irq_data;
207 
208         irq_data = rtc_read(rtc, OMAP_RTC_STATUS_REG);
209 
210         /* alarm irq? */
211         if (irq_data & OMAP_RTC_STATUS_ALARM) {
212                 rtc->type->unlock(rtc);
213                 rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM);
214                 rtc->type->lock(rtc);
215                 events |= RTC_IRQF | RTC_AF;
216         }
217 
218         /* 1/sec periodic/update irq? */
219         if (irq_data & OMAP_RTC_STATUS_1S_EVENT)
220                 events |= RTC_IRQF | RTC_UF;
221 
222         rtc_update_irq(rtc->rtc, 1, events);
223 
224         return IRQ_HANDLED;
225 }
226 
227 static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
228 {
229         struct omap_rtc *rtc = dev_get_drvdata(dev);
230         u8 reg, irqwake_reg = 0;
231 
232         local_irq_disable();
233         rtc_wait_not_busy(rtc);
234         reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
235         if (rtc->type->has_irqwakeen)
236                 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
237 
238         if (enabled) {
239                 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
240                 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
241         } else {
242                 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
243                 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
244         }
245         rtc_wait_not_busy(rtc);
246         rtc->type->unlock(rtc);
247         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
248         if (rtc->type->has_irqwakeen)
249                 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
250         rtc->type->lock(rtc);
251         local_irq_enable();
252 
253         return 0;
254 }
255 
256 /* this hardware doesn't support "don't care" alarm fields */
257 static int tm2bcd(struct rtc_time *tm)
258 {
259         if (rtc_valid_tm(tm) != 0)
260                 return -EINVAL;
261 
262         tm->tm_sec = bin2bcd(tm->tm_sec);
263         tm->tm_min = bin2bcd(tm->tm_min);
264         tm->tm_hour = bin2bcd(tm->tm_hour);
265         tm->tm_mday = bin2bcd(tm->tm_mday);
266 
267         tm->tm_mon = bin2bcd(tm->tm_mon + 1);
268 
269         /* epoch == 1900 */
270         if (tm->tm_year < 100 || tm->tm_year > 199)
271                 return -EINVAL;
272         tm->tm_year = bin2bcd(tm->tm_year - 100);
273 
274         return 0;
275 }
276 
277 static void bcd2tm(struct rtc_time *tm)
278 {
279         tm->tm_sec = bcd2bin(tm->tm_sec);
280         tm->tm_min = bcd2bin(tm->tm_min);
281         tm->tm_hour = bcd2bin(tm->tm_hour);
282         tm->tm_mday = bcd2bin(tm->tm_mday);
283         tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
284         /* epoch == 1900 */
285         tm->tm_year = bcd2bin(tm->tm_year) + 100;
286 }
287 
288 static void omap_rtc_read_time_raw(struct omap_rtc *rtc, struct rtc_time *tm)
289 {
290         tm->tm_sec = rtc_read(rtc, OMAP_RTC_SECONDS_REG);
291         tm->tm_min = rtc_read(rtc, OMAP_RTC_MINUTES_REG);
292         tm->tm_hour = rtc_read(rtc, OMAP_RTC_HOURS_REG);
293         tm->tm_mday = rtc_read(rtc, OMAP_RTC_DAYS_REG);
294         tm->tm_mon = rtc_read(rtc, OMAP_RTC_MONTHS_REG);
295         tm->tm_year = rtc_read(rtc, OMAP_RTC_YEARS_REG);
296 }
297 
298 static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm)
299 {
300         struct omap_rtc *rtc = dev_get_drvdata(dev);
301 
302         /* we don't report wday/yday/isdst ... */
303         local_irq_disable();
304         rtc_wait_not_busy(rtc);
305         omap_rtc_read_time_raw(rtc, tm);
306         local_irq_enable();
307 
308         bcd2tm(tm);
309 
310         return 0;
311 }
312 
313 static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm)
314 {
315         struct omap_rtc *rtc = dev_get_drvdata(dev);
316 
317         if (tm2bcd(tm) < 0)
318                 return -EINVAL;
319 
320         local_irq_disable();
321         rtc_wait_not_busy(rtc);
322 
323         rtc->type->unlock(rtc);
324         rtc_write(rtc, OMAP_RTC_YEARS_REG, tm->tm_year);
325         rtc_write(rtc, OMAP_RTC_MONTHS_REG, tm->tm_mon);
326         rtc_write(rtc, OMAP_RTC_DAYS_REG, tm->tm_mday);
327         rtc_write(rtc, OMAP_RTC_HOURS_REG, tm->tm_hour);
328         rtc_write(rtc, OMAP_RTC_MINUTES_REG, tm->tm_min);
329         rtc_write(rtc, OMAP_RTC_SECONDS_REG, tm->tm_sec);
330         rtc->type->lock(rtc);
331 
332         local_irq_enable();
333 
334         return 0;
335 }
336 
337 static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
338 {
339         struct omap_rtc *rtc = dev_get_drvdata(dev);
340         u8 interrupts;
341 
342         local_irq_disable();
343         rtc_wait_not_busy(rtc);
344 
345         alm->time.tm_sec = rtc_read(rtc, OMAP_RTC_ALARM_SECONDS_REG);
346         alm->time.tm_min = rtc_read(rtc, OMAP_RTC_ALARM_MINUTES_REG);
347         alm->time.tm_hour = rtc_read(rtc, OMAP_RTC_ALARM_HOURS_REG);
348         alm->time.tm_mday = rtc_read(rtc, OMAP_RTC_ALARM_DAYS_REG);
349         alm->time.tm_mon = rtc_read(rtc, OMAP_RTC_ALARM_MONTHS_REG);
350         alm->time.tm_year = rtc_read(rtc, OMAP_RTC_ALARM_YEARS_REG);
351 
352         local_irq_enable();
353 
354         bcd2tm(&alm->time);
355 
356         interrupts = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
357         alm->enabled = !!(interrupts & OMAP_RTC_INTERRUPTS_IT_ALARM);
358 
359         return 0;
360 }
361 
362 static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
363 {
364         struct omap_rtc *rtc = dev_get_drvdata(dev);
365         u8 reg, irqwake_reg = 0;
366 
367         if (tm2bcd(&alm->time) < 0)
368                 return -EINVAL;
369 
370         local_irq_disable();
371         rtc_wait_not_busy(rtc);
372 
373         rtc->type->unlock(rtc);
374         rtc_write(rtc, OMAP_RTC_ALARM_YEARS_REG, alm->time.tm_year);
375         rtc_write(rtc, OMAP_RTC_ALARM_MONTHS_REG, alm->time.tm_mon);
376         rtc_write(rtc, OMAP_RTC_ALARM_DAYS_REG, alm->time.tm_mday);
377         rtc_write(rtc, OMAP_RTC_ALARM_HOURS_REG, alm->time.tm_hour);
378         rtc_write(rtc, OMAP_RTC_ALARM_MINUTES_REG, alm->time.tm_min);
379         rtc_write(rtc, OMAP_RTC_ALARM_SECONDS_REG, alm->time.tm_sec);
380 
381         reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
382         if (rtc->type->has_irqwakeen)
383                 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
384 
385         if (alm->enabled) {
386                 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
387                 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
388         } else {
389                 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
390                 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
391         }
392         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
393         if (rtc->type->has_irqwakeen)
394                 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
395         rtc->type->lock(rtc);
396 
397         local_irq_enable();
398 
399         return 0;
400 }
401 
402 static struct omap_rtc *omap_rtc_power_off_rtc;
403 
404 /*
405  * omap_rtc_poweroff: RTC-controlled power off
406  *
407  * The RTC can be used to control an external PMIC via the pmic_power_en pin,
408  * which can be configured to transition to OFF on ALARM2 events.
409  *
410  * Notes:
411  * The two-second alarm offset is the shortest offset possible as the alarm
412  * registers must be set before the next timer update and the offset
413  * calculation is too heavy for everything to be done within a single access
414  * period (~15 us).
415  *
416  * Called with local interrupts disabled.
417  */
418 static void omap_rtc_power_off(void)
419 {
420         struct omap_rtc *rtc = omap_rtc_power_off_rtc;
421         struct rtc_time tm;
422         unsigned long now;
423         u32 val;
424 
425         rtc->type->unlock(rtc);
426         /* enable pmic_power_en control */
427         val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
428         rtc_writel(rtc, OMAP_RTC_PMIC_REG, val | OMAP_RTC_PMIC_POWER_EN_EN);
429 
430         /* set alarm two seconds from now */
431         omap_rtc_read_time_raw(rtc, &tm);
432         bcd2tm(&tm);
433         rtc_tm_to_time(&tm, &now);
434         rtc_time_to_tm(now + 2, &tm);
435 
436         if (tm2bcd(&tm) < 0) {
437                 dev_err(&rtc->rtc->dev, "power off failed\n");
438                 return;
439         }
440 
441         rtc_wait_not_busy(rtc);
442 
443         rtc_write(rtc, OMAP_RTC_ALARM2_SECONDS_REG, tm.tm_sec);
444         rtc_write(rtc, OMAP_RTC_ALARM2_MINUTES_REG, tm.tm_min);
445         rtc_write(rtc, OMAP_RTC_ALARM2_HOURS_REG, tm.tm_hour);
446         rtc_write(rtc, OMAP_RTC_ALARM2_DAYS_REG, tm.tm_mday);
447         rtc_write(rtc, OMAP_RTC_ALARM2_MONTHS_REG, tm.tm_mon);
448         rtc_write(rtc, OMAP_RTC_ALARM2_YEARS_REG, tm.tm_year);
449 
450         /*
451          * enable ALARM2 interrupt
452          *
453          * NOTE: this fails on AM3352 if rtc_write (writeb) is used
454          */
455         val = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
456         rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG,
457                         val | OMAP_RTC_INTERRUPTS_IT_ALARM2);
458         rtc->type->lock(rtc);
459 
460         /*
461          * Wait for alarm to trigger (within two seconds) and external PMIC to
462          * power off the system. Add a 500 ms margin for external latencies
463          * (e.g. debounce circuits).
464          */
465         mdelay(2500);
466 }
467 
468 static struct rtc_class_ops omap_rtc_ops = {
469         .read_time      = omap_rtc_read_time,
470         .set_time       = omap_rtc_set_time,
471         .read_alarm     = omap_rtc_read_alarm,
472         .set_alarm      = omap_rtc_set_alarm,
473         .alarm_irq_enable = omap_rtc_alarm_irq_enable,
474 };
475 
476 static const struct omap_rtc_device_type omap_rtc_default_type = {
477         .has_power_up_reset = true,
478         .lock           = default_rtc_lock,
479         .unlock         = default_rtc_unlock,
480 };
481 
482 static const struct omap_rtc_device_type omap_rtc_am3352_type = {
483         .has_32kclk_en  = true,
484         .has_irqwakeen  = true,
485         .has_pmic_mode  = true,
486         .lock           = am3352_rtc_lock,
487         .unlock         = am3352_rtc_unlock,
488 };
489 
490 static const struct omap_rtc_device_type omap_rtc_da830_type = {
491         .lock           = am3352_rtc_lock,
492         .unlock         = am3352_rtc_unlock,
493 };
494 
495 static const struct platform_device_id omap_rtc_id_table[] = {
496         {
497                 .name   = "omap_rtc",
498                 .driver_data = (kernel_ulong_t)&omap_rtc_default_type,
499         }, {
500                 .name   = "am3352-rtc",
501                 .driver_data = (kernel_ulong_t)&omap_rtc_am3352_type,
502         }, {
503                 .name   = "da830-rtc",
504                 .driver_data = (kernel_ulong_t)&omap_rtc_da830_type,
505         }, {
506                 /* sentinel */
507         }
508 };
509 MODULE_DEVICE_TABLE(platform, omap_rtc_id_table);
510 
511 static const struct of_device_id omap_rtc_of_match[] = {
512         {
513                 .compatible     = "ti,am3352-rtc",
514                 .data           = &omap_rtc_am3352_type,
515         }, {
516                 .compatible     = "ti,da830-rtc",
517                 .data           = &omap_rtc_da830_type,
518         }, {
519                 /* sentinel */
520         }
521 };
522 MODULE_DEVICE_TABLE(of, omap_rtc_of_match);
523 
524 static int omap_rtc_probe(struct platform_device *pdev)
525 {
526         struct omap_rtc *rtc;
527         struct resource *res;
528         u8 reg, mask, new_ctrl;
529         const struct platform_device_id *id_entry;
530         const struct of_device_id *of_id;
531         int ret;
532 
533         rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
534         if (!rtc)
535                 return -ENOMEM;
536 
537         of_id = of_match_device(omap_rtc_of_match, &pdev->dev);
538         if (of_id) {
539                 rtc->type = of_id->data;
540                 rtc->is_pmic_controller = rtc->type->has_pmic_mode &&
541                                 of_property_read_bool(pdev->dev.of_node,
542                                                 "system-power-controller");
543         } else {
544                 id_entry = platform_get_device_id(pdev);
545                 rtc->type = (void *)id_entry->driver_data;
546         }
547 
548         rtc->irq_timer = platform_get_irq(pdev, 0);
549         if (rtc->irq_timer <= 0)
550                 return -ENOENT;
551 
552         rtc->irq_alarm = platform_get_irq(pdev, 1);
553         if (rtc->irq_alarm <= 0)
554                 return -ENOENT;
555 
556         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
557         rtc->base = devm_ioremap_resource(&pdev->dev, res);
558         if (IS_ERR(rtc->base))
559                 return PTR_ERR(rtc->base);
560 
561         platform_set_drvdata(pdev, rtc);
562 
563         /* Enable the clock/module so that we can access the registers */
564         pm_runtime_enable(&pdev->dev);
565         pm_runtime_get_sync(&pdev->dev);
566 
567         rtc->type->unlock(rtc);
568 
569         /*
570          * disable interrupts
571          *
572          * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used
573          */
574         rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
575 
576         /* enable RTC functional clock */
577         if (rtc->type->has_32kclk_en) {
578                 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
579                 rtc_writel(rtc, OMAP_RTC_OSC_REG,
580                                 reg | OMAP_RTC_OSC_32KCLK_EN);
581         }
582 
583         /* clear old status */
584         reg = rtc_read(rtc, OMAP_RTC_STATUS_REG);
585 
586         mask = OMAP_RTC_STATUS_ALARM;
587 
588         if (rtc->type->has_pmic_mode)
589                 mask |= OMAP_RTC_STATUS_ALARM2;
590 
591         if (rtc->type->has_power_up_reset) {
592                 mask |= OMAP_RTC_STATUS_POWER_UP;
593                 if (reg & OMAP_RTC_STATUS_POWER_UP)
594                         dev_info(&pdev->dev, "RTC power up reset detected\n");
595         }
596 
597         if (reg & mask)
598                 rtc_write(rtc, OMAP_RTC_STATUS_REG, reg & mask);
599 
600         /* On boards with split power, RTC_ON_NOFF won't reset the RTC */
601         reg = rtc_read(rtc, OMAP_RTC_CTRL_REG);
602         if (reg & OMAP_RTC_CTRL_STOP)
603                 dev_info(&pdev->dev, "already running\n");
604 
605         /* force to 24 hour mode */
606         new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP);
607         new_ctrl |= OMAP_RTC_CTRL_STOP;
608 
609         /*
610          * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
611          *
612          *  - Device wake-up capability setting should come through chip
613          *    init logic. OMAP1 boards should initialize the "wakeup capable"
614          *    flag in the platform device if the board is wired right for
615          *    being woken up by RTC alarm. For OMAP-L138, this capability
616          *    is built into the SoC by the "Deep Sleep" capability.
617          *
618          *  - Boards wired so RTC_ON_nOFF is used as the reset signal,
619          *    rather than nPWRON_RESET, should forcibly enable split
620          *    power mode.  (Some chip errata report that RTC_CTRL_SPLIT
621          *    is write-only, and always reads as zero...)
622          */
623 
624         if (new_ctrl & OMAP_RTC_CTRL_SPLIT)
625                 dev_info(&pdev->dev, "split power mode\n");
626 
627         if (reg != new_ctrl)
628                 rtc_write(rtc, OMAP_RTC_CTRL_REG, new_ctrl);
629 
630         rtc->type->lock(rtc);
631 
632         device_init_wakeup(&pdev->dev, true);
633 
634         rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
635                         &omap_rtc_ops, THIS_MODULE);
636         if (IS_ERR(rtc->rtc)) {
637                 ret = PTR_ERR(rtc->rtc);
638                 goto err;
639         }
640 
641         /* handle periodic and alarm irqs */
642         ret = devm_request_irq(&pdev->dev, rtc->irq_timer, rtc_irq, 0,
643                         dev_name(&rtc->rtc->dev), rtc);
644         if (ret)
645                 goto err;
646 
647         if (rtc->irq_timer != rtc->irq_alarm) {
648                 ret = devm_request_irq(&pdev->dev, rtc->irq_alarm, rtc_irq, 0,
649                                 dev_name(&rtc->rtc->dev), rtc);
650                 if (ret)
651                         goto err;
652         }
653 
654         if (rtc->is_pmic_controller) {
655                 if (!pm_power_off) {
656                         omap_rtc_power_off_rtc = rtc;
657                         pm_power_off = omap_rtc_power_off;
658                 }
659         }
660 
661         return 0;
662 
663 err:
664         device_init_wakeup(&pdev->dev, false);
665         rtc->type->lock(rtc);
666         pm_runtime_put_sync(&pdev->dev);
667         pm_runtime_disable(&pdev->dev);
668 
669         return ret;
670 }
671 
672 static int __exit omap_rtc_remove(struct platform_device *pdev)
673 {
674         struct omap_rtc *rtc = platform_get_drvdata(pdev);
675 
676         if (pm_power_off == omap_rtc_power_off &&
677                         omap_rtc_power_off_rtc == rtc) {
678                 pm_power_off = NULL;
679                 omap_rtc_power_off_rtc = NULL;
680         }
681 
682         device_init_wakeup(&pdev->dev, 0);
683 
684         rtc->type->unlock(rtc);
685         /* leave rtc running, but disable irqs */
686         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
687 
688         rtc->type->lock(rtc);
689 
690         /* Disable the clock/module */
691         pm_runtime_put_sync(&pdev->dev);
692         pm_runtime_disable(&pdev->dev);
693 
694         return 0;
695 }
696 
697 #ifdef CONFIG_PM_SLEEP
698 static int omap_rtc_suspend(struct device *dev)
699 {
700         struct omap_rtc *rtc = dev_get_drvdata(dev);
701 
702         rtc->interrupts_reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
703 
704         rtc->type->unlock(rtc);
705         /*
706          * FIXME: the RTC alarm is not currently acting as a wakeup event
707          * source on some platforms, and in fact this enable() call is just
708          * saving a flag that's never used...
709          */
710         if (device_may_wakeup(dev))
711                 enable_irq_wake(rtc->irq_alarm);
712         else
713                 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
714         rtc->type->lock(rtc);
715 
716         /* Disable the clock/module */
717         pm_runtime_put_sync(dev);
718 
719         return 0;
720 }
721 
722 static int omap_rtc_resume(struct device *dev)
723 {
724         struct omap_rtc *rtc = dev_get_drvdata(dev);
725 
726         /* Enable the clock/module so that we can access the registers */
727         pm_runtime_get_sync(dev);
728 
729         rtc->type->unlock(rtc);
730         if (device_may_wakeup(dev))
731                 disable_irq_wake(rtc->irq_alarm);
732         else
733                 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, rtc->interrupts_reg);
734         rtc->type->lock(rtc);
735 
736         return 0;
737 }
738 #endif
739 
740 static SIMPLE_DEV_PM_OPS(omap_rtc_pm_ops, omap_rtc_suspend, omap_rtc_resume);
741 
742 static void omap_rtc_shutdown(struct platform_device *pdev)
743 {
744         struct omap_rtc *rtc = platform_get_drvdata(pdev);
745         u8 mask;
746 
747         /*
748          * Keep the ALARM interrupt enabled to allow the system to power up on
749          * alarm events.
750          */
751         rtc->type->unlock(rtc);
752         mask = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
753         mask &= OMAP_RTC_INTERRUPTS_IT_ALARM;
754         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, mask);
755         rtc->type->lock(rtc);
756 }
757 
758 static struct platform_driver omap_rtc_driver = {
759         .probe          = omap_rtc_probe,
760         .remove         = __exit_p(omap_rtc_remove),
761         .shutdown       = omap_rtc_shutdown,
762         .driver         = {
763                 .name   = "omap_rtc",
764                 .pm     = &omap_rtc_pm_ops,
765                 .of_match_table = omap_rtc_of_match,
766         },
767         .id_table       = omap_rtc_id_table,
768 };
769 
770 module_platform_driver(omap_rtc_driver);
771 
772 MODULE_ALIAS("platform:omap_rtc");
773 MODULE_AUTHOR("George G. Davis (and others)");
774 MODULE_LICENSE("GPL");
775 

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