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Linux/drivers/rtc/rtc-jz4740.c

  1 /*
  2  *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
  3  *  Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
  4  *       JZ4740 SoC RTC driver
  5  *
  6  *  This program is free software; you can redistribute it and/or modify it
  7  *  under  the terms of  the GNU General Public License as published by the
  8  *  Free Software Foundation;  either version 2 of the License, or (at your
  9  *  option) any later version.
 10  *
 11  *  You should have received a copy of the GNU General Public License along
 12  *  with this program; if not, write to the Free Software Foundation, Inc.,
 13  *  675 Mass Ave, Cambridge, MA 02139, USA.
 14  *
 15  */
 16 
 17 #include <linux/clk.h>
 18 #include <linux/io.h>
 19 #include <linux/kernel.h>
 20 #include <linux/module.h>
 21 #include <linux/of_device.h>
 22 #include <linux/platform_device.h>
 23 #include <linux/reboot.h>
 24 #include <linux/rtc.h>
 25 #include <linux/slab.h>
 26 #include <linux/spinlock.h>
 27 
 28 #define JZ_REG_RTC_CTRL         0x00
 29 #define JZ_REG_RTC_SEC          0x04
 30 #define JZ_REG_RTC_SEC_ALARM    0x08
 31 #define JZ_REG_RTC_REGULATOR    0x0C
 32 #define JZ_REG_RTC_HIBERNATE    0x20
 33 #define JZ_REG_RTC_WAKEUP_FILTER        0x24
 34 #define JZ_REG_RTC_RESET_COUNTER        0x28
 35 #define JZ_REG_RTC_SCRATCHPAD   0x34
 36 
 37 /* The following are present on the jz4780 */
 38 #define JZ_REG_RTC_WENR 0x3C
 39 #define JZ_RTC_WENR_WEN BIT(31)
 40 
 41 #define JZ_RTC_CTRL_WRDY        BIT(7)
 42 #define JZ_RTC_CTRL_1HZ         BIT(6)
 43 #define JZ_RTC_CTRL_1HZ_IRQ     BIT(5)
 44 #define JZ_RTC_CTRL_AF          BIT(4)
 45 #define JZ_RTC_CTRL_AF_IRQ      BIT(3)
 46 #define JZ_RTC_CTRL_AE          BIT(2)
 47 #define JZ_RTC_CTRL_ENABLE      BIT(0)
 48 
 49 /* Magic value to enable writes on jz4780 */
 50 #define JZ_RTC_WENR_MAGIC       0xA55A
 51 
 52 #define JZ_RTC_WAKEUP_FILTER_MASK       0x0000FFE0
 53 #define JZ_RTC_RESET_COUNTER_MASK       0x00000FE0
 54 
 55 enum jz4740_rtc_type {
 56         ID_JZ4740,
 57         ID_JZ4780,
 58 };
 59 
 60 struct jz4740_rtc {
 61         void __iomem *base;
 62         enum jz4740_rtc_type type;
 63 
 64         struct rtc_device *rtc;
 65         struct clk *clk;
 66 
 67         int irq;
 68 
 69         spinlock_t lock;
 70 
 71         unsigned int min_wakeup_pin_assert_time;
 72         unsigned int reset_pin_assert_time;
 73 };
 74 
 75 static struct device *dev_for_power_off;
 76 
 77 static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
 78 {
 79         return readl(rtc->base + reg);
 80 }
 81 
 82 static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
 83 {
 84         uint32_t ctrl;
 85         int timeout = 1000;
 86 
 87         do {
 88                 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 89         } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout);
 90 
 91         return timeout ? 0 : -EIO;
 92 }
 93 
 94 static inline int jz4780_rtc_enable_write(struct jz4740_rtc *rtc)
 95 {
 96         uint32_t ctrl;
 97         int ret, timeout = 1000;
 98 
 99         ret = jz4740_rtc_wait_write_ready(rtc);
100         if (ret != 0)
101                 return ret;
102 
103         writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR);
104 
105         do {
106                 ctrl = readl(rtc->base + JZ_REG_RTC_WENR);
107         } while (!(ctrl & JZ_RTC_WENR_WEN) && --timeout);
108 
109         return timeout ? 0 : -EIO;
110 }
111 
112 static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
113         uint32_t val)
114 {
115         int ret = 0;
116 
117         if (rtc->type >= ID_JZ4780)
118                 ret = jz4780_rtc_enable_write(rtc);
119         if (ret == 0)
120                 ret = jz4740_rtc_wait_write_ready(rtc);
121         if (ret == 0)
122                 writel(val, rtc->base + reg);
123 
124         return ret;
125 }
126 
127 static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
128         bool set)
129 {
130         int ret;
131         unsigned long flags;
132         uint32_t ctrl;
133 
134         spin_lock_irqsave(&rtc->lock, flags);
135 
136         ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
137 
138         /* Don't clear interrupt flags by accident */
139         ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;
140 
141         if (set)
142                 ctrl |= mask;
143         else
144                 ctrl &= ~mask;
145 
146         ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
147 
148         spin_unlock_irqrestore(&rtc->lock, flags);
149 
150         return ret;
151 }
152 
153 static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time)
154 {
155         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
156         uint32_t secs, secs2;
157         int timeout = 5;
158 
159         /* If the seconds register is read while it is updated, it can contain a
160          * bogus value. This can be avoided by making sure that two consecutive
161          * reads have the same value.
162          */
163         secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
164         secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
165 
166         while (secs != secs2 && --timeout) {
167                 secs = secs2;
168                 secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
169         }
170 
171         if (timeout == 0)
172                 return -EIO;
173 
174         rtc_time_to_tm(secs, time);
175 
176         return rtc_valid_tm(time);
177 }
178 
179 static int jz4740_rtc_set_mmss(struct device *dev, unsigned long secs)
180 {
181         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
182 
183         return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, secs);
184 }
185 
186 static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
187 {
188         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
189         uint32_t secs;
190         uint32_t ctrl;
191 
192         secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
193 
194         ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
195 
196         alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
197         alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
198 
199         rtc_time_to_tm(secs, &alrm->time);
200 
201         return rtc_valid_tm(&alrm->time);
202 }
203 
204 static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
205 {
206         int ret;
207         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
208         unsigned long secs;
209 
210         rtc_tm_to_time(&alrm->time, &secs);
211 
212         ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
213         if (!ret)
214                 ret = jz4740_rtc_ctrl_set_bits(rtc,
215                         JZ_RTC_CTRL_AE | JZ_RTC_CTRL_AF_IRQ, alrm->enabled);
216 
217         return ret;
218 }
219 
220 static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
221 {
222         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
223         return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
224 }
225 
226 static const struct rtc_class_ops jz4740_rtc_ops = {
227         .read_time      = jz4740_rtc_read_time,
228         .set_mmss       = jz4740_rtc_set_mmss,
229         .read_alarm     = jz4740_rtc_read_alarm,
230         .set_alarm      = jz4740_rtc_set_alarm,
231         .alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
232 };
233 
234 static irqreturn_t jz4740_rtc_irq(int irq, void *data)
235 {
236         struct jz4740_rtc *rtc = data;
237         uint32_t ctrl;
238         unsigned long events = 0;
239 
240         ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
241 
242         if (ctrl & JZ_RTC_CTRL_1HZ)
243                 events |= (RTC_UF | RTC_IRQF);
244 
245         if (ctrl & JZ_RTC_CTRL_AF)
246                 events |= (RTC_AF | RTC_IRQF);
247 
248         rtc_update_irq(rtc->rtc, 1, events);
249 
250         jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, false);
251 
252         return IRQ_HANDLED;
253 }
254 
255 static void jz4740_rtc_poweroff(struct device *dev)
256 {
257         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
258         jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
259 }
260 
261 static void jz4740_rtc_power_off(void)
262 {
263         struct jz4740_rtc *rtc = dev_get_drvdata(dev_for_power_off);
264         unsigned long rtc_rate;
265         unsigned long wakeup_filter_ticks;
266         unsigned long reset_counter_ticks;
267 
268         clk_prepare_enable(rtc->clk);
269 
270         rtc_rate = clk_get_rate(rtc->clk);
271 
272         /*
273          * Set minimum wakeup pin assertion time: 100 ms.
274          * Range is 0 to 2 sec if RTC is clocked at 32 kHz.
275          */
276         wakeup_filter_ticks =
277                 (rtc->min_wakeup_pin_assert_time * rtc_rate) / 1000;
278         if (wakeup_filter_ticks < JZ_RTC_WAKEUP_FILTER_MASK)
279                 wakeup_filter_ticks &= JZ_RTC_WAKEUP_FILTER_MASK;
280         else
281                 wakeup_filter_ticks = JZ_RTC_WAKEUP_FILTER_MASK;
282         jz4740_rtc_reg_write(rtc,
283                              JZ_REG_RTC_WAKEUP_FILTER, wakeup_filter_ticks);
284 
285         /*
286          * Set reset pin low-level assertion time after wakeup: 60 ms.
287          * Range is 0 to 125 ms if RTC is clocked at 32 kHz.
288          */
289         reset_counter_ticks = (rtc->reset_pin_assert_time * rtc_rate) / 1000;
290         if (reset_counter_ticks < JZ_RTC_RESET_COUNTER_MASK)
291                 reset_counter_ticks &= JZ_RTC_RESET_COUNTER_MASK;
292         else
293                 reset_counter_ticks = JZ_RTC_RESET_COUNTER_MASK;
294         jz4740_rtc_reg_write(rtc,
295                              JZ_REG_RTC_RESET_COUNTER, reset_counter_ticks);
296 
297         jz4740_rtc_poweroff(dev_for_power_off);
298         kernel_halt();
299 }
300 
301 static const struct of_device_id jz4740_rtc_of_match[] = {
302         { .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 },
303         { .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4780 },
304         {},
305 };
306 MODULE_DEVICE_TABLE(of, jz4740_rtc_of_match);
307 
308 static int jz4740_rtc_probe(struct platform_device *pdev)
309 {
310         int ret;
311         struct jz4740_rtc *rtc;
312         uint32_t scratchpad;
313         struct resource *mem;
314         const struct platform_device_id *id = platform_get_device_id(pdev);
315         const struct of_device_id *of_id = of_match_device(
316                         jz4740_rtc_of_match, &pdev->dev);
317         struct device_node *np = pdev->dev.of_node;
318 
319         rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
320         if (!rtc)
321                 return -ENOMEM;
322 
323         if (of_id)
324                 rtc->type = (enum jz4740_rtc_type)of_id->data;
325         else
326                 rtc->type = id->driver_data;
327 
328         rtc->irq = platform_get_irq(pdev, 0);
329         if (rtc->irq < 0) {
330                 dev_err(&pdev->dev, "Failed to get platform irq\n");
331                 return -ENOENT;
332         }
333 
334         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
335         rtc->base = devm_ioremap_resource(&pdev->dev, mem);
336         if (IS_ERR(rtc->base))
337                 return PTR_ERR(rtc->base);
338 
339         rtc->clk = devm_clk_get(&pdev->dev, "rtc");
340         if (IS_ERR(rtc->clk)) {
341                 dev_err(&pdev->dev, "Failed to get RTC clock\n");
342                 return PTR_ERR(rtc->clk);
343         }
344 
345         spin_lock_init(&rtc->lock);
346 
347         platform_set_drvdata(pdev, rtc);
348 
349         device_init_wakeup(&pdev->dev, 1);
350 
351         rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
352                                         &jz4740_rtc_ops, THIS_MODULE);
353         if (IS_ERR(rtc->rtc)) {
354                 ret = PTR_ERR(rtc->rtc);
355                 dev_err(&pdev->dev, "Failed to register rtc device: %d\n", ret);
356                 return ret;
357         }
358 
359         ret = devm_request_irq(&pdev->dev, rtc->irq, jz4740_rtc_irq, 0,
360                                 pdev->name, rtc);
361         if (ret) {
362                 dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret);
363                 return ret;
364         }
365 
366         scratchpad = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD);
367         if (scratchpad != 0x12345678) {
368                 ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
369                 ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, 0);
370                 if (ret) {
371                         dev_err(&pdev->dev, "Could not write write to RTC registers\n");
372                         return ret;
373                 }
374         }
375 
376         if (np && of_device_is_system_power_controller(np)) {
377                 if (!pm_power_off) {
378                         /* Default: 60ms */
379                         rtc->reset_pin_assert_time = 60;
380                         of_property_read_u32(np, "reset-pin-assert-time-ms",
381                                              &rtc->reset_pin_assert_time);
382 
383                         /* Default: 100ms */
384                         rtc->min_wakeup_pin_assert_time = 100;
385                         of_property_read_u32(np,
386                                              "min-wakeup-pin-assert-time-ms",
387                                              &rtc->min_wakeup_pin_assert_time);
388 
389                         dev_for_power_off = &pdev->dev;
390                         pm_power_off = jz4740_rtc_power_off;
391                 } else {
392                         dev_warn(&pdev->dev,
393                                  "Poweroff handler already present!\n");
394                 }
395         }
396 
397         return 0;
398 }
399 
400 #ifdef CONFIG_PM
401 static int jz4740_rtc_suspend(struct device *dev)
402 {
403         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
404 
405         if (device_may_wakeup(dev))
406                 enable_irq_wake(rtc->irq);
407         return 0;
408 }
409 
410 static int jz4740_rtc_resume(struct device *dev)
411 {
412         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
413 
414         if (device_may_wakeup(dev))
415                 disable_irq_wake(rtc->irq);
416         return 0;
417 }
418 
419 static const struct dev_pm_ops jz4740_pm_ops = {
420         .suspend = jz4740_rtc_suspend,
421         .resume  = jz4740_rtc_resume,
422 };
423 #define JZ4740_RTC_PM_OPS (&jz4740_pm_ops)
424 
425 #else
426 #define JZ4740_RTC_PM_OPS NULL
427 #endif  /* CONFIG_PM */
428 
429 static const struct platform_device_id jz4740_rtc_ids[] = {
430         { "jz4740-rtc", ID_JZ4740 },
431         { "jz4780-rtc", ID_JZ4780 },
432         {}
433 };
434 MODULE_DEVICE_TABLE(platform, jz4740_rtc_ids);
435 
436 static struct platform_driver jz4740_rtc_driver = {
437         .probe   = jz4740_rtc_probe,
438         .driver  = {
439                 .name  = "jz4740-rtc",
440                 .pm    = JZ4740_RTC_PM_OPS,
441                 .of_match_table = of_match_ptr(jz4740_rtc_of_match),
442         },
443         .id_table = jz4740_rtc_ids,
444 };
445 
446 module_platform_driver(jz4740_rtc_driver);
447 
448 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
449 MODULE_LICENSE("GPL");
450 MODULE_DESCRIPTION("RTC driver for the JZ4740 SoC\n");
451 MODULE_ALIAS("platform:jz4740-rtc");
452 

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