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Linux/drivers/platform/x86/intel_scu_ipc.c

  1 /*
  2  * intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism
  3  *
  4  * (C) Copyright 2008-2010,2015 Intel Corporation
  5  * Author: Sreedhara DS (sreedhara.ds@intel.com)
  6  *
  7  * This program is free software; you can redistribute it and/or
  8  * modify it under the terms of the GNU General Public License
  9  * as published by the Free Software Foundation; version 2
 10  * of the License.
 11  *
 12  * SCU running in ARC processor communicates with other entity running in IA
 13  * core through IPC mechanism which in turn messaging between IA core ad SCU.
 14  * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
 15  * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
 16  * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
 17  * along with other APIs.
 18  */
 19 #include <linux/delay.h>
 20 #include <linux/errno.h>
 21 #include <linux/init.h>
 22 #include <linux/device.h>
 23 #include <linux/pm.h>
 24 #include <linux/pci.h>
 25 #include <linux/interrupt.h>
 26 #include <linux/sfi.h>
 27 #include <linux/module.h>
 28 #include <asm/intel-mid.h>
 29 #include <asm/intel_scu_ipc.h>
 30 
 31 /* IPC defines the following message types */
 32 #define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */
 33 #define IPCMSG_BATTERY        0xEF /* Coulomb Counter Accumulator */
 34 #define IPCMSG_FW_UPDATE      0xFE /* Firmware update */
 35 #define IPCMSG_PCNTRL         0xFF /* Power controller unit read/write */
 36 #define IPCMSG_FW_REVISION    0xF4 /* Get firmware revision */
 37 
 38 /* Command id associated with message IPCMSG_PCNTRL */
 39 #define IPC_CMD_PCNTRL_W      0 /* Register write */
 40 #define IPC_CMD_PCNTRL_R      1 /* Register read */
 41 #define IPC_CMD_PCNTRL_M      2 /* Register read-modify-write */
 42 
 43 /*
 44  * IPC register summary
 45  *
 46  * IPC register blocks are memory mapped at fixed address of PCI BAR 0.
 47  * To read or write information to the SCU, driver writes to IPC-1 memory
 48  * mapped registers. The following is the IPC mechanism
 49  *
 50  * 1. IA core cDMI interface claims this transaction and converts it to a
 51  *    Transaction Layer Packet (TLP) message which is sent across the cDMI.
 52  *
 53  * 2. South Complex cDMI block receives this message and writes it to
 54  *    the IPC-1 register block, causing an interrupt to the SCU
 55  *
 56  * 3. SCU firmware decodes this interrupt and IPC message and the appropriate
 57  *    message handler is called within firmware.
 58  */
 59 
 60 #define IPC_WWBUF_SIZE    20            /* IPC Write buffer Size */
 61 #define IPC_RWBUF_SIZE    20            /* IPC Read buffer Size */
 62 #define IPC_IOC           0x100         /* IPC command register IOC bit */
 63 
 64 #define PCI_DEVICE_ID_LINCROFT          0x082a
 65 #define PCI_DEVICE_ID_PENWELL           0x080e
 66 #define PCI_DEVICE_ID_CLOVERVIEW        0x08ea
 67 #define PCI_DEVICE_ID_TANGIER           0x11a0
 68 
 69 /* intel scu ipc driver data */
 70 struct intel_scu_ipc_pdata_t {
 71         u32 i2c_base;
 72         u32 i2c_len;
 73         u8 irq_mode;
 74 };
 75 
 76 static struct intel_scu_ipc_pdata_t intel_scu_ipc_lincroft_pdata = {
 77         .i2c_base = 0xff12b000,
 78         .i2c_len = 0x10,
 79         .irq_mode = 0,
 80 };
 81 
 82 /* Penwell and Cloverview */
 83 static struct intel_scu_ipc_pdata_t intel_scu_ipc_penwell_pdata = {
 84         .i2c_base = 0xff12b000,
 85         .i2c_len = 0x10,
 86         .irq_mode = 1,
 87 };
 88 
 89 static struct intel_scu_ipc_pdata_t intel_scu_ipc_tangier_pdata = {
 90         .i2c_base  = 0xff00d000,
 91         .i2c_len = 0x10,
 92         .irq_mode = 0,
 93 };
 94 
 95 struct intel_scu_ipc_dev {
 96         struct device *dev;
 97         void __iomem *ipc_base;
 98         void __iomem *i2c_base;
 99         struct completion cmd_complete;
100         u8 irq_mode;
101 };
102 
103 static struct intel_scu_ipc_dev  ipcdev; /* Only one for now */
104 
105 /*
106  * IPC Read Buffer (Read Only):
107  * 16 byte buffer for receiving data from SCU, if IPC command
108  * processing results in response data
109  */
110 #define IPC_READ_BUFFER         0x90
111 
112 #define IPC_I2C_CNTRL_ADDR      0
113 #define I2C_DATA_ADDR           0x04
114 
115 static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
116 
117 /*
118  * Send ipc command
119  * Command Register (Write Only):
120  * A write to this register results in an interrupt to the SCU core processor
121  * Format:
122  * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
123  */
124 static inline void ipc_command(struct intel_scu_ipc_dev *scu, u32 cmd)
125 {
126         if (scu->irq_mode) {
127                 reinit_completion(&scu->cmd_complete);
128                 writel(cmd | IPC_IOC, scu->ipc_base);
129         }
130         writel(cmd, scu->ipc_base);
131 }
132 
133 /*
134  * Write ipc data
135  * IPC Write Buffer (Write Only):
136  * 16-byte buffer for sending data associated with IPC command to
137  * SCU. Size of the data is specified in the IPC_COMMAND_REG register
138  */
139 static inline void ipc_data_writel(struct intel_scu_ipc_dev *scu, u32 data, u32 offset)
140 {
141         writel(data, scu->ipc_base + 0x80 + offset);
142 }
143 
144 /*
145  * Status Register (Read Only):
146  * Driver will read this register to get the ready/busy status of the IPC
147  * block and error status of the IPC command that was just processed by SCU
148  * Format:
149  * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
150  */
151 static inline u8 ipc_read_status(struct intel_scu_ipc_dev *scu)
152 {
153         return __raw_readl(scu->ipc_base + 0x04);
154 }
155 
156 /* Read ipc byte data */
157 static inline u8 ipc_data_readb(struct intel_scu_ipc_dev *scu, u32 offset)
158 {
159         return readb(scu->ipc_base + IPC_READ_BUFFER + offset);
160 }
161 
162 /* Read ipc u32 data */
163 static inline u32 ipc_data_readl(struct intel_scu_ipc_dev *scu, u32 offset)
164 {
165         return readl(scu->ipc_base + IPC_READ_BUFFER + offset);
166 }
167 
168 /* Wait till scu status is busy */
169 static inline int busy_loop(struct intel_scu_ipc_dev *scu)
170 {
171         u32 status = ipc_read_status(scu);
172         u32 loop_count = 100000;
173 
174         /* break if scu doesn't reset busy bit after huge retry */
175         while ((status & BIT(0)) && --loop_count) {
176                 udelay(1); /* scu processing time is in few u secods */
177                 status = ipc_read_status(scu);
178         }
179 
180         if (status & BIT(0)) {
181                 dev_err(scu->dev, "IPC timed out");
182                 return -ETIMEDOUT;
183         }
184 
185         if (status & BIT(1))
186                 return -EIO;
187 
188         return 0;
189 }
190 
191 /* Wait till ipc ioc interrupt is received or timeout in 3 HZ */
192 static inline int ipc_wait_for_interrupt(struct intel_scu_ipc_dev *scu)
193 {
194         int status;
195 
196         if (!wait_for_completion_timeout(&scu->cmd_complete, 3 * HZ)) {
197                 dev_err(scu->dev, "IPC timed out\n");
198                 return -ETIMEDOUT;
199         }
200 
201         status = ipc_read_status(scu);
202         if (status & BIT(1))
203                 return -EIO;
204 
205         return 0;
206 }
207 
208 static int intel_scu_ipc_check_status(struct intel_scu_ipc_dev *scu)
209 {
210         return scu->irq_mode ? ipc_wait_for_interrupt(scu) : busy_loop(scu);
211 }
212 
213 /* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
214 static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
215 {
216         struct intel_scu_ipc_dev *scu = &ipcdev;
217         int nc;
218         u32 offset = 0;
219         int err;
220         u8 cbuf[IPC_WWBUF_SIZE];
221         u32 *wbuf = (u32 *)&cbuf;
222 
223         memset(cbuf, 0, sizeof(cbuf));
224 
225         mutex_lock(&ipclock);
226 
227         if (scu->dev == NULL) {
228                 mutex_unlock(&ipclock);
229                 return -ENODEV;
230         }
231 
232         for (nc = 0; nc < count; nc++, offset += 2) {
233                 cbuf[offset] = addr[nc];
234                 cbuf[offset + 1] = addr[nc] >> 8;
235         }
236 
237         if (id == IPC_CMD_PCNTRL_R) {
238                 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
239                         ipc_data_writel(scu, wbuf[nc], offset);
240                 ipc_command(scu, (count * 2) << 16 | id << 12 | 0 << 8 | op);
241         } else if (id == IPC_CMD_PCNTRL_W) {
242                 for (nc = 0; nc < count; nc++, offset += 1)
243                         cbuf[offset] = data[nc];
244                 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
245                         ipc_data_writel(scu, wbuf[nc], offset);
246                 ipc_command(scu, (count * 3) << 16 | id << 12 | 0 << 8 | op);
247         } else if (id == IPC_CMD_PCNTRL_M) {
248                 cbuf[offset] = data[0];
249                 cbuf[offset + 1] = data[1];
250                 ipc_data_writel(scu, wbuf[0], 0); /* Write wbuff */
251                 ipc_command(scu, 4 << 16 | id << 12 | 0 << 8 | op);
252         }
253 
254         err = intel_scu_ipc_check_status(scu);
255         if (!err && id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
256                 /* Workaround: values are read as 0 without memcpy_fromio */
257                 memcpy_fromio(cbuf, scu->ipc_base + 0x90, 16);
258                 for (nc = 0; nc < count; nc++)
259                         data[nc] = ipc_data_readb(scu, nc);
260         }
261         mutex_unlock(&ipclock);
262         return err;
263 }
264 
265 /**
266  *      intel_scu_ipc_ioread8           -       read a word via the SCU
267  *      @addr: register on SCU
268  *      @data: return pointer for read byte
269  *
270  *      Read a single register. Returns 0 on success or an error code. All
271  *      locking between SCU accesses is handled for the caller.
272  *
273  *      This function may sleep.
274  */
275 int intel_scu_ipc_ioread8(u16 addr, u8 *data)
276 {
277         return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
278 }
279 EXPORT_SYMBOL(intel_scu_ipc_ioread8);
280 
281 /**
282  *      intel_scu_ipc_ioread16          -       read a word via the SCU
283  *      @addr: register on SCU
284  *      @data: return pointer for read word
285  *
286  *      Read a register pair. Returns 0 on success or an error code. All
287  *      locking between SCU accesses is handled for the caller.
288  *
289  *      This function may sleep.
290  */
291 int intel_scu_ipc_ioread16(u16 addr, u16 *data)
292 {
293         u16 x[2] = {addr, addr + 1};
294         return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
295 }
296 EXPORT_SYMBOL(intel_scu_ipc_ioread16);
297 
298 /**
299  *      intel_scu_ipc_ioread32          -       read a dword via the SCU
300  *      @addr: register on SCU
301  *      @data: return pointer for read dword
302  *
303  *      Read four registers. Returns 0 on success or an error code. All
304  *      locking between SCU accesses is handled for the caller.
305  *
306  *      This function may sleep.
307  */
308 int intel_scu_ipc_ioread32(u16 addr, u32 *data)
309 {
310         u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
311         return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
312 }
313 EXPORT_SYMBOL(intel_scu_ipc_ioread32);
314 
315 /**
316  *      intel_scu_ipc_iowrite8          -       write a byte via the SCU
317  *      @addr: register on SCU
318  *      @data: byte to write
319  *
320  *      Write a single register. Returns 0 on success or an error code. All
321  *      locking between SCU accesses is handled for the caller.
322  *
323  *      This function may sleep.
324  */
325 int intel_scu_ipc_iowrite8(u16 addr, u8 data)
326 {
327         return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
328 }
329 EXPORT_SYMBOL(intel_scu_ipc_iowrite8);
330 
331 /**
332  *      intel_scu_ipc_iowrite16         -       write a word via the SCU
333  *      @addr: register on SCU
334  *      @data: word to write
335  *
336  *      Write two registers. Returns 0 on success or an error code. All
337  *      locking between SCU accesses is handled for the caller.
338  *
339  *      This function may sleep.
340  */
341 int intel_scu_ipc_iowrite16(u16 addr, u16 data)
342 {
343         u16 x[2] = {addr, addr + 1};
344         return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
345 }
346 EXPORT_SYMBOL(intel_scu_ipc_iowrite16);
347 
348 /**
349  *      intel_scu_ipc_iowrite32         -       write a dword via the SCU
350  *      @addr: register on SCU
351  *      @data: dword to write
352  *
353  *      Write four registers. Returns 0 on success or an error code. All
354  *      locking between SCU accesses is handled for the caller.
355  *
356  *      This function may sleep.
357  */
358 int intel_scu_ipc_iowrite32(u16 addr, u32 data)
359 {
360         u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
361         return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
362 }
363 EXPORT_SYMBOL(intel_scu_ipc_iowrite32);
364 
365 /**
366  *      intel_scu_ipc_readvv            -       read a set of registers
367  *      @addr: register list
368  *      @data: bytes to return
369  *      @len: length of array
370  *
371  *      Read registers. Returns 0 on success or an error code. All
372  *      locking between SCU accesses is handled for the caller.
373  *
374  *      The largest array length permitted by the hardware is 5 items.
375  *
376  *      This function may sleep.
377  */
378 int intel_scu_ipc_readv(u16 *addr, u8 *data, int len)
379 {
380         return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
381 }
382 EXPORT_SYMBOL(intel_scu_ipc_readv);
383 
384 /**
385  *      intel_scu_ipc_writev            -       write a set of registers
386  *      @addr: register list
387  *      @data: bytes to write
388  *      @len: length of array
389  *
390  *      Write registers. Returns 0 on success or an error code. All
391  *      locking between SCU accesses is handled for the caller.
392  *
393  *      The largest array length permitted by the hardware is 5 items.
394  *
395  *      This function may sleep.
396  *
397  */
398 int intel_scu_ipc_writev(u16 *addr, u8 *data, int len)
399 {
400         return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
401 }
402 EXPORT_SYMBOL(intel_scu_ipc_writev);
403 
404 /**
405  *      intel_scu_ipc_update_register   -       r/m/w a register
406  *      @addr: register address
407  *      @bits: bits to update
408  *      @mask: mask of bits to update
409  *
410  *      Read-modify-write power control unit register. The first data argument
411  *      must be register value and second is mask value
412  *      mask is a bitmap that indicates which bits to update.
413  *      0 = masked. Don't modify this bit, 1 = modify this bit.
414  *      returns 0 on success or an error code.
415  *
416  *      This function may sleep. Locking between SCU accesses is handled
417  *      for the caller.
418  */
419 int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask)
420 {
421         u8 data[2] = { bits, mask };
422         return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
423 }
424 EXPORT_SYMBOL(intel_scu_ipc_update_register);
425 
426 /**
427  *      intel_scu_ipc_simple_command    -       send a simple command
428  *      @cmd: command
429  *      @sub: sub type
430  *
431  *      Issue a simple command to the SCU. Do not use this interface if
432  *      you must then access data as any data values may be overwritten
433  *      by another SCU access by the time this function returns.
434  *
435  *      This function may sleep. Locking for SCU accesses is handled for
436  *      the caller.
437  */
438 int intel_scu_ipc_simple_command(int cmd, int sub)
439 {
440         struct intel_scu_ipc_dev *scu = &ipcdev;
441         int err;
442 
443         mutex_lock(&ipclock);
444         if (scu->dev == NULL) {
445                 mutex_unlock(&ipclock);
446                 return -ENODEV;
447         }
448         ipc_command(scu, sub << 12 | cmd);
449         err = intel_scu_ipc_check_status(scu);
450         mutex_unlock(&ipclock);
451         return err;
452 }
453 EXPORT_SYMBOL(intel_scu_ipc_simple_command);
454 
455 /**
456  *      intel_scu_ipc_command   -       command with data
457  *      @cmd: command
458  *      @sub: sub type
459  *      @in: input data
460  *      @inlen: input length in dwords
461  *      @out: output data
462  *      @outlein: output length in dwords
463  *
464  *      Issue a command to the SCU which involves data transfers. Do the
465  *      data copies under the lock but leave it for the caller to interpret
466  */
467 int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
468                           u32 *out, int outlen)
469 {
470         struct intel_scu_ipc_dev *scu = &ipcdev;
471         int i, err;
472 
473         mutex_lock(&ipclock);
474         if (scu->dev == NULL) {
475                 mutex_unlock(&ipclock);
476                 return -ENODEV;
477         }
478 
479         for (i = 0; i < inlen; i++)
480                 ipc_data_writel(scu, *in++, 4 * i);
481 
482         ipc_command(scu, (inlen << 16) | (sub << 12) | cmd);
483         err = intel_scu_ipc_check_status(scu);
484 
485         if (!err) {
486                 for (i = 0; i < outlen; i++)
487                         *out++ = ipc_data_readl(scu, 4 * i);
488         }
489 
490         mutex_unlock(&ipclock);
491         return err;
492 }
493 EXPORT_SYMBOL(intel_scu_ipc_command);
494 
495 /* I2C commands */
496 #define IPC_I2C_WRITE 1 /* I2C Write command */
497 #define IPC_I2C_READ  2 /* I2C Read command */
498 
499 /**
500  *      intel_scu_ipc_i2c_cntrl         -       I2C read/write operations
501  *      @addr: I2C address + command bits
502  *      @data: data to read/write
503  *
504  *      Perform an an I2C read/write operation via the SCU. All locking is
505  *      handled for the caller. This function may sleep.
506  *
507  *      Returns an error code or 0 on success.
508  *
509  *      This has to be in the IPC driver for the locking.
510  */
511 int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data)
512 {
513         struct intel_scu_ipc_dev *scu = &ipcdev;
514         u32 cmd = 0;
515 
516         mutex_lock(&ipclock);
517         if (scu->dev == NULL) {
518                 mutex_unlock(&ipclock);
519                 return -ENODEV;
520         }
521         cmd = (addr >> 24) & 0xFF;
522         if (cmd == IPC_I2C_READ) {
523                 writel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);
524                 /* Write not getting updated without delay */
525                 mdelay(1);
526                 *data = readl(scu->i2c_base + I2C_DATA_ADDR);
527         } else if (cmd == IPC_I2C_WRITE) {
528                 writel(*data, scu->i2c_base + I2C_DATA_ADDR);
529                 mdelay(1);
530                 writel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);
531         } else {
532                 dev_err(scu->dev,
533                         "intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd);
534 
535                 mutex_unlock(&ipclock);
536                 return -EIO;
537         }
538         mutex_unlock(&ipclock);
539         return 0;
540 }
541 EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);
542 
543 /*
544  * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
545  * When ioc bit is set to 1, caller api must wait for interrupt handler called
546  * which in turn unlocks the caller api. Currently this is not used
547  *
548  * This is edge triggered so we need take no action to clear anything
549  */
550 static irqreturn_t ioc(int irq, void *dev_id)
551 {
552         struct intel_scu_ipc_dev *scu = dev_id;
553 
554         if (scu->irq_mode)
555                 complete(&scu->cmd_complete);
556 
557         return IRQ_HANDLED;
558 }
559 
560 /**
561  *      ipc_probe       -       probe an Intel SCU IPC
562  *      @pdev: the PCI device matching
563  *      @id: entry in the match table
564  *
565  *      Enable and install an intel SCU IPC. This appears in the PCI space
566  *      but uses some hard coded addresses as well.
567  */
568 static int ipc_probe(struct pci_dev *pdev, const struct pci_device_id *id)
569 {
570         int platform;           /* Platform type */
571         int err;
572         struct intel_scu_ipc_dev *scu = &ipcdev;
573         struct intel_scu_ipc_pdata_t *pdata;
574 
575         platform = intel_mid_identify_cpu();
576         if (platform == 0)
577                 return -ENODEV;
578 
579         if (scu->dev)           /* We support only one SCU */
580                 return -EBUSY;
581 
582         pdata = (struct intel_scu_ipc_pdata_t *)id->driver_data;
583 
584         scu->dev = &pdev->dev;
585         scu->irq_mode = pdata->irq_mode;
586 
587         err = pcim_enable_device(pdev);
588         if (err)
589                 return err;
590 
591         err = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
592         if (err)
593                 return err;
594 
595         init_completion(&scu->cmd_complete);
596 
597         err = devm_request_irq(&pdev->dev, pdev->irq, ioc, 0, "intel_scu_ipc",
598                                scu);
599         if (err)
600                 return err;
601 
602         scu->ipc_base = pcim_iomap_table(pdev)[0];
603 
604         scu->i2c_base = ioremap_nocache(pdata->i2c_base, pdata->i2c_len);
605         if (!scu->i2c_base)
606                 return -ENOMEM;
607 
608         intel_scu_devices_create();
609 
610         pci_set_drvdata(pdev, scu);
611         return 0;
612 }
613 
614 /**
615  *      ipc_remove      -       remove a bound IPC device
616  *      @pdev: PCI device
617  *
618  *      In practice the SCU is not removable but this function is also
619  *      called for each device on a module unload or cleanup which is the
620  *      path that will get used.
621  *
622  *      Free up the mappings and release the PCI resources
623  */
624 static void ipc_remove(struct pci_dev *pdev)
625 {
626         struct intel_scu_ipc_dev *scu = pci_get_drvdata(pdev);
627 
628         mutex_lock(&ipclock);
629         scu->dev = NULL;
630         mutex_unlock(&ipclock);
631 
632         iounmap(scu->i2c_base);
633         intel_scu_devices_destroy();
634 }
635 
636 static const struct pci_device_id pci_ids[] = {
637         {
638                 PCI_VDEVICE(INTEL, PCI_DEVICE_ID_LINCROFT),
639                 (kernel_ulong_t)&intel_scu_ipc_lincroft_pdata,
640         }, {
641                 PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL),
642                 (kernel_ulong_t)&intel_scu_ipc_penwell_pdata,
643         }, {
644                 PCI_VDEVICE(INTEL, PCI_DEVICE_ID_CLOVERVIEW),
645                 (kernel_ulong_t)&intel_scu_ipc_penwell_pdata,
646         }, {
647                 PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER),
648                 (kernel_ulong_t)&intel_scu_ipc_tangier_pdata,
649         }, {
650                 0,
651         }
652 };
653 MODULE_DEVICE_TABLE(pci, pci_ids);
654 
655 static struct pci_driver ipc_driver = {
656         .name = "intel_scu_ipc",
657         .id_table = pci_ids,
658         .probe = ipc_probe,
659         .remove = ipc_remove,
660 };
661 
662 module_pci_driver(ipc_driver);
663 
664 MODULE_AUTHOR("Sreedhara DS <sreedhara.ds@intel.com>");
665 MODULE_DESCRIPTION("Intel SCU IPC driver");
666 MODULE_LICENSE("GPL");
667 

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