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Linux/drivers/pinctrl/sh-pfc/core.c

  1 /*
  2  * Pin Control and GPIO driver for SuperH Pin Function Controller.
  3  *
  4  * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
  5  *
  6  * Copyright (C) 2008 Magnus Damm
  7  * Copyright (C) 2009 - 2012 Paul Mundt
  8  *
  9  * This file is subject to the terms and conditions of the GNU General Public
 10  * License.  See the file "COPYING" in the main directory of this archive
 11  * for more details.
 12  */
 13 
 14 #define DRV_NAME "sh-pfc"
 15 
 16 #include <linux/bitops.h>
 17 #include <linux/err.h>
 18 #include <linux/errno.h>
 19 #include <linux/io.h>
 20 #include <linux/ioport.h>
 21 #include <linux/kernel.h>
 22 #include <linux/init.h>
 23 #include <linux/of.h>
 24 #include <linux/of_device.h>
 25 #include <linux/pinctrl/machine.h>
 26 #include <linux/platform_device.h>
 27 #include <linux/slab.h>
 28 
 29 #include "core.h"
 30 
 31 static int sh_pfc_map_resources(struct sh_pfc *pfc,
 32                                 struct platform_device *pdev)
 33 {
 34         unsigned int num_windows, num_irqs;
 35         struct sh_pfc_window *windows;
 36         unsigned int *irqs = NULL;
 37         struct resource *res;
 38         unsigned int i;
 39         int irq;
 40 
 41         /* Count the MEM and IRQ resources. */
 42         for (num_windows = 0;; num_windows++) {
 43                 res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
 44                 if (!res)
 45                         break;
 46         }
 47         for (num_irqs = 0;; num_irqs++) {
 48                 irq = platform_get_irq(pdev, num_irqs);
 49                 if (irq == -EPROBE_DEFER)
 50                         return irq;
 51                 if (irq < 0)
 52                         break;
 53         }
 54 
 55         if (num_windows == 0)
 56                 return -EINVAL;
 57 
 58         /* Allocate memory windows and IRQs arrays. */
 59         windows = devm_kzalloc(pfc->dev, num_windows * sizeof(*windows),
 60                                GFP_KERNEL);
 61         if (windows == NULL)
 62                 return -ENOMEM;
 63 
 64         pfc->num_windows = num_windows;
 65         pfc->windows = windows;
 66 
 67         if (num_irqs) {
 68                 irqs = devm_kzalloc(pfc->dev, num_irqs * sizeof(*irqs),
 69                                     GFP_KERNEL);
 70                 if (irqs == NULL)
 71                         return -ENOMEM;
 72 
 73                 pfc->num_irqs = num_irqs;
 74                 pfc->irqs = irqs;
 75         }
 76 
 77         /* Fill them. */
 78         for (i = 0; i < num_windows; i++) {
 79                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
 80                 windows->phys = res->start;
 81                 windows->size = resource_size(res);
 82                 windows->virt = devm_ioremap_resource(pfc->dev, res);
 83                 if (IS_ERR(windows->virt))
 84                         return -ENOMEM;
 85                 windows++;
 86         }
 87         for (i = 0; i < num_irqs; i++)
 88                 *irqs++ = platform_get_irq(pdev, i);
 89 
 90         return 0;
 91 }
 92 
 93 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
 94 {
 95         struct sh_pfc_window *window;
 96         phys_addr_t address = reg;
 97         unsigned int i;
 98 
 99         /* scan through physical windows and convert address */
100         for (i = 0; i < pfc->num_windows; i++) {
101                 window = pfc->windows + i;
102 
103                 if (address < window->phys)
104                         continue;
105 
106                 if (address >= (window->phys + window->size))
107                         continue;
108 
109                 return window->virt + (address - window->phys);
110         }
111 
112         BUG();
113         return NULL;
114 }
115 
116 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
117 {
118         unsigned int offset;
119         unsigned int i;
120 
121         for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
122                 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
123 
124                 if (pin <= range->end)
125                         return pin >= range->start
126                              ? offset + pin - range->start : -1;
127 
128                 offset += range->end - range->start + 1;
129         }
130 
131         return -EINVAL;
132 }
133 
134 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
135 {
136         if (enum_id < r->begin)
137                 return 0;
138 
139         if (enum_id > r->end)
140                 return 0;
141 
142         return 1;
143 }
144 
145 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
146 {
147         switch (reg_width) {
148         case 8:
149                 return ioread8(mapped_reg);
150         case 16:
151                 return ioread16(mapped_reg);
152         case 32:
153                 return ioread32(mapped_reg);
154         }
155 
156         BUG();
157         return 0;
158 }
159 
160 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
161                           u32 data)
162 {
163         switch (reg_width) {
164         case 8:
165                 iowrite8(data, mapped_reg);
166                 return;
167         case 16:
168                 iowrite16(data, mapped_reg);
169                 return;
170         case 32:
171                 iowrite32(data, mapped_reg);
172                 return;
173         }
174 
175         BUG();
176 }
177 
178 u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width)
179 {
180         return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), width);
181 }
182 
183 void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data)
184 {
185         if (pfc->info->unlock_reg)
186                 sh_pfc_write_raw_reg(
187                         sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
188                         ~data);
189 
190         sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), width, data);
191 }
192 
193 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
194                                      const struct pinmux_cfg_reg *crp,
195                                      unsigned int in_pos,
196                                      void __iomem **mapped_regp, u32 *maskp,
197                                      unsigned int *posp)
198 {
199         unsigned int k;
200 
201         *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
202 
203         if (crp->field_width) {
204                 *maskp = (1 << crp->field_width) - 1;
205                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
206         } else {
207                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
208                 *posp = crp->reg_width;
209                 for (k = 0; k <= in_pos; k++)
210                         *posp -= crp->var_field_width[k];
211         }
212 }
213 
214 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
215                                     const struct pinmux_cfg_reg *crp,
216                                     unsigned int field, u32 value)
217 {
218         void __iomem *mapped_reg;
219         unsigned int pos;
220         u32 mask, data;
221 
222         sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
223 
224         dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
225                 "r_width = %u, f_width = %u\n",
226                 crp->reg, value, field, crp->reg_width, crp->field_width);
227 
228         mask = ~(mask << pos);
229         value = value << pos;
230 
231         data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
232         data &= mask;
233         data |= value;
234 
235         if (pfc->info->unlock_reg)
236                 sh_pfc_write_raw_reg(
237                         sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
238                         ~data);
239 
240         sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
241 }
242 
243 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
244                                  const struct pinmux_cfg_reg **crp,
245                                  unsigned int *fieldp, u32 *valuep)
246 {
247         unsigned int k = 0;
248 
249         while (1) {
250                 const struct pinmux_cfg_reg *config_reg =
251                         pfc->info->cfg_regs + k;
252                 unsigned int r_width = config_reg->reg_width;
253                 unsigned int f_width = config_reg->field_width;
254                 unsigned int curr_width;
255                 unsigned int bit_pos;
256                 unsigned int pos = 0;
257                 unsigned int m = 0;
258 
259                 if (!r_width)
260                         break;
261 
262                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
263                         u32 ncomb;
264                         u32 n;
265 
266                         if (f_width)
267                                 curr_width = f_width;
268                         else
269                                 curr_width = config_reg->var_field_width[m];
270 
271                         ncomb = 1 << curr_width;
272                         for (n = 0; n < ncomb; n++) {
273                                 if (config_reg->enum_ids[pos + n] == enum_id) {
274                                         *crp = config_reg;
275                                         *fieldp = m;
276                                         *valuep = n;
277                                         return 0;
278                                 }
279                         }
280                         pos += ncomb;
281                         m++;
282                 }
283                 k++;
284         }
285 
286         return -EINVAL;
287 }
288 
289 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
290                               u16 *enum_idp)
291 {
292         const u16 *data = pfc->info->pinmux_data;
293         unsigned int k;
294 
295         if (pos) {
296                 *enum_idp = data[pos + 1];
297                 return pos + 1;
298         }
299 
300         for (k = 0; k < pfc->info->pinmux_data_size; k++) {
301                 if (data[k] == mark) {
302                         *enum_idp = data[k + 1];
303                         return k + 1;
304                 }
305         }
306 
307         dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
308                 mark);
309         return -EINVAL;
310 }
311 
312 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
313 {
314         const struct pinmux_range *range;
315         int pos = 0;
316 
317         switch (pinmux_type) {
318         case PINMUX_TYPE_GPIO:
319         case PINMUX_TYPE_FUNCTION:
320                 range = NULL;
321                 break;
322 
323         case PINMUX_TYPE_OUTPUT:
324                 range = &pfc->info->output;
325                 break;
326 
327         case PINMUX_TYPE_INPUT:
328                 range = &pfc->info->input;
329                 break;
330 
331         default:
332                 return -EINVAL;
333         }
334 
335         /* Iterate over all the configuration fields we need to update. */
336         while (1) {
337                 const struct pinmux_cfg_reg *cr;
338                 unsigned int field;
339                 u16 enum_id;
340                 u32 value;
341                 int in_range;
342                 int ret;
343 
344                 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
345                 if (pos < 0)
346                         return pos;
347 
348                 if (!enum_id)
349                         break;
350 
351                 /* Check if the configuration field selects a function. If it
352                  * doesn't, skip the field if it's not applicable to the
353                  * requested pinmux type.
354                  */
355                 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
356                 if (!in_range) {
357                         if (pinmux_type == PINMUX_TYPE_FUNCTION) {
358                                 /* Functions are allowed to modify all
359                                  * fields.
360                                  */
361                                 in_range = 1;
362                         } else if (pinmux_type != PINMUX_TYPE_GPIO) {
363                                 /* Input/output types can only modify fields
364                                  * that correspond to their respective ranges.
365                                  */
366                                 in_range = sh_pfc_enum_in_range(enum_id, range);
367 
368                                 /*
369                                  * special case pass through for fixed
370                                  * input-only or output-only pins without
371                                  * function enum register association.
372                                  */
373                                 if (in_range && enum_id == range->force)
374                                         continue;
375                         }
376                         /* GPIOs are only allowed to modify function fields. */
377                 }
378 
379                 if (!in_range)
380                         continue;
381 
382                 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
383                 if (ret < 0)
384                         return ret;
385 
386                 sh_pfc_write_config_reg(pfc, cr, field, value);
387         }
388 
389         return 0;
390 }
391 
392 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
393 {
394         struct sh_pfc_pin_range *range;
395         unsigned int nr_ranges;
396         unsigned int i;
397 
398         if (pfc->info->pins[0].pin == (u16)-1) {
399                 /* Pin number -1 denotes that the SoC doesn't report pin numbers
400                  * in its pin arrays yet. Consider the pin numbers range as
401                  * continuous and allocate a single range.
402                  */
403                 pfc->nr_ranges = 1;
404                 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
405                                            GFP_KERNEL);
406                 if (pfc->ranges == NULL)
407                         return -ENOMEM;
408 
409                 pfc->ranges->start = 0;
410                 pfc->ranges->end = pfc->info->nr_pins - 1;
411                 pfc->nr_gpio_pins = pfc->info->nr_pins;
412 
413                 return 0;
414         }
415 
416         /* Count, allocate and fill the ranges. The PFC SoC data pins array must
417          * be sorted by pin numbers, and pins without a GPIO port must come
418          * last.
419          */
420         for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
421                 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
422                         nr_ranges++;
423         }
424 
425         pfc->nr_ranges = nr_ranges;
426         pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges) * nr_ranges,
427                                    GFP_KERNEL);
428         if (pfc->ranges == NULL)
429                 return -ENOMEM;
430 
431         range = pfc->ranges;
432         range->start = pfc->info->pins[0].pin;
433 
434         for (i = 1; i < pfc->info->nr_pins; ++i) {
435                 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
436                         continue;
437 
438                 range->end = pfc->info->pins[i-1].pin;
439                 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
440                         pfc->nr_gpio_pins = range->end + 1;
441 
442                 range++;
443                 range->start = pfc->info->pins[i].pin;
444         }
445 
446         range->end = pfc->info->pins[i-1].pin;
447         if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
448                 pfc->nr_gpio_pins = range->end + 1;
449 
450         return 0;
451 }
452 
453 #ifdef CONFIG_OF
454 static const struct of_device_id sh_pfc_of_table[] = {
455 #ifdef CONFIG_PINCTRL_PFC_EMEV2
456         {
457                 .compatible = "renesas,pfc-emev2",
458                 .data = &emev2_pinmux_info,
459         },
460 #endif
461 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
462         {
463                 .compatible = "renesas,pfc-r8a73a4",
464                 .data = &r8a73a4_pinmux_info,
465         },
466 #endif
467 #ifdef CONFIG_PINCTRL_PFC_R8A7740
468         {
469                 .compatible = "renesas,pfc-r8a7740",
470                 .data = &r8a7740_pinmux_info,
471         },
472 #endif
473 #ifdef CONFIG_PINCTRL_PFC_R8A7778
474         {
475                 .compatible = "renesas,pfc-r8a7778",
476                 .data = &r8a7778_pinmux_info,
477         },
478 #endif
479 #ifdef CONFIG_PINCTRL_PFC_R8A7779
480         {
481                 .compatible = "renesas,pfc-r8a7779",
482                 .data = &r8a7779_pinmux_info,
483         },
484 #endif
485 #ifdef CONFIG_PINCTRL_PFC_R8A7790
486         {
487                 .compatible = "renesas,pfc-r8a7790",
488                 .data = &r8a7790_pinmux_info,
489         },
490 #endif
491 #ifdef CONFIG_PINCTRL_PFC_R8A7791
492         {
493                 .compatible = "renesas,pfc-r8a7791",
494                 .data = &r8a7791_pinmux_info,
495         },
496 #endif
497 #ifdef CONFIG_PINCTRL_PFC_R8A7793
498         {
499                 .compatible = "renesas,pfc-r8a7793",
500                 .data = &r8a7793_pinmux_info,
501         },
502 #endif
503 #ifdef CONFIG_PINCTRL_PFC_R8A7794
504         {
505                 .compatible = "renesas,pfc-r8a7794",
506                 .data = &r8a7794_pinmux_info,
507         },
508 #endif
509 #ifdef CONFIG_PINCTRL_PFC_R8A7795
510         {
511                 .compatible = "renesas,pfc-r8a7795",
512                 .data = &r8a7795_pinmux_info,
513         },
514 #endif
515 #ifdef CONFIG_PINCTRL_PFC_SH73A0
516         {
517                 .compatible = "renesas,pfc-sh73a0",
518                 .data = &sh73a0_pinmux_info,
519         },
520 #endif
521         { },
522 };
523 #endif
524 
525 static int sh_pfc_probe(struct platform_device *pdev)
526 {
527         const struct platform_device_id *platid = platform_get_device_id(pdev);
528 #ifdef CONFIG_OF
529         struct device_node *np = pdev->dev.of_node;
530 #endif
531         const struct sh_pfc_soc_info *info;
532         struct sh_pfc *pfc;
533         int ret;
534 
535 #ifdef CONFIG_OF
536         if (np)
537                 info = of_device_get_match_data(&pdev->dev);
538         else
539 #endif
540                 info = platid ? (const void *)platid->driver_data : NULL;
541 
542         if (info == NULL)
543                 return -ENODEV;
544 
545         pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
546         if (pfc == NULL)
547                 return -ENOMEM;
548 
549         pfc->info = info;
550         pfc->dev = &pdev->dev;
551 
552         ret = sh_pfc_map_resources(pfc, pdev);
553         if (unlikely(ret < 0))
554                 return ret;
555 
556         spin_lock_init(&pfc->lock);
557 
558         if (info->ops && info->ops->init) {
559                 ret = info->ops->init(pfc);
560                 if (ret < 0)
561                         return ret;
562         }
563 
564         /* Enable dummy states for those platforms without pinctrl support */
565         if (!of_have_populated_dt())
566                 pinctrl_provide_dummies();
567 
568         ret = sh_pfc_init_ranges(pfc);
569         if (ret < 0)
570                 return ret;
571 
572         /*
573          * Initialize pinctrl bindings first
574          */
575         ret = sh_pfc_register_pinctrl(pfc);
576         if (unlikely(ret != 0))
577                 return ret;
578 
579 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
580         /*
581          * Then the GPIO chip
582          */
583         ret = sh_pfc_register_gpiochip(pfc);
584         if (unlikely(ret != 0)) {
585                 /*
586                  * If the GPIO chip fails to come up we still leave the
587                  * PFC state as it is, given that there are already
588                  * extant users of it that have succeeded by this point.
589                  */
590                 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
591         }
592 #endif
593 
594         platform_set_drvdata(pdev, pfc);
595 
596         dev_info(pfc->dev, "%s support registered\n", info->name);
597 
598         return 0;
599 }
600 
601 static int sh_pfc_remove(struct platform_device *pdev)
602 {
603 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
604         sh_pfc_unregister_gpiochip(platform_get_drvdata(pdev));
605 #endif
606 
607         return 0;
608 }
609 
610 static const struct platform_device_id sh_pfc_id_table[] = {
611 #ifdef CONFIG_PINCTRL_PFC_SH7203
612         { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
613 #endif
614 #ifdef CONFIG_PINCTRL_PFC_SH7264
615         { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
616 #endif
617 #ifdef CONFIG_PINCTRL_PFC_SH7269
618         { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
619 #endif
620 #ifdef CONFIG_PINCTRL_PFC_SH7720
621         { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
622 #endif
623 #ifdef CONFIG_PINCTRL_PFC_SH7722
624         { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
625 #endif
626 #ifdef CONFIG_PINCTRL_PFC_SH7723
627         { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
628 #endif
629 #ifdef CONFIG_PINCTRL_PFC_SH7724
630         { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
631 #endif
632 #ifdef CONFIG_PINCTRL_PFC_SH7734
633         { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
634 #endif
635 #ifdef CONFIG_PINCTRL_PFC_SH7757
636         { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
637 #endif
638 #ifdef CONFIG_PINCTRL_PFC_SH7785
639         { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
640 #endif
641 #ifdef CONFIG_PINCTRL_PFC_SH7786
642         { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
643 #endif
644 #ifdef CONFIG_PINCTRL_PFC_SHX3
645         { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
646 #endif
647         { "sh-pfc", 0 },
648         { },
649 };
650 
651 static struct platform_driver sh_pfc_driver = {
652         .probe          = sh_pfc_probe,
653         .remove         = sh_pfc_remove,
654         .id_table       = sh_pfc_id_table,
655         .driver         = {
656                 .name   = DRV_NAME,
657                 .of_match_table = of_match_ptr(sh_pfc_of_table),
658         },
659 };
660 
661 static int __init sh_pfc_init(void)
662 {
663         return platform_driver_register(&sh_pfc_driver);
664 }
665 postcore_initcall(sh_pfc_init);
666 

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