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Linux/drivers/pinctrl/sh-pfc/core.c

  1 /*
  2  * SuperH Pin Function Controller support.
  3  *
  4  * Copyright (C) 2008 Magnus Damm
  5  * Copyright (C) 2009 - 2012 Paul Mundt
  6  *
  7  * This file is subject to the terms and conditions of the GNU General Public
  8  * License.  See the file "COPYING" in the main directory of this archive
  9  * for more details.
 10  */
 11 
 12 #define DRV_NAME "sh-pfc"
 13 
 14 #include <linux/bitops.h>
 15 #include <linux/err.h>
 16 #include <linux/errno.h>
 17 #include <linux/io.h>
 18 #include <linux/ioport.h>
 19 #include <linux/kernel.h>
 20 #include <linux/module.h>
 21 #include <linux/of.h>
 22 #include <linux/of_device.h>
 23 #include <linux/pinctrl/machine.h>
 24 #include <linux/platform_device.h>
 25 #include <linux/slab.h>
 26 
 27 #include "core.h"
 28 
 29 static int sh_pfc_map_resources(struct sh_pfc *pfc,
 30                                 struct platform_device *pdev)
 31 {
 32         unsigned int num_windows = 0;
 33         unsigned int num_irqs = 0;
 34         struct sh_pfc_window *windows;
 35         unsigned int *irqs = NULL;
 36         struct resource *res;
 37         unsigned int i;
 38 
 39         /* Count the MEM and IRQ resources. */
 40         for (i = 0; i < pdev->num_resources; ++i) {
 41                 switch (resource_type(&pdev->resource[i])) {
 42                 case IORESOURCE_MEM:
 43                         num_windows++;
 44                         break;
 45 
 46                 case IORESOURCE_IRQ:
 47                         num_irqs++;
 48                         break;
 49                 }
 50         }
 51 
 52         if (num_windows == 0)
 53                 return -EINVAL;
 54 
 55         /* Allocate memory windows and IRQs arrays. */
 56         windows = devm_kzalloc(pfc->dev, num_windows * sizeof(*windows),
 57                                GFP_KERNEL);
 58         if (windows == NULL)
 59                 return -ENOMEM;
 60 
 61         pfc->num_windows = num_windows;
 62         pfc->windows = windows;
 63 
 64         if (num_irqs) {
 65                 irqs = devm_kzalloc(pfc->dev, num_irqs * sizeof(*irqs),
 66                                     GFP_KERNEL);
 67                 if (irqs == NULL)
 68                         return -ENOMEM;
 69 
 70                 pfc->num_irqs = num_irqs;
 71                 pfc->irqs = irqs;
 72         }
 73 
 74         /* Fill them. */
 75         for (i = 0, res = pdev->resource; i < pdev->num_resources; i++, res++) {
 76                 switch (resource_type(res)) {
 77                 case IORESOURCE_MEM:
 78                         windows->phys = res->start;
 79                         windows->size = resource_size(res);
 80                         windows->virt = devm_ioremap_resource(pfc->dev, res);
 81                         if (IS_ERR(windows->virt))
 82                                 return -ENOMEM;
 83                         windows++;
 84                         break;
 85 
 86                 case IORESOURCE_IRQ:
 87                         *irqs++ = res->start;
 88                         break;
 89                 }
 90         }
 91 
 92         return 0;
 93 }
 94 
 95 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
 96                                          unsigned long address)
 97 {
 98         struct sh_pfc_window *window;
 99         unsigned int i;
100 
101         /* scan through physical windows and convert address */
102         for (i = 0; i < pfc->num_windows; i++) {
103                 window = pfc->windows + i;
104 
105                 if (address < window->phys)
106                         continue;
107 
108                 if (address >= (window->phys + window->size))
109                         continue;
110 
111                 return window->virt + (address - window->phys);
112         }
113 
114         BUG();
115         return NULL;
116 }
117 
118 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
119 {
120         unsigned int offset;
121         unsigned int i;
122 
123         for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
124                 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
125 
126                 if (pin <= range->end)
127                         return pin >= range->start
128                              ? offset + pin - range->start : -1;
129 
130                 offset += range->end - range->start + 1;
131         }
132 
133         return -EINVAL;
134 }
135 
136 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
137 {
138         if (enum_id < r->begin)
139                 return 0;
140 
141         if (enum_id > r->end)
142                 return 0;
143 
144         return 1;
145 }
146 
147 unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
148                                   unsigned long reg_width)
149 {
150         switch (reg_width) {
151         case 8:
152                 return ioread8(mapped_reg);
153         case 16:
154                 return ioread16(mapped_reg);
155         case 32:
156                 return ioread32(mapped_reg);
157         }
158 
159         BUG();
160         return 0;
161 }
162 
163 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
164                           unsigned long data)
165 {
166         switch (reg_width) {
167         case 8:
168                 iowrite8(data, mapped_reg);
169                 return;
170         case 16:
171                 iowrite16(data, mapped_reg);
172                 return;
173         case 32:
174                 iowrite32(data, mapped_reg);
175                 return;
176         }
177 
178         BUG();
179 }
180 
181 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
182                                      const struct pinmux_cfg_reg *crp,
183                                      unsigned long in_pos,
184                                      void __iomem **mapped_regp,
185                                      unsigned long *maskp,
186                                      unsigned long *posp)
187 {
188         unsigned int k;
189 
190         *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
191 
192         if (crp->field_width) {
193                 *maskp = (1 << crp->field_width) - 1;
194                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
195         } else {
196                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
197                 *posp = crp->reg_width;
198                 for (k = 0; k <= in_pos; k++)
199                         *posp -= crp->var_field_width[k];
200         }
201 }
202 
203 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
204                                     const struct pinmux_cfg_reg *crp,
205                                     unsigned long field, unsigned long value)
206 {
207         void __iomem *mapped_reg;
208         unsigned long mask, pos, data;
209 
210         sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
211 
212         dev_dbg(pfc->dev, "write_reg addr = %lx, value = %ld, field = %ld, "
213                 "r_width = %ld, f_width = %ld\n",
214                 crp->reg, value, field, crp->reg_width, crp->field_width);
215 
216         mask = ~(mask << pos);
217         value = value << pos;
218 
219         data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
220         data &= mask;
221         data |= value;
222 
223         if (pfc->info->unlock_reg)
224                 sh_pfc_write_raw_reg(
225                         sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
226                         ~data);
227 
228         sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
229 }
230 
231 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
232                                  const struct pinmux_cfg_reg **crp, int *fieldp,
233                                  int *valuep)
234 {
235         const struct pinmux_cfg_reg *config_reg;
236         unsigned long r_width, f_width, curr_width, ncomb;
237         unsigned int k, m, n, pos, bit_pos;
238 
239         k = 0;
240         while (1) {
241                 config_reg = pfc->info->cfg_regs + k;
242 
243                 r_width = config_reg->reg_width;
244                 f_width = config_reg->field_width;
245 
246                 if (!r_width)
247                         break;
248 
249                 pos = 0;
250                 m = 0;
251                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
252                         if (f_width)
253                                 curr_width = f_width;
254                         else
255                                 curr_width = config_reg->var_field_width[m];
256 
257                         ncomb = 1 << curr_width;
258                         for (n = 0; n < ncomb; n++) {
259                                 if (config_reg->enum_ids[pos + n] == enum_id) {
260                                         *crp = config_reg;
261                                         *fieldp = m;
262                                         *valuep = n;
263                                         return 0;
264                                 }
265                         }
266                         pos += ncomb;
267                         m++;
268                 }
269                 k++;
270         }
271 
272         return -EINVAL;
273 }
274 
275 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
276                               u16 *enum_idp)
277 {
278         const u16 *data = pfc->info->gpio_data;
279         unsigned int k;
280 
281         if (pos) {
282                 *enum_idp = data[pos + 1];
283                 return pos + 1;
284         }
285 
286         for (k = 0; k < pfc->info->gpio_data_size; k++) {
287                 if (data[k] == mark) {
288                         *enum_idp = data[k + 1];
289                         return k + 1;
290                 }
291         }
292 
293         dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
294                 mark);
295         return -EINVAL;
296 }
297 
298 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
299 {
300         const struct pinmux_cfg_reg *cr = NULL;
301         u16 enum_id;
302         const struct pinmux_range *range;
303         int in_range, pos, field, value;
304         int ret;
305 
306         switch (pinmux_type) {
307         case PINMUX_TYPE_GPIO:
308         case PINMUX_TYPE_FUNCTION:
309                 range = NULL;
310                 break;
311 
312         case PINMUX_TYPE_OUTPUT:
313                 range = &pfc->info->output;
314                 break;
315 
316         case PINMUX_TYPE_INPUT:
317                 range = &pfc->info->input;
318                 break;
319 
320         default:
321                 return -EINVAL;
322         }
323 
324         pos = 0;
325         enum_id = 0;
326         field = 0;
327         value = 0;
328 
329         /* Iterate over all the configuration fields we need to update. */
330         while (1) {
331                 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
332                 if (pos < 0)
333                         return pos;
334 
335                 if (!enum_id)
336                         break;
337 
338                 /* Check if the configuration field selects a function. If it
339                  * doesn't, skip the field if it's not applicable to the
340                  * requested pinmux type.
341                  */
342                 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
343                 if (!in_range) {
344                         if (pinmux_type == PINMUX_TYPE_FUNCTION) {
345                                 /* Functions are allowed to modify all
346                                  * fields.
347                                  */
348                                 in_range = 1;
349                         } else if (pinmux_type != PINMUX_TYPE_GPIO) {
350                                 /* Input/output types can only modify fields
351                                  * that correspond to their respective ranges.
352                                  */
353                                 in_range = sh_pfc_enum_in_range(enum_id, range);
354 
355                                 /*
356                                  * special case pass through for fixed
357                                  * input-only or output-only pins without
358                                  * function enum register association.
359                                  */
360                                 if (in_range && enum_id == range->force)
361                                         continue;
362                         }
363                         /* GPIOs are only allowed to modify function fields. */
364                 }
365 
366                 if (!in_range)
367                         continue;
368 
369                 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
370                 if (ret < 0)
371                         return ret;
372 
373                 sh_pfc_write_config_reg(pfc, cr, field, value);
374         }
375 
376         return 0;
377 }
378 
379 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
380 {
381         struct sh_pfc_pin_range *range;
382         unsigned int nr_ranges;
383         unsigned int i;
384 
385         if (pfc->info->pins[0].pin == (u16)-1) {
386                 /* Pin number -1 denotes that the SoC doesn't report pin numbers
387                  * in its pin arrays yet. Consider the pin numbers range as
388                  * continuous and allocate a single range.
389                  */
390                 pfc->nr_ranges = 1;
391                 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
392                                            GFP_KERNEL);
393                 if (pfc->ranges == NULL)
394                         return -ENOMEM;
395 
396                 pfc->ranges->start = 0;
397                 pfc->ranges->end = pfc->info->nr_pins - 1;
398                 pfc->nr_gpio_pins = pfc->info->nr_pins;
399 
400                 return 0;
401         }
402 
403         /* Count, allocate and fill the ranges. The PFC SoC data pins array must
404          * be sorted by pin numbers, and pins without a GPIO port must come
405          * last.
406          */
407         for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
408                 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
409                         nr_ranges++;
410         }
411 
412         pfc->nr_ranges = nr_ranges;
413         pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges) * nr_ranges,
414                                    GFP_KERNEL);
415         if (pfc->ranges == NULL)
416                 return -ENOMEM;
417 
418         range = pfc->ranges;
419         range->start = pfc->info->pins[0].pin;
420 
421         for (i = 1; i < pfc->info->nr_pins; ++i) {
422                 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
423                         continue;
424 
425                 range->end = pfc->info->pins[i-1].pin;
426                 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
427                         pfc->nr_gpio_pins = range->end + 1;
428 
429                 range++;
430                 range->start = pfc->info->pins[i].pin;
431         }
432 
433         range->end = pfc->info->pins[i-1].pin;
434         if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
435                 pfc->nr_gpio_pins = range->end + 1;
436 
437         return 0;
438 }
439 
440 #ifdef CONFIG_OF
441 static const struct of_device_id sh_pfc_of_table[] = {
442 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
443         {
444                 .compatible = "renesas,pfc-r8a73a4",
445                 .data = &r8a73a4_pinmux_info,
446         },
447 #endif
448 #ifdef CONFIG_PINCTRL_PFC_R8A7740
449         {
450                 .compatible = "renesas,pfc-r8a7740",
451                 .data = &r8a7740_pinmux_info,
452         },
453 #endif
454 #ifdef CONFIG_PINCTRL_PFC_R8A7778
455         {
456                 .compatible = "renesas,pfc-r8a7778",
457                 .data = &r8a7778_pinmux_info,
458         },
459 #endif
460 #ifdef CONFIG_PINCTRL_PFC_R8A7779
461         {
462                 .compatible = "renesas,pfc-r8a7779",
463                 .data = &r8a7779_pinmux_info,
464         },
465 #endif
466 #ifdef CONFIG_PINCTRL_PFC_R8A7790
467         {
468                 .compatible = "renesas,pfc-r8a7790",
469                 .data = &r8a7790_pinmux_info,
470         },
471 #endif
472 #ifdef CONFIG_PINCTRL_PFC_R8A7791
473         {
474                 .compatible = "renesas,pfc-r8a7791",
475                 .data = &r8a7791_pinmux_info,
476         },
477 #endif
478 #ifdef CONFIG_PINCTRL_PFC_SH7372
479         {
480                 .compatible = "renesas,pfc-sh7372",
481                 .data = &sh7372_pinmux_info,
482         },
483 #endif
484 #ifdef CONFIG_PINCTRL_PFC_SH73A0
485         {
486                 .compatible = "renesas,pfc-sh73a0",
487                 .data = &sh73a0_pinmux_info,
488         },
489 #endif
490         { },
491 };
492 MODULE_DEVICE_TABLE(of, sh_pfc_of_table);
493 #endif
494 
495 static int sh_pfc_probe(struct platform_device *pdev)
496 {
497         const struct platform_device_id *platid = platform_get_device_id(pdev);
498 #ifdef CONFIG_OF
499         struct device_node *np = pdev->dev.of_node;
500 #endif
501         const struct sh_pfc_soc_info *info;
502         struct sh_pfc *pfc;
503         int ret;
504 
505 #ifdef CONFIG_OF
506         if (np)
507                 info = of_match_device(sh_pfc_of_table, &pdev->dev)->data;
508         else
509 #endif
510                 info = platid ? (const void *)platid->driver_data : NULL;
511 
512         if (info == NULL)
513                 return -ENODEV;
514 
515         pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
516         if (pfc == NULL)
517                 return -ENOMEM;
518 
519         pfc->info = info;
520         pfc->dev = &pdev->dev;
521 
522         ret = sh_pfc_map_resources(pfc, pdev);
523         if (unlikely(ret < 0))
524                 return ret;
525 
526         spin_lock_init(&pfc->lock);
527 
528         if (info->ops && info->ops->init) {
529                 ret = info->ops->init(pfc);
530                 if (ret < 0)
531                         return ret;
532         }
533 
534         pinctrl_provide_dummies();
535 
536         ret = sh_pfc_init_ranges(pfc);
537         if (ret < 0)
538                 return ret;
539 
540         /*
541          * Initialize pinctrl bindings first
542          */
543         ret = sh_pfc_register_pinctrl(pfc);
544         if (unlikely(ret != 0))
545                 return ret;
546 
547 #ifdef CONFIG_GPIO_SH_PFC
548         /*
549          * Then the GPIO chip
550          */
551         ret = sh_pfc_register_gpiochip(pfc);
552         if (unlikely(ret != 0)) {
553                 /*
554                  * If the GPIO chip fails to come up we still leave the
555                  * PFC state as it is, given that there are already
556                  * extant users of it that have succeeded by this point.
557                  */
558                 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
559         }
560 #endif
561 
562         platform_set_drvdata(pdev, pfc);
563 
564         dev_info(pfc->dev, "%s support registered\n", info->name);
565 
566         return 0;
567 }
568 
569 static int sh_pfc_remove(struct platform_device *pdev)
570 {
571         struct sh_pfc *pfc = platform_get_drvdata(pdev);
572 
573 #ifdef CONFIG_GPIO_SH_PFC
574         sh_pfc_unregister_gpiochip(pfc);
575 #endif
576         sh_pfc_unregister_pinctrl(pfc);
577 
578         return 0;
579 }
580 
581 static const struct platform_device_id sh_pfc_id_table[] = {
582 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
583         { "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info },
584 #endif
585 #ifdef CONFIG_PINCTRL_PFC_R8A7740
586         { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
587 #endif
588 #ifdef CONFIG_PINCTRL_PFC_R8A7778
589         { "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info },
590 #endif
591 #ifdef CONFIG_PINCTRL_PFC_R8A7779
592         { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
593 #endif
594 #ifdef CONFIG_PINCTRL_PFC_R8A7790
595         { "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info },
596 #endif
597 #ifdef CONFIG_PINCTRL_PFC_R8A7791
598         { "pfc-r8a7791", (kernel_ulong_t)&r8a7791_pinmux_info },
599 #endif
600 #ifdef CONFIG_PINCTRL_PFC_SH7203
601         { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
602 #endif
603 #ifdef CONFIG_PINCTRL_PFC_SH7264
604         { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
605 #endif
606 #ifdef CONFIG_PINCTRL_PFC_SH7269
607         { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
608 #endif
609 #ifdef CONFIG_PINCTRL_PFC_SH7372
610         { "pfc-sh7372", (kernel_ulong_t)&sh7372_pinmux_info },
611 #endif
612 #ifdef CONFIG_PINCTRL_PFC_SH73A0
613         { "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info },
614 #endif
615 #ifdef CONFIG_PINCTRL_PFC_SH7720
616         { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
617 #endif
618 #ifdef CONFIG_PINCTRL_PFC_SH7722
619         { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
620 #endif
621 #ifdef CONFIG_PINCTRL_PFC_SH7723
622         { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
623 #endif
624 #ifdef CONFIG_PINCTRL_PFC_SH7724
625         { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
626 #endif
627 #ifdef CONFIG_PINCTRL_PFC_SH7734
628         { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
629 #endif
630 #ifdef CONFIG_PINCTRL_PFC_SH7757
631         { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
632 #endif
633 #ifdef CONFIG_PINCTRL_PFC_SH7785
634         { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
635 #endif
636 #ifdef CONFIG_PINCTRL_PFC_SH7786
637         { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
638 #endif
639 #ifdef CONFIG_PINCTRL_PFC_SHX3
640         { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
641 #endif
642         { "sh-pfc", 0 },
643         { },
644 };
645 MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);
646 
647 static struct platform_driver sh_pfc_driver = {
648         .probe          = sh_pfc_probe,
649         .remove         = sh_pfc_remove,
650         .id_table       = sh_pfc_id_table,
651         .driver         = {
652                 .name   = DRV_NAME,
653                 .owner  = THIS_MODULE,
654                 .of_match_table = of_match_ptr(sh_pfc_of_table),
655         },
656 };
657 
658 static int __init sh_pfc_init(void)
659 {
660         return platform_driver_register(&sh_pfc_driver);
661 }
662 postcore_initcall(sh_pfc_init);
663 
664 static void __exit sh_pfc_exit(void)
665 {
666         platform_driver_unregister(&sh_pfc_driver);
667 }
668 module_exit(sh_pfc_exit);
669 
670 MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
671 MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
672 MODULE_LICENSE("GPL v2");
673 

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