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Linux/drivers/pinctrl/sh-pfc/core.c

  1 /*
  2  * Pin Control and GPIO driver for SuperH Pin Function Controller.
  3  *
  4  * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
  5  *
  6  * Copyright (C) 2008 Magnus Damm
  7  * Copyright (C) 2009 - 2012 Paul Mundt
  8  *
  9  * This file is subject to the terms and conditions of the GNU General Public
 10  * License.  See the file "COPYING" in the main directory of this archive
 11  * for more details.
 12  */
 13 
 14 #define DRV_NAME "sh-pfc"
 15 
 16 #include <linux/bitops.h>
 17 #include <linux/err.h>
 18 #include <linux/errno.h>
 19 #include <linux/io.h>
 20 #include <linux/ioport.h>
 21 #include <linux/kernel.h>
 22 #include <linux/init.h>
 23 #include <linux/of.h>
 24 #include <linux/of_device.h>
 25 #include <linux/pinctrl/machine.h>
 26 #include <linux/platform_device.h>
 27 #include <linux/slab.h>
 28 
 29 #include "core.h"
 30 
 31 static int sh_pfc_map_resources(struct sh_pfc *pfc,
 32                                 struct platform_device *pdev)
 33 {
 34         unsigned int num_windows, num_irqs;
 35         struct sh_pfc_window *windows;
 36         unsigned int *irqs = NULL;
 37         struct resource *res;
 38         unsigned int i;
 39         int irq;
 40 
 41         /* Count the MEM and IRQ resources. */
 42         for (num_windows = 0;; num_windows++) {
 43                 res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
 44                 if (!res)
 45                         break;
 46         }
 47         for (num_irqs = 0;; num_irqs++) {
 48                 irq = platform_get_irq(pdev, num_irqs);
 49                 if (irq == -EPROBE_DEFER)
 50                         return irq;
 51                 if (irq < 0)
 52                         break;
 53         }
 54 
 55         if (num_windows == 0)
 56                 return -EINVAL;
 57 
 58         /* Allocate memory windows and IRQs arrays. */
 59         windows = devm_kzalloc(pfc->dev, num_windows * sizeof(*windows),
 60                                GFP_KERNEL);
 61         if (windows == NULL)
 62                 return -ENOMEM;
 63 
 64         pfc->num_windows = num_windows;
 65         pfc->windows = windows;
 66 
 67         if (num_irqs) {
 68                 irqs = devm_kzalloc(pfc->dev, num_irqs * sizeof(*irqs),
 69                                     GFP_KERNEL);
 70                 if (irqs == NULL)
 71                         return -ENOMEM;
 72 
 73                 pfc->num_irqs = num_irqs;
 74                 pfc->irqs = irqs;
 75         }
 76 
 77         /* Fill them. */
 78         for (i = 0; i < num_windows; i++) {
 79                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
 80                 windows->phys = res->start;
 81                 windows->size = resource_size(res);
 82                 windows->virt = devm_ioremap_resource(pfc->dev, res);
 83                 if (IS_ERR(windows->virt))
 84                         return -ENOMEM;
 85                 windows++;
 86         }
 87         for (i = 0; i < num_irqs; i++)
 88                 *irqs++ = platform_get_irq(pdev, i);
 89 
 90         return 0;
 91 }
 92 
 93 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
 94 {
 95         struct sh_pfc_window *window;
 96         phys_addr_t address = reg;
 97         unsigned int i;
 98 
 99         /* scan through physical windows and convert address */
100         for (i = 0; i < pfc->num_windows; i++) {
101                 window = pfc->windows + i;
102 
103                 if (address < window->phys)
104                         continue;
105 
106                 if (address >= (window->phys + window->size))
107                         continue;
108 
109                 return window->virt + (address - window->phys);
110         }
111 
112         BUG();
113         return NULL;
114 }
115 
116 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
117 {
118         unsigned int offset;
119         unsigned int i;
120 
121         for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
122                 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
123 
124                 if (pin <= range->end)
125                         return pin >= range->start
126                              ? offset + pin - range->start : -1;
127 
128                 offset += range->end - range->start + 1;
129         }
130 
131         return -EINVAL;
132 }
133 
134 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
135 {
136         if (enum_id < r->begin)
137                 return 0;
138 
139         if (enum_id > r->end)
140                 return 0;
141 
142         return 1;
143 }
144 
145 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
146 {
147         switch (reg_width) {
148         case 8:
149                 return ioread8(mapped_reg);
150         case 16:
151                 return ioread16(mapped_reg);
152         case 32:
153                 return ioread32(mapped_reg);
154         }
155 
156         BUG();
157         return 0;
158 }
159 
160 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
161                           u32 data)
162 {
163         switch (reg_width) {
164         case 8:
165                 iowrite8(data, mapped_reg);
166                 return;
167         case 16:
168                 iowrite16(data, mapped_reg);
169                 return;
170         case 32:
171                 iowrite32(data, mapped_reg);
172                 return;
173         }
174 
175         BUG();
176 }
177 
178 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
179                                      const struct pinmux_cfg_reg *crp,
180                                      unsigned int in_pos,
181                                      void __iomem **mapped_regp, u32 *maskp,
182                                      unsigned int *posp)
183 {
184         unsigned int k;
185 
186         *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
187 
188         if (crp->field_width) {
189                 *maskp = (1 << crp->field_width) - 1;
190                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
191         } else {
192                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
193                 *posp = crp->reg_width;
194                 for (k = 0; k <= in_pos; k++)
195                         *posp -= crp->var_field_width[k];
196         }
197 }
198 
199 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
200                                     const struct pinmux_cfg_reg *crp,
201                                     unsigned int field, u32 value)
202 {
203         void __iomem *mapped_reg;
204         unsigned int pos;
205         u32 mask, data;
206 
207         sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
208 
209         dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
210                 "r_width = %u, f_width = %u\n",
211                 crp->reg, value, field, crp->reg_width, crp->field_width);
212 
213         mask = ~(mask << pos);
214         value = value << pos;
215 
216         data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
217         data &= mask;
218         data |= value;
219 
220         if (pfc->info->unlock_reg)
221                 sh_pfc_write_raw_reg(
222                         sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
223                         ~data);
224 
225         sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
226 }
227 
228 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
229                                  const struct pinmux_cfg_reg **crp,
230                                  unsigned int *fieldp, u32 *valuep)
231 {
232         unsigned int k = 0;
233 
234         while (1) {
235                 const struct pinmux_cfg_reg *config_reg =
236                         pfc->info->cfg_regs + k;
237                 unsigned int r_width = config_reg->reg_width;
238                 unsigned int f_width = config_reg->field_width;
239                 unsigned int curr_width;
240                 unsigned int bit_pos;
241                 unsigned int pos = 0;
242                 unsigned int m = 0;
243 
244                 if (!r_width)
245                         break;
246 
247                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
248                         u32 ncomb;
249                         u32 n;
250 
251                         if (f_width)
252                                 curr_width = f_width;
253                         else
254                                 curr_width = config_reg->var_field_width[m];
255 
256                         ncomb = 1 << curr_width;
257                         for (n = 0; n < ncomb; n++) {
258                                 if (config_reg->enum_ids[pos + n] == enum_id) {
259                                         *crp = config_reg;
260                                         *fieldp = m;
261                                         *valuep = n;
262                                         return 0;
263                                 }
264                         }
265                         pos += ncomb;
266                         m++;
267                 }
268                 k++;
269         }
270 
271         return -EINVAL;
272 }
273 
274 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
275                               u16 *enum_idp)
276 {
277         const u16 *data = pfc->info->pinmux_data;
278         unsigned int k;
279 
280         if (pos) {
281                 *enum_idp = data[pos + 1];
282                 return pos + 1;
283         }
284 
285         for (k = 0; k < pfc->info->pinmux_data_size; k++) {
286                 if (data[k] == mark) {
287                         *enum_idp = data[k + 1];
288                         return k + 1;
289                 }
290         }
291 
292         dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
293                 mark);
294         return -EINVAL;
295 }
296 
297 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
298 {
299         const struct pinmux_range *range;
300         int pos = 0;
301 
302         switch (pinmux_type) {
303         case PINMUX_TYPE_GPIO:
304         case PINMUX_TYPE_FUNCTION:
305                 range = NULL;
306                 break;
307 
308         case PINMUX_TYPE_OUTPUT:
309                 range = &pfc->info->output;
310                 break;
311 
312         case PINMUX_TYPE_INPUT:
313                 range = &pfc->info->input;
314                 break;
315 
316         default:
317                 return -EINVAL;
318         }
319 
320         /* Iterate over all the configuration fields we need to update. */
321         while (1) {
322                 const struct pinmux_cfg_reg *cr;
323                 unsigned int field;
324                 u16 enum_id;
325                 u32 value;
326                 int in_range;
327                 int ret;
328 
329                 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
330                 if (pos < 0)
331                         return pos;
332 
333                 if (!enum_id)
334                         break;
335 
336                 /* Check if the configuration field selects a function. If it
337                  * doesn't, skip the field if it's not applicable to the
338                  * requested pinmux type.
339                  */
340                 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
341                 if (!in_range) {
342                         if (pinmux_type == PINMUX_TYPE_FUNCTION) {
343                                 /* Functions are allowed to modify all
344                                  * fields.
345                                  */
346                                 in_range = 1;
347                         } else if (pinmux_type != PINMUX_TYPE_GPIO) {
348                                 /* Input/output types can only modify fields
349                                  * that correspond to their respective ranges.
350                                  */
351                                 in_range = sh_pfc_enum_in_range(enum_id, range);
352 
353                                 /*
354                                  * special case pass through for fixed
355                                  * input-only or output-only pins without
356                                  * function enum register association.
357                                  */
358                                 if (in_range && enum_id == range->force)
359                                         continue;
360                         }
361                         /* GPIOs are only allowed to modify function fields. */
362                 }
363 
364                 if (!in_range)
365                         continue;
366 
367                 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
368                 if (ret < 0)
369                         return ret;
370 
371                 sh_pfc_write_config_reg(pfc, cr, field, value);
372         }
373 
374         return 0;
375 }
376 
377 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
378 {
379         struct sh_pfc_pin_range *range;
380         unsigned int nr_ranges;
381         unsigned int i;
382 
383         if (pfc->info->pins[0].pin == (u16)-1) {
384                 /* Pin number -1 denotes that the SoC doesn't report pin numbers
385                  * in its pin arrays yet. Consider the pin numbers range as
386                  * continuous and allocate a single range.
387                  */
388                 pfc->nr_ranges = 1;
389                 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
390                                            GFP_KERNEL);
391                 if (pfc->ranges == NULL)
392                         return -ENOMEM;
393 
394                 pfc->ranges->start = 0;
395                 pfc->ranges->end = pfc->info->nr_pins - 1;
396                 pfc->nr_gpio_pins = pfc->info->nr_pins;
397 
398                 return 0;
399         }
400 
401         /* Count, allocate and fill the ranges. The PFC SoC data pins array must
402          * be sorted by pin numbers, and pins without a GPIO port must come
403          * last.
404          */
405         for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
406                 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
407                         nr_ranges++;
408         }
409 
410         pfc->nr_ranges = nr_ranges;
411         pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges) * nr_ranges,
412                                    GFP_KERNEL);
413         if (pfc->ranges == NULL)
414                 return -ENOMEM;
415 
416         range = pfc->ranges;
417         range->start = pfc->info->pins[0].pin;
418 
419         for (i = 1; i < pfc->info->nr_pins; ++i) {
420                 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
421                         continue;
422 
423                 range->end = pfc->info->pins[i-1].pin;
424                 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
425                         pfc->nr_gpio_pins = range->end + 1;
426 
427                 range++;
428                 range->start = pfc->info->pins[i].pin;
429         }
430 
431         range->end = pfc->info->pins[i-1].pin;
432         if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
433                 pfc->nr_gpio_pins = range->end + 1;
434 
435         return 0;
436 }
437 
438 #ifdef CONFIG_OF
439 static const struct of_device_id sh_pfc_of_table[] = {
440 #ifdef CONFIG_PINCTRL_PFC_EMEV2
441         {
442                 .compatible = "renesas,pfc-emev2",
443                 .data = &emev2_pinmux_info,
444         },
445 #endif
446 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
447         {
448                 .compatible = "renesas,pfc-r8a73a4",
449                 .data = &r8a73a4_pinmux_info,
450         },
451 #endif
452 #ifdef CONFIG_PINCTRL_PFC_R8A7740
453         {
454                 .compatible = "renesas,pfc-r8a7740",
455                 .data = &r8a7740_pinmux_info,
456         },
457 #endif
458 #ifdef CONFIG_PINCTRL_PFC_R8A7778
459         {
460                 .compatible = "renesas,pfc-r8a7778",
461                 .data = &r8a7778_pinmux_info,
462         },
463 #endif
464 #ifdef CONFIG_PINCTRL_PFC_R8A7779
465         {
466                 .compatible = "renesas,pfc-r8a7779",
467                 .data = &r8a7779_pinmux_info,
468         },
469 #endif
470 #ifdef CONFIG_PINCTRL_PFC_R8A7790
471         {
472                 .compatible = "renesas,pfc-r8a7790",
473                 .data = &r8a7790_pinmux_info,
474         },
475 #endif
476 #ifdef CONFIG_PINCTRL_PFC_R8A7791
477         {
478                 .compatible = "renesas,pfc-r8a7791",
479                 .data = &r8a7791_pinmux_info,
480         },
481 #endif
482 #ifdef CONFIG_PINCTRL_PFC_R8A7793
483         {
484                 .compatible = "renesas,pfc-r8a7793",
485                 .data = &r8a7793_pinmux_info,
486         },
487 #endif
488 #ifdef CONFIG_PINCTRL_PFC_R8A7794
489         {
490                 .compatible = "renesas,pfc-r8a7794",
491                 .data = &r8a7794_pinmux_info,
492         },
493 #endif
494 #ifdef CONFIG_PINCTRL_PFC_R8A7795
495         {
496                 .compatible = "renesas,pfc-r8a7795",
497                 .data = &r8a7795_pinmux_info,
498         },
499 #endif
500 #ifdef CONFIG_PINCTRL_PFC_SH73A0
501         {
502                 .compatible = "renesas,pfc-sh73a0",
503                 .data = &sh73a0_pinmux_info,
504         },
505 #endif
506         { },
507 };
508 #endif
509 
510 static int sh_pfc_probe(struct platform_device *pdev)
511 {
512         const struct platform_device_id *platid = platform_get_device_id(pdev);
513 #ifdef CONFIG_OF
514         struct device_node *np = pdev->dev.of_node;
515 #endif
516         const struct sh_pfc_soc_info *info;
517         struct sh_pfc *pfc;
518         int ret;
519 
520 #ifdef CONFIG_OF
521         if (np)
522                 info = of_device_get_match_data(&pdev->dev);
523         else
524 #endif
525                 info = platid ? (const void *)platid->driver_data : NULL;
526 
527         if (info == NULL)
528                 return -ENODEV;
529 
530         pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
531         if (pfc == NULL)
532                 return -ENOMEM;
533 
534         pfc->info = info;
535         pfc->dev = &pdev->dev;
536 
537         ret = sh_pfc_map_resources(pfc, pdev);
538         if (unlikely(ret < 0))
539                 return ret;
540 
541         spin_lock_init(&pfc->lock);
542 
543         if (info->ops && info->ops->init) {
544                 ret = info->ops->init(pfc);
545                 if (ret < 0)
546                         return ret;
547         }
548 
549         /* Enable dummy states for those platforms without pinctrl support */
550         if (!of_have_populated_dt())
551                 pinctrl_provide_dummies();
552 
553         ret = sh_pfc_init_ranges(pfc);
554         if (ret < 0)
555                 return ret;
556 
557         /*
558          * Initialize pinctrl bindings first
559          */
560         ret = sh_pfc_register_pinctrl(pfc);
561         if (unlikely(ret != 0))
562                 return ret;
563 
564 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
565         /*
566          * Then the GPIO chip
567          */
568         ret = sh_pfc_register_gpiochip(pfc);
569         if (unlikely(ret != 0)) {
570                 /*
571                  * If the GPIO chip fails to come up we still leave the
572                  * PFC state as it is, given that there are already
573                  * extant users of it that have succeeded by this point.
574                  */
575                 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
576         }
577 #endif
578 
579         platform_set_drvdata(pdev, pfc);
580 
581         dev_info(pfc->dev, "%s support registered\n", info->name);
582 
583         return 0;
584 }
585 
586 static int sh_pfc_remove(struct platform_device *pdev)
587 {
588         struct sh_pfc *pfc = platform_get_drvdata(pdev);
589 
590 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
591         sh_pfc_unregister_gpiochip(pfc);
592 #endif
593         sh_pfc_unregister_pinctrl(pfc);
594 
595         return 0;
596 }
597 
598 static const struct platform_device_id sh_pfc_id_table[] = {
599 #ifdef CONFIG_PINCTRL_PFC_SH7203
600         { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
601 #endif
602 #ifdef CONFIG_PINCTRL_PFC_SH7264
603         { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
604 #endif
605 #ifdef CONFIG_PINCTRL_PFC_SH7269
606         { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
607 #endif
608 #ifdef CONFIG_PINCTRL_PFC_SH7720
609         { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
610 #endif
611 #ifdef CONFIG_PINCTRL_PFC_SH7722
612         { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
613 #endif
614 #ifdef CONFIG_PINCTRL_PFC_SH7723
615         { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
616 #endif
617 #ifdef CONFIG_PINCTRL_PFC_SH7724
618         { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
619 #endif
620 #ifdef CONFIG_PINCTRL_PFC_SH7734
621         { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
622 #endif
623 #ifdef CONFIG_PINCTRL_PFC_SH7757
624         { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
625 #endif
626 #ifdef CONFIG_PINCTRL_PFC_SH7785
627         { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
628 #endif
629 #ifdef CONFIG_PINCTRL_PFC_SH7786
630         { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
631 #endif
632 #ifdef CONFIG_PINCTRL_PFC_SHX3
633         { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
634 #endif
635         { "sh-pfc", 0 },
636         { },
637 };
638 
639 static struct platform_driver sh_pfc_driver = {
640         .probe          = sh_pfc_probe,
641         .remove         = sh_pfc_remove,
642         .id_table       = sh_pfc_id_table,
643         .driver         = {
644                 .name   = DRV_NAME,
645                 .of_match_table = of_match_ptr(sh_pfc_of_table),
646         },
647 };
648 
649 static int __init sh_pfc_init(void)
650 {
651         return platform_driver_register(&sh_pfc_driver);
652 }
653 postcore_initcall(sh_pfc_init);
654 

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