Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/pinctrl/pinctrl-tegra.c

  1 /*
  2  * Driver for the NVIDIA Tegra pinmux
  3  *
  4  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
  5  *
  6  * Derived from code:
  7  * Copyright (C) 2010 Google, Inc.
  8  * Copyright (C) 2010 NVIDIA Corporation
  9  * Copyright (C) 2009-2011 ST-Ericsson AB
 10  *
 11  * This program is free software; you can redistribute it and/or modify it
 12  * under the terms and conditions of the GNU General Public License,
 13  * version 2, as published by the Free Software Foundation.
 14  *
 15  * This program is distributed in the hope it will be useful, but WITHOUT
 16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 17  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 18  * more details.
 19  */
 20 
 21 #include <linux/err.h>
 22 #include <linux/init.h>
 23 #include <linux/io.h>
 24 #include <linux/module.h>
 25 #include <linux/of.h>
 26 #include <linux/platform_device.h>
 27 #include <linux/pinctrl/machine.h>
 28 #include <linux/pinctrl/pinctrl.h>
 29 #include <linux/pinctrl/pinmux.h>
 30 #include <linux/pinctrl/pinconf.h>
 31 #include <linux/slab.h>
 32 
 33 #include "core.h"
 34 #include "pinctrl-tegra.h"
 35 #include "pinctrl-utils.h"
 36 
 37 struct tegra_pmx {
 38         struct device *dev;
 39         struct pinctrl_dev *pctl;
 40 
 41         const struct tegra_pinctrl_soc_data *soc;
 42         const char **group_pins;
 43 
 44         int nbanks;
 45         void __iomem **regs;
 46 };
 47 
 48 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
 49 {
 50         return readl(pmx->regs[bank] + reg);
 51 }
 52 
 53 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
 54 {
 55         writel(val, pmx->regs[bank] + reg);
 56 }
 57 
 58 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
 59 {
 60         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 61 
 62         return pmx->soc->ngroups;
 63 }
 64 
 65 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
 66                                                 unsigned group)
 67 {
 68         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 69 
 70         return pmx->soc->groups[group].name;
 71 }
 72 
 73 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
 74                                         unsigned group,
 75                                         const unsigned **pins,
 76                                         unsigned *num_pins)
 77 {
 78         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 79 
 80         *pins = pmx->soc->groups[group].pins;
 81         *num_pins = pmx->soc->groups[group].npins;
 82 
 83         return 0;
 84 }
 85 
 86 #ifdef CONFIG_DEBUG_FS
 87 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
 88                                        struct seq_file *s,
 89                                        unsigned offset)
 90 {
 91         seq_printf(s, " %s", dev_name(pctldev->dev));
 92 }
 93 #endif
 94 
 95 static const struct cfg_param {
 96         const char *property;
 97         enum tegra_pinconf_param param;
 98 } cfg_params[] = {
 99         {"nvidia,pull",                 TEGRA_PINCONF_PARAM_PULL},
100         {"nvidia,tristate",             TEGRA_PINCONF_PARAM_TRISTATE},
101         {"nvidia,enable-input",         TEGRA_PINCONF_PARAM_ENABLE_INPUT},
102         {"nvidia,open-drain",           TEGRA_PINCONF_PARAM_OPEN_DRAIN},
103         {"nvidia,lock",                 TEGRA_PINCONF_PARAM_LOCK},
104         {"nvidia,io-reset",             TEGRA_PINCONF_PARAM_IORESET},
105         {"nvidia,rcv-sel",              TEGRA_PINCONF_PARAM_RCV_SEL},
106         {"nvidia,high-speed-mode",      TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
107         {"nvidia,schmitt",              TEGRA_PINCONF_PARAM_SCHMITT},
108         {"nvidia,low-power-mode",       TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
109         {"nvidia,pull-down-strength",   TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
110         {"nvidia,pull-up-strength",     TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
111         {"nvidia,slew-rate-falling",    TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
112         {"nvidia,slew-rate-rising",     TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
113         {"nvidia,drive-type",           TEGRA_PINCONF_PARAM_DRIVE_TYPE},
114 };
115 
116 static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
117                                            struct device_node *np,
118                                            struct pinctrl_map **map,
119                                            unsigned *reserved_maps,
120                                            unsigned *num_maps)
121 {
122         struct device *dev = pctldev->dev;
123         int ret, i;
124         const char *function;
125         u32 val;
126         unsigned long config;
127         unsigned long *configs = NULL;
128         unsigned num_configs = 0;
129         unsigned reserve;
130         struct property *prop;
131         const char *group;
132 
133         ret = of_property_read_string(np, "nvidia,function", &function);
134         if (ret < 0) {
135                 /* EINVAL=missing, which is fine since it's optional */
136                 if (ret != -EINVAL)
137                         dev_err(dev,
138                                 "could not parse property nvidia,function\n");
139                 function = NULL;
140         }
141 
142         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
143                 ret = of_property_read_u32(np, cfg_params[i].property, &val);
144                 if (!ret) {
145                         config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
146                         ret = pinctrl_utils_add_config(pctldev, &configs,
147                                         &num_configs, config);
148                         if (ret < 0)
149                                 goto exit;
150                 /* EINVAL=missing, which is fine since it's optional */
151                 } else if (ret != -EINVAL) {
152                         dev_err(dev, "could not parse property %s\n",
153                                 cfg_params[i].property);
154                 }
155         }
156 
157         reserve = 0;
158         if (function != NULL)
159                 reserve++;
160         if (num_configs)
161                 reserve++;
162         ret = of_property_count_strings(np, "nvidia,pins");
163         if (ret < 0) {
164                 dev_err(dev, "could not parse property nvidia,pins\n");
165                 goto exit;
166         }
167         reserve *= ret;
168 
169         ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
170                                         num_maps, reserve);
171         if (ret < 0)
172                 goto exit;
173 
174         of_property_for_each_string(np, "nvidia,pins", prop, group) {
175                 if (function) {
176                         ret = pinctrl_utils_add_map_mux(pctldev, map,
177                                         reserved_maps, num_maps, group,
178                                         function);
179                         if (ret < 0)
180                                 goto exit;
181                 }
182 
183                 if (num_configs) {
184                         ret = pinctrl_utils_add_map_configs(pctldev, map,
185                                         reserved_maps, num_maps, group,
186                                         configs, num_configs,
187                                         PIN_MAP_TYPE_CONFIGS_GROUP);
188                         if (ret < 0)
189                                 goto exit;
190                 }
191         }
192 
193         ret = 0;
194 
195 exit:
196         kfree(configs);
197         return ret;
198 }
199 
200 static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
201                                         struct device_node *np_config,
202                                         struct pinctrl_map **map,
203                                         unsigned *num_maps)
204 {
205         unsigned reserved_maps;
206         struct device_node *np;
207         int ret;
208 
209         reserved_maps = 0;
210         *map = NULL;
211         *num_maps = 0;
212 
213         for_each_child_of_node(np_config, np) {
214                 ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
215                                                       &reserved_maps, num_maps);
216                 if (ret < 0) {
217                         pinctrl_utils_dt_free_map(pctldev, *map,
218                                 *num_maps);
219                         return ret;
220                 }
221         }
222 
223         return 0;
224 }
225 
226 static const struct pinctrl_ops tegra_pinctrl_ops = {
227         .get_groups_count = tegra_pinctrl_get_groups_count,
228         .get_group_name = tegra_pinctrl_get_group_name,
229         .get_group_pins = tegra_pinctrl_get_group_pins,
230 #ifdef CONFIG_DEBUG_FS
231         .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
232 #endif
233         .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
234         .dt_free_map = pinctrl_utils_dt_free_map,
235 };
236 
237 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
238 {
239         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
240 
241         return pmx->soc->nfunctions;
242 }
243 
244 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
245                                                unsigned function)
246 {
247         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
248 
249         return pmx->soc->functions[function].name;
250 }
251 
252 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
253                                          unsigned function,
254                                          const char * const **groups,
255                                          unsigned * const num_groups)
256 {
257         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
258 
259         *groups = pmx->soc->functions[function].groups;
260         *num_groups = pmx->soc->functions[function].ngroups;
261 
262         return 0;
263 }
264 
265 static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
266                                unsigned group)
267 {
268         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
269         const struct tegra_pingroup *g;
270         int i;
271         u32 val;
272 
273         g = &pmx->soc->groups[group];
274 
275         if (WARN_ON(g->mux_reg < 0))
276                 return -EINVAL;
277 
278         for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
279                 if (g->funcs[i] == function)
280                         break;
281         }
282         if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
283                 return -EINVAL;
284 
285         val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
286         val &= ~(0x3 << g->mux_bit);
287         val |= i << g->mux_bit;
288         pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
289 
290         return 0;
291 }
292 
293 static const struct pinmux_ops tegra_pinmux_ops = {
294         .get_functions_count = tegra_pinctrl_get_funcs_count,
295         .get_function_name = tegra_pinctrl_get_func_name,
296         .get_function_groups = tegra_pinctrl_get_func_groups,
297         .enable = tegra_pinctrl_enable,
298 };
299 
300 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
301                              const struct tegra_pingroup *g,
302                              enum tegra_pinconf_param param,
303                              bool report_err,
304                              s8 *bank, s16 *reg, s8 *bit, s8 *width)
305 {
306         switch (param) {
307         case TEGRA_PINCONF_PARAM_PULL:
308                 *bank = g->pupd_bank;
309                 *reg = g->pupd_reg;
310                 *bit = g->pupd_bit;
311                 *width = 2;
312                 break;
313         case TEGRA_PINCONF_PARAM_TRISTATE:
314                 *bank = g->tri_bank;
315                 *reg = g->tri_reg;
316                 *bit = g->tri_bit;
317                 *width = 1;
318                 break;
319         case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
320                 *bank = g->mux_bank;
321                 *reg = g->mux_reg;
322                 *bit = g->einput_bit;
323                 *width = 1;
324                 break;
325         case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
326                 *bank = g->mux_bank;
327                 *reg = g->mux_reg;
328                 *bit = g->odrain_bit;
329                 *width = 1;
330                 break;
331         case TEGRA_PINCONF_PARAM_LOCK:
332                 *bank = g->mux_bank;
333                 *reg = g->mux_reg;
334                 *bit = g->lock_bit;
335                 *width = 1;
336                 break;
337         case TEGRA_PINCONF_PARAM_IORESET:
338                 *bank = g->mux_bank;
339                 *reg = g->mux_reg;
340                 *bit = g->ioreset_bit;
341                 *width = 1;
342                 break;
343         case TEGRA_PINCONF_PARAM_RCV_SEL:
344                 *bank = g->mux_bank;
345                 *reg = g->mux_reg;
346                 *bit = g->rcv_sel_bit;
347                 *width = 1;
348                 break;
349         case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
350                 *bank = g->drv_bank;
351                 *reg = g->drv_reg;
352                 *bit = g->hsm_bit;
353                 *width = 1;
354                 break;
355         case TEGRA_PINCONF_PARAM_SCHMITT:
356                 *bank = g->drv_bank;
357                 *reg = g->drv_reg;
358                 *bit = g->schmitt_bit;
359                 *width = 1;
360                 break;
361         case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
362                 *bank = g->drv_bank;
363                 *reg = g->drv_reg;
364                 *bit = g->lpmd_bit;
365                 *width = 2;
366                 break;
367         case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
368                 *bank = g->drv_bank;
369                 *reg = g->drv_reg;
370                 *bit = g->drvdn_bit;
371                 *width = g->drvdn_width;
372                 break;
373         case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
374                 *bank = g->drv_bank;
375                 *reg = g->drv_reg;
376                 *bit = g->drvup_bit;
377                 *width = g->drvup_width;
378                 break;
379         case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
380                 *bank = g->drv_bank;
381                 *reg = g->drv_reg;
382                 *bit = g->slwf_bit;
383                 *width = g->slwf_width;
384                 break;
385         case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
386                 *bank = g->drv_bank;
387                 *reg = g->drv_reg;
388                 *bit = g->slwr_bit;
389                 *width = g->slwr_width;
390                 break;
391         case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
392                 *bank = g->drv_bank;
393                 *reg = g->drv_reg;
394                 *bit = g->drvtype_bit;
395                 *width = 2;
396                 break;
397         default:
398                 dev_err(pmx->dev, "Invalid config param %04x\n", param);
399                 return -ENOTSUPP;
400         }
401 
402         if (*reg < 0 || *bit > 31) {
403                 if (report_err) {
404                         const char *prop = "unknown";
405                         int i;
406 
407                         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
408                                 if (cfg_params[i].param == param) {
409                                         prop = cfg_params[i].property;
410                                         break;
411                                 }
412                         }
413 
414                         dev_err(pmx->dev,
415                                 "Config param %04x (%s) not supported on group %s\n",
416                                 param, prop, g->name);
417                 }
418                 return -ENOTSUPP;
419         }
420 
421         return 0;
422 }
423 
424 static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
425                              unsigned pin, unsigned long *config)
426 {
427         dev_err(pctldev->dev, "pin_config_get op not supported\n");
428         return -ENOTSUPP;
429 }
430 
431 static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
432                              unsigned pin, unsigned long *configs,
433                              unsigned num_configs)
434 {
435         dev_err(pctldev->dev, "pin_config_set op not supported\n");
436         return -ENOTSUPP;
437 }
438 
439 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
440                                    unsigned group, unsigned long *config)
441 {
442         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
443         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
444         u16 arg;
445         const struct tegra_pingroup *g;
446         int ret;
447         s8 bank, bit, width;
448         s16 reg;
449         u32 val, mask;
450 
451         g = &pmx->soc->groups[group];
452 
453         ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
454                                 &width);
455         if (ret < 0)
456                 return ret;
457 
458         val = pmx_readl(pmx, bank, reg);
459         mask = (1 << width) - 1;
460         arg = (val >> bit) & mask;
461 
462         *config = TEGRA_PINCONF_PACK(param, arg);
463 
464         return 0;
465 }
466 
467 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
468                                    unsigned group, unsigned long *configs,
469                                    unsigned num_configs)
470 {
471         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
472         enum tegra_pinconf_param param;
473         u16 arg;
474         const struct tegra_pingroup *g;
475         int ret, i;
476         s8 bank, bit, width;
477         s16 reg;
478         u32 val, mask;
479 
480         g = &pmx->soc->groups[group];
481 
482         for (i = 0; i < num_configs; i++) {
483                 param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]);
484                 arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]);
485 
486                 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
487                                         &width);
488                 if (ret < 0)
489                         return ret;
490 
491                 val = pmx_readl(pmx, bank, reg);
492 
493                 /* LOCK can't be cleared */
494                 if (param == TEGRA_PINCONF_PARAM_LOCK) {
495                         if ((val & BIT(bit)) && !arg) {
496                                 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
497                                 return -EINVAL;
498                         }
499                 }
500 
501                 /* Special-case Boolean values; allow any non-zero as true */
502                 if (width == 1)
503                         arg = !!arg;
504 
505                 /* Range-check user-supplied value */
506                 mask = (1 << width) - 1;
507                 if (arg & ~mask) {
508                         dev_err(pctldev->dev,
509                                 "config %lx: %x too big for %d bit register\n",
510                                 configs[i], arg, width);
511                         return -EINVAL;
512                 }
513 
514                 /* Update register */
515                 val &= ~(mask << bit);
516                 val |= arg << bit;
517                 pmx_writel(pmx, val, bank, reg);
518         } /* for each config */
519 
520         return 0;
521 }
522 
523 #ifdef CONFIG_DEBUG_FS
524 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
525                                    struct seq_file *s, unsigned offset)
526 {
527 }
528 
529 static const char *strip_prefix(const char *s)
530 {
531         const char *comma = strchr(s, ',');
532         if (!comma)
533                 return s;
534 
535         return comma + 1;
536 }
537 
538 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
539                                          struct seq_file *s, unsigned group)
540 {
541         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
542         const struct tegra_pingroup *g;
543         int i, ret;
544         s8 bank, bit, width;
545         s16 reg;
546         u32 val;
547 
548         g = &pmx->soc->groups[group];
549 
550         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
551                 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
552                                         &bank, &reg, &bit, &width);
553                 if (ret < 0)
554                         continue;
555 
556                 val = pmx_readl(pmx, bank, reg);
557                 val >>= bit;
558                 val &= (1 << width) - 1;
559 
560                 seq_printf(s, "\n\t%s=%u",
561                            strip_prefix(cfg_params[i].property), val);
562         }
563 }
564 
565 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
566                                           struct seq_file *s,
567                                           unsigned long config)
568 {
569         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
570         u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
571         const char *pname = "unknown";
572         int i;
573 
574         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
575                 if (cfg_params[i].param == param) {
576                         pname = cfg_params[i].property;
577                         break;
578                 }
579         }
580 
581         seq_printf(s, "%s=%d", strip_prefix(pname), arg);
582 }
583 #endif
584 
585 static const struct pinconf_ops tegra_pinconf_ops = {
586         .pin_config_get = tegra_pinconf_get,
587         .pin_config_set = tegra_pinconf_set,
588         .pin_config_group_get = tegra_pinconf_group_get,
589         .pin_config_group_set = tegra_pinconf_group_set,
590 #ifdef CONFIG_DEBUG_FS
591         .pin_config_dbg_show = tegra_pinconf_dbg_show,
592         .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
593         .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
594 #endif
595 };
596 
597 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
598         .name = "Tegra GPIOs",
599         .id = 0,
600         .base = 0,
601 };
602 
603 static struct pinctrl_desc tegra_pinctrl_desc = {
604         .pctlops = &tegra_pinctrl_ops,
605         .pmxops = &tegra_pinmux_ops,
606         .confops = &tegra_pinconf_ops,
607         .owner = THIS_MODULE,
608 };
609 
610 int tegra_pinctrl_probe(struct platform_device *pdev,
611                         const struct tegra_pinctrl_soc_data *soc_data)
612 {
613         struct tegra_pmx *pmx;
614         struct resource *res;
615         int i;
616         const char **group_pins;
617         int fn, gn, gfn;
618 
619         pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
620         if (!pmx) {
621                 dev_err(&pdev->dev, "Can't alloc tegra_pmx\n");
622                 return -ENOMEM;
623         }
624         pmx->dev = &pdev->dev;
625         pmx->soc = soc_data;
626 
627         /*
628          * Each mux group will appear in 4 functions' list of groups.
629          * This over-allocates slightly, since not all groups are mux groups.
630          */
631         pmx->group_pins = devm_kzalloc(&pdev->dev,
632                 soc_data->ngroups * 4 * sizeof(*pmx->group_pins),
633                 GFP_KERNEL);
634         if (!pmx->group_pins)
635                 return -ENOMEM;
636 
637         group_pins = pmx->group_pins;
638         for (fn = 0; fn < soc_data->nfunctions; fn++) {
639                 struct tegra_function *func = &soc_data->functions[fn];
640 
641                 func->groups = group_pins;
642 
643                 for (gn = 0; gn < soc_data->ngroups; gn++) {
644                         const struct tegra_pingroup *g = &soc_data->groups[gn];
645 
646                         if (g->mux_reg == -1)
647                                 continue;
648 
649                         for (gfn = 0; gfn < 4; gfn++)
650                                 if (g->funcs[gfn] == fn)
651                                         break;
652                         if (gfn == 4)
653                                 continue;
654 
655                         BUG_ON(group_pins - pmx->group_pins >=
656                                 soc_data->ngroups * 4);
657                         *group_pins++ = g->name;
658                         func->ngroups++;
659                 }
660         }
661 
662         tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
663         tegra_pinctrl_desc.name = dev_name(&pdev->dev);
664         tegra_pinctrl_desc.pins = pmx->soc->pins;
665         tegra_pinctrl_desc.npins = pmx->soc->npins;
666 
667         for (i = 0; ; i++) {
668                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
669                 if (!res)
670                         break;
671         }
672         pmx->nbanks = i;
673 
674         pmx->regs = devm_kzalloc(&pdev->dev, pmx->nbanks * sizeof(*pmx->regs),
675                                  GFP_KERNEL);
676         if (!pmx->regs) {
677                 dev_err(&pdev->dev, "Can't alloc regs pointer\n");
678                 return -ENOMEM;
679         }
680 
681         for (i = 0; i < pmx->nbanks; i++) {
682                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
683                 pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);
684                 if (IS_ERR(pmx->regs[i]))
685                         return PTR_ERR(pmx->regs[i]);
686         }
687 
688         pmx->pctl = pinctrl_register(&tegra_pinctrl_desc, &pdev->dev, pmx);
689         if (!pmx->pctl) {
690                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
691                 return -ENODEV;
692         }
693 
694         pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
695 
696         platform_set_drvdata(pdev, pmx);
697 
698         dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
699 
700         return 0;
701 }
702 EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);
703 
704 int tegra_pinctrl_remove(struct platform_device *pdev)
705 {
706         struct tegra_pmx *pmx = platform_get_drvdata(pdev);
707 
708         pinctrl_unregister(pmx->pctl);
709 
710         return 0;
711 }
712 EXPORT_SYMBOL_GPL(tegra_pinctrl_remove);
713 

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