Version:  2.0.40 2.2.26 2.4.37 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15

Linux/drivers/pinctrl/pinctrl-tegra.c

  1 /*
  2  * Driver for the NVIDIA Tegra pinmux
  3  *
  4  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
  5  *
  6  * Derived from code:
  7  * Copyright (C) 2010 Google, Inc.
  8  * Copyright (C) 2010 NVIDIA Corporation
  9  * Copyright (C) 2009-2011 ST-Ericsson AB
 10  *
 11  * This program is free software; you can redistribute it and/or modify it
 12  * under the terms and conditions of the GNU General Public License,
 13  * version 2, as published by the Free Software Foundation.
 14  *
 15  * This program is distributed in the hope it will be useful, but WITHOUT
 16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 17  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 18  * more details.
 19  */
 20 
 21 #include <linux/err.h>
 22 #include <linux/init.h>
 23 #include <linux/io.h>
 24 #include <linux/module.h>
 25 #include <linux/of.h>
 26 #include <linux/platform_device.h>
 27 #include <linux/pinctrl/machine.h>
 28 #include <linux/pinctrl/pinctrl.h>
 29 #include <linux/pinctrl/pinmux.h>
 30 #include <linux/pinctrl/pinconf.h>
 31 #include <linux/slab.h>
 32 
 33 #include "core.h"
 34 #include "pinctrl-tegra.h"
 35 #include "pinctrl-utils.h"
 36 
 37 struct tegra_pmx {
 38         struct device *dev;
 39         struct pinctrl_dev *pctl;
 40 
 41         const struct tegra_pinctrl_soc_data *soc;
 42         const char **group_pins;
 43 
 44         int nbanks;
 45         void __iomem **regs;
 46 };
 47 
 48 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
 49 {
 50         return readl(pmx->regs[bank] + reg);
 51 }
 52 
 53 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
 54 {
 55         writel(val, pmx->regs[bank] + reg);
 56 }
 57 
 58 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
 59 {
 60         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 61 
 62         return pmx->soc->ngroups;
 63 }
 64 
 65 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
 66                                                 unsigned group)
 67 {
 68         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 69 
 70         return pmx->soc->groups[group].name;
 71 }
 72 
 73 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
 74                                         unsigned group,
 75                                         const unsigned **pins,
 76                                         unsigned *num_pins)
 77 {
 78         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 79 
 80         *pins = pmx->soc->groups[group].pins;
 81         *num_pins = pmx->soc->groups[group].npins;
 82 
 83         return 0;
 84 }
 85 
 86 #ifdef CONFIG_DEBUG_FS
 87 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
 88                                        struct seq_file *s,
 89                                        unsigned offset)
 90 {
 91         seq_printf(s, " %s", dev_name(pctldev->dev));
 92 }
 93 #endif
 94 
 95 static const struct cfg_param {
 96         const char *property;
 97         enum tegra_pinconf_param param;
 98 } cfg_params[] = {
 99         {"nvidia,pull",                 TEGRA_PINCONF_PARAM_PULL},
100         {"nvidia,tristate",             TEGRA_PINCONF_PARAM_TRISTATE},
101         {"nvidia,enable-input",         TEGRA_PINCONF_PARAM_ENABLE_INPUT},
102         {"nvidia,open-drain",           TEGRA_PINCONF_PARAM_OPEN_DRAIN},
103         {"nvidia,lock",                 TEGRA_PINCONF_PARAM_LOCK},
104         {"nvidia,io-reset",             TEGRA_PINCONF_PARAM_IORESET},
105         {"nvidia,rcv-sel",              TEGRA_PINCONF_PARAM_RCV_SEL},
106         {"nvidia,high-speed-mode",      TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
107         {"nvidia,schmitt",              TEGRA_PINCONF_PARAM_SCHMITT},
108         {"nvidia,low-power-mode",       TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
109         {"nvidia,pull-down-strength",   TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
110         {"nvidia,pull-up-strength",     TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
111         {"nvidia,slew-rate-falling",    TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
112         {"nvidia,slew-rate-rising",     TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
113         {"nvidia,drive-type",           TEGRA_PINCONF_PARAM_DRIVE_TYPE},
114 };
115 
116 static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
117                                            struct device_node *np,
118                                            struct pinctrl_map **map,
119                                            unsigned *reserved_maps,
120                                            unsigned *num_maps)
121 {
122         struct device *dev = pctldev->dev;
123         int ret, i;
124         const char *function;
125         u32 val;
126         unsigned long config;
127         unsigned long *configs = NULL;
128         unsigned num_configs = 0;
129         unsigned reserve;
130         struct property *prop;
131         const char *group;
132 
133         ret = of_property_read_string(np, "nvidia,function", &function);
134         if (ret < 0) {
135                 /* EINVAL=missing, which is fine since it's optional */
136                 if (ret != -EINVAL)
137                         dev_err(dev,
138                                 "could not parse property nvidia,function\n");
139                 function = NULL;
140         }
141 
142         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
143                 ret = of_property_read_u32(np, cfg_params[i].property, &val);
144                 if (!ret) {
145                         config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
146                         ret = pinctrl_utils_add_config(pctldev, &configs,
147                                         &num_configs, config);
148                         if (ret < 0)
149                                 goto exit;
150                 /* EINVAL=missing, which is fine since it's optional */
151                 } else if (ret != -EINVAL) {
152                         dev_err(dev, "could not parse property %s\n",
153                                 cfg_params[i].property);
154                 }
155         }
156 
157         reserve = 0;
158         if (function != NULL)
159                 reserve++;
160         if (num_configs)
161                 reserve++;
162         ret = of_property_count_strings(np, "nvidia,pins");
163         if (ret < 0) {
164                 dev_err(dev, "could not parse property nvidia,pins\n");
165                 goto exit;
166         }
167         reserve *= ret;
168 
169         ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
170                                         num_maps, reserve);
171         if (ret < 0)
172                 goto exit;
173 
174         of_property_for_each_string(np, "nvidia,pins", prop, group) {
175                 if (function) {
176                         ret = pinctrl_utils_add_map_mux(pctldev, map,
177                                         reserved_maps, num_maps, group,
178                                         function);
179                         if (ret < 0)
180                                 goto exit;
181                 }
182 
183                 if (num_configs) {
184                         ret = pinctrl_utils_add_map_configs(pctldev, map,
185                                         reserved_maps, num_maps, group,
186                                         configs, num_configs,
187                                         PIN_MAP_TYPE_CONFIGS_GROUP);
188                         if (ret < 0)
189                                 goto exit;
190                 }
191         }
192 
193         ret = 0;
194 
195 exit:
196         kfree(configs);
197         return ret;
198 }
199 
200 static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
201                                         struct device_node *np_config,
202                                         struct pinctrl_map **map,
203                                         unsigned *num_maps)
204 {
205         unsigned reserved_maps;
206         struct device_node *np;
207         int ret;
208 
209         reserved_maps = 0;
210         *map = NULL;
211         *num_maps = 0;
212 
213         for_each_child_of_node(np_config, np) {
214                 ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
215                                                       &reserved_maps, num_maps);
216                 if (ret < 0) {
217                         pinctrl_utils_dt_free_map(pctldev, *map,
218                                 *num_maps);
219                         return ret;
220                 }
221         }
222 
223         return 0;
224 }
225 
226 static const struct pinctrl_ops tegra_pinctrl_ops = {
227         .get_groups_count = tegra_pinctrl_get_groups_count,
228         .get_group_name = tegra_pinctrl_get_group_name,
229         .get_group_pins = tegra_pinctrl_get_group_pins,
230 #ifdef CONFIG_DEBUG_FS
231         .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
232 #endif
233         .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
234         .dt_free_map = pinctrl_utils_dt_free_map,
235 };
236 
237 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
238 {
239         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
240 
241         return pmx->soc->nfunctions;
242 }
243 
244 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
245                                                unsigned function)
246 {
247         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
248 
249         return pmx->soc->functions[function].name;
250 }
251 
252 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
253                                          unsigned function,
254                                          const char * const **groups,
255                                          unsigned * const num_groups)
256 {
257         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
258 
259         *groups = pmx->soc->functions[function].groups;
260         *num_groups = pmx->soc->functions[function].ngroups;
261 
262         return 0;
263 }
264 
265 static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
266                                unsigned group)
267 {
268         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
269         const struct tegra_pingroup *g;
270         int i;
271         u32 val;
272 
273         g = &pmx->soc->groups[group];
274 
275         if (WARN_ON(g->mux_reg < 0))
276                 return -EINVAL;
277 
278         for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
279                 if (g->funcs[i] == function)
280                         break;
281         }
282         if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
283                 return -EINVAL;
284 
285         val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
286         val &= ~(0x3 << g->mux_bit);
287         val |= i << g->mux_bit;
288         pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
289 
290         return 0;
291 }
292 
293 static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
294                                   unsigned function, unsigned group)
295 {
296         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
297         const struct tegra_pingroup *g;
298         u32 val;
299 
300         g = &pmx->soc->groups[group];
301 
302         if (WARN_ON(g->mux_reg < 0))
303                 return;
304 
305         val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
306         val &= ~(0x3 << g->mux_bit);
307         val |= g->func_safe << g->mux_bit;
308         pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
309 }
310 
311 static const struct pinmux_ops tegra_pinmux_ops = {
312         .get_functions_count = tegra_pinctrl_get_funcs_count,
313         .get_function_name = tegra_pinctrl_get_func_name,
314         .get_function_groups = tegra_pinctrl_get_func_groups,
315         .enable = tegra_pinctrl_enable,
316         .disable = tegra_pinctrl_disable,
317 };
318 
319 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
320                              const struct tegra_pingroup *g,
321                              enum tegra_pinconf_param param,
322                              bool report_err,
323                              s8 *bank, s16 *reg, s8 *bit, s8 *width)
324 {
325         switch (param) {
326         case TEGRA_PINCONF_PARAM_PULL:
327                 *bank = g->pupd_bank;
328                 *reg = g->pupd_reg;
329                 *bit = g->pupd_bit;
330                 *width = 2;
331                 break;
332         case TEGRA_PINCONF_PARAM_TRISTATE:
333                 *bank = g->tri_bank;
334                 *reg = g->tri_reg;
335                 *bit = g->tri_bit;
336                 *width = 1;
337                 break;
338         case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
339                 *bank = g->einput_bank;
340                 *reg = g->einput_reg;
341                 *bit = g->einput_bit;
342                 *width = 1;
343                 break;
344         case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
345                 *bank = g->odrain_bank;
346                 *reg = g->odrain_reg;
347                 *bit = g->odrain_bit;
348                 *width = 1;
349                 break;
350         case TEGRA_PINCONF_PARAM_LOCK:
351                 *bank = g->lock_bank;
352                 *reg = g->lock_reg;
353                 *bit = g->lock_bit;
354                 *width = 1;
355                 break;
356         case TEGRA_PINCONF_PARAM_IORESET:
357                 *bank = g->ioreset_bank;
358                 *reg = g->ioreset_reg;
359                 *bit = g->ioreset_bit;
360                 *width = 1;
361                 break;
362         case TEGRA_PINCONF_PARAM_RCV_SEL:
363                 *bank = g->rcv_sel_bank;
364                 *reg = g->rcv_sel_reg;
365                 *bit = g->rcv_sel_bit;
366                 *width = 1;
367                 break;
368         case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
369                 *bank = g->drv_bank;
370                 *reg = g->drv_reg;
371                 *bit = g->hsm_bit;
372                 *width = 1;
373                 break;
374         case TEGRA_PINCONF_PARAM_SCHMITT:
375                 *bank = g->drv_bank;
376                 *reg = g->drv_reg;
377                 *bit = g->schmitt_bit;
378                 *width = 1;
379                 break;
380         case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
381                 *bank = g->drv_bank;
382                 *reg = g->drv_reg;
383                 *bit = g->lpmd_bit;
384                 *width = 2;
385                 break;
386         case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
387                 *bank = g->drv_bank;
388                 *reg = g->drv_reg;
389                 *bit = g->drvdn_bit;
390                 *width = g->drvdn_width;
391                 break;
392         case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
393                 *bank = g->drv_bank;
394                 *reg = g->drv_reg;
395                 *bit = g->drvup_bit;
396                 *width = g->drvup_width;
397                 break;
398         case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
399                 *bank = g->drv_bank;
400                 *reg = g->drv_reg;
401                 *bit = g->slwf_bit;
402                 *width = g->slwf_width;
403                 break;
404         case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
405                 *bank = g->drv_bank;
406                 *reg = g->drv_reg;
407                 *bit = g->slwr_bit;
408                 *width = g->slwr_width;
409                 break;
410         case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
411                 *bank = g->drvtype_bank;
412                 *reg = g->drvtype_reg;
413                 *bit = g->drvtype_bit;
414                 *width = 2;
415                 break;
416         default:
417                 dev_err(pmx->dev, "Invalid config param %04x\n", param);
418                 return -ENOTSUPP;
419         }
420 
421         if (*reg < 0) {
422                 if (report_err)
423                         dev_err(pmx->dev,
424                                 "Config param %04x not supported on group %s\n",
425                                 param, g->name);
426                 return -ENOTSUPP;
427         }
428 
429         return 0;
430 }
431 
432 static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
433                              unsigned pin, unsigned long *config)
434 {
435         dev_err(pctldev->dev, "pin_config_get op not supported\n");
436         return -ENOTSUPP;
437 }
438 
439 static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
440                              unsigned pin, unsigned long *configs,
441                              unsigned num_configs)
442 {
443         dev_err(pctldev->dev, "pin_config_set op not supported\n");
444         return -ENOTSUPP;
445 }
446 
447 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
448                                    unsigned group, unsigned long *config)
449 {
450         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
451         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
452         u16 arg;
453         const struct tegra_pingroup *g;
454         int ret;
455         s8 bank, bit, width;
456         s16 reg;
457         u32 val, mask;
458 
459         g = &pmx->soc->groups[group];
460 
461         ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
462                                 &width);
463         if (ret < 0)
464                 return ret;
465 
466         val = pmx_readl(pmx, bank, reg);
467         mask = (1 << width) - 1;
468         arg = (val >> bit) & mask;
469 
470         *config = TEGRA_PINCONF_PACK(param, arg);
471 
472         return 0;
473 }
474 
475 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
476                                    unsigned group, unsigned long *configs,
477                                    unsigned num_configs)
478 {
479         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
480         enum tegra_pinconf_param param;
481         u16 arg;
482         const struct tegra_pingroup *g;
483         int ret, i;
484         s8 bank, bit, width;
485         s16 reg;
486         u32 val, mask;
487 
488         g = &pmx->soc->groups[group];
489 
490         for (i = 0; i < num_configs; i++) {
491                 param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]);
492                 arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]);
493 
494                 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
495                                         &width);
496                 if (ret < 0)
497                         return ret;
498 
499                 val = pmx_readl(pmx, bank, reg);
500 
501                 /* LOCK can't be cleared */
502                 if (param == TEGRA_PINCONF_PARAM_LOCK) {
503                         if ((val & BIT(bit)) && !arg) {
504                                 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
505                                 return -EINVAL;
506                         }
507                 }
508 
509                 /* Special-case Boolean values; allow any non-zero as true */
510                 if (width == 1)
511                         arg = !!arg;
512 
513                 /* Range-check user-supplied value */
514                 mask = (1 << width) - 1;
515                 if (arg & ~mask) {
516                         dev_err(pctldev->dev,
517                                 "config %lx: %x too big for %d bit register\n",
518                                 configs[i], arg, width);
519                         return -EINVAL;
520                 }
521 
522                 /* Update register */
523                 val &= ~(mask << bit);
524                 val |= arg << bit;
525                 pmx_writel(pmx, val, bank, reg);
526         } /* for each config */
527 
528         return 0;
529 }
530 
531 #ifdef CONFIG_DEBUG_FS
532 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
533                                    struct seq_file *s, unsigned offset)
534 {
535 }
536 
537 static const char *strip_prefix(const char *s)
538 {
539         const char *comma = strchr(s, ',');
540         if (!comma)
541                 return s;
542 
543         return comma + 1;
544 }
545 
546 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
547                                          struct seq_file *s, unsigned group)
548 {
549         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
550         const struct tegra_pingroup *g;
551         int i, ret;
552         s8 bank, bit, width;
553         s16 reg;
554         u32 val;
555 
556         g = &pmx->soc->groups[group];
557 
558         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
559                 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
560                                         &bank, &reg, &bit, &width);
561                 if (ret < 0)
562                         continue;
563 
564                 val = pmx_readl(pmx, bank, reg);
565                 val >>= bit;
566                 val &= (1 << width) - 1;
567 
568                 seq_printf(s, "\n\t%s=%u",
569                            strip_prefix(cfg_params[i].property), val);
570         }
571 }
572 
573 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
574                                           struct seq_file *s,
575                                           unsigned long config)
576 {
577         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
578         u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
579         const char *pname = "unknown";
580         int i;
581 
582         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
583                 if (cfg_params[i].param == param) {
584                         pname = cfg_params[i].property;
585                         break;
586                 }
587         }
588 
589         seq_printf(s, "%s=%d", strip_prefix(pname), arg);
590 }
591 #endif
592 
593 static const struct pinconf_ops tegra_pinconf_ops = {
594         .pin_config_get = tegra_pinconf_get,
595         .pin_config_set = tegra_pinconf_set,
596         .pin_config_group_get = tegra_pinconf_group_get,
597         .pin_config_group_set = tegra_pinconf_group_set,
598 #ifdef CONFIG_DEBUG_FS
599         .pin_config_dbg_show = tegra_pinconf_dbg_show,
600         .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
601         .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
602 #endif
603 };
604 
605 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
606         .name = "Tegra GPIOs",
607         .id = 0,
608         .base = 0,
609 };
610 
611 static struct pinctrl_desc tegra_pinctrl_desc = {
612         .pctlops = &tegra_pinctrl_ops,
613         .pmxops = &tegra_pinmux_ops,
614         .confops = &tegra_pinconf_ops,
615         .owner = THIS_MODULE,
616 };
617 
618 int tegra_pinctrl_probe(struct platform_device *pdev,
619                         const struct tegra_pinctrl_soc_data *soc_data)
620 {
621         struct tegra_pmx *pmx;
622         struct resource *res;
623         int i;
624         const char **group_pins;
625         int fn, gn, gfn;
626 
627         pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
628         if (!pmx) {
629                 dev_err(&pdev->dev, "Can't alloc tegra_pmx\n");
630                 return -ENOMEM;
631         }
632         pmx->dev = &pdev->dev;
633         pmx->soc = soc_data;
634 
635         /*
636          * Each mux group will appear in 4 functions' list of groups.
637          * This over-allocates slightly, since not all groups are mux groups.
638          */
639         pmx->group_pins = devm_kzalloc(&pdev->dev,
640                 soc_data->ngroups * 4 * sizeof(*pmx->group_pins),
641                 GFP_KERNEL);
642         if (!pmx->group_pins)
643                 return -ENOMEM;
644 
645         group_pins = pmx->group_pins;
646         for (fn = 0; fn < soc_data->nfunctions; fn++) {
647                 struct tegra_function *func = &soc_data->functions[fn];
648 
649                 func->groups = group_pins;
650 
651                 for (gn = 0; gn < soc_data->ngroups; gn++) {
652                         const struct tegra_pingroup *g = &soc_data->groups[gn];
653 
654                         if (g->mux_reg == -1)
655                                 continue;
656 
657                         for (gfn = 0; gfn < 4; gfn++)
658                                 if (g->funcs[gfn] == fn)
659                                         break;
660                         if (gfn == 4)
661                                 continue;
662 
663                         BUG_ON(group_pins - pmx->group_pins >=
664                                 soc_data->ngroups * 4);
665                         *group_pins++ = g->name;
666                         func->ngroups++;
667                 }
668         }
669 
670         tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
671         tegra_pinctrl_desc.name = dev_name(&pdev->dev);
672         tegra_pinctrl_desc.pins = pmx->soc->pins;
673         tegra_pinctrl_desc.npins = pmx->soc->npins;
674 
675         for (i = 0; ; i++) {
676                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
677                 if (!res)
678                         break;
679         }
680         pmx->nbanks = i;
681 
682         pmx->regs = devm_kzalloc(&pdev->dev, pmx->nbanks * sizeof(*pmx->regs),
683                                  GFP_KERNEL);
684         if (!pmx->regs) {
685                 dev_err(&pdev->dev, "Can't alloc regs pointer\n");
686                 return -ENOMEM;
687         }
688 
689         for (i = 0; i < pmx->nbanks; i++) {
690                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
691                 pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);
692                 if (IS_ERR(pmx->regs[i]))
693                         return PTR_ERR(pmx->regs[i]);
694         }
695 
696         pmx->pctl = pinctrl_register(&tegra_pinctrl_desc, &pdev->dev, pmx);
697         if (!pmx->pctl) {
698                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
699                 return -ENODEV;
700         }
701 
702         pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
703 
704         platform_set_drvdata(pdev, pmx);
705 
706         dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
707 
708         return 0;
709 }
710 EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);
711 
712 int tegra_pinctrl_remove(struct platform_device *pdev)
713 {
714         struct tegra_pmx *pmx = platform_get_drvdata(pdev);
715 
716         pinctrl_unregister(pmx->pctl);
717 
718         return 0;
719 }
720 EXPORT_SYMBOL_GPL(tegra_pinctrl_remove);
721 

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