Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/pinctrl/pinctrl-single.c

  1 /*
  2  * Generic device tree based pinctrl driver for one register per pin
  3  * type pinmux controllers
  4  *
  5  * Copyright (C) 2012 Texas Instruments, Inc.
  6  *
  7  * This file is licensed under the terms of the GNU General Public
  8  * License version 2. This program is licensed "as is" without any
  9  * warranty of any kind, whether express or implied.
 10  */
 11 
 12 #include <linux/init.h>
 13 #include <linux/module.h>
 14 #include <linux/io.h>
 15 #include <linux/slab.h>
 16 #include <linux/err.h>
 17 #include <linux/list.h>
 18 #include <linux/interrupt.h>
 19 
 20 #include <linux/irqchip/chained_irq.h>
 21 
 22 #include <linux/of.h>
 23 #include <linux/of_device.h>
 24 #include <linux/of_address.h>
 25 #include <linux/of_irq.h>
 26 
 27 #include <linux/pinctrl/pinctrl.h>
 28 #include <linux/pinctrl/pinmux.h>
 29 #include <linux/pinctrl/pinconf-generic.h>
 30 
 31 #include <linux/platform_data/pinctrl-single.h>
 32 
 33 #include "core.h"
 34 #include "pinconf.h"
 35 
 36 #define DRIVER_NAME                     "pinctrl-single"
 37 #define PCS_MUX_PINS_NAME               "pinctrl-single,pins"
 38 #define PCS_MUX_BITS_NAME               "pinctrl-single,bits"
 39 #define PCS_REG_NAME_LEN                ((sizeof(unsigned long) * 2) + 3)
 40 #define PCS_OFF_DISABLED                ~0U
 41 
 42 /**
 43  * struct pcs_pingroup - pingroups for a function
 44  * @np:         pingroup device node pointer
 45  * @name:       pingroup name
 46  * @gpins:      array of the pins in the group
 47  * @ngpins:     number of pins in the group
 48  * @node:       list node
 49  */
 50 struct pcs_pingroup {
 51         struct device_node *np;
 52         const char *name;
 53         int *gpins;
 54         int ngpins;
 55         struct list_head node;
 56 };
 57 
 58 /**
 59  * struct pcs_func_vals - mux function register offset and value pair
 60  * @reg:        register virtual address
 61  * @val:        register value
 62  */
 63 struct pcs_func_vals {
 64         void __iomem *reg;
 65         unsigned val;
 66         unsigned mask;
 67 };
 68 
 69 /**
 70  * struct pcs_conf_vals - pinconf parameter, pinconf register offset
 71  * and value, enable, disable, mask
 72  * @param:      config parameter
 73  * @val:        user input bits in the pinconf register
 74  * @enable:     enable bits in the pinconf register
 75  * @disable:    disable bits in the pinconf register
 76  * @mask:       mask bits in the register value
 77  */
 78 struct pcs_conf_vals {
 79         enum pin_config_param param;
 80         unsigned val;
 81         unsigned enable;
 82         unsigned disable;
 83         unsigned mask;
 84 };
 85 
 86 /**
 87  * struct pcs_conf_type - pinconf property name, pinconf param pair
 88  * @name:       property name in DTS file
 89  * @param:      config parameter
 90  */
 91 struct pcs_conf_type {
 92         const char *name;
 93         enum pin_config_param param;
 94 };
 95 
 96 /**
 97  * struct pcs_function - pinctrl function
 98  * @name:       pinctrl function name
 99  * @vals:       register and vals array
100  * @nvals:      number of entries in vals array
101  * @pgnames:    array of pingroup names the function uses
102  * @npgnames:   number of pingroup names the function uses
103  * @node:       list node
104  */
105 struct pcs_function {
106         const char *name;
107         struct pcs_func_vals *vals;
108         unsigned nvals;
109         const char **pgnames;
110         int npgnames;
111         struct pcs_conf_vals *conf;
112         int nconfs;
113         struct list_head node;
114 };
115 
116 /**
117  * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
118  * @offset:     offset base of pins
119  * @npins:      number pins with the same mux value of gpio function
120  * @gpiofunc:   mux value of gpio function
121  * @node:       list node
122  */
123 struct pcs_gpiofunc_range {
124         unsigned offset;
125         unsigned npins;
126         unsigned gpiofunc;
127         struct list_head node;
128 };
129 
130 /**
131  * struct pcs_data - wrapper for data needed by pinctrl framework
132  * @pa:         pindesc array
133  * @cur:        index to current element
134  *
135  * REVISIT: We should be able to drop this eventually by adding
136  * support for registering pins individually in the pinctrl
137  * framework for those drivers that don't need a static array.
138  */
139 struct pcs_data {
140         struct pinctrl_pin_desc *pa;
141         int cur;
142 };
143 
144 /**
145  * struct pcs_name - register name for a pin
146  * @name:       name of the pinctrl register
147  *
148  * REVISIT: We may want to make names optional in the pinctrl
149  * framework as some drivers may not care about pin names to
150  * avoid kernel bloat. The pin names can be deciphered by user
151  * space tools using debugfs based on the register address and
152  * SoC packaging information.
153  */
154 struct pcs_name {
155         char name[PCS_REG_NAME_LEN];
156 };
157 
158 /**
159  * struct pcs_soc_data - SoC specific settings
160  * @flags:      initial SoC specific PCS_FEAT_xxx values
161  * @irq:        optional interrupt for the controller
162  * @irq_enable_mask:    optional SoC specific interrupt enable mask
163  * @irq_status_mask:    optional SoC specific interrupt status mask
164  * @rearm:      optional SoC specific wake-up rearm function
165  */
166 struct pcs_soc_data {
167         unsigned flags;
168         int irq;
169         unsigned irq_enable_mask;
170         unsigned irq_status_mask;
171         void (*rearm)(void);
172 };
173 
174 /**
175  * struct pcs_device - pinctrl device instance
176  * @res:        resources
177  * @base:       virtual address of the controller
178  * @size:       size of the ioremapped area
179  * @dev:        device entry
180  * @pctl:       pin controller device
181  * @flags:      mask of PCS_FEAT_xxx values
182  * @lock:       spinlock for register access
183  * @mutex:      mutex protecting the lists
184  * @width:      bits per mux register
185  * @fmask:      function register mask
186  * @fshift:     function register shift
187  * @foff:       value to turn mux off
188  * @fmax:       max number of functions in fmask
189  * @bits_per_pin:number of bits per pin
190  * @names:      array of register names for pins
191  * @pins:       physical pins on the SoC
192  * @pgtree:     pingroup index radix tree
193  * @ftree:      function index radix tree
194  * @pingroups:  list of pingroups
195  * @functions:  list of functions
196  * @gpiofuncs:  list of gpio functions
197  * @irqs:       list of interrupt registers
198  * @chip:       chip container for this instance
199  * @domain:     IRQ domain for this instance
200  * @ngroups:    number of pingroups
201  * @nfuncs:     number of functions
202  * @desc:       pin controller descriptor
203  * @read:       register read function to use
204  * @write:      register write function to use
205  */
206 struct pcs_device {
207         struct resource *res;
208         void __iomem *base;
209         unsigned size;
210         struct device *dev;
211         struct pinctrl_dev *pctl;
212         unsigned flags;
213 #define PCS_QUIRK_SHARED_IRQ    (1 << 2)
214 #define PCS_FEAT_IRQ            (1 << 1)
215 #define PCS_FEAT_PINCONF        (1 << 0)
216         struct pcs_soc_data socdata;
217         raw_spinlock_t lock;
218         struct mutex mutex;
219         unsigned width;
220         unsigned fmask;
221         unsigned fshift;
222         unsigned foff;
223         unsigned fmax;
224         bool bits_per_mux;
225         unsigned bits_per_pin;
226         struct pcs_name *names;
227         struct pcs_data pins;
228         struct radix_tree_root pgtree;
229         struct radix_tree_root ftree;
230         struct list_head pingroups;
231         struct list_head functions;
232         struct list_head gpiofuncs;
233         struct list_head irqs;
234         struct irq_chip chip;
235         struct irq_domain *domain;
236         unsigned ngroups;
237         unsigned nfuncs;
238         struct pinctrl_desc desc;
239         unsigned (*read)(void __iomem *reg);
240         void (*write)(unsigned val, void __iomem *reg);
241 };
242 
243 #define PCS_QUIRK_HAS_SHARED_IRQ        (pcs->flags & PCS_QUIRK_SHARED_IRQ)
244 #define PCS_HAS_IRQ             (pcs->flags & PCS_FEAT_IRQ)
245 #define PCS_HAS_PINCONF         (pcs->flags & PCS_FEAT_PINCONF)
246 
247 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
248                            unsigned long *config);
249 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
250                            unsigned long *configs, unsigned num_configs);
251 
252 static enum pin_config_param pcs_bias[] = {
253         PIN_CONFIG_BIAS_PULL_DOWN,
254         PIN_CONFIG_BIAS_PULL_UP,
255 };
256 
257 /*
258  * REVISIT: Reads and writes could eventually use regmap or something
259  * generic. But at least on omaps, some mux registers are performance
260  * critical as they may need to be remuxed every time before and after
261  * idle. Adding tests for register access width for every read and
262  * write like regmap is doing is not desired, and caching the registers
263  * does not help in this case.
264  */
265 
266 static unsigned __maybe_unused pcs_readb(void __iomem *reg)
267 {
268         return readb(reg);
269 }
270 
271 static unsigned __maybe_unused pcs_readw(void __iomem *reg)
272 {
273         return readw(reg);
274 }
275 
276 static unsigned __maybe_unused pcs_readl(void __iomem *reg)
277 {
278         return readl(reg);
279 }
280 
281 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
282 {
283         writeb(val, reg);
284 }
285 
286 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
287 {
288         writew(val, reg);
289 }
290 
291 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
292 {
293         writel(val, reg);
294 }
295 
296 static int pcs_get_groups_count(struct pinctrl_dev *pctldev)
297 {
298         struct pcs_device *pcs;
299 
300         pcs = pinctrl_dev_get_drvdata(pctldev);
301 
302         return pcs->ngroups;
303 }
304 
305 static const char *pcs_get_group_name(struct pinctrl_dev *pctldev,
306                                         unsigned gselector)
307 {
308         struct pcs_device *pcs;
309         struct pcs_pingroup *group;
310 
311         pcs = pinctrl_dev_get_drvdata(pctldev);
312         group = radix_tree_lookup(&pcs->pgtree, gselector);
313         if (!group) {
314                 dev_err(pcs->dev, "%s could not find pingroup%i\n",
315                         __func__, gselector);
316                 return NULL;
317         }
318 
319         return group->name;
320 }
321 
322 static int pcs_get_group_pins(struct pinctrl_dev *pctldev,
323                                         unsigned gselector,
324                                         const unsigned **pins,
325                                         unsigned *npins)
326 {
327         struct pcs_device *pcs;
328         struct pcs_pingroup *group;
329 
330         pcs = pinctrl_dev_get_drvdata(pctldev);
331         group = radix_tree_lookup(&pcs->pgtree, gselector);
332         if (!group) {
333                 dev_err(pcs->dev, "%s could not find pingroup%i\n",
334                         __func__, gselector);
335                 return -EINVAL;
336         }
337 
338         *pins = group->gpins;
339         *npins = group->ngpins;
340 
341         return 0;
342 }
343 
344 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
345                                         struct seq_file *s,
346                                         unsigned pin)
347 {
348         struct pcs_device *pcs;
349         unsigned val, mux_bytes;
350 
351         pcs = pinctrl_dev_get_drvdata(pctldev);
352 
353         mux_bytes = pcs->width / BITS_PER_BYTE;
354         val = pcs->read(pcs->base + pin * mux_bytes);
355 
356         seq_printf(s, "%08x %s " , val, DRIVER_NAME);
357 }
358 
359 static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
360                                 struct pinctrl_map *map, unsigned num_maps)
361 {
362         struct pcs_device *pcs;
363 
364         pcs = pinctrl_dev_get_drvdata(pctldev);
365         devm_kfree(pcs->dev, map);
366 }
367 
368 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
369                                 struct device_node *np_config,
370                                 struct pinctrl_map **map, unsigned *num_maps);
371 
372 static const struct pinctrl_ops pcs_pinctrl_ops = {
373         .get_groups_count = pcs_get_groups_count,
374         .get_group_name = pcs_get_group_name,
375         .get_group_pins = pcs_get_group_pins,
376         .pin_dbg_show = pcs_pin_dbg_show,
377         .dt_node_to_map = pcs_dt_node_to_map,
378         .dt_free_map = pcs_dt_free_map,
379 };
380 
381 static int pcs_get_functions_count(struct pinctrl_dev *pctldev)
382 {
383         struct pcs_device *pcs;
384 
385         pcs = pinctrl_dev_get_drvdata(pctldev);
386 
387         return pcs->nfuncs;
388 }
389 
390 static const char *pcs_get_function_name(struct pinctrl_dev *pctldev,
391                                                 unsigned fselector)
392 {
393         struct pcs_device *pcs;
394         struct pcs_function *func;
395 
396         pcs = pinctrl_dev_get_drvdata(pctldev);
397         func = radix_tree_lookup(&pcs->ftree, fselector);
398         if (!func) {
399                 dev_err(pcs->dev, "%s could not find function%i\n",
400                         __func__, fselector);
401                 return NULL;
402         }
403 
404         return func->name;
405 }
406 
407 static int pcs_get_function_groups(struct pinctrl_dev *pctldev,
408                                         unsigned fselector,
409                                         const char * const **groups,
410                                         unsigned * const ngroups)
411 {
412         struct pcs_device *pcs;
413         struct pcs_function *func;
414 
415         pcs = pinctrl_dev_get_drvdata(pctldev);
416         func = radix_tree_lookup(&pcs->ftree, fselector);
417         if (!func) {
418                 dev_err(pcs->dev, "%s could not find function%i\n",
419                         __func__, fselector);
420                 return -EINVAL;
421         }
422         *groups = func->pgnames;
423         *ngroups = func->npgnames;
424 
425         return 0;
426 }
427 
428 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
429                             struct pcs_function **func)
430 {
431         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
432         struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
433         const struct pinctrl_setting_mux *setting;
434         unsigned fselector;
435 
436         /* If pin is not described in DTS & enabled, mux_setting is NULL. */
437         setting = pdesc->mux_setting;
438         if (!setting)
439                 return -ENOTSUPP;
440         fselector = setting->func;
441         *func = radix_tree_lookup(&pcs->ftree, fselector);
442         if (!(*func)) {
443                 dev_err(pcs->dev, "%s could not find function%i\n",
444                         __func__, fselector);
445                 return -ENOTSUPP;
446         }
447         return 0;
448 }
449 
450 static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
451         unsigned group)
452 {
453         struct pcs_device *pcs;
454         struct pcs_function *func;
455         int i;
456 
457         pcs = pinctrl_dev_get_drvdata(pctldev);
458         /* If function mask is null, needn't enable it. */
459         if (!pcs->fmask)
460                 return 0;
461         func = radix_tree_lookup(&pcs->ftree, fselector);
462         if (!func)
463                 return -EINVAL;
464 
465         dev_dbg(pcs->dev, "enabling %s function%i\n",
466                 func->name, fselector);
467 
468         for (i = 0; i < func->nvals; i++) {
469                 struct pcs_func_vals *vals;
470                 unsigned long flags;
471                 unsigned val, mask;
472 
473                 vals = &func->vals[i];
474                 raw_spin_lock_irqsave(&pcs->lock, flags);
475                 val = pcs->read(vals->reg);
476 
477                 if (pcs->bits_per_mux)
478                         mask = vals->mask;
479                 else
480                         mask = pcs->fmask;
481 
482                 val &= ~mask;
483                 val |= (vals->val & mask);
484                 pcs->write(val, vals->reg);
485                 raw_spin_unlock_irqrestore(&pcs->lock, flags);
486         }
487 
488         return 0;
489 }
490 
491 static int pcs_request_gpio(struct pinctrl_dev *pctldev,
492                             struct pinctrl_gpio_range *range, unsigned pin)
493 {
494         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
495         struct pcs_gpiofunc_range *frange = NULL;
496         struct list_head *pos, *tmp;
497         int mux_bytes = 0;
498         unsigned data;
499 
500         /* If function mask is null, return directly. */
501         if (!pcs->fmask)
502                 return -ENOTSUPP;
503 
504         list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
505                 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
506                 if (pin >= frange->offset + frange->npins
507                         || pin < frange->offset)
508                         continue;
509                 mux_bytes = pcs->width / BITS_PER_BYTE;
510                 data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask;
511                 data |= frange->gpiofunc;
512                 pcs->write(data, pcs->base + pin * mux_bytes);
513                 break;
514         }
515         return 0;
516 }
517 
518 static const struct pinmux_ops pcs_pinmux_ops = {
519         .get_functions_count = pcs_get_functions_count,
520         .get_function_name = pcs_get_function_name,
521         .get_function_groups = pcs_get_function_groups,
522         .enable = pcs_enable,
523         .gpio_request_enable = pcs_request_gpio,
524 };
525 
526 /* Clear BIAS value */
527 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
528 {
529         unsigned long config;
530         int i;
531         for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
532                 config = pinconf_to_config_packed(pcs_bias[i], 0);
533                 pcs_pinconf_set(pctldev, pin, &config, 1);
534         }
535 }
536 
537 /*
538  * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
539  * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
540  */
541 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
542 {
543         unsigned long config;
544         int i;
545 
546         for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
547                 config = pinconf_to_config_packed(pcs_bias[i], 0);
548                 if (!pcs_pinconf_get(pctldev, pin, &config))
549                         goto out;
550         }
551         return true;
552 out:
553         return false;
554 }
555 
556 static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
557                                 unsigned pin, unsigned long *config)
558 {
559         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
560         struct pcs_function *func;
561         enum pin_config_param param;
562         unsigned offset = 0, data = 0, i, j, ret;
563 
564         ret = pcs_get_function(pctldev, pin, &func);
565         if (ret)
566                 return ret;
567 
568         for (i = 0; i < func->nconfs; i++) {
569                 param = pinconf_to_config_param(*config);
570                 if (param == PIN_CONFIG_BIAS_DISABLE) {
571                         if (pcs_pinconf_bias_disable(pctldev, pin)) {
572                                 *config = 0;
573                                 return 0;
574                         } else {
575                                 return -ENOTSUPP;
576                         }
577                 } else if (param != func->conf[i].param) {
578                         continue;
579                 }
580 
581                 offset = pin * (pcs->width / BITS_PER_BYTE);
582                 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
583                 switch (func->conf[i].param) {
584                 /* 4 parameters */
585                 case PIN_CONFIG_BIAS_PULL_DOWN:
586                 case PIN_CONFIG_BIAS_PULL_UP:
587                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
588                         if ((data != func->conf[i].enable) ||
589                             (data == func->conf[i].disable))
590                                 return -ENOTSUPP;
591                         *config = 0;
592                         break;
593                 /* 2 parameters */
594                 case PIN_CONFIG_INPUT_SCHMITT:
595                         for (j = 0; j < func->nconfs; j++) {
596                                 switch (func->conf[j].param) {
597                                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
598                                         if (data != func->conf[j].enable)
599                                                 return -ENOTSUPP;
600                                         break;
601                                 default:
602                                         break;
603                                 }
604                         }
605                         *config = data;
606                         break;
607                 case PIN_CONFIG_DRIVE_STRENGTH:
608                 case PIN_CONFIG_SLEW_RATE:
609                 case PIN_CONFIG_LOW_POWER_MODE:
610                 default:
611                         *config = data;
612                         break;
613                 }
614                 return 0;
615         }
616         return -ENOTSUPP;
617 }
618 
619 static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
620                                 unsigned pin, unsigned long *configs,
621                                 unsigned num_configs)
622 {
623         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
624         struct pcs_function *func;
625         unsigned offset = 0, shift = 0, i, data, ret;
626         u16 arg;
627         int j;
628 
629         ret = pcs_get_function(pctldev, pin, &func);
630         if (ret)
631                 return ret;
632 
633         for (j = 0; j < num_configs; j++) {
634                 for (i = 0; i < func->nconfs; i++) {
635                         if (pinconf_to_config_param(configs[j])
636                                 != func->conf[i].param)
637                                 continue;
638 
639                         offset = pin * (pcs->width / BITS_PER_BYTE);
640                         data = pcs->read(pcs->base + offset);
641                         arg = pinconf_to_config_argument(configs[j]);
642                         switch (func->conf[i].param) {
643                         /* 2 parameters */
644                         case PIN_CONFIG_INPUT_SCHMITT:
645                         case PIN_CONFIG_DRIVE_STRENGTH:
646                         case PIN_CONFIG_SLEW_RATE:
647                         case PIN_CONFIG_LOW_POWER_MODE:
648                                 shift = ffs(func->conf[i].mask) - 1;
649                                 data &= ~func->conf[i].mask;
650                                 data |= (arg << shift) & func->conf[i].mask;
651                                 break;
652                         /* 4 parameters */
653                         case PIN_CONFIG_BIAS_DISABLE:
654                                 pcs_pinconf_clear_bias(pctldev, pin);
655                                 break;
656                         case PIN_CONFIG_BIAS_PULL_DOWN:
657                         case PIN_CONFIG_BIAS_PULL_UP:
658                                 if (arg)
659                                         pcs_pinconf_clear_bias(pctldev, pin);
660                                 /* fall through */
661                         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
662                                 data &= ~func->conf[i].mask;
663                                 if (arg)
664                                         data |= func->conf[i].enable;
665                                 else
666                                         data |= func->conf[i].disable;
667                                 break;
668                         default:
669                                 return -ENOTSUPP;
670                         }
671                         pcs->write(data, pcs->base + offset);
672 
673                         break;
674                 }
675                 if (i >= func->nconfs)
676                         return -ENOTSUPP;
677         } /* for each config */
678 
679         return 0;
680 }
681 
682 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
683                                 unsigned group, unsigned long *config)
684 {
685         const unsigned *pins;
686         unsigned npins, old = 0;
687         int i, ret;
688 
689         ret = pcs_get_group_pins(pctldev, group, &pins, &npins);
690         if (ret)
691                 return ret;
692         for (i = 0; i < npins; i++) {
693                 if (pcs_pinconf_get(pctldev, pins[i], config))
694                         return -ENOTSUPP;
695                 /* configs do not match between two pins */
696                 if (i && (old != *config))
697                         return -ENOTSUPP;
698                 old = *config;
699         }
700         return 0;
701 }
702 
703 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
704                                 unsigned group, unsigned long *configs,
705                                 unsigned num_configs)
706 {
707         const unsigned *pins;
708         unsigned npins;
709         int i, ret;
710 
711         ret = pcs_get_group_pins(pctldev, group, &pins, &npins);
712         if (ret)
713                 return ret;
714         for (i = 0; i < npins; i++) {
715                 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
716                         return -ENOTSUPP;
717         }
718         return 0;
719 }
720 
721 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
722                                 struct seq_file *s, unsigned pin)
723 {
724 }
725 
726 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
727                                 struct seq_file *s, unsigned selector)
728 {
729 }
730 
731 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
732                                         struct seq_file *s,
733                                         unsigned long config)
734 {
735         pinconf_generic_dump_config(pctldev, s, config);
736 }
737 
738 static const struct pinconf_ops pcs_pinconf_ops = {
739         .pin_config_get = pcs_pinconf_get,
740         .pin_config_set = pcs_pinconf_set,
741         .pin_config_group_get = pcs_pinconf_group_get,
742         .pin_config_group_set = pcs_pinconf_group_set,
743         .pin_config_dbg_show = pcs_pinconf_dbg_show,
744         .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
745         .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
746         .is_generic = true,
747 };
748 
749 /**
750  * pcs_add_pin() - add a pin to the static per controller pin array
751  * @pcs: pcs driver instance
752  * @offset: register offset from base
753  */
754 static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
755                 unsigned pin_pos)
756 {
757         struct pcs_soc_data *pcs_soc = &pcs->socdata;
758         struct pinctrl_pin_desc *pin;
759         struct pcs_name *pn;
760         int i;
761 
762         i = pcs->pins.cur;
763         if (i >= pcs->desc.npins) {
764                 dev_err(pcs->dev, "too many pins, max %i\n",
765                         pcs->desc.npins);
766                 return -ENOMEM;
767         }
768 
769         if (pcs_soc->irq_enable_mask) {
770                 unsigned val;
771 
772                 val = pcs->read(pcs->base + offset);
773                 if (val & pcs_soc->irq_enable_mask) {
774                         dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
775                                 (unsigned long)pcs->res->start + offset, val);
776                         val &= ~pcs_soc->irq_enable_mask;
777                         pcs->write(val, pcs->base + offset);
778                 }
779         }
780 
781         pin = &pcs->pins.pa[i];
782         pn = &pcs->names[i];
783         sprintf(pn->name, "%lx.%u",
784                 (unsigned long)pcs->res->start + offset, pin_pos);
785         pin->name = pn->name;
786         pin->number = i;
787         pcs->pins.cur++;
788 
789         return i;
790 }
791 
792 /**
793  * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
794  * @pcs: pcs driver instance
795  *
796  * In case of errors, resources are freed in pcs_free_resources.
797  *
798  * If your hardware needs holes in the address space, then just set
799  * up multiple driver instances.
800  */
801 static int pcs_allocate_pin_table(struct pcs_device *pcs)
802 {
803         int mux_bytes, nr_pins, i;
804         int num_pins_in_register = 0;
805 
806         mux_bytes = pcs->width / BITS_PER_BYTE;
807 
808         if (pcs->bits_per_mux) {
809                 pcs->bits_per_pin = fls(pcs->fmask);
810                 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
811                 num_pins_in_register = pcs->width / pcs->bits_per_pin;
812         } else {
813                 nr_pins = pcs->size / mux_bytes;
814         }
815 
816         dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
817         pcs->pins.pa = devm_kzalloc(pcs->dev,
818                                 sizeof(*pcs->pins.pa) * nr_pins,
819                                 GFP_KERNEL);
820         if (!pcs->pins.pa)
821                 return -ENOMEM;
822 
823         pcs->names = devm_kzalloc(pcs->dev,
824                                 sizeof(struct pcs_name) * nr_pins,
825                                 GFP_KERNEL);
826         if (!pcs->names)
827                 return -ENOMEM;
828 
829         pcs->desc.pins = pcs->pins.pa;
830         pcs->desc.npins = nr_pins;
831 
832         for (i = 0; i < pcs->desc.npins; i++) {
833                 unsigned offset;
834                 int res;
835                 int byte_num;
836                 int pin_pos = 0;
837 
838                 if (pcs->bits_per_mux) {
839                         byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
840                         offset = (byte_num / mux_bytes) * mux_bytes;
841                         pin_pos = i % num_pins_in_register;
842                 } else {
843                         offset = i * mux_bytes;
844                 }
845                 res = pcs_add_pin(pcs, offset, pin_pos);
846                 if (res < 0) {
847                         dev_err(pcs->dev, "error adding pins: %i\n", res);
848                         return res;
849                 }
850         }
851 
852         return 0;
853 }
854 
855 /**
856  * pcs_add_function() - adds a new function to the function list
857  * @pcs: pcs driver instance
858  * @np: device node of the mux entry
859  * @name: name of the function
860  * @vals: array of mux register value pairs used by the function
861  * @nvals: number of mux register value pairs
862  * @pgnames: array of pingroup names for the function
863  * @npgnames: number of pingroup names
864  */
865 static struct pcs_function *pcs_add_function(struct pcs_device *pcs,
866                                         struct device_node *np,
867                                         const char *name,
868                                         struct pcs_func_vals *vals,
869                                         unsigned nvals,
870                                         const char **pgnames,
871                                         unsigned npgnames)
872 {
873         struct pcs_function *function;
874 
875         function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
876         if (!function)
877                 return NULL;
878 
879         function->name = name;
880         function->vals = vals;
881         function->nvals = nvals;
882         function->pgnames = pgnames;
883         function->npgnames = npgnames;
884 
885         mutex_lock(&pcs->mutex);
886         list_add_tail(&function->node, &pcs->functions);
887         radix_tree_insert(&pcs->ftree, pcs->nfuncs, function);
888         pcs->nfuncs++;
889         mutex_unlock(&pcs->mutex);
890 
891         return function;
892 }
893 
894 static void pcs_remove_function(struct pcs_device *pcs,
895                                 struct pcs_function *function)
896 {
897         int i;
898 
899         mutex_lock(&pcs->mutex);
900         for (i = 0; i < pcs->nfuncs; i++) {
901                 struct pcs_function *found;
902 
903                 found = radix_tree_lookup(&pcs->ftree, i);
904                 if (found == function)
905                         radix_tree_delete(&pcs->ftree, i);
906         }
907         list_del(&function->node);
908         mutex_unlock(&pcs->mutex);
909 }
910 
911 /**
912  * pcs_add_pingroup() - add a pingroup to the pingroup list
913  * @pcs: pcs driver instance
914  * @np: device node of the mux entry
915  * @name: name of the pingroup
916  * @gpins: array of the pins that belong to the group
917  * @ngpins: number of pins in the group
918  */
919 static int pcs_add_pingroup(struct pcs_device *pcs,
920                                         struct device_node *np,
921                                         const char *name,
922                                         int *gpins,
923                                         int ngpins)
924 {
925         struct pcs_pingroup *pingroup;
926 
927         pingroup = devm_kzalloc(pcs->dev, sizeof(*pingroup), GFP_KERNEL);
928         if (!pingroup)
929                 return -ENOMEM;
930 
931         pingroup->name = name;
932         pingroup->np = np;
933         pingroup->gpins = gpins;
934         pingroup->ngpins = ngpins;
935 
936         mutex_lock(&pcs->mutex);
937         list_add_tail(&pingroup->node, &pcs->pingroups);
938         radix_tree_insert(&pcs->pgtree, pcs->ngroups, pingroup);
939         pcs->ngroups++;
940         mutex_unlock(&pcs->mutex);
941 
942         return 0;
943 }
944 
945 /**
946  * pcs_get_pin_by_offset() - get a pin index based on the register offset
947  * @pcs: pcs driver instance
948  * @offset: register offset from the base
949  *
950  * Note that this is OK as long as the pins are in a static array.
951  */
952 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
953 {
954         unsigned index;
955 
956         if (offset >= pcs->size) {
957                 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
958                         offset, pcs->size);
959                 return -EINVAL;
960         }
961 
962         if (pcs->bits_per_mux)
963                 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
964         else
965                 index = offset / (pcs->width / BITS_PER_BYTE);
966 
967         return index;
968 }
969 
970 /*
971  * check whether data matches enable bits or disable bits
972  * Return value: 1 for matching enable bits, 0 for matching disable bits,
973  *               and negative value for matching failure.
974  */
975 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
976 {
977         int ret = -EINVAL;
978 
979         if (data == enable)
980                 ret = 1;
981         else if (data == disable)
982                 ret = 0;
983         return ret;
984 }
985 
986 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
987                        unsigned value, unsigned enable, unsigned disable,
988                        unsigned mask)
989 {
990         (*conf)->param = param;
991         (*conf)->val = value;
992         (*conf)->enable = enable;
993         (*conf)->disable = disable;
994         (*conf)->mask = mask;
995         (*conf)++;
996 }
997 
998 static void add_setting(unsigned long **setting, enum pin_config_param param,
999                         unsigned arg)
1000 {
1001         **setting = pinconf_to_config_packed(param, arg);
1002         (*setting)++;
1003 }
1004 
1005 /* add pinconf setting with 2 parameters */
1006 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
1007                           const char *name, enum pin_config_param param,
1008                           struct pcs_conf_vals **conf, unsigned long **settings)
1009 {
1010         unsigned value[2], shift;
1011         int ret;
1012 
1013         ret = of_property_read_u32_array(np, name, value, 2);
1014         if (ret)
1015                 return;
1016         /* set value & mask */
1017         value[0] &= value[1];
1018         shift = ffs(value[1]) - 1;
1019         /* skip enable & disable */
1020         add_config(conf, param, value[0], 0, 0, value[1]);
1021         add_setting(settings, param, value[0] >> shift);
1022 }
1023 
1024 /* add pinconf setting with 4 parameters */
1025 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
1026                           const char *name, enum pin_config_param param,
1027                           struct pcs_conf_vals **conf, unsigned long **settings)
1028 {
1029         unsigned value[4];
1030         int ret;
1031 
1032         /* value to set, enable, disable, mask */
1033         ret = of_property_read_u32_array(np, name, value, 4);
1034         if (ret)
1035                 return;
1036         if (!value[3]) {
1037                 dev_err(pcs->dev, "mask field of the property can't be 0\n");
1038                 return;
1039         }
1040         value[0] &= value[3];
1041         value[1] &= value[3];
1042         value[2] &= value[3];
1043         ret = pcs_config_match(value[0], value[1], value[2]);
1044         if (ret < 0)
1045                 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
1046         add_config(conf, param, value[0], value[1], value[2], value[3]);
1047         add_setting(settings, param, ret);
1048 }
1049 
1050 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
1051                              struct pcs_function *func,
1052                              struct pinctrl_map **map)
1053 
1054 {
1055         struct pinctrl_map *m = *map;
1056         int i = 0, nconfs = 0;
1057         unsigned long *settings = NULL, *s = NULL;
1058         struct pcs_conf_vals *conf = NULL;
1059         struct pcs_conf_type prop2[] = {
1060                 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
1061                 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
1062                 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
1063                 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
1064         };
1065         struct pcs_conf_type prop4[] = {
1066                 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
1067                 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
1068                 { "pinctrl-single,input-schmitt-enable",
1069                         PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
1070         };
1071 
1072         /* If pinconf isn't supported, don't parse properties in below. */
1073         if (!PCS_HAS_PINCONF)
1074                 return 0;
1075 
1076         /* cacluate how much properties are supported in current node */
1077         for (i = 0; i < ARRAY_SIZE(prop2); i++) {
1078                 if (of_find_property(np, prop2[i].name, NULL))
1079                         nconfs++;
1080         }
1081         for (i = 0; i < ARRAY_SIZE(prop4); i++) {
1082                 if (of_find_property(np, prop4[i].name, NULL))
1083                         nconfs++;
1084         }
1085         if (!nconfs)
1086                 return 0;
1087 
1088         func->conf = devm_kzalloc(pcs->dev,
1089                                   sizeof(struct pcs_conf_vals) * nconfs,
1090                                   GFP_KERNEL);
1091         if (!func->conf)
1092                 return -ENOMEM;
1093         func->nconfs = nconfs;
1094         conf = &(func->conf[0]);
1095         m++;
1096         settings = devm_kzalloc(pcs->dev, sizeof(unsigned long) * nconfs,
1097                                 GFP_KERNEL);
1098         if (!settings)
1099                 return -ENOMEM;
1100         s = &settings[0];
1101 
1102         for (i = 0; i < ARRAY_SIZE(prop2); i++)
1103                 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
1104                               &conf, &s);
1105         for (i = 0; i < ARRAY_SIZE(prop4); i++)
1106                 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
1107                               &conf, &s);
1108         m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
1109         m->data.configs.group_or_pin = np->name;
1110         m->data.configs.configs = settings;
1111         m->data.configs.num_configs = nconfs;
1112         return 0;
1113 }
1114 
1115 static void pcs_free_pingroups(struct pcs_device *pcs);
1116 
1117 /**
1118  * smux_parse_one_pinctrl_entry() - parses a device tree mux entry
1119  * @pcs: pinctrl driver instance
1120  * @np: device node of the mux entry
1121  * @map: map entry
1122  * @num_maps: number of map
1123  * @pgnames: pingroup names
1124  *
1125  * Note that this binding currently supports only sets of one register + value.
1126  *
1127  * Also note that this driver tries to avoid understanding pin and function
1128  * names because of the extra bloat they would cause especially in the case of
1129  * a large number of pins. This driver just sets what is specified for the board
1130  * in the .dts file. Further user space debugging tools can be developed to
1131  * decipher the pin and function names using debugfs.
1132  *
1133  * If you are concerned about the boot time, set up the static pins in
1134  * the bootloader, and only set up selected pins as device tree entries.
1135  */
1136 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
1137                                                 struct device_node *np,
1138                                                 struct pinctrl_map **map,
1139                                                 unsigned *num_maps,
1140                                                 const char **pgnames)
1141 {
1142         struct pcs_func_vals *vals;
1143         const __be32 *mux;
1144         int size, rows, *pins, index = 0, found = 0, res = -ENOMEM;
1145         struct pcs_function *function;
1146 
1147         mux = of_get_property(np, PCS_MUX_PINS_NAME, &size);
1148         if ((!mux) || (size < sizeof(*mux) * 2)) {
1149                 dev_err(pcs->dev, "bad data for mux %s\n",
1150                         np->name);
1151                 return -EINVAL;
1152         }
1153 
1154         size /= sizeof(*mux);   /* Number of elements in array */
1155         rows = size / 2;
1156 
1157         vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL);
1158         if (!vals)
1159                 return -ENOMEM;
1160 
1161         pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows, GFP_KERNEL);
1162         if (!pins)
1163                 goto free_vals;
1164 
1165         while (index < size) {
1166                 unsigned offset, val;
1167                 int pin;
1168 
1169                 offset = be32_to_cpup(mux + index++);
1170                 val = be32_to_cpup(mux + index++);
1171                 vals[found].reg = pcs->base + offset;
1172                 vals[found].val = val;
1173 
1174                 pin = pcs_get_pin_by_offset(pcs, offset);
1175                 if (pin < 0) {
1176                         dev_err(pcs->dev,
1177                                 "could not add functions for %s %ux\n",
1178                                 np->name, offset);
1179                         break;
1180                 }
1181                 pins[found++] = pin;
1182         }
1183 
1184         pgnames[0] = np->name;
1185         function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1186         if (!function)
1187                 goto free_pins;
1188 
1189         res = pcs_add_pingroup(pcs, np, np->name, pins, found);
1190         if (res < 0)
1191                 goto free_function;
1192 
1193         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1194         (*map)->data.mux.group = np->name;
1195         (*map)->data.mux.function = np->name;
1196 
1197         if (PCS_HAS_PINCONF) {
1198                 res = pcs_parse_pinconf(pcs, np, function, map);
1199                 if (res)
1200                         goto free_pingroups;
1201                 *num_maps = 2;
1202         } else {
1203                 *num_maps = 1;
1204         }
1205         return 0;
1206 
1207 free_pingroups:
1208         pcs_free_pingroups(pcs);
1209         *num_maps = 1;
1210 free_function:
1211         pcs_remove_function(pcs, function);
1212 
1213 free_pins:
1214         devm_kfree(pcs->dev, pins);
1215 
1216 free_vals:
1217         devm_kfree(pcs->dev, vals);
1218 
1219         return res;
1220 }
1221 
1222 #define PARAMS_FOR_BITS_PER_MUX 3
1223 
1224 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1225                                                 struct device_node *np,
1226                                                 struct pinctrl_map **map,
1227                                                 unsigned *num_maps,
1228                                                 const char **pgnames)
1229 {
1230         struct pcs_func_vals *vals;
1231         const __be32 *mux;
1232         int size, rows, *pins, index = 0, found = 0, res = -ENOMEM;
1233         int npins_in_row;
1234         struct pcs_function *function;
1235 
1236         mux = of_get_property(np, PCS_MUX_BITS_NAME, &size);
1237 
1238         if (!mux) {
1239                 dev_err(pcs->dev, "no valid property for %s\n", np->name);
1240                 return -EINVAL;
1241         }
1242 
1243         if (size < (sizeof(*mux) * PARAMS_FOR_BITS_PER_MUX)) {
1244                 dev_err(pcs->dev, "bad data for %s\n", np->name);
1245                 return -EINVAL;
1246         }
1247 
1248         /* Number of elements in array */
1249         size /= sizeof(*mux);
1250 
1251         rows = size / PARAMS_FOR_BITS_PER_MUX;
1252         npins_in_row = pcs->width / pcs->bits_per_pin;
1253 
1254         vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows * npins_in_row,
1255                         GFP_KERNEL);
1256         if (!vals)
1257                 return -ENOMEM;
1258 
1259         pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows * npins_in_row,
1260                         GFP_KERNEL);
1261         if (!pins)
1262                 goto free_vals;
1263 
1264         while (index < size) {
1265                 unsigned offset, val;
1266                 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1267                 unsigned pin_num_from_lsb;
1268                 int pin;
1269 
1270                 offset = be32_to_cpup(mux + index++);
1271                 val = be32_to_cpup(mux + index++);
1272                 mask = be32_to_cpup(mux + index++);
1273 
1274                 /* Parse pins in each row from LSB */
1275                 while (mask) {
1276                         bit_pos = ffs(mask);
1277                         pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1278                         mask_pos = ((pcs->fmask) << (bit_pos - 1));
1279                         val_pos = val & mask_pos;
1280                         submask = mask & mask_pos;
1281 
1282                         if ((mask & mask_pos) == 0) {
1283                                 dev_err(pcs->dev,
1284                                         "Invalid mask for %s at 0x%x\n",
1285                                         np->name, offset);
1286                                 break;
1287                         }
1288 
1289                         mask &= ~mask_pos;
1290 
1291                         if (submask != mask_pos) {
1292                                 dev_warn(pcs->dev,
1293                                                 "Invalid submask 0x%x for %s at 0x%x\n",
1294                                                 submask, np->name, offset);
1295                                 continue;
1296                         }
1297 
1298                         vals[found].mask = submask;
1299                         vals[found].reg = pcs->base + offset;
1300                         vals[found].val = val_pos;
1301 
1302                         pin = pcs_get_pin_by_offset(pcs, offset);
1303                         if (pin < 0) {
1304                                 dev_err(pcs->dev,
1305                                         "could not add functions for %s %ux\n",
1306                                         np->name, offset);
1307                                 break;
1308                         }
1309                         pins[found++] = pin + pin_num_from_lsb;
1310                 }
1311         }
1312 
1313         pgnames[0] = np->name;
1314         function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1315         if (!function)
1316                 goto free_pins;
1317 
1318         res = pcs_add_pingroup(pcs, np, np->name, pins, found);
1319         if (res < 0)
1320                 goto free_function;
1321 
1322         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1323         (*map)->data.mux.group = np->name;
1324         (*map)->data.mux.function = np->name;
1325 
1326         if (PCS_HAS_PINCONF) {
1327                 dev_err(pcs->dev, "pinconf not supported\n");
1328                 goto free_pingroups;
1329         }
1330 
1331         *num_maps = 1;
1332         return 0;
1333 
1334 free_pingroups:
1335         pcs_free_pingroups(pcs);
1336         *num_maps = 1;
1337 free_function:
1338         pcs_remove_function(pcs, function);
1339 
1340 free_pins:
1341         devm_kfree(pcs->dev, pins);
1342 
1343 free_vals:
1344         devm_kfree(pcs->dev, vals);
1345 
1346         return res;
1347 }
1348 /**
1349  * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1350  * @pctldev: pinctrl instance
1351  * @np_config: device tree pinmux entry
1352  * @map: array of map entries
1353  * @num_maps: number of maps
1354  */
1355 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1356                                 struct device_node *np_config,
1357                                 struct pinctrl_map **map, unsigned *num_maps)
1358 {
1359         struct pcs_device *pcs;
1360         const char **pgnames;
1361         int ret;
1362 
1363         pcs = pinctrl_dev_get_drvdata(pctldev);
1364 
1365         /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1366         *map = devm_kzalloc(pcs->dev, sizeof(**map) * 2, GFP_KERNEL);
1367         if (!*map)
1368                 return -ENOMEM;
1369 
1370         *num_maps = 0;
1371 
1372         pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1373         if (!pgnames) {
1374                 ret = -ENOMEM;
1375                 goto free_map;
1376         }
1377 
1378         if (pcs->bits_per_mux) {
1379                 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1380                                 num_maps, pgnames);
1381                 if (ret < 0) {
1382                         dev_err(pcs->dev, "no pins entries for %s\n",
1383                                 np_config->name);
1384                         goto free_pgnames;
1385                 }
1386         } else {
1387                 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1388                                 num_maps, pgnames);
1389                 if (ret < 0) {
1390                         dev_err(pcs->dev, "no pins entries for %s\n",
1391                                 np_config->name);
1392                         goto free_pgnames;
1393                 }
1394         }
1395 
1396         return 0;
1397 
1398 free_pgnames:
1399         devm_kfree(pcs->dev, pgnames);
1400 free_map:
1401         devm_kfree(pcs->dev, *map);
1402 
1403         return ret;
1404 }
1405 
1406 /**
1407  * pcs_free_funcs() - free memory used by functions
1408  * @pcs: pcs driver instance
1409  */
1410 static void pcs_free_funcs(struct pcs_device *pcs)
1411 {
1412         struct list_head *pos, *tmp;
1413         int i;
1414 
1415         mutex_lock(&pcs->mutex);
1416         for (i = 0; i < pcs->nfuncs; i++) {
1417                 struct pcs_function *func;
1418 
1419                 func = radix_tree_lookup(&pcs->ftree, i);
1420                 if (!func)
1421                         continue;
1422                 radix_tree_delete(&pcs->ftree, i);
1423         }
1424         list_for_each_safe(pos, tmp, &pcs->functions) {
1425                 struct pcs_function *function;
1426 
1427                 function = list_entry(pos, struct pcs_function, node);
1428                 list_del(&function->node);
1429         }
1430         mutex_unlock(&pcs->mutex);
1431 }
1432 
1433 /**
1434  * pcs_free_pingroups() - free memory used by pingroups
1435  * @pcs: pcs driver instance
1436  */
1437 static void pcs_free_pingroups(struct pcs_device *pcs)
1438 {
1439         struct list_head *pos, *tmp;
1440         int i;
1441 
1442         mutex_lock(&pcs->mutex);
1443         for (i = 0; i < pcs->ngroups; i++) {
1444                 struct pcs_pingroup *pingroup;
1445 
1446                 pingroup = radix_tree_lookup(&pcs->pgtree, i);
1447                 if (!pingroup)
1448                         continue;
1449                 radix_tree_delete(&pcs->pgtree, i);
1450         }
1451         list_for_each_safe(pos, tmp, &pcs->pingroups) {
1452                 struct pcs_pingroup *pingroup;
1453 
1454                 pingroup = list_entry(pos, struct pcs_pingroup, node);
1455                 list_del(&pingroup->node);
1456         }
1457         mutex_unlock(&pcs->mutex);
1458 }
1459 
1460 /**
1461  * pcs_irq_free() - free interrupt
1462  * @pcs: pcs driver instance
1463  */
1464 static void pcs_irq_free(struct pcs_device *pcs)
1465 {
1466         struct pcs_soc_data *pcs_soc = &pcs->socdata;
1467 
1468         if (pcs_soc->irq < 0)
1469                 return;
1470 
1471         if (pcs->domain)
1472                 irq_domain_remove(pcs->domain);
1473 
1474         if (PCS_QUIRK_HAS_SHARED_IRQ)
1475                 free_irq(pcs_soc->irq, pcs_soc);
1476         else
1477                 irq_set_chained_handler(pcs_soc->irq, NULL);
1478 }
1479 
1480 /**
1481  * pcs_free_resources() - free memory used by this driver
1482  * @pcs: pcs driver instance
1483  */
1484 static void pcs_free_resources(struct pcs_device *pcs)
1485 {
1486         pcs_irq_free(pcs);
1487 
1488         if (pcs->pctl)
1489                 pinctrl_unregister(pcs->pctl);
1490 
1491         pcs_free_funcs(pcs);
1492         pcs_free_pingroups(pcs);
1493 }
1494 
1495 #define PCS_GET_PROP_U32(name, reg, err)                                \
1496         do {                                                            \
1497                 ret = of_property_read_u32(np, name, reg);              \
1498                 if (ret) {                                              \
1499                         dev_err(pcs->dev, err);                         \
1500                         return ret;                                     \
1501                 }                                                       \
1502         } while (0);
1503 
1504 static struct of_device_id pcs_of_match[];
1505 
1506 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1507 {
1508         const char *propname = "pinctrl-single,gpio-range";
1509         const char *cellname = "#pinctrl-single,gpio-range-cells";
1510         struct of_phandle_args gpiospec;
1511         struct pcs_gpiofunc_range *range;
1512         int ret, i;
1513 
1514         for (i = 0; ; i++) {
1515                 ret = of_parse_phandle_with_args(node, propname, cellname,
1516                                                  i, &gpiospec);
1517                 /* Do not treat it as error. Only treat it as end condition. */
1518                 if (ret) {
1519                         ret = 0;
1520                         break;
1521                 }
1522                 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1523                 if (!range) {
1524                         ret = -ENOMEM;
1525                         break;
1526                 }
1527                 range->offset = gpiospec.args[0];
1528                 range->npins = gpiospec.args[1];
1529                 range->gpiofunc = gpiospec.args[2];
1530                 mutex_lock(&pcs->mutex);
1531                 list_add_tail(&range->node, &pcs->gpiofuncs);
1532                 mutex_unlock(&pcs->mutex);
1533         }
1534         return ret;
1535 }
1536 /**
1537  * @reg:        virtual address of interrupt register
1538  * @hwirq:      hardware irq number
1539  * @irq:        virtual irq number
1540  * @node:       list node
1541  */
1542 struct pcs_interrupt {
1543         void __iomem *reg;
1544         irq_hw_number_t hwirq;
1545         unsigned int irq;
1546         struct list_head node;
1547 };
1548 
1549 /**
1550  * pcs_irq_set() - enables or disables an interrupt
1551  *
1552  * Note that this currently assumes one interrupt per pinctrl
1553  * register that is typically used for wake-up events.
1554  */
1555 static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1556                                int irq, const bool enable)
1557 {
1558         struct pcs_device *pcs;
1559         struct list_head *pos;
1560         unsigned mask;
1561 
1562         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1563         list_for_each(pos, &pcs->irqs) {
1564                 struct pcs_interrupt *pcswi;
1565                 unsigned soc_mask;
1566 
1567                 pcswi = list_entry(pos, struct pcs_interrupt, node);
1568                 if (irq != pcswi->irq)
1569                         continue;
1570 
1571                 soc_mask = pcs_soc->irq_enable_mask;
1572                 raw_spin_lock(&pcs->lock);
1573                 mask = pcs->read(pcswi->reg);
1574                 if (enable)
1575                         mask |= soc_mask;
1576                 else
1577                         mask &= ~soc_mask;
1578                 pcs->write(mask, pcswi->reg);
1579                 raw_spin_unlock(&pcs->lock);
1580         }
1581 
1582         if (pcs_soc->rearm)
1583                 pcs_soc->rearm();
1584 }
1585 
1586 /**
1587  * pcs_irq_mask() - mask pinctrl interrupt
1588  * @d: interrupt data
1589  */
1590 static void pcs_irq_mask(struct irq_data *d)
1591 {
1592         struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1593 
1594         pcs_irq_set(pcs_soc, d->irq, false);
1595 }
1596 
1597 /**
1598  * pcs_irq_unmask() - unmask pinctrl interrupt
1599  * @d: interrupt data
1600  */
1601 static void pcs_irq_unmask(struct irq_data *d)
1602 {
1603         struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1604 
1605         pcs_irq_set(pcs_soc, d->irq, true);
1606 }
1607 
1608 /**
1609  * pcs_irq_set_wake() - toggle the suspend and resume wake up
1610  * @d: interrupt data
1611  * @state: wake-up state
1612  *
1613  * Note that this should be called only for suspend and resume.
1614  * For runtime PM, the wake-up events should be enabled by default.
1615  */
1616 static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1617 {
1618         if (state)
1619                 pcs_irq_unmask(d);
1620         else
1621                 pcs_irq_mask(d);
1622 
1623         return 0;
1624 }
1625 
1626 /**
1627  * pcs_irq_handle() - common interrupt handler
1628  * @pcs_irq: interrupt data
1629  *
1630  * Note that this currently assumes we have one interrupt bit per
1631  * mux register. This interrupt is typically used for wake-up events.
1632  * For more complex interrupts different handlers can be specified.
1633  */
1634 static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1635 {
1636         struct pcs_device *pcs;
1637         struct list_head *pos;
1638         int count = 0;
1639 
1640         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1641         list_for_each(pos, &pcs->irqs) {
1642                 struct pcs_interrupt *pcswi;
1643                 unsigned mask;
1644 
1645                 pcswi = list_entry(pos, struct pcs_interrupt, node);
1646                 raw_spin_lock(&pcs->lock);
1647                 mask = pcs->read(pcswi->reg);
1648                 raw_spin_unlock(&pcs->lock);
1649                 if (mask & pcs_soc->irq_status_mask) {
1650                         generic_handle_irq(irq_find_mapping(pcs->domain,
1651                                                             pcswi->hwirq));
1652                         count++;
1653                 }
1654         }
1655 
1656         return count;
1657 }
1658 
1659 /**
1660  * pcs_irq_handler() - handler for the shared interrupt case
1661  * @irq: interrupt
1662  * @d: data
1663  *
1664  * Use this for cases where multiple instances of
1665  * pinctrl-single share a single interrupt like on omaps.
1666  */
1667 static irqreturn_t pcs_irq_handler(int irq, void *d)
1668 {
1669         struct pcs_soc_data *pcs_soc = d;
1670 
1671         return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1672 }
1673 
1674 /**
1675  * pcs_irq_handle() - handler for the dedicated chained interrupt case
1676  * @irq: interrupt
1677  * @desc: interrupt descriptor
1678  *
1679  * Use this if you have a separate interrupt for each
1680  * pinctrl-single instance.
1681  */
1682 static void pcs_irq_chain_handler(unsigned int irq, struct irq_desc *desc)
1683 {
1684         struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1685         struct irq_chip *chip;
1686 
1687         chip = irq_get_chip(irq);
1688         chained_irq_enter(chip, desc);
1689         pcs_irq_handle(pcs_soc);
1690         /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1691         chained_irq_exit(chip, desc);
1692 
1693         return;
1694 }
1695 
1696 static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1697                              irq_hw_number_t hwirq)
1698 {
1699         struct pcs_soc_data *pcs_soc = d->host_data;
1700         struct pcs_device *pcs;
1701         struct pcs_interrupt *pcswi;
1702 
1703         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1704         pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1705         if (!pcswi)
1706                 return -ENOMEM;
1707 
1708         pcswi->reg = pcs->base + hwirq;
1709         pcswi->hwirq = hwirq;
1710         pcswi->irq = irq;
1711 
1712         mutex_lock(&pcs->mutex);
1713         list_add_tail(&pcswi->node, &pcs->irqs);
1714         mutex_unlock(&pcs->mutex);
1715 
1716         irq_set_chip_data(irq, pcs_soc);
1717         irq_set_chip_and_handler(irq, &pcs->chip,
1718                                  handle_level_irq);
1719 
1720 #ifdef CONFIG_ARM
1721         set_irq_flags(irq, IRQF_VALID);
1722 #else
1723         irq_set_noprobe(irq);
1724 #endif
1725 
1726         return 0;
1727 }
1728 
1729 static struct irq_domain_ops pcs_irqdomain_ops = {
1730         .map = pcs_irqdomain_map,
1731         .xlate = irq_domain_xlate_onecell,
1732 };
1733 
1734 /**
1735  * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1736  * @pcs: pcs driver instance
1737  * @np: device node pointer
1738  */
1739 static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1740                                         struct device_node *np)
1741 {
1742         struct pcs_soc_data *pcs_soc = &pcs->socdata;
1743         const char *name = "pinctrl";
1744         int num_irqs;
1745 
1746         if (!pcs_soc->irq_enable_mask ||
1747             !pcs_soc->irq_status_mask) {
1748                 pcs_soc->irq = -1;
1749                 return -EINVAL;
1750         }
1751 
1752         INIT_LIST_HEAD(&pcs->irqs);
1753         pcs->chip.name = name;
1754         pcs->chip.irq_ack = pcs_irq_mask;
1755         pcs->chip.irq_mask = pcs_irq_mask;
1756         pcs->chip.irq_unmask = pcs_irq_unmask;
1757         pcs->chip.irq_set_wake = pcs_irq_set_wake;
1758 
1759         if (PCS_QUIRK_HAS_SHARED_IRQ) {
1760                 int res;
1761 
1762                 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1763                                   IRQF_SHARED | IRQF_NO_SUSPEND,
1764                                   name, pcs_soc);
1765                 if (res) {
1766                         pcs_soc->irq = -1;
1767                         return res;
1768                 }
1769         } else {
1770                 irq_set_handler_data(pcs_soc->irq, pcs_soc);
1771                 irq_set_chained_handler(pcs_soc->irq,
1772                                         pcs_irq_chain_handler);
1773         }
1774 
1775         /*
1776          * We can use the register offset as the hardirq
1777          * number as irq_domain_add_simple maps them lazily.
1778          * This way we can easily support more than one
1779          * interrupt per function if needed.
1780          */
1781         num_irqs = pcs->size;
1782 
1783         pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1784                                             &pcs_irqdomain_ops,
1785                                             pcs_soc);
1786         if (!pcs->domain) {
1787                 irq_set_chained_handler(pcs_soc->irq, NULL);
1788                 return -EINVAL;
1789         }
1790 
1791         return 0;
1792 }
1793 
1794 #ifdef CONFIG_PM
1795 static int pinctrl_single_suspend(struct platform_device *pdev,
1796                                         pm_message_t state)
1797 {
1798         struct pcs_device *pcs;
1799 
1800         pcs = platform_get_drvdata(pdev);
1801         if (!pcs)
1802                 return -EINVAL;
1803 
1804         return pinctrl_force_sleep(pcs->pctl);
1805 }
1806 
1807 static int pinctrl_single_resume(struct platform_device *pdev)
1808 {
1809         struct pcs_device *pcs;
1810 
1811         pcs = platform_get_drvdata(pdev);
1812         if (!pcs)
1813                 return -EINVAL;
1814 
1815         return pinctrl_force_default(pcs->pctl);
1816 }
1817 #endif
1818 
1819 static int pcs_probe(struct platform_device *pdev)
1820 {
1821         struct device_node *np = pdev->dev.of_node;
1822         const struct of_device_id *match;
1823         struct pcs_pdata *pdata;
1824         struct resource *res;
1825         struct pcs_device *pcs;
1826         const struct pcs_soc_data *soc;
1827         int ret;
1828 
1829         match = of_match_device(pcs_of_match, &pdev->dev);
1830         if (!match)
1831                 return -EINVAL;
1832 
1833         pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1834         if (!pcs) {
1835                 dev_err(&pdev->dev, "could not allocate\n");
1836                 return -ENOMEM;
1837         }
1838         pcs->dev = &pdev->dev;
1839         raw_spin_lock_init(&pcs->lock);
1840         mutex_init(&pcs->mutex);
1841         INIT_LIST_HEAD(&pcs->pingroups);
1842         INIT_LIST_HEAD(&pcs->functions);
1843         INIT_LIST_HEAD(&pcs->gpiofuncs);
1844         soc = match->data;
1845         pcs->flags = soc->flags;
1846         memcpy(&pcs->socdata, soc, sizeof(*soc));
1847 
1848         PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width,
1849                          "register width not specified\n");
1850 
1851         ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1852                                    &pcs->fmask);
1853         if (!ret) {
1854                 pcs->fshift = ffs(pcs->fmask) - 1;
1855                 pcs->fmax = pcs->fmask >> pcs->fshift;
1856         } else {
1857                 /* If mask property doesn't exist, function mux is invalid. */
1858                 pcs->fmask = 0;
1859                 pcs->fshift = 0;
1860                 pcs->fmax = 0;
1861         }
1862 
1863         ret = of_property_read_u32(np, "pinctrl-single,function-off",
1864                                         &pcs->foff);
1865         if (ret)
1866                 pcs->foff = PCS_OFF_DISABLED;
1867 
1868         pcs->bits_per_mux = of_property_read_bool(np,
1869                                                   "pinctrl-single,bit-per-mux");
1870 
1871         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1872         if (!res) {
1873                 dev_err(pcs->dev, "could not get resource\n");
1874                 return -ENODEV;
1875         }
1876 
1877         pcs->res = devm_request_mem_region(pcs->dev, res->start,
1878                         resource_size(res), DRIVER_NAME);
1879         if (!pcs->res) {
1880                 dev_err(pcs->dev, "could not get mem_region\n");
1881                 return -EBUSY;
1882         }
1883 
1884         pcs->size = resource_size(pcs->res);
1885         pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1886         if (!pcs->base) {
1887                 dev_err(pcs->dev, "could not ioremap\n");
1888                 return -ENODEV;
1889         }
1890 
1891         INIT_RADIX_TREE(&pcs->pgtree, GFP_KERNEL);
1892         INIT_RADIX_TREE(&pcs->ftree, GFP_KERNEL);
1893         platform_set_drvdata(pdev, pcs);
1894 
1895         switch (pcs->width) {
1896         case 8:
1897                 pcs->read = pcs_readb;
1898                 pcs->write = pcs_writeb;
1899                 break;
1900         case 16:
1901                 pcs->read = pcs_readw;
1902                 pcs->write = pcs_writew;
1903                 break;
1904         case 32:
1905                 pcs->read = pcs_readl;
1906                 pcs->write = pcs_writel;
1907                 break;
1908         default:
1909                 break;
1910         }
1911 
1912         pcs->desc.name = DRIVER_NAME;
1913         pcs->desc.pctlops = &pcs_pinctrl_ops;
1914         pcs->desc.pmxops = &pcs_pinmux_ops;
1915         if (PCS_HAS_PINCONF)
1916                 pcs->desc.confops = &pcs_pinconf_ops;
1917         pcs->desc.owner = THIS_MODULE;
1918 
1919         ret = pcs_allocate_pin_table(pcs);
1920         if (ret < 0)
1921                 goto free;
1922 
1923         pcs->pctl = pinctrl_register(&pcs->desc, pcs->dev, pcs);
1924         if (!pcs->pctl) {
1925                 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1926                 ret = -EINVAL;
1927                 goto free;
1928         }
1929 
1930         ret = pcs_add_gpio_func(np, pcs);
1931         if (ret < 0)
1932                 goto free;
1933 
1934         pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1935         if (pcs->socdata.irq)
1936                 pcs->flags |= PCS_FEAT_IRQ;
1937 
1938         /* We still need auxdata for some omaps for PRM interrupts */
1939         pdata = dev_get_platdata(&pdev->dev);
1940         if (pdata) {
1941                 if (pdata->rearm)
1942                         pcs->socdata.rearm = pdata->rearm;
1943                 if (pdata->irq) {
1944                         pcs->socdata.irq = pdata->irq;
1945                         pcs->flags |= PCS_FEAT_IRQ;
1946                 }
1947         }
1948 
1949         if (PCS_HAS_IRQ) {
1950                 ret = pcs_irq_init_chained_handler(pcs, np);
1951                 if (ret < 0)
1952                         dev_warn(pcs->dev, "initialized with no interrupts\n");
1953         }
1954 
1955         dev_info(pcs->dev, "%i pins at pa %p size %u\n",
1956                  pcs->desc.npins, pcs->base, pcs->size);
1957 
1958         return 0;
1959 
1960 free:
1961         pcs_free_resources(pcs);
1962 
1963         return ret;
1964 }
1965 
1966 static int pcs_remove(struct platform_device *pdev)
1967 {
1968         struct pcs_device *pcs = platform_get_drvdata(pdev);
1969 
1970         if (!pcs)
1971                 return 0;
1972 
1973         pcs_free_resources(pcs);
1974 
1975         return 0;
1976 }
1977 
1978 static const struct pcs_soc_data pinctrl_single_omap_wkup = {
1979         .flags = PCS_QUIRK_SHARED_IRQ,
1980         .irq_enable_mask = (1 << 14),   /* OMAP_WAKEUP_EN */
1981         .irq_status_mask = (1 << 15),   /* OMAP_WAKEUP_EVENT */
1982 };
1983 
1984 static const struct pcs_soc_data pinctrl_single = {
1985 };
1986 
1987 static const struct pcs_soc_data pinconf_single = {
1988         .flags = PCS_FEAT_PINCONF,
1989 };
1990 
1991 static struct of_device_id pcs_of_match[] = {
1992         { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1993         { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1994         { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1995         { .compatible = "pinctrl-single", .data = &pinctrl_single },
1996         { .compatible = "pinconf-single", .data = &pinconf_single },
1997         { },
1998 };
1999 MODULE_DEVICE_TABLE(of, pcs_of_match);
2000 
2001 static struct platform_driver pcs_driver = {
2002         .probe          = pcs_probe,
2003         .remove         = pcs_remove,
2004         .driver = {
2005                 .owner          = THIS_MODULE,
2006                 .name           = DRIVER_NAME,
2007                 .of_match_table = pcs_of_match,
2008         },
2009 #ifdef CONFIG_PM
2010         .suspend = pinctrl_single_suspend,
2011         .resume = pinctrl_single_resume,
2012 #endif
2013 };
2014 
2015 module_platform_driver(pcs_driver);
2016 
2017 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
2018 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
2019 MODULE_LICENSE("GPL v2");
2020 

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