Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/pinctrl/pinctrl-exynos5440.c

  1 /*
  2  * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's EXYNOS5440 SoC.
  3  *
  4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  5  *              http://www.samsung.com
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License as published by
  9  * the Free Software Foundation; either version 2 of the License, or
 10  * (at your option) any later version.
 11  */
 12 
 13 #include <linux/module.h>
 14 #include <linux/platform_device.h>
 15 #include <linux/io.h>
 16 #include <linux/slab.h>
 17 #include <linux/err.h>
 18 #include <linux/gpio.h>
 19 #include <linux/device.h>
 20 #include <linux/pinctrl/pinctrl.h>
 21 #include <linux/pinctrl/pinmux.h>
 22 #include <linux/pinctrl/pinconf.h>
 23 #include <linux/interrupt.h>
 24 #include <linux/irqdomain.h>
 25 #include <linux/of_irq.h>
 26 #include "core.h"
 27 
 28 /* EXYNOS5440 GPIO and Pinctrl register offsets */
 29 #define GPIO_MUX                0x00
 30 #define GPIO_IE                 0x04
 31 #define GPIO_INT                0x08
 32 #define GPIO_TYPE               0x0C
 33 #define GPIO_VAL                0x10
 34 #define GPIO_OE                 0x14
 35 #define GPIO_IN                 0x18
 36 #define GPIO_PE                 0x1C
 37 #define GPIO_PS                 0x20
 38 #define GPIO_SR                 0x24
 39 #define GPIO_DS0                0x28
 40 #define GPIO_DS1                0x2C
 41 
 42 #define EXYNOS5440_MAX_PINS             23
 43 #define EXYNOS5440_MAX_GPIO_INT 8
 44 #define PIN_NAME_LENGTH         10
 45 
 46 #define GROUP_SUFFIX            "-grp"
 47 #define GSUFFIX_LEN             sizeof(GROUP_SUFFIX)
 48 #define FUNCTION_SUFFIX         "-mux"
 49 #define FSUFFIX_LEN             sizeof(FUNCTION_SUFFIX)
 50 
 51 /*
 52  * pin configuration type and its value are packed together into a 16-bits.
 53  * The upper 8-bits represent the configuration type and the lower 8-bits
 54  * hold the value of the configuration type.
 55  */
 56 #define PINCFG_TYPE_MASK                0xFF
 57 #define PINCFG_VALUE_SHIFT              8
 58 #define PINCFG_VALUE_MASK               (0xFF << PINCFG_VALUE_SHIFT)
 59 #define PINCFG_PACK(type, value)        (((value) << PINCFG_VALUE_SHIFT) | type)
 60 #define PINCFG_UNPACK_TYPE(cfg)         ((cfg) & PINCFG_TYPE_MASK)
 61 #define PINCFG_UNPACK_VALUE(cfg)        (((cfg) & PINCFG_VALUE_MASK) >> \
 62                                                 PINCFG_VALUE_SHIFT)
 63 
 64 /**
 65  * enum pincfg_type - possible pin configuration types supported.
 66  * @PINCFG_TYPE_PUD: Pull up/down configuration.
 67  * @PINCFG_TYPE_DRV: Drive strength configuration.
 68  * @PINCFG_TYPE_SKEW_RATE: Skew rate configuration.
 69  * @PINCFG_TYPE_INPUT_TYPE: Pin input type configuration.
 70  */
 71 enum pincfg_type {
 72         PINCFG_TYPE_PUD,
 73         PINCFG_TYPE_DRV,
 74         PINCFG_TYPE_SKEW_RATE,
 75         PINCFG_TYPE_INPUT_TYPE
 76 };
 77 
 78 /**
 79  * struct exynos5440_pin_group: represent group of pins for pincfg setting.
 80  * @name: name of the pin group, used to lookup the group.
 81  * @pins: the pins included in this group.
 82  * @num_pins: number of pins included in this group.
 83  */
 84 struct exynos5440_pin_group {
 85         const char              *name;
 86         const unsigned int      *pins;
 87         u8                      num_pins;
 88 };
 89 
 90 /**
 91  * struct exynos5440_pmx_func: represent a pin function.
 92  * @name: name of the pin function, used to lookup the function.
 93  * @groups: one or more names of pin groups that provide this function.
 94  * @num_groups: number of groups included in @groups.
 95  * @function: the function number to be programmed when selected.
 96  */
 97 struct exynos5440_pmx_func {
 98         const char              *name;
 99         const char              **groups;
100         u8                      num_groups;
101         unsigned long           function;
102 };
103 
104 /**
105  * struct exynos5440_pinctrl_priv_data: driver's private runtime data.
106  * @reg_base: ioremapped based address of the register space.
107  * @gc: gpio chip registered with gpiolib.
108  * @pin_groups: list of pin groups parsed from device tree.
109  * @nr_groups: number of pin groups available.
110  * @pmx_functions: list of pin functions parsed from device tree.
111  * @nr_functions: number of pin functions available.
112  */
113 struct exynos5440_pinctrl_priv_data {
114         void __iomem                    *reg_base;
115         struct gpio_chip                *gc;
116         struct irq_domain               *irq_domain;
117 
118         const struct exynos5440_pin_group       *pin_groups;
119         unsigned int                    nr_groups;
120         const struct exynos5440_pmx_func        *pmx_functions;
121         unsigned int                    nr_functions;
122 };
123 
124 /**
125  * struct exynos5440_gpio_intr_data: private data for gpio interrupts.
126  * @priv: driver's private runtime data.
127  * @gpio_int: gpio interrupt number.
128  */
129 struct exynos5440_gpio_intr_data {
130         struct exynos5440_pinctrl_priv_data     *priv;
131         unsigned int                            gpio_int;
132 };
133 
134 /* list of all possible config options supported */
135 static struct pin_config {
136         char            *prop_cfg;
137         unsigned int    cfg_type;
138 } pcfgs[] = {
139         { "samsung,exynos5440-pin-pud", PINCFG_TYPE_PUD },
140         { "samsung,exynos5440-pin-drv", PINCFG_TYPE_DRV },
141         { "samsung,exynos5440-pin-skew-rate", PINCFG_TYPE_SKEW_RATE },
142         { "samsung,exynos5440-pin-input-type", PINCFG_TYPE_INPUT_TYPE },
143 };
144 
145 /* check if the selector is a valid pin group selector */
146 static int exynos5440_get_group_count(struct pinctrl_dev *pctldev)
147 {
148         struct exynos5440_pinctrl_priv_data *priv;
149 
150         priv = pinctrl_dev_get_drvdata(pctldev);
151         return priv->nr_groups;
152 }
153 
154 /* return the name of the group selected by the group selector */
155 static const char *exynos5440_get_group_name(struct pinctrl_dev *pctldev,
156                                                 unsigned selector)
157 {
158         struct exynos5440_pinctrl_priv_data *priv;
159 
160         priv = pinctrl_dev_get_drvdata(pctldev);
161         return priv->pin_groups[selector].name;
162 }
163 
164 /* return the pin numbers associated with the specified group */
165 static int exynos5440_get_group_pins(struct pinctrl_dev *pctldev,
166                 unsigned selector, const unsigned **pins, unsigned *num_pins)
167 {
168         struct exynos5440_pinctrl_priv_data *priv;
169 
170         priv = pinctrl_dev_get_drvdata(pctldev);
171         *pins = priv->pin_groups[selector].pins;
172         *num_pins = priv->pin_groups[selector].num_pins;
173         return 0;
174 }
175 
176 /* create pinctrl_map entries by parsing device tree nodes */
177 static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev,
178                         struct device_node *np, struct pinctrl_map **maps,
179                         unsigned *nmaps)
180 {
181         struct device *dev = pctldev->dev;
182         struct pinctrl_map *map;
183         unsigned long *cfg = NULL;
184         char *gname, *fname;
185         int cfg_cnt = 0, map_cnt = 0, idx = 0;
186 
187         /* count the number of config options specfied in the node */
188         for (idx = 0; idx < ARRAY_SIZE(pcfgs); idx++)
189                 if (of_find_property(np, pcfgs[idx].prop_cfg, NULL))
190                         cfg_cnt++;
191 
192         /*
193          * Find out the number of map entries to create. All the config options
194          * can be accomadated into a single config map entry.
195          */
196         if (cfg_cnt)
197                 map_cnt = 1;
198         if (of_find_property(np, "samsung,exynos5440-pin-function", NULL))
199                 map_cnt++;
200         if (!map_cnt) {
201                 dev_err(dev, "node %s does not have either config or function "
202                                 "configurations\n", np->name);
203                 return -EINVAL;
204         }
205 
206         /* Allocate memory for pin-map entries */
207         map = kzalloc(sizeof(*map) * map_cnt, GFP_KERNEL);
208         if (!map) {
209                 dev_err(dev, "could not alloc memory for pin-maps\n");
210                 return -ENOMEM;
211         }
212         *nmaps = 0;
213 
214         /*
215          * Allocate memory for pin group name. The pin group name is derived
216          * from the node name from which these map entries are be created.
217          */
218         gname = kzalloc(strlen(np->name) + GSUFFIX_LEN, GFP_KERNEL);
219         if (!gname) {
220                 dev_err(dev, "failed to alloc memory for group name\n");
221                 goto free_map;
222         }
223         snprintf(gname, strlen(np->name) + 4, "%s%s", np->name, GROUP_SUFFIX);
224 
225         /*
226          * don't have config options? then skip over to creating function
227          * map entries.
228          */
229         if (!cfg_cnt)
230                 goto skip_cfgs;
231 
232         /* Allocate memory for config entries */
233         cfg = kzalloc(sizeof(*cfg) * cfg_cnt, GFP_KERNEL);
234         if (!cfg) {
235                 dev_err(dev, "failed to alloc memory for configs\n");
236                 goto free_gname;
237         }
238 
239         /* Prepare a list of config settings */
240         for (idx = 0, cfg_cnt = 0; idx < ARRAY_SIZE(pcfgs); idx++) {
241                 u32 value;
242                 if (!of_property_read_u32(np, pcfgs[idx].prop_cfg, &value))
243                         cfg[cfg_cnt++] =
244                                 PINCFG_PACK(pcfgs[idx].cfg_type, value);
245         }
246 
247         /* create the config map entry */
248         map[*nmaps].data.configs.group_or_pin = gname;
249         map[*nmaps].data.configs.configs = cfg;
250         map[*nmaps].data.configs.num_configs = cfg_cnt;
251         map[*nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
252         *nmaps += 1;
253 
254 skip_cfgs:
255         /* create the function map entry */
256         if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) {
257                 fname = kzalloc(strlen(np->name) + FSUFFIX_LEN, GFP_KERNEL);
258                 if (!fname) {
259                         dev_err(dev, "failed to alloc memory for func name\n");
260                         goto free_cfg;
261                 }
262                 snprintf(fname, strlen(np->name) + 4, "%s%s", np->name,
263                          FUNCTION_SUFFIX);
264 
265                 map[*nmaps].data.mux.group = gname;
266                 map[*nmaps].data.mux.function = fname;
267                 map[*nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
268                 *nmaps += 1;
269         }
270 
271         *maps = map;
272         return 0;
273 
274 free_cfg:
275         kfree(cfg);
276 free_gname:
277         kfree(gname);
278 free_map:
279         kfree(map);
280         return -ENOMEM;
281 }
282 
283 /* free the memory allocated to hold the pin-map table */
284 static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev,
285                              struct pinctrl_map *map, unsigned num_maps)
286 {
287         int idx;
288 
289         for (idx = 0; idx < num_maps; idx++) {
290                 if (map[idx].type == PIN_MAP_TYPE_MUX_GROUP) {
291                         kfree(map[idx].data.mux.function);
292                         if (!idx)
293                                 kfree(map[idx].data.mux.group);
294                 } else if (map->type == PIN_MAP_TYPE_CONFIGS_GROUP) {
295                         kfree(map[idx].data.configs.configs);
296                         if (!idx)
297                                 kfree(map[idx].data.configs.group_or_pin);
298                 }
299         };
300 
301         kfree(map);
302 }
303 
304 /* list of pinctrl callbacks for the pinctrl core */
305 static const struct pinctrl_ops exynos5440_pctrl_ops = {
306         .get_groups_count       = exynos5440_get_group_count,
307         .get_group_name         = exynos5440_get_group_name,
308         .get_group_pins         = exynos5440_get_group_pins,
309         .dt_node_to_map         = exynos5440_dt_node_to_map,
310         .dt_free_map            = exynos5440_dt_free_map,
311 };
312 
313 /* check if the selector is a valid pin function selector */
314 static int exynos5440_get_functions_count(struct pinctrl_dev *pctldev)
315 {
316         struct exynos5440_pinctrl_priv_data *priv;
317 
318         priv = pinctrl_dev_get_drvdata(pctldev);
319         return priv->nr_functions;
320 }
321 
322 /* return the name of the pin function specified */
323 static const char *exynos5440_pinmux_get_fname(struct pinctrl_dev *pctldev,
324                                                 unsigned selector)
325 {
326         struct exynos5440_pinctrl_priv_data *priv;
327 
328         priv = pinctrl_dev_get_drvdata(pctldev);
329         return priv->pmx_functions[selector].name;
330 }
331 
332 /* return the groups associated for the specified function selector */
333 static int exynos5440_pinmux_get_groups(struct pinctrl_dev *pctldev,
334                 unsigned selector, const char * const **groups,
335                 unsigned * const num_groups)
336 {
337         struct exynos5440_pinctrl_priv_data *priv;
338 
339         priv = pinctrl_dev_get_drvdata(pctldev);
340         *groups = priv->pmx_functions[selector].groups;
341         *num_groups = priv->pmx_functions[selector].num_groups;
342         return 0;
343 }
344 
345 /* enable or disable a pinmux function */
346 static void exynos5440_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
347                                         unsigned group, bool enable)
348 {
349         struct exynos5440_pinctrl_priv_data *priv;
350         void __iomem *base;
351         u32 function;
352         u32 data;
353 
354         priv = pinctrl_dev_get_drvdata(pctldev);
355         base = priv->reg_base;
356         function = priv->pmx_functions[selector].function;
357 
358         data = readl(base + GPIO_MUX);
359         if (enable)
360                 data |= (1 << function);
361         else
362                 data &= ~(1 << function);
363         writel(data, base + GPIO_MUX);
364 }
365 
366 /* enable a specified pinmux by writing to registers */
367 static int exynos5440_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
368                                         unsigned group)
369 {
370         exynos5440_pinmux_setup(pctldev, selector, group, true);
371         return 0;
372 }
373 
374 /* disable a specified pinmux by writing to registers */
375 static void exynos5440_pinmux_disable(struct pinctrl_dev *pctldev,
376                                         unsigned selector, unsigned group)
377 {
378         exynos5440_pinmux_setup(pctldev, selector, group, false);
379 }
380 
381 /*
382  * The calls to gpio_direction_output() and gpio_direction_input()
383  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
384  * function called from the gpiolib interface).
385  */
386 static int exynos5440_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
387                 struct pinctrl_gpio_range *range, unsigned offset, bool input)
388 {
389         return 0;
390 }
391 
392 /* list of pinmux callbacks for the pinmux vertical in pinctrl core */
393 static const struct pinmux_ops exynos5440_pinmux_ops = {
394         .get_functions_count    = exynos5440_get_functions_count,
395         .get_function_name      = exynos5440_pinmux_get_fname,
396         .get_function_groups    = exynos5440_pinmux_get_groups,
397         .enable                 = exynos5440_pinmux_enable,
398         .disable                = exynos5440_pinmux_disable,
399         .gpio_set_direction     = exynos5440_pinmux_gpio_set_direction,
400 };
401 
402 /* set the pin config settings for a specified pin */
403 static int exynos5440_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
404                                 unsigned long *configs,
405                                 unsigned num_configs)
406 {
407         struct exynos5440_pinctrl_priv_data *priv;
408         void __iomem *base;
409         enum pincfg_type cfg_type;
410         u32 cfg_value;
411         u32 data;
412         int i;
413 
414         priv = pinctrl_dev_get_drvdata(pctldev);
415         base = priv->reg_base;
416 
417         for (i = 0; i < num_configs; i++) {
418                 cfg_type = PINCFG_UNPACK_TYPE(configs[i]);
419                 cfg_value = PINCFG_UNPACK_VALUE(configs[i]);
420 
421                 switch (cfg_type) {
422                 case PINCFG_TYPE_PUD:
423                         /* first set pull enable/disable bit */
424                         data = readl(base + GPIO_PE);
425                         data &= ~(1 << pin);
426                         if (cfg_value)
427                                 data |= (1 << pin);
428                         writel(data, base + GPIO_PE);
429 
430                         /* then set pull up/down bit */
431                         data = readl(base + GPIO_PS);
432                         data &= ~(1 << pin);
433                         if (cfg_value == 2)
434                                 data |= (1 << pin);
435                         writel(data, base + GPIO_PS);
436                         break;
437 
438                 case PINCFG_TYPE_DRV:
439                         /* set the first bit of the drive strength */
440                         data = readl(base + GPIO_DS0);
441                         data &= ~(1 << pin);
442                         data |= ((cfg_value & 1) << pin);
443                         writel(data, base + GPIO_DS0);
444                         cfg_value >>= 1;
445 
446                         /* set the second bit of the driver strength */
447                         data = readl(base + GPIO_DS1);
448                         data &= ~(1 << pin);
449                         data |= ((cfg_value & 1) << pin);
450                         writel(data, base + GPIO_DS1);
451                         break;
452                 case PINCFG_TYPE_SKEW_RATE:
453                         data = readl(base + GPIO_SR);
454                         data &= ~(1 << pin);
455                         data |= ((cfg_value & 1) << pin);
456                         writel(data, base + GPIO_SR);
457                         break;
458                 case PINCFG_TYPE_INPUT_TYPE:
459                         data = readl(base + GPIO_TYPE);
460                         data &= ~(1 << pin);
461                         data |= ((cfg_value & 1) << pin);
462                         writel(data, base + GPIO_TYPE);
463                         break;
464                 default:
465                         WARN_ON(1);
466                         return -EINVAL;
467                 }
468         } /* for each config */
469 
470         return 0;
471 }
472 
473 /* get the pin config settings for a specified pin */
474 static int exynos5440_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
475                                         unsigned long *config)
476 {
477         struct exynos5440_pinctrl_priv_data *priv;
478         void __iomem *base;
479         enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(*config);
480         u32 data;
481 
482         priv = pinctrl_dev_get_drvdata(pctldev);
483         base = priv->reg_base;
484 
485         switch (cfg_type) {
486         case PINCFG_TYPE_PUD:
487                 data = readl(base + GPIO_PE);
488                 data = (data >> pin) & 1;
489                 if (!data)
490                         *config = 0;
491                 else
492                         *config = ((readl(base + GPIO_PS) >> pin) & 1) + 1;
493                 break;
494         case PINCFG_TYPE_DRV:
495                 data = readl(base + GPIO_DS0);
496                 data = (data >> pin) & 1;
497                 *config = data;
498                 data = readl(base + GPIO_DS1);
499                 data = (data >> pin) & 1;
500                 *config |= (data << 1);
501                 break;
502         case PINCFG_TYPE_SKEW_RATE:
503                 data = readl(base + GPIO_SR);
504                 *config = (data >> pin) & 1;
505                 break;
506         case PINCFG_TYPE_INPUT_TYPE:
507                 data = readl(base + GPIO_TYPE);
508                 *config = (data >> pin) & 1;
509                 break;
510         default:
511                 WARN_ON(1);
512                 return -EINVAL;
513         }
514 
515         return 0;
516 }
517 
518 /* set the pin config settings for a specified pin group */
519 static int exynos5440_pinconf_group_set(struct pinctrl_dev *pctldev,
520                         unsigned group, unsigned long *configs,
521                         unsigned num_configs)
522 {
523         struct exynos5440_pinctrl_priv_data *priv;
524         const unsigned int *pins;
525         unsigned int cnt;
526 
527         priv = pinctrl_dev_get_drvdata(pctldev);
528         pins = priv->pin_groups[group].pins;
529 
530         for (cnt = 0; cnt < priv->pin_groups[group].num_pins; cnt++)
531                 exynos5440_pinconf_set(pctldev, pins[cnt], configs,
532                                        num_configs);
533 
534         return 0;
535 }
536 
537 /* get the pin config settings for a specified pin group */
538 static int exynos5440_pinconf_group_get(struct pinctrl_dev *pctldev,
539                                 unsigned int group, unsigned long *config)
540 {
541         struct exynos5440_pinctrl_priv_data *priv;
542         const unsigned int *pins;
543 
544         priv = pinctrl_dev_get_drvdata(pctldev);
545         pins = priv->pin_groups[group].pins;
546         exynos5440_pinconf_get(pctldev, pins[0], config);
547         return 0;
548 }
549 
550 /* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */
551 static const struct pinconf_ops exynos5440_pinconf_ops = {
552         .pin_config_get         = exynos5440_pinconf_get,
553         .pin_config_set         = exynos5440_pinconf_set,
554         .pin_config_group_get   = exynos5440_pinconf_group_get,
555         .pin_config_group_set   = exynos5440_pinconf_group_set,
556 };
557 
558 /* gpiolib gpio_set callback function */
559 static void exynos5440_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
560 {
561         struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
562         void __iomem *base = priv->reg_base;
563         u32 data;
564 
565         data = readl(base + GPIO_VAL);
566         data &= ~(1 << offset);
567         if (value)
568                 data |= 1 << offset;
569         writel(data, base + GPIO_VAL);
570 }
571 
572 /* gpiolib gpio_get callback function */
573 static int exynos5440_gpio_get(struct gpio_chip *gc, unsigned offset)
574 {
575         struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
576         void __iomem *base = priv->reg_base;
577         u32 data;
578 
579         data = readl(base + GPIO_IN);
580         data >>= offset;
581         data &= 1;
582         return data;
583 }
584 
585 /* gpiolib gpio_direction_input callback function */
586 static int exynos5440_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
587 {
588         struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
589         void __iomem *base = priv->reg_base;
590         u32 data;
591 
592         /* first disable the data output enable on this pin */
593         data = readl(base + GPIO_OE);
594         data &= ~(1 << offset);
595         writel(data, base + GPIO_OE);
596 
597         /* now enable input on this pin */
598         data =  readl(base + GPIO_IE);
599         data |= 1 << offset;
600         writel(data, base + GPIO_IE);
601         return 0;
602 }
603 
604 /* gpiolib gpio_direction_output callback function */
605 static int exynos5440_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
606                                                         int value)
607 {
608         struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
609         void __iomem *base = priv->reg_base;
610         u32 data;
611 
612         exynos5440_gpio_set(gc, offset, value);
613 
614         /* first disable the data input enable on this pin */
615         data = readl(base + GPIO_IE);
616         data &= ~(1 << offset);
617         writel(data, base + GPIO_IE);
618 
619         /* now enable output on this pin */
620         data =  readl(base + GPIO_OE);
621         data |= 1 << offset;
622         writel(data, base + GPIO_OE);
623         return 0;
624 }
625 
626 /* gpiolib gpio_to_irq callback function */
627 static int exynos5440_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
628 {
629         struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
630         unsigned int virq;
631 
632         if (offset < 16 || offset > 23)
633                 return -ENXIO;
634 
635         if (!priv->irq_domain)
636                 return -ENXIO;
637 
638         virq = irq_create_mapping(priv->irq_domain, offset - 16);
639         return virq ? : -ENXIO;
640 }
641 
642 /* parse the pin numbers listed in the 'samsung,exynos5440-pins' property */
643 static int exynos5440_pinctrl_parse_dt_pins(struct platform_device *pdev,
644                         struct device_node *cfg_np, unsigned int **pin_list,
645                         unsigned int *npins)
646 {
647         struct device *dev = &pdev->dev;
648         struct property *prop;
649 
650         prop = of_find_property(cfg_np, "samsung,exynos5440-pins", NULL);
651         if (!prop)
652                 return -ENOENT;
653 
654         *npins = prop->length / sizeof(unsigned long);
655         if (!*npins) {
656                 dev_err(dev, "invalid pin list in %s node", cfg_np->name);
657                 return -EINVAL;
658         }
659 
660         *pin_list = devm_kzalloc(dev, *npins * sizeof(**pin_list), GFP_KERNEL);
661         if (!*pin_list) {
662                 dev_err(dev, "failed to allocate memory for pin list\n");
663                 return -ENOMEM;
664         }
665 
666         return of_property_read_u32_array(cfg_np, "samsung,exynos5440-pins",
667                         *pin_list, *npins);
668 }
669 
670 /*
671  * Parse the information about all the available pin groups and pin functions
672  * from device node of the pin-controller.
673  */
674 static int exynos5440_pinctrl_parse_dt(struct platform_device *pdev,
675                                 struct exynos5440_pinctrl_priv_data *priv)
676 {
677         struct device *dev = &pdev->dev;
678         struct device_node *dev_np = dev->of_node;
679         struct device_node *cfg_np;
680         struct exynos5440_pin_group *groups, *grp;
681         struct exynos5440_pmx_func *functions, *func;
682         unsigned *pin_list;
683         unsigned int npins, grp_cnt, func_idx = 0;
684         char *gname, *fname;
685         int ret;
686 
687         grp_cnt = of_get_child_count(dev_np);
688         if (!grp_cnt)
689                 return -EINVAL;
690 
691         groups = devm_kzalloc(dev, grp_cnt * sizeof(*groups), GFP_KERNEL);
692         if (!groups) {
693                 dev_err(dev, "failed allocate memory for ping group list\n");
694                 return -EINVAL;
695         }
696         grp = groups;
697 
698         functions = devm_kzalloc(dev, grp_cnt * sizeof(*functions), GFP_KERNEL);
699         if (!functions) {
700                 dev_err(dev, "failed to allocate memory for function list\n");
701                 return -EINVAL;
702         }
703         func = functions;
704 
705         /*
706          * Iterate over all the child nodes of the pin controller node
707          * and create pin groups and pin function lists.
708          */
709         for_each_child_of_node(dev_np, cfg_np) {
710                 u32 function;
711 
712                 ret = exynos5440_pinctrl_parse_dt_pins(pdev, cfg_np,
713                                         &pin_list, &npins);
714                 if (ret) {
715                         gname = NULL;
716                         goto skip_to_pin_function;
717                 }
718 
719                 /* derive pin group name from the node name */
720                 gname = devm_kzalloc(dev, strlen(cfg_np->name) + GSUFFIX_LEN,
721                                         GFP_KERNEL);
722                 if (!gname) {
723                         dev_err(dev, "failed to alloc memory for group name\n");
724                         return -ENOMEM;
725                 }
726                 snprintf(gname, strlen(cfg_np->name) + 4, "%s%s", cfg_np->name,
727                          GROUP_SUFFIX);
728 
729                 grp->name = gname;
730                 grp->pins = pin_list;
731                 grp->num_pins = npins;
732                 grp++;
733 
734 skip_to_pin_function:
735                 ret = of_property_read_u32(cfg_np, "samsung,exynos5440-pin-function",
736                                                 &function);
737                 if (ret)
738                         continue;
739 
740                 /* derive function name from the node name */
741                 fname = devm_kzalloc(dev, strlen(cfg_np->name) + FSUFFIX_LEN,
742                                         GFP_KERNEL);
743                 if (!fname) {
744                         dev_err(dev, "failed to alloc memory for func name\n");
745                         return -ENOMEM;
746                 }
747                 snprintf(fname, strlen(cfg_np->name) + 4, "%s%s", cfg_np->name,
748                          FUNCTION_SUFFIX);
749 
750                 func->name = fname;
751                 func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
752                 if (!func->groups) {
753                         dev_err(dev, "failed to alloc memory for group list "
754                                         "in pin function");
755                         return -ENOMEM;
756                 }
757                 func->groups[0] = gname;
758                 func->num_groups = gname ? 1 : 0;
759                 func->function = function;
760                 func++;
761                 func_idx++;
762         }
763 
764         priv->pin_groups = groups;
765         priv->nr_groups = grp_cnt;
766         priv->pmx_functions = functions;
767         priv->nr_functions = func_idx;
768         return 0;
769 }
770 
771 /* register the pinctrl interface with the pinctrl subsystem */
772 static int exynos5440_pinctrl_register(struct platform_device *pdev,
773                                 struct exynos5440_pinctrl_priv_data *priv)
774 {
775         struct device *dev = &pdev->dev;
776         struct pinctrl_desc *ctrldesc;
777         struct pinctrl_dev *pctl_dev;
778         struct pinctrl_pin_desc *pindesc, *pdesc;
779         struct pinctrl_gpio_range grange;
780         char *pin_names;
781         int pin, ret;
782 
783         ctrldesc = devm_kzalloc(dev, sizeof(*ctrldesc), GFP_KERNEL);
784         if (!ctrldesc) {
785                 dev_err(dev, "could not allocate memory for pinctrl desc\n");
786                 return -ENOMEM;
787         }
788 
789         ctrldesc->name = "exynos5440-pinctrl";
790         ctrldesc->owner = THIS_MODULE;
791         ctrldesc->pctlops = &exynos5440_pctrl_ops;
792         ctrldesc->pmxops = &exynos5440_pinmux_ops;
793         ctrldesc->confops = &exynos5440_pinconf_ops;
794 
795         pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
796                                 EXYNOS5440_MAX_PINS, GFP_KERNEL);
797         if (!pindesc) {
798                 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
799                 return -ENOMEM;
800         }
801         ctrldesc->pins = pindesc;
802         ctrldesc->npins = EXYNOS5440_MAX_PINS;
803 
804         /* dynamically populate the pin number and pin name for pindesc */
805         for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++)
806                 pdesc->number = pin;
807 
808         /*
809          * allocate space for storing the dynamically generated names for all
810          * the pins which belong to this pin-controller.
811          */
812         pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH *
813                                         ctrldesc->npins, GFP_KERNEL);
814         if (!pin_names) {
815                 dev_err(&pdev->dev, "mem alloc for pin names failed\n");
816                 return -ENOMEM;
817         }
818 
819         /* for each pin, set the name of the pin */
820         for (pin = 0; pin < ctrldesc->npins; pin++) {
821                 snprintf(pin_names, 6, "gpio%02d", pin);
822                 pdesc = pindesc + pin;
823                 pdesc->name = pin_names;
824                 pin_names += PIN_NAME_LENGTH;
825         }
826 
827         ret = exynos5440_pinctrl_parse_dt(pdev, priv);
828         if (ret)
829                 return ret;
830 
831         pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, priv);
832         if (!pctl_dev) {
833                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
834                 return -EINVAL;
835         }
836 
837         grange.name = "exynos5440-pctrl-gpio-range";
838         grange.id = 0;
839         grange.base = 0;
840         grange.npins = EXYNOS5440_MAX_PINS;
841         grange.gc = priv->gc;
842         pinctrl_add_gpio_range(pctl_dev, &grange);
843         return 0;
844 }
845 
846 /* register the gpiolib interface with the gpiolib subsystem */
847 static int exynos5440_gpiolib_register(struct platform_device *pdev,
848                                 struct exynos5440_pinctrl_priv_data *priv)
849 {
850         struct gpio_chip *gc;
851         int ret;
852 
853         gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
854         if (!gc) {
855                 dev_err(&pdev->dev, "mem alloc for gpio_chip failed\n");
856                 return -ENOMEM;
857         }
858 
859         priv->gc = gc;
860         gc->base = 0;
861         gc->ngpio = EXYNOS5440_MAX_PINS;
862         gc->dev = &pdev->dev;
863         gc->set = exynos5440_gpio_set;
864         gc->get = exynos5440_gpio_get;
865         gc->direction_input = exynos5440_gpio_direction_input;
866         gc->direction_output = exynos5440_gpio_direction_output;
867         gc->to_irq = exynos5440_gpio_to_irq;
868         gc->label = "gpiolib-exynos5440";
869         gc->owner = THIS_MODULE;
870         ret = gpiochip_add(gc);
871         if (ret) {
872                 dev_err(&pdev->dev, "failed to register gpio_chip %s, error "
873                                         "code: %d\n", gc->label, ret);
874                 return ret;
875         }
876 
877         return 0;
878 }
879 
880 /* unregister the gpiolib interface with the gpiolib subsystem */
881 static int exynos5440_gpiolib_unregister(struct platform_device *pdev,
882                                 struct exynos5440_pinctrl_priv_data *priv)
883 {
884         int ret = gpiochip_remove(priv->gc);
885         if (ret) {
886                 dev_err(&pdev->dev, "gpio chip remove failed\n");
887                 return ret;
888         }
889         return 0;
890 }
891 
892 static void exynos5440_gpio_irq_unmask(struct irq_data *irqd)
893 {
894         struct exynos5440_pinctrl_priv_data *d;
895         unsigned long gpio_int;
896 
897         d = irq_data_get_irq_chip_data(irqd);
898         gpio_int = readl(d->reg_base + GPIO_INT);
899         gpio_int |= 1 << irqd->hwirq;
900         writel(gpio_int, d->reg_base + GPIO_INT);
901 }
902 
903 static void exynos5440_gpio_irq_mask(struct irq_data *irqd)
904 {
905         struct exynos5440_pinctrl_priv_data *d;
906         unsigned long gpio_int;
907 
908         d = irq_data_get_irq_chip_data(irqd);
909         gpio_int = readl(d->reg_base + GPIO_INT);
910         gpio_int &= ~(1 << irqd->hwirq);
911         writel(gpio_int, d->reg_base + GPIO_INT);
912 }
913 
914 /* irq_chip for gpio interrupts */
915 static struct irq_chip exynos5440_gpio_irq_chip = {
916         .name           = "exynos5440_gpio_irq_chip",
917         .irq_unmask     = exynos5440_gpio_irq_unmask,
918         .irq_mask       = exynos5440_gpio_irq_mask,
919 };
920 
921 /* interrupt handler for GPIO interrupts 0..7 */
922 static irqreturn_t exynos5440_gpio_irq(int irq, void *data)
923 {
924         struct exynos5440_gpio_intr_data *intd = data;
925         struct exynos5440_pinctrl_priv_data *d = intd->priv;
926         int virq;
927 
928         virq = irq_linear_revmap(d->irq_domain, intd->gpio_int);
929         if (!virq)
930                 return IRQ_NONE;
931         generic_handle_irq(virq);
932         return IRQ_HANDLED;
933 }
934 
935 static int exynos5440_gpio_irq_map(struct irq_domain *h, unsigned int virq,
936                                         irq_hw_number_t hw)
937 {
938         struct exynos5440_pinctrl_priv_data *d = h->host_data;
939 
940         irq_set_chip_data(virq, d);
941         irq_set_chip_and_handler(virq, &exynos5440_gpio_irq_chip,
942                                         handle_level_irq);
943         set_irq_flags(virq, IRQF_VALID);
944         return 0;
945 }
946 
947 /* irq domain callbacks for gpio interrupt controller */
948 static const struct irq_domain_ops exynos5440_gpio_irqd_ops = {
949         .map    = exynos5440_gpio_irq_map,
950         .xlate  = irq_domain_xlate_twocell,
951 };
952 
953 /* setup handling of gpio interrupts */
954 static int exynos5440_gpio_irq_init(struct platform_device *pdev,
955                                 struct exynos5440_pinctrl_priv_data *priv)
956 {
957         struct device *dev = &pdev->dev;
958         struct exynos5440_gpio_intr_data *intd;
959         int i, irq, ret;
960 
961         intd = devm_kzalloc(dev, sizeof(*intd) * EXYNOS5440_MAX_GPIO_INT,
962                                         GFP_KERNEL);
963         if (!intd) {
964                 dev_err(dev, "failed to allocate memory for gpio intr data\n");
965                 return -ENOMEM;
966         }
967 
968         for (i = 0; i < EXYNOS5440_MAX_GPIO_INT; i++) {
969                 irq = irq_of_parse_and_map(dev->of_node, i);
970                 if (irq <= 0) {
971                         dev_err(dev, "irq parsing failed\n");
972                         return -EINVAL;
973                 }
974 
975                 intd->gpio_int = i;
976                 intd->priv = priv;
977                 ret = devm_request_irq(dev, irq, exynos5440_gpio_irq,
978                                         0, dev_name(dev), intd++);
979                 if (ret) {
980                         dev_err(dev, "irq request failed\n");
981                         return -ENXIO;
982                 }
983         }
984 
985         priv->irq_domain = irq_domain_add_linear(dev->of_node,
986                                 EXYNOS5440_MAX_GPIO_INT,
987                                 &exynos5440_gpio_irqd_ops, priv);
988         if (!priv->irq_domain) {
989                 dev_err(dev, "failed to create irq domain\n");
990                 return -ENXIO;
991         }
992 
993         return 0;
994 }
995 
996 static int exynos5440_pinctrl_probe(struct platform_device *pdev)
997 {
998         struct device *dev = &pdev->dev;
999         struct exynos5440_pinctrl_priv_data *priv;
1000         struct resource *res;
1001         int ret;
1002 
1003         if (!dev->of_node) {
1004                 dev_err(dev, "device tree node not found\n");
1005                 return -ENODEV;
1006         }
1007 
1008         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1009         if (!priv) {
1010                 dev_err(dev, "could not allocate memory for private data\n");
1011                 return -ENOMEM;
1012         }
1013 
1014         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1015         priv->reg_base = devm_ioremap_resource(&pdev->dev, res);
1016         if (IS_ERR(priv->reg_base))
1017                 return PTR_ERR(priv->reg_base);
1018 
1019         ret = exynos5440_gpiolib_register(pdev, priv);
1020         if (ret)
1021                 return ret;
1022 
1023         ret = exynos5440_pinctrl_register(pdev, priv);
1024         if (ret) {
1025                 exynos5440_gpiolib_unregister(pdev, priv);
1026                 return ret;
1027         }
1028 
1029         ret = exynos5440_gpio_irq_init(pdev, priv);
1030         if (ret) {
1031                 dev_err(dev, "failed to setup gpio interrupts\n");
1032                 return ret;
1033         }
1034 
1035         platform_set_drvdata(pdev, priv);
1036         dev_info(dev, "EXYNOS5440 pinctrl driver registered\n");
1037         return 0;
1038 }
1039 
1040 static const struct of_device_id exynos5440_pinctrl_dt_match[] = {
1041         { .compatible = "samsung,exynos5440-pinctrl" },
1042         {},
1043 };
1044 MODULE_DEVICE_TABLE(of, exynos5440_pinctrl_dt_match);
1045 
1046 static struct platform_driver exynos5440_pinctrl_driver = {
1047         .probe          = exynos5440_pinctrl_probe,
1048         .driver = {
1049                 .name   = "exynos5440-pinctrl",
1050                 .owner  = THIS_MODULE,
1051                 .of_match_table = exynos5440_pinctrl_dt_match,
1052         },
1053 };
1054 
1055 static int __init exynos5440_pinctrl_drv_register(void)
1056 {
1057         return platform_driver_register(&exynos5440_pinctrl_driver);
1058 }
1059 postcore_initcall(exynos5440_pinctrl_drv_register);
1060 
1061 static void __exit exynos5440_pinctrl_drv_unregister(void)
1062 {
1063         platform_driver_unregister(&exynos5440_pinctrl_driver);
1064 }
1065 module_exit(exynos5440_pinctrl_drv_unregister);
1066 
1067 MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
1068 MODULE_DESCRIPTION("Samsung EXYNOS5440 SoC pinctrl driver");
1069 MODULE_LICENSE("GPL v2");
1070 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us