Version:  2.0.40 2.2.26 2.4.37 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1

Linux/drivers/pinctrl/pinctrl-at91.c

  1 /*
  2  * at91 pinctrl driver based on at91 pinmux core
  3  *
  4  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  5  *
  6  * Under GPLv2 only
  7  */
  8 
  9 #include <linux/clk.h>
 10 #include <linux/err.h>
 11 #include <linux/init.h>
 12 #include <linux/module.h>
 13 #include <linux/of.h>
 14 #include <linux/of_device.h>
 15 #include <linux/of_address.h>
 16 #include <linux/of_irq.h>
 17 #include <linux/slab.h>
 18 #include <linux/interrupt.h>
 19 #include <linux/io.h>
 20 #include <linux/gpio.h>
 21 #include <linux/pinctrl/machine.h>
 22 #include <linux/pinctrl/pinconf.h>
 23 #include <linux/pinctrl/pinctrl.h>
 24 #include <linux/pinctrl/pinmux.h>
 25 /* Since we request GPIOs from ourself */
 26 #include <linux/pinctrl/consumer.h>
 27 
 28 #include "pinctrl-at91.h"
 29 #include "core.h"
 30 
 31 #define MAX_GPIO_BANKS          5
 32 #define MAX_NB_GPIO_PER_BANK    32
 33 
 34 struct at91_pinctrl_mux_ops;
 35 
 36 struct at91_gpio_chip {
 37         struct gpio_chip        chip;
 38         struct pinctrl_gpio_range range;
 39         struct at91_gpio_chip   *next;          /* Bank sharing same clock */
 40         int                     pioc_hwirq;     /* PIO bank interrupt identifier on AIC */
 41         int                     pioc_virq;      /* PIO bank Linux virtual interrupt */
 42         int                     pioc_idx;       /* PIO bank index */
 43         void __iomem            *regbase;       /* PIO bank virtual address */
 44         struct clk              *clock;         /* associated clock */
 45         struct at91_pinctrl_mux_ops *ops;       /* ops */
 46 };
 47 
 48 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
 49 
 50 static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
 51 
 52 static int gpio_banks;
 53 
 54 #define PULL_UP         (1 << 0)
 55 #define MULTI_DRIVE     (1 << 1)
 56 #define DEGLITCH        (1 << 2)
 57 #define PULL_DOWN       (1 << 3)
 58 #define DIS_SCHMIT      (1 << 4)
 59 #define DRIVE_STRENGTH_SHIFT    5
 60 #define DRIVE_STRENGTH_MASK             0x3
 61 #define DRIVE_STRENGTH   (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
 62 #define DEBOUNCE        (1 << 16)
 63 #define DEBOUNCE_VAL_SHIFT      17
 64 #define DEBOUNCE_VAL    (0x3fff << DEBOUNCE_VAL_SHIFT)
 65 
 66 /**
 67  * These defines will translated the dt binding settings to our internal
 68  * settings. They are not necessarily the same value as the register setting.
 69  * The actual drive strength current of low, medium and high must be looked up
 70  * from the corresponding device datasheet. This value is different for pins
 71  * that are even in the same banks. It is also dependent on VCC.
 72  * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
 73  * strength when there is no dt config for it.
 74  */
 75 #define DRIVE_STRENGTH_DEFAULT          (0 << DRIVE_STRENGTH_SHIFT)
 76 #define DRIVE_STRENGTH_LOW          (1 << DRIVE_STRENGTH_SHIFT)
 77 #define DRIVE_STRENGTH_MED          (2 << DRIVE_STRENGTH_SHIFT)
 78 #define DRIVE_STRENGTH_HI           (3 << DRIVE_STRENGTH_SHIFT)
 79 
 80 /**
 81  * struct at91_pmx_func - describes AT91 pinmux functions
 82  * @name: the name of this specific function
 83  * @groups: corresponding pin groups
 84  * @ngroups: the number of groups
 85  */
 86 struct at91_pmx_func {
 87         const char      *name;
 88         const char      **groups;
 89         unsigned        ngroups;
 90 };
 91 
 92 enum at91_mux {
 93         AT91_MUX_GPIO = 0,
 94         AT91_MUX_PERIPH_A = 1,
 95         AT91_MUX_PERIPH_B = 2,
 96         AT91_MUX_PERIPH_C = 3,
 97         AT91_MUX_PERIPH_D = 4,
 98 };
 99 
100 /**
101  * struct at91_pmx_pin - describes an At91 pin mux
102  * @bank: the bank of the pin
103  * @pin: the pin number in the @bank
104  * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
105  * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
106  */
107 struct at91_pmx_pin {
108         uint32_t        bank;
109         uint32_t        pin;
110         enum at91_mux   mux;
111         unsigned long   conf;
112 };
113 
114 /**
115  * struct at91_pin_group - describes an At91 pin group
116  * @name: the name of this specific pin group
117  * @pins_conf: the mux mode for each pin in this group. The size of this
118  *      array is the same as pins.
119  * @pins: an array of discrete physical pins used in this group, taken
120  *      from the driver-local pin enumeration space
121  * @npins: the number of pins in this group array, i.e. the number of
122  *      elements in .pins so we can iterate over that array
123  */
124 struct at91_pin_group {
125         const char              *name;
126         struct at91_pmx_pin     *pins_conf;
127         unsigned int            *pins;
128         unsigned                npins;
129 };
130 
131 /**
132  * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
133  * on new IP with support for periph C and D the way to mux in
134  * periph A and B has changed
135  * So provide the right call back
136  * if not present means the IP does not support it
137  * @get_periph: return the periph mode configured
138  * @mux_A_periph: mux as periph A
139  * @mux_B_periph: mux as periph B
140  * @mux_C_periph: mux as periph C
141  * @mux_D_periph: mux as periph D
142  * @get_deglitch: get deglitch status
143  * @set_deglitch: enable/disable deglitch
144  * @get_debounce: get debounce status
145  * @set_debounce: enable/disable debounce
146  * @get_pulldown: get pulldown status
147  * @set_pulldown: enable/disable pulldown
148  * @get_schmitt_trig: get schmitt trigger status
149  * @disable_schmitt_trig: disable schmitt trigger
150  * @irq_type: return irq type
151  */
152 struct at91_pinctrl_mux_ops {
153         enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
154         void (*mux_A_periph)(void __iomem *pio, unsigned mask);
155         void (*mux_B_periph)(void __iomem *pio, unsigned mask);
156         void (*mux_C_periph)(void __iomem *pio, unsigned mask);
157         void (*mux_D_periph)(void __iomem *pio, unsigned mask);
158         bool (*get_deglitch)(void __iomem *pio, unsigned pin);
159         void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
160         bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
161         void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
162         bool (*get_pulldown)(void __iomem *pio, unsigned pin);
163         void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
164         bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
165         void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
166         unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
167         void (*set_drivestrength)(void __iomem *pio, unsigned pin,
168                                         u32 strength);
169         /* irq */
170         int (*irq_type)(struct irq_data *d, unsigned type);
171 };
172 
173 static int gpio_irq_type(struct irq_data *d, unsigned type);
174 static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
175 
176 struct at91_pinctrl {
177         struct device           *dev;
178         struct pinctrl_dev      *pctl;
179 
180         int                     nactive_banks;
181 
182         uint32_t                *mux_mask;
183         int                     nmux;
184 
185         struct at91_pmx_func    *functions;
186         int                     nfunctions;
187 
188         struct at91_pin_group   *groups;
189         int                     ngroups;
190 
191         struct at91_pinctrl_mux_ops *ops;
192 };
193 
194 static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name(
195                                 const struct at91_pinctrl *info,
196                                 const char *name)
197 {
198         const struct at91_pin_group *grp = NULL;
199         int i;
200 
201         for (i = 0; i < info->ngroups; i++) {
202                 if (strcmp(info->groups[i].name, name))
203                         continue;
204 
205                 grp = &info->groups[i];
206                 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
207                 break;
208         }
209 
210         return grp;
211 }
212 
213 static int at91_get_groups_count(struct pinctrl_dev *pctldev)
214 {
215         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
216 
217         return info->ngroups;
218 }
219 
220 static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
221                                        unsigned selector)
222 {
223         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
224 
225         return info->groups[selector].name;
226 }
227 
228 static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
229                                const unsigned **pins,
230                                unsigned *npins)
231 {
232         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
233 
234         if (selector >= info->ngroups)
235                 return -EINVAL;
236 
237         *pins = info->groups[selector].pins;
238         *npins = info->groups[selector].npins;
239 
240         return 0;
241 }
242 
243 static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
244                    unsigned offset)
245 {
246         seq_printf(s, "%s", dev_name(pctldev->dev));
247 }
248 
249 static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
250                         struct device_node *np,
251                         struct pinctrl_map **map, unsigned *num_maps)
252 {
253         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
254         const struct at91_pin_group *grp;
255         struct pinctrl_map *new_map;
256         struct device_node *parent;
257         int map_num = 1;
258         int i;
259 
260         /*
261          * first find the group of this node and check if we need to create
262          * config maps for pins
263          */
264         grp = at91_pinctrl_find_group_by_name(info, np->name);
265         if (!grp) {
266                 dev_err(info->dev, "unable to find group for node %s\n",
267                         np->name);
268                 return -EINVAL;
269         }
270 
271         map_num += grp->npins;
272         new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL);
273         if (!new_map)
274                 return -ENOMEM;
275 
276         *map = new_map;
277         *num_maps = map_num;
278 
279         /* create mux map */
280         parent = of_get_parent(np);
281         if (!parent) {
282                 devm_kfree(pctldev->dev, new_map);
283                 return -EINVAL;
284         }
285         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
286         new_map[0].data.mux.function = parent->name;
287         new_map[0].data.mux.group = np->name;
288         of_node_put(parent);
289 
290         /* create config map */
291         new_map++;
292         for (i = 0; i < grp->npins; i++) {
293                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
294                 new_map[i].data.configs.group_or_pin =
295                                 pin_get_name(pctldev, grp->pins[i]);
296                 new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
297                 new_map[i].data.configs.num_configs = 1;
298         }
299 
300         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
301                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
302 
303         return 0;
304 }
305 
306 static void at91_dt_free_map(struct pinctrl_dev *pctldev,
307                                 struct pinctrl_map *map, unsigned num_maps)
308 {
309 }
310 
311 static const struct pinctrl_ops at91_pctrl_ops = {
312         .get_groups_count       = at91_get_groups_count,
313         .get_group_name         = at91_get_group_name,
314         .get_group_pins         = at91_get_group_pins,
315         .pin_dbg_show           = at91_pin_dbg_show,
316         .dt_node_to_map         = at91_dt_node_to_map,
317         .dt_free_map            = at91_dt_free_map,
318 };
319 
320 static void __iomem *pin_to_controller(struct at91_pinctrl *info,
321                                  unsigned int bank)
322 {
323         return gpio_chips[bank]->regbase;
324 }
325 
326 static inline int pin_to_bank(unsigned pin)
327 {
328         return pin /= MAX_NB_GPIO_PER_BANK;
329 }
330 
331 static unsigned pin_to_mask(unsigned int pin)
332 {
333         return 1 << pin;
334 }
335 
336 static unsigned two_bit_pin_value_shift_amount(unsigned int pin)
337 {
338         /* return the shift value for a pin for "two bit" per pin registers,
339          * i.e. drive strength */
340         return 2*((pin >= MAX_NB_GPIO_PER_BANK/2)
341                         ? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
342 }
343 
344 static unsigned sama5d3_get_drive_register(unsigned int pin)
345 {
346         /* drive strength is split between two registers
347          * with two bits per pin */
348         return (pin >= MAX_NB_GPIO_PER_BANK/2)
349                         ? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1;
350 }
351 
352 static unsigned at91sam9x5_get_drive_register(unsigned int pin)
353 {
354         /* drive strength is split between two registers
355          * with two bits per pin */
356         return (pin >= MAX_NB_GPIO_PER_BANK/2)
357                         ? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1;
358 }
359 
360 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
361 {
362         writel_relaxed(mask, pio + PIO_IDR);
363 }
364 
365 static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
366 {
367         return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1);
368 }
369 
370 static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
371 {
372         if (on)
373                 writel_relaxed(mask, pio + PIO_PPDDR);
374 
375         writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
376 }
377 
378 static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
379 {
380         return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
381 }
382 
383 static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
384 {
385         writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
386 }
387 
388 static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
389 {
390         writel_relaxed(mask, pio + PIO_ASR);
391 }
392 
393 static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
394 {
395         writel_relaxed(mask, pio + PIO_BSR);
396 }
397 
398 static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
399 {
400 
401         writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
402                                                 pio + PIO_ABCDSR1);
403         writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
404                                                 pio + PIO_ABCDSR2);
405 }
406 
407 static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
408 {
409         writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
410                                                 pio + PIO_ABCDSR1);
411         writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
412                                                 pio + PIO_ABCDSR2);
413 }
414 
415 static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
416 {
417         writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
418         writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
419 }
420 
421 static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
422 {
423         writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
424         writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
425 }
426 
427 static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
428 {
429         unsigned select;
430 
431         if (readl_relaxed(pio + PIO_PSR) & mask)
432                 return AT91_MUX_GPIO;
433 
434         select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
435         select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
436 
437         return select + 1;
438 }
439 
440 static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
441 {
442         unsigned select;
443 
444         if (readl_relaxed(pio + PIO_PSR) & mask)
445                 return AT91_MUX_GPIO;
446 
447         select = readl_relaxed(pio + PIO_ABSR) & mask;
448 
449         return select + 1;
450 }
451 
452 static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
453 {
454         return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1;
455 }
456 
457 static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
458 {
459         writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
460 }
461 
462 static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
463 {
464         if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1)
465                 return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
466 
467         return false;
468 }
469 
470 static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
471 {
472         if (is_on)
473                 writel_relaxed(mask, pio + PIO_IFSCDR);
474         at91_mux_set_deglitch(pio, mask, is_on);
475 }
476 
477 static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
478 {
479         *div = readl_relaxed(pio + PIO_SCDR);
480 
481         return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) &&
482                ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
483 }
484 
485 static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
486                                 bool is_on, u32 div)
487 {
488         if (is_on) {
489                 writel_relaxed(mask, pio + PIO_IFSCER);
490                 writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR);
491                 writel_relaxed(mask, pio + PIO_IFER);
492         } else
493                 writel_relaxed(mask, pio + PIO_IFSCDR);
494 }
495 
496 static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
497 {
498         return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1);
499 }
500 
501 static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
502 {
503         if (is_on)
504                 writel_relaxed(mask, pio + PIO_PUDR);
505 
506         writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
507 }
508 
509 static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
510 {
511         writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
512 }
513 
514 static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
515 {
516         return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1;
517 }
518 
519 static inline u32 read_drive_strength(void __iomem *reg, unsigned pin)
520 {
521         unsigned tmp = readl_relaxed(reg);
522 
523         tmp = tmp >> two_bit_pin_value_shift_amount(pin);
524 
525         return tmp & DRIVE_STRENGTH_MASK;
526 }
527 
528 static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
529                                                         unsigned pin)
530 {
531         unsigned tmp = read_drive_strength(pio +
532                                         sama5d3_get_drive_register(pin), pin);
533 
534         /* SAMA5 strength is 1:1 with our defines,
535          * except 0 is equivalent to low per datasheet */
536         if (!tmp)
537                 tmp = DRIVE_STRENGTH_LOW;
538 
539         return tmp;
540 }
541 
542 static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
543                                                         unsigned pin)
544 {
545         unsigned tmp = read_drive_strength(pio +
546                                 at91sam9x5_get_drive_register(pin), pin);
547 
548         /* strength is inverse in SAM9x5s hardware with the pinctrl defines
549          * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
550         tmp = DRIVE_STRENGTH_HI - tmp;
551 
552         return tmp;
553 }
554 
555 static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
556 {
557         unsigned tmp = readl_relaxed(reg);
558         unsigned shift = two_bit_pin_value_shift_amount(pin);
559 
560         tmp &= ~(DRIVE_STRENGTH_MASK  <<  shift);
561         tmp |= strength << shift;
562 
563         writel_relaxed(tmp, reg);
564 }
565 
566 static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin,
567                                                 u32 setting)
568 {
569         /* do nothing if setting is zero */
570         if (!setting)
571                 return;
572 
573         /* strength is 1 to 1 with setting for SAMA5 */
574         set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting);
575 }
576 
577 static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
578                                                 u32 setting)
579 {
580         /* do nothing if setting is zero */
581         if (!setting)
582                 return;
583 
584         /* strength is inverse on SAM9x5s with our defines
585          * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
586         setting = DRIVE_STRENGTH_HI - setting;
587 
588         set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
589                                 setting);
590 }
591 
592 static struct at91_pinctrl_mux_ops at91rm9200_ops = {
593         .get_periph     = at91_mux_get_periph,
594         .mux_A_periph   = at91_mux_set_A_periph,
595         .mux_B_periph   = at91_mux_set_B_periph,
596         .get_deglitch   = at91_mux_get_deglitch,
597         .set_deglitch   = at91_mux_set_deglitch,
598         .irq_type       = gpio_irq_type,
599 };
600 
601 static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
602         .get_periph     = at91_mux_pio3_get_periph,
603         .mux_A_periph   = at91_mux_pio3_set_A_periph,
604         .mux_B_periph   = at91_mux_pio3_set_B_periph,
605         .mux_C_periph   = at91_mux_pio3_set_C_periph,
606         .mux_D_periph   = at91_mux_pio3_set_D_periph,
607         .get_deglitch   = at91_mux_pio3_get_deglitch,
608         .set_deglitch   = at91_mux_pio3_set_deglitch,
609         .get_debounce   = at91_mux_pio3_get_debounce,
610         .set_debounce   = at91_mux_pio3_set_debounce,
611         .get_pulldown   = at91_mux_pio3_get_pulldown,
612         .set_pulldown   = at91_mux_pio3_set_pulldown,
613         .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
614         .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
615         .get_drivestrength = at91_mux_sam9x5_get_drivestrength,
616         .set_drivestrength = at91_mux_sam9x5_set_drivestrength,
617         .irq_type       = alt_gpio_irq_type,
618 };
619 
620 static struct at91_pinctrl_mux_ops sama5d3_ops = {
621         .get_periph     = at91_mux_pio3_get_periph,
622         .mux_A_periph   = at91_mux_pio3_set_A_periph,
623         .mux_B_periph   = at91_mux_pio3_set_B_periph,
624         .mux_C_periph   = at91_mux_pio3_set_C_periph,
625         .mux_D_periph   = at91_mux_pio3_set_D_periph,
626         .get_deglitch   = at91_mux_pio3_get_deglitch,
627         .set_deglitch   = at91_mux_pio3_set_deglitch,
628         .get_debounce   = at91_mux_pio3_get_debounce,
629         .set_debounce   = at91_mux_pio3_set_debounce,
630         .get_pulldown   = at91_mux_pio3_get_pulldown,
631         .set_pulldown   = at91_mux_pio3_set_pulldown,
632         .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
633         .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
634         .get_drivestrength = at91_mux_sama5d3_get_drivestrength,
635         .set_drivestrength = at91_mux_sama5d3_set_drivestrength,
636         .irq_type       = alt_gpio_irq_type,
637 };
638 
639 static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
640 {
641         if (pin->mux) {
642                 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n",
643                         pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
644         } else {
645                 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n",
646                         pin->bank + 'A', pin->pin, pin->conf);
647         }
648 }
649 
650 static int pin_check_config(struct at91_pinctrl *info, const char *name,
651                             int index, const struct at91_pmx_pin *pin)
652 {
653         int mux;
654 
655         /* check if it's a valid config */
656         if (pin->bank >= gpio_banks) {
657                 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
658                         name, index, pin->bank, gpio_banks);
659                 return -EINVAL;
660         }
661 
662         if (!gpio_chips[pin->bank]) {
663                 dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n",
664                         name, index, pin->bank);
665                 return -ENXIO;
666         }
667 
668         if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
669                 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
670                         name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
671                 return -EINVAL;
672         }
673 
674         if (!pin->mux)
675                 return 0;
676 
677         mux = pin->mux - 1;
678 
679         if (mux >= info->nmux) {
680                 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
681                         name, index, mux, info->nmux);
682                 return -EINVAL;
683         }
684 
685         if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
686                 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
687                         name, index, mux, pin->bank + 'A', pin->pin);
688                 return -EINVAL;
689         }
690 
691         return 0;
692 }
693 
694 static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
695 {
696         writel_relaxed(mask, pio + PIO_PDR);
697 }
698 
699 static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
700 {
701         writel_relaxed(mask, pio + PIO_PER);
702         writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
703 }
704 
705 static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
706                         unsigned group)
707 {
708         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
709         const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
710         const struct at91_pmx_pin *pin;
711         uint32_t npins = info->groups[group].npins;
712         int i, ret;
713         unsigned mask;
714         void __iomem *pio;
715 
716         dev_dbg(info->dev, "enable function %s group %s\n",
717                 info->functions[selector].name, info->groups[group].name);
718 
719         /* first check that all the pins of the group are valid with a valid
720          * parameter */
721         for (i = 0; i < npins; i++) {
722                 pin = &pins_conf[i];
723                 ret = pin_check_config(info, info->groups[group].name, i, pin);
724                 if (ret)
725                         return ret;
726         }
727 
728         for (i = 0; i < npins; i++) {
729                 pin = &pins_conf[i];
730                 at91_pin_dbg(info->dev, pin);
731                 pio = pin_to_controller(info, pin->bank);
732                 mask = pin_to_mask(pin->pin);
733                 at91_mux_disable_interrupt(pio, mask);
734                 switch (pin->mux) {
735                 case AT91_MUX_GPIO:
736                         at91_mux_gpio_enable(pio, mask, 1);
737                         break;
738                 case AT91_MUX_PERIPH_A:
739                         info->ops->mux_A_periph(pio, mask);
740                         break;
741                 case AT91_MUX_PERIPH_B:
742                         info->ops->mux_B_periph(pio, mask);
743                         break;
744                 case AT91_MUX_PERIPH_C:
745                         if (!info->ops->mux_C_periph)
746                                 return -EINVAL;
747                         info->ops->mux_C_periph(pio, mask);
748                         break;
749                 case AT91_MUX_PERIPH_D:
750                         if (!info->ops->mux_D_periph)
751                                 return -EINVAL;
752                         info->ops->mux_D_periph(pio, mask);
753                         break;
754                 }
755                 if (pin->mux)
756                         at91_mux_gpio_disable(pio, mask);
757         }
758 
759         return 0;
760 }
761 
762 static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
763 {
764         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
765 
766         return info->nfunctions;
767 }
768 
769 static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
770                                           unsigned selector)
771 {
772         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
773 
774         return info->functions[selector].name;
775 }
776 
777 static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
778                                const char * const **groups,
779                                unsigned * const num_groups)
780 {
781         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
782 
783         *groups = info->functions[selector].groups;
784         *num_groups = info->functions[selector].ngroups;
785 
786         return 0;
787 }
788 
789 static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
790                                     struct pinctrl_gpio_range *range,
791                                     unsigned offset)
792 {
793         struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
794         struct at91_gpio_chip *at91_chip;
795         struct gpio_chip *chip;
796         unsigned mask;
797 
798         if (!range) {
799                 dev_err(npct->dev, "invalid range\n");
800                 return -EINVAL;
801         }
802         if (!range->gc) {
803                 dev_err(npct->dev, "missing GPIO chip in range\n");
804                 return -EINVAL;
805         }
806         chip = range->gc;
807         at91_chip = container_of(chip, struct at91_gpio_chip, chip);
808 
809         dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
810 
811         mask = 1 << (offset - chip->base);
812 
813         dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
814                 offset, 'A' + range->id, offset - chip->base, mask);
815 
816         writel_relaxed(mask, at91_chip->regbase + PIO_PER);
817 
818         return 0;
819 }
820 
821 static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
822                                    struct pinctrl_gpio_range *range,
823                                    unsigned offset)
824 {
825         struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
826 
827         dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
828         /* Set the pin to some default state, GPIO is usually default */
829 }
830 
831 static const struct pinmux_ops at91_pmx_ops = {
832         .get_functions_count    = at91_pmx_get_funcs_count,
833         .get_function_name      = at91_pmx_get_func_name,
834         .get_function_groups    = at91_pmx_get_groups,
835         .set_mux                = at91_pmx_set,
836         .gpio_request_enable    = at91_gpio_request_enable,
837         .gpio_disable_free      = at91_gpio_disable_free,
838 };
839 
840 static int at91_pinconf_get(struct pinctrl_dev *pctldev,
841                              unsigned pin_id, unsigned long *config)
842 {
843         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
844         void __iomem *pio;
845         unsigned pin;
846         int div;
847 
848         *config = 0;
849         dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id);
850         pio = pin_to_controller(info, pin_to_bank(pin_id));
851         pin = pin_id % MAX_NB_GPIO_PER_BANK;
852 
853         if (at91_mux_get_multidrive(pio, pin))
854                 *config |= MULTI_DRIVE;
855 
856         if (at91_mux_get_pullup(pio, pin))
857                 *config |= PULL_UP;
858 
859         if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
860                 *config |= DEGLITCH;
861         if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
862                 *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
863         if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
864                 *config |= PULL_DOWN;
865         if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
866                 *config |= DIS_SCHMIT;
867         if (info->ops->get_drivestrength)
868                 *config |= (info->ops->get_drivestrength(pio, pin)
869                                 << DRIVE_STRENGTH_SHIFT);
870 
871         return 0;
872 }
873 
874 static int at91_pinconf_set(struct pinctrl_dev *pctldev,
875                              unsigned pin_id, unsigned long *configs,
876                              unsigned num_configs)
877 {
878         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
879         unsigned mask;
880         void __iomem *pio;
881         int i;
882         unsigned long config;
883         unsigned pin;
884 
885         for (i = 0; i < num_configs; i++) {
886                 config = configs[i];
887 
888                 dev_dbg(info->dev,
889                         "%s:%d, pin_id=%d, config=0x%lx",
890                         __func__, __LINE__, pin_id, config);
891                 pio = pin_to_controller(info, pin_to_bank(pin_id));
892                 pin = pin_id % MAX_NB_GPIO_PER_BANK;
893                 mask = pin_to_mask(pin);
894 
895                 if (config & PULL_UP && config & PULL_DOWN)
896                         return -EINVAL;
897 
898                 at91_mux_set_pullup(pio, mask, config & PULL_UP);
899                 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
900                 if (info->ops->set_deglitch)
901                         info->ops->set_deglitch(pio, mask, config & DEGLITCH);
902                 if (info->ops->set_debounce)
903                         info->ops->set_debounce(pio, mask, config & DEBOUNCE,
904                                 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
905                 if (info->ops->set_pulldown)
906                         info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
907                 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
908                         info->ops->disable_schmitt_trig(pio, mask);
909                 if (info->ops->set_drivestrength)
910                         info->ops->set_drivestrength(pio, pin,
911                                 (config & DRIVE_STRENGTH)
912                                         >> DRIVE_STRENGTH_SHIFT);
913 
914         } /* for each config */
915 
916         return 0;
917 }
918 
919 #define DBG_SHOW_FLAG(flag) do {                \
920         if (config & flag) {                    \
921                 if (num_conf)                   \
922                         seq_puts(s, "|");       \
923                 seq_puts(s, #flag);             \
924                 num_conf++;                     \
925         }                                       \
926 } while (0)
927 
928 #define DBG_SHOW_FLAG_MASKED(mask,flag) do {    \
929         if ((config & mask) == flag) {          \
930                 if (num_conf)                   \
931                         seq_puts(s, "|");       \
932                 seq_puts(s, #flag);             \
933                 num_conf++;                     \
934         }                                       \
935 } while (0)
936 
937 static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
938                                    struct seq_file *s, unsigned pin_id)
939 {
940         unsigned long config;
941         int val, num_conf = 0;
942 
943         at91_pinconf_get(pctldev, pin_id, &config);
944 
945         DBG_SHOW_FLAG(MULTI_DRIVE);
946         DBG_SHOW_FLAG(PULL_UP);
947         DBG_SHOW_FLAG(PULL_DOWN);
948         DBG_SHOW_FLAG(DIS_SCHMIT);
949         DBG_SHOW_FLAG(DEGLITCH);
950         DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
951         DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
952         DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
953         DBG_SHOW_FLAG(DEBOUNCE);
954         if (config & DEBOUNCE) {
955                 val = config >> DEBOUNCE_VAL_SHIFT;
956                 seq_printf(s, "(%d)", val);
957         }
958 
959         return;
960 }
961 
962 static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
963                                          struct seq_file *s, unsigned group)
964 {
965 }
966 
967 static const struct pinconf_ops at91_pinconf_ops = {
968         .pin_config_get                 = at91_pinconf_get,
969         .pin_config_set                 = at91_pinconf_set,
970         .pin_config_dbg_show            = at91_pinconf_dbg_show,
971         .pin_config_group_dbg_show      = at91_pinconf_group_dbg_show,
972 };
973 
974 static struct pinctrl_desc at91_pinctrl_desc = {
975         .pctlops        = &at91_pctrl_ops,
976         .pmxops         = &at91_pmx_ops,
977         .confops        = &at91_pinconf_ops,
978         .owner          = THIS_MODULE,
979 };
980 
981 static const char *gpio_compat = "atmel,at91rm9200-gpio";
982 
983 static void at91_pinctrl_child_count(struct at91_pinctrl *info,
984                                      struct device_node *np)
985 {
986         struct device_node *child;
987 
988         for_each_child_of_node(np, child) {
989                 if (of_device_is_compatible(child, gpio_compat)) {
990                         if (of_device_is_available(child))
991                                 info->nactive_banks++;
992                 } else {
993                         info->nfunctions++;
994                         info->ngroups += of_get_child_count(child);
995                 }
996         }
997 }
998 
999 static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
1000                                  struct device_node *np)
1001 {
1002         int ret = 0;
1003         int size;
1004         const __be32 *list;
1005 
1006         list = of_get_property(np, "atmel,mux-mask", &size);
1007         if (!list) {
1008                 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1009                 return -EINVAL;
1010         }
1011 
1012         size /= sizeof(*list);
1013         if (!size || size % gpio_banks) {
1014                 dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks);
1015                 return -EINVAL;
1016         }
1017         info->nmux = size / gpio_banks;
1018 
1019         info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);
1020         if (!info->mux_mask) {
1021                 dev_err(info->dev, "could not alloc mux_mask\n");
1022                 return -ENOMEM;
1023         }
1024 
1025         ret = of_property_read_u32_array(np, "atmel,mux-mask",
1026                                           info->mux_mask, size);
1027         if (ret)
1028                 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1029         return ret;
1030 }
1031 
1032 static int at91_pinctrl_parse_groups(struct device_node *np,
1033                                      struct at91_pin_group *grp,
1034                                      struct at91_pinctrl *info, u32 index)
1035 {
1036         struct at91_pmx_pin *pin;
1037         int size;
1038         const __be32 *list;
1039         int i, j;
1040 
1041         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1042 
1043         /* Initialise group */
1044         grp->name = np->name;
1045 
1046         /*
1047          * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
1048          * do sanity check and calculate pins number
1049          */
1050         list = of_get_property(np, "atmel,pins", &size);
1051         /* we do not check return since it's safe node passed down */
1052         size /= sizeof(*list);
1053         if (!size || size % 4) {
1054                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1055                 return -EINVAL;
1056         }
1057 
1058         grp->npins = size / 4;
1059         pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin),
1060                                 GFP_KERNEL);
1061         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1062                                 GFP_KERNEL);
1063         if (!grp->pins_conf || !grp->pins)
1064                 return -ENOMEM;
1065 
1066         for (i = 0, j = 0; i < size; i += 4, j++) {
1067                 pin->bank = be32_to_cpu(*list++);
1068                 pin->pin = be32_to_cpu(*list++);
1069                 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
1070                 pin->mux = be32_to_cpu(*list++);
1071                 pin->conf = be32_to_cpu(*list++);
1072 
1073                 at91_pin_dbg(info->dev, pin);
1074                 pin++;
1075         }
1076 
1077         return 0;
1078 }
1079 
1080 static int at91_pinctrl_parse_functions(struct device_node *np,
1081                                         struct at91_pinctrl *info, u32 index)
1082 {
1083         struct device_node *child;
1084         struct at91_pmx_func *func;
1085         struct at91_pin_group *grp;
1086         int ret;
1087         static u32 grp_index;
1088         u32 i = 0;
1089 
1090         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1091 
1092         func = &info->functions[index];
1093 
1094         /* Initialise function */
1095         func->name = np->name;
1096         func->ngroups = of_get_child_count(np);
1097         if (func->ngroups == 0) {
1098                 dev_err(info->dev, "no groups defined\n");
1099                 return -EINVAL;
1100         }
1101         func->groups = devm_kzalloc(info->dev,
1102                         func->ngroups * sizeof(char *), GFP_KERNEL);
1103         if (!func->groups)
1104                 return -ENOMEM;
1105 
1106         for_each_child_of_node(np, child) {
1107                 func->groups[i] = child->name;
1108                 grp = &info->groups[grp_index++];
1109                 ret = at91_pinctrl_parse_groups(child, grp, info, i++);
1110                 if (ret)
1111                         return ret;
1112         }
1113 
1114         return 0;
1115 }
1116 
1117 static const struct of_device_id at91_pinctrl_of_match[] = {
1118         { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
1119         { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
1120         { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
1121         { /* sentinel */ }
1122 };
1123 
1124 static int at91_pinctrl_probe_dt(struct platform_device *pdev,
1125                                  struct at91_pinctrl *info)
1126 {
1127         int ret = 0;
1128         int i, j;
1129         uint32_t *tmp;
1130         struct device_node *np = pdev->dev.of_node;
1131         struct device_node *child;
1132 
1133         if (!np)
1134                 return -ENODEV;
1135 
1136         info->dev = &pdev->dev;
1137         info->ops = (struct at91_pinctrl_mux_ops *)
1138                 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
1139         at91_pinctrl_child_count(info, np);
1140 
1141         if (gpio_banks < 1) {
1142                 dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n");
1143                 return -EINVAL;
1144         }
1145 
1146         ret = at91_pinctrl_mux_mask(info, np);
1147         if (ret)
1148                 return ret;
1149 
1150         dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
1151 
1152         dev_dbg(&pdev->dev, "mux-mask\n");
1153         tmp = info->mux_mask;
1154         for (i = 0; i < gpio_banks; i++) {
1155                 for (j = 0; j < info->nmux; j++, tmp++) {
1156                         dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
1157                 }
1158         }
1159 
1160         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1161         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1162         info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func),
1163                                         GFP_KERNEL);
1164         if (!info->functions)
1165                 return -ENOMEM;
1166 
1167         info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group),
1168                                         GFP_KERNEL);
1169         if (!info->groups)
1170                 return -ENOMEM;
1171 
1172         dev_dbg(&pdev->dev, "nbanks = %d\n", gpio_banks);
1173         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1174         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1175 
1176         i = 0;
1177 
1178         for_each_child_of_node(np, child) {
1179                 if (of_device_is_compatible(child, gpio_compat))
1180                         continue;
1181                 ret = at91_pinctrl_parse_functions(child, info, i++);
1182                 if (ret) {
1183                         dev_err(&pdev->dev, "failed to parse function\n");
1184                         return ret;
1185                 }
1186         }
1187 
1188         return 0;
1189 }
1190 
1191 static int at91_pinctrl_probe(struct platform_device *pdev)
1192 {
1193         struct at91_pinctrl *info;
1194         struct pinctrl_pin_desc *pdesc;
1195         int ret, i, j, k, ngpio_chips_enabled = 0;
1196 
1197         info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1198         if (!info)
1199                 return -ENOMEM;
1200 
1201         ret = at91_pinctrl_probe_dt(pdev, info);
1202         if (ret)
1203                 return ret;
1204 
1205         /*
1206          * We need all the GPIO drivers to probe FIRST, or we will not be able
1207          * to obtain references to the struct gpio_chip * for them, and we
1208          * need this to proceed.
1209          */
1210         for (i = 0; i < gpio_banks; i++)
1211                 if (gpio_chips[i])
1212                         ngpio_chips_enabled++;
1213 
1214         if (ngpio_chips_enabled < info->nactive_banks) {
1215                 dev_warn(&pdev->dev,
1216                          "All GPIO chips are not registered yet (%d/%d)\n",
1217                          ngpio_chips_enabled, info->nactive_banks);
1218                 devm_kfree(&pdev->dev, info);
1219                 return -EPROBE_DEFER;
1220         }
1221 
1222         at91_pinctrl_desc.name = dev_name(&pdev->dev);
1223         at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK;
1224         at91_pinctrl_desc.pins = pdesc =
1225                 devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL);
1226 
1227         if (!at91_pinctrl_desc.pins)
1228                 return -ENOMEM;
1229 
1230         for (i = 0, k = 0; i < gpio_banks; i++) {
1231                 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1232                         pdesc->number = k;
1233                         pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
1234                         pdesc++;
1235                 }
1236         }
1237 
1238         platform_set_drvdata(pdev, info);
1239         info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info);
1240 
1241         if (!info->pctl) {
1242                 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
1243                 return -EINVAL;
1244         }
1245 
1246         /* We will handle a range of GPIO pins */
1247         for (i = 0; i < gpio_banks; i++)
1248                 if (gpio_chips[i])
1249                         pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
1250 
1251         dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
1252 
1253         return 0;
1254 }
1255 
1256 static int at91_pinctrl_remove(struct platform_device *pdev)
1257 {
1258         struct at91_pinctrl *info = platform_get_drvdata(pdev);
1259 
1260         pinctrl_unregister(info->pctl);
1261 
1262         return 0;
1263 }
1264 
1265 static int at91_gpio_request(struct gpio_chip *chip, unsigned offset)
1266 {
1267         /*
1268          * Map back to global GPIO space and request muxing, the direction
1269          * parameter does not matter for this controller.
1270          */
1271         int gpio = chip->base + offset;
1272         int bank = chip->base / chip->ngpio;
1273 
1274         dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__,
1275                  'A' + bank, offset, gpio);
1276 
1277         return pinctrl_request_gpio(gpio);
1278 }
1279 
1280 static void at91_gpio_free(struct gpio_chip *chip, unsigned offset)
1281 {
1282         int gpio = chip->base + offset;
1283 
1284         pinctrl_free_gpio(gpio);
1285 }
1286 
1287 static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1288 {
1289         struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1290         void __iomem *pio = at91_gpio->regbase;
1291         unsigned mask = 1 << offset;
1292         u32 osr;
1293 
1294         osr = readl_relaxed(pio + PIO_OSR);
1295         return !(osr & mask);
1296 }
1297 
1298 static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1299 {
1300         struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1301         void __iomem *pio = at91_gpio->regbase;
1302         unsigned mask = 1 << offset;
1303 
1304         writel_relaxed(mask, pio + PIO_ODR);
1305         return 0;
1306 }
1307 
1308 static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1309 {
1310         struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1311         void __iomem *pio = at91_gpio->regbase;
1312         unsigned mask = 1 << offset;
1313         u32 pdsr;
1314 
1315         pdsr = readl_relaxed(pio + PIO_PDSR);
1316         return (pdsr & mask) != 0;
1317 }
1318 
1319 static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1320                                 int val)
1321 {
1322         struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1323         void __iomem *pio = at91_gpio->regbase;
1324         unsigned mask = 1 << offset;
1325 
1326         writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1327 }
1328 
1329 static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1330                                 int val)
1331 {
1332         struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1333         void __iomem *pio = at91_gpio->regbase;
1334         unsigned mask = 1 << offset;
1335 
1336         writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1337         writel_relaxed(mask, pio + PIO_OER);
1338 
1339         return 0;
1340 }
1341 
1342 #ifdef CONFIG_DEBUG_FS
1343 static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1344 {
1345         enum at91_mux mode;
1346         int i;
1347         struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1348         void __iomem *pio = at91_gpio->regbase;
1349 
1350         for (i = 0; i < chip->ngpio; i++) {
1351                 unsigned mask = pin_to_mask(i);
1352                 const char *gpio_label;
1353 
1354                 gpio_label = gpiochip_is_requested(chip, i);
1355                 if (!gpio_label)
1356                         continue;
1357                 mode = at91_gpio->ops->get_periph(pio, mask);
1358                 seq_printf(s, "[%s] GPIO%s%d: ",
1359                            gpio_label, chip->label, i);
1360                 if (mode == AT91_MUX_GPIO) {
1361                         seq_printf(s, "[gpio] ");
1362                         seq_printf(s, "%s ",
1363                                       readl_relaxed(pio + PIO_OSR) & mask ?
1364                                       "output" : "input");
1365                         seq_printf(s, "%s\n",
1366                                       readl_relaxed(pio + PIO_PDSR) & mask ?
1367                                       "set" : "clear");
1368                 } else {
1369                         seq_printf(s, "[periph %c]\n",
1370                                    mode + 'A' - 1);
1371                 }
1372         }
1373 }
1374 #else
1375 #define at91_gpio_dbg_show      NULL
1376 #endif
1377 
1378 /* Several AIC controller irqs are dispatched through this GPIO handler.
1379  * To use any AT91_PIN_* as an externally triggered IRQ, first call
1380  * at91_set_gpio_input() then maybe enable its glitch filter.
1381  * Then just request_irq() with the pin ID; it works like any ARM IRQ
1382  * handler.
1383  * First implementation always triggers on rising and falling edges
1384  * whereas the newer PIO3 can be additionally configured to trigger on
1385  * level, edge with any polarity.
1386  *
1387  * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1388  * configuring them with at91_set_a_periph() or at91_set_b_periph().
1389  * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1390  */
1391 
1392 static void gpio_irq_mask(struct irq_data *d)
1393 {
1394         struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1395         void __iomem    *pio = at91_gpio->regbase;
1396         unsigned        mask = 1 << d->hwirq;
1397 
1398         if (pio)
1399                 writel_relaxed(mask, pio + PIO_IDR);
1400 }
1401 
1402 static void gpio_irq_unmask(struct irq_data *d)
1403 {
1404         struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1405         void __iomem    *pio = at91_gpio->regbase;
1406         unsigned        mask = 1 << d->hwirq;
1407 
1408         if (pio)
1409                 writel_relaxed(mask, pio + PIO_IER);
1410 }
1411 
1412 static int gpio_irq_type(struct irq_data *d, unsigned type)
1413 {
1414         switch (type) {
1415         case IRQ_TYPE_NONE:
1416         case IRQ_TYPE_EDGE_BOTH:
1417                 return 0;
1418         default:
1419                 return -EINVAL;
1420         }
1421 }
1422 
1423 /* Alternate irq type for PIO3 support */
1424 static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1425 {
1426         struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1427         void __iomem    *pio = at91_gpio->regbase;
1428         unsigned        mask = 1 << d->hwirq;
1429 
1430         switch (type) {
1431         case IRQ_TYPE_EDGE_RISING:
1432                 __irq_set_handler_locked(d->irq, handle_simple_irq);
1433                 writel_relaxed(mask, pio + PIO_ESR);
1434                 writel_relaxed(mask, pio + PIO_REHLSR);
1435                 break;
1436         case IRQ_TYPE_EDGE_FALLING:
1437                 __irq_set_handler_locked(d->irq, handle_simple_irq);
1438                 writel_relaxed(mask, pio + PIO_ESR);
1439                 writel_relaxed(mask, pio + PIO_FELLSR);
1440                 break;
1441         case IRQ_TYPE_LEVEL_LOW:
1442                 __irq_set_handler_locked(d->irq, handle_level_irq);
1443                 writel_relaxed(mask, pio + PIO_LSR);
1444                 writel_relaxed(mask, pio + PIO_FELLSR);
1445                 break;
1446         case IRQ_TYPE_LEVEL_HIGH:
1447                 __irq_set_handler_locked(d->irq, handle_level_irq);
1448                 writel_relaxed(mask, pio + PIO_LSR);
1449                 writel_relaxed(mask, pio + PIO_REHLSR);
1450                 break;
1451         case IRQ_TYPE_EDGE_BOTH:
1452                 /*
1453                  * disable additional interrupt modes:
1454                  * fall back to default behavior
1455                  */
1456                 __irq_set_handler_locked(d->irq, handle_simple_irq);
1457                 writel_relaxed(mask, pio + PIO_AIMDR);
1458                 return 0;
1459         case IRQ_TYPE_NONE:
1460         default:
1461                 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
1462                 return -EINVAL;
1463         }
1464 
1465         /* enable additional interrupt modes */
1466         writel_relaxed(mask, pio + PIO_AIMER);
1467 
1468         return 0;
1469 }
1470 
1471 static void gpio_irq_ack(struct irq_data *d)
1472 {
1473         /* the interrupt is already cleared before by reading ISR */
1474 }
1475 
1476 static int gpio_irq_request_res(struct irq_data *d)
1477 {
1478         struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1479         unsigned        pin = d->hwirq;
1480         int ret;
1481 
1482         ret = gpiochip_lock_as_irq(&at91_gpio->chip, pin);
1483         if (ret)
1484                 dev_err(at91_gpio->chip.dev, "unable to lock pind %lu IRQ\n",
1485                         d->hwirq);
1486 
1487         return ret;
1488 }
1489 
1490 static void gpio_irq_release_res(struct irq_data *d)
1491 {
1492         struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1493         unsigned        pin = d->hwirq;
1494 
1495         gpiochip_unlock_as_irq(&at91_gpio->chip, pin);
1496 }
1497 
1498 #ifdef CONFIG_PM
1499 
1500 static u32 wakeups[MAX_GPIO_BANKS];
1501 static u32 backups[MAX_GPIO_BANKS];
1502 
1503 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1504 {
1505         struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1506         unsigned        bank = at91_gpio->pioc_idx;
1507         unsigned mask = 1 << d->hwirq;
1508 
1509         if (unlikely(bank >= MAX_GPIO_BANKS))
1510                 return -EINVAL;
1511 
1512         if (state)
1513                 wakeups[bank] |= mask;
1514         else
1515                 wakeups[bank] &= ~mask;
1516 
1517         irq_set_irq_wake(at91_gpio->pioc_virq, state);
1518 
1519         return 0;
1520 }
1521 
1522 void at91_pinctrl_gpio_suspend(void)
1523 {
1524         int i;
1525 
1526         for (i = 0; i < gpio_banks; i++) {
1527                 void __iomem  *pio;
1528 
1529                 if (!gpio_chips[i])
1530                         continue;
1531 
1532                 pio = gpio_chips[i]->regbase;
1533 
1534                 backups[i] = readl_relaxed(pio + PIO_IMR);
1535                 writel_relaxed(backups[i], pio + PIO_IDR);
1536                 writel_relaxed(wakeups[i], pio + PIO_IER);
1537 
1538                 if (!wakeups[i])
1539                         clk_disable_unprepare(gpio_chips[i]->clock);
1540                 else
1541                         printk(KERN_DEBUG "GPIO-%c may wake for %08x\n",
1542                                'A'+i, wakeups[i]);
1543         }
1544 }
1545 
1546 void at91_pinctrl_gpio_resume(void)
1547 {
1548         int i;
1549 
1550         for (i = 0; i < gpio_banks; i++) {
1551                 void __iomem  *pio;
1552 
1553                 if (!gpio_chips[i])
1554                         continue;
1555 
1556                 pio = gpio_chips[i]->regbase;
1557 
1558                 if (!wakeups[i])
1559                         clk_prepare_enable(gpio_chips[i]->clock);
1560 
1561                 writel_relaxed(wakeups[i], pio + PIO_IDR);
1562                 writel_relaxed(backups[i], pio + PIO_IER);
1563         }
1564 }
1565 
1566 #else
1567 #define gpio_irq_set_wake       NULL
1568 #endif /* CONFIG_PM */
1569 
1570 static struct irq_chip gpio_irqchip = {
1571         .name           = "GPIO",
1572         .irq_ack        = gpio_irq_ack,
1573         .irq_request_resources = gpio_irq_request_res,
1574         .irq_release_resources = gpio_irq_release_res,
1575         .irq_disable    = gpio_irq_mask,
1576         .irq_mask       = gpio_irq_mask,
1577         .irq_unmask     = gpio_irq_unmask,
1578         /* .irq_set_type is set dynamically */
1579         .irq_set_wake   = gpio_irq_set_wake,
1580 };
1581 
1582 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1583 {
1584         struct irq_chip *chip = irq_get_chip(irq);
1585         struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc);
1586         struct at91_gpio_chip *at91_gpio = container_of(gpio_chip,
1587                                            struct at91_gpio_chip, chip);
1588 
1589         void __iomem    *pio = at91_gpio->regbase;
1590         unsigned long   isr;
1591         int             n;
1592 
1593         chained_irq_enter(chip, desc);
1594         for (;;) {
1595                 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
1596                  * When there are none pending, we're finished unless we need
1597                  * to process multiple banks (like ID_PIOCDE on sam9263).
1598                  */
1599                 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1600                 if (!isr) {
1601                         if (!at91_gpio->next)
1602                                 break;
1603                         at91_gpio = at91_gpio->next;
1604                         pio = at91_gpio->regbase;
1605                         gpio_chip = &at91_gpio->chip;
1606                         continue;
1607                 }
1608 
1609                 for_each_set_bit(n, &isr, BITS_PER_LONG) {
1610                         generic_handle_irq(irq_find_mapping(
1611                                            gpio_chip->irqdomain, n));
1612                 }
1613         }
1614         chained_irq_exit(chip, desc);
1615         /* now it may re-trigger */
1616 }
1617 
1618 static int at91_gpio_of_irq_setup(struct platform_device *pdev,
1619                                   struct at91_gpio_chip *at91_gpio)
1620 {
1621         struct gpio_chip        *gpiochip_prev = NULL;
1622         struct at91_gpio_chip   *prev = NULL;
1623         struct irq_data         *d = irq_get_irq_data(at91_gpio->pioc_virq);
1624         int ret, i;
1625 
1626         at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1627 
1628         /* Setup proper .irq_set_type function */
1629         gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type;
1630 
1631         /* Disable irqs of this PIO controller */
1632         writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1633 
1634         /*
1635          * Let the generic code handle this edge IRQ, the the chained
1636          * handler will perform the actual work of handling the parent
1637          * interrupt.
1638          */
1639         ret = gpiochip_irqchip_add(&at91_gpio->chip,
1640                                    &gpio_irqchip,
1641                                    0,
1642                                    handle_edge_irq,
1643                                    IRQ_TYPE_EDGE_BOTH);
1644         if (ret) {
1645                 dev_err(&pdev->dev, "at91_gpio.%d: Couldn't add irqchip to gpiochip.\n",
1646                         at91_gpio->pioc_idx);
1647                 return ret;
1648         }
1649 
1650         /* The top level handler handles one bank of GPIOs, except
1651          * on some SoC it can handle up to three...
1652          * We only set up the handler for the first of the list.
1653          */
1654         gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq);
1655         if (!gpiochip_prev) {
1656                 /* Then register the chain on the parent IRQ */
1657                 gpiochip_set_chained_irqchip(&at91_gpio->chip,
1658                                              &gpio_irqchip,
1659                                              at91_gpio->pioc_virq,
1660                                              gpio_irq_handler);
1661                 return 0;
1662         }
1663 
1664         prev = container_of(gpiochip_prev, struct at91_gpio_chip, chip);
1665 
1666         /* we can only have 2 banks before */
1667         for (i = 0; i < 2; i++) {
1668                 if (prev->next) {
1669                         prev = prev->next;
1670                 } else {
1671                         prev->next = at91_gpio;
1672                         return 0;
1673                 }
1674         }
1675 
1676         return -EINVAL;
1677 }
1678 
1679 /* This structure is replicated for each GPIO block allocated at probe time */
1680 static struct gpio_chip at91_gpio_template = {
1681         .request                = at91_gpio_request,
1682         .free                   = at91_gpio_free,
1683         .get_direction          = at91_gpio_get_direction,
1684         .direction_input        = at91_gpio_direction_input,
1685         .get                    = at91_gpio_get,
1686         .direction_output       = at91_gpio_direction_output,
1687         .set                    = at91_gpio_set,
1688         .dbg_show               = at91_gpio_dbg_show,
1689         .can_sleep              = false,
1690         .ngpio                  = MAX_NB_GPIO_PER_BANK,
1691 };
1692 
1693 static const struct of_device_id at91_gpio_of_match[] = {
1694         { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1695         { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1696         { /* sentinel */ }
1697 };
1698 
1699 static int at91_gpio_probe(struct platform_device *pdev)
1700 {
1701         struct device_node *np = pdev->dev.of_node;
1702         struct resource *res;
1703         struct at91_gpio_chip *at91_chip = NULL;
1704         struct gpio_chip *chip;
1705         struct pinctrl_gpio_range *range;
1706         int ret = 0;
1707         int irq, i;
1708         int alias_idx = of_alias_get_id(np, "gpio");
1709         uint32_t ngpio;
1710         char **names;
1711 
1712         BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1713         if (gpio_chips[alias_idx]) {
1714                 ret = -EBUSY;
1715                 goto err;
1716         }
1717 
1718         irq = platform_get_irq(pdev, 0);
1719         if (irq < 0) {
1720                 ret = irq;
1721                 goto err;
1722         }
1723 
1724         at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
1725         if (!at91_chip) {
1726                 ret = -ENOMEM;
1727                 goto err;
1728         }
1729 
1730         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1731         at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res);
1732         if (IS_ERR(at91_chip->regbase)) {
1733                 ret = PTR_ERR(at91_chip->regbase);
1734                 goto err;
1735         }
1736 
1737         at91_chip->ops = (struct at91_pinctrl_mux_ops *)
1738                 of_match_device(at91_gpio_of_match, &pdev->dev)->data;
1739         at91_chip->pioc_virq = irq;
1740         at91_chip->pioc_idx = alias_idx;
1741 
1742         at91_chip->clock = devm_clk_get(&pdev->dev, NULL);
1743         if (IS_ERR(at91_chip->clock)) {
1744                 dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
1745                 ret = PTR_ERR(at91_chip->clock);
1746                 goto err;
1747         }
1748 
1749         ret = clk_prepare(at91_chip->clock);
1750         if (ret)
1751                 goto clk_prepare_err;
1752 
1753         /* enable PIO controller's clock */
1754         ret = clk_enable(at91_chip->clock);
1755         if (ret) {
1756                 dev_err(&pdev->dev, "failed to enable clock, ignoring.\n");
1757                 goto clk_enable_err;
1758         }
1759 
1760         at91_chip->chip = at91_gpio_template;
1761 
1762         chip = &at91_chip->chip;
1763         chip->of_node = np;
1764         chip->label = dev_name(&pdev->dev);
1765         chip->dev = &pdev->dev;
1766         chip->owner = THIS_MODULE;
1767         chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1768 
1769         if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1770                 if (ngpio >= MAX_NB_GPIO_PER_BANK)
1771                         pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1772                                alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1773                 else
1774                         chip->ngpio = ngpio;
1775         }
1776 
1777         names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio,
1778                              GFP_KERNEL);
1779 
1780         if (!names) {
1781                 ret = -ENOMEM;
1782                 goto clk_enable_err;
1783         }
1784 
1785         for (i = 0; i < chip->ngpio; i++)
1786                 names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i);
1787 
1788         chip->names = (const char *const *)names;
1789 
1790         range = &at91_chip->range;
1791         range->name = chip->label;
1792         range->id = alias_idx;
1793         range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1794 
1795         range->npins = chip->ngpio;
1796         range->gc = chip;
1797 
1798         ret = gpiochip_add(chip);
1799         if (ret)
1800                 goto gpiochip_add_err;
1801 
1802         gpio_chips[alias_idx] = at91_chip;
1803         gpio_banks = max(gpio_banks, alias_idx + 1);
1804 
1805         ret = at91_gpio_of_irq_setup(pdev, at91_chip);
1806         if (ret)
1807                 goto irq_setup_err;
1808 
1809         dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1810 
1811         return 0;
1812 
1813 irq_setup_err:
1814         gpiochip_remove(chip);
1815 gpiochip_add_err:
1816         clk_disable(at91_chip->clock);
1817 clk_enable_err:
1818         clk_unprepare(at91_chip->clock);
1819 clk_prepare_err:
1820 err:
1821         dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1822 
1823         return ret;
1824 }
1825 
1826 static struct platform_driver at91_gpio_driver = {
1827         .driver = {
1828                 .name = "gpio-at91",
1829                 .of_match_table = at91_gpio_of_match,
1830         },
1831         .probe = at91_gpio_probe,
1832 };
1833 
1834 static struct platform_driver at91_pinctrl_driver = {
1835         .driver = {
1836                 .name = "pinctrl-at91",
1837                 .of_match_table = at91_pinctrl_of_match,
1838         },
1839         .probe = at91_pinctrl_probe,
1840         .remove = at91_pinctrl_remove,
1841 };
1842 
1843 static int __init at91_pinctrl_init(void)
1844 {
1845         int ret;
1846 
1847         ret = platform_driver_register(&at91_gpio_driver);
1848         if (ret)
1849                 return ret;
1850         return platform_driver_register(&at91_pinctrl_driver);
1851 }
1852 arch_initcall(at91_pinctrl_init);
1853 
1854 static void __exit at91_pinctrl_exit(void)
1855 {
1856         platform_driver_unregister(&at91_pinctrl_driver);
1857 }
1858 
1859 module_exit(at91_pinctrl_exit);
1860 MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>");
1861 MODULE_DESCRIPTION("Atmel AT91 pinctrl driver");
1862 MODULE_LICENSE("GPL v2");
1863 

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