Version:  2.0.40 2.2.26 2.4.37 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10

Linux/drivers/pinctrl/pinctrl-at91.c

  1 /*
  2  * at91 pinctrl driver based on at91 pinmux core
  3  *
  4  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  5  *
  6  * Under GPLv2 only
  7  */
  8 
  9 #include <linux/clk.h>
 10 #include <linux/err.h>
 11 #include <linux/init.h>
 12 #include <linux/of.h>
 13 #include <linux/of_device.h>
 14 #include <linux/of_address.h>
 15 #include <linux/of_irq.h>
 16 #include <linux/slab.h>
 17 #include <linux/interrupt.h>
 18 #include <linux/io.h>
 19 #include <linux/gpio.h>
 20 #include <linux/pinctrl/machine.h>
 21 #include <linux/pinctrl/pinconf.h>
 22 #include <linux/pinctrl/pinctrl.h>
 23 #include <linux/pinctrl/pinmux.h>
 24 /* Since we request GPIOs from ourself */
 25 #include <linux/pinctrl/consumer.h>
 26 
 27 #include "pinctrl-at91.h"
 28 #include "core.h"
 29 
 30 #define MAX_GPIO_BANKS          5
 31 #define MAX_NB_GPIO_PER_BANK    32
 32 
 33 struct at91_pinctrl_mux_ops;
 34 
 35 struct at91_gpio_chip {
 36         struct gpio_chip        chip;
 37         struct pinctrl_gpio_range range;
 38         struct at91_gpio_chip   *next;          /* Bank sharing same clock */
 39         int                     pioc_hwirq;     /* PIO bank interrupt identifier on AIC */
 40         int                     pioc_virq;      /* PIO bank Linux virtual interrupt */
 41         int                     pioc_idx;       /* PIO bank index */
 42         void __iomem            *regbase;       /* PIO bank virtual address */
 43         struct clk              *clock;         /* associated clock */
 44         struct at91_pinctrl_mux_ops *ops;       /* ops */
 45 };
 46 
 47 static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
 48 
 49 static int gpio_banks;
 50 
 51 #define PULL_UP         (1 << 0)
 52 #define MULTI_DRIVE     (1 << 1)
 53 #define DEGLITCH        (1 << 2)
 54 #define PULL_DOWN       (1 << 3)
 55 #define DIS_SCHMIT      (1 << 4)
 56 #define DRIVE_STRENGTH_SHIFT    5
 57 #define DRIVE_STRENGTH_MASK             0x3
 58 #define DRIVE_STRENGTH   (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
 59 #define OUTPUT          (1 << 7)
 60 #define OUTPUT_VAL_SHIFT        8
 61 #define OUTPUT_VAL      (0x1 << OUTPUT_VAL_SHIFT)
 62 #define DEBOUNCE        (1 << 16)
 63 #define DEBOUNCE_VAL_SHIFT      17
 64 #define DEBOUNCE_VAL    (0x3fff << DEBOUNCE_VAL_SHIFT)
 65 
 66 /**
 67  * These defines will translated the dt binding settings to our internal
 68  * settings. They are not necessarily the same value as the register setting.
 69  * The actual drive strength current of low, medium and high must be looked up
 70  * from the corresponding device datasheet. This value is different for pins
 71  * that are even in the same banks. It is also dependent on VCC.
 72  * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
 73  * strength when there is no dt config for it.
 74  */
 75 #define DRIVE_STRENGTH_DEFAULT          (0 << DRIVE_STRENGTH_SHIFT)
 76 #define DRIVE_STRENGTH_LOW          (1 << DRIVE_STRENGTH_SHIFT)
 77 #define DRIVE_STRENGTH_MED          (2 << DRIVE_STRENGTH_SHIFT)
 78 #define DRIVE_STRENGTH_HI           (3 << DRIVE_STRENGTH_SHIFT)
 79 
 80 /**
 81  * struct at91_pmx_func - describes AT91 pinmux functions
 82  * @name: the name of this specific function
 83  * @groups: corresponding pin groups
 84  * @ngroups: the number of groups
 85  */
 86 struct at91_pmx_func {
 87         const char      *name;
 88         const char      **groups;
 89         unsigned        ngroups;
 90 };
 91 
 92 enum at91_mux {
 93         AT91_MUX_GPIO = 0,
 94         AT91_MUX_PERIPH_A = 1,
 95         AT91_MUX_PERIPH_B = 2,
 96         AT91_MUX_PERIPH_C = 3,
 97         AT91_MUX_PERIPH_D = 4,
 98 };
 99 
100 /**
101  * struct at91_pmx_pin - describes an At91 pin mux
102  * @bank: the bank of the pin
103  * @pin: the pin number in the @bank
104  * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
105  * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
106  */
107 struct at91_pmx_pin {
108         uint32_t        bank;
109         uint32_t        pin;
110         enum at91_mux   mux;
111         unsigned long   conf;
112 };
113 
114 /**
115  * struct at91_pin_group - describes an At91 pin group
116  * @name: the name of this specific pin group
117  * @pins_conf: the mux mode for each pin in this group. The size of this
118  *      array is the same as pins.
119  * @pins: an array of discrete physical pins used in this group, taken
120  *      from the driver-local pin enumeration space
121  * @npins: the number of pins in this group array, i.e. the number of
122  *      elements in .pins so we can iterate over that array
123  */
124 struct at91_pin_group {
125         const char              *name;
126         struct at91_pmx_pin     *pins_conf;
127         unsigned int            *pins;
128         unsigned                npins;
129 };
130 
131 /**
132  * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
133  * on new IP with support for periph C and D the way to mux in
134  * periph A and B has changed
135  * So provide the right call back
136  * if not present means the IP does not support it
137  * @get_periph: return the periph mode configured
138  * @mux_A_periph: mux as periph A
139  * @mux_B_periph: mux as periph B
140  * @mux_C_periph: mux as periph C
141  * @mux_D_periph: mux as periph D
142  * @get_deglitch: get deglitch status
143  * @set_deglitch: enable/disable deglitch
144  * @get_debounce: get debounce status
145  * @set_debounce: enable/disable debounce
146  * @get_pulldown: get pulldown status
147  * @set_pulldown: enable/disable pulldown
148  * @get_schmitt_trig: get schmitt trigger status
149  * @disable_schmitt_trig: disable schmitt trigger
150  * @irq_type: return irq type
151  */
152 struct at91_pinctrl_mux_ops {
153         enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
154         void (*mux_A_periph)(void __iomem *pio, unsigned mask);
155         void (*mux_B_periph)(void __iomem *pio, unsigned mask);
156         void (*mux_C_periph)(void __iomem *pio, unsigned mask);
157         void (*mux_D_periph)(void __iomem *pio, unsigned mask);
158         bool (*get_deglitch)(void __iomem *pio, unsigned pin);
159         void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
160         bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
161         void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
162         bool (*get_pulldown)(void __iomem *pio, unsigned pin);
163         void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
164         bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
165         void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
166         unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
167         void (*set_drivestrength)(void __iomem *pio, unsigned pin,
168                                         u32 strength);
169         /* irq */
170         int (*irq_type)(struct irq_data *d, unsigned type);
171 };
172 
173 static int gpio_irq_type(struct irq_data *d, unsigned type);
174 static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
175 
176 struct at91_pinctrl {
177         struct device           *dev;
178         struct pinctrl_dev      *pctl;
179 
180         int                     nactive_banks;
181 
182         uint32_t                *mux_mask;
183         int                     nmux;
184 
185         struct at91_pmx_func    *functions;
186         int                     nfunctions;
187 
188         struct at91_pin_group   *groups;
189         int                     ngroups;
190 
191         struct at91_pinctrl_mux_ops *ops;
192 };
193 
194 static inline const struct at91_pin_group *at91_pinctrl_find_group_by_name(
195                                 const struct at91_pinctrl *info,
196                                 const char *name)
197 {
198         const struct at91_pin_group *grp = NULL;
199         int i;
200 
201         for (i = 0; i < info->ngroups; i++) {
202                 if (strcmp(info->groups[i].name, name))
203                         continue;
204 
205                 grp = &info->groups[i];
206                 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
207                 break;
208         }
209 
210         return grp;
211 }
212 
213 static int at91_get_groups_count(struct pinctrl_dev *pctldev)
214 {
215         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
216 
217         return info->ngroups;
218 }
219 
220 static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
221                                        unsigned selector)
222 {
223         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
224 
225         return info->groups[selector].name;
226 }
227 
228 static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
229                                const unsigned **pins,
230                                unsigned *npins)
231 {
232         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
233 
234         if (selector >= info->ngroups)
235                 return -EINVAL;
236 
237         *pins = info->groups[selector].pins;
238         *npins = info->groups[selector].npins;
239 
240         return 0;
241 }
242 
243 static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
244                    unsigned offset)
245 {
246         seq_printf(s, "%s", dev_name(pctldev->dev));
247 }
248 
249 static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
250                         struct device_node *np,
251                         struct pinctrl_map **map, unsigned *num_maps)
252 {
253         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
254         const struct at91_pin_group *grp;
255         struct pinctrl_map *new_map;
256         struct device_node *parent;
257         int map_num = 1;
258         int i;
259 
260         /*
261          * first find the group of this node and check if we need to create
262          * config maps for pins
263          */
264         grp = at91_pinctrl_find_group_by_name(info, np->name);
265         if (!grp) {
266                 dev_err(info->dev, "unable to find group for node %s\n",
267                         np->name);
268                 return -EINVAL;
269         }
270 
271         map_num += grp->npins;
272         new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL);
273         if (!new_map)
274                 return -ENOMEM;
275 
276         *map = new_map;
277         *num_maps = map_num;
278 
279         /* create mux map */
280         parent = of_get_parent(np);
281         if (!parent) {
282                 devm_kfree(pctldev->dev, new_map);
283                 return -EINVAL;
284         }
285         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
286         new_map[0].data.mux.function = parent->name;
287         new_map[0].data.mux.group = np->name;
288         of_node_put(parent);
289 
290         /* create config map */
291         new_map++;
292         for (i = 0; i < grp->npins; i++) {
293                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
294                 new_map[i].data.configs.group_or_pin =
295                                 pin_get_name(pctldev, grp->pins[i]);
296                 new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
297                 new_map[i].data.configs.num_configs = 1;
298         }
299 
300         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
301                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
302 
303         return 0;
304 }
305 
306 static void at91_dt_free_map(struct pinctrl_dev *pctldev,
307                                 struct pinctrl_map *map, unsigned num_maps)
308 {
309 }
310 
311 static const struct pinctrl_ops at91_pctrl_ops = {
312         .get_groups_count       = at91_get_groups_count,
313         .get_group_name         = at91_get_group_name,
314         .get_group_pins         = at91_get_group_pins,
315         .pin_dbg_show           = at91_pin_dbg_show,
316         .dt_node_to_map         = at91_dt_node_to_map,
317         .dt_free_map            = at91_dt_free_map,
318 };
319 
320 static void __iomem *pin_to_controller(struct at91_pinctrl *info,
321                                  unsigned int bank)
322 {
323         if (!gpio_chips[bank])
324                 return NULL;
325 
326         return gpio_chips[bank]->regbase;
327 }
328 
329 static inline int pin_to_bank(unsigned pin)
330 {
331         return pin /= MAX_NB_GPIO_PER_BANK;
332 }
333 
334 static unsigned pin_to_mask(unsigned int pin)
335 {
336         return 1 << pin;
337 }
338 
339 static unsigned two_bit_pin_value_shift_amount(unsigned int pin)
340 {
341         /* return the shift value for a pin for "two bit" per pin registers,
342          * i.e. drive strength */
343         return 2*((pin >= MAX_NB_GPIO_PER_BANK/2)
344                         ? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
345 }
346 
347 static unsigned sama5d3_get_drive_register(unsigned int pin)
348 {
349         /* drive strength is split between two registers
350          * with two bits per pin */
351         return (pin >= MAX_NB_GPIO_PER_BANK/2)
352                         ? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1;
353 }
354 
355 static unsigned at91sam9x5_get_drive_register(unsigned int pin)
356 {
357         /* drive strength is split between two registers
358          * with two bits per pin */
359         return (pin >= MAX_NB_GPIO_PER_BANK/2)
360                         ? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1;
361 }
362 
363 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
364 {
365         writel_relaxed(mask, pio + PIO_IDR);
366 }
367 
368 static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
369 {
370         return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1);
371 }
372 
373 static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
374 {
375         if (on)
376                 writel_relaxed(mask, pio + PIO_PPDDR);
377 
378         writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
379 }
380 
381 static bool at91_mux_get_output(void __iomem *pio, unsigned int pin, bool *val)
382 {
383         *val = (readl_relaxed(pio + PIO_ODSR) >> pin) & 0x1;
384         return (readl_relaxed(pio + PIO_OSR) >> pin) & 0x1;
385 }
386 
387 static void at91_mux_set_output(void __iomem *pio, unsigned int mask,
388                                 bool is_on, bool val)
389 {
390         writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
391         writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR));
392 }
393 
394 static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
395 {
396         return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
397 }
398 
399 static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
400 {
401         writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
402 }
403 
404 static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
405 {
406         writel_relaxed(mask, pio + PIO_ASR);
407 }
408 
409 static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
410 {
411         writel_relaxed(mask, pio + PIO_BSR);
412 }
413 
414 static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
415 {
416 
417         writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
418                                                 pio + PIO_ABCDSR1);
419         writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
420                                                 pio + PIO_ABCDSR2);
421 }
422 
423 static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
424 {
425         writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
426                                                 pio + PIO_ABCDSR1);
427         writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
428                                                 pio + PIO_ABCDSR2);
429 }
430 
431 static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
432 {
433         writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
434         writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
435 }
436 
437 static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
438 {
439         writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
440         writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
441 }
442 
443 static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
444 {
445         unsigned select;
446 
447         if (readl_relaxed(pio + PIO_PSR) & mask)
448                 return AT91_MUX_GPIO;
449 
450         select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
451         select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
452 
453         return select + 1;
454 }
455 
456 static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
457 {
458         unsigned select;
459 
460         if (readl_relaxed(pio + PIO_PSR) & mask)
461                 return AT91_MUX_GPIO;
462 
463         select = readl_relaxed(pio + PIO_ABSR) & mask;
464 
465         return select + 1;
466 }
467 
468 static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
469 {
470         return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1;
471 }
472 
473 static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
474 {
475         writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
476 }
477 
478 static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
479 {
480         if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1)
481                 return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
482 
483         return false;
484 }
485 
486 static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
487 {
488         if (is_on)
489                 writel_relaxed(mask, pio + PIO_IFSCDR);
490         at91_mux_set_deglitch(pio, mask, is_on);
491 }
492 
493 static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
494 {
495         *div = readl_relaxed(pio + PIO_SCDR);
496 
497         return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) &&
498                ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
499 }
500 
501 static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
502                                 bool is_on, u32 div)
503 {
504         if (is_on) {
505                 writel_relaxed(mask, pio + PIO_IFSCER);
506                 writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR);
507                 writel_relaxed(mask, pio + PIO_IFER);
508         } else
509                 writel_relaxed(mask, pio + PIO_IFSCDR);
510 }
511 
512 static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
513 {
514         return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1);
515 }
516 
517 static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
518 {
519         if (is_on)
520                 writel_relaxed(mask, pio + PIO_PUDR);
521 
522         writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
523 }
524 
525 static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
526 {
527         writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
528 }
529 
530 static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
531 {
532         return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1;
533 }
534 
535 static inline u32 read_drive_strength(void __iomem *reg, unsigned pin)
536 {
537         unsigned tmp = readl_relaxed(reg);
538 
539         tmp = tmp >> two_bit_pin_value_shift_amount(pin);
540 
541         return tmp & DRIVE_STRENGTH_MASK;
542 }
543 
544 static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
545                                                         unsigned pin)
546 {
547         unsigned tmp = read_drive_strength(pio +
548                                         sama5d3_get_drive_register(pin), pin);
549 
550         /* SAMA5 strength is 1:1 with our defines,
551          * except 0 is equivalent to low per datasheet */
552         if (!tmp)
553                 tmp = DRIVE_STRENGTH_LOW;
554 
555         return tmp;
556 }
557 
558 static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
559                                                         unsigned pin)
560 {
561         unsigned tmp = read_drive_strength(pio +
562                                 at91sam9x5_get_drive_register(pin), pin);
563 
564         /* strength is inverse in SAM9x5s hardware with the pinctrl defines
565          * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
566         tmp = DRIVE_STRENGTH_HI - tmp;
567 
568         return tmp;
569 }
570 
571 static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
572 {
573         unsigned tmp = readl_relaxed(reg);
574         unsigned shift = two_bit_pin_value_shift_amount(pin);
575 
576         tmp &= ~(DRIVE_STRENGTH_MASK  <<  shift);
577         tmp |= strength << shift;
578 
579         writel_relaxed(tmp, reg);
580 }
581 
582 static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin,
583                                                 u32 setting)
584 {
585         /* do nothing if setting is zero */
586         if (!setting)
587                 return;
588 
589         /* strength is 1 to 1 with setting for SAMA5 */
590         set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting);
591 }
592 
593 static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
594                                                 u32 setting)
595 {
596         /* do nothing if setting is zero */
597         if (!setting)
598                 return;
599 
600         /* strength is inverse on SAM9x5s with our defines
601          * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
602         setting = DRIVE_STRENGTH_HI - setting;
603 
604         set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
605                                 setting);
606 }
607 
608 static struct at91_pinctrl_mux_ops at91rm9200_ops = {
609         .get_periph     = at91_mux_get_periph,
610         .mux_A_periph   = at91_mux_set_A_periph,
611         .mux_B_periph   = at91_mux_set_B_periph,
612         .get_deglitch   = at91_mux_get_deglitch,
613         .set_deglitch   = at91_mux_set_deglitch,
614         .irq_type       = gpio_irq_type,
615 };
616 
617 static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
618         .get_periph     = at91_mux_pio3_get_periph,
619         .mux_A_periph   = at91_mux_pio3_set_A_periph,
620         .mux_B_periph   = at91_mux_pio3_set_B_periph,
621         .mux_C_periph   = at91_mux_pio3_set_C_periph,
622         .mux_D_periph   = at91_mux_pio3_set_D_periph,
623         .get_deglitch   = at91_mux_pio3_get_deglitch,
624         .set_deglitch   = at91_mux_pio3_set_deglitch,
625         .get_debounce   = at91_mux_pio3_get_debounce,
626         .set_debounce   = at91_mux_pio3_set_debounce,
627         .get_pulldown   = at91_mux_pio3_get_pulldown,
628         .set_pulldown   = at91_mux_pio3_set_pulldown,
629         .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
630         .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
631         .get_drivestrength = at91_mux_sam9x5_get_drivestrength,
632         .set_drivestrength = at91_mux_sam9x5_set_drivestrength,
633         .irq_type       = alt_gpio_irq_type,
634 };
635 
636 static struct at91_pinctrl_mux_ops sama5d3_ops = {
637         .get_periph     = at91_mux_pio3_get_periph,
638         .mux_A_periph   = at91_mux_pio3_set_A_periph,
639         .mux_B_periph   = at91_mux_pio3_set_B_periph,
640         .mux_C_periph   = at91_mux_pio3_set_C_periph,
641         .mux_D_periph   = at91_mux_pio3_set_D_periph,
642         .get_deglitch   = at91_mux_pio3_get_deglitch,
643         .set_deglitch   = at91_mux_pio3_set_deglitch,
644         .get_debounce   = at91_mux_pio3_get_debounce,
645         .set_debounce   = at91_mux_pio3_set_debounce,
646         .get_pulldown   = at91_mux_pio3_get_pulldown,
647         .set_pulldown   = at91_mux_pio3_set_pulldown,
648         .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
649         .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
650         .get_drivestrength = at91_mux_sama5d3_get_drivestrength,
651         .set_drivestrength = at91_mux_sama5d3_set_drivestrength,
652         .irq_type       = alt_gpio_irq_type,
653 };
654 
655 static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
656 {
657         if (pin->mux) {
658                 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n",
659                         pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
660         } else {
661                 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n",
662                         pin->bank + 'A', pin->pin, pin->conf);
663         }
664 }
665 
666 static int pin_check_config(struct at91_pinctrl *info, const char *name,
667                             int index, const struct at91_pmx_pin *pin)
668 {
669         int mux;
670 
671         /* check if it's a valid config */
672         if (pin->bank >= gpio_banks) {
673                 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
674                         name, index, pin->bank, gpio_banks);
675                 return -EINVAL;
676         }
677 
678         if (!gpio_chips[pin->bank]) {
679                 dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n",
680                         name, index, pin->bank);
681                 return -ENXIO;
682         }
683 
684         if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
685                 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
686                         name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
687                 return -EINVAL;
688         }
689 
690         if (!pin->mux)
691                 return 0;
692 
693         mux = pin->mux - 1;
694 
695         if (mux >= info->nmux) {
696                 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
697                         name, index, mux, info->nmux);
698                 return -EINVAL;
699         }
700 
701         if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
702                 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
703                         name, index, mux, pin->bank + 'A', pin->pin);
704                 return -EINVAL;
705         }
706 
707         return 0;
708 }
709 
710 static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
711 {
712         writel_relaxed(mask, pio + PIO_PDR);
713 }
714 
715 static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
716 {
717         writel_relaxed(mask, pio + PIO_PER);
718         writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
719 }
720 
721 static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
722                         unsigned group)
723 {
724         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
725         const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
726         const struct at91_pmx_pin *pin;
727         uint32_t npins = info->groups[group].npins;
728         int i, ret;
729         unsigned mask;
730         void __iomem *pio;
731 
732         dev_dbg(info->dev, "enable function %s group %s\n",
733                 info->functions[selector].name, info->groups[group].name);
734 
735         /* first check that all the pins of the group are valid with a valid
736          * parameter */
737         for (i = 0; i < npins; i++) {
738                 pin = &pins_conf[i];
739                 ret = pin_check_config(info, info->groups[group].name, i, pin);
740                 if (ret)
741                         return ret;
742         }
743 
744         for (i = 0; i < npins; i++) {
745                 pin = &pins_conf[i];
746                 at91_pin_dbg(info->dev, pin);
747                 pio = pin_to_controller(info, pin->bank);
748 
749                 if (!pio)
750                         continue;
751 
752                 mask = pin_to_mask(pin->pin);
753                 at91_mux_disable_interrupt(pio, mask);
754                 switch (pin->mux) {
755                 case AT91_MUX_GPIO:
756                         at91_mux_gpio_enable(pio, mask, 1);
757                         break;
758                 case AT91_MUX_PERIPH_A:
759                         info->ops->mux_A_periph(pio, mask);
760                         break;
761                 case AT91_MUX_PERIPH_B:
762                         info->ops->mux_B_periph(pio, mask);
763                         break;
764                 case AT91_MUX_PERIPH_C:
765                         if (!info->ops->mux_C_periph)
766                                 return -EINVAL;
767                         info->ops->mux_C_periph(pio, mask);
768                         break;
769                 case AT91_MUX_PERIPH_D:
770                         if (!info->ops->mux_D_periph)
771                                 return -EINVAL;
772                         info->ops->mux_D_periph(pio, mask);
773                         break;
774                 }
775                 if (pin->mux)
776                         at91_mux_gpio_disable(pio, mask);
777         }
778 
779         return 0;
780 }
781 
782 static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
783 {
784         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
785 
786         return info->nfunctions;
787 }
788 
789 static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
790                                           unsigned selector)
791 {
792         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
793 
794         return info->functions[selector].name;
795 }
796 
797 static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
798                                const char * const **groups,
799                                unsigned * const num_groups)
800 {
801         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
802 
803         *groups = info->functions[selector].groups;
804         *num_groups = info->functions[selector].ngroups;
805 
806         return 0;
807 }
808 
809 static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
810                                     struct pinctrl_gpio_range *range,
811                                     unsigned offset)
812 {
813         struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
814         struct at91_gpio_chip *at91_chip;
815         struct gpio_chip *chip;
816         unsigned mask;
817 
818         if (!range) {
819                 dev_err(npct->dev, "invalid range\n");
820                 return -EINVAL;
821         }
822         if (!range->gc) {
823                 dev_err(npct->dev, "missing GPIO chip in range\n");
824                 return -EINVAL;
825         }
826         chip = range->gc;
827         at91_chip = gpiochip_get_data(chip);
828 
829         dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
830 
831         mask = 1 << (offset - chip->base);
832 
833         dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
834                 offset, 'A' + range->id, offset - chip->base, mask);
835 
836         writel_relaxed(mask, at91_chip->regbase + PIO_PER);
837 
838         return 0;
839 }
840 
841 static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
842                                    struct pinctrl_gpio_range *range,
843                                    unsigned offset)
844 {
845         struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
846 
847         dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
848         /* Set the pin to some default state, GPIO is usually default */
849 }
850 
851 static const struct pinmux_ops at91_pmx_ops = {
852         .get_functions_count    = at91_pmx_get_funcs_count,
853         .get_function_name      = at91_pmx_get_func_name,
854         .get_function_groups    = at91_pmx_get_groups,
855         .set_mux                = at91_pmx_set,
856         .gpio_request_enable    = at91_gpio_request_enable,
857         .gpio_disable_free      = at91_gpio_disable_free,
858 };
859 
860 static int at91_pinconf_get(struct pinctrl_dev *pctldev,
861                              unsigned pin_id, unsigned long *config)
862 {
863         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
864         void __iomem *pio;
865         unsigned pin;
866         int div;
867         bool out;
868 
869         *config = 0;
870         dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id);
871         pio = pin_to_controller(info, pin_to_bank(pin_id));
872 
873         if (!pio)
874                 return -EINVAL;
875 
876         pin = pin_id % MAX_NB_GPIO_PER_BANK;
877 
878         if (at91_mux_get_multidrive(pio, pin))
879                 *config |= MULTI_DRIVE;
880 
881         if (at91_mux_get_pullup(pio, pin))
882                 *config |= PULL_UP;
883 
884         if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
885                 *config |= DEGLITCH;
886         if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
887                 *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
888         if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
889                 *config |= PULL_DOWN;
890         if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
891                 *config |= DIS_SCHMIT;
892         if (info->ops->get_drivestrength)
893                 *config |= (info->ops->get_drivestrength(pio, pin)
894                                 << DRIVE_STRENGTH_SHIFT);
895         if (at91_mux_get_output(pio, pin, &out))
896                 *config |= OUTPUT | (out << OUTPUT_VAL_SHIFT);
897 
898         return 0;
899 }
900 
901 static int at91_pinconf_set(struct pinctrl_dev *pctldev,
902                              unsigned pin_id, unsigned long *configs,
903                              unsigned num_configs)
904 {
905         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
906         unsigned mask;
907         void __iomem *pio;
908         int i;
909         unsigned long config;
910         unsigned pin;
911 
912         for (i = 0; i < num_configs; i++) {
913                 config = configs[i];
914 
915                 dev_dbg(info->dev,
916                         "%s:%d, pin_id=%d, config=0x%lx",
917                         __func__, __LINE__, pin_id, config);
918                 pio = pin_to_controller(info, pin_to_bank(pin_id));
919 
920                 if (!pio)
921                         return -EINVAL;
922 
923                 pin = pin_id % MAX_NB_GPIO_PER_BANK;
924                 mask = pin_to_mask(pin);
925 
926                 if (config & PULL_UP && config & PULL_DOWN)
927                         return -EINVAL;
928 
929                 at91_mux_set_output(pio, mask, config & OUTPUT,
930                                     (config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT);
931                 at91_mux_set_pullup(pio, mask, config & PULL_UP);
932                 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
933                 if (info->ops->set_deglitch)
934                         info->ops->set_deglitch(pio, mask, config & DEGLITCH);
935                 if (info->ops->set_debounce)
936                         info->ops->set_debounce(pio, mask, config & DEBOUNCE,
937                                 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
938                 if (info->ops->set_pulldown)
939                         info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
940                 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
941                         info->ops->disable_schmitt_trig(pio, mask);
942                 if (info->ops->set_drivestrength)
943                         info->ops->set_drivestrength(pio, pin,
944                                 (config & DRIVE_STRENGTH)
945                                         >> DRIVE_STRENGTH_SHIFT);
946 
947         } /* for each config */
948 
949         return 0;
950 }
951 
952 #define DBG_SHOW_FLAG(flag) do {                \
953         if (config & flag) {                    \
954                 if (num_conf)                   \
955                         seq_puts(s, "|");       \
956                 seq_puts(s, #flag);             \
957                 num_conf++;                     \
958         }                                       \
959 } while (0)
960 
961 #define DBG_SHOW_FLAG_MASKED(mask,flag) do {    \
962         if ((config & mask) == flag) {          \
963                 if (num_conf)                   \
964                         seq_puts(s, "|");       \
965                 seq_puts(s, #flag);             \
966                 num_conf++;                     \
967         }                                       \
968 } while (0)
969 
970 static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
971                                    struct seq_file *s, unsigned pin_id)
972 {
973         unsigned long config;
974         int val, num_conf = 0;
975 
976         at91_pinconf_get(pctldev, pin_id, &config);
977 
978         DBG_SHOW_FLAG(MULTI_DRIVE);
979         DBG_SHOW_FLAG(PULL_UP);
980         DBG_SHOW_FLAG(PULL_DOWN);
981         DBG_SHOW_FLAG(DIS_SCHMIT);
982         DBG_SHOW_FLAG(DEGLITCH);
983         DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
984         DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
985         DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
986         DBG_SHOW_FLAG(DEBOUNCE);
987         if (config & DEBOUNCE) {
988                 val = config >> DEBOUNCE_VAL_SHIFT;
989                 seq_printf(s, "(%d)", val);
990         }
991 
992         return;
993 }
994 
995 static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
996                                          struct seq_file *s, unsigned group)
997 {
998 }
999 
1000 static const struct pinconf_ops at91_pinconf_ops = {
1001         .pin_config_get                 = at91_pinconf_get,
1002         .pin_config_set                 = at91_pinconf_set,
1003         .pin_config_dbg_show            = at91_pinconf_dbg_show,
1004         .pin_config_group_dbg_show      = at91_pinconf_group_dbg_show,
1005 };
1006 
1007 static struct pinctrl_desc at91_pinctrl_desc = {
1008         .pctlops        = &at91_pctrl_ops,
1009         .pmxops         = &at91_pmx_ops,
1010         .confops        = &at91_pinconf_ops,
1011         .owner          = THIS_MODULE,
1012 };
1013 
1014 static const char *gpio_compat = "atmel,at91rm9200-gpio";
1015 
1016 static void at91_pinctrl_child_count(struct at91_pinctrl *info,
1017                                      struct device_node *np)
1018 {
1019         struct device_node *child;
1020 
1021         for_each_child_of_node(np, child) {
1022                 if (of_device_is_compatible(child, gpio_compat)) {
1023                         if (of_device_is_available(child))
1024                                 info->nactive_banks++;
1025                 } else {
1026                         info->nfunctions++;
1027                         info->ngroups += of_get_child_count(child);
1028                 }
1029         }
1030 }
1031 
1032 static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
1033                                  struct device_node *np)
1034 {
1035         int ret = 0;
1036         int size;
1037         const __be32 *list;
1038 
1039         list = of_get_property(np, "atmel,mux-mask", &size);
1040         if (!list) {
1041                 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1042                 return -EINVAL;
1043         }
1044 
1045         size /= sizeof(*list);
1046         if (!size || size % gpio_banks) {
1047                 dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks);
1048                 return -EINVAL;
1049         }
1050         info->nmux = size / gpio_banks;
1051 
1052         info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);
1053         if (!info->mux_mask) {
1054                 dev_err(info->dev, "could not alloc mux_mask\n");
1055                 return -ENOMEM;
1056         }
1057 
1058         ret = of_property_read_u32_array(np, "atmel,mux-mask",
1059                                           info->mux_mask, size);
1060         if (ret)
1061                 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1062         return ret;
1063 }
1064 
1065 static int at91_pinctrl_parse_groups(struct device_node *np,
1066                                      struct at91_pin_group *grp,
1067                                      struct at91_pinctrl *info, u32 index)
1068 {
1069         struct at91_pmx_pin *pin;
1070         int size;
1071         const __be32 *list;
1072         int i, j;
1073 
1074         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1075 
1076         /* Initialise group */
1077         grp->name = np->name;
1078 
1079         /*
1080          * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
1081          * do sanity check and calculate pins number
1082          */
1083         list = of_get_property(np, "atmel,pins", &size);
1084         /* we do not check return since it's safe node passed down */
1085         size /= sizeof(*list);
1086         if (!size || size % 4) {
1087                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1088                 return -EINVAL;
1089         }
1090 
1091         grp->npins = size / 4;
1092         pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin),
1093                                 GFP_KERNEL);
1094         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1095                                 GFP_KERNEL);
1096         if (!grp->pins_conf || !grp->pins)
1097                 return -ENOMEM;
1098 
1099         for (i = 0, j = 0; i < size; i += 4, j++) {
1100                 pin->bank = be32_to_cpu(*list++);
1101                 pin->pin = be32_to_cpu(*list++);
1102                 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
1103                 pin->mux = be32_to_cpu(*list++);
1104                 pin->conf = be32_to_cpu(*list++);
1105 
1106                 at91_pin_dbg(info->dev, pin);
1107                 pin++;
1108         }
1109 
1110         return 0;
1111 }
1112 
1113 static int at91_pinctrl_parse_functions(struct device_node *np,
1114                                         struct at91_pinctrl *info, u32 index)
1115 {
1116         struct device_node *child;
1117         struct at91_pmx_func *func;
1118         struct at91_pin_group *grp;
1119         int ret;
1120         static u32 grp_index;
1121         u32 i = 0;
1122 
1123         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1124 
1125         func = &info->functions[index];
1126 
1127         /* Initialise function */
1128         func->name = np->name;
1129         func->ngroups = of_get_child_count(np);
1130         if (func->ngroups == 0) {
1131                 dev_err(info->dev, "no groups defined\n");
1132                 return -EINVAL;
1133         }
1134         func->groups = devm_kzalloc(info->dev,
1135                         func->ngroups * sizeof(char *), GFP_KERNEL);
1136         if (!func->groups)
1137                 return -ENOMEM;
1138 
1139         for_each_child_of_node(np, child) {
1140                 func->groups[i] = child->name;
1141                 grp = &info->groups[grp_index++];
1142                 ret = at91_pinctrl_parse_groups(child, grp, info, i++);
1143                 if (ret) {
1144                         of_node_put(child);
1145                         return ret;
1146                 }
1147         }
1148 
1149         return 0;
1150 }
1151 
1152 static const struct of_device_id at91_pinctrl_of_match[] = {
1153         { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
1154         { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
1155         { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
1156         { /* sentinel */ }
1157 };
1158 
1159 static int at91_pinctrl_probe_dt(struct platform_device *pdev,
1160                                  struct at91_pinctrl *info)
1161 {
1162         int ret = 0;
1163         int i, j;
1164         uint32_t *tmp;
1165         struct device_node *np = pdev->dev.of_node;
1166         struct device_node *child;
1167 
1168         if (!np)
1169                 return -ENODEV;
1170 
1171         info->dev = &pdev->dev;
1172         info->ops = (struct at91_pinctrl_mux_ops *)
1173                 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
1174         at91_pinctrl_child_count(info, np);
1175 
1176         if (gpio_banks < 1) {
1177                 dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n");
1178                 return -EINVAL;
1179         }
1180 
1181         ret = at91_pinctrl_mux_mask(info, np);
1182         if (ret)
1183                 return ret;
1184 
1185         dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
1186 
1187         dev_dbg(&pdev->dev, "mux-mask\n");
1188         tmp = info->mux_mask;
1189         for (i = 0; i < gpio_banks; i++) {
1190                 for (j = 0; j < info->nmux; j++, tmp++) {
1191                         dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
1192                 }
1193         }
1194 
1195         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1196         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1197         info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func),
1198                                         GFP_KERNEL);
1199         if (!info->functions)
1200                 return -ENOMEM;
1201 
1202         info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group),
1203                                         GFP_KERNEL);
1204         if (!info->groups)
1205                 return -ENOMEM;
1206 
1207         dev_dbg(&pdev->dev, "nbanks = %d\n", gpio_banks);
1208         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1209         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1210 
1211         i = 0;
1212 
1213         for_each_child_of_node(np, child) {
1214                 if (of_device_is_compatible(child, gpio_compat))
1215                         continue;
1216                 ret = at91_pinctrl_parse_functions(child, info, i++);
1217                 if (ret) {
1218                         dev_err(&pdev->dev, "failed to parse function\n");
1219                         of_node_put(child);
1220                         return ret;
1221                 }
1222         }
1223 
1224         return 0;
1225 }
1226 
1227 static int at91_pinctrl_probe(struct platform_device *pdev)
1228 {
1229         struct at91_pinctrl *info;
1230         struct pinctrl_pin_desc *pdesc;
1231         int ret, i, j, k, ngpio_chips_enabled = 0;
1232 
1233         info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1234         if (!info)
1235                 return -ENOMEM;
1236 
1237         ret = at91_pinctrl_probe_dt(pdev, info);
1238         if (ret)
1239                 return ret;
1240 
1241         /*
1242          * We need all the GPIO drivers to probe FIRST, or we will not be able
1243          * to obtain references to the struct gpio_chip * for them, and we
1244          * need this to proceed.
1245          */
1246         for (i = 0; i < gpio_banks; i++)
1247                 if (gpio_chips[i])
1248                         ngpio_chips_enabled++;
1249 
1250         if (ngpio_chips_enabled < info->nactive_banks) {
1251                 dev_warn(&pdev->dev,
1252                          "All GPIO chips are not registered yet (%d/%d)\n",
1253                          ngpio_chips_enabled, info->nactive_banks);
1254                 devm_kfree(&pdev->dev, info);
1255                 return -EPROBE_DEFER;
1256         }
1257 
1258         at91_pinctrl_desc.name = dev_name(&pdev->dev);
1259         at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK;
1260         at91_pinctrl_desc.pins = pdesc =
1261                 devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL);
1262 
1263         if (!at91_pinctrl_desc.pins)
1264                 return -ENOMEM;
1265 
1266         for (i = 0, k = 0; i < gpio_banks; i++) {
1267                 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1268                         pdesc->number = k;
1269                         pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
1270                         pdesc++;
1271                 }
1272         }
1273 
1274         platform_set_drvdata(pdev, info);
1275         info->pctl = devm_pinctrl_register(&pdev->dev, &at91_pinctrl_desc,
1276                                            info);
1277 
1278         if (IS_ERR(info->pctl)) {
1279                 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
1280                 return PTR_ERR(info->pctl);
1281         }
1282 
1283         /* We will handle a range of GPIO pins */
1284         for (i = 0; i < gpio_banks; i++)
1285                 if (gpio_chips[i])
1286                         pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
1287 
1288         dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
1289 
1290         return 0;
1291 }
1292 
1293 static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1294 {
1295         struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1296         void __iomem *pio = at91_gpio->regbase;
1297         unsigned mask = 1 << offset;
1298         u32 osr;
1299 
1300         osr = readl_relaxed(pio + PIO_OSR);
1301         return !(osr & mask);
1302 }
1303 
1304 static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1305 {
1306         struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1307         void __iomem *pio = at91_gpio->regbase;
1308         unsigned mask = 1 << offset;
1309 
1310         writel_relaxed(mask, pio + PIO_ODR);
1311         return 0;
1312 }
1313 
1314 static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1315 {
1316         struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1317         void __iomem *pio = at91_gpio->regbase;
1318         unsigned mask = 1 << offset;
1319         u32 pdsr;
1320 
1321         pdsr = readl_relaxed(pio + PIO_PDSR);
1322         return (pdsr & mask) != 0;
1323 }
1324 
1325 static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1326                                 int val)
1327 {
1328         struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1329         void __iomem *pio = at91_gpio->regbase;
1330         unsigned mask = 1 << offset;
1331 
1332         writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1333 }
1334 
1335 static void at91_gpio_set_multiple(struct gpio_chip *chip,
1336                                       unsigned long *mask, unsigned long *bits)
1337 {
1338         struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1339         void __iomem *pio = at91_gpio->regbase;
1340 
1341 #define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1))
1342         /* Mask additionally to ngpio as not all GPIO controllers have 32 pins */
1343         uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio);
1344         uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio);
1345 
1346         writel_relaxed(set_mask, pio + PIO_SODR);
1347         writel_relaxed(clear_mask, pio + PIO_CODR);
1348 }
1349 
1350 static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1351                                 int val)
1352 {
1353         struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1354         void __iomem *pio = at91_gpio->regbase;
1355         unsigned mask = 1 << offset;
1356 
1357         writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1358         writel_relaxed(mask, pio + PIO_OER);
1359 
1360         return 0;
1361 }
1362 
1363 #ifdef CONFIG_DEBUG_FS
1364 static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1365 {
1366         enum at91_mux mode;
1367         int i;
1368         struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1369         void __iomem *pio = at91_gpio->regbase;
1370 
1371         for (i = 0; i < chip->ngpio; i++) {
1372                 unsigned mask = pin_to_mask(i);
1373                 const char *gpio_label;
1374 
1375                 gpio_label = gpiochip_is_requested(chip, i);
1376                 if (!gpio_label)
1377                         continue;
1378                 mode = at91_gpio->ops->get_periph(pio, mask);
1379                 seq_printf(s, "[%s] GPIO%s%d: ",
1380                            gpio_label, chip->label, i);
1381                 if (mode == AT91_MUX_GPIO) {
1382                         seq_printf(s, "[gpio] ");
1383                         seq_printf(s, "%s ",
1384                                       readl_relaxed(pio + PIO_OSR) & mask ?
1385                                       "output" : "input");
1386                         seq_printf(s, "%s\n",
1387                                       readl_relaxed(pio + PIO_PDSR) & mask ?
1388                                       "set" : "clear");
1389                 } else {
1390                         seq_printf(s, "[periph %c]\n",
1391                                    mode + 'A' - 1);
1392                 }
1393         }
1394 }
1395 #else
1396 #define at91_gpio_dbg_show      NULL
1397 #endif
1398 
1399 /* Several AIC controller irqs are dispatched through this GPIO handler.
1400  * To use any AT91_PIN_* as an externally triggered IRQ, first call
1401  * at91_set_gpio_input() then maybe enable its glitch filter.
1402  * Then just request_irq() with the pin ID; it works like any ARM IRQ
1403  * handler.
1404  * First implementation always triggers on rising and falling edges
1405  * whereas the newer PIO3 can be additionally configured to trigger on
1406  * level, edge with any polarity.
1407  *
1408  * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1409  * configuring them with at91_set_a_periph() or at91_set_b_periph().
1410  * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1411  */
1412 
1413 static void gpio_irq_mask(struct irq_data *d)
1414 {
1415         struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1416         void __iomem    *pio = at91_gpio->regbase;
1417         unsigned        mask = 1 << d->hwirq;
1418 
1419         if (pio)
1420                 writel_relaxed(mask, pio + PIO_IDR);
1421 }
1422 
1423 static void gpio_irq_unmask(struct irq_data *d)
1424 {
1425         struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1426         void __iomem    *pio = at91_gpio->regbase;
1427         unsigned        mask = 1 << d->hwirq;
1428 
1429         if (pio)
1430                 writel_relaxed(mask, pio + PIO_IER);
1431 }
1432 
1433 static int gpio_irq_type(struct irq_data *d, unsigned type)
1434 {
1435         switch (type) {
1436         case IRQ_TYPE_NONE:
1437         case IRQ_TYPE_EDGE_BOTH:
1438                 return 0;
1439         default:
1440                 return -EINVAL;
1441         }
1442 }
1443 
1444 /* Alternate irq type for PIO3 support */
1445 static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1446 {
1447         struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1448         void __iomem    *pio = at91_gpio->regbase;
1449         unsigned        mask = 1 << d->hwirq;
1450 
1451         switch (type) {
1452         case IRQ_TYPE_EDGE_RISING:
1453                 irq_set_handler_locked(d, handle_simple_irq);
1454                 writel_relaxed(mask, pio + PIO_ESR);
1455                 writel_relaxed(mask, pio + PIO_REHLSR);
1456                 break;
1457         case IRQ_TYPE_EDGE_FALLING:
1458                 irq_set_handler_locked(d, handle_simple_irq);
1459                 writel_relaxed(mask, pio + PIO_ESR);
1460                 writel_relaxed(mask, pio + PIO_FELLSR);
1461                 break;
1462         case IRQ_TYPE_LEVEL_LOW:
1463                 irq_set_handler_locked(d, handle_level_irq);
1464                 writel_relaxed(mask, pio + PIO_LSR);
1465                 writel_relaxed(mask, pio + PIO_FELLSR);
1466                 break;
1467         case IRQ_TYPE_LEVEL_HIGH:
1468                 irq_set_handler_locked(d, handle_level_irq);
1469                 writel_relaxed(mask, pio + PIO_LSR);
1470                 writel_relaxed(mask, pio + PIO_REHLSR);
1471                 break;
1472         case IRQ_TYPE_EDGE_BOTH:
1473                 /*
1474                  * disable additional interrupt modes:
1475                  * fall back to default behavior
1476                  */
1477                 irq_set_handler_locked(d, handle_simple_irq);
1478                 writel_relaxed(mask, pio + PIO_AIMDR);
1479                 return 0;
1480         case IRQ_TYPE_NONE:
1481         default:
1482                 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
1483                 return -EINVAL;
1484         }
1485 
1486         /* enable additional interrupt modes */
1487         writel_relaxed(mask, pio + PIO_AIMER);
1488 
1489         return 0;
1490 }
1491 
1492 static void gpio_irq_ack(struct irq_data *d)
1493 {
1494         /* the interrupt is already cleared before by reading ISR */
1495 }
1496 
1497 #ifdef CONFIG_PM
1498 
1499 static u32 wakeups[MAX_GPIO_BANKS];
1500 static u32 backups[MAX_GPIO_BANKS];
1501 
1502 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1503 {
1504         struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1505         unsigned        bank = at91_gpio->pioc_idx;
1506         unsigned mask = 1 << d->hwirq;
1507 
1508         if (unlikely(bank >= MAX_GPIO_BANKS))
1509                 return -EINVAL;
1510 
1511         if (state)
1512                 wakeups[bank] |= mask;
1513         else
1514                 wakeups[bank] &= ~mask;
1515 
1516         irq_set_irq_wake(at91_gpio->pioc_virq, state);
1517 
1518         return 0;
1519 }
1520 
1521 void at91_pinctrl_gpio_suspend(void)
1522 {
1523         int i;
1524 
1525         for (i = 0; i < gpio_banks; i++) {
1526                 void __iomem  *pio;
1527 
1528                 if (!gpio_chips[i])
1529                         continue;
1530 
1531                 pio = gpio_chips[i]->regbase;
1532 
1533                 backups[i] = readl_relaxed(pio + PIO_IMR);
1534                 writel_relaxed(backups[i], pio + PIO_IDR);
1535                 writel_relaxed(wakeups[i], pio + PIO_IER);
1536 
1537                 if (!wakeups[i])
1538                         clk_disable_unprepare(gpio_chips[i]->clock);
1539                 else
1540                         printk(KERN_DEBUG "GPIO-%c may wake for %08x\n",
1541                                'A'+i, wakeups[i]);
1542         }
1543 }
1544 
1545 void at91_pinctrl_gpio_resume(void)
1546 {
1547         int i;
1548 
1549         for (i = 0; i < gpio_banks; i++) {
1550                 void __iomem  *pio;
1551 
1552                 if (!gpio_chips[i])
1553                         continue;
1554 
1555                 pio = gpio_chips[i]->regbase;
1556 
1557                 if (!wakeups[i])
1558                         clk_prepare_enable(gpio_chips[i]->clock);
1559 
1560                 writel_relaxed(wakeups[i], pio + PIO_IDR);
1561                 writel_relaxed(backups[i], pio + PIO_IER);
1562         }
1563 }
1564 
1565 #else
1566 #define gpio_irq_set_wake       NULL
1567 #endif /* CONFIG_PM */
1568 
1569 static struct irq_chip gpio_irqchip = {
1570         .name           = "GPIO",
1571         .irq_ack        = gpio_irq_ack,
1572         .irq_disable    = gpio_irq_mask,
1573         .irq_mask       = gpio_irq_mask,
1574         .irq_unmask     = gpio_irq_unmask,
1575         /* .irq_set_type is set dynamically */
1576         .irq_set_wake   = gpio_irq_set_wake,
1577 };
1578 
1579 static void gpio_irq_handler(struct irq_desc *desc)
1580 {
1581         struct irq_chip *chip = irq_desc_get_chip(desc);
1582         struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc);
1583         struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gpio_chip);
1584         void __iomem    *pio = at91_gpio->regbase;
1585         unsigned long   isr;
1586         int             n;
1587 
1588         chained_irq_enter(chip, desc);
1589         for (;;) {
1590                 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
1591                  * When there are none pending, we're finished unless we need
1592                  * to process multiple banks (like ID_PIOCDE on sam9263).
1593                  */
1594                 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1595                 if (!isr) {
1596                         if (!at91_gpio->next)
1597                                 break;
1598                         at91_gpio = at91_gpio->next;
1599                         pio = at91_gpio->regbase;
1600                         gpio_chip = &at91_gpio->chip;
1601                         continue;
1602                 }
1603 
1604                 for_each_set_bit(n, &isr, BITS_PER_LONG) {
1605                         generic_handle_irq(irq_find_mapping(
1606                                            gpio_chip->irqdomain, n));
1607                 }
1608         }
1609         chained_irq_exit(chip, desc);
1610         /* now it may re-trigger */
1611 }
1612 
1613 static int at91_gpio_of_irq_setup(struct platform_device *pdev,
1614                                   struct at91_gpio_chip *at91_gpio)
1615 {
1616         struct gpio_chip        *gpiochip_prev = NULL;
1617         struct at91_gpio_chip   *prev = NULL;
1618         struct irq_data         *d = irq_get_irq_data(at91_gpio->pioc_virq);
1619         int ret, i;
1620 
1621         at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1622 
1623         /* Setup proper .irq_set_type function */
1624         gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type;
1625 
1626         /* Disable irqs of this PIO controller */
1627         writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1628 
1629         /*
1630          * Let the generic code handle this edge IRQ, the the chained
1631          * handler will perform the actual work of handling the parent
1632          * interrupt.
1633          */
1634         ret = gpiochip_irqchip_add(&at91_gpio->chip,
1635                                    &gpio_irqchip,
1636                                    0,
1637                                    handle_edge_irq,
1638                                    IRQ_TYPE_NONE);
1639         if (ret) {
1640                 dev_err(&pdev->dev, "at91_gpio.%d: Couldn't add irqchip to gpiochip.\n",
1641                         at91_gpio->pioc_idx);
1642                 return ret;
1643         }
1644 
1645         /* The top level handler handles one bank of GPIOs, except
1646          * on some SoC it can handle up to three...
1647          * We only set up the handler for the first of the list.
1648          */
1649         gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq);
1650         if (!gpiochip_prev) {
1651                 /* Then register the chain on the parent IRQ */
1652                 gpiochip_set_chained_irqchip(&at91_gpio->chip,
1653                                              &gpio_irqchip,
1654                                              at91_gpio->pioc_virq,
1655                                              gpio_irq_handler);
1656                 return 0;
1657         }
1658 
1659         prev = gpiochip_get_data(gpiochip_prev);
1660 
1661         /* we can only have 2 banks before */
1662         for (i = 0; i < 2; i++) {
1663                 if (prev->next) {
1664                         prev = prev->next;
1665                 } else {
1666                         prev->next = at91_gpio;
1667                         return 0;
1668                 }
1669         }
1670 
1671         return -EINVAL;
1672 }
1673 
1674 /* This structure is replicated for each GPIO block allocated at probe time */
1675 static const struct gpio_chip at91_gpio_template = {
1676         .request                = gpiochip_generic_request,
1677         .free                   = gpiochip_generic_free,
1678         .get_direction          = at91_gpio_get_direction,
1679         .direction_input        = at91_gpio_direction_input,
1680         .get                    = at91_gpio_get,
1681         .direction_output       = at91_gpio_direction_output,
1682         .set                    = at91_gpio_set,
1683         .set_multiple           = at91_gpio_set_multiple,
1684         .dbg_show               = at91_gpio_dbg_show,
1685         .can_sleep              = false,
1686         .ngpio                  = MAX_NB_GPIO_PER_BANK,
1687 };
1688 
1689 static const struct of_device_id at91_gpio_of_match[] = {
1690         { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1691         { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1692         { /* sentinel */ }
1693 };
1694 
1695 static int at91_gpio_probe(struct platform_device *pdev)
1696 {
1697         struct device_node *np = pdev->dev.of_node;
1698         struct resource *res;
1699         struct at91_gpio_chip *at91_chip = NULL;
1700         struct gpio_chip *chip;
1701         struct pinctrl_gpio_range *range;
1702         int ret = 0;
1703         int irq, i;
1704         int alias_idx = of_alias_get_id(np, "gpio");
1705         uint32_t ngpio;
1706         char **names;
1707 
1708         BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1709         if (gpio_chips[alias_idx]) {
1710                 ret = -EBUSY;
1711                 goto err;
1712         }
1713 
1714         irq = platform_get_irq(pdev, 0);
1715         if (irq < 0) {
1716                 ret = irq;
1717                 goto err;
1718         }
1719 
1720         at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
1721         if (!at91_chip) {
1722                 ret = -ENOMEM;
1723                 goto err;
1724         }
1725 
1726         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1727         at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res);
1728         if (IS_ERR(at91_chip->regbase)) {
1729                 ret = PTR_ERR(at91_chip->regbase);
1730                 goto err;
1731         }
1732 
1733         at91_chip->ops = (struct at91_pinctrl_mux_ops *)
1734                 of_match_device(at91_gpio_of_match, &pdev->dev)->data;
1735         at91_chip->pioc_virq = irq;
1736         at91_chip->pioc_idx = alias_idx;
1737 
1738         at91_chip->clock = devm_clk_get(&pdev->dev, NULL);
1739         if (IS_ERR(at91_chip->clock)) {
1740                 dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
1741                 ret = PTR_ERR(at91_chip->clock);
1742                 goto err;
1743         }
1744 
1745         ret = clk_prepare_enable(at91_chip->clock);
1746         if (ret) {
1747                 dev_err(&pdev->dev, "failed to prepare and enable clock, ignoring.\n");
1748                 goto clk_enable_err;
1749         }
1750 
1751         at91_chip->chip = at91_gpio_template;
1752 
1753         chip = &at91_chip->chip;
1754         chip->of_node = np;
1755         chip->label = dev_name(&pdev->dev);
1756         chip->parent = &pdev->dev;
1757         chip->owner = THIS_MODULE;
1758         chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1759 
1760         if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1761                 if (ngpio >= MAX_NB_GPIO_PER_BANK)
1762                         pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1763                                alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1764                 else
1765                         chip->ngpio = ngpio;
1766         }
1767 
1768         names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio,
1769                              GFP_KERNEL);
1770 
1771         if (!names) {
1772                 ret = -ENOMEM;
1773                 goto clk_enable_err;
1774         }
1775 
1776         for (i = 0; i < chip->ngpio; i++)
1777                 names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i);
1778 
1779         chip->names = (const char *const *)names;
1780 
1781         range = &at91_chip->range;
1782         range->name = chip->label;
1783         range->id = alias_idx;
1784         range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1785 
1786         range->npins = chip->ngpio;
1787         range->gc = chip;
1788 
1789         ret = gpiochip_add_data(chip, at91_chip);
1790         if (ret)
1791                 goto gpiochip_add_err;
1792 
1793         gpio_chips[alias_idx] = at91_chip;
1794         gpio_banks = max(gpio_banks, alias_idx + 1);
1795 
1796         ret = at91_gpio_of_irq_setup(pdev, at91_chip);
1797         if (ret)
1798                 goto irq_setup_err;
1799 
1800         dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1801 
1802         return 0;
1803 
1804 irq_setup_err:
1805         gpiochip_remove(chip);
1806 gpiochip_add_err:
1807 clk_enable_err:
1808         clk_disable_unprepare(at91_chip->clock);
1809 err:
1810         dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1811 
1812         return ret;
1813 }
1814 
1815 static struct platform_driver at91_gpio_driver = {
1816         .driver = {
1817                 .name = "gpio-at91",
1818                 .of_match_table = at91_gpio_of_match,
1819         },
1820         .probe = at91_gpio_probe,
1821 };
1822 
1823 static struct platform_driver at91_pinctrl_driver = {
1824         .driver = {
1825                 .name = "pinctrl-at91",
1826                 .of_match_table = at91_pinctrl_of_match,
1827         },
1828         .probe = at91_pinctrl_probe,
1829 };
1830 
1831 static struct platform_driver * const drivers[] = {
1832         &at91_gpio_driver,
1833         &at91_pinctrl_driver,
1834 };
1835 
1836 static int __init at91_pinctrl_init(void)
1837 {
1838         return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
1839 }
1840 arch_initcall(at91_pinctrl_init);
1841 

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