Version:  2.0.40 2.2.26 2.4.37 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2

Linux/drivers/phy/phy-twl4030-usb.c

  1 /*
  2  * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller
  3  *
  4  * Copyright (C) 2004-2007 Texas Instruments
  5  * Copyright (C) 2008 Nokia Corporation
  6  * Contact: Felipe Balbi <felipe.balbi@nokia.com>
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License, or
 11  * (at your option) any later version.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  * GNU General Public License for more details.
 17  *
 18  * You should have received a copy of the GNU General Public License
 19  * along with this program; if not, write to the Free Software
 20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 21  *
 22  * Current status:
 23  *      - HS USB ULPI mode works.
 24  *      - 3-pin mode support may be added in future.
 25  */
 26 
 27 #include <linux/module.h>
 28 #include <linux/init.h>
 29 #include <linux/interrupt.h>
 30 #include <linux/platform_device.h>
 31 #include <linux/workqueue.h>
 32 #include <linux/io.h>
 33 #include <linux/delay.h>
 34 #include <linux/usb/otg.h>
 35 #include <linux/phy/phy.h>
 36 #include <linux/pm_runtime.h>
 37 #include <linux/usb/musb-omap.h>
 38 #include <linux/usb/ulpi.h>
 39 #include <linux/i2c/twl.h>
 40 #include <linux/regulator/consumer.h>
 41 #include <linux/err.h>
 42 #include <linux/slab.h>
 43 
 44 /* Register defines */
 45 
 46 #define MCPC_CTRL                       0x30
 47 #define MCPC_CTRL_RTSOL                 (1 << 7)
 48 #define MCPC_CTRL_EXTSWR                (1 << 6)
 49 #define MCPC_CTRL_EXTSWC                (1 << 5)
 50 #define MCPC_CTRL_VOICESW               (1 << 4)
 51 #define MCPC_CTRL_OUT64K                (1 << 3)
 52 #define MCPC_CTRL_RTSCTSSW              (1 << 2)
 53 #define MCPC_CTRL_HS_UART               (1 << 0)
 54 
 55 #define MCPC_IO_CTRL                    0x33
 56 #define MCPC_IO_CTRL_MICBIASEN          (1 << 5)
 57 #define MCPC_IO_CTRL_CTS_NPU            (1 << 4)
 58 #define MCPC_IO_CTRL_RXD_PU             (1 << 3)
 59 #define MCPC_IO_CTRL_TXDTYP             (1 << 2)
 60 #define MCPC_IO_CTRL_CTSTYP             (1 << 1)
 61 #define MCPC_IO_CTRL_RTSTYP             (1 << 0)
 62 
 63 #define MCPC_CTRL2                      0x36
 64 #define MCPC_CTRL2_MCPC_CK_EN           (1 << 0)
 65 
 66 #define OTHER_FUNC_CTRL                 0x80
 67 #define OTHER_FUNC_CTRL_BDIS_ACON_EN    (1 << 4)
 68 #define OTHER_FUNC_CTRL_FIVEWIRE_MODE   (1 << 2)
 69 
 70 #define OTHER_IFC_CTRL                  0x83
 71 #define OTHER_IFC_CTRL_OE_INT_EN        (1 << 6)
 72 #define OTHER_IFC_CTRL_CEA2011_MODE     (1 << 5)
 73 #define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN      (1 << 4)
 74 #define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT       (1 << 3)
 75 #define OTHER_IFC_CTRL_HIZ_ULPI         (1 << 2)
 76 #define OTHER_IFC_CTRL_ALT_INT_REROUTE  (1 << 0)
 77 
 78 #define OTHER_INT_EN_RISE               0x86
 79 #define OTHER_INT_EN_FALL               0x89
 80 #define OTHER_INT_STS                   0x8C
 81 #define OTHER_INT_LATCH                 0x8D
 82 #define OTHER_INT_VB_SESS_VLD           (1 << 7)
 83 #define OTHER_INT_DM_HI                 (1 << 6) /* not valid for "latch" reg */
 84 #define OTHER_INT_DP_HI                 (1 << 5) /* not valid for "latch" reg */
 85 #define OTHER_INT_BDIS_ACON             (1 << 3) /* not valid for "fall" regs */
 86 #define OTHER_INT_MANU                  (1 << 1)
 87 #define OTHER_INT_ABNORMAL_STRESS       (1 << 0)
 88 
 89 #define ID_STATUS                       0x96
 90 #define ID_RES_FLOAT                    (1 << 4)
 91 #define ID_RES_440K                     (1 << 3)
 92 #define ID_RES_200K                     (1 << 2)
 93 #define ID_RES_102K                     (1 << 1)
 94 #define ID_RES_GND                      (1 << 0)
 95 
 96 #define POWER_CTRL                      0xAC
 97 #define POWER_CTRL_OTG_ENAB             (1 << 5)
 98 
 99 #define OTHER_IFC_CTRL2                 0xAF
100 #define OTHER_IFC_CTRL2_ULPI_STP_LOW    (1 << 4)
101 #define OTHER_IFC_CTRL2_ULPI_TXEN_POL   (1 << 3)
102 #define OTHER_IFC_CTRL2_ULPI_4PIN_2430  (1 << 2)
103 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK     (3 << 0) /* bits 0 and 1 */
104 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N    (0 << 0)
105 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N    (1 << 0)
106 
107 #define REG_CTRL_EN                     0xB2
108 #define REG_CTRL_ERROR                  0xB5
109 #define ULPI_I2C_CONFLICT_INTEN         (1 << 0)
110 
111 #define OTHER_FUNC_CTRL2                0xB8
112 #define OTHER_FUNC_CTRL2_VBAT_TIMER_EN  (1 << 0)
113 
114 /* following registers do not have separate _clr and _set registers */
115 #define VBUS_DEBOUNCE                   0xC0
116 #define ID_DEBOUNCE                     0xC1
117 #define VBAT_TIMER                      0xD3
118 #define PHY_PWR_CTRL                    0xFD
119 #define PHY_PWR_PHYPWD                  (1 << 0)
120 #define PHY_CLK_CTRL                    0xFE
121 #define PHY_CLK_CTRL_CLOCKGATING_EN     (1 << 2)
122 #define PHY_CLK_CTRL_CLK32K_EN          (1 << 1)
123 #define REQ_PHY_DPLL_CLK                (1 << 0)
124 #define PHY_CLK_CTRL_STS                0xFF
125 #define PHY_DPLL_CLK                    (1 << 0)
126 
127 /* In module TWL_MODULE_PM_MASTER */
128 #define STS_HW_CONDITIONS               0x0F
129 
130 /* In module TWL_MODULE_PM_RECEIVER */
131 #define VUSB_DEDICATED1                 0x7D
132 #define VUSB_DEDICATED2                 0x7E
133 #define VUSB1V5_DEV_GRP                 0x71
134 #define VUSB1V5_TYPE                    0x72
135 #define VUSB1V5_REMAP                   0x73
136 #define VUSB1V8_DEV_GRP                 0x74
137 #define VUSB1V8_TYPE                    0x75
138 #define VUSB1V8_REMAP                   0x76
139 #define VUSB3V1_DEV_GRP                 0x77
140 #define VUSB3V1_TYPE                    0x78
141 #define VUSB3V1_REMAP                   0x79
142 
143 /* In module TWL4030_MODULE_INTBR */
144 #define PMBR1                           0x0D
145 #define GPIO_USB_4PIN_ULPI_2430C        (3 << 0)
146 
147 /*
148  * If VBUS is valid or ID is ground, then we know a
149  * cable is present and we need to be runtime-enabled
150  */
151 static inline bool cable_present(enum omap_musb_vbus_id_status stat)
152 {
153         return stat == OMAP_MUSB_VBUS_VALID ||
154                 stat == OMAP_MUSB_ID_GROUND;
155 }
156 
157 struct twl4030_usb {
158         struct usb_phy          phy;
159         struct device           *dev;
160 
161         /* TWL4030 internal USB regulator supplies */
162         struct regulator        *usb1v5;
163         struct regulator        *usb1v8;
164         struct regulator        *usb3v1;
165 
166         /* for vbus reporting with irqs disabled */
167         struct mutex            lock;
168 
169         /* pin configuration */
170         enum twl4030_usb_mode   usb_mode;
171 
172         int                     irq;
173         enum omap_musb_vbus_id_status linkstat;
174         bool                    vbus_supplied;
175 
176         struct delayed_work     id_workaround_work;
177 };
178 
179 /* internal define on top of container_of */
180 #define phy_to_twl(x)           container_of((x), struct twl4030_usb, phy)
181 
182 /*-------------------------------------------------------------------------*/
183 
184 static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl,
185                 u8 module, u8 data, u8 address)
186 {
187         u8 check;
188 
189         if ((twl_i2c_write_u8(module, data, address) >= 0) &&
190             (twl_i2c_read_u8(module, &check, address) >= 0) &&
191                                                 (check == data))
192                 return 0;
193         dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
194                         1, module, address, check, data);
195 
196         /* Failed once: Try again */
197         if ((twl_i2c_write_u8(module, data, address) >= 0) &&
198             (twl_i2c_read_u8(module, &check, address) >= 0) &&
199                                                 (check == data))
200                 return 0;
201         dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
202                         2, module, address, check, data);
203 
204         /* Failed again: Return error */
205         return -EBUSY;
206 }
207 
208 #define twl4030_usb_write_verify(twl, address, data)    \
209         twl4030_i2c_write_u8_verify(twl, TWL_MODULE_USB, (data), (address))
210 
211 static inline int twl4030_usb_write(struct twl4030_usb *twl,
212                 u8 address, u8 data)
213 {
214         int ret = 0;
215 
216         ret = twl_i2c_write_u8(TWL_MODULE_USB, data, address);
217         if (ret < 0)
218                 dev_dbg(twl->dev,
219                         "TWL4030:USB:Write[0x%x] Error %d\n", address, ret);
220         return ret;
221 }
222 
223 static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address)
224 {
225         u8 data;
226         int ret = 0;
227 
228         ret = twl_i2c_read_u8(module, &data, address);
229         if (ret >= 0)
230                 ret = data;
231         else
232                 dev_dbg(twl->dev,
233                         "TWL4030:readb[0x%x,0x%x] Error %d\n",
234                                         module, address, ret);
235 
236         return ret;
237 }
238 
239 static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address)
240 {
241         return twl4030_readb(twl, TWL_MODULE_USB, address);
242 }
243 
244 /*-------------------------------------------------------------------------*/
245 
246 static inline int
247 twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
248 {
249         return twl4030_usb_write(twl, ULPI_SET(reg), bits);
250 }
251 
252 static inline int
253 twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
254 {
255         return twl4030_usb_write(twl, ULPI_CLR(reg), bits);
256 }
257 
258 /*-------------------------------------------------------------------------*/
259 
260 static bool twl4030_is_driving_vbus(struct twl4030_usb *twl)
261 {
262         int ret;
263 
264         ret = twl4030_usb_read(twl, PHY_CLK_CTRL_STS);
265         if (ret < 0 || !(ret & PHY_DPLL_CLK))
266                 /*
267                  * if clocks are off, registers are not updated,
268                  * but we can assume we don't drive VBUS in this case
269                  */
270                 return false;
271 
272         ret = twl4030_usb_read(twl, ULPI_OTG_CTRL);
273         if (ret < 0)
274                 return false;
275 
276         return (ret & (ULPI_OTG_DRVVBUS | ULPI_OTG_CHRGVBUS)) ? true : false;
277 }
278 
279 static enum omap_musb_vbus_id_status
280         twl4030_usb_linkstat(struct twl4030_usb *twl)
281 {
282         int     status;
283         enum omap_musb_vbus_id_status linkstat = OMAP_MUSB_UNKNOWN;
284 
285         twl->vbus_supplied = false;
286 
287         /*
288          * For ID/VBUS sensing, see manual section 15.4.8 ...
289          * except when using only battery backup power, two
290          * comparators produce VBUS_PRES and ID_PRES signals,
291          * which don't match docs elsewhere.  But ... BIT(7)
292          * and BIT(2) of STS_HW_CONDITIONS, respectively, do
293          * seem to match up.  If either is true the USB_PRES
294          * signal is active, the OTG module is activated, and
295          * its interrupt may be raised (may wake the system).
296          */
297         status = twl4030_readb(twl, TWL_MODULE_PM_MASTER, STS_HW_CONDITIONS);
298         if (status < 0)
299                 dev_err(twl->dev, "USB link status err %d\n", status);
300         else if (status & (BIT(7) | BIT(2))) {
301                 if (status & BIT(7)) {
302                         if (twl4030_is_driving_vbus(twl))
303                                 status &= ~BIT(7);
304                         else
305                                 twl->vbus_supplied = true;
306                 }
307 
308                 if (status & BIT(2))
309                         linkstat = OMAP_MUSB_ID_GROUND;
310                 else if (status & BIT(7))
311                         linkstat = OMAP_MUSB_VBUS_VALID;
312                 else
313                         linkstat = OMAP_MUSB_VBUS_OFF;
314         } else {
315                 if (twl->linkstat != OMAP_MUSB_UNKNOWN)
316                         linkstat = OMAP_MUSB_VBUS_OFF;
317         }
318 
319         dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n",
320                         status, status, linkstat);
321 
322         /* REVISIT this assumes host and peripheral controllers
323          * are registered, and that both are active...
324          */
325 
326         return linkstat;
327 }
328 
329 static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode)
330 {
331         twl->usb_mode = mode;
332 
333         switch (mode) {
334         case T2_USB_MODE_ULPI:
335                 twl4030_usb_clear_bits(twl, ULPI_IFC_CTRL,
336                                         ULPI_IFC_CTRL_CARKITMODE);
337                 twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
338                 twl4030_usb_clear_bits(twl, ULPI_FUNC_CTRL,
339                                         ULPI_FUNC_CTRL_XCVRSEL_MASK |
340                                         ULPI_FUNC_CTRL_OPMODE_MASK);
341                 break;
342         case -1:
343                 /* FIXME: power on defaults */
344                 break;
345         default:
346                 dev_err(twl->dev, "unsupported T2 transceiver mode %d\n",
347                                 mode);
348                 break;
349         }
350 }
351 
352 static void twl4030_i2c_access(struct twl4030_usb *twl, int on)
353 {
354         unsigned long timeout;
355         int val = twl4030_usb_read(twl, PHY_CLK_CTRL);
356 
357         if (val >= 0) {
358                 if (on) {
359                         /* enable DPLL to access PHY registers over I2C */
360                         val |= REQ_PHY_DPLL_CLK;
361                         WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
362                                                 (u8)val) < 0);
363 
364                         timeout = jiffies + HZ;
365                         while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
366                                                         PHY_DPLL_CLK)
367                                 && time_before(jiffies, timeout))
368                                         udelay(10);
369                         if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
370                                                         PHY_DPLL_CLK))
371                                 dev_err(twl->dev, "Timeout setting T2 HSUSB "
372                                                 "PHY DPLL clock\n");
373                 } else {
374                         /* let ULPI control the DPLL clock */
375                         val &= ~REQ_PHY_DPLL_CLK;
376                         WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
377                                                 (u8)val) < 0);
378                 }
379         }
380 }
381 
382 static void __twl4030_phy_power(struct twl4030_usb *twl, int on)
383 {
384         u8 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL);
385 
386         if (on)
387                 pwr &= ~PHY_PWR_PHYPWD;
388         else
389                 pwr |= PHY_PWR_PHYPWD;
390 
391         WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0);
392 }
393 
394 static int twl4030_usb_runtime_suspend(struct device *dev)
395 {
396         struct twl4030_usb *twl = dev_get_drvdata(dev);
397 
398         dev_dbg(twl->dev, "%s\n", __func__);
399 
400         __twl4030_phy_power(twl, 0);
401         regulator_disable(twl->usb1v5);
402         regulator_disable(twl->usb1v8);
403         regulator_disable(twl->usb3v1);
404 
405         return 0;
406 }
407 
408 static int twl4030_usb_runtime_resume(struct device *dev)
409 {
410         struct twl4030_usb *twl = dev_get_drvdata(dev);
411         int res;
412 
413         dev_dbg(twl->dev, "%s\n", __func__);
414 
415         res = regulator_enable(twl->usb3v1);
416         if (res)
417                 dev_err(twl->dev, "Failed to enable usb3v1\n");
418 
419         res = regulator_enable(twl->usb1v8);
420         if (res)
421                 dev_err(twl->dev, "Failed to enable usb1v8\n");
422 
423         /*
424          * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP
425          * in twl4030) resets the VUSB_DEDICATED2 register. This reset
426          * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to
427          * SLEEP. We work around this by clearing the bit after usv3v1
428          * is re-activated. This ensures that VUSB3V1 is really active.
429          */
430         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);
431 
432         res = regulator_enable(twl->usb1v5);
433         if (res)
434                 dev_err(twl->dev, "Failed to enable usb1v5\n");
435 
436         __twl4030_phy_power(twl, 1);
437         twl4030_usb_write(twl, PHY_CLK_CTRL,
438                           twl4030_usb_read(twl, PHY_CLK_CTRL) |
439                           (PHY_CLK_CTRL_CLOCKGATING_EN |
440                            PHY_CLK_CTRL_CLK32K_EN));
441 
442         return 0;
443 }
444 
445 static int twl4030_phy_power_off(struct phy *phy)
446 {
447         struct twl4030_usb *twl = phy_get_drvdata(phy);
448 
449         dev_dbg(twl->dev, "%s\n", __func__);
450         pm_runtime_mark_last_busy(twl->dev);
451         pm_runtime_put_autosuspend(twl->dev);
452 
453         return 0;
454 }
455 
456 static int twl4030_phy_power_on(struct phy *phy)
457 {
458         struct twl4030_usb *twl = phy_get_drvdata(phy);
459 
460         dev_dbg(twl->dev, "%s\n", __func__);
461         pm_runtime_get_sync(twl->dev);
462         twl4030_i2c_access(twl, 1);
463         twl4030_usb_set_mode(twl, twl->usb_mode);
464         if (twl->usb_mode == T2_USB_MODE_ULPI)
465                 twl4030_i2c_access(twl, 0);
466         schedule_delayed_work(&twl->id_workaround_work, 0);
467 
468         return 0;
469 }
470 
471 static int twl4030_usb_ldo_init(struct twl4030_usb *twl)
472 {
473         /* Enable writing to power configuration registers */
474         twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
475                          TWL4030_PM_MASTER_PROTECT_KEY);
476 
477         twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
478                          TWL4030_PM_MASTER_PROTECT_KEY);
479 
480         /* Keep VUSB3V1 LDO in sleep state until VBUS/ID change detected*/
481         /*twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);*/
482 
483         /* input to VUSB3V1 LDO is from VBAT, not VBUS */
484         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1);
485 
486         /* Initialize 3.1V regulator */
487         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_DEV_GRP);
488 
489         twl->usb3v1 = devm_regulator_get(twl->dev, "usb3v1");
490         if (IS_ERR(twl->usb3v1))
491                 return -ENODEV;
492 
493         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE);
494 
495         /* Initialize 1.5V regulator */
496         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_DEV_GRP);
497 
498         twl->usb1v5 = devm_regulator_get(twl->dev, "usb1v5");
499         if (IS_ERR(twl->usb1v5))
500                 return -ENODEV;
501 
502         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE);
503 
504         /* Initialize 1.8V regulator */
505         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_DEV_GRP);
506 
507         twl->usb1v8 = devm_regulator_get(twl->dev, "usb1v8");
508         if (IS_ERR(twl->usb1v8))
509                 return -ENODEV;
510 
511         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE);
512 
513         /* disable access to power configuration registers */
514         twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
515                          TWL4030_PM_MASTER_PROTECT_KEY);
516 
517         return 0;
518 }
519 
520 static ssize_t twl4030_usb_vbus_show(struct device *dev,
521                 struct device_attribute *attr, char *buf)
522 {
523         struct twl4030_usb *twl = dev_get_drvdata(dev);
524         int ret = -EINVAL;
525 
526         mutex_lock(&twl->lock);
527         ret = sprintf(buf, "%s\n",
528                         twl->vbus_supplied ? "on" : "off");
529         mutex_unlock(&twl->lock);
530 
531         return ret;
532 }
533 static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL);
534 
535 static irqreturn_t twl4030_usb_irq(int irq, void *_twl)
536 {
537         struct twl4030_usb *twl = _twl;
538         enum omap_musb_vbus_id_status status;
539         bool status_changed = false;
540 
541         status = twl4030_usb_linkstat(twl);
542 
543         mutex_lock(&twl->lock);
544         if (status >= 0 && status != twl->linkstat) {
545                 status_changed =
546                         cable_present(twl->linkstat) !=
547                         cable_present(status);
548                 twl->linkstat = status;
549         }
550         mutex_unlock(&twl->lock);
551 
552         if (status_changed) {
553                 /* FIXME add a set_power() method so that B-devices can
554                  * configure the charger appropriately.  It's not always
555                  * correct to consume VBUS power, and how much current to
556                  * consume is a function of the USB configuration chosen
557                  * by the host.
558                  *
559                  * REVISIT usb_gadget_vbus_connect(...) as needed, ditto
560                  * its disconnect() sibling, when changing to/from the
561                  * USB_LINK_VBUS state.  musb_hdrc won't care until it
562                  * starts to handle softconnect right.
563                  */
564                 if (cable_present(status)) {
565                         pm_runtime_get_sync(twl->dev);
566                 } else {
567                         pm_runtime_mark_last_busy(twl->dev);
568                         pm_runtime_put_autosuspend(twl->dev);
569                 }
570                 omap_musb_mailbox(status);
571         }
572 
573         /* don't schedule during sleep - irq works right then */
574         if (status == OMAP_MUSB_ID_GROUND && pm_runtime_active(twl->dev)) {
575                 cancel_delayed_work(&twl->id_workaround_work);
576                 schedule_delayed_work(&twl->id_workaround_work, HZ);
577         }
578 
579         if (irq)
580                 sysfs_notify(&twl->dev->kobj, NULL, "vbus");
581 
582         return IRQ_HANDLED;
583 }
584 
585 static void twl4030_id_workaround_work(struct work_struct *work)
586 {
587         struct twl4030_usb *twl = container_of(work, struct twl4030_usb,
588                 id_workaround_work.work);
589 
590         twl4030_usb_irq(0, twl);
591 }
592 
593 static int twl4030_phy_init(struct phy *phy)
594 {
595         struct twl4030_usb *twl = phy_get_drvdata(phy);
596 
597         pm_runtime_get_sync(twl->dev);
598         schedule_delayed_work(&twl->id_workaround_work, 0);
599         pm_runtime_mark_last_busy(twl->dev);
600         pm_runtime_put_autosuspend(twl->dev);
601 
602         return 0;
603 }
604 
605 static int twl4030_set_peripheral(struct usb_otg *otg,
606                                         struct usb_gadget *gadget)
607 {
608         if (!otg)
609                 return -ENODEV;
610 
611         otg->gadget = gadget;
612         if (!gadget)
613                 otg->state = OTG_STATE_UNDEFINED;
614 
615         return 0;
616 }
617 
618 static int twl4030_set_host(struct usb_otg *otg, struct usb_bus *host)
619 {
620         if (!otg)
621                 return -ENODEV;
622 
623         otg->host = host;
624         if (!host)
625                 otg->state = OTG_STATE_UNDEFINED;
626 
627         return 0;
628 }
629 
630 static const struct phy_ops ops = {
631         .init           = twl4030_phy_init,
632         .power_on       = twl4030_phy_power_on,
633         .power_off      = twl4030_phy_power_off,
634         .owner          = THIS_MODULE,
635 };
636 
637 static const struct dev_pm_ops twl4030_usb_pm_ops = {
638         SET_RUNTIME_PM_OPS(twl4030_usb_runtime_suspend,
639                            twl4030_usb_runtime_resume, NULL)
640 };
641 
642 static int twl4030_usb_probe(struct platform_device *pdev)
643 {
644         struct twl4030_usb_data *pdata = dev_get_platdata(&pdev->dev);
645         struct twl4030_usb      *twl;
646         struct phy              *phy;
647         int                     status, err;
648         struct usb_otg          *otg;
649         struct device_node      *np = pdev->dev.of_node;
650         struct phy_provider     *phy_provider;
651 
652         twl = devm_kzalloc(&pdev->dev, sizeof(*twl), GFP_KERNEL);
653         if (!twl)
654                 return -ENOMEM;
655 
656         if (np)
657                 of_property_read_u32(np, "usb_mode",
658                                 (enum twl4030_usb_mode *)&twl->usb_mode);
659         else if (pdata) {
660                 twl->usb_mode = pdata->usb_mode;
661         } else {
662                 dev_err(&pdev->dev, "twl4030 initialized without pdata\n");
663                 return -EINVAL;
664         }
665 
666         otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL);
667         if (!otg)
668                 return -ENOMEM;
669 
670         twl->dev                = &pdev->dev;
671         twl->irq                = platform_get_irq(pdev, 0);
672         twl->vbus_supplied      = false;
673         twl->linkstat           = OMAP_MUSB_UNKNOWN;
674 
675         twl->phy.dev            = twl->dev;
676         twl->phy.label          = "twl4030";
677         twl->phy.otg            = otg;
678         twl->phy.type           = USB_PHY_TYPE_USB2;
679 
680         otg->usb_phy            = &twl->phy;
681         otg->set_host           = twl4030_set_host;
682         otg->set_peripheral     = twl4030_set_peripheral;
683 
684         phy = devm_phy_create(twl->dev, NULL, &ops);
685         if (IS_ERR(phy)) {
686                 dev_dbg(&pdev->dev, "Failed to create PHY\n");
687                 return PTR_ERR(phy);
688         }
689 
690         phy_set_drvdata(phy, twl);
691 
692         phy_provider = devm_of_phy_provider_register(twl->dev,
693                 of_phy_simple_xlate);
694         if (IS_ERR(phy_provider))
695                 return PTR_ERR(phy_provider);
696 
697         /* init mutex for workqueue */
698         mutex_init(&twl->lock);
699 
700         INIT_DELAYED_WORK(&twl->id_workaround_work, twl4030_id_workaround_work);
701 
702         err = twl4030_usb_ldo_init(twl);
703         if (err) {
704                 dev_err(&pdev->dev, "ldo init failed\n");
705                 return err;
706         }
707         usb_add_phy_dev(&twl->phy);
708 
709         platform_set_drvdata(pdev, twl);
710         if (device_create_file(&pdev->dev, &dev_attr_vbus))
711                 dev_warn(&pdev->dev, "could not create sysfs file\n");
712 
713         ATOMIC_INIT_NOTIFIER_HEAD(&twl->phy.notifier);
714 
715         pm_runtime_use_autosuspend(&pdev->dev);
716         pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
717         pm_runtime_enable(&pdev->dev);
718 
719         /* Our job is to use irqs and status from the power module
720          * to keep the transceiver disabled when nothing's connected.
721          *
722          * FIXME we actually shouldn't start enabling it until the
723          * USB controller drivers have said they're ready, by calling
724          * set_host() and/or set_peripheral() ... OTG_capable boards
725          * need both handles, otherwise just one suffices.
726          */
727         status = devm_request_threaded_irq(twl->dev, twl->irq, NULL,
728                         twl4030_usb_irq, IRQF_TRIGGER_FALLING |
729                         IRQF_TRIGGER_RISING | IRQF_ONESHOT, "twl4030_usb", twl);
730         if (status < 0) {
731                 dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n",
732                         twl->irq, status);
733                 return status;
734         }
735 
736         if (pdata)
737                 err = phy_create_lookup(phy, "usb", "musb-hdrc.0");
738         if (err)
739                 return err;
740 
741         pm_runtime_mark_last_busy(&pdev->dev);
742         pm_runtime_put_autosuspend(twl->dev);
743 
744         dev_info(&pdev->dev, "Initialized TWL4030 USB module\n");
745         return 0;
746 }
747 
748 static int twl4030_usb_remove(struct platform_device *pdev)
749 {
750         struct twl4030_usb *twl = platform_get_drvdata(pdev);
751         int val;
752 
753         pm_runtime_get_sync(twl->dev);
754         cancel_delayed_work(&twl->id_workaround_work);
755         device_remove_file(twl->dev, &dev_attr_vbus);
756 
757         /* set transceiver mode to power on defaults */
758         twl4030_usb_set_mode(twl, -1);
759 
760         /* autogate 60MHz ULPI clock,
761          * clear dpll clock request for i2c access,
762          * disable 32KHz
763          */
764         val = twl4030_usb_read(twl, PHY_CLK_CTRL);
765         if (val >= 0) {
766                 val |= PHY_CLK_CTRL_CLOCKGATING_EN;
767                 val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK);
768                 twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val);
769         }
770 
771         /* disable complete OTG block */
772         twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
773 
774         if (cable_present(twl->linkstat))
775                 pm_runtime_put_noidle(twl->dev);
776         pm_runtime_mark_last_busy(twl->dev);
777         pm_runtime_put(twl->dev);
778 
779         return 0;
780 }
781 
782 #ifdef CONFIG_OF
783 static const struct of_device_id twl4030_usb_id_table[] = {
784         { .compatible = "ti,twl4030-usb" },
785         {}
786 };
787 MODULE_DEVICE_TABLE(of, twl4030_usb_id_table);
788 #endif
789 
790 static struct platform_driver twl4030_usb_driver = {
791         .probe          = twl4030_usb_probe,
792         .remove         = twl4030_usb_remove,
793         .driver         = {
794                 .name   = "twl4030_usb",
795                 .pm     = &twl4030_usb_pm_ops,
796                 .of_match_table = of_match_ptr(twl4030_usb_id_table),
797         },
798 };
799 
800 static int __init twl4030_usb_init(void)
801 {
802         return platform_driver_register(&twl4030_usb_driver);
803 }
804 subsys_initcall(twl4030_usb_init);
805 
806 static void __exit twl4030_usb_exit(void)
807 {
808         platform_driver_unregister(&twl4030_usb_driver);
809 }
810 module_exit(twl4030_usb_exit);
811 
812 MODULE_ALIAS("platform:twl4030_usb");
813 MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation");
814 MODULE_DESCRIPTION("TWL4030 USB transceiver driver");
815 MODULE_LICENSE("GPL");
816 

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