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Linux/drivers/parisc/eisa.c

  1 /*
  2  * eisa.c - provide support for EISA adapters in PA-RISC machines
  3  *
  4  * This program is free software; you can redistribute it and/or
  5  * modify it under the terms of the GNU General Public License
  6  * as published by the Free Software Foundation; either version
  7  * 2 of the License, or (at your option) any later version.
  8  *
  9  * Copyright (c) 2001 Matthew Wilcox for Hewlett Packard
 10  * Copyright (c) 2001 Daniel Engstrom <5116@telia.com>
 11  *
 12  * There are two distinct EISA adapters.  Mongoose is found in machines
 13  * before the 712; then the Wax ASIC is used.  To complicate matters, the
 14  * Wax ASIC also includes a PS/2 and RS-232 controller, but those are
 15  * dealt with elsewhere; this file is concerned only with the EISA portions
 16  * of Wax.
 17  * 
 18  * 
 19  * HINT:
 20  * -----
 21  * To allow an ISA card to work properly in the EISA slot you need to
 22  * set an edge trigger level. This may be done on the palo command line 
 23  * by adding the kernel parameter "eisa_irq_edge=n,n2,[...]]", with 
 24  * n and n2 as the irq levels you want to use.
 25  * 
 26  * Example: "eisa_irq_edge=10,11" allows ISA cards to operate at 
 27  * irq levels 10 and 11.
 28  */
 29 
 30 #include <linux/init.h>
 31 #include <linux/ioport.h>
 32 #include <linux/interrupt.h>
 33 #include <linux/kernel.h>
 34 #include <linux/module.h>
 35 #include <linux/pci.h>
 36 #include <linux/spinlock.h>
 37 #include <linux/eisa.h>
 38 
 39 #include <asm/byteorder.h>
 40 #include <asm/io.h>
 41 #include <asm/hardware.h>
 42 #include <asm/processor.h>
 43 #include <asm/parisc-device.h>
 44 #include <asm/delay.h>
 45 #include <asm/eisa_bus.h>
 46 #include <asm/eisa_eeprom.h>
 47 
 48 #if 0
 49 #define EISA_DBG(msg, arg... ) printk(KERN_DEBUG "eisa: " msg , ## arg )
 50 #else
 51 #define EISA_DBG(msg, arg... )  
 52 #endif
 53 
 54 #define SNAKES_EEPROM_BASE_ADDR 0xF0810400
 55 #define MIRAGE_EEPROM_BASE_ADDR 0xF00C0400
 56 
 57 static DEFINE_SPINLOCK(eisa_irq_lock);
 58 
 59 void __iomem *eisa_eeprom_addr __read_mostly;
 60 
 61 /* We can only have one EISA adapter in the system because neither
 62  * implementation can be flexed.
 63  */
 64 static struct eisa_ba {
 65         struct pci_hba_data     hba;
 66         unsigned long eeprom_addr;
 67         struct eisa_root_device root;
 68 } eisa_dev;
 69 
 70 /* Port ops */
 71 
 72 static inline unsigned long eisa_permute(unsigned short port)
 73 {
 74         if (port & 0x300) {
 75                 return 0xfc000000 | ((port & 0xfc00) >> 6)
 76                         | ((port & 0x3f8) << 9) | (port & 7);
 77         } else {
 78                 return 0xfc000000 | port;
 79         }
 80 }
 81 
 82 unsigned char eisa_in8(unsigned short port)
 83 {
 84         if (EISA_bus)
 85                 return gsc_readb(eisa_permute(port));
 86         return 0xff;
 87 }
 88 
 89 unsigned short eisa_in16(unsigned short port)
 90 {
 91         if (EISA_bus)
 92                 return le16_to_cpu(gsc_readw(eisa_permute(port)));
 93         return 0xffff;
 94 }
 95 
 96 unsigned int eisa_in32(unsigned short port)
 97 {
 98         if (EISA_bus)
 99                 return le32_to_cpu(gsc_readl(eisa_permute(port)));
100         return 0xffffffff;
101 }
102 
103 void eisa_out8(unsigned char data, unsigned short port)
104 {
105         if (EISA_bus)
106                 gsc_writeb(data, eisa_permute(port));
107 }
108 
109 void eisa_out16(unsigned short data, unsigned short port)
110 {
111         if (EISA_bus)   
112                 gsc_writew(cpu_to_le16(data), eisa_permute(port));
113 }
114 
115 void eisa_out32(unsigned int data, unsigned short port)
116 {
117         if (EISA_bus)
118                 gsc_writel(cpu_to_le32(data), eisa_permute(port));
119 }
120 
121 #ifndef CONFIG_PCI
122 /* We call these directly without PCI.  See asm/io.h. */
123 EXPORT_SYMBOL(eisa_in8);
124 EXPORT_SYMBOL(eisa_in16);
125 EXPORT_SYMBOL(eisa_in32);
126 EXPORT_SYMBOL(eisa_out8);
127 EXPORT_SYMBOL(eisa_out16);
128 EXPORT_SYMBOL(eisa_out32);
129 #endif
130 
131 /* Interrupt handling */
132 
133 /* cached interrupt mask registers */
134 static int master_mask;
135 static int slave_mask;
136 
137 /* the trig level can be set with the
138  * eisa_irq_edge=n,n,n commandline parameter 
139  * We should really read this from the EEPROM 
140  * in the furure. 
141  */
142 /* irq 13,8,2,1,0 must be edge */
143 static unsigned int eisa_irq_level __read_mostly; /* default to edge triggered */
144 
145 
146 /* called by free irq */
147 static void eisa_mask_irq(struct irq_data *d)
148 {
149         unsigned int irq = d->irq;
150         unsigned long flags;
151 
152         EISA_DBG("disable irq %d\n", irq);
153         /* just mask for now */
154         spin_lock_irqsave(&eisa_irq_lock, flags);
155         if (irq & 8) {
156                 slave_mask |= (1 << (irq&7));
157                 eisa_out8(slave_mask, 0xa1);
158         } else {
159                 master_mask |= (1 << (irq&7));
160                 eisa_out8(master_mask, 0x21);
161         }
162         spin_unlock_irqrestore(&eisa_irq_lock, flags);
163         EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
164         EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
165 }
166 
167 /* called by request irq */
168 static void eisa_unmask_irq(struct irq_data *d)
169 {
170         unsigned int irq = d->irq;
171         unsigned long flags;
172         EISA_DBG("enable irq %d\n", irq);
173                 
174         spin_lock_irqsave(&eisa_irq_lock, flags);
175         if (irq & 8) {
176                 slave_mask &= ~(1 << (irq&7));
177                 eisa_out8(slave_mask, 0xa1);
178         } else {
179                 master_mask &= ~(1 << (irq&7));
180                 eisa_out8(master_mask, 0x21);
181         }
182         spin_unlock_irqrestore(&eisa_irq_lock, flags);
183         EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
184         EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
185 }
186 
187 static struct irq_chip eisa_interrupt_type = {
188         .name           =       "EISA",
189         .irq_unmask     =       eisa_unmask_irq,
190         .irq_mask       =       eisa_mask_irq,
191 };
192 
193 static irqreturn_t eisa_irq(int wax_irq, void *intr_dev)
194 {
195         int irq = gsc_readb(0xfc01f000); /* EISA supports 16 irqs */
196         unsigned long flags;
197         
198         spin_lock_irqsave(&eisa_irq_lock, flags);
199         /* read IRR command */
200         eisa_out8(0x0a, 0x20);
201         eisa_out8(0x0a, 0xa0);
202 
203         EISA_DBG("irq IAR %02x 8259-1 irr %02x 8259-2 irr %02x\n",
204                    irq, eisa_in8(0x20), eisa_in8(0xa0));
205    
206         /* read ISR command */
207         eisa_out8(0x0a, 0x20);
208         eisa_out8(0x0a, 0xa0);
209         EISA_DBG("irq 8259-1 isr %02x imr %02x 8259-2 isr %02x imr %02x\n",
210                  eisa_in8(0x20), eisa_in8(0x21), eisa_in8(0xa0), eisa_in8(0xa1));
211         
212         irq &= 0xf;
213         
214         /* mask irq and write eoi */
215         if (irq & 8) {
216                 slave_mask |= (1 << (irq&7));
217                 eisa_out8(slave_mask, 0xa1);
218                 eisa_out8(0x60 | (irq&7),0xa0);/* 'Specific EOI' to slave */
219                 eisa_out8(0x62,0x20);   /* 'Specific EOI' to master-IRQ2 */
220                 
221         } else {
222                 master_mask |= (1 << (irq&7));
223                 eisa_out8(master_mask, 0x21);
224                 eisa_out8(0x60|irq,0x20);       /* 'Specific EOI' to master */
225         }
226         spin_unlock_irqrestore(&eisa_irq_lock, flags);
227 
228         generic_handle_irq(irq);
229    
230         spin_lock_irqsave(&eisa_irq_lock, flags);
231         /* unmask */
232         if (irq & 8) {
233                 slave_mask &= ~(1 << (irq&7));
234                 eisa_out8(slave_mask, 0xa1);
235         } else {
236                 master_mask &= ~(1 << (irq&7));
237                 eisa_out8(master_mask, 0x21);
238         }
239         spin_unlock_irqrestore(&eisa_irq_lock, flags);
240         return IRQ_HANDLED;
241 }
242 
243 static irqreturn_t dummy_irq2_handler(int _, void *dev)
244 {
245         printk(KERN_ALERT "eisa: uhh, irq2?\n");
246         return IRQ_HANDLED;
247 }
248 
249 static struct irqaction irq2_action = {
250         .handler = dummy_irq2_handler,
251         .name = "cascade",
252 };
253 
254 static void init_eisa_pic(void)
255 {
256         unsigned long flags;
257         
258         spin_lock_irqsave(&eisa_irq_lock, flags);
259 
260         eisa_out8(0xff, 0x21); /* mask during init */
261         eisa_out8(0xff, 0xa1); /* mask during init */
262         
263         /* master pic */
264         eisa_out8(0x11,0x20); /* ICW1 */   
265         eisa_out8(0x00,0x21); /* ICW2 */   
266         eisa_out8(0x04,0x21); /* ICW3 */   
267         eisa_out8(0x01,0x21); /* ICW4 */   
268         eisa_out8(0x40,0x20); /* OCW2 */   
269         
270         /* slave pic */
271         eisa_out8(0x11,0xa0); /* ICW1 */   
272         eisa_out8(0x08,0xa1); /* ICW2 */   
273         eisa_out8(0x02,0xa1); /* ICW3 */   
274         eisa_out8(0x01,0xa1); /* ICW4 */   
275         eisa_out8(0x40,0xa0); /* OCW2 */   
276         
277         udelay(100);
278         
279         slave_mask = 0xff; 
280         master_mask = 0xfb; 
281         eisa_out8(slave_mask, 0xa1); /* OCW1 */
282         eisa_out8(master_mask, 0x21); /* OCW1 */
283         
284         /* setup trig level */
285         EISA_DBG("EISA edge/level %04x\n", eisa_irq_level);
286         
287         eisa_out8(eisa_irq_level&0xff, 0x4d0); /* Set all irq's to edge  */
288         eisa_out8((eisa_irq_level >> 8) & 0xff, 0x4d1); 
289         
290         EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
291         EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
292         EISA_DBG("pic0 edge/level %02x\n", eisa_in8(0x4d0));
293         EISA_DBG("pic1 edge/level %02x\n", eisa_in8(0x4d1));
294         
295         spin_unlock_irqrestore(&eisa_irq_lock, flags);
296 }
297 
298 /* Device initialisation */
299 
300 #define is_mongoose(dev) (dev->id.sversion == 0x00076)
301 
302 static int __init eisa_probe(struct parisc_device *dev)
303 {
304         int i, result;
305 
306         char *name = is_mongoose(dev) ? "Mongoose" : "Wax";
307 
308         printk(KERN_INFO "%s EISA Adapter found at 0x%08lx\n", 
309                 name, (unsigned long)dev->hpa.start);
310 
311         eisa_dev.hba.dev = dev;
312         eisa_dev.hba.iommu = ccio_get_iommu(dev);
313 
314         eisa_dev.hba.lmmio_space.name = "EISA";
315         eisa_dev.hba.lmmio_space.start = F_EXTEND(0xfc000000);
316         eisa_dev.hba.lmmio_space.end = F_EXTEND(0xffbfffff);
317         eisa_dev.hba.lmmio_space.flags = IORESOURCE_MEM;
318         result = ccio_request_resource(dev, &eisa_dev.hba.lmmio_space);
319         if (result < 0) {
320                 printk(KERN_ERR "EISA: failed to claim EISA Bus address space!\n");
321                 return result;
322         }
323         eisa_dev.hba.io_space.name = "EISA";
324         eisa_dev.hba.io_space.start = 0;
325         eisa_dev.hba.io_space.end = 0xffff;
326         eisa_dev.hba.lmmio_space.flags = IORESOURCE_IO;
327         result = request_resource(&ioport_resource, &eisa_dev.hba.io_space);
328         if (result < 0) {
329                 printk(KERN_ERR "EISA: failed to claim EISA Bus port space!\n");
330                 return result;
331         }
332         pcibios_register_hba(&eisa_dev.hba);
333 
334         result = request_irq(dev->irq, eisa_irq, IRQF_SHARED, "EISA", &eisa_dev);
335         if (result) {
336                 printk(KERN_ERR "EISA: request_irq failed!\n");
337                 return result;
338         }
339         
340         /* Reserve IRQ2 */
341         setup_irq(2, &irq2_action);
342         for (i = 0; i < 16; i++) {
343                 irq_set_chip_and_handler(i, &eisa_interrupt_type,
344                                          handle_simple_irq);
345         }
346         
347         EISA_bus = 1;
348 
349         if (dev->num_addrs) {
350                 /* newer firmware hand out the eeprom address */
351                 eisa_dev.eeprom_addr = dev->addr[0];
352         } else {
353                 /* old firmware, need to figure out the box */
354                 if (is_mongoose(dev)) {
355                         eisa_dev.eeprom_addr = SNAKES_EEPROM_BASE_ADDR;
356                 } else {
357                         eisa_dev.eeprom_addr = MIRAGE_EEPROM_BASE_ADDR;
358                 }
359         }
360         eisa_eeprom_addr = ioremap_nocache(eisa_dev.eeprom_addr, HPEE_MAX_LENGTH);
361         result = eisa_enumerator(eisa_dev.eeprom_addr, &eisa_dev.hba.io_space,
362                         &eisa_dev.hba.lmmio_space);
363         init_eisa_pic();
364 
365         if (result >= 0) {
366                 /* FIXME : Don't enumerate the bus twice. */
367                 eisa_dev.root.dev = &dev->dev;
368                 dev_set_drvdata(&dev->dev, &eisa_dev.root);
369                 eisa_dev.root.bus_base_addr = 0;
370                 eisa_dev.root.res = &eisa_dev.hba.io_space;
371                 eisa_dev.root.slots = result;
372                 eisa_dev.root.dma_mask = 0xffffffff; /* wild guess */
373                 if (eisa_root_register (&eisa_dev.root)) {
374                         printk(KERN_ERR "EISA: Failed to register EISA root\n");
375                         return -1;
376                 }
377         }
378         
379         return 0;
380 }
381 
382 static const struct parisc_device_id eisa_tbl[] = {
383         { HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00076 }, /* Mongoose */
384         { HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00090 }, /* Wax EISA */
385         { 0, }
386 };
387 
388 MODULE_DEVICE_TABLE(parisc, eisa_tbl);
389 
390 static struct parisc_driver eisa_driver = {
391         .name =         "eisa_ba",
392         .id_table =     eisa_tbl,
393         .probe =        eisa_probe,
394 };
395 
396 void __init eisa_init(void)
397 {
398         register_parisc_driver(&eisa_driver);
399 }
400 
401 
402 static unsigned int eisa_irq_configured;
403 void eisa_make_irq_level(int num)
404 {
405         if (eisa_irq_configured& (1<<num)) {
406                 printk(KERN_WARNING
407                        "IRQ %d polarity configured twice (last to level)\n", 
408                        num);
409         }
410         eisa_irq_level |= (1<<num); /* set the corresponding bit */
411         eisa_irq_configured |= (1<<num); /* set the corresponding bit */
412 }
413 
414 void eisa_make_irq_edge(int num)
415 {
416         if (eisa_irq_configured& (1<<num)) {
417                 printk(KERN_WARNING 
418                        "IRQ %d polarity configured twice (last to edge)\n",
419                        num);
420         }
421         eisa_irq_level &= ~(1<<num); /* clear the corresponding bit */
422         eisa_irq_configured |= (1<<num); /* set the corresponding bit */
423 }
424 
425 static int __init eisa_irq_setup(char *str)
426 {
427         char *cur = str;
428         int val;
429 
430         EISA_DBG("IRQ setup\n");
431         while (cur != NULL) {
432                 char *pe;
433                 
434                 val = (int) simple_strtoul(cur, &pe, 0);
435                 if (val > 15 || val < 0) {
436                         printk(KERN_ERR "eisa: EISA irq value are 0-15\n");
437                         continue;
438                 }
439                 if (val == 2) { 
440                         val = 9;
441                 }
442                 eisa_make_irq_edge(val); /* clear the corresponding bit */
443                 EISA_DBG("setting IRQ %d to edge-triggered mode\n", val);
444                 
445                 if ((cur = strchr(cur, ','))) {
446                         cur++;
447                 } else {
448                         break;
449                 }
450         }
451         return 1;
452 }
453 
454 __setup("eisa_irq_edge=", eisa_irq_setup);
455 
456 

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