Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/net/wireless/rtlwifi/rtl8192ce/sw.c

  1 /******************************************************************************
  2  *
  3  * Copyright(c) 2009-2012  Realtek Corporation.
  4  *
  5  * This program is free software; you can redistribute it and/or modify it
  6  * under the terms of version 2 of the GNU General Public License as
  7  * published by the Free Software Foundation.
  8  *
  9  * This program is distributed in the hope that it will be useful, but WITHOUT
 10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 12  * more details.
 13  *
 14  * You should have received a copy of the GNU General Public License along with
 15  * this program; if not, write to the Free Software Foundation, Inc.,
 16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 17  *
 18  * The full GNU General Public License is included in this distribution in the
 19  * file called LICENSE.
 20  *
 21  * Contact Information:
 22  * wlanfae <wlanfae@realtek.com>
 23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
 24  * Hsinchu 300, Taiwan.
 25  *
 26  * Larry Finger <Larry.Finger@lwfinger.net>
 27  *
 28  *****************************************************************************/
 29 
 30 #include "../wifi.h"
 31 #include "../core.h"
 32 #include "../pci.h"
 33 #include "../base.h"
 34 #include "reg.h"
 35 #include "def.h"
 36 #include "phy.h"
 37 #include "dm.h"
 38 #include "hw.h"
 39 #include "rf.h"
 40 #include "sw.h"
 41 #include "trx.h"
 42 #include "led.h"
 43 
 44 #include <linux/module.h>
 45 
 46 static void rtl92c_init_aspm_vars(struct ieee80211_hw *hw)
 47 {
 48         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 49 
 50         /*close ASPM for AMD defaultly */
 51         rtlpci->const_amdpci_aspm = 0;
 52 
 53         /*
 54          * ASPM PS mode.
 55          * 0 - Disable ASPM,
 56          * 1 - Enable ASPM without Clock Req,
 57          * 2 - Enable ASPM with Clock Req,
 58          * 3 - Alwyas Enable ASPM with Clock Req,
 59          * 4 - Always Enable ASPM without Clock Req.
 60          * set defult to RTL8192CE:3 RTL8192E:2
 61          * */
 62         rtlpci->const_pci_aspm = 3;
 63 
 64         /*Setting for PCI-E device */
 65         rtlpci->const_devicepci_aspm_setting = 0x03;
 66 
 67         /*Setting for PCI-E bridge */
 68         rtlpci->const_hostpci_aspm_setting = 0x02;
 69 
 70         /*
 71          * In Hw/Sw Radio Off situation.
 72          * 0 - Default,
 73          * 1 - From ASPM setting without low Mac Pwr,
 74          * 2 - From ASPM setting with low Mac Pwr,
 75          * 3 - Bus D3
 76          * set default to RTL8192CE:0 RTL8192SE:2
 77          */
 78         rtlpci->const_hwsw_rfoff_d3 = 0;
 79 
 80         /*
 81          * This setting works for those device with
 82          * backdoor ASPM setting such as EPHY setting.
 83          * 0 - Not support ASPM,
 84          * 1 - Support ASPM,
 85          * 2 - According to chipset.
 86          */
 87         rtlpci->const_support_pciaspm = 1;
 88 }
 89 
 90 int rtl92c_init_sw_vars(struct ieee80211_hw *hw)
 91 {
 92         int err;
 93         struct rtl_priv *rtlpriv = rtl_priv(hw);
 94         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 95         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 96 
 97         rtl8192ce_bt_reg_init(hw);
 98 
 99         rtlpriv->dm.dm_initialgain_enable = true;
100         rtlpriv->dm.dm_flag = 0;
101         rtlpriv->dm.disable_framebursting = false;
102         rtlpriv->dm.thermalvalue = 0;
103         rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
104 
105         /* compatible 5G band 88ce just 2.4G band & smsp */
106         rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
107         rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
108         rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
109 
110         rtlpci->receive_config = (RCR_APPFCS |
111                                   RCR_AMF |
112                                   RCR_ADF |
113                                   RCR_APP_MIC |
114                                   RCR_APP_ICV |
115                                   RCR_AICV |
116                                   RCR_ACRC32 |
117                                   RCR_AB |
118                                   RCR_AM |
119                                   RCR_APM |
120                                   RCR_APP_PHYST_RXFF | RCR_HTC_LOC_CTRL | 0);
121 
122         rtlpci->irq_mask[0] =
123             (u32) (IMR_ROK |
124                    IMR_VODOK |
125                    IMR_VIDOK |
126                    IMR_BEDOK |
127                    IMR_BKDOK |
128                    IMR_MGNTDOK |
129                    IMR_HIGHDOK | IMR_BDOK | IMR_RDU | IMR_RXFOVW | 0);
130 
131         rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD | 0);
132 
133         /* for debug level */
134         rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
135         /* for LPS & IPS */
136         rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
137         rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
138         rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
139         if (!rtlpriv->psc.inactiveps)
140                 pr_info("rtl8192ce: Power Save off (module option)\n");
141         if (!rtlpriv->psc.fwctrl_lps)
142                 pr_info("rtl8192ce: FW Power Save off (module option)\n");
143         rtlpriv->psc.reg_fwctrl_lps = 3;
144         rtlpriv->psc.reg_max_lps_awakeintvl = 5;
145         /* for ASPM, you can close aspm through
146          * set const_support_pciaspm = 0 */
147         rtl92c_init_aspm_vars(hw);
148 
149         if (rtlpriv->psc.reg_fwctrl_lps == 1)
150                 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
151         else if (rtlpriv->psc.reg_fwctrl_lps == 2)
152                 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
153         else if (rtlpriv->psc.reg_fwctrl_lps == 3)
154                 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
155 
156         /* for firmware buf */
157         rtlpriv->rtlhal.pfirmware = vzalloc(0x4000);
158         if (!rtlpriv->rtlhal.pfirmware) {
159                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
160                          "Can't alloc buffer for fw\n");
161                 return 1;
162         }
163 
164         /* request fw */
165         if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
166             !IS_92C_SERIAL(rtlhal->version))
167                 rtlpriv->cfg->fw_name = "rtlwifi/rtl8192cfwU.bin";
168         else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version))
169                 rtlpriv->cfg->fw_name = "rtlwifi/rtl8192cfwU_B.bin";
170 
171         rtlpriv->max_fw_size = 0x4000;
172         pr_info("Using firmware %s\n", rtlpriv->cfg->fw_name);
173         err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
174                                       rtlpriv->io.dev, GFP_KERNEL, hw,
175                                       rtl_fw_cb);
176         if (err) {
177                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
178                          "Failed to request firmware!\n");
179                 return 1;
180         }
181 
182         return 0;
183 }
184 
185 void rtl92c_deinit_sw_vars(struct ieee80211_hw *hw)
186 {
187         struct rtl_priv *rtlpriv = rtl_priv(hw);
188 
189         if (rtlpriv->rtlhal.pfirmware) {
190                 vfree(rtlpriv->rtlhal.pfirmware);
191                 rtlpriv->rtlhal.pfirmware = NULL;
192         }
193 }
194 
195 static struct rtl_hal_ops rtl8192ce_hal_ops = {
196         .init_sw_vars = rtl92c_init_sw_vars,
197         .deinit_sw_vars = rtl92c_deinit_sw_vars,
198         .read_eeprom_info = rtl92ce_read_eeprom_info,
199         .interrupt_recognized = rtl92ce_interrupt_recognized,
200         .hw_init = rtl92ce_hw_init,
201         .hw_disable = rtl92ce_card_disable,
202         .hw_suspend = rtl92ce_suspend,
203         .hw_resume = rtl92ce_resume,
204         .enable_interrupt = rtl92ce_enable_interrupt,
205         .disable_interrupt = rtl92ce_disable_interrupt,
206         .set_network_type = rtl92ce_set_network_type,
207         .set_chk_bssid = rtl92ce_set_check_bssid,
208         .set_qos = rtl92ce_set_qos,
209         .set_bcn_reg = rtl92ce_set_beacon_related_registers,
210         .set_bcn_intv = rtl92ce_set_beacon_interval,
211         .update_interrupt_mask = rtl92ce_update_interrupt_mask,
212         .get_hw_reg = rtl92ce_get_hw_reg,
213         .set_hw_reg = rtl92ce_set_hw_reg,
214         .update_rate_tbl = rtl92ce_update_hal_rate_tbl,
215         .fill_tx_desc = rtl92ce_tx_fill_desc,
216         .fill_tx_cmddesc = rtl92ce_tx_fill_cmddesc,
217         .query_rx_desc = rtl92ce_rx_query_desc,
218         .set_channel_access = rtl92ce_update_channel_access_setting,
219         .radio_onoff_checking = rtl92ce_gpio_radio_on_off_checking,
220         .set_bw_mode = rtl92c_phy_set_bw_mode,
221         .switch_channel = rtl92c_phy_sw_chnl,
222         .dm_watchdog = rtl92c_dm_watchdog,
223         .scan_operation_backup = rtl_phy_scan_operation_backup,
224         .set_rf_power_state = rtl92c_phy_set_rf_power_state,
225         .led_control = rtl92ce_led_control,
226         .set_desc = rtl92ce_set_desc,
227         .get_desc = rtl92ce_get_desc,
228         .tx_polling = rtl92ce_tx_polling,
229         .enable_hw_sec = rtl92ce_enable_hw_security_config,
230         .set_key = rtl92ce_set_key,
231         .init_sw_leds = rtl92ce_init_sw_leds,
232         .get_bbreg = rtl92c_phy_query_bb_reg,
233         .set_bbreg = rtl92c_phy_set_bb_reg,
234         .set_rfreg = rtl92ce_phy_set_rf_reg,
235         .get_rfreg = rtl92c_phy_query_rf_reg,
236         .phy_rf6052_config = rtl92ce_phy_rf6052_config,
237         .phy_rf6052_set_cck_txpower = rtl92ce_phy_rf6052_set_cck_txpower,
238         .phy_rf6052_set_ofdm_txpower = rtl92ce_phy_rf6052_set_ofdm_txpower,
239         .config_bb_with_headerfile = _rtl92ce_phy_config_bb_with_headerfile,
240         .config_bb_with_pgheaderfile = _rtl92ce_phy_config_bb_with_pgheaderfile,
241         .phy_lc_calibrate = _rtl92ce_phy_lc_calibrate,
242         .phy_set_bw_mode_callback = rtl92ce_phy_set_bw_mode_callback,
243         .dm_dynamic_txpower = rtl92ce_dm_dynamic_txpower,
244 };
245 
246 static struct rtl_mod_params rtl92ce_mod_params = {
247         .sw_crypto = false,
248         .inactiveps = true,
249         .swctrl_lps = false,
250         .fwctrl_lps = true,
251         .debug = DBG_EMERG,
252 };
253 
254 static struct rtl_hal_cfg rtl92ce_hal_cfg = {
255         .bar_id = 2,
256         .write_readback = true,
257         .name = "rtl92c_pci",
258         .fw_name = "rtlwifi/rtl8192cfw.bin",
259         .ops = &rtl8192ce_hal_ops,
260         .mod_params = &rtl92ce_mod_params,
261 
262         .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
263         .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
264         .maps[SYS_CLK] = REG_SYS_CLKR,
265         .maps[MAC_RCR_AM] = AM,
266         .maps[MAC_RCR_AB] = AB,
267         .maps[MAC_RCR_ACRC32] = ACRC32,
268         .maps[MAC_RCR_ACF] = ACF,
269         .maps[MAC_RCR_AAP] = AAP,
270 
271         .maps[EFUSE_TEST] = REG_EFUSE_TEST,
272         .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
273         .maps[EFUSE_CLK] = 0,
274         .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
275         .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
276         .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
277         .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
278         .maps[EFUSE_ANA8M] = EFUSE_ANA8M,
279         .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
280         .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
281         .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
282         .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
283 
284         .maps[RWCAM] = REG_CAMCMD,
285         .maps[WCAMI] = REG_CAMWRITE,
286         .maps[RCAMO] = REG_CAMREAD,
287         .maps[CAMDBG] = REG_CAMDBG,
288         .maps[SECR] = REG_SECCFG,
289         .maps[SEC_CAM_NONE] = CAM_NONE,
290         .maps[SEC_CAM_WEP40] = CAM_WEP40,
291         .maps[SEC_CAM_TKIP] = CAM_TKIP,
292         .maps[SEC_CAM_AES] = CAM_AES,
293         .maps[SEC_CAM_WEP104] = CAM_WEP104,
294 
295         .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
296         .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
297         .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
298         .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
299         .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
300         .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
301         .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
302         .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
303         .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
304         .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
305         .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
306         .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
307         .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
308         .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
309         .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
310         .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
311 
312         .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
313         .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
314         .maps[RTL_IMR_BCNINT] = IMR_BCNINT,
315         .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
316         .maps[RTL_IMR_RDU] = IMR_RDU,
317         .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
318         .maps[RTL_IMR_BDOK] = IMR_BDOK,
319         .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
320         .maps[RTL_IMR_TBDER] = IMR_TBDER,
321         .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
322         .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
323         .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
324         .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
325         .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
326         .maps[RTL_IMR_VODOK] = IMR_VODOK,
327         .maps[RTL_IMR_ROK] = IMR_ROK,
328         .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
329 
330         .maps[RTL_RC_CCK_RATE1M] = DESC92_RATE1M,
331         .maps[RTL_RC_CCK_RATE2M] = DESC92_RATE2M,
332         .maps[RTL_RC_CCK_RATE5_5M] = DESC92_RATE5_5M,
333         .maps[RTL_RC_CCK_RATE11M] = DESC92_RATE11M,
334         .maps[RTL_RC_OFDM_RATE6M] = DESC92_RATE6M,
335         .maps[RTL_RC_OFDM_RATE9M] = DESC92_RATE9M,
336         .maps[RTL_RC_OFDM_RATE12M] = DESC92_RATE12M,
337         .maps[RTL_RC_OFDM_RATE18M] = DESC92_RATE18M,
338         .maps[RTL_RC_OFDM_RATE24M] = DESC92_RATE24M,
339         .maps[RTL_RC_OFDM_RATE36M] = DESC92_RATE36M,
340         .maps[RTL_RC_OFDM_RATE48M] = DESC92_RATE48M,
341         .maps[RTL_RC_OFDM_RATE54M] = DESC92_RATE54M,
342 
343         .maps[RTL_RC_HT_RATEMCS7] = DESC92_RATEMCS7,
344         .maps[RTL_RC_HT_RATEMCS15] = DESC92_RATEMCS15,
345 };
346 
347 static const struct pci_device_id rtl92ce_pci_ids[] = {
348         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8191, rtl92ce_hal_cfg)},
349         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8178, rtl92ce_hal_cfg)},
350         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8177, rtl92ce_hal_cfg)},
351         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8176, rtl92ce_hal_cfg)},
352         {},
353 };
354 
355 MODULE_DEVICE_TABLE(pci, rtl92ce_pci_ids);
356 
357 MODULE_AUTHOR("lizhaoming       <chaoming_li@realsil.com.cn>");
358 MODULE_AUTHOR("Realtek WlanFAE  <wlanfae@realtek.com>");
359 MODULE_AUTHOR("Larry Finger     <Larry.Finger@lwfinger.net>");
360 MODULE_LICENSE("GPL");
361 MODULE_DESCRIPTION("Realtek 8192C/8188C 802.11n PCI wireless");
362 MODULE_FIRMWARE("rtlwifi/rtl8192cfw.bin");
363 MODULE_FIRMWARE("rtlwifi/rtl8192cfwU.bin");
364 MODULE_FIRMWARE("rtlwifi/rtl8192cfwU_B.bin");
365 
366 module_param_named(swenc, rtl92ce_mod_params.sw_crypto, bool, 0444);
367 module_param_named(debug, rtl92ce_mod_params.debug, int, 0444);
368 module_param_named(ips, rtl92ce_mod_params.inactiveps, bool, 0444);
369 module_param_named(swlps, rtl92ce_mod_params.swctrl_lps, bool, 0444);
370 module_param_named(fwlps, rtl92ce_mod_params.fwctrl_lps, bool, 0444);
371 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
372 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
373 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
374 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
375 MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
376 
377 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
378 
379 static struct pci_driver rtl92ce_driver = {
380         .name = KBUILD_MODNAME,
381         .id_table = rtl92ce_pci_ids,
382         .probe = rtl_pci_probe,
383         .remove = rtl_pci_disconnect,
384         .driver.pm = &rtlwifi_pm_ops,
385 };
386 
387 module_pci_driver(rtl92ce_driver);
388 

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