Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/net/wireless/rt2x00/rt2400pci.c

  1 /*
  2         Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
  3         <http://rt2x00.serialmonkey.com>
  4 
  5         This program is free software; you can redistribute it and/or modify
  6         it under the terms of the GNU General Public License as published by
  7         the Free Software Foundation; either version 2 of the License, or
  8         (at your option) any later version.
  9 
 10         This program is distributed in the hope that it will be useful,
 11         but WITHOUT ANY WARRANTY; without even the implied warranty of
 12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 13         GNU General Public License for more details.
 14 
 15         You should have received a copy of the GNU General Public License
 16         along with this program; if not, see <http://www.gnu.org/licenses/>.
 17  */
 18 
 19 /*
 20         Module: rt2400pci
 21         Abstract: rt2400pci device specific routines.
 22         Supported chipsets: RT2460.
 23  */
 24 
 25 #include <linux/delay.h>
 26 #include <linux/etherdevice.h>
 27 #include <linux/kernel.h>
 28 #include <linux/module.h>
 29 #include <linux/pci.h>
 30 #include <linux/eeprom_93cx6.h>
 31 #include <linux/slab.h>
 32 
 33 #include "rt2x00.h"
 34 #include "rt2x00mmio.h"
 35 #include "rt2x00pci.h"
 36 #include "rt2400pci.h"
 37 
 38 /*
 39  * Register access.
 40  * All access to the CSR registers will go through the methods
 41  * rt2x00mmio_register_read and rt2x00mmio_register_write.
 42  * BBP and RF register require indirect register access,
 43  * and use the CSR registers BBPCSR and RFCSR to achieve this.
 44  * These indirect registers work with busy bits,
 45  * and we will try maximal REGISTER_BUSY_COUNT times to access
 46  * the register while taking a REGISTER_BUSY_DELAY us delay
 47  * between each attempt. When the busy bit is still set at that time,
 48  * the access attempt is considered to have failed,
 49  * and we will print an error.
 50  */
 51 #define WAIT_FOR_BBP(__dev, __reg) \
 52         rt2x00mmio_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
 53 #define WAIT_FOR_RF(__dev, __reg) \
 54         rt2x00mmio_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
 55 
 56 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
 57                                 const unsigned int word, const u8 value)
 58 {
 59         u32 reg;
 60 
 61         mutex_lock(&rt2x00dev->csr_mutex);
 62 
 63         /*
 64          * Wait until the BBP becomes available, afterwards we
 65          * can safely write the new data into the register.
 66          */
 67         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 68                 reg = 0;
 69                 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
 70                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 71                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 72                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
 73 
 74                 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
 75         }
 76 
 77         mutex_unlock(&rt2x00dev->csr_mutex);
 78 }
 79 
 80 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
 81                                const unsigned int word, u8 *value)
 82 {
 83         u32 reg;
 84 
 85         mutex_lock(&rt2x00dev->csr_mutex);
 86 
 87         /*
 88          * Wait until the BBP becomes available, afterwards we
 89          * can safely write the read request into the register.
 90          * After the data has been written, we wait until hardware
 91          * returns the correct value, if at any time the register
 92          * doesn't become available in time, reg will be 0xffffffff
 93          * which means we return 0xff to the caller.
 94          */
 95         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 96                 reg = 0;
 97                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 98                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 99                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
100 
101                 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
102 
103                 WAIT_FOR_BBP(rt2x00dev, &reg);
104         }
105 
106         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
107 
108         mutex_unlock(&rt2x00dev->csr_mutex);
109 }
110 
111 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
112                                const unsigned int word, const u32 value)
113 {
114         u32 reg;
115 
116         mutex_lock(&rt2x00dev->csr_mutex);
117 
118         /*
119          * Wait until the RF becomes available, afterwards we
120          * can safely write the new data into the register.
121          */
122         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
123                 reg = 0;
124                 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
125                 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
126                 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
127                 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
128 
129                 rt2x00mmio_register_write(rt2x00dev, RFCSR, reg);
130                 rt2x00_rf_write(rt2x00dev, word, value);
131         }
132 
133         mutex_unlock(&rt2x00dev->csr_mutex);
134 }
135 
136 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
137 {
138         struct rt2x00_dev *rt2x00dev = eeprom->data;
139         u32 reg;
140 
141         rt2x00mmio_register_read(rt2x00dev, CSR21, &reg);
142 
143         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
144         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
145         eeprom->reg_data_clock =
146             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
147         eeprom->reg_chip_select =
148             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
149 }
150 
151 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
152 {
153         struct rt2x00_dev *rt2x00dev = eeprom->data;
154         u32 reg = 0;
155 
156         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
157         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
158         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
159                            !!eeprom->reg_data_clock);
160         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
161                            !!eeprom->reg_chip_select);
162 
163         rt2x00mmio_register_write(rt2x00dev, CSR21, reg);
164 }
165 
166 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
167 static const struct rt2x00debug rt2400pci_rt2x00debug = {
168         .owner  = THIS_MODULE,
169         .csr    = {
170                 .read           = rt2x00mmio_register_read,
171                 .write          = rt2x00mmio_register_write,
172                 .flags          = RT2X00DEBUGFS_OFFSET,
173                 .word_base      = CSR_REG_BASE,
174                 .word_size      = sizeof(u32),
175                 .word_count     = CSR_REG_SIZE / sizeof(u32),
176         },
177         .eeprom = {
178                 .read           = rt2x00_eeprom_read,
179                 .write          = rt2x00_eeprom_write,
180                 .word_base      = EEPROM_BASE,
181                 .word_size      = sizeof(u16),
182                 .word_count     = EEPROM_SIZE / sizeof(u16),
183         },
184         .bbp    = {
185                 .read           = rt2400pci_bbp_read,
186                 .write          = rt2400pci_bbp_write,
187                 .word_base      = BBP_BASE,
188                 .word_size      = sizeof(u8),
189                 .word_count     = BBP_SIZE / sizeof(u8),
190         },
191         .rf     = {
192                 .read           = rt2x00_rf_read,
193                 .write          = rt2400pci_rf_write,
194                 .word_base      = RF_BASE,
195                 .word_size      = sizeof(u32),
196                 .word_count     = RF_SIZE / sizeof(u32),
197         },
198 };
199 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
200 
201 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
202 {
203         u32 reg;
204 
205         rt2x00mmio_register_read(rt2x00dev, GPIOCSR, &reg);
206         return rt2x00_get_field32(reg, GPIOCSR_VAL0);
207 }
208 
209 #ifdef CONFIG_RT2X00_LIB_LEDS
210 static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
211                                      enum led_brightness brightness)
212 {
213         struct rt2x00_led *led =
214             container_of(led_cdev, struct rt2x00_led, led_dev);
215         unsigned int enabled = brightness != LED_OFF;
216         u32 reg;
217 
218         rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, &reg);
219 
220         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
221                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
222         else if (led->type == LED_TYPE_ACTIVITY)
223                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
224 
225         rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
226 }
227 
228 static int rt2400pci_blink_set(struct led_classdev *led_cdev,
229                                unsigned long *delay_on,
230                                unsigned long *delay_off)
231 {
232         struct rt2x00_led *led =
233             container_of(led_cdev, struct rt2x00_led, led_dev);
234         u32 reg;
235 
236         rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, &reg);
237         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
238         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
239         rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
240 
241         return 0;
242 }
243 
244 static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
245                                struct rt2x00_led *led,
246                                enum led_type type)
247 {
248         led->rt2x00dev = rt2x00dev;
249         led->type = type;
250         led->led_dev.brightness_set = rt2400pci_brightness_set;
251         led->led_dev.blink_set = rt2400pci_blink_set;
252         led->flags = LED_INITIALIZED;
253 }
254 #endif /* CONFIG_RT2X00_LIB_LEDS */
255 
256 /*
257  * Configuration handlers.
258  */
259 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
260                                     const unsigned int filter_flags)
261 {
262         u32 reg;
263 
264         /*
265          * Start configuration steps.
266          * Note that the version error will always be dropped
267          * since there is no filter for it at this time.
268          */
269         rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
270         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
271                            !(filter_flags & FIF_FCSFAIL));
272         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
273                            !(filter_flags & FIF_PLCPFAIL));
274         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
275                            !(filter_flags & FIF_CONTROL));
276         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
277                            !(filter_flags & FIF_PROMISC_IN_BSS));
278         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
279                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
280                            !rt2x00dev->intf_ap_count);
281         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
282         rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
283 }
284 
285 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
286                                   struct rt2x00_intf *intf,
287                                   struct rt2x00intf_conf *conf,
288                                   const unsigned int flags)
289 {
290         unsigned int bcn_preload;
291         u32 reg;
292 
293         if (flags & CONFIG_UPDATE_TYPE) {
294                 /*
295                  * Enable beacon config
296                  */
297                 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
298                 rt2x00mmio_register_read(rt2x00dev, BCNCSR1, &reg);
299                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
300                 rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg);
301 
302                 /*
303                  * Enable synchronisation.
304                  */
305                 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
306                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
307                 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
308         }
309 
310         if (flags & CONFIG_UPDATE_MAC)
311                 rt2x00mmio_register_multiwrite(rt2x00dev, CSR3,
312                                                conf->mac, sizeof(conf->mac));
313 
314         if (flags & CONFIG_UPDATE_BSSID)
315                 rt2x00mmio_register_multiwrite(rt2x00dev, CSR5,
316                                                conf->bssid,
317                                                sizeof(conf->bssid));
318 }
319 
320 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
321                                  struct rt2x00lib_erp *erp,
322                                  u32 changed)
323 {
324         int preamble_mask;
325         u32 reg;
326 
327         /*
328          * When short preamble is enabled, we should set bit 0x08
329          */
330         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
331                 preamble_mask = erp->short_preamble << 3;
332 
333                 rt2x00mmio_register_read(rt2x00dev, TXCSR1, &reg);
334                 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff);
335                 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a);
336                 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
337                 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
338                 rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg);
339 
340                 rt2x00mmio_register_read(rt2x00dev, ARCSR2, &reg);
341                 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
342                 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
343                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
344                                    GET_DURATION(ACK_SIZE, 10));
345                 rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg);
346 
347                 rt2x00mmio_register_read(rt2x00dev, ARCSR3, &reg);
348                 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
349                 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
350                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
351                                    GET_DURATION(ACK_SIZE, 20));
352                 rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg);
353 
354                 rt2x00mmio_register_read(rt2x00dev, ARCSR4, &reg);
355                 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
356                 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
357                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
358                                    GET_DURATION(ACK_SIZE, 55));
359                 rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg);
360 
361                 rt2x00mmio_register_read(rt2x00dev, ARCSR5, &reg);
362                 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
363                 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
364                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
365                                    GET_DURATION(ACK_SIZE, 110));
366                 rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg);
367         }
368 
369         if (changed & BSS_CHANGED_BASIC_RATES)
370                 rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
371 
372         if (changed & BSS_CHANGED_ERP_SLOT) {
373                 rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
374                 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
375                 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
376 
377                 rt2x00mmio_register_read(rt2x00dev, CSR18, &reg);
378                 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
379                 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
380                 rt2x00mmio_register_write(rt2x00dev, CSR18, reg);
381 
382                 rt2x00mmio_register_read(rt2x00dev, CSR19, &reg);
383                 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
384                 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
385                 rt2x00mmio_register_write(rt2x00dev, CSR19, reg);
386         }
387 
388         if (changed & BSS_CHANGED_BEACON_INT) {
389                 rt2x00mmio_register_read(rt2x00dev, CSR12, &reg);
390                 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
391                                    erp->beacon_int * 16);
392                 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
393                                    erp->beacon_int * 16);
394                 rt2x00mmio_register_write(rt2x00dev, CSR12, reg);
395         }
396 }
397 
398 static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
399                                  struct antenna_setup *ant)
400 {
401         u8 r1;
402         u8 r4;
403 
404         /*
405          * We should never come here because rt2x00lib is supposed
406          * to catch this and send us the correct antenna explicitely.
407          */
408         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
409                ant->tx == ANTENNA_SW_DIVERSITY);
410 
411         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
412         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
413 
414         /*
415          * Configure the TX antenna.
416          */
417         switch (ant->tx) {
418         case ANTENNA_HW_DIVERSITY:
419                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
420                 break;
421         case ANTENNA_A:
422                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
423                 break;
424         case ANTENNA_B:
425         default:
426                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
427                 break;
428         }
429 
430         /*
431          * Configure the RX antenna.
432          */
433         switch (ant->rx) {
434         case ANTENNA_HW_DIVERSITY:
435                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
436                 break;
437         case ANTENNA_A:
438                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
439                 break;
440         case ANTENNA_B:
441         default:
442                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
443                 break;
444         }
445 
446         rt2400pci_bbp_write(rt2x00dev, 4, r4);
447         rt2400pci_bbp_write(rt2x00dev, 1, r1);
448 }
449 
450 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
451                                      struct rf_channel *rf)
452 {
453         /*
454          * Switch on tuning bits.
455          */
456         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
457         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
458 
459         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
460         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
461         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
462 
463         /*
464          * RF2420 chipset don't need any additional actions.
465          */
466         if (rt2x00_rf(rt2x00dev, RF2420))
467                 return;
468 
469         /*
470          * For the RT2421 chipsets we need to write an invalid
471          * reference clock rate to activate auto_tune.
472          * After that we set the value back to the correct channel.
473          */
474         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
475         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
476         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
477 
478         msleep(1);
479 
480         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
481         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
482         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
483 
484         msleep(1);
485 
486         /*
487          * Switch off tuning bits.
488          */
489         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
490         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
491 
492         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
493         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
494 
495         /*
496          * Clear false CRC during channel switch.
497          */
498         rt2x00mmio_register_read(rt2x00dev, CNT0, &rf->rf1);
499 }
500 
501 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
502 {
503         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
504 }
505 
506 static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
507                                          struct rt2x00lib_conf *libconf)
508 {
509         u32 reg;
510 
511         rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
512         rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
513                            libconf->conf->long_frame_max_tx_count);
514         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
515                            libconf->conf->short_frame_max_tx_count);
516         rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
517 }
518 
519 static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
520                                 struct rt2x00lib_conf *libconf)
521 {
522         enum dev_state state =
523             (libconf->conf->flags & IEEE80211_CONF_PS) ?
524                 STATE_SLEEP : STATE_AWAKE;
525         u32 reg;
526 
527         if (state == STATE_SLEEP) {
528                 rt2x00mmio_register_read(rt2x00dev, CSR20, &reg);
529                 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
530                                    (rt2x00dev->beacon_int - 20) * 16);
531                 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
532                                    libconf->conf->listen_interval - 1);
533 
534                 /* We must first disable autowake before it can be enabled */
535                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
536                 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
537 
538                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
539                 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
540         } else {
541                 rt2x00mmio_register_read(rt2x00dev, CSR20, &reg);
542                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
543                 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
544         }
545 
546         rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
547 }
548 
549 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
550                              struct rt2x00lib_conf *libconf,
551                              const unsigned int flags)
552 {
553         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
554                 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
555         if (flags & IEEE80211_CONF_CHANGE_POWER)
556                 rt2400pci_config_txpower(rt2x00dev,
557                                          libconf->conf->power_level);
558         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
559                 rt2400pci_config_retry_limit(rt2x00dev, libconf);
560         if (flags & IEEE80211_CONF_CHANGE_PS)
561                 rt2400pci_config_ps(rt2x00dev, libconf);
562 }
563 
564 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
565                                 const int cw_min, const int cw_max)
566 {
567         u32 reg;
568 
569         rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
570         rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
571         rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
572         rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
573 }
574 
575 /*
576  * Link tuning
577  */
578 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
579                                  struct link_qual *qual)
580 {
581         u32 reg;
582         u8 bbp;
583 
584         /*
585          * Update FCS error count from register.
586          */
587         rt2x00mmio_register_read(rt2x00dev, CNT0, &reg);
588         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
589 
590         /*
591          * Update False CCA count from register.
592          */
593         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
594         qual->false_cca = bbp;
595 }
596 
597 static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
598                                      struct link_qual *qual, u8 vgc_level)
599 {
600         if (qual->vgc_level_reg != vgc_level) {
601                 rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
602                 qual->vgc_level = vgc_level;
603                 qual->vgc_level_reg = vgc_level;
604         }
605 }
606 
607 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
608                                   struct link_qual *qual)
609 {
610         rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
611 }
612 
613 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
614                                  struct link_qual *qual, const u32 count)
615 {
616         /*
617          * The link tuner should not run longer then 60 seconds,
618          * and should run once every 2 seconds.
619          */
620         if (count > 60 || !(count & 1))
621                 return;
622 
623         /*
624          * Base r13 link tuning on the false cca count.
625          */
626         if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
627                 rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
628         else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
629                 rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
630 }
631 
632 /*
633  * Queue handlers.
634  */
635 static void rt2400pci_start_queue(struct data_queue *queue)
636 {
637         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
638         u32 reg;
639 
640         switch (queue->qid) {
641         case QID_RX:
642                 rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
643                 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
644                 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
645                 break;
646         case QID_BEACON:
647                 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
648                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
649                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
650                 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
651                 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
652                 break;
653         default:
654                 break;
655         }
656 }
657 
658 static void rt2400pci_kick_queue(struct data_queue *queue)
659 {
660         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
661         u32 reg;
662 
663         switch (queue->qid) {
664         case QID_AC_VO:
665                 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
666                 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
667                 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
668                 break;
669         case QID_AC_VI:
670                 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
671                 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
672                 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
673                 break;
674         case QID_ATIM:
675                 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
676                 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
677                 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
678                 break;
679         default:
680                 break;
681         }
682 }
683 
684 static void rt2400pci_stop_queue(struct data_queue *queue)
685 {
686         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
687         u32 reg;
688 
689         switch (queue->qid) {
690         case QID_AC_VO:
691         case QID_AC_VI:
692         case QID_ATIM:
693                 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
694                 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
695                 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
696                 break;
697         case QID_RX:
698                 rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
699                 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
700                 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
701                 break;
702         case QID_BEACON:
703                 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
704                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
705                 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
706                 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
707                 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
708 
709                 /*
710                  * Wait for possibly running tbtt tasklets.
711                  */
712                 tasklet_kill(&rt2x00dev->tbtt_tasklet);
713                 break;
714         default:
715                 break;
716         }
717 }
718 
719 /*
720  * Initialization functions.
721  */
722 static bool rt2400pci_get_entry_state(struct queue_entry *entry)
723 {
724         struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
725         u32 word;
726 
727         if (entry->queue->qid == QID_RX) {
728                 rt2x00_desc_read(entry_priv->desc, 0, &word);
729 
730                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
731         } else {
732                 rt2x00_desc_read(entry_priv->desc, 0, &word);
733 
734                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
735                         rt2x00_get_field32(word, TXD_W0_VALID));
736         }
737 }
738 
739 static void rt2400pci_clear_entry(struct queue_entry *entry)
740 {
741         struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
742         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
743         u32 word;
744 
745         if (entry->queue->qid == QID_RX) {
746                 rt2x00_desc_read(entry_priv->desc, 2, &word);
747                 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
748                 rt2x00_desc_write(entry_priv->desc, 2, word);
749 
750                 rt2x00_desc_read(entry_priv->desc, 1, &word);
751                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
752                 rt2x00_desc_write(entry_priv->desc, 1, word);
753 
754                 rt2x00_desc_read(entry_priv->desc, 0, &word);
755                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
756                 rt2x00_desc_write(entry_priv->desc, 0, word);
757         } else {
758                 rt2x00_desc_read(entry_priv->desc, 0, &word);
759                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
760                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
761                 rt2x00_desc_write(entry_priv->desc, 0, word);
762         }
763 }
764 
765 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
766 {
767         struct queue_entry_priv_mmio *entry_priv;
768         u32 reg;
769 
770         /*
771          * Initialize registers.
772          */
773         rt2x00mmio_register_read(rt2x00dev, TXCSR2, &reg);
774         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
775         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
776         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
777         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
778         rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg);
779 
780         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
781         rt2x00mmio_register_read(rt2x00dev, TXCSR3, &reg);
782         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
783                            entry_priv->desc_dma);
784         rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg);
785 
786         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
787         rt2x00mmio_register_read(rt2x00dev, TXCSR5, &reg);
788         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
789                            entry_priv->desc_dma);
790         rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg);
791 
792         entry_priv = rt2x00dev->atim->entries[0].priv_data;
793         rt2x00mmio_register_read(rt2x00dev, TXCSR4, &reg);
794         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
795                            entry_priv->desc_dma);
796         rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg);
797 
798         entry_priv = rt2x00dev->bcn->entries[0].priv_data;
799         rt2x00mmio_register_read(rt2x00dev, TXCSR6, &reg);
800         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
801                            entry_priv->desc_dma);
802         rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg);
803 
804         rt2x00mmio_register_read(rt2x00dev, RXCSR1, &reg);
805         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
806         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
807         rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg);
808 
809         entry_priv = rt2x00dev->rx->entries[0].priv_data;
810         rt2x00mmio_register_read(rt2x00dev, RXCSR2, &reg);
811         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
812                            entry_priv->desc_dma);
813         rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg);
814 
815         return 0;
816 }
817 
818 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
819 {
820         u32 reg;
821 
822         rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002);
823         rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002);
824         rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00023f20);
825         rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002);
826 
827         rt2x00mmio_register_read(rt2x00dev, TIMECSR, &reg);
828         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
829         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
830         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
831         rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg);
832 
833         rt2x00mmio_register_read(rt2x00dev, CSR9, &reg);
834         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
835                            (rt2x00dev->rx->data_size / 128));
836         rt2x00mmio_register_write(rt2x00dev, CSR9, reg);
837 
838         rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
839         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
840         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
841         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
842         rt2x00_set_field32(&reg, CSR14_TCFP, 0);
843         rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
844         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
845         rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
846         rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
847         rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
848 
849         rt2x00mmio_register_write(rt2x00dev, CNT3, 0x3f080000);
850 
851         rt2x00mmio_register_read(rt2x00dev, ARCSR0, &reg);
852         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
853         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
854         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
855         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
856         rt2x00mmio_register_write(rt2x00dev, ARCSR0, reg);
857 
858         rt2x00mmio_register_read(rt2x00dev, RXCSR3, &reg);
859         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
860         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
861         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
862         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
863         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
864         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
865         rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg);
866 
867         rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
868 
869         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
870                 return -EBUSY;
871 
872         rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00217223);
873         rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518);
874 
875         rt2x00mmio_register_read(rt2x00dev, MACCSR2, &reg);
876         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
877         rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg);
878 
879         rt2x00mmio_register_read(rt2x00dev, RALINKCSR, &reg);
880         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
881         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
882         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
883         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
884         rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg);
885 
886         rt2x00mmio_register_read(rt2x00dev, CSR1, &reg);
887         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
888         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
889         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
890         rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
891 
892         rt2x00mmio_register_read(rt2x00dev, CSR1, &reg);
893         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
894         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
895         rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
896 
897         /*
898          * We must clear the FCS and FIFO error count.
899          * These registers are cleared on read,
900          * so we may pass a useless variable to store the value.
901          */
902         rt2x00mmio_register_read(rt2x00dev, CNT0, &reg);
903         rt2x00mmio_register_read(rt2x00dev, CNT4, &reg);
904 
905         return 0;
906 }
907 
908 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
909 {
910         unsigned int i;
911         u8 value;
912 
913         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
914                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
915                 if ((value != 0xff) && (value != 0x00))
916                         return 0;
917                 udelay(REGISTER_BUSY_DELAY);
918         }
919 
920         rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
921         return -EACCES;
922 }
923 
924 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
925 {
926         unsigned int i;
927         u16 eeprom;
928         u8 reg_id;
929         u8 value;
930 
931         if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
932                 return -EACCES;
933 
934         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
935         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
936         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
937         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
938         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
939         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
940         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
941         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
942         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
943         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
944         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
945         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
946         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
947         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
948 
949         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
950                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
951 
952                 if (eeprom != 0xffff && eeprom != 0x0000) {
953                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
954                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
955                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
956                 }
957         }
958 
959         return 0;
960 }
961 
962 /*
963  * Device state switch handlers.
964  */
965 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
966                                  enum dev_state state)
967 {
968         int mask = (state == STATE_RADIO_IRQ_OFF);
969         u32 reg;
970         unsigned long flags;
971 
972         /*
973          * When interrupts are being enabled, the interrupt registers
974          * should clear the register to assure a clean state.
975          */
976         if (state == STATE_RADIO_IRQ_ON) {
977                 rt2x00mmio_register_read(rt2x00dev, CSR7, &reg);
978                 rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
979         }
980 
981         /*
982          * Only toggle the interrupts bits we are going to use.
983          * Non-checked interrupt bits are disabled by default.
984          */
985         spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
986 
987         rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
988         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
989         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
990         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
991         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
992         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
993         rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
994 
995         spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
996 
997         if (state == STATE_RADIO_IRQ_OFF) {
998                 /*
999                  * Ensure that all tasklets are finished before
1000                  * disabling the interrupts.
1001                  */
1002                 tasklet_kill(&rt2x00dev->txstatus_tasklet);
1003                 tasklet_kill(&rt2x00dev->rxdone_tasklet);
1004                 tasklet_kill(&rt2x00dev->tbtt_tasklet);
1005         }
1006 }
1007 
1008 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1009 {
1010         /*
1011          * Initialize all registers.
1012          */
1013         if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
1014                      rt2400pci_init_registers(rt2x00dev) ||
1015                      rt2400pci_init_bbp(rt2x00dev)))
1016                 return -EIO;
1017 
1018         return 0;
1019 }
1020 
1021 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1022 {
1023         /*
1024          * Disable power
1025          */
1026         rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0);
1027 }
1028 
1029 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
1030                                enum dev_state state)
1031 {
1032         u32 reg, reg2;
1033         unsigned int i;
1034         char put_to_sleep;
1035         char bbp_state;
1036         char rf_state;
1037 
1038         put_to_sleep = (state != STATE_AWAKE);
1039 
1040         rt2x00mmio_register_read(rt2x00dev, PWRCSR1, &reg);
1041         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1042         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1043         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1044         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1045         rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1046 
1047         /*
1048          * Device is not guaranteed to be in the requested state yet.
1049          * We must wait until the register indicates that the
1050          * device has entered the correct state.
1051          */
1052         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1053                 rt2x00mmio_register_read(rt2x00dev, PWRCSR1, &reg2);
1054                 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
1055                 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
1056                 if (bbp_state == state && rf_state == state)
1057                         return 0;
1058                 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1059                 msleep(10);
1060         }
1061 
1062         return -EBUSY;
1063 }
1064 
1065 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1066                                       enum dev_state state)
1067 {
1068         int retval = 0;
1069 
1070         switch (state) {
1071         case STATE_RADIO_ON:
1072                 retval = rt2400pci_enable_radio(rt2x00dev);
1073                 break;
1074         case STATE_RADIO_OFF:
1075                 rt2400pci_disable_radio(rt2x00dev);
1076                 break;
1077         case STATE_RADIO_IRQ_ON:
1078         case STATE_RADIO_IRQ_OFF:
1079                 rt2400pci_toggle_irq(rt2x00dev, state);
1080                 break;
1081         case STATE_DEEP_SLEEP:
1082         case STATE_SLEEP:
1083         case STATE_STANDBY:
1084         case STATE_AWAKE:
1085                 retval = rt2400pci_set_state(rt2x00dev, state);
1086                 break;
1087         default:
1088                 retval = -ENOTSUPP;
1089                 break;
1090         }
1091 
1092         if (unlikely(retval))
1093                 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
1094                            state, retval);
1095 
1096         return retval;
1097 }
1098 
1099 /*
1100  * TX descriptor initialization
1101  */
1102 static void rt2400pci_write_tx_desc(struct queue_entry *entry,
1103                                     struct txentry_desc *txdesc)
1104 {
1105         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1106         struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1107         __le32 *txd = entry_priv->desc;
1108         u32 word;
1109 
1110         /*
1111          * Start writing the descriptor words.
1112          */
1113         rt2x00_desc_read(txd, 1, &word);
1114         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1115         rt2x00_desc_write(txd, 1, word);
1116 
1117         rt2x00_desc_read(txd, 2, &word);
1118         rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
1119         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
1120         rt2x00_desc_write(txd, 2, word);
1121 
1122         rt2x00_desc_read(txd, 3, &word);
1123         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
1124         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1125         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1126         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
1127         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1128         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1129         rt2x00_desc_write(txd, 3, word);
1130 
1131         rt2x00_desc_read(txd, 4, &word);
1132         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW,
1133                            txdesc->u.plcp.length_low);
1134         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1135         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1136         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH,
1137                            txdesc->u.plcp.length_high);
1138         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1139         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1140         rt2x00_desc_write(txd, 4, word);
1141 
1142         /*
1143          * Writing TXD word 0 must the last to prevent a race condition with
1144          * the device, whereby the device may take hold of the TXD before we
1145          * finished updating it.
1146          */
1147         rt2x00_desc_read(txd, 0, &word);
1148         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1149         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1150         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1151                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1152         rt2x00_set_field32(&word, TXD_W0_ACK,
1153                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1154         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1155                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1156         rt2x00_set_field32(&word, TXD_W0_RTS,
1157                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1158         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1159         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1160                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1161         rt2x00_desc_write(txd, 0, word);
1162 
1163         /*
1164          * Register descriptor details in skb frame descriptor.
1165          */
1166         skbdesc->desc = txd;
1167         skbdesc->desc_len = TXD_DESC_SIZE;
1168 }
1169 
1170 /*
1171  * TX data initialization
1172  */
1173 static void rt2400pci_write_beacon(struct queue_entry *entry,
1174                                    struct txentry_desc *txdesc)
1175 {
1176         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1177         u32 reg;
1178 
1179         /*
1180          * Disable beaconing while we are reloading the beacon data,
1181          * otherwise we might be sending out invalid data.
1182          */
1183         rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
1184         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1185         rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1186 
1187         if (rt2x00queue_map_txskb(entry)) {
1188                 rt2x00_err(rt2x00dev, "Fail to map beacon, aborting\n");
1189                 goto out;
1190         }
1191         /*
1192          * Enable beaconing again.
1193          */
1194         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1195         /*
1196          * Write the TX descriptor for the beacon.
1197          */
1198         rt2400pci_write_tx_desc(entry, txdesc);
1199 
1200         /*
1201          * Dump beacon to userspace through debugfs.
1202          */
1203         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1204 out:
1205         /*
1206          * Enable beaconing again.
1207          */
1208         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1209         rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1210 }
1211 
1212 /*
1213  * RX control handlers
1214  */
1215 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1216                                   struct rxdone_entry_desc *rxdesc)
1217 {
1218         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1219         struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1220         u32 word0;
1221         u32 word2;
1222         u32 word3;
1223         u32 word4;
1224         u64 tsf;
1225         u32 rx_low;
1226         u32 rx_high;
1227 
1228         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1229         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1230         rt2x00_desc_read(entry_priv->desc, 3, &word3);
1231         rt2x00_desc_read(entry_priv->desc, 4, &word4);
1232 
1233         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1234                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1235         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1236                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1237 
1238         /*
1239          * We only get the lower 32bits from the timestamp,
1240          * to get the full 64bits we must complement it with
1241          * the timestamp from get_tsf().
1242          * Note that when a wraparound of the lower 32bits
1243          * has occurred between the frame arrival and the get_tsf()
1244          * call, we must decrease the higher 32bits with 1 to get
1245          * to correct value.
1246          */
1247         tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw, NULL);
1248         rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1249         rx_high = upper_32_bits(tsf);
1250 
1251         if ((u32)tsf <= rx_low)
1252                 rx_high--;
1253 
1254         /*
1255          * Obtain the status about this packet.
1256          * The signal is the PLCP value, and needs to be stripped
1257          * of the preamble bit (0x08).
1258          */
1259         rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
1260         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1261         rxdesc->rssi = rt2x00_get_field32(word3, RXD_W3_RSSI) -
1262             entry->queue->rt2x00dev->rssi_offset;
1263         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1264 
1265         rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1266         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1267                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1268 }
1269 
1270 /*
1271  * Interrupt functions.
1272  */
1273 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1274                              const enum data_queue_qid queue_idx)
1275 {
1276         struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
1277         struct queue_entry_priv_mmio *entry_priv;
1278         struct queue_entry *entry;
1279         struct txdone_entry_desc txdesc;
1280         u32 word;
1281 
1282         while (!rt2x00queue_empty(queue)) {
1283                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1284                 entry_priv = entry->priv_data;
1285                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1286 
1287                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1288                     !rt2x00_get_field32(word, TXD_W0_VALID))
1289                         break;
1290 
1291                 /*
1292                  * Obtain the status about this packet.
1293                  */
1294                 txdesc.flags = 0;
1295                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1296                 case 0: /* Success */
1297                 case 1: /* Success with retry */
1298                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1299                         break;
1300                 case 2: /* Failure, excessive retries */
1301                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1302                         /* Don't break, this is a failed frame! */
1303                 default: /* Failure */
1304                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1305                 }
1306                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1307 
1308                 rt2x00lib_txdone(entry, &txdesc);
1309         }
1310 }
1311 
1312 static inline void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
1313                                               struct rt2x00_field32 irq_field)
1314 {
1315         u32 reg;
1316 
1317         /*
1318          * Enable a single interrupt. The interrupt mask register
1319          * access needs locking.
1320          */
1321         spin_lock_irq(&rt2x00dev->irqmask_lock);
1322 
1323         rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
1324         rt2x00_set_field32(&reg, irq_field, 0);
1325         rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1326 
1327         spin_unlock_irq(&rt2x00dev->irqmask_lock);
1328 }
1329 
1330 static void rt2400pci_txstatus_tasklet(unsigned long data)
1331 {
1332         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1333         u32 reg;
1334 
1335         /*
1336          * Handle all tx queues.
1337          */
1338         rt2400pci_txdone(rt2x00dev, QID_ATIM);
1339         rt2400pci_txdone(rt2x00dev, QID_AC_VO);
1340         rt2400pci_txdone(rt2x00dev, QID_AC_VI);
1341 
1342         /*
1343          * Enable all TXDONE interrupts again.
1344          */
1345         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) {
1346                 spin_lock_irq(&rt2x00dev->irqmask_lock);
1347 
1348                 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
1349                 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
1350                 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
1351                 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
1352                 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1353 
1354                 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1355         }
1356 }
1357 
1358 static void rt2400pci_tbtt_tasklet(unsigned long data)
1359 {
1360         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1361         rt2x00lib_beacondone(rt2x00dev);
1362         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1363                 rt2400pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
1364 }
1365 
1366 static void rt2400pci_rxdone_tasklet(unsigned long data)
1367 {
1368         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1369         if (rt2x00mmio_rxdone(rt2x00dev))
1370                 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1371         else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1372                 rt2400pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
1373 }
1374 
1375 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1376 {
1377         struct rt2x00_dev *rt2x00dev = dev_instance;
1378         u32 reg, mask;
1379 
1380         /*
1381          * Get the interrupt sources & saved to local variable.
1382          * Write register value back to clear pending interrupts.
1383          */
1384         rt2x00mmio_register_read(rt2x00dev, CSR7, &reg);
1385         rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
1386 
1387         if (!reg)
1388                 return IRQ_NONE;
1389 
1390         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1391                 return IRQ_HANDLED;
1392 
1393         mask = reg;
1394 
1395         /*
1396          * Schedule tasklets for interrupt handling.
1397          */
1398         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1399                 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1400 
1401         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1402                 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1403 
1404         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
1405             rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
1406             rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
1407                 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1408                 /*
1409                  * Mask out all txdone interrupts.
1410                  */
1411                 rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
1412                 rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
1413                 rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
1414         }
1415 
1416         /*
1417          * Disable all interrupts for which a tasklet was scheduled right now,
1418          * the tasklet will reenable the appropriate interrupts.
1419          */
1420         spin_lock(&rt2x00dev->irqmask_lock);
1421 
1422         rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
1423         reg |= mask;
1424         rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1425 
1426         spin_unlock(&rt2x00dev->irqmask_lock);
1427 
1428 
1429 
1430         return IRQ_HANDLED;
1431 }
1432 
1433 /*
1434  * Device probe functions.
1435  */
1436 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1437 {
1438         struct eeprom_93cx6 eeprom;
1439         u32 reg;
1440         u16 word;
1441         u8 *mac;
1442 
1443         rt2x00mmio_register_read(rt2x00dev, CSR21, &reg);
1444 
1445         eeprom.data = rt2x00dev;
1446         eeprom.register_read = rt2400pci_eepromregister_read;
1447         eeprom.register_write = rt2400pci_eepromregister_write;
1448         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1449             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1450         eeprom.reg_data_in = 0;
1451         eeprom.reg_data_out = 0;
1452         eeprom.reg_data_clock = 0;
1453         eeprom.reg_chip_select = 0;
1454 
1455         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1456                                EEPROM_SIZE / sizeof(u16));
1457 
1458         /*
1459          * Start validation of the data that has been read.
1460          */
1461         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1462         if (!is_valid_ether_addr(mac)) {
1463                 eth_random_addr(mac);
1464                 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
1465         }
1466 
1467         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1468         if (word == 0xffff) {
1469                 rt2x00_err(rt2x00dev, "Invalid EEPROM data detected\n");
1470                 return -EINVAL;
1471         }
1472 
1473         return 0;
1474 }
1475 
1476 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1477 {
1478         u32 reg;
1479         u16 value;
1480         u16 eeprom;
1481 
1482         /*
1483          * Read EEPROM word for configuration.
1484          */
1485         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1486 
1487         /*
1488          * Identify RF chipset.
1489          */
1490         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1491         rt2x00mmio_register_read(rt2x00dev, CSR0, &reg);
1492         rt2x00_set_chip(rt2x00dev, RT2460, value,
1493                         rt2x00_get_field32(reg, CSR0_REVISION));
1494 
1495         if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
1496                 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
1497                 return -ENODEV;
1498         }
1499 
1500         /*
1501          * Identify default antenna configuration.
1502          */
1503         rt2x00dev->default_ant.tx =
1504             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1505         rt2x00dev->default_ant.rx =
1506             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1507 
1508         /*
1509          * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1510          * I am not 100% sure about this, but the legacy drivers do not
1511          * indicate antenna swapping in software is required when
1512          * diversity is enabled.
1513          */
1514         if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1515                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1516         if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1517                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1518 
1519         /*
1520          * Store led mode, for correct led behaviour.
1521          */
1522 #ifdef CONFIG_RT2X00_LIB_LEDS
1523         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1524 
1525         rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1526         if (value == LED_MODE_TXRX_ACTIVITY ||
1527             value == LED_MODE_DEFAULT ||
1528             value == LED_MODE_ASUS)
1529                 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1530                                    LED_TYPE_ACTIVITY);
1531 #endif /* CONFIG_RT2X00_LIB_LEDS */
1532 
1533         /*
1534          * Detect if this device has an hardware controlled radio.
1535          */
1536         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1537                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
1538 
1539         /*
1540          * Check if the BBP tuning should be enabled.
1541          */
1542         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1543                 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
1544 
1545         return 0;
1546 }
1547 
1548 /*
1549  * RF value list for RF2420 & RF2421
1550  * Supports: 2.4 GHz
1551  */
1552 static const struct rf_channel rf_vals_b[] = {
1553         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1554         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1555         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1556         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1557         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1558         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1559         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1560         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1561         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1562         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1563         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1564         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1565         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1566         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1567 };
1568 
1569 static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1570 {
1571         struct hw_mode_spec *spec = &rt2x00dev->spec;
1572         struct channel_info *info;
1573         char *tx_power;
1574         unsigned int i;
1575 
1576         /*
1577          * Initialize all hw fields.
1578          */
1579         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1580                                IEEE80211_HW_SIGNAL_DBM |
1581                                IEEE80211_HW_SUPPORTS_PS |
1582                                IEEE80211_HW_PS_NULLFUNC_STACK;
1583 
1584         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1585         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1586                                 rt2x00_eeprom_addr(rt2x00dev,
1587                                                    EEPROM_MAC_ADDR_0));
1588 
1589         /*
1590          * Initialize hw_mode information.
1591          */
1592         spec->supported_bands = SUPPORT_BAND_2GHZ;
1593         spec->supported_rates = SUPPORT_RATE_CCK;
1594 
1595         spec->num_channels = ARRAY_SIZE(rf_vals_b);
1596         spec->channels = rf_vals_b;
1597 
1598         /*
1599          * Create channel information array
1600          */
1601         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
1602         if (!info)
1603                 return -ENOMEM;
1604 
1605         spec->channels_info = info;
1606 
1607         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1608         for (i = 0; i < 14; i++) {
1609                 info[i].max_power = TXPOWER_FROM_DEV(MAX_TXPOWER);
1610                 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1611         }
1612 
1613         return 0;
1614 }
1615 
1616 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1617 {
1618         int retval;
1619         u32 reg;
1620 
1621         /*
1622          * Allocate eeprom data.
1623          */
1624         retval = rt2400pci_validate_eeprom(rt2x00dev);
1625         if (retval)
1626                 return retval;
1627 
1628         retval = rt2400pci_init_eeprom(rt2x00dev);
1629         if (retval)
1630                 return retval;
1631 
1632         /*
1633          * Enable rfkill polling by setting GPIO direction of the
1634          * rfkill switch GPIO pin correctly.
1635          */
1636         rt2x00mmio_register_read(rt2x00dev, GPIOCSR, &reg);
1637         rt2x00_set_field32(&reg, GPIOCSR_DIR0, 1);
1638         rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg);
1639 
1640         /*
1641          * Initialize hw specifications.
1642          */
1643         retval = rt2400pci_probe_hw_mode(rt2x00dev);
1644         if (retval)
1645                 return retval;
1646 
1647         /*
1648          * This device requires the atim queue and DMA-mapped skbs.
1649          */
1650         __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
1651         __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
1652         __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
1653 
1654         /*
1655          * Set the rssi offset.
1656          */
1657         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1658 
1659         return 0;
1660 }
1661 
1662 /*
1663  * IEEE80211 stack callback functions.
1664  */
1665 static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1666                              struct ieee80211_vif *vif, u16 queue,
1667                              const struct ieee80211_tx_queue_params *params)
1668 {
1669         struct rt2x00_dev *rt2x00dev = hw->priv;
1670 
1671         /*
1672          * We don't support variating cw_min and cw_max variables
1673          * per queue. So by default we only configure the TX queue,
1674          * and ignore all other configurations.
1675          */
1676         if (queue != 0)
1677                 return -EINVAL;
1678 
1679         if (rt2x00mac_conf_tx(hw, vif, queue, params))
1680                 return -EINVAL;
1681 
1682         /*
1683          * Write configuration to register.
1684          */
1685         rt2400pci_config_cw(rt2x00dev,
1686                             rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1687 
1688         return 0;
1689 }
1690 
1691 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw,
1692                              struct ieee80211_vif *vif)
1693 {
1694         struct rt2x00_dev *rt2x00dev = hw->priv;
1695         u64 tsf;
1696         u32 reg;
1697 
1698         rt2x00mmio_register_read(rt2x00dev, CSR17, &reg);
1699         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1700         rt2x00mmio_register_read(rt2x00dev, CSR16, &reg);
1701         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1702 
1703         return tsf;
1704 }
1705 
1706 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1707 {
1708         struct rt2x00_dev *rt2x00dev = hw->priv;
1709         u32 reg;
1710 
1711         rt2x00mmio_register_read(rt2x00dev, CSR15, &reg);
1712         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1713 }
1714 
1715 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1716         .tx                     = rt2x00mac_tx,
1717         .start                  = rt2x00mac_start,
1718         .stop                   = rt2x00mac_stop,
1719         .add_interface          = rt2x00mac_add_interface,
1720         .remove_interface       = rt2x00mac_remove_interface,
1721         .config                 = rt2x00mac_config,
1722         .configure_filter       = rt2x00mac_configure_filter,
1723         .sw_scan_start          = rt2x00mac_sw_scan_start,
1724         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
1725         .get_stats              = rt2x00mac_get_stats,
1726         .bss_info_changed       = rt2x00mac_bss_info_changed,
1727         .conf_tx                = rt2400pci_conf_tx,
1728         .get_tsf                = rt2400pci_get_tsf,
1729         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1730         .rfkill_poll            = rt2x00mac_rfkill_poll,
1731         .flush                  = rt2x00mac_flush,
1732         .set_antenna            = rt2x00mac_set_antenna,
1733         .get_antenna            = rt2x00mac_get_antenna,
1734         .get_ringparam          = rt2x00mac_get_ringparam,
1735         .tx_frames_pending      = rt2x00mac_tx_frames_pending,
1736 };
1737 
1738 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1739         .irq_handler            = rt2400pci_interrupt,
1740         .txstatus_tasklet       = rt2400pci_txstatus_tasklet,
1741         .tbtt_tasklet           = rt2400pci_tbtt_tasklet,
1742         .rxdone_tasklet         = rt2400pci_rxdone_tasklet,
1743         .probe_hw               = rt2400pci_probe_hw,
1744         .initialize             = rt2x00mmio_initialize,
1745         .uninitialize           = rt2x00mmio_uninitialize,
1746         .get_entry_state        = rt2400pci_get_entry_state,
1747         .clear_entry            = rt2400pci_clear_entry,
1748         .set_device_state       = rt2400pci_set_device_state,
1749         .rfkill_poll            = rt2400pci_rfkill_poll,
1750         .link_stats             = rt2400pci_link_stats,
1751         .reset_tuner            = rt2400pci_reset_tuner,
1752         .link_tuner             = rt2400pci_link_tuner,
1753         .start_queue            = rt2400pci_start_queue,
1754         .kick_queue             = rt2400pci_kick_queue,
1755         .stop_queue             = rt2400pci_stop_queue,
1756         .flush_queue            = rt2x00mmio_flush_queue,
1757         .write_tx_desc          = rt2400pci_write_tx_desc,
1758         .write_beacon           = rt2400pci_write_beacon,
1759         .fill_rxdone            = rt2400pci_fill_rxdone,
1760         .config_filter          = rt2400pci_config_filter,
1761         .config_intf            = rt2400pci_config_intf,
1762         .config_erp             = rt2400pci_config_erp,
1763         .config_ant             = rt2400pci_config_ant,
1764         .config                 = rt2400pci_config,
1765 };
1766 
1767 static void rt2400pci_queue_init(struct data_queue *queue)
1768 {
1769         switch (queue->qid) {
1770         case QID_RX:
1771                 queue->limit = 24;
1772                 queue->data_size = DATA_FRAME_SIZE;
1773                 queue->desc_size = RXD_DESC_SIZE;
1774                 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1775                 break;
1776 
1777         case QID_AC_VO:
1778         case QID_AC_VI:
1779         case QID_AC_BE:
1780         case QID_AC_BK:
1781                 queue->limit = 24;
1782                 queue->data_size = DATA_FRAME_SIZE;
1783                 queue->desc_size = TXD_DESC_SIZE;
1784                 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1785                 break;
1786 
1787         case QID_BEACON:
1788                 queue->limit = 1;
1789                 queue->data_size = MGMT_FRAME_SIZE;
1790                 queue->desc_size = TXD_DESC_SIZE;
1791                 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1792                 break;
1793 
1794         case QID_ATIM:
1795                 queue->limit = 8;
1796                 queue->data_size = DATA_FRAME_SIZE;
1797                 queue->desc_size = TXD_DESC_SIZE;
1798                 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1799                 break;
1800 
1801         default:
1802                 BUG();
1803                 break;
1804         }
1805 }
1806 
1807 static const struct rt2x00_ops rt2400pci_ops = {
1808         .name                   = KBUILD_MODNAME,
1809         .max_ap_intf            = 1,
1810         .eeprom_size            = EEPROM_SIZE,
1811         .rf_size                = RF_SIZE,
1812         .tx_queues              = NUM_TX_QUEUES,
1813         .queue_init             = rt2400pci_queue_init,
1814         .lib                    = &rt2400pci_rt2x00_ops,
1815         .hw                     = &rt2400pci_mac80211_ops,
1816 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1817         .debugfs                = &rt2400pci_rt2x00debug,
1818 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1819 };
1820 
1821 /*
1822  * RT2400pci module information.
1823  */
1824 static const struct pci_device_id rt2400pci_device_table[] = {
1825         { PCI_DEVICE(0x1814, 0x0101) },
1826         { 0, }
1827 };
1828 
1829 
1830 MODULE_AUTHOR(DRV_PROJECT);
1831 MODULE_VERSION(DRV_VERSION);
1832 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1833 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1834 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1835 MODULE_LICENSE("GPL");
1836 
1837 static int rt2400pci_probe(struct pci_dev *pci_dev,
1838                            const struct pci_device_id *id)
1839 {
1840         return rt2x00pci_probe(pci_dev, &rt2400pci_ops);
1841 }
1842 
1843 static struct pci_driver rt2400pci_driver = {
1844         .name           = KBUILD_MODNAME,
1845         .id_table       = rt2400pci_device_table,
1846         .probe          = rt2400pci_probe,
1847         .remove         = rt2x00pci_remove,
1848         .suspend        = rt2x00pci_suspend,
1849         .resume         = rt2x00pci_resume,
1850 };
1851 
1852 module_pci_driver(rt2400pci_driver);
1853 

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