Linux/drivers/net/wireless/ath/ath5k/eeprom.h

  1 /*
  2  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
  3  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
  4  *
  5  * Permission to use, copy, modify, and distribute this software for any
  6  * purpose with or without fee is hereby granted, provided that the above
  7  * copyright notice and this permission notice appear in all copies.
  8  *
  9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 16  *
 17  */
 18 
 19 /*
 20  * Common ar5xxx EEPROM data offsets (set these on AR5K_EEPROM_BASE)
 21  */
 22 #define AR5K_EEPROM_PCIE_OFFSET         0x02    /* Contains offset to PCI-E infos */
 23 #define AR5K_EEPROM_PCIE_SERDES_SECTION 0x40    /* PCIE_OFFSET points here when
 24                                                  * SERDES infos are present */
 25 #define AR5K_EEPROM_MAGIC               0x003d  /* EEPROM Magic number */
 26 #define AR5K_EEPROM_MAGIC_VALUE         0x5aa5  /* Default - found on EEPROM */
 27 
 28 #define AR5K_EEPROM_IS_HB63             0x000b  /* Talon detect */
 29 
 30 #define AR5K_EEPROM_RFKILL              0x0f
 31 #define AR5K_EEPROM_RFKILL_GPIO_SEL     0x0000001c
 32 #define AR5K_EEPROM_RFKILL_GPIO_SEL_S   2
 33 #define AR5K_EEPROM_RFKILL_POLARITY     0x00000002
 34 #define AR5K_EEPROM_RFKILL_POLARITY_S   1
 35 
 36 #define AR5K_EEPROM_REG_DOMAIN          0x00bf  /* EEPROM regdom */
 37 
 38 /* FLASH(EEPROM) Defines for AR531X chips */
 39 #define AR5K_EEPROM_SIZE_LOWER          0x1b /* size info -- lower */
 40 #define AR5K_EEPROM_SIZE_UPPER          0x1c /* size info -- upper */
 41 #define AR5K_EEPROM_SIZE_UPPER_MASK     0xfff0
 42 #define AR5K_EEPROM_SIZE_UPPER_SHIFT    4
 43 #define AR5K_EEPROM_SIZE_ENDLOC_SHIFT   12
 44 
 45 #define AR5K_EEPROM_CHECKSUM            0x00c0  /* EEPROM checksum */
 46 #define AR5K_EEPROM_INFO_BASE           0x00c0  /* EEPROM header */
 47 #define AR5K_EEPROM_INFO_MAX            (0x400 - AR5K_EEPROM_INFO_BASE)
 48 #define AR5K_EEPROM_INFO_CKSUM          0xffff
 49 #define AR5K_EEPROM_INFO(_n)            (AR5K_EEPROM_INFO_BASE + (_n))
 50 
 51 #define AR5K_EEPROM_VERSION             AR5K_EEPROM_INFO(1)     /* EEPROM Version */
 52 #define AR5K_EEPROM_VERSION_3_0         0x3000  /* No idea what's going on before this version */
 53 #define AR5K_EEPROM_VERSION_3_1         0x3001  /* ob/db values for 2Ghz (ar5211_rfregs) */
 54 #define AR5K_EEPROM_VERSION_3_2         0x3002  /* different frequency representation (eeprom_bin2freq) */
 55 #define AR5K_EEPROM_VERSION_3_3         0x3003  /* offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes) */
 56 #define AR5K_EEPROM_VERSION_3_4         0x3004  /* has ee_i_gain, ee_cck_ofdm_power_delta (eeprom_read_modes) */
 57 #define AR5K_EEPROM_VERSION_4_0         0x4000  /* has ee_misc, ee_cal_pier, ee_turbo_max_power and ee_xr_power (eeprom_init) */
 58 #define AR5K_EEPROM_VERSION_4_1         0x4001  /* has ee_margin_tx_rx (eeprom_init) */
 59 #define AR5K_EEPROM_VERSION_4_2         0x4002  /* has ee_cck_ofdm_gain_delta (eeprom_init) */
 60 #define AR5K_EEPROM_VERSION_4_3         0x4003  /* power calibration changes */
 61 #define AR5K_EEPROM_VERSION_4_4         0x4004
 62 #define AR5K_EEPROM_VERSION_4_5         0x4005
 63 #define AR5K_EEPROM_VERSION_4_6         0x4006  /* has ee_scaled_cck_delta */
 64 #define AR5K_EEPROM_VERSION_4_7         0x3007  /* 4007 ? */
 65 #define AR5K_EEPROM_VERSION_4_9         0x4009  /* EAR futureproofing */
 66 #define AR5K_EEPROM_VERSION_5_0         0x5000  /* Has 2413 PDADC calibration etc */
 67 #define AR5K_EEPROM_VERSION_5_1         0x5001  /* Has capability values */
 68 #define AR5K_EEPROM_VERSION_5_3         0x5003  /* Has spur mitigation tables */
 69 
 70 #define AR5K_EEPROM_MODE_11A            0
 71 #define AR5K_EEPROM_MODE_11B            1
 72 #define AR5K_EEPROM_MODE_11G            2
 73 
 74 #define AR5K_EEPROM_HDR                 AR5K_EEPROM_INFO(2)     /* Header that contains the device caps */
 75 #define AR5K_EEPROM_HDR_11A(_v)         (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1)
 76 #define AR5K_EEPROM_HDR_11B(_v)         (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1)
 77 #define AR5K_EEPROM_HDR_11G(_v)         (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1)
 78 #define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v)  (((_v) >> 3) & 0x1)     /* Disable turbo for 2Ghz */
 79 #define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v)  (((_v) >> 4) & 0x7f)    /* Max turbo power for < 2W power consumption */
 80 #define AR5K_EEPROM_HDR_DEVICE(_v)      (((_v) >> 11) & 0x7)    /* Device type (1 Cardbus, 2 PCI, 3 MiniPCI, 4 AP) */
 81 #define AR5K_EEPROM_HDR_RFKILL(_v)      (((_v) >> 14) & 0x1)    /* Device has RFKill support */
 82 #define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v)  (((_v) >> 15) & 0x1)    /* Disable turbo for 5Ghz */
 83 
 84 /* Newer EEPROMs are using a different offset */
 85 #define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \
 86         (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0)
 87 
 88 #define AR5K_EEPROM_ANT_GAIN(_v)        AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3)
 89 #define AR5K_EEPROM_ANT_GAIN_5GHZ(_v)   ((s8)(((_v) >> 8) & 0xff))
 90 #define AR5K_EEPROM_ANT_GAIN_2GHZ(_v)   ((s8)((_v) & 0xff))
 91 
 92 /* Misc values available since EEPROM 4.0 */
 93 #define AR5K_EEPROM_MISC0               AR5K_EEPROM_INFO(4)
 94 #define AR5K_EEPROM_EARSTART(_v)        ((_v) & 0xfff)
 95 #define AR5K_EEPROM_HDR_XR2_DIS(_v)     (((_v) >> 12) & 0x1)
 96 #define AR5K_EEPROM_HDR_XR5_DIS(_v)     (((_v) >> 13) & 0x1)
 97 #define AR5K_EEPROM_EEMAP(_v)           (((_v) >> 14) & 0x3)
 98 
 99 #define AR5K_EEPROM_MISC1                       AR5K_EEPROM_INFO(5)
100 #define AR5K_EEPROM_TARGET_PWRSTART(_v)         ((_v) & 0xfff)
101 #define AR5K_EEPROM_HAS32KHZCRYSTAL(_v)         (((_v) >> 14) & 0x1)    /* has 32KHz crystal for sleep mode */
102 #define AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(_v)     (((_v) >> 15) & 0x1)
103 
104 #define AR5K_EEPROM_MISC2                       AR5K_EEPROM_INFO(6)
105 #define AR5K_EEPROM_EEP_FILE_VERSION(_v)        (((_v) >> 8) & 0xff)
106 #define AR5K_EEPROM_EAR_FILE_VERSION(_v)        ((_v) & 0xff)
107 
108 #define AR5K_EEPROM_MISC3               AR5K_EEPROM_INFO(7)
109 #define AR5K_EEPROM_ART_BUILD_NUM(_v)   (((_v) >> 10) & 0x3f)
110 #define AR5K_EEPROM_EAR_FILE_ID(_v)     ((_v) & 0xff)
111 
112 #define AR5K_EEPROM_MISC4               AR5K_EEPROM_INFO(8)
113 #define AR5K_EEPROM_CAL_DATA_START(_v)  (((_v) >> 4) & 0xfff)
114 #define AR5K_EEPROM_MASK_R0(_v)         (((_v) >> 2) & 0x3)     /* modes supported by radio 0 (bit 1: G, bit 2: A) */
115 #define AR5K_EEPROM_MASK_R1(_v)         ((_v) & 0x3)            /* modes supported by radio 1 (bit 1: G, bit 2: A) */
116 
117 #define AR5K_EEPROM_MISC5               AR5K_EEPROM_INFO(9)
118 #define AR5K_EEPROM_COMP_DIS(_v)        ((_v) & 0x1)            /* disable compression */
119 #define AR5K_EEPROM_AES_DIS(_v)         (((_v) >> 1) & 0x1)     /* disable AES */
120 #define AR5K_EEPROM_FF_DIS(_v)          (((_v) >> 2) & 0x1)     /* disable fast frames */
121 #define AR5K_EEPROM_BURST_DIS(_v)       (((_v) >> 3) & 0x1)     /* disable bursting */
122 #define AR5K_EEPROM_MAX_QCU(_v)         (((_v) >> 4) & 0xf)     /* max number of QCUs. defaults to 10 */
123 #define AR5K_EEPROM_HEAVY_CLIP_EN(_v)   (((_v) >> 8) & 0x1)     /* enable heayy clipping */
124 #define AR5K_EEPROM_KEY_CACHE_SIZE(_v)  (((_v) >> 12) & 0xf)    /* key cache size. defaults to 128 */
125 
126 #define AR5K_EEPROM_MISC6               AR5K_EEPROM_INFO(10)
127 #define AR5K_EEPROM_TX_CHAIN_DIS        ((_v) & 0x7)            /* MIMO chains disabled for TX bitmask */
128 #define AR5K_EEPROM_RX_CHAIN_DIS        (((_v) >> 3) & 0x7)     /* MIMO chains disabled for RX bitmask */
129 #define AR5K_EEPROM_FCC_MID_EN          (((_v) >> 6) & 0x1)     /* 5.47-5.7GHz supported */
130 #define AR5K_EEPROM_JAP_U1EVEN_EN       (((_v) >> 7) & 0x1)     /* Japan UNII1 band (5.15-5.25GHz) on even channels (5180, 5200, 5220, 5240) supported */
131 #define AR5K_EEPROM_JAP_U2_EN           (((_v) >> 8) & 0x1)     /* Japan UNII2 band (5.25-5.35GHz) supported */
132 #define AR5K_EEPROM_JAP_MID_EN          (((_v) >> 9) & 0x1)     /* Japan band from 5.47-5.7GHz supported */
133 #define AR5K_EEPROM_JAP_U1ODD_EN        (((_v) >> 10) & 0x1)    /* Japan UNII2 band (5.15-5.25GHz) on odd channels (5170, 5190, 5210, 5230) supported */
134 #define AR5K_EEPROM_JAP_11A_NEW_EN      (((_v) >> 11) & 0x1)    /* Japan A mode enabled (using even channels) */
135 
136 /* calibration settings */
137 #define AR5K_EEPROM_MODES_11A(_v)       AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4)
138 #define AR5K_EEPROM_MODES_11B(_v)       AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2)
139 #define AR5K_EEPROM_MODES_11G(_v)       AR5K_EEPROM_OFF(_v, 0x00da, 0x010d)
140 #define AR5K_EEPROM_CTL(_v)             AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128)     /* Conformance test limits */
141 #define AR5K_EEPROM_GROUPS_START(_v)    AR5K_EEPROM_OFF(_v, 0x0100, 0x0150)     /* Start of Groups */
142 #define AR5K_EEPROM_GROUP1_OFFSET       0x0
143 #define AR5K_EEPROM_GROUP2_OFFSET       0x5
144 #define AR5K_EEPROM_GROUP3_OFFSET       0x37
145 #define AR5K_EEPROM_GROUP4_OFFSET       0x46
146 #define AR5K_EEPROM_GROUP5_OFFSET       0x55
147 #define AR5K_EEPROM_GROUP6_OFFSET       0x65
148 #define AR5K_EEPROM_GROUP7_OFFSET       0x69
149 #define AR5K_EEPROM_GROUP8_OFFSET       0x6f
150 
151 #define AR5K_EEPROM_TARGET_PWR_OFF_11A(_v)      AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
152                                                                 AR5K_EEPROM_GROUP5_OFFSET, 0x0000)
153 #define AR5K_EEPROM_TARGET_PWR_OFF_11B(_v)      AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
154                                                                 AR5K_EEPROM_GROUP6_OFFSET, 0x0010)
155 #define AR5K_EEPROM_TARGET_PWR_OFF_11G(_v)      AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
156                                                                 AR5K_EEPROM_GROUP7_OFFSET, 0x0014)
157 
158 /* [3.1 - 3.3] */
159 #define AR5K_EEPROM_OBDB0_2GHZ          0x00ec
160 #define AR5K_EEPROM_OBDB1_2GHZ          0x00ed
161 
162 #define AR5K_EEPROM_PROTECT             0x003f  /* EEPROM protect status */
163 #define AR5K_EEPROM_PROTECT_RD_0_31     0x0001  /* Read protection bit for offsets 0x0 - 0x1f */
164 #define AR5K_EEPROM_PROTECT_WR_0_31     0x0002  /* Write protection bit for offsets 0x0 - 0x1f */
165 #define AR5K_EEPROM_PROTECT_RD_32_63    0x0004  /* 0x20 - 0x3f */
166 #define AR5K_EEPROM_PROTECT_WR_32_63    0x0008
167 #define AR5K_EEPROM_PROTECT_RD_64_127   0x0010  /* 0x40 - 0x7f */
168 #define AR5K_EEPROM_PROTECT_WR_64_127   0x0020
169 #define AR5K_EEPROM_PROTECT_RD_128_191  0x0040  /* 0x80 - 0xbf (regdom) */
170 #define AR5K_EEPROM_PROTECT_WR_128_191  0x0080
171 #define AR5K_EEPROM_PROTECT_RD_192_207  0x0100  /* 0xc0 - 0xcf */
172 #define AR5K_EEPROM_PROTECT_WR_192_207  0x0200
173 #define AR5K_EEPROM_PROTECT_RD_208_223  0x0400  /* 0xd0 - 0xdf */
174 #define AR5K_EEPROM_PROTECT_WR_208_223  0x0800
175 #define AR5K_EEPROM_PROTECT_RD_224_239  0x1000  /* 0xe0 - 0xef */
176 #define AR5K_EEPROM_PROTECT_WR_224_239  0x2000
177 #define AR5K_EEPROM_PROTECT_RD_240_255  0x4000  /* 0xf0 - 0xff */
178 #define AR5K_EEPROM_PROTECT_WR_240_255  0x8000
179 
180 /* Some EEPROM defines */
181 #define AR5K_EEPROM_EEP_SCALE           100
182 #define AR5K_EEPROM_EEP_DELTA           10
183 #define AR5K_EEPROM_N_MODES             3
184 #define AR5K_EEPROM_N_5GHZ_CHAN         10
185 #define AR5K_EEPROM_N_2GHZ_CHAN         3
186 #define AR5K_EEPROM_N_2GHZ_CHAN_2413    4
187 #define AR5K_EEPROM_N_2GHZ_CHAN_MAX     4
188 #define AR5K_EEPROM_MAX_CHAN            10
189 #define AR5K_EEPROM_N_PWR_POINTS_5111   11
190 #define AR5K_EEPROM_N_PCDAC             11
191 #define AR5K_EEPROM_N_PHASE_CAL         5
192 #define AR5K_EEPROM_N_TEST_FREQ         8
193 #define AR5K_EEPROM_N_EDGES             8
194 #define AR5K_EEPROM_N_INTERCEPTS        11
195 #define AR5K_EEPROM_FREQ_M(_v)          AR5K_EEPROM_OFF(_v, 0x7f, 0xff)
196 #define AR5K_EEPROM_PCDAC_M             0x3f
197 #define AR5K_EEPROM_PCDAC_START         1
198 #define AR5K_EEPROM_PCDAC_STOP          63
199 #define AR5K_EEPROM_PCDAC_STEP          1
200 #define AR5K_EEPROM_NON_EDGE_M          0x40
201 #define AR5K_EEPROM_CHANNEL_POWER       8
202 #define AR5K_EEPROM_N_OBDB              4
203 #define AR5K_EEPROM_OBDB_DIS            0xffff
204 #define AR5K_EEPROM_CHANNEL_DIS         0xff
205 #define AR5K_EEPROM_SCALE_OC_DELTA(_x)  (((_x) * 2) / 10)
206 #define AR5K_EEPROM_N_CTLS(_v)          AR5K_EEPROM_OFF(_v, 16, 32)
207 #define AR5K_EEPROM_MAX_CTLS            32
208 #define AR5K_EEPROM_N_PD_CURVES         4
209 #define AR5K_EEPROM_N_XPD0_POINTS       4
210 #define AR5K_EEPROM_N_XPD3_POINTS       3
211 #define AR5K_EEPROM_N_PD_GAINS          4
212 #define AR5K_EEPROM_N_PD_POINTS         5
213 #define AR5K_EEPROM_N_INTERCEPT_10_2GHZ 35
214 #define AR5K_EEPROM_N_INTERCEPT_10_5GHZ 55
215 #define AR5K_EEPROM_POWER_M             0x3f
216 #define AR5K_EEPROM_POWER_MIN           0
217 #define AR5K_EEPROM_POWER_MAX           3150
218 #define AR5K_EEPROM_POWER_STEP          50
219 #define AR5K_EEPROM_POWER_TABLE_SIZE    64
220 #define AR5K_EEPROM_N_POWER_LOC_11B     4
221 #define AR5K_EEPROM_N_POWER_LOC_11G     6
222 #define AR5K_EEPROM_I_GAIN              10
223 #define AR5K_EEPROM_CCK_OFDM_DELTA      15
224 #define AR5K_EEPROM_N_IQ_CAL            2
225 /* 5GHz/2GHz */
226 enum ath5k_eeprom_freq_bands{
227         AR5K_EEPROM_BAND_5GHZ = 0,
228         AR5K_EEPROM_BAND_2GHZ = 1,
229         AR5K_EEPROM_N_FREQ_BANDS,
230 };
231 /* Spur chans per freq band */
232 #define AR5K_EEPROM_N_SPUR_CHANS        5
233 /* fbin value for chan 2464 x2 */
234 #define AR5K_EEPROM_5413_SPUR_CHAN_1    1640
235 /* fbin value for chan 2420 x2 */
236 #define AR5K_EEPROM_5413_SPUR_CHAN_2    1200
237 #define AR5K_EEPROM_SPUR_CHAN_MASK      0x3FFF
238 #define AR5K_EEPROM_NO_SPUR             0x8000
239 #define AR5K_SPUR_CHAN_WIDTH                    87
240 #define AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz       3125
241 #define AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz      6250
242 
243 #define AR5K_EEPROM_READ(_o, _v) do {                   \
244         ret = ath5k_hw_eeprom_read(ah, (_o), &(_v));    \
245         if (ret)                                        \
246                 return ret;                             \
247 } while (0)
248 
249 #define AR5K_EEPROM_READ_HDR(_o, _v)                                    \
250         AR5K_EEPROM_READ(_o, ah->ah_capabilities.cap_eeprom._v);        \
251 
252 enum ath5k_ant_table {
253         AR5K_ANT_CTL            = 0,    /* Idle switch table settings */
254         AR5K_ANT_SWTABLE_A      = 1,    /* Switch table for antenna A */
255         AR5K_ANT_SWTABLE_B      = 2,    /* Switch table for antenna B */
256         AR5K_ANT_MAX,
257 };
258 
259 enum ath5k_ctl_mode {
260         AR5K_CTL_11A = 0,
261         AR5K_CTL_11B = 1,
262         AR5K_CTL_11G = 2,
263         AR5K_CTL_TURBO = 3,
264         AR5K_CTL_TURBOG = 4,
265         AR5K_CTL_2GHT20 = 5,
266         AR5K_CTL_5GHT20 = 6,
267         AR5K_CTL_2GHT40 = 7,
268         AR5K_CTL_5GHT40 = 8,
269         AR5K_CTL_MODE_M = 15,
270 };
271 
272 /* Default CTL ids for the 3 main reg domains.
273  * Atheros only uses these by default but vendors
274  * can have up to 32 different CTLs for different
275  * scenarios. Note that theese values are ORed with
276  * the mode id (above) so we can have up to 24 CTL
277  * datasets out of these 3 main regdomains. That leaves
278  * 8 ids that can be used by vendors and since 0x20 is
279  * missing from HAL sources i guess this is the set of
280  * custom CTLs vendors can use. */
281 #define AR5K_CTL_FCC    0x10
282 #define AR5K_CTL_CUSTOM 0x20
283 #define AR5K_CTL_ETSI   0x30
284 #define AR5K_CTL_MKK    0x40
285 
286 /* Indicates a CTL with only mode set and
287  * no reg domain mapping, such CTLs are used
288  * for world roaming domains or simply when
289  * a reg domain is not set */
290 #define AR5K_CTL_NO_REGDOMAIN   0xf0
291 
292 /* Indicates an empty (invalid) CTL */
293 #define AR5K_CTL_NO_CTL         0xff
294 
295 /* Per channel calibration data, used for power table setup */
296 struct ath5k_chan_pcal_info_rf5111 {
297         /* Power levels in half dbm units
298          * for one power curve. */
299         u8 pwr[AR5K_EEPROM_N_PWR_POINTS_5111];
300         /* PCDAC table steps
301          * for the above values */
302         u8 pcdac[AR5K_EEPROM_N_PWR_POINTS_5111];
303         /* Starting PCDAC step */
304         u8 pcdac_min;
305         /* Final PCDAC step */
306         u8 pcdac_max;
307 };
308 
309 struct ath5k_chan_pcal_info_rf5112 {
310         /* Power levels in quarter dBm units
311          * for lower (0) and higher (3)
312          * level curves in 0.25dB units */
313         s8 pwr_x0[AR5K_EEPROM_N_XPD0_POINTS];
314         s8 pwr_x3[AR5K_EEPROM_N_XPD3_POINTS];
315         /* PCDAC table steps
316          * for the above values */
317         u8 pcdac_x0[AR5K_EEPROM_N_XPD0_POINTS];
318         u8 pcdac_x3[AR5K_EEPROM_N_XPD3_POINTS];
319 };
320 
321 struct ath5k_chan_pcal_info_rf2413 {
322         /* Starting pwr/pddac values */
323         s8 pwr_i[AR5K_EEPROM_N_PD_GAINS];
324         u8 pddac_i[AR5K_EEPROM_N_PD_GAINS];
325         /* (pwr,pddac) points
326          * power levels in 0.5dB units */
327         s8 pwr[AR5K_EEPROM_N_PD_GAINS]
328                 [AR5K_EEPROM_N_PD_POINTS];
329         u8 pddac[AR5K_EEPROM_N_PD_GAINS]
330                 [AR5K_EEPROM_N_PD_POINTS];
331 };
332 
333 enum ath5k_powertable_type {
334         AR5K_PWRTABLE_PWR_TO_PCDAC = 0,
335         AR5K_PWRTABLE_LINEAR_PCDAC = 1,
336         AR5K_PWRTABLE_PWR_TO_PDADC = 2,
337 };
338 
339 struct ath5k_pdgain_info {
340         u8 pd_points;
341         u8 *pd_step;
342         /* Power values are in
343          * 0.25dB units */
344         s16 *pd_pwr;
345 };
346 
347 struct ath5k_chan_pcal_info {
348         /* Frequency */
349         u16     freq;
350         /* Tx power boundaries */
351         s16     max_pwr;
352         s16     min_pwr;
353         union {
354                 struct ath5k_chan_pcal_info_rf5111 rf5111_info;
355                 struct ath5k_chan_pcal_info_rf5112 rf5112_info;
356                 struct ath5k_chan_pcal_info_rf2413 rf2413_info;
357         };
358         /* Raw values used by phy code
359          * Curves are stored in order from lower
360          * gain to higher gain (max txpower -> min txpower) */
361         struct ath5k_pdgain_info *pd_curves;
362 };
363 
364 /* Per rate calibration data for each mode,
365  * used for rate power table setup.
366  * Note: Values in 0.5dB units */
367 struct ath5k_rate_pcal_info {
368         u16     freq; /* Frequency */
369         /* Power level for 6-24Mbit/s rates or
370          * 1Mb rate */
371         u16     target_power_6to24;
372         /* Power level for 36Mbit rate or
373          * 2Mb rate */
374         u16     target_power_36;
375         /* Power level for 48Mbit rate or
376          * 5.5Mbit rate */
377         u16     target_power_48;
378         /* Power level for 54Mbit rate or
379          * 11Mbit rate */
380         u16     target_power_54;
381 };
382 
383 /* Power edges for conformance test limits */
384 struct ath5k_edge_power {
385         u16 freq;
386         u16 edge; /* in half dBm */
387         bool flag;
388 };
389 
390 /**
391  * struct ath5k_eeprom_info - EEPROM calibration data
392  *
393  * @ee_regdomain: ath/regd.c takes care of COUNTRY_ERD and WORLDWIDE_ROAMING
394  *      flags
395  * @ee_ant_gain: Antenna gain in 0.5dB steps signed [5211 only?]
396  * @ee_cck_ofdm_gain_delta: difference in gainF to output the same power for
397  *      OFDM and CCK packets
398  * @ee_cck_ofdm_power_delta: power difference between OFDM (6Mbps) and CCK
399  *      (11Mbps) rate in G mode. 0.1dB steps
400  * @ee_scaled_cck_delta: for Japan Channel 14: 0.1dB resolution
401  *
402  * @ee_i_cal: Initial I coefficient to correct I/Q mismatch in the receive path
403  * @ee_q_cal: Initial Q coefficient to correct I/Q mismatch in the receive path
404  * @ee_fixed_bias: use ee_ob and ee_db settings or use automatic control
405  * @ee_switch_settling: RX/TX Switch settling time
406  * @ee_atn_tx_rx: Difference in attenuation between TX and RX in 1dB steps
407  * @ee_ant_control: Antenna Control Settings
408  * @ee_ob: Bias current for Output stage of PA
409  *      B/G mode: Index [0] is used for AR2112/5112, otherwise [1]
410  *      A mode: [0] 5.15-5.25 [1] 5.25-5.50 [2] 5.50-5.70 [3] 5.70-5.85 GHz
411  * @ee_db: Bias current for Output stage of PA. see @ee_ob
412  * @ee_tx_end2xlna_enable: Time difference from when BB finishes sending a frame
413  *      to when the external LNA is activated
414  * @ee_tx_end2xpa_disable: Time difference from when BB finishes sending a frame
415  *      to when the external PA switch is deactivated
416  * @ee_tx_frm2xpa_enable: Time difference from when MAC sends frame to when
417  *      external PA switch is activated
418  * @ee_thr_62: Clear Channel Assessment (CCA) sensitivity
419  *      (IEEE802.11a section 17.3.10.5 )
420  * @ee_xlna_gain: Total gain of the LNA (information only)
421  * @ee_xpd: Use external (1) or internal power detector
422  * @ee_x_gain: Gain for external power detector output (differences in EEMAP
423  *      versions!)
424  * @ee_i_gain: Initial gain value after reset
425  * @ee_margin_tx_rx: Margin in dB when final attenuation stage should be used
426  *
427  * @ee_false_detect: Backoff in Sensitivity (dB) on channels with spur signals
428  * @ee_noise_floor_thr: Noise floor threshold in 1dB steps
429  * @ee_adc_desired_size: Desired amplitude for ADC, used by AGC; in 0.5 dB steps
430  * @ee_pga_desired_size: Desired output of PGA (for BB gain) in 0.5 dB steps
431  * @ee_pd_gain_overlap: PD ADC curves need to overlap in 0.5dB steps (ee_map>=2)
432  */
433 struct ath5k_eeprom_info {
434 
435         /* Header information */
436         u16     ee_magic;
437         u16     ee_protect;
438         u16     ee_regdomain;
439         u16     ee_version;
440         u16     ee_header;
441         u16     ee_ant_gain;
442         u8      ee_rfkill_pin;
443         bool    ee_rfkill_pol;
444         bool    ee_is_hb63;
445         bool    ee_serdes;
446         u16     ee_misc0;
447         u16     ee_misc1;
448         u16     ee_misc2;
449         u16     ee_misc3;
450         u16     ee_misc4;
451         u16     ee_misc5;
452         u16     ee_misc6;
453         u16     ee_cck_ofdm_gain_delta;
454         u16     ee_cck_ofdm_power_delta;
455         u16     ee_scaled_cck_delta;
456 
457         /* RF Calibration settings (reset, rfregs) */
458         u16     ee_i_cal[AR5K_EEPROM_N_MODES];
459         u16     ee_q_cal[AR5K_EEPROM_N_MODES];
460         u16     ee_fixed_bias[AR5K_EEPROM_N_MODES];
461         u16     ee_turbo_max_power[AR5K_EEPROM_N_MODES];
462         u16     ee_xr_power[AR5K_EEPROM_N_MODES];
463         u16     ee_switch_settling[AR5K_EEPROM_N_MODES];
464         u16     ee_atn_tx_rx[AR5K_EEPROM_N_MODES];
465         u16     ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC];
466         u16     ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
467         u16     ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
468         u16     ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES];
469         u16     ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES];
470         u16     ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES];
471         u16     ee_thr_62[AR5K_EEPROM_N_MODES];
472         u16     ee_xlna_gain[AR5K_EEPROM_N_MODES];
473         u16     ee_xpd[AR5K_EEPROM_N_MODES];
474         u16     ee_x_gain[AR5K_EEPROM_N_MODES];
475         u16     ee_i_gain[AR5K_EEPROM_N_MODES];
476         u16     ee_margin_tx_rx[AR5K_EEPROM_N_MODES];
477         u16     ee_switch_settling_turbo[AR5K_EEPROM_N_MODES];
478         u16     ee_margin_tx_rx_turbo[AR5K_EEPROM_N_MODES];
479         u16     ee_atn_tx_rx_turbo[AR5K_EEPROM_N_MODES];
480 
481         /* Power calibration data */
482         u16     ee_false_detect[AR5K_EEPROM_N_MODES];
483 
484         /* Number of pd gain curves per mode */
485         u8      ee_pd_gains[AR5K_EEPROM_N_MODES];
486         /* Back mapping pdcurve number -> pdcurve index in pd->pd_curves */
487         u8      ee_pdc_to_idx[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PD_GAINS];
488 
489         u8      ee_n_piers[AR5K_EEPROM_N_MODES];
490         struct ath5k_chan_pcal_info     ee_pwr_cal_a[AR5K_EEPROM_N_5GHZ_CHAN];
491         struct ath5k_chan_pcal_info     ee_pwr_cal_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
492         struct ath5k_chan_pcal_info     ee_pwr_cal_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
493 
494         /* Per rate target power levels */
495         u8      ee_rate_target_pwr_num[AR5K_EEPROM_N_MODES];
496         struct ath5k_rate_pcal_info     ee_rate_tpwr_a[AR5K_EEPROM_N_5GHZ_CHAN];
497         struct ath5k_rate_pcal_info     ee_rate_tpwr_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
498         struct ath5k_rate_pcal_info     ee_rate_tpwr_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
499 
500         /* Conformance test limits (Unused) */
501         u8      ee_ctls;
502         u8      ee_ctl[AR5K_EEPROM_MAX_CTLS];
503         struct ath5k_edge_power ee_ctl_pwr[AR5K_EEPROM_N_EDGES * AR5K_EEPROM_MAX_CTLS];
504 
505         /* Noise Floor Calibration settings */
506         s16     ee_noise_floor_thr[AR5K_EEPROM_N_MODES];
507         s8      ee_adc_desired_size[AR5K_EEPROM_N_MODES];
508         s8      ee_pga_desired_size[AR5K_EEPROM_N_MODES];
509         s8      ee_adc_desired_size_turbo[AR5K_EEPROM_N_MODES];
510         s8      ee_pga_desired_size_turbo[AR5K_EEPROM_N_MODES];
511         s8      ee_pd_gain_overlap;
512 
513         /* Spur mitigation data (fbin values for spur channels) */
514         u16     ee_spur_chans[AR5K_EEPROM_N_SPUR_CHANS][AR5K_EEPROM_N_FREQ_BANDS];
515 
516         /* Antenna raw switch tables */
517         u32     ee_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
518 };
519 
520 

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