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Linux/drivers/net/wan/ixp4xx_hss.c

  1 /*
  2  * Intel IXP4xx HSS (synchronous serial port) driver for Linux
  3  *
  4  * Copyright (C) 2007-2008 Krzysztof HaƂasa <khc@pm.waw.pl>
  5  *
  6  * This program is free software; you can redistribute it and/or modify it
  7  * under the terms of version 2 of the GNU General Public License
  8  * as published by the Free Software Foundation.
  9  */
 10 
 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 12 
 13 #include <linux/module.h>
 14 #include <linux/bitops.h>
 15 #include <linux/cdev.h>
 16 #include <linux/dma-mapping.h>
 17 #include <linux/dmapool.h>
 18 #include <linux/fs.h>
 19 #include <linux/hdlc.h>
 20 #include <linux/io.h>
 21 #include <linux/kernel.h>
 22 #include <linux/platform_device.h>
 23 #include <linux/poll.h>
 24 #include <linux/slab.h>
 25 #include <mach/npe.h>
 26 #include <mach/qmgr.h>
 27 
 28 #define DEBUG_DESC              0
 29 #define DEBUG_RX                0
 30 #define DEBUG_TX                0
 31 #define DEBUG_PKT_BYTES         0
 32 #define DEBUG_CLOSE             0
 33 
 34 #define DRV_NAME                "ixp4xx_hss"
 35 
 36 #define PKT_EXTRA_FLAGS         0 /* orig 1 */
 37 #define PKT_NUM_PIPES           1 /* 1, 2 or 4 */
 38 #define PKT_PIPE_FIFO_SIZEW     4 /* total 4 dwords per HSS */
 39 
 40 #define RX_DESCS                16 /* also length of all RX queues */
 41 #define TX_DESCS                16 /* also length of all TX queues */
 42 
 43 #define POOL_ALLOC_SIZE         (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
 44 #define RX_SIZE                 (HDLC_MAX_MRU + 4) /* NPE needs more space */
 45 #define MAX_CLOSE_WAIT          1000 /* microseconds */
 46 #define HSS_COUNT               2
 47 #define FRAME_SIZE              256 /* doesn't matter at this point */
 48 #define FRAME_OFFSET            0
 49 #define MAX_CHANNELS            (FRAME_SIZE / 8)
 50 
 51 #define NAPI_WEIGHT             16
 52 
 53 /* Queue IDs */
 54 #define HSS0_CHL_RXTRIG_QUEUE   12      /* orig size = 32 dwords */
 55 #define HSS0_PKT_RX_QUEUE       13      /* orig size = 32 dwords */
 56 #define HSS0_PKT_TX0_QUEUE      14      /* orig size = 16 dwords */
 57 #define HSS0_PKT_TX1_QUEUE      15
 58 #define HSS0_PKT_TX2_QUEUE      16
 59 #define HSS0_PKT_TX3_QUEUE      17
 60 #define HSS0_PKT_RXFREE0_QUEUE  18      /* orig size = 16 dwords */
 61 #define HSS0_PKT_RXFREE1_QUEUE  19
 62 #define HSS0_PKT_RXFREE2_QUEUE  20
 63 #define HSS0_PKT_RXFREE3_QUEUE  21
 64 #define HSS0_PKT_TXDONE_QUEUE   22      /* orig size = 64 dwords */
 65 
 66 #define HSS1_CHL_RXTRIG_QUEUE   10
 67 #define HSS1_PKT_RX_QUEUE       0
 68 #define HSS1_PKT_TX0_QUEUE      5
 69 #define HSS1_PKT_TX1_QUEUE      6
 70 #define HSS1_PKT_TX2_QUEUE      7
 71 #define HSS1_PKT_TX3_QUEUE      8
 72 #define HSS1_PKT_RXFREE0_QUEUE  1
 73 #define HSS1_PKT_RXFREE1_QUEUE  2
 74 #define HSS1_PKT_RXFREE2_QUEUE  3
 75 #define HSS1_PKT_RXFREE3_QUEUE  4
 76 #define HSS1_PKT_TXDONE_QUEUE   9
 77 
 78 #define NPE_PKT_MODE_HDLC               0
 79 #define NPE_PKT_MODE_RAW                1
 80 #define NPE_PKT_MODE_56KMODE            2
 81 #define NPE_PKT_MODE_56KENDIAN_MSB      4
 82 
 83 /* PKT_PIPE_HDLC_CFG_WRITE flags */
 84 #define PKT_HDLC_IDLE_ONES              0x1 /* default = flags */
 85 #define PKT_HDLC_CRC_32                 0x2 /* default = CRC-16 */
 86 #define PKT_HDLC_MSB_ENDIAN             0x4 /* default = LE */
 87 
 88 
 89 /* hss_config, PCRs */
 90 /* Frame sync sampling, default = active low */
 91 #define PCR_FRM_SYNC_ACTIVE_HIGH        0x40000000
 92 #define PCR_FRM_SYNC_FALLINGEDGE        0x80000000
 93 #define PCR_FRM_SYNC_RISINGEDGE         0xC0000000
 94 
 95 /* Frame sync pin: input (default) or output generated off a given clk edge */
 96 #define PCR_FRM_SYNC_OUTPUT_FALLING     0x20000000
 97 #define PCR_FRM_SYNC_OUTPUT_RISING      0x30000000
 98 
 99 /* Frame and data clock sampling on edge, default = falling */
100 #define PCR_FCLK_EDGE_RISING            0x08000000
101 #define PCR_DCLK_EDGE_RISING            0x04000000
102 
103 /* Clock direction, default = input */
104 #define PCR_SYNC_CLK_DIR_OUTPUT         0x02000000
105 
106 /* Generate/Receive frame pulses, default = enabled */
107 #define PCR_FRM_PULSE_DISABLED          0x01000000
108 
109  /* Data rate is full (default) or half the configured clk speed */
110 #define PCR_HALF_CLK_RATE               0x00200000
111 
112 /* Invert data between NPE and HSS FIFOs? (default = no) */
113 #define PCR_DATA_POLARITY_INVERT        0x00100000
114 
115 /* TX/RX endianness, default = LSB */
116 #define PCR_MSB_ENDIAN                  0x00080000
117 
118 /* Normal (default) / open drain mode (TX only) */
119 #define PCR_TX_PINS_OPEN_DRAIN          0x00040000
120 
121 /* No framing bit transmitted and expected on RX? (default = framing bit) */
122 #define PCR_SOF_NO_FBIT                 0x00020000
123 
124 /* Drive data pins? */
125 #define PCR_TX_DATA_ENABLE              0x00010000
126 
127 /* Voice 56k type: drive the data pins low (default), high, high Z */
128 #define PCR_TX_V56K_HIGH                0x00002000
129 #define PCR_TX_V56K_HIGH_IMP            0x00004000
130 
131 /* Unassigned type: drive the data pins low (default), high, high Z */
132 #define PCR_TX_UNASS_HIGH               0x00000800
133 #define PCR_TX_UNASS_HIGH_IMP           0x00001000
134 
135 /* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
136 #define PCR_TX_FB_HIGH_IMP              0x00000400
137 
138 /* 56k data endiannes - which bit unused: high (default) or low */
139 #define PCR_TX_56KE_BIT_0_UNUSED        0x00000200
140 
141 /* 56k data transmission type: 32/8 bit data (default) or 56K data */
142 #define PCR_TX_56KS_56K_DATA            0x00000100
143 
144 /* hss_config, cCR */
145 /* Number of packetized clients, default = 1 */
146 #define CCR_NPE_HFIFO_2_HDLC            0x04000000
147 #define CCR_NPE_HFIFO_3_OR_4HDLC        0x08000000
148 
149 /* default = no loopback */
150 #define CCR_LOOPBACK                    0x02000000
151 
152 /* HSS number, default = 0 (first) */
153 #define CCR_SECOND_HSS                  0x01000000
154 
155 
156 /* hss_config, clkCR: main:10, num:10, denom:12 */
157 #define CLK42X_SPEED_EXP        ((0x3FF << 22) | (  2 << 12) |   15) /*65 KHz*/
158 
159 #define CLK42X_SPEED_512KHZ     ((  130 << 22) | (  2 << 12) |   15)
160 #define CLK42X_SPEED_1536KHZ    ((   43 << 22) | ( 18 << 12) |   47)
161 #define CLK42X_SPEED_1544KHZ    ((   43 << 22) | ( 33 << 12) |  192)
162 #define CLK42X_SPEED_2048KHZ    ((   32 << 22) | ( 34 << 12) |   63)
163 #define CLK42X_SPEED_4096KHZ    ((   16 << 22) | ( 34 << 12) |  127)
164 #define CLK42X_SPEED_8192KHZ    ((    8 << 22) | ( 34 << 12) |  255)
165 
166 #define CLK46X_SPEED_512KHZ     ((  130 << 22) | ( 24 << 12) |  127)
167 #define CLK46X_SPEED_1536KHZ    ((   43 << 22) | (152 << 12) |  383)
168 #define CLK46X_SPEED_1544KHZ    ((   43 << 22) | ( 66 << 12) |  385)
169 #define CLK46X_SPEED_2048KHZ    ((   32 << 22) | (280 << 12) |  511)
170 #define CLK46X_SPEED_4096KHZ    ((   16 << 22) | (280 << 12) | 1023)
171 #define CLK46X_SPEED_8192KHZ    ((    8 << 22) | (280 << 12) | 2047)
172 
173 /*
174  * HSS_CONFIG_CLOCK_CR register consists of 3 parts:
175  *     A (10 bits), B (10 bits) and C (12 bits).
176  * IXP42x HSS clock generator operation (verified with an oscilloscope):
177  * Each clock bit takes 7.5 ns (1 / 133.xx MHz).
178  * The clock sequence consists of (C - B) states of 0s and 1s, each state is
179  * A bits wide. It's followed by (B + 1) states of 0s and 1s, each state is
180  * (A + 1) bits wide.
181  *
182  * The resulting average clock frequency (assuming 33.333 MHz oscillator) is:
183  * freq = 66.666 MHz / (A + (B + 1) / (C + 1))
184  * minimum freq = 66.666 MHz / (A + 1)
185  * maximum freq = 66.666 MHz / A
186  *
187  * Example: A = 2, B = 2, C = 7, CLOCK_CR register = 2 << 22 | 2 << 12 | 7
188  * freq = 66.666 MHz / (2 + (2 + 1) / (7 + 1)) = 28.07 MHz (Mb/s).
189  * The clock sequence is: 1100110011 (5 doubles) 000111000 (3 triples).
190  * The sequence takes (C - B) * A + (B + 1) * (A + 1) = 5 * 2 + 3 * 3 bits
191  * = 19 bits (each 7.5 ns long) = 142.5 ns (then the sequence repeats).
192  * The sequence consists of 4 complete clock periods, thus the average
193  * frequency (= clock rate) is 4 / 142.5 ns = 28.07 MHz (Mb/s).
194  * (max specified clock rate for IXP42x HSS is 8.192 Mb/s).
195  */
196 
197 /* hss_config, LUT entries */
198 #define TDMMAP_UNASSIGNED       0
199 #define TDMMAP_HDLC             1       /* HDLC - packetized */
200 #define TDMMAP_VOICE56K         2       /* Voice56K - 7-bit channelized */
201 #define TDMMAP_VOICE64K         3       /* Voice64K - 8-bit channelized */
202 
203 /* offsets into HSS config */
204 #define HSS_CONFIG_TX_PCR       0x00 /* port configuration registers */
205 #define HSS_CONFIG_RX_PCR       0x04
206 #define HSS_CONFIG_CORE_CR      0x08 /* loopback control, HSS# */
207 #define HSS_CONFIG_CLOCK_CR     0x0C /* clock generator control */
208 #define HSS_CONFIG_TX_FCR       0x10 /* frame configuration registers */
209 #define HSS_CONFIG_RX_FCR       0x14
210 #define HSS_CONFIG_TX_LUT       0x18 /* channel look-up tables */
211 #define HSS_CONFIG_RX_LUT       0x38
212 
213 
214 /* NPE command codes */
215 /* writes the ConfigWord value to the location specified by offset */
216 #define PORT_CONFIG_WRITE               0x40
217 
218 /* triggers the NPE to load the contents of the configuration table */
219 #define PORT_CONFIG_LOAD                0x41
220 
221 /* triggers the NPE to return an HssErrorReadResponse message */
222 #define PORT_ERROR_READ                 0x42
223 
224 /* triggers the NPE to reset internal status and enable the HssPacketized
225    operation for the flow specified by pPipe */
226 #define PKT_PIPE_FLOW_ENABLE            0x50
227 #define PKT_PIPE_FLOW_DISABLE           0x51
228 #define PKT_NUM_PIPES_WRITE             0x52
229 #define PKT_PIPE_FIFO_SIZEW_WRITE       0x53
230 #define PKT_PIPE_HDLC_CFG_WRITE         0x54
231 #define PKT_PIPE_IDLE_PATTERN_WRITE     0x55
232 #define PKT_PIPE_RX_SIZE_WRITE          0x56
233 #define PKT_PIPE_MODE_WRITE             0x57
234 
235 /* HDLC packet status values - desc->status */
236 #define ERR_SHUTDOWN            1 /* stop or shutdown occurrence */
237 #define ERR_HDLC_ALIGN          2 /* HDLC alignment error */
238 #define ERR_HDLC_FCS            3 /* HDLC Frame Check Sum error */
239 #define ERR_RXFREE_Q_EMPTY      4 /* RX-free queue became empty while receiving
240                                      this packet (if buf_len < pkt_len) */
241 #define ERR_HDLC_TOO_LONG       5 /* HDLC frame size too long */
242 #define ERR_HDLC_ABORT          6 /* abort sequence received */
243 #define ERR_DISCONNECTING       7 /* disconnect is in progress */
244 
245 
246 #ifdef __ARMEB__
247 typedef struct sk_buff buffer_t;
248 #define free_buffer dev_kfree_skb
249 #define free_buffer_irq dev_kfree_skb_irq
250 #else
251 typedef void buffer_t;
252 #define free_buffer kfree
253 #define free_buffer_irq kfree
254 #endif
255 
256 struct port {
257         struct device *dev;
258         struct npe *npe;
259         struct net_device *netdev;
260         struct napi_struct napi;
261         struct hss_plat_info *plat;
262         buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
263         struct desc *desc_tab;  /* coherent */
264         u32 desc_tab_phys;
265         unsigned int id;
266         unsigned int clock_type, clock_rate, loopback;
267         unsigned int initialized, carrier;
268         u8 hdlc_cfg;
269         u32 clock_reg;
270 };
271 
272 /* NPE message structure */
273 struct msg {
274 #ifdef __ARMEB__
275         u8 cmd, unused, hss_port, index;
276         union {
277                 struct { u8 data8a, data8b, data8c, data8d; };
278                 struct { u16 data16a, data16b; };
279                 struct { u32 data32; };
280         };
281 #else
282         u8 index, hss_port, unused, cmd;
283         union {
284                 struct { u8 data8d, data8c, data8b, data8a; };
285                 struct { u16 data16b, data16a; };
286                 struct { u32 data32; };
287         };
288 #endif
289 };
290 
291 /* HDLC packet descriptor */
292 struct desc {
293         u32 next;               /* pointer to next buffer, unused */
294 
295 #ifdef __ARMEB__
296         u16 buf_len;            /* buffer length */
297         u16 pkt_len;            /* packet length */
298         u32 data;               /* pointer to data buffer in RAM */
299         u8 status;
300         u8 error_count;
301         u16 __reserved;
302 #else
303         u16 pkt_len;            /* packet length */
304         u16 buf_len;            /* buffer length */
305         u32 data;               /* pointer to data buffer in RAM */
306         u16 __reserved;
307         u8 error_count;
308         u8 status;
309 #endif
310         u32 __reserved1[4];
311 };
312 
313 
314 #define rx_desc_phys(port, n)   ((port)->desc_tab_phys +                \
315                                  (n) * sizeof(struct desc))
316 #define rx_desc_ptr(port, n)    (&(port)->desc_tab[n])
317 
318 #define tx_desc_phys(port, n)   ((port)->desc_tab_phys +                \
319                                  ((n) + RX_DESCS) * sizeof(struct desc))
320 #define tx_desc_ptr(port, n)    (&(port)->desc_tab[(n) + RX_DESCS])
321 
322 /*****************************************************************************
323  * global variables
324  ****************************************************************************/
325 
326 static int ports_open;
327 static struct dma_pool *dma_pool;
328 static spinlock_t npe_lock;
329 
330 static const struct {
331         int tx, txdone, rx, rxfree;
332 }queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE,
333                   HSS0_PKT_RXFREE0_QUEUE},
334                  {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE,
335                   HSS1_PKT_RXFREE0_QUEUE},
336 };
337 
338 /*****************************************************************************
339  * utility functions
340  ****************************************************************************/
341 
342 static inline struct port* dev_to_port(struct net_device *dev)
343 {
344         return dev_to_hdlc(dev)->priv;
345 }
346 
347 #ifndef __ARMEB__
348 static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
349 {
350         int i;
351         for (i = 0; i < cnt; i++)
352                 dest[i] = swab32(src[i]);
353 }
354 #endif
355 
356 /*****************************************************************************
357  * HSS access
358  ****************************************************************************/
359 
360 static void hss_npe_send(struct port *port, struct msg *msg, const char* what)
361 {
362         u32 *val = (u32*)msg;
363         if (npe_send_message(port->npe, msg, what)) {
364                 pr_crit("HSS-%i: unable to send command [%08X:%08X] to %s\n",
365                         port->id, val[0], val[1], npe_name(port->npe));
366                 BUG();
367         }
368 }
369 
370 static void hss_config_set_lut(struct port *port)
371 {
372         struct msg msg;
373         int ch;
374 
375         memset(&msg, 0, sizeof(msg));
376         msg.cmd = PORT_CONFIG_WRITE;
377         msg.hss_port = port->id;
378 
379         for (ch = 0; ch < MAX_CHANNELS; ch++) {
380                 msg.data32 >>= 2;
381                 msg.data32 |= TDMMAP_HDLC << 30;
382 
383                 if (ch % 16 == 15) {
384                         msg.index = HSS_CONFIG_TX_LUT + ((ch / 4) & ~3);
385                         hss_npe_send(port, &msg, "HSS_SET_TX_LUT");
386 
387                         msg.index += HSS_CONFIG_RX_LUT - HSS_CONFIG_TX_LUT;
388                         hss_npe_send(port, &msg, "HSS_SET_RX_LUT");
389                 }
390         }
391 }
392 
393 static void hss_config(struct port *port)
394 {
395         struct msg msg;
396 
397         memset(&msg, 0, sizeof(msg));
398         msg.cmd = PORT_CONFIG_WRITE;
399         msg.hss_port = port->id;
400         msg.index = HSS_CONFIG_TX_PCR;
401         msg.data32 = PCR_FRM_PULSE_DISABLED | PCR_MSB_ENDIAN |
402                 PCR_TX_DATA_ENABLE | PCR_SOF_NO_FBIT;
403         if (port->clock_type == CLOCK_INT)
404                 msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
405         hss_npe_send(port, &msg, "HSS_SET_TX_PCR");
406 
407         msg.index = HSS_CONFIG_RX_PCR;
408         msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
409         hss_npe_send(port, &msg, "HSS_SET_RX_PCR");
410 
411         memset(&msg, 0, sizeof(msg));
412         msg.cmd = PORT_CONFIG_WRITE;
413         msg.hss_port = port->id;
414         msg.index = HSS_CONFIG_CORE_CR;
415         msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |
416                 (port->id ? CCR_SECOND_HSS : 0);
417         hss_npe_send(port, &msg, "HSS_SET_CORE_CR");
418 
419         memset(&msg, 0, sizeof(msg));
420         msg.cmd = PORT_CONFIG_WRITE;
421         msg.hss_port = port->id;
422         msg.index = HSS_CONFIG_CLOCK_CR;
423         msg.data32 = port->clock_reg;
424         hss_npe_send(port, &msg, "HSS_SET_CLOCK_CR");
425 
426         memset(&msg, 0, sizeof(msg));
427         msg.cmd = PORT_CONFIG_WRITE;
428         msg.hss_port = port->id;
429         msg.index = HSS_CONFIG_TX_FCR;
430         msg.data16a = FRAME_OFFSET;
431         msg.data16b = FRAME_SIZE - 1;
432         hss_npe_send(port, &msg, "HSS_SET_TX_FCR");
433 
434         memset(&msg, 0, sizeof(msg));
435         msg.cmd = PORT_CONFIG_WRITE;
436         msg.hss_port = port->id;
437         msg.index = HSS_CONFIG_RX_FCR;
438         msg.data16a = FRAME_OFFSET;
439         msg.data16b = FRAME_SIZE - 1;
440         hss_npe_send(port, &msg, "HSS_SET_RX_FCR");
441 
442         hss_config_set_lut(port);
443 
444         memset(&msg, 0, sizeof(msg));
445         msg.cmd = PORT_CONFIG_LOAD;
446         msg.hss_port = port->id;
447         hss_npe_send(port, &msg, "HSS_LOAD_CONFIG");
448 
449         if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG") ||
450             /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
451             msg.cmd != PORT_CONFIG_LOAD || msg.data32) {
452                 pr_crit("HSS-%i: HSS_LOAD_CONFIG failed\n", port->id);
453                 BUG();
454         }
455 
456         /* HDLC may stop working without this - check FIXME */
457         npe_recv_message(port->npe, &msg, "FLUSH_IT");
458 }
459 
460 static void hss_set_hdlc_cfg(struct port *port)
461 {
462         struct msg msg;
463 
464         memset(&msg, 0, sizeof(msg));
465         msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
466         msg.hss_port = port->id;
467         msg.data8a = port->hdlc_cfg; /* rx_cfg */
468         msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
469         hss_npe_send(port, &msg, "HSS_SET_HDLC_CFG");
470 }
471 
472 static u32 hss_get_status(struct port *port)
473 {
474         struct msg msg;
475 
476         memset(&msg, 0, sizeof(msg));
477         msg.cmd = PORT_ERROR_READ;
478         msg.hss_port = port->id;
479         hss_npe_send(port, &msg, "PORT_ERROR_READ");
480         if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ")) {
481                 pr_crit("HSS-%i: unable to read HSS status\n", port->id);
482                 BUG();
483         }
484 
485         return msg.data32;
486 }
487 
488 static void hss_start_hdlc(struct port *port)
489 {
490         struct msg msg;
491 
492         memset(&msg, 0, sizeof(msg));
493         msg.cmd = PKT_PIPE_FLOW_ENABLE;
494         msg.hss_port = port->id;
495         msg.data32 = 0;
496         hss_npe_send(port, &msg, "HSS_ENABLE_PKT_PIPE");
497 }
498 
499 static void hss_stop_hdlc(struct port *port)
500 {
501         struct msg msg;
502 
503         memset(&msg, 0, sizeof(msg));
504         msg.cmd = PKT_PIPE_FLOW_DISABLE;
505         msg.hss_port = port->id;
506         hss_npe_send(port, &msg, "HSS_DISABLE_PKT_PIPE");
507         hss_get_status(port); /* make sure it's halted */
508 }
509 
510 static int hss_load_firmware(struct port *port)
511 {
512         struct msg msg;
513         int err;
514 
515         if (port->initialized)
516                 return 0;
517 
518         if (!npe_running(port->npe) &&
519             (err = npe_load_firmware(port->npe, npe_name(port->npe),
520                                      port->dev)))
521                 return err;
522 
523         /* HDLC mode configuration */
524         memset(&msg, 0, sizeof(msg));
525         msg.cmd = PKT_NUM_PIPES_WRITE;
526         msg.hss_port = port->id;
527         msg.data8a = PKT_NUM_PIPES;
528         hss_npe_send(port, &msg, "HSS_SET_PKT_PIPES");
529 
530         msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
531         msg.data8a = PKT_PIPE_FIFO_SIZEW;
532         hss_npe_send(port, &msg, "HSS_SET_PKT_FIFO");
533 
534         msg.cmd = PKT_PIPE_MODE_WRITE;
535         msg.data8a = NPE_PKT_MODE_HDLC;
536         /* msg.data8b = inv_mask */
537         /* msg.data8c = or_mask */
538         hss_npe_send(port, &msg, "HSS_SET_PKT_MODE");
539 
540         msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
541         msg.data16a = HDLC_MAX_MRU; /* including CRC */
542         hss_npe_send(port, &msg, "HSS_SET_PKT_RX_SIZE");
543 
544         msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
545         msg.data32 = 0x7F7F7F7F; /* ??? FIXME */
546         hss_npe_send(port, &msg, "HSS_SET_PKT_IDLE");
547 
548         port->initialized = 1;
549         return 0;
550 }
551 
552 /*****************************************************************************
553  * packetized (HDLC) operation
554  ****************************************************************************/
555 
556 static inline void debug_pkt(struct net_device *dev, const char *func,
557                              u8 *data, int len)
558 {
559 #if DEBUG_PKT_BYTES
560         int i;
561 
562         printk(KERN_DEBUG "%s: %s(%i)", dev->name, func, len);
563         for (i = 0; i < len; i++) {
564                 if (i >= DEBUG_PKT_BYTES)
565                         break;
566                 printk("%s%02X", !(i % 4) ? " " : "", data[i]);
567         }
568         printk("\n");
569 #endif
570 }
571 
572 
573 static inline void debug_desc(u32 phys, struct desc *desc)
574 {
575 #if DEBUG_DESC
576         printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
577                phys, desc->next, desc->buf_len, desc->pkt_len,
578                desc->data, desc->status, desc->error_count);
579 #endif
580 }
581 
582 static inline int queue_get_desc(unsigned int queue, struct port *port,
583                                  int is_tx)
584 {
585         u32 phys, tab_phys, n_desc;
586         struct desc *tab;
587 
588         if (!(phys = qmgr_get_entry(queue)))
589                 return -1;
590 
591         BUG_ON(phys & 0x1F);
592         tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
593         tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
594         n_desc = (phys - tab_phys) / sizeof(struct desc);
595         BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
596         debug_desc(phys, &tab[n_desc]);
597         BUG_ON(tab[n_desc].next);
598         return n_desc;
599 }
600 
601 static inline void queue_put_desc(unsigned int queue, u32 phys,
602                                   struct desc *desc)
603 {
604         debug_desc(phys, desc);
605         BUG_ON(phys & 0x1F);
606         qmgr_put_entry(queue, phys);
607         /* Don't check for queue overflow here, we've allocated sufficient
608            length and queues >= 32 don't support this check anyway. */
609 }
610 
611 
612 static inline void dma_unmap_tx(struct port *port, struct desc *desc)
613 {
614 #ifdef __ARMEB__
615         dma_unmap_single(&port->netdev->dev, desc->data,
616                          desc->buf_len, DMA_TO_DEVICE);
617 #else
618         dma_unmap_single(&port->netdev->dev, desc->data & ~3,
619                          ALIGN((desc->data & 3) + desc->buf_len, 4),
620                          DMA_TO_DEVICE);
621 #endif
622 }
623 
624 
625 static void hss_hdlc_set_carrier(void *pdev, int carrier)
626 {
627         struct net_device *netdev = pdev;
628         struct port *port = dev_to_port(netdev);
629         unsigned long flags;
630 
631         spin_lock_irqsave(&npe_lock, flags);
632         port->carrier = carrier;
633         if (!port->loopback) {
634                 if (carrier)
635                         netif_carrier_on(netdev);
636                 else
637                         netif_carrier_off(netdev);
638         }
639         spin_unlock_irqrestore(&npe_lock, flags);
640 }
641 
642 static void hss_hdlc_rx_irq(void *pdev)
643 {
644         struct net_device *dev = pdev;
645         struct port *port = dev_to_port(dev);
646 
647 #if DEBUG_RX
648         printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
649 #endif
650         qmgr_disable_irq(queue_ids[port->id].rx);
651         napi_schedule(&port->napi);
652 }
653 
654 static int hss_hdlc_poll(struct napi_struct *napi, int budget)
655 {
656         struct port *port = container_of(napi, struct port, napi);
657         struct net_device *dev = port->netdev;
658         unsigned int rxq = queue_ids[port->id].rx;
659         unsigned int rxfreeq = queue_ids[port->id].rxfree;
660         int received = 0;
661 
662 #if DEBUG_RX
663         printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name);
664 #endif
665 
666         while (received < budget) {
667                 struct sk_buff *skb;
668                 struct desc *desc;
669                 int n;
670 #ifdef __ARMEB__
671                 struct sk_buff *temp;
672                 u32 phys;
673 #endif
674 
675                 if ((n = queue_get_desc(rxq, port, 0)) < 0) {
676 #if DEBUG_RX
677                         printk(KERN_DEBUG "%s: hss_hdlc_poll"
678                                " napi_complete\n", dev->name);
679 #endif
680                         napi_complete(napi);
681                         qmgr_enable_irq(rxq);
682                         if (!qmgr_stat_empty(rxq) &&
683                             napi_reschedule(napi)) {
684 #if DEBUG_RX
685                                 printk(KERN_DEBUG "%s: hss_hdlc_poll"
686                                        " napi_reschedule succeeded\n",
687                                        dev->name);
688 #endif
689                                 qmgr_disable_irq(rxq);
690                                 continue;
691                         }
692 #if DEBUG_RX
693                         printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n",
694                                dev->name);
695 #endif
696                         return received; /* all work done */
697                 }
698 
699                 desc = rx_desc_ptr(port, n);
700 #if 0 /* FIXME - error_count counts modulo 256, perhaps we should use it */
701                 if (desc->error_count)
702                         printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X"
703                                " errors %u\n", dev->name, desc->status,
704                                desc->error_count);
705 #endif
706                 skb = NULL;
707                 switch (desc->status) {
708                 case 0:
709 #ifdef __ARMEB__
710                         if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) {
711                                 phys = dma_map_single(&dev->dev, skb->data,
712                                                       RX_SIZE,
713                                                       DMA_FROM_DEVICE);
714                                 if (dma_mapping_error(&dev->dev, phys)) {
715                                         dev_kfree_skb(skb);
716                                         skb = NULL;
717                                 }
718                         }
719 #else
720                         skb = netdev_alloc_skb(dev, desc->pkt_len);
721 #endif
722                         if (!skb)
723                                 dev->stats.rx_dropped++;
724                         break;
725                 case ERR_HDLC_ALIGN:
726                 case ERR_HDLC_ABORT:
727                         dev->stats.rx_frame_errors++;
728                         dev->stats.rx_errors++;
729                         break;
730                 case ERR_HDLC_FCS:
731                         dev->stats.rx_crc_errors++;
732                         dev->stats.rx_errors++;
733                         break;
734                 case ERR_HDLC_TOO_LONG:
735                         dev->stats.rx_length_errors++;
736                         dev->stats.rx_errors++;
737                         break;
738                 default:        /* FIXME - remove printk */
739                         netdev_err(dev, "hss_hdlc_poll: status 0x%02X errors %u\n",
740                                    desc->status, desc->error_count);
741                         dev->stats.rx_errors++;
742                 }
743 
744                 if (!skb) {
745                         /* put the desc back on RX-ready queue */
746                         desc->buf_len = RX_SIZE;
747                         desc->pkt_len = desc->status = 0;
748                         queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
749                         continue;
750                 }
751 
752                 /* process received frame */
753 #ifdef __ARMEB__
754                 temp = skb;
755                 skb = port->rx_buff_tab[n];
756                 dma_unmap_single(&dev->dev, desc->data,
757                                  RX_SIZE, DMA_FROM_DEVICE);
758 #else
759                 dma_sync_single_for_cpu(&dev->dev, desc->data,
760                                         RX_SIZE, DMA_FROM_DEVICE);
761                 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
762                               ALIGN(desc->pkt_len, 4) / 4);
763 #endif
764                 skb_put(skb, desc->pkt_len);
765 
766                 debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len);
767 
768                 skb->protocol = hdlc_type_trans(skb, dev);
769                 dev->stats.rx_packets++;
770                 dev->stats.rx_bytes += skb->len;
771                 netif_receive_skb(skb);
772 
773                 /* put the new buffer on RX-free queue */
774 #ifdef __ARMEB__
775                 port->rx_buff_tab[n] = temp;
776                 desc->data = phys;
777 #endif
778                 desc->buf_len = RX_SIZE;
779                 desc->pkt_len = 0;
780                 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
781                 received++;
782         }
783 #if DEBUG_RX
784         printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
785 #endif
786         return received;        /* not all work done */
787 }
788 
789 
790 static void hss_hdlc_txdone_irq(void *pdev)
791 {
792         struct net_device *dev = pdev;
793         struct port *port = dev_to_port(dev);
794         int n_desc;
795 
796 #if DEBUG_TX
797         printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");
798 #endif
799         while ((n_desc = queue_get_desc(queue_ids[port->id].txdone,
800                                         port, 1)) >= 0) {
801                 struct desc *desc;
802                 int start;
803 
804                 desc = tx_desc_ptr(port, n_desc);
805 
806                 dev->stats.tx_packets++;
807                 dev->stats.tx_bytes += desc->pkt_len;
808 
809                 dma_unmap_tx(port, desc);
810 #if DEBUG_TX
811                 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n",
812                        dev->name, port->tx_buff_tab[n_desc]);
813 #endif
814                 free_buffer_irq(port->tx_buff_tab[n_desc]);
815                 port->tx_buff_tab[n_desc] = NULL;
816 
817                 start = qmgr_stat_below_low_watermark(port->plat->txreadyq);
818                 queue_put_desc(port->plat->txreadyq,
819                                tx_desc_phys(port, n_desc), desc);
820                 if (start) { /* TX-ready queue was empty */
821 #if DEBUG_TX
822                         printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit"
823                                " ready\n", dev->name);
824 #endif
825                         netif_wake_queue(dev);
826                 }
827         }
828 }
829 
830 static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
831 {
832         struct port *port = dev_to_port(dev);
833         unsigned int txreadyq = port->plat->txreadyq;
834         int len, offset, bytes, n;
835         void *mem;
836         u32 phys;
837         struct desc *desc;
838 
839 #if DEBUG_TX
840         printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name);
841 #endif
842 
843         if (unlikely(skb->len > HDLC_MAX_MRU)) {
844                 dev_kfree_skb(skb);
845                 dev->stats.tx_errors++;
846                 return NETDEV_TX_OK;
847         }
848 
849         debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len);
850 
851         len = skb->len;
852 #ifdef __ARMEB__
853         offset = 0; /* no need to keep alignment */
854         bytes = len;
855         mem = skb->data;
856 #else
857         offset = (int)skb->data & 3; /* keep 32-bit alignment */
858         bytes = ALIGN(offset + len, 4);
859         if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
860                 dev_kfree_skb(skb);
861                 dev->stats.tx_dropped++;
862                 return NETDEV_TX_OK;
863         }
864         memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
865         dev_kfree_skb(skb);
866 #endif
867 
868         phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
869         if (dma_mapping_error(&dev->dev, phys)) {
870 #ifdef __ARMEB__
871                 dev_kfree_skb(skb);
872 #else
873                 kfree(mem);
874 #endif
875                 dev->stats.tx_dropped++;
876                 return NETDEV_TX_OK;
877         }
878 
879         n = queue_get_desc(txreadyq, port, 1);
880         BUG_ON(n < 0);
881         desc = tx_desc_ptr(port, n);
882 
883 #ifdef __ARMEB__
884         port->tx_buff_tab[n] = skb;
885 #else
886         port->tx_buff_tab[n] = mem;
887 #endif
888         desc->data = phys + offset;
889         desc->buf_len = desc->pkt_len = len;
890 
891         wmb();
892         queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc);
893 
894         if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */
895 #if DEBUG_TX
896                 printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name);
897 #endif
898                 netif_stop_queue(dev);
899                 /* we could miss TX ready interrupt */
900                 if (!qmgr_stat_below_low_watermark(txreadyq)) {
901 #if DEBUG_TX
902                         printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n",
903                                dev->name);
904 #endif
905                         netif_wake_queue(dev);
906                 }
907         }
908 
909 #if DEBUG_TX
910         printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
911 #endif
912         return NETDEV_TX_OK;
913 }
914 
915 
916 static int request_hdlc_queues(struct port *port)
917 {
918         int err;
919 
920         err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0,
921                                  "%s:RX-free", port->netdev->name);
922         if (err)
923                 return err;
924 
925         err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0,
926                                  "%s:RX", port->netdev->name);
927         if (err)
928                 goto rel_rxfree;
929 
930         err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0,
931                                  "%s:TX", port->netdev->name);
932         if (err)
933                 goto rel_rx;
934 
935         err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,
936                                  "%s:TX-ready", port->netdev->name);
937         if (err)
938                 goto rel_tx;
939 
940         err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0,
941                                  "%s:TX-done", port->netdev->name);
942         if (err)
943                 goto rel_txready;
944         return 0;
945 
946 rel_txready:
947         qmgr_release_queue(port->plat->txreadyq);
948 rel_tx:
949         qmgr_release_queue(queue_ids[port->id].tx);
950 rel_rx:
951         qmgr_release_queue(queue_ids[port->id].rx);
952 rel_rxfree:
953         qmgr_release_queue(queue_ids[port->id].rxfree);
954         printk(KERN_DEBUG "%s: unable to request hardware queues\n",
955                port->netdev->name);
956         return err;
957 }
958 
959 static void release_hdlc_queues(struct port *port)
960 {
961         qmgr_release_queue(queue_ids[port->id].rxfree);
962         qmgr_release_queue(queue_ids[port->id].rx);
963         qmgr_release_queue(queue_ids[port->id].txdone);
964         qmgr_release_queue(queue_ids[port->id].tx);
965         qmgr_release_queue(port->plat->txreadyq);
966 }
967 
968 static int init_hdlc_queues(struct port *port)
969 {
970         int i;
971 
972         if (!ports_open) {
973                 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev,
974                                            POOL_ALLOC_SIZE, 32, 0);
975                 if (!dma_pool)
976                         return -ENOMEM;
977         }
978 
979         if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
980                                               &port->desc_tab_phys)))
981                 return -ENOMEM;
982         memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
983         memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
984         memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
985 
986         /* Setup RX buffers */
987         for (i = 0; i < RX_DESCS; i++) {
988                 struct desc *desc = rx_desc_ptr(port, i);
989                 buffer_t *buff;
990                 void *data;
991 #ifdef __ARMEB__
992                 if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE)))
993                         return -ENOMEM;
994                 data = buff->data;
995 #else
996                 if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL)))
997                         return -ENOMEM;
998                 data = buff;
999 #endif
1000                 desc->buf_len = RX_SIZE;
1001                 desc->data = dma_map_single(&port->netdev->dev, data,
1002                                             RX_SIZE, DMA_FROM_DEVICE);
1003                 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
1004                         free_buffer(buff);
1005                         return -EIO;
1006                 }
1007                 port->rx_buff_tab[i] = buff;
1008         }
1009 
1010         return 0;
1011 }
1012 
1013 static void destroy_hdlc_queues(struct port *port)
1014 {
1015         int i;
1016 
1017         if (port->desc_tab) {
1018                 for (i = 0; i < RX_DESCS; i++) {
1019                         struct desc *desc = rx_desc_ptr(port, i);
1020                         buffer_t *buff = port->rx_buff_tab[i];
1021                         if (buff) {
1022                                 dma_unmap_single(&port->netdev->dev,
1023                                                  desc->data, RX_SIZE,
1024                                                  DMA_FROM_DEVICE);
1025                                 free_buffer(buff);
1026                         }
1027                 }
1028                 for (i = 0; i < TX_DESCS; i++) {
1029                         struct desc *desc = tx_desc_ptr(port, i);
1030                         buffer_t *buff = port->tx_buff_tab[i];
1031                         if (buff) {
1032                                 dma_unmap_tx(port, desc);
1033                                 free_buffer(buff);
1034                         }
1035                 }
1036                 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1037                 port->desc_tab = NULL;
1038         }
1039 
1040         if (!ports_open && dma_pool) {
1041                 dma_pool_destroy(dma_pool);
1042                 dma_pool = NULL;
1043         }
1044 }
1045 
1046 static int hss_hdlc_open(struct net_device *dev)
1047 {
1048         struct port *port = dev_to_port(dev);
1049         unsigned long flags;
1050         int i, err = 0;
1051 
1052         if ((err = hdlc_open(dev)))
1053                 return err;
1054 
1055         if ((err = hss_load_firmware(port)))
1056                 goto err_hdlc_close;
1057 
1058         if ((err = request_hdlc_queues(port)))
1059                 goto err_hdlc_close;
1060 
1061         if ((err = init_hdlc_queues(port)))
1062                 goto err_destroy_queues;
1063 
1064         spin_lock_irqsave(&npe_lock, flags);
1065         if (port->plat->open)
1066                 if ((err = port->plat->open(port->id, dev,
1067                                             hss_hdlc_set_carrier)))
1068                         goto err_unlock;
1069         spin_unlock_irqrestore(&npe_lock, flags);
1070 
1071         /* Populate queues with buffers, no failure after this point */
1072         for (i = 0; i < TX_DESCS; i++)
1073                 queue_put_desc(port->plat->txreadyq,
1074                                tx_desc_phys(port, i), tx_desc_ptr(port, i));
1075 
1076         for (i = 0; i < RX_DESCS; i++)
1077                 queue_put_desc(queue_ids[port->id].rxfree,
1078                                rx_desc_phys(port, i), rx_desc_ptr(port, i));
1079 
1080         napi_enable(&port->napi);
1081         netif_start_queue(dev);
1082 
1083         qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY,
1084                      hss_hdlc_rx_irq, dev);
1085 
1086         qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY,
1087                      hss_hdlc_txdone_irq, dev);
1088         qmgr_enable_irq(queue_ids[port->id].txdone);
1089 
1090         ports_open++;
1091 
1092         hss_set_hdlc_cfg(port);
1093         hss_config(port);
1094 
1095         hss_start_hdlc(port);
1096 
1097         /* we may already have RX data, enables IRQ */
1098         napi_schedule(&port->napi);
1099         return 0;
1100 
1101 err_unlock:
1102         spin_unlock_irqrestore(&npe_lock, flags);
1103 err_destroy_queues:
1104         destroy_hdlc_queues(port);
1105         release_hdlc_queues(port);
1106 err_hdlc_close:
1107         hdlc_close(dev);
1108         return err;
1109 }
1110 
1111 static int hss_hdlc_close(struct net_device *dev)
1112 {
1113         struct port *port = dev_to_port(dev);
1114         unsigned long flags;
1115         int i, buffs = RX_DESCS; /* allocated RX buffers */
1116 
1117         spin_lock_irqsave(&npe_lock, flags);
1118         ports_open--;
1119         qmgr_disable_irq(queue_ids[port->id].rx);
1120         netif_stop_queue(dev);
1121         napi_disable(&port->napi);
1122 
1123         hss_stop_hdlc(port);
1124 
1125         while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0)
1126                 buffs--;
1127         while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0)
1128                 buffs--;
1129 
1130         if (buffs)
1131                 netdev_crit(dev, "unable to drain RX queue, %i buffer(s) left in NPE\n",
1132                             buffs);
1133 
1134         buffs = TX_DESCS;
1135         while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0)
1136                 buffs--; /* cancel TX */
1137 
1138         i = 0;
1139         do {
1140                 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1141                         buffs--;
1142                 if (!buffs)
1143                         break;
1144         } while (++i < MAX_CLOSE_WAIT);
1145 
1146         if (buffs)
1147                 netdev_crit(dev, "unable to drain TX queue, %i buffer(s) left in NPE\n",
1148                             buffs);
1149 #if DEBUG_CLOSE
1150         if (!buffs)
1151                 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1152 #endif
1153         qmgr_disable_irq(queue_ids[port->id].txdone);
1154 
1155         if (port->plat->close)
1156                 port->plat->close(port->id, dev);
1157         spin_unlock_irqrestore(&npe_lock, flags);
1158 
1159         destroy_hdlc_queues(port);
1160         release_hdlc_queues(port);
1161         hdlc_close(dev);
1162         return 0;
1163 }
1164 
1165 
1166 static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
1167                            unsigned short parity)
1168 {
1169         struct port *port = dev_to_port(dev);
1170 
1171         if (encoding != ENCODING_NRZ)
1172                 return -EINVAL;
1173 
1174         switch(parity) {
1175         case PARITY_CRC16_PR1_CCITT:
1176                 port->hdlc_cfg = 0;
1177                 return 0;
1178 
1179         case PARITY_CRC32_PR1_CCITT:
1180                 port->hdlc_cfg = PKT_HDLC_CRC_32;
1181                 return 0;
1182 
1183         default:
1184                 return -EINVAL;
1185         }
1186 }
1187 
1188 static u32 check_clock(u32 rate, u32 a, u32 b, u32 c,
1189                        u32 *best, u32 *best_diff, u32 *reg)
1190 {
1191         /* a is 10-bit, b is 10-bit, c is 12-bit */
1192         u64 new_rate;
1193         u32 new_diff;
1194 
1195         new_rate = ixp4xx_timer_freq * (u64)(c + 1);
1196         do_div(new_rate, a * (c + 1) + b + 1);
1197         new_diff = abs((u32)new_rate - rate);
1198 
1199         if (new_diff < *best_diff) {
1200                 *best = new_rate;
1201                 *best_diff = new_diff;
1202                 *reg = (a << 22) | (b << 12) | c;
1203         }
1204         return new_diff;
1205 }
1206 
1207 static void find_best_clock(u32 rate, u32 *best, u32 *reg)
1208 {
1209         u32 a, b, diff = 0xFFFFFFFF;
1210 
1211         a = ixp4xx_timer_freq / rate;
1212 
1213         if (a > 0x3FF) { /* 10-bit value - we can go as slow as ca. 65 kb/s */
1214                 check_clock(rate, 0x3FF, 1, 1, best, &diff, reg);
1215                 return;
1216         }
1217         if (a == 0) { /* > 66.666 MHz */
1218                 a = 1; /* minimum divider is 1 (a = 0, b = 1, c = 1) */
1219                 rate = ixp4xx_timer_freq;
1220         }
1221 
1222         if (rate * a == ixp4xx_timer_freq) { /* don't divide by 0 later */
1223                 check_clock(rate, a - 1, 1, 1, best, &diff, reg);
1224                 return;
1225         }
1226 
1227         for (b = 0; b < 0x400; b++) {
1228                 u64 c = (b + 1) * (u64)rate;
1229                 do_div(c, ixp4xx_timer_freq - rate * a);
1230                 c--;
1231                 if (c >= 0xFFF) { /* 12-bit - no need to check more 'b's */
1232                         if (b == 0 && /* also try a bit higher rate */
1233                             !check_clock(rate, a - 1, 1, 1, best, &diff, reg))
1234                                 return;
1235                         check_clock(rate, a, b, 0xFFF, best, &diff, reg);
1236                         return;
1237                 }
1238                 if (!check_clock(rate, a, b, c, best, &diff, reg))
1239                         return;
1240                 if (!check_clock(rate, a, b, c + 1, best, &diff, reg))
1241                         return;
1242         }
1243 }
1244 
1245 static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1246 {
1247         const size_t size = sizeof(sync_serial_settings);
1248         sync_serial_settings new_line;
1249         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1250         struct port *port = dev_to_port(dev);
1251         unsigned long flags;
1252         int clk;
1253 
1254         if (cmd != SIOCWANDEV)
1255                 return hdlc_ioctl(dev, ifr, cmd);
1256 
1257         switch(ifr->ifr_settings.type) {
1258         case IF_GET_IFACE:
1259                 ifr->ifr_settings.type = IF_IFACE_V35;
1260                 if (ifr->ifr_settings.size < size) {
1261                         ifr->ifr_settings.size = size; /* data size wanted */
1262                         return -ENOBUFS;
1263                 }
1264                 memset(&new_line, 0, sizeof(new_line));
1265                 new_line.clock_type = port->clock_type;
1266                 new_line.clock_rate = port->clock_rate;
1267                 new_line.loopback = port->loopback;
1268                 if (copy_to_user(line, &new_line, size))
1269                         return -EFAULT;
1270                 return 0;
1271 
1272         case IF_IFACE_SYNC_SERIAL:
1273         case IF_IFACE_V35:
1274                 if(!capable(CAP_NET_ADMIN))
1275                         return -EPERM;
1276                 if (copy_from_user(&new_line, line, size))
1277                         return -EFAULT;
1278 
1279                 clk = new_line.clock_type;
1280                 if (port->plat->set_clock)
1281                         clk = port->plat->set_clock(port->id, clk);
1282 
1283                 if (clk != CLOCK_EXT && clk != CLOCK_INT)
1284                         return -EINVAL; /* No such clock setting */
1285 
1286                 if (new_line.loopback != 0 && new_line.loopback != 1)
1287                         return -EINVAL;
1288 
1289                 port->clock_type = clk; /* Update settings */
1290                 if (clk == CLOCK_INT)
1291                         find_best_clock(new_line.clock_rate, &port->clock_rate,
1292                                         &port->clock_reg);
1293                 else {
1294                         port->clock_rate = 0;
1295                         port->clock_reg = CLK42X_SPEED_2048KHZ;
1296                 }
1297                 port->loopback = new_line.loopback;
1298 
1299                 spin_lock_irqsave(&npe_lock, flags);
1300 
1301                 if (dev->flags & IFF_UP)
1302                         hss_config(port);
1303 
1304                 if (port->loopback || port->carrier)
1305                         netif_carrier_on(port->netdev);
1306                 else
1307                         netif_carrier_off(port->netdev);
1308                 spin_unlock_irqrestore(&npe_lock, flags);
1309 
1310                 return 0;
1311 
1312         default:
1313                 return hdlc_ioctl(dev, ifr, cmd);
1314         }
1315 }
1316 
1317 /*****************************************************************************
1318  * initialization
1319  ****************************************************************************/
1320 
1321 static const struct net_device_ops hss_hdlc_ops = {
1322         .ndo_open       = hss_hdlc_open,
1323         .ndo_stop       = hss_hdlc_close,
1324         .ndo_change_mtu = hdlc_change_mtu,
1325         .ndo_start_xmit = hdlc_start_xmit,
1326         .ndo_do_ioctl   = hss_hdlc_ioctl,
1327 };
1328 
1329 static int hss_init_one(struct platform_device *pdev)
1330 {
1331         struct port *port;
1332         struct net_device *dev;
1333         hdlc_device *hdlc;
1334         int err;
1335 
1336         if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
1337                 return -ENOMEM;
1338 
1339         if ((port->npe = npe_request(0)) == NULL) {
1340                 err = -ENODEV;
1341                 goto err_free;
1342         }
1343 
1344         if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) {
1345                 err = -ENOMEM;
1346                 goto err_plat;
1347         }
1348 
1349         SET_NETDEV_DEV(dev, &pdev->dev);
1350         hdlc = dev_to_hdlc(dev);
1351         hdlc->attach = hss_hdlc_attach;
1352         hdlc->xmit = hss_hdlc_xmit;
1353         dev->netdev_ops = &hss_hdlc_ops;
1354         dev->tx_queue_len = 100;
1355         port->clock_type = CLOCK_EXT;
1356         port->clock_rate = 0;
1357         port->clock_reg = CLK42X_SPEED_2048KHZ;
1358         port->id = pdev->id;
1359         port->dev = &pdev->dev;
1360         port->plat = pdev->dev.platform_data;
1361         netif_napi_add(dev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT);
1362 
1363         if ((err = register_hdlc_device(dev)))
1364                 goto err_free_netdev;
1365 
1366         platform_set_drvdata(pdev, port);
1367 
1368         netdev_info(dev, "initialized\n");
1369         return 0;
1370 
1371 err_free_netdev:
1372         free_netdev(dev);
1373 err_plat:
1374         npe_release(port->npe);
1375 err_free:
1376         kfree(port);
1377         return err;
1378 }
1379 
1380 static int hss_remove_one(struct platform_device *pdev)
1381 {
1382         struct port *port = platform_get_drvdata(pdev);
1383 
1384         unregister_hdlc_device(port->netdev);
1385         free_netdev(port->netdev);
1386         npe_release(port->npe);
1387         kfree(port);
1388         return 0;
1389 }
1390 
1391 static struct platform_driver ixp4xx_hss_driver = {
1392         .driver.name    = DRV_NAME,
1393         .probe          = hss_init_one,
1394         .remove         = hss_remove_one,
1395 };
1396 
1397 static int __init hss_init_module(void)
1398 {
1399         if ((ixp4xx_read_feature_bits() &
1400              (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
1401             (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS))
1402                 return -ENODEV;
1403 
1404         spin_lock_init(&npe_lock);
1405 
1406         return platform_driver_register(&ixp4xx_hss_driver);
1407 }
1408 
1409 static void __exit hss_cleanup_module(void)
1410 {
1411         platform_driver_unregister(&ixp4xx_hss_driver);
1412 }
1413 
1414 MODULE_AUTHOR("Krzysztof Halasa");
1415 MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
1416 MODULE_LICENSE("GPL v2");
1417 MODULE_ALIAS("platform:ixp4xx_hss");
1418 module_init(hss_init_module);
1419 module_exit(hss_cleanup_module);
1420 

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