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Linux/drivers/net/wan/dscc4.c

  1 /*
  2  * drivers/net/wan/dscc4/dscc4.c: a DSCC4 HDLC driver for Linux
  3  *
  4  * This software may be used and distributed according to the terms of the
  5  * GNU General Public License.
  6  *
  7  * The author may be reached as romieu@cogenit.fr.
  8  * Specific bug reports/asian food will be welcome.
  9  *
 10  * Special thanks to the nice people at CS-Telecom for the hardware and the
 11  * access to the test/measure tools.
 12  *
 13  *
 14  *                             Theory of Operation
 15  *
 16  * I. Board Compatibility
 17  *
 18  * This device driver is designed for the Siemens PEB20534 4 ports serial
 19  * controller as found on Etinc PCISYNC cards. The documentation for the
 20  * chipset is available at http://www.infineon.com:
 21  * - Data Sheet "DSCC4, DMA Supported Serial Communication Controller with
 22  * 4 Channels, PEB 20534 Version 2.1, PEF 20534 Version 2.1";
 23  * - Application Hint "Management of DSCC4 on-chip FIFO resources".
 24  * - Errata sheet DS5 (courtesy of Michael Skerritt).
 25  * Jens David has built an adapter based on the same chipset. Take a look
 26  * at http://www.afthd.tu-darmstadt.de/~dg1kjd/pciscc4 for a specific
 27  * driver.
 28  * Sample code (2 revisions) is available at Infineon.
 29  *
 30  * II. Board-specific settings
 31  *
 32  * Pcisync can transmit some clock signal to the outside world on the
 33  * *first two* ports provided you put a quartz and a line driver on it and
 34  * remove the jumpers. The operation is described on Etinc web site. If you
 35  * go DCE on these ports, don't forget to use an adequate cable.
 36  *
 37  * Sharing of the PCI interrupt line for this board is possible.
 38  *
 39  * III. Driver operation
 40  *
 41  * The rx/tx operations are based on a linked list of descriptors. The driver
 42  * doesn't use HOLD mode any more. HOLD mode is definitely buggy and the more
 43  * I tried to fix it, the more it started to look like (convoluted) software
 44  * mutation of LxDA method. Errata sheet DS5 suggests to use LxDA: consider
 45  * this a rfc2119 MUST.
 46  *
 47  * Tx direction
 48  * When the tx ring is full, the xmit routine issues a call to netdev_stop.
 49  * The device is supposed to be enabled again during an ALLS irq (we could
 50  * use HI but as it's easy to lose events, it's fscked).
 51  *
 52  * Rx direction
 53  * The received frames aren't supposed to span over multiple receiving areas.
 54  * I may implement it some day but it isn't the highest ranked item.
 55  *
 56  * IV. Notes
 57  * The current error (XDU, RFO) recovery code is untested.
 58  * So far, RDO takes his RX channel down and the right sequence to enable it
 59  * again is still a mystery. If RDO happens, plan a reboot. More details
 60  * in the code (NB: as this happens, TX still works).
 61  * Don't mess the cables during operation, especially on DTE ports. I don't
 62  * suggest it for DCE either but at least one can get some messages instead
 63  * of a complete instant freeze.
 64  * Tests are done on Rev. 20 of the silicium. The RDO handling changes with
 65  * the documentation/chipset releases.
 66  *
 67  * TODO:
 68  * - test X25.
 69  * - use polling at high irq/s,
 70  * - performance analysis,
 71  * - endianness.
 72  *
 73  * 2001/12/10   Daniela Squassoni  <daniela@cyclades.com>
 74  * - Contribution to support the new generic HDLC layer.
 75  *
 76  * 2002/01      Ueimor
 77  * - old style interface removal
 78  * - dscc4_release_ring fix (related to DMA mapping)
 79  * - hard_start_xmit fix (hint: TxSizeMax)
 80  * - misc crapectomy.
 81  */
 82 
 83 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 84 
 85 #include <linux/module.h>
 86 #include <linux/sched.h>
 87 #include <linux/types.h>
 88 #include <linux/errno.h>
 89 #include <linux/list.h>
 90 #include <linux/ioport.h>
 91 #include <linux/pci.h>
 92 #include <linux/kernel.h>
 93 #include <linux/mm.h>
 94 #include <linux/slab.h>
 95 
 96 #include <asm/cache.h>
 97 #include <asm/byteorder.h>
 98 #include <linux/uaccess.h>
 99 #include <asm/io.h>
100 #include <asm/irq.h>
101 
102 #include <linux/init.h>
103 #include <linux/interrupt.h>
104 #include <linux/string.h>
105 
106 #include <linux/if_arp.h>
107 #include <linux/netdevice.h>
108 #include <linux/skbuff.h>
109 #include <linux/delay.h>
110 #include <linux/hdlc.h>
111 #include <linux/mutex.h>
112 
113 /* Version */
114 static const char version[] = "$Id: dscc4.c,v 1.173 2003/09/20 23:55:34 romieu Exp $ for Linux\n";
115 static int debug;
116 static int quartz;
117 
118 #ifdef CONFIG_DSCC4_PCI_RST
119 static DEFINE_MUTEX(dscc4_mutex);
120 static u32 dscc4_pci_config_store[16];
121 #endif
122 
123 #define DRV_NAME        "dscc4"
124 
125 #undef DSCC4_POLLING
126 
127 /* Module parameters */
128 
129 MODULE_AUTHOR("Maintainer: Francois Romieu <romieu@cogenit.fr>");
130 MODULE_DESCRIPTION("Siemens PEB20534 PCI Controller");
131 MODULE_LICENSE("GPL");
132 module_param(debug, int, 0);
133 MODULE_PARM_DESC(debug,"Enable/disable extra messages");
134 module_param(quartz, int, 0);
135 MODULE_PARM_DESC(quartz,"If present, on-board quartz frequency (Hz)");
136 
137 /* Structures */
138 
139 struct thingie {
140         int define;
141         u32 bits;
142 };
143 
144 struct TxFD {
145         __le32 state;
146         __le32 next;
147         __le32 data;
148         __le32 complete;
149         u32 jiffies; /* Allows sizeof(TxFD) == sizeof(RxFD) + extra hack */
150                      /* FWIW, datasheet calls that "dummy" and says that card
151                       * never looks at it; neither does the driver */
152 };
153 
154 struct RxFD {
155         __le32 state1;
156         __le32 next;
157         __le32 data;
158         __le32 state2;
159         __le32 end;
160 };
161 
162 #define DUMMY_SKB_SIZE          64
163 #define TX_LOW                  8
164 #define TX_RING_SIZE            32
165 #define RX_RING_SIZE            32
166 #define TX_TOTAL_SIZE           TX_RING_SIZE*sizeof(struct TxFD)
167 #define RX_TOTAL_SIZE           RX_RING_SIZE*sizeof(struct RxFD)
168 #define IRQ_RING_SIZE           64              /* Keep it a multiple of 32 */
169 #define TX_TIMEOUT              (HZ/10)
170 #define DSCC4_HZ_MAX            33000000
171 #define BRR_DIVIDER_MAX         64*0x00004000   /* Cf errata DS5 p.10 */
172 #define dev_per_card            4
173 #define SCC_REGISTERS_MAX       23              /* Cf errata DS5 p.4 */
174 
175 #define SOURCE_ID(flags)        (((flags) >> 28) & 0x03)
176 #define TO_SIZE(state)          (((state) >> 16) & 0x1fff)
177 
178 /*
179  * Given the operating range of Linux HDLC, the 2 defines below could be
180  * made simpler. However they are a fine reminder for the limitations of
181  * the driver: it's better to stay < TxSizeMax and < RxSizeMax.
182  */
183 #define TO_STATE_TX(len)        cpu_to_le32(((len) & TxSizeMax) << 16)
184 #define TO_STATE_RX(len)        cpu_to_le32((RX_MAX(len) % RxSizeMax) << 16)
185 #define RX_MAX(len)             ((((len) >> 5) + 1) << 5)       /* Cf RLCR */
186 #define SCC_REG_START(dpriv)    (SCC_START+(dpriv->dev_id)*SCC_OFFSET)
187 
188 struct dscc4_pci_priv {
189         __le32 *iqcfg;
190         int cfg_cur;
191         spinlock_t lock;
192         struct pci_dev *pdev;
193 
194         struct dscc4_dev_priv *root;
195         dma_addr_t iqcfg_dma;
196         u32 xtal_hz;
197 };
198 
199 struct dscc4_dev_priv {
200         struct sk_buff *rx_skbuff[RX_RING_SIZE];
201         struct sk_buff *tx_skbuff[TX_RING_SIZE];
202 
203         struct RxFD *rx_fd;
204         struct TxFD *tx_fd;
205         __le32 *iqrx;
206         __le32 *iqtx;
207 
208         /* FIXME: check all the volatile are required */
209         volatile u32 tx_current;
210         u32 rx_current;
211         u32 iqtx_current;
212         u32 iqrx_current;
213 
214         volatile u32 tx_dirty;
215         volatile u32 ltda;
216         u32 rx_dirty;
217         u32 lrda;
218 
219         dma_addr_t tx_fd_dma;
220         dma_addr_t rx_fd_dma;
221         dma_addr_t iqtx_dma;
222         dma_addr_t iqrx_dma;
223 
224         u32 scc_regs[SCC_REGISTERS_MAX]; /* Cf errata DS5 p.4 */
225 
226         struct timer_list timer;
227 
228         struct dscc4_pci_priv *pci_priv;
229         spinlock_t lock;
230 
231         int dev_id;
232         volatile u32 flags;
233         u32 timer_help;
234 
235         unsigned short encoding;
236         unsigned short parity;
237         struct net_device *dev;
238         sync_serial_settings settings;
239         void __iomem *base_addr;
240         u32 __pad __attribute__ ((aligned (4)));
241 };
242 
243 /* GLOBAL registers definitions */
244 #define GCMDR   0x00
245 #define GSTAR   0x04
246 #define GMODE   0x08
247 #define IQLENR0 0x0C
248 #define IQLENR1 0x10
249 #define IQRX0   0x14
250 #define IQTX0   0x24
251 #define IQCFG   0x3c
252 #define FIFOCR1 0x44
253 #define FIFOCR2 0x48
254 #define FIFOCR3 0x4c
255 #define FIFOCR4 0x34
256 #define CH0CFG  0x50
257 #define CH0BRDA 0x54
258 #define CH0BTDA 0x58
259 #define CH0FRDA 0x98
260 #define CH0FTDA 0xb0
261 #define CH0LRDA 0xc8
262 #define CH0LTDA 0xe0
263 
264 /* SCC registers definitions */
265 #define SCC_START       0x0100
266 #define SCC_OFFSET      0x80
267 #define CMDR    0x00
268 #define STAR    0x04
269 #define CCR0    0x08
270 #define CCR1    0x0c
271 #define CCR2    0x10
272 #define BRR     0x2C
273 #define RLCR    0x40
274 #define IMR     0x54
275 #define ISR     0x58
276 
277 #define GPDIR   0x0400
278 #define GPDATA  0x0404
279 #define GPIM    0x0408
280 
281 /* Bit masks */
282 #define EncodingMask    0x00700000
283 #define CrcMask         0x00000003
284 
285 #define IntRxScc0       0x10000000
286 #define IntTxScc0       0x01000000
287 
288 #define TxPollCmd       0x00000400
289 #define RxActivate      0x08000000
290 #define MTFi            0x04000000
291 #define Rdr             0x00400000
292 #define Rdt             0x00200000
293 #define Idr             0x00100000
294 #define Idt             0x00080000
295 #define TxSccRes        0x01000000
296 #define RxSccRes        0x00010000
297 #define TxSizeMax       0x1fff          /* Datasheet DS1 - 11.1.1.1 */
298 #define RxSizeMax       0x1ffc          /* Datasheet DS1 - 11.1.2.1 */
299 
300 #define Ccr0ClockMask   0x0000003f
301 #define Ccr1LoopMask    0x00000200
302 #define IsrMask         0x000fffff
303 #define BrrExpMask      0x00000f00
304 #define BrrMultMask     0x0000003f
305 #define EncodingMask    0x00700000
306 #define Hold            cpu_to_le32(0x40000000)
307 #define SccBusy         0x10000000
308 #define PowerUp         0x80000000
309 #define Vis             0x00001000
310 #define FrameOk         (FrameVfr | FrameCrc)
311 #define FrameVfr        0x80
312 #define FrameRdo        0x40
313 #define FrameCrc        0x20
314 #define FrameRab        0x10
315 #define FrameAborted    cpu_to_le32(0x00000200)
316 #define FrameEnd        cpu_to_le32(0x80000000)
317 #define DataComplete    cpu_to_le32(0x40000000)
318 #define LengthCheck     0x00008000
319 #define SccEvt          0x02000000
320 #define NoAck           0x00000200
321 #define Action          0x00000001
322 #define HiDesc          cpu_to_le32(0x20000000)
323 
324 /* SCC events */
325 #define RxEvt           0xf0000000
326 #define TxEvt           0x0f000000
327 #define Alls            0x00040000
328 #define Xdu             0x00010000
329 #define Cts             0x00004000
330 #define Xmr             0x00002000
331 #define Xpr             0x00001000
332 #define Rdo             0x00000080
333 #define Rfs             0x00000040
334 #define Cd              0x00000004
335 #define Rfo             0x00000002
336 #define Flex            0x00000001
337 
338 /* DMA core events */
339 #define Cfg             0x00200000
340 #define Hi              0x00040000
341 #define Fi              0x00020000
342 #define Err             0x00010000
343 #define Arf             0x00000002
344 #define ArAck           0x00000001
345 
346 /* State flags */
347 #define Ready           0x00000000
348 #define NeedIDR         0x00000001
349 #define NeedIDT         0x00000002
350 #define RdoSet          0x00000004
351 #define FakeReset       0x00000008
352 
353 /* Don't mask RDO. Ever. */
354 #ifdef DSCC4_POLLING
355 #define EventsMask      0xfffeef7f
356 #else
357 #define EventsMask      0xfffa8f7a
358 #endif
359 
360 /* Functions prototypes */
361 static void dscc4_rx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
362 static void dscc4_tx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
363 static int dscc4_found1(struct pci_dev *, void __iomem *ioaddr);
364 static int dscc4_init_one(struct pci_dev *, const struct pci_device_id *ent);
365 static int dscc4_open(struct net_device *);
366 static netdev_tx_t dscc4_start_xmit(struct sk_buff *,
367                                           struct net_device *);
368 static int dscc4_close(struct net_device *);
369 static int dscc4_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
370 static int dscc4_init_ring(struct net_device *);
371 static void dscc4_release_ring(struct dscc4_dev_priv *);
372 static void dscc4_timer(unsigned long);
373 static void dscc4_tx_timeout(struct net_device *);
374 static irqreturn_t dscc4_irq(int irq, void *dev_id);
375 static int dscc4_hdlc_attach(struct net_device *, unsigned short, unsigned short);
376 static int dscc4_set_iface(struct dscc4_dev_priv *, struct net_device *);
377 #ifdef DSCC4_POLLING
378 static int dscc4_tx_poll(struct dscc4_dev_priv *, struct net_device *);
379 #endif
380 
381 static inline struct dscc4_dev_priv *dscc4_priv(struct net_device *dev)
382 {
383         return dev_to_hdlc(dev)->priv;
384 }
385 
386 static inline struct net_device *dscc4_to_dev(struct dscc4_dev_priv *p)
387 {
388         return p->dev;
389 }
390 
391 static void scc_patchl(u32 mask, u32 value, struct dscc4_dev_priv *dpriv,
392                         struct net_device *dev, int offset)
393 {
394         u32 state;
395 
396         /* Cf scc_writel for concern regarding thread-safety */
397         state = dpriv->scc_regs[offset >> 2];
398         state &= ~mask;
399         state |= value;
400         dpriv->scc_regs[offset >> 2] = state;
401         writel(state, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
402 }
403 
404 static void scc_writel(u32 bits, struct dscc4_dev_priv *dpriv,
405                        struct net_device *dev, int offset)
406 {
407         /*
408          * Thread-UNsafe.
409          * As of 2002/02/16, there are no thread racing for access.
410          */
411         dpriv->scc_regs[offset >> 2] = bits;
412         writel(bits, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
413 }
414 
415 static inline u32 scc_readl(struct dscc4_dev_priv *dpriv, int offset)
416 {
417         return dpriv->scc_regs[offset >> 2];
418 }
419 
420 static u32 scc_readl_star(struct dscc4_dev_priv *dpriv, struct net_device *dev)
421 {
422         /* Cf errata DS5 p.4 */
423         readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
424         return readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
425 }
426 
427 static inline void dscc4_do_tx(struct dscc4_dev_priv *dpriv,
428                                struct net_device *dev)
429 {
430         dpriv->ltda = dpriv->tx_fd_dma +
431                       ((dpriv->tx_current-1)%TX_RING_SIZE)*sizeof(struct TxFD);
432         writel(dpriv->ltda, dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
433         /* Flush posted writes *NOW* */
434         readl(dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
435 }
436 
437 static inline void dscc4_rx_update(struct dscc4_dev_priv *dpriv,
438                                    struct net_device *dev)
439 {
440         dpriv->lrda = dpriv->rx_fd_dma +
441                       ((dpriv->rx_dirty - 1)%RX_RING_SIZE)*sizeof(struct RxFD);
442         writel(dpriv->lrda, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
443 }
444 
445 static inline unsigned int dscc4_tx_done(struct dscc4_dev_priv *dpriv)
446 {
447         return dpriv->tx_current == dpriv->tx_dirty;
448 }
449 
450 static inline unsigned int dscc4_tx_quiescent(struct dscc4_dev_priv *dpriv,
451                                               struct net_device *dev)
452 {
453         return readl(dpriv->base_addr + CH0FTDA + dpriv->dev_id*4) == dpriv->ltda;
454 }
455 
456 static int state_check(u32 state, struct dscc4_dev_priv *dpriv,
457                        struct net_device *dev, const char *msg)
458 {
459         int ret = 0;
460 
461         if (debug > 1) {
462         if (SOURCE_ID(state) != dpriv->dev_id) {
463                 printk(KERN_DEBUG "%s (%s): Source Id=%d, state=%08x\n",
464                        dev->name, msg, SOURCE_ID(state), state );
465                         ret = -1;
466         }
467         if (state & 0x0df80c00) {
468                 printk(KERN_DEBUG "%s (%s): state=%08x (UFO alert)\n",
469                        dev->name, msg, state);
470                         ret = -1;
471         }
472         }
473         return ret;
474 }
475 
476 static void dscc4_tx_print(struct net_device *dev,
477                            struct dscc4_dev_priv *dpriv,
478                            char *msg)
479 {
480         printk(KERN_DEBUG "%s: tx_current=%02d tx_dirty=%02d (%s)\n",
481                dev->name, dpriv->tx_current, dpriv->tx_dirty, msg);
482 }
483 
484 static void dscc4_release_ring(struct dscc4_dev_priv *dpriv)
485 {
486         struct pci_dev *pdev = dpriv->pci_priv->pdev;
487         struct TxFD *tx_fd = dpriv->tx_fd;
488         struct RxFD *rx_fd = dpriv->rx_fd;
489         struct sk_buff **skbuff;
490         int i;
491 
492         pci_free_consistent(pdev, TX_TOTAL_SIZE, tx_fd, dpriv->tx_fd_dma);
493         pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
494 
495         skbuff = dpriv->tx_skbuff;
496         for (i = 0; i < TX_RING_SIZE; i++) {
497                 if (*skbuff) {
498                         pci_unmap_single(pdev, le32_to_cpu(tx_fd->data),
499                                 (*skbuff)->len, PCI_DMA_TODEVICE);
500                         dev_kfree_skb(*skbuff);
501                 }
502                 skbuff++;
503                 tx_fd++;
504         }
505 
506         skbuff = dpriv->rx_skbuff;
507         for (i = 0; i < RX_RING_SIZE; i++) {
508                 if (*skbuff) {
509                         pci_unmap_single(pdev, le32_to_cpu(rx_fd->data),
510                                 RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
511                         dev_kfree_skb(*skbuff);
512                 }
513                 skbuff++;
514                 rx_fd++;
515         }
516 }
517 
518 static inline int try_get_rx_skb(struct dscc4_dev_priv *dpriv,
519                                  struct net_device *dev)
520 {
521         unsigned int dirty = dpriv->rx_dirty%RX_RING_SIZE;
522         struct RxFD *rx_fd = dpriv->rx_fd + dirty;
523         const int len = RX_MAX(HDLC_MAX_MRU);
524         struct sk_buff *skb;
525         int ret = 0;
526 
527         skb = dev_alloc_skb(len);
528         dpriv->rx_skbuff[dirty] = skb;
529         if (skb) {
530                 skb->protocol = hdlc_type_trans(skb, dev);
531                 rx_fd->data = cpu_to_le32(pci_map_single(dpriv->pci_priv->pdev,
532                                           skb->data, len, PCI_DMA_FROMDEVICE));
533         } else {
534                 rx_fd->data = 0;
535                 ret = -1;
536         }
537         return ret;
538 }
539 
540 /*
541  * IRQ/thread/whatever safe
542  */
543 static int dscc4_wait_ack_cec(struct dscc4_dev_priv *dpriv,
544                               struct net_device *dev, char *msg)
545 {
546         s8 i = 0;
547 
548         do {
549                 if (!(scc_readl_star(dpriv, dev) & SccBusy)) {
550                         printk(KERN_DEBUG "%s: %s ack (%d try)\n", dev->name,
551                                msg, i);
552                         goto done;
553                 }
554                 schedule_timeout_uninterruptible(msecs_to_jiffies(100));
555                 rmb();
556         } while (++i > 0);
557         netdev_err(dev, "%s timeout\n", msg);
558 done:
559         return (i >= 0) ? i : -EAGAIN;
560 }
561 
562 static int dscc4_do_action(struct net_device *dev, char *msg)
563 {
564         void __iomem *ioaddr = dscc4_priv(dev)->base_addr;
565         s16 i = 0;
566 
567         writel(Action, ioaddr + GCMDR);
568         ioaddr += GSTAR;
569         do {
570                 u32 state = readl(ioaddr);
571 
572                 if (state & ArAck) {
573                         netdev_dbg(dev, "%s ack\n", msg);
574                         writel(ArAck, ioaddr);
575                         goto done;
576                 } else if (state & Arf) {
577                         netdev_err(dev, "%s failed\n", msg);
578                         writel(Arf, ioaddr);
579                         i = -1;
580                         goto done;
581         }
582                 rmb();
583         } while (++i > 0);
584         netdev_err(dev, "%s timeout\n", msg);
585 done:
586         return i;
587 }
588 
589 static inline int dscc4_xpr_ack(struct dscc4_dev_priv *dpriv)
590 {
591         int cur = dpriv->iqtx_current%IRQ_RING_SIZE;
592         s8 i = 0;
593 
594         do {
595                 if (!(dpriv->flags & (NeedIDR | NeedIDT)) ||
596                     (dpriv->iqtx[cur] & cpu_to_le32(Xpr)))
597                         break;
598                 smp_rmb();
599                 schedule_timeout_uninterruptible(msecs_to_jiffies(100));
600         } while (++i > 0);
601 
602         return (i >= 0 ) ? i : -EAGAIN;
603 }
604 
605 #if 0 /* dscc4_{rx/tx}_reset are both unreliable - more tweak needed */
606 static void dscc4_rx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
607 {
608         unsigned long flags;
609 
610         spin_lock_irqsave(&dpriv->pci_priv->lock, flags);
611         /* Cf errata DS5 p.6 */
612         writel(0x00000000, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
613         scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
614         readl(dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
615         writel(MTFi|Rdr, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
616         writel(Action, dpriv->base_addr + GCMDR);
617         spin_unlock_irqrestore(&dpriv->pci_priv->lock, flags);
618 }
619 
620 #endif
621 
622 #if 0
623 static void dscc4_tx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
624 {
625         u16 i = 0;
626 
627         /* Cf errata DS5 p.7 */
628         scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
629         scc_writel(0x00050000, dpriv, dev, CCR2);
630         /*
631          * Must be longer than the time required to fill the fifo.
632          */
633         while (!dscc4_tx_quiescent(dpriv, dev) && ++i) {
634                 udelay(1);
635                 wmb();
636         }
637 
638         writel(MTFi|Rdt, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
639         if (dscc4_do_action(dev, "Rdt") < 0)
640                 netdev_err(dev, "Tx reset failed\n");
641 }
642 #endif
643 
644 /* TODO: (ab)use this function to refill a completely depleted RX ring. */
645 static inline void dscc4_rx_skb(struct dscc4_dev_priv *dpriv,
646                                 struct net_device *dev)
647 {
648         struct RxFD *rx_fd = dpriv->rx_fd + dpriv->rx_current%RX_RING_SIZE;
649         struct pci_dev *pdev = dpriv->pci_priv->pdev;
650         struct sk_buff *skb;
651         int pkt_len;
652 
653         skb = dpriv->rx_skbuff[dpriv->rx_current++%RX_RING_SIZE];
654         if (!skb) {
655                 printk(KERN_DEBUG "%s: skb=0 (%s)\n", dev->name, __func__);
656                 goto refill;
657         }
658         pkt_len = TO_SIZE(le32_to_cpu(rx_fd->state2));
659         pci_unmap_single(pdev, le32_to_cpu(rx_fd->data),
660                          RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
661         if ((skb->data[--pkt_len] & FrameOk) == FrameOk) {
662                 dev->stats.rx_packets++;
663                 dev->stats.rx_bytes += pkt_len;
664                 skb_put(skb, pkt_len);
665                 if (netif_running(dev))
666                         skb->protocol = hdlc_type_trans(skb, dev);
667                 netif_rx(skb);
668         } else {
669                 if (skb->data[pkt_len] & FrameRdo)
670                         dev->stats.rx_fifo_errors++;
671                 else if (!(skb->data[pkt_len] & FrameCrc))
672                         dev->stats.rx_crc_errors++;
673                 else if ((skb->data[pkt_len] & (FrameVfr | FrameRab)) !=
674                          (FrameVfr | FrameRab))
675                         dev->stats.rx_length_errors++;
676                 dev->stats.rx_errors++;
677                 dev_kfree_skb_irq(skb);
678         }
679 refill:
680         while ((dpriv->rx_dirty - dpriv->rx_current) % RX_RING_SIZE) {
681                 if (try_get_rx_skb(dpriv, dev) < 0)
682                         break;
683                 dpriv->rx_dirty++;
684         }
685         dscc4_rx_update(dpriv, dev);
686         rx_fd->state2 = 0x00000000;
687         rx_fd->end = cpu_to_le32(0xbabeface);
688 }
689 
690 static void dscc4_free1(struct pci_dev *pdev)
691 {
692         struct dscc4_pci_priv *ppriv;
693         struct dscc4_dev_priv *root;
694         int i;
695 
696         ppriv = pci_get_drvdata(pdev);
697         root = ppriv->root;
698 
699         for (i = 0; i < dev_per_card; i++)
700                 unregister_hdlc_device(dscc4_to_dev(root + i));
701 
702         for (i = 0; i < dev_per_card; i++)
703                 free_netdev(root[i].dev);
704         kfree(root);
705         kfree(ppriv);
706 }
707 
708 static int dscc4_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
709 {
710         struct dscc4_pci_priv *priv;
711         struct dscc4_dev_priv *dpriv;
712         void __iomem *ioaddr;
713         int i, rc;
714 
715         printk(KERN_DEBUG "%s", version);
716 
717         rc = pci_enable_device(pdev);
718         if (rc < 0)
719                 goto out;
720 
721         rc = pci_request_region(pdev, 0, "registers");
722         if (rc < 0) {
723                 pr_err("can't reserve MMIO region (regs)\n");
724                 goto err_disable_0;
725         }
726         rc = pci_request_region(pdev, 1, "LBI interface");
727         if (rc < 0) {
728                 pr_err("can't reserve MMIO region (lbi)\n");
729                 goto err_free_mmio_region_1;
730         }
731 
732         ioaddr = pci_ioremap_bar(pdev, 0);
733         if (!ioaddr) {
734                 pr_err("cannot remap MMIO region %llx @ %llx\n",
735                        (unsigned long long)pci_resource_len(pdev, 0),
736                        (unsigned long long)pci_resource_start(pdev, 0));
737                 rc = -EIO;
738                 goto err_free_mmio_regions_2;
739         }
740         printk(KERN_DEBUG "Siemens DSCC4, MMIO at %#llx (regs), %#llx (lbi), IRQ %d\n",
741                 (unsigned long long)pci_resource_start(pdev, 0),
742                 (unsigned long long)pci_resource_start(pdev, 1), pdev->irq);
743 
744         /* Cf errata DS5 p.2 */
745         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xf8);
746         pci_set_master(pdev);
747 
748         rc = dscc4_found1(pdev, ioaddr);
749         if (rc < 0)
750                 goto err_iounmap_3;
751 
752         priv = pci_get_drvdata(pdev);
753 
754         rc = request_irq(pdev->irq, dscc4_irq, IRQF_SHARED, DRV_NAME, priv->root);
755         if (rc < 0) {
756                 pr_warn("IRQ %d busy\n", pdev->irq);
757                 goto err_release_4;
758         }
759 
760         /* power up/little endian/dma core controlled via lrda/ltda */
761         writel(0x00000001, ioaddr + GMODE);
762         /* Shared interrupt queue */
763         {
764                 u32 bits;
765 
766                 bits = (IRQ_RING_SIZE >> 5) - 1;
767                 bits |= bits << 4;
768                 bits |= bits << 8;
769                 bits |= bits << 16;
770                 writel(bits, ioaddr + IQLENR0);
771         }
772         /* Global interrupt queue */
773         writel((u32)(((IRQ_RING_SIZE >> 5) - 1) << 20), ioaddr + IQLENR1);
774 
775         rc = -ENOMEM;
776 
777         priv->iqcfg = (__le32 *) pci_alloc_consistent(pdev,
778                 IRQ_RING_SIZE*sizeof(__le32), &priv->iqcfg_dma);
779         if (!priv->iqcfg)
780                 goto err_free_irq_5;
781         writel(priv->iqcfg_dma, ioaddr + IQCFG);
782 
783         /*
784          * SCC 0-3 private rx/tx irq structures
785          * IQRX/TXi needs to be set soon. Learned it the hard way...
786          */
787         for (i = 0; i < dev_per_card; i++) {
788                 dpriv = priv->root + i;
789                 dpriv->iqtx = (__le32 *) pci_alloc_consistent(pdev,
790                         IRQ_RING_SIZE*sizeof(u32), &dpriv->iqtx_dma);
791                 if (!dpriv->iqtx)
792                         goto err_free_iqtx_6;
793                 writel(dpriv->iqtx_dma, ioaddr + IQTX0 + i*4);
794         }
795         for (i = 0; i < dev_per_card; i++) {
796                 dpriv = priv->root + i;
797                 dpriv->iqrx = (__le32 *) pci_alloc_consistent(pdev,
798                         IRQ_RING_SIZE*sizeof(u32), &dpriv->iqrx_dma);
799                 if (!dpriv->iqrx)
800                         goto err_free_iqrx_7;
801                 writel(dpriv->iqrx_dma, ioaddr + IQRX0 + i*4);
802         }
803 
804         /* Cf application hint. Beware of hard-lock condition on threshold. */
805         writel(0x42104000, ioaddr + FIFOCR1);
806         //writel(0x9ce69800, ioaddr + FIFOCR2);
807         writel(0xdef6d800, ioaddr + FIFOCR2);
808         //writel(0x11111111, ioaddr + FIFOCR4);
809         writel(0x18181818, ioaddr + FIFOCR4);
810         // FIXME: should depend on the chipset revision
811         writel(0x0000000e, ioaddr + FIFOCR3);
812 
813         writel(0xff200001, ioaddr + GCMDR);
814 
815         rc = 0;
816 out:
817         return rc;
818 
819 err_free_iqrx_7:
820         while (--i >= 0) {
821                 dpriv = priv->root + i;
822                 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
823                                     dpriv->iqrx, dpriv->iqrx_dma);
824         }
825         i = dev_per_card;
826 err_free_iqtx_6:
827         while (--i >= 0) {
828                 dpriv = priv->root + i;
829                 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
830                                     dpriv->iqtx, dpriv->iqtx_dma);
831         }
832         pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), priv->iqcfg,
833                             priv->iqcfg_dma);
834 err_free_irq_5:
835         free_irq(pdev->irq, priv->root);
836 err_release_4:
837         dscc4_free1(pdev);
838 err_iounmap_3:
839         iounmap (ioaddr);
840 err_free_mmio_regions_2:
841         pci_release_region(pdev, 1);
842 err_free_mmio_region_1:
843         pci_release_region(pdev, 0);
844 err_disable_0:
845         pci_disable_device(pdev);
846         goto out;
847 };
848 
849 /*
850  * Let's hope the default values are decent enough to protect my
851  * feet from the user's gun - Ueimor
852  */
853 static void dscc4_init_registers(struct dscc4_dev_priv *dpriv,
854                                  struct net_device *dev)
855 {
856         /* No interrupts, SCC core disabled. Let's relax */
857         scc_writel(0x00000000, dpriv, dev, CCR0);
858 
859         scc_writel(LengthCheck | (HDLC_MAX_MRU >> 5), dpriv, dev, RLCR);
860 
861         /*
862          * No address recognition/crc-CCITT/cts enabled
863          * Shared flags transmission disabled - cf errata DS5 p.11
864          * Carrier detect disabled - cf errata p.14
865          * FIXME: carrier detection/polarity may be handled more gracefully.
866          */
867         scc_writel(0x02408000, dpriv, dev, CCR1);
868 
869         /* crc not forwarded - Cf errata DS5 p.11 */
870         scc_writel(0x00050008 & ~RxActivate, dpriv, dev, CCR2);
871         // crc forwarded
872         //scc_writel(0x00250008 & ~RxActivate, dpriv, dev, CCR2);
873 }
874 
875 static inline int dscc4_set_quartz(struct dscc4_dev_priv *dpriv, int hz)
876 {
877         int ret = 0;
878 
879         if ((hz < 0) || (hz > DSCC4_HZ_MAX))
880                 ret = -EOPNOTSUPP;
881         else
882                 dpriv->pci_priv->xtal_hz = hz;
883 
884         return ret;
885 }
886 
887 static const struct net_device_ops dscc4_ops = {
888         .ndo_open       = dscc4_open,
889         .ndo_stop       = dscc4_close,
890         .ndo_start_xmit = hdlc_start_xmit,
891         .ndo_do_ioctl   = dscc4_ioctl,
892         .ndo_tx_timeout = dscc4_tx_timeout,
893 };
894 
895 static int dscc4_found1(struct pci_dev *pdev, void __iomem *ioaddr)
896 {
897         struct dscc4_pci_priv *ppriv;
898         struct dscc4_dev_priv *root;
899         int i, ret = -ENOMEM;
900 
901         root = kcalloc(dev_per_card, sizeof(*root), GFP_KERNEL);
902         if (!root)
903                 goto err_out;
904 
905         for (i = 0; i < dev_per_card; i++) {
906                 root[i].dev = alloc_hdlcdev(root + i);
907                 if (!root[i].dev)
908                         goto err_free_dev;
909         }
910 
911         ppriv = kzalloc(sizeof(*ppriv), GFP_KERNEL);
912         if (!ppriv)
913                 goto err_free_dev;
914 
915         ppriv->root = root;
916         spin_lock_init(&ppriv->lock);
917 
918         for (i = 0; i < dev_per_card; i++) {
919                 struct dscc4_dev_priv *dpriv = root + i;
920                 struct net_device *d = dscc4_to_dev(dpriv);
921                 hdlc_device *hdlc = dev_to_hdlc(d);
922 
923                 d->base_addr = (unsigned long)ioaddr;
924                 d->irq = pdev->irq;
925                 d->netdev_ops = &dscc4_ops;
926                 d->watchdog_timeo = TX_TIMEOUT;
927                 SET_NETDEV_DEV(d, &pdev->dev);
928 
929                 dpriv->dev_id = i;
930                 dpriv->pci_priv = ppriv;
931                 dpriv->base_addr = ioaddr;
932                 spin_lock_init(&dpriv->lock);
933 
934                 hdlc->xmit = dscc4_start_xmit;
935                 hdlc->attach = dscc4_hdlc_attach;
936 
937                 dscc4_init_registers(dpriv, d);
938                 dpriv->parity = PARITY_CRC16_PR0_CCITT;
939                 dpriv->encoding = ENCODING_NRZ;
940         
941                 ret = dscc4_init_ring(d);
942                 if (ret < 0)
943                         goto err_unregister;
944 
945                 ret = register_hdlc_device(d);
946                 if (ret < 0) {
947                         pr_err("unable to register\n");
948                         dscc4_release_ring(dpriv);
949                         goto err_unregister;
950                 }
951         }
952 
953         ret = dscc4_set_quartz(root, quartz);
954         if (ret < 0)
955                 goto err_unregister;
956 
957         pci_set_drvdata(pdev, ppriv);
958         return ret;
959 
960 err_unregister:
961         while (i-- > 0) {
962                 dscc4_release_ring(root + i);
963                 unregister_hdlc_device(dscc4_to_dev(root + i));
964         }
965         kfree(ppriv);
966         i = dev_per_card;
967 err_free_dev:
968         while (i-- > 0)
969                 free_netdev(root[i].dev);
970         kfree(root);
971 err_out:
972         return ret;
973 };
974 
975 /* FIXME: get rid of the unneeded code */
976 static void dscc4_timer(unsigned long data)
977 {
978         struct net_device *dev = (struct net_device *)data;
979         struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
980 //      struct dscc4_pci_priv *ppriv;
981 
982         goto done;
983 done:
984         dpriv->timer.expires = jiffies + TX_TIMEOUT;
985         add_timer(&dpriv->timer);
986 }
987 
988 static void dscc4_tx_timeout(struct net_device *dev)
989 {
990         /* FIXME: something is missing there */
991 }
992 
993 static int dscc4_loopback_check(struct dscc4_dev_priv *dpriv)
994 {
995         sync_serial_settings *settings = &dpriv->settings;
996 
997         if (settings->loopback && (settings->clock_type != CLOCK_INT)) {
998                 struct net_device *dev = dscc4_to_dev(dpriv);
999 
1000                 netdev_info(dev, "loopback requires clock\n");
1001                 return -1;
1002         }
1003         return 0;
1004 }
1005 
1006 #ifdef CONFIG_DSCC4_PCI_RST
1007 /*
1008  * Some DSCC4-based cards wires the GPIO port and the PCI #RST pin together
1009  * so as to provide a safe way to reset the asic while not the whole machine
1010  * rebooting.
1011  *
1012  * This code doesn't need to be efficient. Keep It Simple
1013  */
1014 static void dscc4_pci_reset(struct pci_dev *pdev, void __iomem *ioaddr)
1015 {
1016         int i;
1017 
1018         mutex_lock(&dscc4_mutex);
1019         for (i = 0; i < 16; i++)
1020                 pci_read_config_dword(pdev, i << 2, dscc4_pci_config_store + i);
1021 
1022         /* Maximal LBI clock divider (who cares ?) and whole GPIO range. */
1023         writel(0x001c0000, ioaddr + GMODE);
1024         /* Configure GPIO port as output */
1025         writel(0x0000ffff, ioaddr + GPDIR);
1026         /* Disable interruption */
1027         writel(0x0000ffff, ioaddr + GPIM);
1028 
1029         writel(0x0000ffff, ioaddr + GPDATA);
1030         writel(0x00000000, ioaddr + GPDATA);
1031 
1032         /* Flush posted writes */
1033         readl(ioaddr + GSTAR);
1034 
1035         schedule_timeout_uninterruptible(msecs_to_jiffies(100));
1036 
1037         for (i = 0; i < 16; i++)
1038                 pci_write_config_dword(pdev, i << 2, dscc4_pci_config_store[i]);
1039         mutex_unlock(&dscc4_mutex);
1040 }
1041 #else
1042 #define dscc4_pci_reset(pdev,ioaddr)    do {} while (0)
1043 #endif /* CONFIG_DSCC4_PCI_RST */
1044 
1045 static int dscc4_open(struct net_device *dev)
1046 {
1047         struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1048         int ret = -EAGAIN;
1049 
1050         if ((dscc4_loopback_check(dpriv) < 0))
1051                 goto err;
1052 
1053         if ((ret = hdlc_open(dev)))
1054                 goto err;
1055 
1056         /*
1057          * Due to various bugs, there is no way to reliably reset a
1058          * specific port (manufacturer's dependent special PCI #RST wiring
1059          * apart: it affects all ports). Thus the device goes in the best
1060          * silent mode possible at dscc4_close() time and simply claims to
1061          * be up if it's opened again. It still isn't possible to change
1062          * the HDLC configuration without rebooting but at least the ports
1063          * can be up/down ifconfig'ed without killing the host.
1064          */
1065         if (dpriv->flags & FakeReset) {
1066                 dpriv->flags &= ~FakeReset;
1067                 scc_patchl(0, PowerUp, dpriv, dev, CCR0);
1068                 scc_patchl(0, 0x00050000, dpriv, dev, CCR2);
1069                 scc_writel(EventsMask, dpriv, dev, IMR);
1070                 netdev_info(dev, "up again\n");
1071                 goto done;
1072         }
1073 
1074         /* IDT+IDR during XPR */
1075         dpriv->flags = NeedIDR | NeedIDT;
1076 
1077         scc_patchl(0, PowerUp | Vis, dpriv, dev, CCR0);
1078 
1079         /*
1080          * The following is a bit paranoid...
1081          *
1082          * NB: the datasheet "...CEC will stay active if the SCC is in
1083          * power-down mode or..." and CCR2.RAC = 1 are two different
1084          * situations.
1085          */
1086         if (scc_readl_star(dpriv, dev) & SccBusy) {
1087                 netdev_err(dev, "busy - try later\n");
1088                 ret = -EAGAIN;
1089                 goto err_out;
1090         } else
1091                 netdev_info(dev, "available - good\n");
1092 
1093         scc_writel(EventsMask, dpriv, dev, IMR);
1094 
1095         /* Posted write is flushed in the wait_ack loop */
1096         scc_writel(TxSccRes | RxSccRes, dpriv, dev, CMDR);
1097 
1098         if ((ret = dscc4_wait_ack_cec(dpriv, dev, "Cec")) < 0)
1099                 goto err_disable_scc_events;
1100 
1101         /*
1102          * I would expect XPR near CE completion (before ? after ?).
1103          * At worst, this code won't see a late XPR and people
1104          * will have to re-issue an ifconfig (this is harmless).
1105          * WARNING, a really missing XPR usually means a hardware
1106          * reset is needed. Suggestions anyone ?
1107          */
1108         if ((ret = dscc4_xpr_ack(dpriv)) < 0) {
1109                 pr_err("XPR timeout\n");
1110                 goto err_disable_scc_events;
1111         }
1112         
1113         if (debug > 2)
1114                 dscc4_tx_print(dev, dpriv, "Open");
1115 
1116 done:
1117         netif_start_queue(dev);
1118 
1119         init_timer(&dpriv->timer);
1120         dpriv->timer.expires = jiffies + 10*HZ;
1121         dpriv->timer.data = (unsigned long)dev;
1122         dpriv->timer.function = dscc4_timer;
1123         add_timer(&dpriv->timer);
1124         netif_carrier_on(dev);
1125 
1126         return 0;
1127 
1128 err_disable_scc_events:
1129         scc_writel(0xffffffff, dpriv, dev, IMR);
1130         scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1131 err_out:
1132         hdlc_close(dev);
1133 err:
1134         return ret;
1135 }
1136 
1137 #ifdef DSCC4_POLLING
1138 static int dscc4_tx_poll(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1139 {
1140         /* FIXME: it's gonna be easy (TM), for sure */
1141 }
1142 #endif /* DSCC4_POLLING */
1143 
1144 static netdev_tx_t dscc4_start_xmit(struct sk_buff *skb,
1145                                           struct net_device *dev)
1146 {
1147         struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1148         struct dscc4_pci_priv *ppriv = dpriv->pci_priv;
1149         struct TxFD *tx_fd;
1150         int next;
1151 
1152         next = dpriv->tx_current%TX_RING_SIZE;
1153         dpriv->tx_skbuff[next] = skb;
1154         tx_fd = dpriv->tx_fd + next;
1155         tx_fd->state = FrameEnd | TO_STATE_TX(skb->len);
1156         tx_fd->data = cpu_to_le32(pci_map_single(ppriv->pdev, skb->data, skb->len,
1157                                      PCI_DMA_TODEVICE));
1158         tx_fd->complete = 0x00000000;
1159         tx_fd->jiffies = jiffies;
1160         mb();
1161 
1162 #ifdef DSCC4_POLLING
1163         spin_lock(&dpriv->lock);
1164         while (dscc4_tx_poll(dpriv, dev));
1165         spin_unlock(&dpriv->lock);
1166 #endif
1167 
1168         if (debug > 2)
1169                 dscc4_tx_print(dev, dpriv, "Xmit");
1170         /* To be cleaned(unsigned int)/optimized. Later, ok ? */
1171         if (!((++dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE))
1172                 netif_stop_queue(dev);
1173 
1174         if (dscc4_tx_quiescent(dpriv, dev))
1175                 dscc4_do_tx(dpriv, dev);
1176 
1177         return NETDEV_TX_OK;
1178 }
1179 
1180 static int dscc4_close(struct net_device *dev)
1181 {
1182         struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1183 
1184         del_timer_sync(&dpriv->timer);
1185         netif_stop_queue(dev);
1186 
1187         scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1188         scc_patchl(0x00050000, 0, dpriv, dev, CCR2);
1189         scc_writel(0xffffffff, dpriv, dev, IMR);
1190 
1191         dpriv->flags |= FakeReset;
1192 
1193         hdlc_close(dev);
1194 
1195         return 0;
1196 }
1197 
1198 static inline int dscc4_check_clock_ability(int port)
1199 {
1200         int ret = 0;
1201 
1202 #ifdef CONFIG_DSCC4_PCISYNC
1203         if (port >= 2)
1204                 ret = -1;
1205 #endif
1206         return ret;
1207 }
1208 
1209 /*
1210  * DS1 p.137: "There are a total of 13 different clocking modes..."
1211  *                                  ^^
1212  * Design choices:
1213  * - by default, assume a clock is provided on pin RxClk/TxClk (clock mode 0a).
1214  *   Clock mode 3b _should_ work but the testing seems to make this point
1215  *   dubious (DIY testing requires setting CCR0 at 0x00000033).
1216  *   This is supposed to provide least surprise "DTE like" behavior.
1217  * - if line rate is specified, clocks are assumed to be locally generated.
1218  *   A quartz must be available (on pin XTAL1). Modes 6b/7b are used. Choosing
1219  *   between these it automagically done according on the required frequency
1220  *   scaling. Of course some rounding may take place.
1221  * - no high speed mode (40Mb/s). May be trivial to do but I don't have an
1222  *   appropriate external clocking device for testing.
1223  * - no time-slot/clock mode 5: shameless laziness.
1224  *
1225  * The clock signals wiring can be (is ?) manufacturer dependent. Good luck.
1226  *
1227  * BIG FAT WARNING: if the device isn't provided enough clocking signal, it
1228  * won't pass the init sequence. For example, straight back-to-back DTE without
1229  * external clock will fail when dscc4_open() (<- 'ifconfig hdlcx xxx') is
1230  * called.
1231  *
1232  * Typos lurk in datasheet (missing divier in clock mode 7a figure 51 p.153
1233  * DS0 for example)
1234  *
1235  * Clock mode related bits of CCR0:
1236  *     +------------ TOE: output TxClk (0b/2b/3a/3b/6b/7a/7b only)
1237  *     | +---------- SSEL: sub-mode select 0 -> a, 1 -> b
1238  *     | | +-------- High Speed: say 0
1239  *     | | | +-+-+-- Clock Mode: 0..7
1240  *     | | | | | |
1241  * -+-+-+-+-+-+-+-+
1242  * x|x|5|4|3|2|1|0| lower bits
1243  *
1244  * Division factor of BRR: k = (N+1)x2^M (total divider = 16xk in mode 6b)
1245  *            +-+-+-+------------------ M (0..15)
1246  *            | | | |     +-+-+-+-+-+-- N (0..63)
1247  *    0 0 0 0 | | | | 0 0 | | | | | |
1248  * ...-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1249  *    f|e|d|c|b|a|9|8|7|6|5|4|3|2|1|0| lower bits
1250  *
1251  */
1252 static int dscc4_set_clock(struct net_device *dev, u32 *bps, u32 *state)
1253 {
1254         struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1255         int ret = -1;
1256         u32 brr;
1257 
1258         *state &= ~Ccr0ClockMask;
1259         if (*bps) { /* Clock generated - required for DCE */
1260                 u32 n = 0, m = 0, divider;
1261                 int xtal;
1262 
1263                 xtal = dpriv->pci_priv->xtal_hz;
1264                 if (!xtal)
1265                         goto done;
1266                 if (dscc4_check_clock_ability(dpriv->dev_id) < 0)
1267                         goto done;
1268                 divider = xtal / *bps;
1269                 if (divider > BRR_DIVIDER_MAX) {
1270                         divider >>= 4;
1271                         *state |= 0x00000036; /* Clock mode 6b (BRG/16) */
1272                 } else
1273                         *state |= 0x00000037; /* Clock mode 7b (BRG) */
1274                 if (divider >> 22) {
1275                         n = 63;
1276                         m = 15;
1277                 } else if (divider) {
1278                         /* Extraction of the 6 highest weighted bits */
1279                         m = 0;
1280                         while (0xffffffc0 & divider) {
1281                                 m++;
1282                                 divider >>= 1;
1283                         }
1284                         n = divider;
1285                 }
1286                 brr = (m << 8) | n;
1287                 divider = n << m;
1288                 if (!(*state & 0x00000001)) /* ?b mode mask => clock mode 6b */
1289                         divider <<= 4;
1290                 *bps = xtal / divider;
1291         } else {
1292                 /*
1293                  * External clock - DTE
1294                  * "state" already reflects Clock mode 0a (CCR0 = 0xzzzzzz00).
1295                  * Nothing more to be done
1296                  */
1297                 brr = 0;
1298         }
1299         scc_writel(brr, dpriv, dev, BRR);
1300         ret = 0;
1301 done:
1302         return ret;
1303 }
1304 
1305 static int dscc4_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1306 {
1307         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1308         struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1309         const size_t size = sizeof(dpriv->settings);
1310         int ret = 0;
1311 
1312         if (dev->flags & IFF_UP)
1313                 return -EBUSY;
1314 
1315         if (cmd != SIOCWANDEV)
1316                 return -EOPNOTSUPP;
1317 
1318         switch(ifr->ifr_settings.type) {
1319         case IF_GET_IFACE:
1320                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1321                 if (ifr->ifr_settings.size < size) {
1322                         ifr->ifr_settings.size = size; /* data size wanted */
1323                         return -ENOBUFS;
1324                 }
1325                 if (copy_to_user(line, &dpriv->settings, size))
1326                         return -EFAULT;
1327                 break;
1328 
1329         case IF_IFACE_SYNC_SERIAL:
1330                 if (!capable(CAP_NET_ADMIN))
1331                         return -EPERM;
1332 
1333                 if (dpriv->flags & FakeReset) {
1334                         netdev_info(dev, "please reset the device before this command\n");
1335                         return -EPERM;
1336                 }
1337                 if (copy_from_user(&dpriv->settings, line, size))
1338                         return -EFAULT;
1339                 ret = dscc4_set_iface(dpriv, dev);
1340                 break;
1341 
1342         default:
1343                 ret = hdlc_ioctl(dev, ifr, cmd);
1344                 break;
1345         }
1346 
1347         return ret;
1348 }
1349 
1350 static int dscc4_match(const struct thingie *p, int value)
1351 {
1352         int i;
1353 
1354         for (i = 0; p[i].define != -1; i++) {
1355                 if (value == p[i].define)
1356                         break;
1357         }
1358         if (p[i].define == -1)
1359                 return -1;
1360         else
1361                 return i;
1362 }
1363 
1364 static int dscc4_clock_setting(struct dscc4_dev_priv *dpriv,
1365                                struct net_device *dev)
1366 {
1367         sync_serial_settings *settings = &dpriv->settings;
1368         int ret = -EOPNOTSUPP;
1369         u32 bps, state;
1370 
1371         bps = settings->clock_rate;
1372         state = scc_readl(dpriv, CCR0);
1373         if (dscc4_set_clock(dev, &bps, &state) < 0)
1374                 goto done;
1375         if (bps) { /* DCE */
1376                 printk(KERN_DEBUG "%s: generated RxClk (DCE)\n", dev->name);
1377                 if (settings->clock_rate != bps) {
1378                         printk(KERN_DEBUG "%s: clock adjusted (%08d -> %08d)\n",
1379                                 dev->name, settings->clock_rate, bps);
1380                         settings->clock_rate = bps;
1381                 }
1382         } else { /* DTE */
1383                 state |= PowerUp | Vis;
1384                 printk(KERN_DEBUG "%s: external RxClk (DTE)\n", dev->name);
1385         }
1386         scc_writel(state, dpriv, dev, CCR0);
1387         ret = 0;
1388 done:
1389         return ret;
1390 }
1391 
1392 static int dscc4_encoding_setting(struct dscc4_dev_priv *dpriv,
1393                                   struct net_device *dev)
1394 {
1395         static const struct thingie encoding[] = {
1396                 { ENCODING_NRZ,         0x00000000 },
1397                 { ENCODING_NRZI,        0x00200000 },
1398                 { ENCODING_FM_MARK,     0x00400000 },
1399                 { ENCODING_FM_SPACE,    0x00500000 },
1400                 { ENCODING_MANCHESTER,  0x00600000 },
1401                 { -1,                   0}
1402         };
1403         int i, ret = 0;
1404 
1405         i = dscc4_match(encoding, dpriv->encoding);
1406         if (i >= 0)
1407                 scc_patchl(EncodingMask, encoding[i].bits, dpriv, dev, CCR0);
1408         else
1409                 ret = -EOPNOTSUPP;
1410         return ret;
1411 }
1412 
1413 static int dscc4_loopback_setting(struct dscc4_dev_priv *dpriv,
1414                                   struct net_device *dev)
1415 {
1416         sync_serial_settings *settings = &dpriv->settings;
1417         u32 state;
1418 
1419         state = scc_readl(dpriv, CCR1);
1420         if (settings->loopback) {
1421                 printk(KERN_DEBUG "%s: loopback\n", dev->name);
1422                 state |= 0x00000100;
1423         } else {
1424                 printk(KERN_DEBUG "%s: normal\n", dev->name);
1425                 state &= ~0x00000100;
1426         }
1427         scc_writel(state, dpriv, dev, CCR1);
1428         return 0;
1429 }
1430 
1431 static int dscc4_crc_setting(struct dscc4_dev_priv *dpriv,
1432                              struct net_device *dev)
1433 {
1434         static const struct thingie crc[] = {
1435                 { PARITY_CRC16_PR0_CCITT,       0x00000010 },
1436                 { PARITY_CRC16_PR1_CCITT,       0x00000000 },
1437                 { PARITY_CRC32_PR0_CCITT,       0x00000011 },
1438                 { PARITY_CRC32_PR1_CCITT,       0x00000001 }
1439         };
1440         int i, ret = 0;
1441 
1442         i = dscc4_match(crc, dpriv->parity);
1443         if (i >= 0)
1444                 scc_patchl(CrcMask, crc[i].bits, dpriv, dev, CCR1);
1445         else
1446                 ret = -EOPNOTSUPP;
1447         return ret;
1448 }
1449 
1450 static int dscc4_set_iface(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1451 {
1452         struct {
1453                 int (*action)(struct dscc4_dev_priv *, struct net_device *);
1454         } *p, do_setting[] = {
1455                 { dscc4_encoding_setting },
1456                 { dscc4_clock_setting },
1457                 { dscc4_loopback_setting },
1458                 { dscc4_crc_setting },
1459                 { NULL }
1460         };
1461         int ret = 0;
1462 
1463         for (p = do_setting; p->action; p++) {
1464                 if ((ret = p->action(dpriv, dev)) < 0)
1465                         break;
1466         }
1467         return ret;
1468 }
1469 
1470 static irqreturn_t dscc4_irq(int irq, void *token)
1471 {
1472         struct dscc4_dev_priv *root = token;
1473         struct dscc4_pci_priv *priv;
1474         struct net_device *dev;
1475         void __iomem *ioaddr;
1476         u32 state;
1477         unsigned long flags;
1478         int i, handled = 1;
1479 
1480         priv = root->pci_priv;
1481         dev = dscc4_to_dev(root);
1482 
1483         spin_lock_irqsave(&priv->lock, flags);
1484 
1485         ioaddr = root->base_addr;
1486 
1487         state = readl(ioaddr + GSTAR);
1488         if (!state) {
1489                 handled = 0;
1490                 goto out;
1491         }
1492         if (debug > 3)
1493                 printk(KERN_DEBUG "%s: GSTAR = 0x%08x\n", DRV_NAME, state);
1494         writel(state, ioaddr + GSTAR);
1495 
1496         if (state & Arf) {
1497                 netdev_err(dev, "failure (Arf). Harass the maintainer\n");
1498                 goto out;
1499         }
1500         state &= ~ArAck;
1501         if (state & Cfg) {
1502                 if (debug > 0)
1503                         printk(KERN_DEBUG "%s: CfgIV\n", DRV_NAME);
1504                 if (priv->iqcfg[priv->cfg_cur++%IRQ_RING_SIZE] & cpu_to_le32(Arf))
1505                         netdev_err(dev, "CFG failed\n");
1506                 if (!(state &= ~Cfg))
1507                         goto out;
1508         }
1509         if (state & RxEvt) {
1510                 i = dev_per_card - 1;
1511                 do {
1512                         dscc4_rx_irq(priv, root + i);
1513                 } while (--i >= 0);
1514                 state &= ~RxEvt;
1515         }
1516         if (state & TxEvt) {
1517                 i = dev_per_card - 1;
1518                 do {
1519                         dscc4_tx_irq(priv, root + i);
1520                 } while (--i >= 0);
1521                 state &= ~TxEvt;
1522         }
1523 out:
1524         spin_unlock_irqrestore(&priv->lock, flags);
1525         return IRQ_RETVAL(handled);
1526 }
1527 
1528 static void dscc4_tx_irq(struct dscc4_pci_priv *ppriv,
1529                                 struct dscc4_dev_priv *dpriv)
1530 {
1531         struct net_device *dev = dscc4_to_dev(dpriv);
1532         u32 state;
1533         int cur, loop = 0;
1534 
1535 try:
1536         cur = dpriv->iqtx_current%IRQ_RING_SIZE;
1537         state = le32_to_cpu(dpriv->iqtx[cur]);
1538         if (!state) {
1539                 if (debug > 4)
1540                         printk(KERN_DEBUG "%s: Tx ISR = 0x%08x\n", dev->name,
1541                                state);
1542                 if ((debug > 1) && (loop > 1))
1543                         printk(KERN_DEBUG "%s: Tx irq loop=%d\n", dev->name, loop);
1544                 if (loop && netif_queue_stopped(dev))
1545                         if ((dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE)
1546                                 netif_wake_queue(dev);
1547 
1548                 if (netif_running(dev) && dscc4_tx_quiescent(dpriv, dev) &&
1549                     !dscc4_tx_done(dpriv))
1550                                 dscc4_do_tx(dpriv, dev);
1551                 return;
1552         }
1553         loop++;
1554         dpriv->iqtx[cur] = 0;
1555         dpriv->iqtx_current++;
1556 
1557         if (state_check(state, dpriv, dev, "Tx") < 0)
1558                 return;
1559 
1560         if (state & SccEvt) {
1561                 if (state & Alls) {
1562                         struct sk_buff *skb;
1563                         struct TxFD *tx_fd;
1564 
1565                         if (debug > 2)
1566                                 dscc4_tx_print(dev, dpriv, "Alls");
1567                         /*
1568                          * DataComplete can't be trusted for Tx completion.
1569                          * Cf errata DS5 p.8
1570                          */
1571                         cur = dpriv->tx_dirty%TX_RING_SIZE;
1572                         tx_fd = dpriv->tx_fd + cur;
1573                         skb = dpriv->tx_skbuff[cur];
1574                         if (skb) {
1575                                 pci_unmap_single(ppriv->pdev, le32_to_cpu(tx_fd->data),
1576                                                  skb->len, PCI_DMA_TODEVICE);
1577                                 if (tx_fd->state & FrameEnd) {
1578                                         dev->stats.tx_packets++;
1579                                         dev->stats.tx_bytes += skb->len;
1580                                 }
1581                                 dev_kfree_skb_irq(skb);
1582                                 dpriv->tx_skbuff[cur] = NULL;
1583                                 ++dpriv->tx_dirty;
1584                         } else {
1585                                 if (debug > 1)
1586                                         netdev_err(dev, "Tx: NULL skb %d\n",
1587                                                    cur);
1588                         }
1589                         /*
1590                          * If the driver ends sending crap on the wire, it
1591                          * will be way easier to diagnose than the (not so)
1592                          * random freeze induced by null sized tx frames.
1593                          */
1594                         tx_fd->data = tx_fd->next;
1595                         tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
1596                         tx_fd->complete = 0x00000000;
1597                         tx_fd->jiffies = 0;
1598 
1599                         if (!(state &= ~Alls))
1600                                 goto try;
1601                 }
1602                 /*
1603                  * Transmit Data Underrun
1604                  */
1605                 if (state & Xdu) {
1606                         netdev_err(dev, "Tx Data Underrun. Ask maintainer\n");
1607                         dpriv->flags = NeedIDT;
1608                         /* Tx reset */
1609                         writel(MTFi | Rdt,
1610                                dpriv->base_addr + 0x0c*dpriv->dev_id + CH0CFG);
1611                         writel(Action, dpriv->base_addr + GCMDR);
1612                         return;
1613                 }
1614                 if (state & Cts) {
1615                         netdev_info(dev, "CTS transition\n");
1616                         if (!(state &= ~Cts)) /* DEBUG */
1617                                 goto try;
1618                 }
1619                 if (state & Xmr) {
1620                         /* Frame needs to be sent again - FIXME */
1621                         netdev_err(dev, "Tx ReTx. Ask maintainer\n");
1622                         if (!(state &= ~Xmr)) /* DEBUG */
1623                                 goto try;
1624                 }
1625                 if (state & Xpr) {
1626                         void __iomem *scc_addr;
1627                         unsigned long ring;
1628                         unsigned int i;
1629 
1630                         /*
1631                          * - the busy condition happens (sometimes);
1632                          * - it doesn't seem to make the handler unreliable.
1633                          */
1634                         for (i = 1; i; i <<= 1) {
1635                                 if (!(scc_readl_star(dpriv, dev) & SccBusy))
1636                                         break;
1637                         }
1638                         if (!i)
1639                                 netdev_info(dev, "busy in irq\n");
1640 
1641                         scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
1642                         /* Keep this order: IDT before IDR */
1643                         if (dpriv->flags & NeedIDT) {
1644                                 if (debug > 2)
1645                                         dscc4_tx_print(dev, dpriv, "Xpr");
1646                                 ring = dpriv->tx_fd_dma +
1647                                        (dpriv->tx_dirty%TX_RING_SIZE)*
1648                                        sizeof(struct TxFD);
1649                                 writel(ring, scc_addr + CH0BTDA);
1650                                 dscc4_do_tx(dpriv, dev);
1651                                 writel(MTFi | Idt, scc_addr + CH0CFG);
1652                                 if (dscc4_do_action(dev, "IDT") < 0)
1653                                         goto err_xpr;
1654                                 dpriv->flags &= ~NeedIDT;
1655                         }
1656                         if (dpriv->flags & NeedIDR) {
1657                                 ring = dpriv->rx_fd_dma +
1658                                        (dpriv->rx_current%RX_RING_SIZE)*
1659                                        sizeof(struct RxFD);
1660                                 writel(ring, scc_addr + CH0BRDA);
1661                                 dscc4_rx_update(dpriv, dev);
1662                                 writel(MTFi | Idr, scc_addr + CH0CFG);
1663                                 if (dscc4_do_action(dev, "IDR") < 0)
1664                                         goto err_xpr;
1665                                 dpriv->flags &= ~NeedIDR;
1666                                 smp_wmb();
1667                                 /* Activate receiver and misc */
1668                                 scc_writel(0x08050008, dpriv, dev, CCR2);
1669                         }
1670                 err_xpr:
1671                         if (!(state &= ~Xpr))
1672                                 goto try;
1673                 }
1674                 if (state & Cd) {
1675                         if (debug > 0)
1676                                 netdev_info(dev, "CD transition\n");
1677                         if (!(state &= ~Cd)) /* DEBUG */
1678                                 goto try;
1679                 }
1680         } else { /* ! SccEvt */
1681                 if (state & Hi) {
1682 #ifdef DSCC4_POLLING
1683                         while (!dscc4_tx_poll(dpriv, dev));
1684 #endif
1685                         netdev_info(dev, "Tx Hi\n");
1686                         state &= ~Hi;
1687                 }
1688                 if (state & Err) {
1689                         netdev_info(dev, "Tx ERR\n");
1690                         dev->stats.tx_errors++;
1691                         state &= ~Err;
1692                 }
1693         }
1694         goto try;
1695 }
1696 
1697 static void dscc4_rx_irq(struct dscc4_pci_priv *priv,
1698                                     struct dscc4_dev_priv *dpriv)
1699 {
1700         struct net_device *dev = dscc4_to_dev(dpriv);
1701         u32 state;
1702         int cur;
1703 
1704 try:
1705         cur = dpriv->iqrx_current%IRQ_RING_SIZE;
1706         state = le32_to_cpu(dpriv->iqrx[cur]);
1707         if (!state)
1708                 return;
1709         dpriv->iqrx[cur] = 0;
1710         dpriv->iqrx_current++;
1711 
1712         if (state_check(state, dpriv, dev, "Rx") < 0)
1713                 return;
1714 
1715         if (!(state & SccEvt)){
1716                 struct RxFD *rx_fd;
1717 
1718                 if (debug > 4)
1719                         printk(KERN_DEBUG "%s: Rx ISR = 0x%08x\n", dev->name,
1720                                state);
1721                 state &= 0x00ffffff;
1722                 if (state & Err) { /* Hold or reset */
1723                         printk(KERN_DEBUG "%s: Rx ERR\n", dev->name);
1724                         cur = dpriv->rx_current%RX_RING_SIZE;
1725                         rx_fd = dpriv->rx_fd + cur;
1726                         /*
1727                          * Presume we're not facing a DMAC receiver reset.
1728                          * As We use the rx size-filtering feature of the
1729                          * DSCC4, the beginning of a new frame is waiting in
1730                          * the rx fifo. I bet a Receive Data Overflow will
1731                          * happen most of time but let's try and avoid it.
1732                          * Btw (as for RDO) if one experiences ERR whereas
1733                          * the system looks rather idle, there may be a
1734                          * problem with latency. In this case, increasing
1735                          * RX_RING_SIZE may help.
1736                          */
1737                         //while (dpriv->rx_needs_refill) {
1738                                 while (!(rx_fd->state1 & Hold)) {
1739                                         rx_fd++;
1740                                         cur++;
1741                                         if (!(cur = cur%RX_RING_SIZE))
1742                                                 rx_fd = dpriv->rx_fd;
1743                                 }
1744                                 //dpriv->rx_needs_refill--;
1745                                 try_get_rx_skb(dpriv, dev);
1746                                 if (!rx_fd->data)
1747                                         goto try;
1748                                 rx_fd->state1 &= ~Hold;
1749                                 rx_fd->state2 = 0x00000000;
1750                                 rx_fd->end = cpu_to_le32(0xbabeface);
1751                         //}
1752                         goto try;
1753                 }
1754                 if (state & Fi) {
1755                         dscc4_rx_skb(dpriv, dev);
1756                         goto try;
1757                 }
1758                 if (state & Hi ) { /* HI bit */
1759                         netdev_info(dev, "Rx Hi\n");
1760                         state &= ~Hi;
1761                         goto try;
1762                 }
1763         } else { /* SccEvt */
1764                 if (debug > 1) {
1765                         //FIXME: verifier la presence de tous les evenements
1766                 static struct {
1767                         u32 mask;
1768                         const char *irq_name;
1769                 } evts[] = {
1770                         { 0x00008000, "TIN"},
1771                         { 0x00000020, "RSC"},
1772                         { 0x00000010, "PCE"},
1773                         { 0x00000008, "PLLA"},
1774                         { 0, NULL}
1775                 }, *evt;
1776 
1777                 for (evt = evts; evt->irq_name; evt++) {
1778                         if (state & evt->mask) {
1779                                         printk(KERN_DEBUG "%s: %s\n",
1780                                                 dev->name, evt->irq_name);
1781                                 if (!(state &= ~evt->mask))
1782                                         goto try;
1783                         }
1784                 }
1785                 } else {
1786                         if (!(state &= ~0x0000c03c))
1787                                 goto try;
1788                 }
1789                 if (state & Cts) {
1790                         netdev_info(dev, "CTS transition\n");
1791                         if (!(state &= ~Cts)) /* DEBUG */
1792                                 goto try;
1793                 }
1794                 /*
1795                  * Receive Data Overflow (FIXME: fscked)
1796                  */
1797                 if (state & Rdo) {
1798                         struct RxFD *rx_fd;
1799                         void __iomem *scc_addr;
1800                         int cur;
1801 
1802                         //if (debug)
1803                         //      dscc4_rx_dump(dpriv);
1804                         scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
1805 
1806                         scc_patchl(RxActivate, 0, dpriv, dev, CCR2);
1807                         /*
1808                          * This has no effect. Why ?
1809                          * ORed with TxSccRes, one sees the CFG ack (for
1810                          * the TX part only).
1811                          */
1812                         scc_writel(RxSccRes, dpriv, dev, CMDR);
1813                         dpriv->flags |= RdoSet;
1814 
1815                         /*
1816                          * Let's try and save something in the received data.
1817                          * rx_current must be incremented at least once to
1818                          * avoid HOLD in the BRDA-to-be-pointed desc.
1819                          */
1820                         do {
1821                                 cur = dpriv->rx_current++%RX_RING_SIZE;
1822                                 rx_fd = dpriv->rx_fd + cur;
1823                                 if (!(rx_fd->state2 & DataComplete))
1824                                         break;
1825                                 if (rx_fd->state2 & FrameAborted) {
1826                                         dev->stats.rx_over_errors++;
1827                                         rx_fd->state1 |= Hold;
1828                                         rx_fd->state2 = 0x00000000;
1829                                         rx_fd->end = cpu_to_le32(0xbabeface);
1830                                 } else
1831                                         dscc4_rx_skb(dpriv, dev);
1832                         } while (1);
1833 
1834                         if (debug > 0) {
1835                                 if (dpriv->flags & RdoSet)
1836                                         printk(KERN_DEBUG
1837                                                "%s: no RDO in Rx data\n", DRV_NAME);
1838                         }
1839 #ifdef DSCC4_RDO_EXPERIMENTAL_RECOVERY
1840                         /*
1841                          * FIXME: must the reset be this violent ?
1842                          */
1843 #warning "FIXME: CH0BRDA"
1844                         writel(dpriv->rx_fd_dma +
1845                                (dpriv->rx_current%RX_RING_SIZE)*
1846                                sizeof(struct RxFD), scc_addr + CH0BRDA);
1847                         writel(MTFi|Rdr|Idr, scc_addr + CH0CFG);
1848                         if (dscc4_do_action(dev, "RDR") < 0) {
1849                                 netdev_err(dev, "RDO recovery failed(RDR)\n");
1850                                 goto rdo_end;
1851                         }
1852                         writel(MTFi|Idr, scc_addr + CH0CFG);
1853                         if (dscc4_do_action(dev, "IDR") < 0) {
1854                                 netdev_err(dev, "RDO recovery failed(IDR)\n");
1855                                 goto rdo_end;
1856                         }
1857                 rdo_end:
1858 #endif
1859                         scc_patchl(0, RxActivate, dpriv, dev, CCR2);
1860                         goto try;
1861                 }
1862                 if (state & Cd) {
1863                         netdev_info(dev, "CD transition\n");
1864                         if (!(state &= ~Cd)) /* DEBUG */
1865                                 goto try;
1866                 }
1867                 if (state & Flex) {
1868                         printk(KERN_DEBUG "%s: Flex. Ttttt...\n", DRV_NAME);
1869                         if (!(state &= ~Flex))
1870                                 goto try;
1871                 }
1872         }
1873 }
1874 
1875 /*
1876  * I had expected the following to work for the first descriptor
1877  * (tx_fd->state = 0xc0000000)
1878  * - Hold=1 (don't try and branch to the next descripto);
1879  * - No=0 (I want an empty data section, i.e. size=0);
1880  * - Fe=1 (required by No=0 or we got an Err irq and must reset).
1881  * It failed and locked solid. Thus the introduction of a dummy skb.
1882  * Problem is acknowledged in errata sheet DS5. Joy :o/
1883  */
1884 static struct sk_buff *dscc4_init_dummy_skb(struct dscc4_dev_priv *dpriv)
1885 {
1886         struct sk_buff *skb;
1887 
1888         skb = dev_alloc_skb(DUMMY_SKB_SIZE);
1889         if (skb) {
1890                 int last = dpriv->tx_dirty%TX_RING_SIZE;
1891                 struct TxFD *tx_fd = dpriv->tx_fd + last;
1892 
1893                 skb->len = DUMMY_SKB_SIZE;
1894                 skb_copy_to_linear_data(skb, version,
1895                                         strlen(version) % DUMMY_SKB_SIZE);
1896                 tx_fd->state = FrameEnd | TO_STATE_TX(DUMMY_SKB_SIZE);
1897                 tx_fd->data = cpu_to_le32(pci_map_single(dpriv->pci_priv->pdev,
1898                                              skb->data, DUMMY_SKB_SIZE,
1899                                              PCI_DMA_TODEVICE));
1900                 dpriv->tx_skbuff[last] = skb;
1901         }
1902         return skb;
1903 }
1904 
1905 static int dscc4_init_ring(struct net_device *dev)
1906 {
1907         struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1908         struct pci_dev *pdev = dpriv->pci_priv->pdev;
1909         struct TxFD *tx_fd;
1910         struct RxFD *rx_fd;
1911         void *ring;
1912         int i;
1913 
1914         ring = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &dpriv->rx_fd_dma);
1915         if (!ring)
1916                 goto err_out;
1917         dpriv->rx_fd = rx_fd = (struct RxFD *) ring;
1918 
1919         ring = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &dpriv->tx_fd_dma);
1920         if (!ring)
1921                 goto err_free_dma_rx;
1922         dpriv->tx_fd = tx_fd = (struct TxFD *) ring;
1923 
1924         memset(dpriv->tx_skbuff, 0, sizeof(struct sk_buff *)*TX_RING_SIZE);
1925         dpriv->tx_dirty = 0xffffffff;
1926         i = dpriv->tx_current = 0;
1927         do {
1928                 tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
1929                 tx_fd->complete = 0x00000000;
1930                 /* FIXME: NULL should be ok - to be tried */
1931                 tx_fd->data = cpu_to_le32(dpriv->tx_fd_dma);
1932                 (tx_fd++)->next = cpu_to_le32(dpriv->tx_fd_dma +
1933                                         (++i%TX_RING_SIZE)*sizeof(*tx_fd));
1934         } while (i < TX_RING_SIZE);
1935 
1936         if (!dscc4_init_dummy_skb(dpriv))
1937                 goto err_free_dma_tx;
1938 
1939         memset(dpriv->rx_skbuff, 0, sizeof(struct sk_buff *)*RX_RING_SIZE);
1940         i = dpriv->rx_dirty = dpriv->rx_current = 0;
1941         do {
1942                 /* size set by the host. Multiple of 4 bytes please */
1943                 rx_fd->state1 = HiDesc;
1944                 rx_fd->state2 = 0x00000000;
1945                 rx_fd->end = cpu_to_le32(0xbabeface);
1946                 rx_fd->state1 |= TO_STATE_RX(HDLC_MAX_MRU);
1947                 // FIXME: return value verifiee mais traitement suspect
1948                 if (try_get_rx_skb(dpriv, dev) >= 0)
1949                         dpriv->rx_dirty++;
1950                 (rx_fd++)->next = cpu_to_le32(dpriv->rx_fd_dma +
1951                                         (++i%RX_RING_SIZE)*sizeof(*rx_fd));
1952         } while (i < RX_RING_SIZE);
1953 
1954         return 0;
1955 
1956 err_free_dma_tx:
1957         pci_free_consistent(pdev, TX_TOTAL_SIZE, ring, dpriv->tx_fd_dma);
1958 err_free_dma_rx:
1959         pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
1960 err_out:
1961         return -ENOMEM;
1962 }
1963 
1964 static void dscc4_remove_one(struct pci_dev *pdev)
1965 {
1966         struct dscc4_pci_priv *ppriv;
1967         struct dscc4_dev_priv *root;
1968         void __iomem *ioaddr;
1969         int i;
1970 
1971         ppriv = pci_get_drvdata(pdev);
1972         root = ppriv->root;
1973 
1974         ioaddr = root->base_addr;
1975 
1976         dscc4_pci_reset(pdev, ioaddr);
1977 
1978         free_irq(pdev->irq, root);
1979         pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), ppriv->iqcfg,
1980                             ppriv->iqcfg_dma);
1981         for (i = 0; i < dev_per_card; i++) {
1982                 struct dscc4_dev_priv *dpriv = root + i;
1983 
1984                 dscc4_release_ring(dpriv);
1985                 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
1986                                     dpriv->iqrx, dpriv->iqrx_dma);
1987                 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
1988                                     dpriv->iqtx, dpriv->iqtx_dma);
1989         }
1990 
1991         dscc4_free1(pdev);
1992 
1993         iounmap(ioaddr);
1994 
1995         pci_release_region(pdev, 1);
1996         pci_release_region(pdev, 0);
1997 
1998         pci_disable_device(pdev);
1999 }
2000 
2001 static int dscc4_hdlc_attach(struct net_device *dev, unsigned short encoding,
2002         unsigned short parity)
2003 {
2004         struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
2005 
2006         if (encoding != ENCODING_NRZ &&
2007             encoding != ENCODING_NRZI &&
2008             encoding != ENCODING_FM_MARK &&
2009             encoding != ENCODING_FM_SPACE &&
2010             encoding != ENCODING_MANCHESTER)
2011                 return -EINVAL;
2012 
2013         if (parity != PARITY_NONE &&
2014             parity != PARITY_CRC16_PR0_CCITT &&
2015             parity != PARITY_CRC16_PR1_CCITT &&
2016             parity != PARITY_CRC32_PR0_CCITT &&
2017             parity != PARITY_CRC32_PR1_CCITT)
2018                 return -EINVAL;
2019 
2020         dpriv->encoding = encoding;
2021         dpriv->parity = parity;
2022         return 0;
2023 }
2024 
2025 #ifndef MODULE
2026 static int __init dscc4_setup(char *str)
2027 {
2028         int *args[] = { &debug, &quartz, NULL }, **p = args;
2029 
2030         while (*p && (get_option(&str, *p) == 2))
2031                 p++;
2032         return 1;
2033 }
2034 
2035 __setup("dscc4.setup=", dscc4_setup);
2036 #endif
2037 
2038 static const struct pci_device_id dscc4_pci_tbl[] = {
2039         { PCI_VENDOR_ID_SIEMENS, PCI_DEVICE_ID_SIEMENS_DSCC4,
2040                 PCI_ANY_ID, PCI_ANY_ID, },
2041         { 0,}
2042 };
2043 MODULE_DEVICE_TABLE(pci, dscc4_pci_tbl);
2044 
2045 static struct pci_driver dscc4_driver = {
2046         .name           = DRV_NAME,
2047         .id_table       = dscc4_pci_tbl,
2048         .probe          = dscc4_init_one,
2049         .remove         = dscc4_remove_one,
2050 };
2051 
2052 module_pci_driver(dscc4_driver);
2053 

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