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Linux/drivers/net/usb/r8152.c

  1 /*
  2  *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
  3  *
  4  * This program is free software; you can redistribute it and/or
  5  * modify it under the terms of the GNU General Public License
  6  * version 2 as published by the Free Software Foundation.
  7  *
  8  */
  9 
 10 #include <linux/signal.h>
 11 #include <linux/slab.h>
 12 #include <linux/module.h>
 13 #include <linux/netdevice.h>
 14 #include <linux/etherdevice.h>
 15 #include <linux/mii.h>
 16 #include <linux/ethtool.h>
 17 #include <linux/usb.h>
 18 #include <linux/crc32.h>
 19 #include <linux/if_vlan.h>
 20 #include <linux/uaccess.h>
 21 #include <linux/list.h>
 22 #include <linux/ip.h>
 23 #include <linux/ipv6.h>
 24 
 25 /* Version Information */
 26 #define DRIVER_VERSION "v1.04.0 (2014/01/15)"
 27 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
 28 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
 29 #define MODULENAME "r8152"
 30 
 31 #define R8152_PHY_ID            32
 32 
 33 #define PLA_IDR                 0xc000
 34 #define PLA_RCR                 0xc010
 35 #define PLA_RMS                 0xc016
 36 #define PLA_RXFIFO_CTRL0        0xc0a0
 37 #define PLA_RXFIFO_CTRL1        0xc0a4
 38 #define PLA_RXFIFO_CTRL2        0xc0a8
 39 #define PLA_FMC                 0xc0b4
 40 #define PLA_CFG_WOL             0xc0b6
 41 #define PLA_TEREDO_CFG          0xc0bc
 42 #define PLA_MAR                 0xcd00
 43 #define PLA_BACKUP              0xd000
 44 #define PAL_BDC_CR              0xd1a0
 45 #define PLA_TEREDO_TIMER        0xd2cc
 46 #define PLA_REALWOW_TIMER       0xd2e8
 47 #define PLA_LEDSEL              0xdd90
 48 #define PLA_LED_FEATURE         0xdd92
 49 #define PLA_PHYAR               0xde00
 50 #define PLA_BOOT_CTRL           0xe004
 51 #define PLA_GPHY_INTR_IMR       0xe022
 52 #define PLA_EEE_CR              0xe040
 53 #define PLA_EEEP_CR             0xe080
 54 #define PLA_MAC_PWR_CTRL        0xe0c0
 55 #define PLA_MAC_PWR_CTRL2       0xe0ca
 56 #define PLA_MAC_PWR_CTRL3       0xe0cc
 57 #define PLA_MAC_PWR_CTRL4       0xe0ce
 58 #define PLA_WDT6_CTRL           0xe428
 59 #define PLA_TCR0                0xe610
 60 #define PLA_TCR1                0xe612
 61 #define PLA_TXFIFO_CTRL         0xe618
 62 #define PLA_RSTTELLY            0xe800
 63 #define PLA_CR                  0xe813
 64 #define PLA_CRWECR              0xe81c
 65 #define PLA_CONFIG5             0xe822
 66 #define PLA_PHY_PWR             0xe84c
 67 #define PLA_OOB_CTRL            0xe84f
 68 #define PLA_CPCR                0xe854
 69 #define PLA_MISC_0              0xe858
 70 #define PLA_MISC_1              0xe85a
 71 #define PLA_OCP_GPHY_BASE       0xe86c
 72 #define PLA_TELLYCNT            0xe890
 73 #define PLA_SFF_STS_7           0xe8de
 74 #define PLA_PHYSTATUS           0xe908
 75 #define PLA_BP_BA               0xfc26
 76 #define PLA_BP_0                0xfc28
 77 #define PLA_BP_1                0xfc2a
 78 #define PLA_BP_2                0xfc2c
 79 #define PLA_BP_3                0xfc2e
 80 #define PLA_BP_4                0xfc30
 81 #define PLA_BP_5                0xfc32
 82 #define PLA_BP_6                0xfc34
 83 #define PLA_BP_7                0xfc36
 84 #define PLA_BP_EN               0xfc38
 85 
 86 #define USB_U2P3_CTRL           0xb460
 87 #define USB_DEV_STAT            0xb808
 88 #define USB_USB_CTRL            0xd406
 89 #define USB_PHY_CTRL            0xd408
 90 #define USB_TX_AGG              0xd40a
 91 #define USB_RX_BUF_TH           0xd40c
 92 #define USB_USB_TIMER           0xd428
 93 #define USB_RX_EARLY_AGG        0xd42c
 94 #define USB_PM_CTRL_STATUS      0xd432
 95 #define USB_TX_DMA              0xd434
 96 #define USB_TOLERANCE           0xd490
 97 #define USB_LPM_CTRL            0xd41a
 98 #define USB_UPS_CTRL            0xd800
 99 #define USB_MISC_0              0xd81a
100 #define USB_POWER_CUT           0xd80a
101 #define USB_AFE_CTRL2           0xd824
102 #define USB_WDT11_CTRL          0xe43c
103 #define USB_BP_BA               0xfc26
104 #define USB_BP_0                0xfc28
105 #define USB_BP_1                0xfc2a
106 #define USB_BP_2                0xfc2c
107 #define USB_BP_3                0xfc2e
108 #define USB_BP_4                0xfc30
109 #define USB_BP_5                0xfc32
110 #define USB_BP_6                0xfc34
111 #define USB_BP_7                0xfc36
112 #define USB_BP_EN               0xfc38
113 
114 /* OCP Registers */
115 #define OCP_ALDPS_CONFIG        0x2010
116 #define OCP_EEE_CONFIG1         0x2080
117 #define OCP_EEE_CONFIG2         0x2092
118 #define OCP_EEE_CONFIG3         0x2094
119 #define OCP_BASE_MII            0xa400
120 #define OCP_EEE_AR              0xa41a
121 #define OCP_EEE_DATA            0xa41c
122 #define OCP_PHY_STATUS          0xa420
123 #define OCP_POWER_CFG           0xa430
124 #define OCP_EEE_CFG             0xa432
125 #define OCP_SRAM_ADDR           0xa436
126 #define OCP_SRAM_DATA           0xa438
127 #define OCP_DOWN_SPEED          0xa442
128 #define OCP_EEE_CFG2            0xa5d0
129 #define OCP_ADC_CFG             0xbc06
130 
131 /* SRAM Register */
132 #define SRAM_LPF_CFG            0x8012
133 #define SRAM_10M_AMP1           0x8080
134 #define SRAM_10M_AMP2           0x8082
135 #define SRAM_IMPEDANCE          0x8084
136 
137 /* PLA_RCR */
138 #define RCR_AAP                 0x00000001
139 #define RCR_APM                 0x00000002
140 #define RCR_AM                  0x00000004
141 #define RCR_AB                  0x00000008
142 #define RCR_ACPT_ALL            (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
143 
144 /* PLA_RXFIFO_CTRL0 */
145 #define RXFIFO_THR1_NORMAL      0x00080002
146 #define RXFIFO_THR1_OOB         0x01800003
147 
148 /* PLA_RXFIFO_CTRL1 */
149 #define RXFIFO_THR2_FULL        0x00000060
150 #define RXFIFO_THR2_HIGH        0x00000038
151 #define RXFIFO_THR2_OOB         0x0000004a
152 #define RXFIFO_THR2_NORMAL      0x00a0
153 
154 /* PLA_RXFIFO_CTRL2 */
155 #define RXFIFO_THR3_FULL        0x00000078
156 #define RXFIFO_THR3_HIGH        0x00000048
157 #define RXFIFO_THR3_OOB         0x0000005a
158 #define RXFIFO_THR3_NORMAL      0x0110
159 
160 /* PLA_TXFIFO_CTRL */
161 #define TXFIFO_THR_NORMAL       0x00400008
162 #define TXFIFO_THR_NORMAL2      0x01000008
163 
164 /* PLA_FMC */
165 #define FMC_FCR_MCU_EN          0x0001
166 
167 /* PLA_EEEP_CR */
168 #define EEEP_CR_EEEP_TX         0x0002
169 
170 /* PLA_WDT6_CTRL */
171 #define WDT6_SET_MODE           0x0010
172 
173 /* PLA_TCR0 */
174 #define TCR0_TX_EMPTY           0x0800
175 #define TCR0_AUTO_FIFO          0x0080
176 
177 /* PLA_TCR1 */
178 #define VERSION_MASK            0x7cf0
179 
180 /* PLA_CR */
181 #define CR_RST                  0x10
182 #define CR_RE                   0x08
183 #define CR_TE                   0x04
184 
185 /* PLA_CRWECR */
186 #define CRWECR_NORAML           0x00
187 #define CRWECR_CONFIG           0xc0
188 
189 /* PLA_OOB_CTRL */
190 #define NOW_IS_OOB              0x80
191 #define TXFIFO_EMPTY            0x20
192 #define RXFIFO_EMPTY            0x10
193 #define LINK_LIST_READY         0x02
194 #define DIS_MCU_CLROOB          0x01
195 #define FIFO_EMPTY              (TXFIFO_EMPTY | RXFIFO_EMPTY)
196 
197 /* PLA_MISC_1 */
198 #define RXDY_GATED_EN           0x0008
199 
200 /* PLA_SFF_STS_7 */
201 #define RE_INIT_LL              0x8000
202 #define MCU_BORW_EN             0x4000
203 
204 /* PLA_CPCR */
205 #define CPCR_RX_VLAN            0x0040
206 
207 /* PLA_CFG_WOL */
208 #define MAGIC_EN                0x0001
209 
210 /* PLA_TEREDO_CFG */
211 #define TEREDO_SEL              0x8000
212 #define TEREDO_WAKE_MASK        0x7f00
213 #define TEREDO_RS_EVENT_MASK    0x00fe
214 #define OOB_TEREDO_EN           0x0001
215 
216 /* PAL_BDC_CR */
217 #define ALDPS_PROXY_MODE        0x0001
218 
219 /* PLA_CONFIG5 */
220 #define LAN_WAKE_EN             0x0002
221 
222 /* PLA_LED_FEATURE */
223 #define LED_MODE_MASK           0x0700
224 
225 /* PLA_PHY_PWR */
226 #define TX_10M_IDLE_EN          0x0080
227 #define PFM_PWM_SWITCH          0x0040
228 
229 /* PLA_MAC_PWR_CTRL */
230 #define D3_CLK_GATED_EN         0x00004000
231 #define MCU_CLK_RATIO           0x07010f07
232 #define MCU_CLK_RATIO_MASK      0x0f0f0f0f
233 #define ALDPS_SPDWN_RATIO       0x0f87
234 
235 /* PLA_MAC_PWR_CTRL2 */
236 #define EEE_SPDWN_RATIO         0x8007
237 
238 /* PLA_MAC_PWR_CTRL3 */
239 #define PKT_AVAIL_SPDWN_EN      0x0100
240 #define SUSPEND_SPDWN_EN        0x0004
241 #define U1U2_SPDWN_EN           0x0002
242 #define L1_SPDWN_EN             0x0001
243 
244 /* PLA_MAC_PWR_CTRL4 */
245 #define PWRSAVE_SPDWN_EN        0x1000
246 #define RXDV_SPDWN_EN           0x0800
247 #define TX10MIDLE_EN            0x0100
248 #define TP100_SPDWN_EN          0x0020
249 #define TP500_SPDWN_EN          0x0010
250 #define TP1000_SPDWN_EN         0x0008
251 #define EEE_SPDWN_EN            0x0001
252 
253 /* PLA_GPHY_INTR_IMR */
254 #define GPHY_STS_MSK            0x0001
255 #define SPEED_DOWN_MSK          0x0002
256 #define SPDWN_RXDV_MSK          0x0004
257 #define SPDWN_LINKCHG_MSK       0x0008
258 
259 /* PLA_PHYAR */
260 #define PHYAR_FLAG              0x80000000
261 
262 /* PLA_EEE_CR */
263 #define EEE_RX_EN               0x0001
264 #define EEE_TX_EN               0x0002
265 
266 /* PLA_BOOT_CTRL */
267 #define AUTOLOAD_DONE           0x0002
268 
269 /* USB_DEV_STAT */
270 #define STAT_SPEED_MASK         0x0006
271 #define STAT_SPEED_HIGH         0x0000
272 #define STAT_SPEED_FULL         0x0001
273 
274 /* USB_TX_AGG */
275 #define TX_AGG_MAX_THRESHOLD    0x03
276 
277 /* USB_RX_BUF_TH */
278 #define RX_THR_SUPPER           0x0c350180
279 #define RX_THR_HIGH             0x7a120180
280 #define RX_THR_SLOW             0xffff0180
281 
282 /* USB_TX_DMA */
283 #define TEST_MODE_DISABLE       0x00000001
284 #define TX_SIZE_ADJUST1         0x00000100
285 
286 /* USB_UPS_CTRL */
287 #define POWER_CUT               0x0100
288 
289 /* USB_PM_CTRL_STATUS */
290 #define RESUME_INDICATE         0x0001
291 
292 /* USB_USB_CTRL */
293 #define RX_AGG_DISABLE          0x0010
294 
295 /* USB_U2P3_CTRL */
296 #define U2P3_ENABLE             0x0001
297 
298 /* USB_POWER_CUT */
299 #define PWR_EN                  0x0001
300 #define PHASE2_EN               0x0008
301 
302 /* USB_MISC_0 */
303 #define PCUT_STATUS             0x0001
304 
305 /* USB_RX_EARLY_AGG */
306 #define EARLY_AGG_SUPPER        0x0e832981
307 #define EARLY_AGG_HIGH          0x0e837a12
308 #define EARLY_AGG_SLOW          0x0e83ffff
309 
310 /* USB_WDT11_CTRL */
311 #define TIMER11_EN              0x0001
312 
313 /* USB_LPM_CTRL */
314 #define LPM_TIMER_MASK          0x0c
315 #define LPM_TIMER_500MS         0x04    /* 500 ms */
316 #define LPM_TIMER_500US         0x0c    /* 500 us */
317 
318 /* USB_AFE_CTRL2 */
319 #define SEN_VAL_MASK            0xf800
320 #define SEN_VAL_NORMAL          0xa000
321 #define SEL_RXIDLE              0x0100
322 
323 /* OCP_ALDPS_CONFIG */
324 #define ENPWRSAVE               0x8000
325 #define ENPDNPS                 0x0200
326 #define LINKENA                 0x0100
327 #define DIS_SDSAVE              0x0010
328 
329 /* OCP_PHY_STATUS */
330 #define PHY_STAT_MASK           0x0007
331 #define PHY_STAT_LAN_ON         3
332 #define PHY_STAT_PWRDN          5
333 
334 /* OCP_POWER_CFG */
335 #define EEE_CLKDIV_EN           0x8000
336 #define EN_ALDPS                0x0004
337 #define EN_10M_PLLOFF           0x0001
338 
339 /* OCP_EEE_CONFIG1 */
340 #define RG_TXLPI_MSK_HFDUP      0x8000
341 #define RG_MATCLR_EN            0x4000
342 #define EEE_10_CAP              0x2000
343 #define EEE_NWAY_EN             0x1000
344 #define TX_QUIET_EN             0x0200
345 #define RX_QUIET_EN             0x0100
346 #define SDRISETIME              0x0010  /* bit 4 ~ 6 */
347 #define RG_RXLPI_MSK_HFDUP      0x0008
348 #define SDFALLTIME              0x0007  /* bit 0 ~ 2 */
349 
350 /* OCP_EEE_CONFIG2 */
351 #define RG_LPIHYS_NUM           0x7000  /* bit 12 ~ 15 */
352 #define RG_DACQUIET_EN          0x0400
353 #define RG_LDVQUIET_EN          0x0200
354 #define RG_CKRSEL               0x0020
355 #define RG_EEEPRG_EN            0x0010
356 
357 /* OCP_EEE_CONFIG3 */
358 #define FST_SNR_EYE_R           0x1500  /* bit 7 ~ 15 */
359 #define RG_LFS_SEL              0x0060  /* bit 6 ~ 5 */
360 #define MSK_PH                  0x0006  /* bit 0 ~ 3 */
361 
362 /* OCP_EEE_AR */
363 /* bit[15:14] function */
364 #define FUN_ADDR                0x0000
365 #define FUN_DATA                0x4000
366 /* bit[4:0] device addr */
367 #define DEVICE_ADDR             0x0007
368 
369 /* OCP_EEE_DATA */
370 #define EEE_ADDR                0x003C
371 #define EEE_DATA                0x0002
372 
373 /* OCP_EEE_CFG */
374 #define CTAP_SHORT_EN           0x0040
375 #define EEE10_EN                0x0010
376 
377 /* OCP_DOWN_SPEED */
378 #define EN_10M_BGOFF            0x0080
379 
380 /* OCP_EEE_CFG2 */
381 #define MY1000_EEE              0x0004
382 #define MY100_EEE               0x0002
383 
384 /* OCP_ADC_CFG */
385 #define CKADSEL_L               0x0100
386 #define ADC_EN                  0x0080
387 #define EN_EMI_L                0x0040
388 
389 /* SRAM_LPF_CFG */
390 #define LPF_AUTO_TUNE           0x8000
391 
392 /* SRAM_10M_AMP1 */
393 #define GDAC_IB_UPALL           0x0008
394 
395 /* SRAM_10M_AMP2 */
396 #define AMP_DN                  0x0200
397 
398 /* SRAM_IMPEDANCE */
399 #define RX_DRIVING_MASK         0x6000
400 
401 enum rtl_register_content {
402         _1000bps        = 0x10,
403         _100bps         = 0x08,
404         _10bps          = 0x04,
405         LINK_STATUS     = 0x02,
406         FULL_DUP        = 0x01,
407 };
408 
409 #define RTL8152_MAX_TX          10
410 #define RTL8152_MAX_RX          10
411 #define INTBUFSIZE              2
412 #define CRC_SIZE                4
413 #define TX_ALIGN                4
414 #define RX_ALIGN                8
415 
416 #define INTR_LINK               0x0004
417 
418 #define RTL8152_REQT_READ       0xc0
419 #define RTL8152_REQT_WRITE      0x40
420 #define RTL8152_REQ_GET_REGS    0x05
421 #define RTL8152_REQ_SET_REGS    0x05
422 
423 #define BYTE_EN_DWORD           0xff
424 #define BYTE_EN_WORD            0x33
425 #define BYTE_EN_BYTE            0x11
426 #define BYTE_EN_SIX_BYTES       0x3f
427 #define BYTE_EN_START_MASK      0x0f
428 #define BYTE_EN_END_MASK        0xf0
429 
430 #define RTL8152_RMS             (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
431 #define RTL8152_TX_TIMEOUT      (HZ)
432 
433 /* rtl8152 flags */
434 enum rtl8152_flags {
435         RTL8152_UNPLUG = 0,
436         RTL8152_SET_RX_MODE,
437         WORK_ENABLE,
438         RTL8152_LINK_CHG,
439 };
440 
441 /* Define these values to match your device */
442 #define VENDOR_ID_REALTEK               0x0bda
443 #define PRODUCT_ID_RTL8152              0x8152
444 #define PRODUCT_ID_RTL8153              0x8153
445 
446 #define VENDOR_ID_SAMSUNG               0x04e8
447 #define PRODUCT_ID_SAMSUNG              0xa101
448 
449 #define MCU_TYPE_PLA                    0x0100
450 #define MCU_TYPE_USB                    0x0000
451 
452 struct rx_desc {
453         __le32 opts1;
454 #define RX_LEN_MASK                     0x7fff
455         __le32 opts2;
456         __le32 opts3;
457         __le32 opts4;
458         __le32 opts5;
459         __le32 opts6;
460 };
461 
462 struct tx_desc {
463         __le32 opts1;
464 #define TX_FS                   (1 << 31) /* First segment of a packet */
465 #define TX_LS                   (1 << 30) /* Final segment of a packet */
466 #define TX_LEN_MASK             0x3ffff
467 
468         __le32 opts2;
469 #define UDP_CS                  (1 << 31) /* Calculate UDP/IP checksum */
470 #define TCP_CS                  (1 << 30) /* Calculate TCP/IP checksum */
471 #define IPV4_CS                 (1 << 29) /* Calculate IPv4 checksum */
472 #define IPV6_CS                 (1 << 28) /* Calculate IPv6 checksum */
473 };
474 
475 struct r8152;
476 
477 struct rx_agg {
478         struct list_head list;
479         struct urb *urb;
480         struct r8152 *context;
481         void *buffer;
482         void *head;
483 };
484 
485 struct tx_agg {
486         struct list_head list;
487         struct urb *urb;
488         struct r8152 *context;
489         void *buffer;
490         void *head;
491         u32 skb_num;
492         u32 skb_len;
493 };
494 
495 struct r8152 {
496         unsigned long flags;
497         struct usb_device *udev;
498         struct tasklet_struct tl;
499         struct usb_interface *intf;
500         struct net_device *netdev;
501         struct urb *intr_urb;
502         struct tx_agg tx_info[RTL8152_MAX_TX];
503         struct rx_agg rx_info[RTL8152_MAX_RX];
504         struct list_head rx_done, tx_free;
505         struct sk_buff_head tx_queue;
506         spinlock_t rx_lock, tx_lock;
507         struct delayed_work schedule;
508         struct mii_if_info mii;
509 
510         struct rtl_ops {
511                 void (*init)(struct r8152 *);
512                 int (*enable)(struct r8152 *);
513                 void (*disable)(struct r8152 *);
514                 void (*down)(struct r8152 *);
515                 void (*unload)(struct r8152 *);
516         } rtl_ops;
517 
518         int intr_interval;
519         u32 msg_enable;
520         u32 tx_qlen;
521         u16 ocp_base;
522         u8 *intr_buff;
523         u8 version;
524         u8 speed;
525 };
526 
527 enum rtl_version {
528         RTL_VER_UNKNOWN = 0,
529         RTL_VER_01,
530         RTL_VER_02,
531         RTL_VER_03,
532         RTL_VER_04,
533         RTL_VER_05,
534         RTL_VER_MAX
535 };
536 
537 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
538  * The RTL chips use a 64 element hash table based on the Ethernet CRC.
539  */
540 static const int multicast_filter_limit = 32;
541 static unsigned int rx_buf_sz = 16384;
542 
543 static
544 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
545 {
546         int ret;
547         void *tmp;
548 
549         tmp = kmalloc(size, GFP_KERNEL);
550         if (!tmp)
551                 return -ENOMEM;
552 
553         ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
554                                RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
555                                value, index, tmp, size, 500);
556 
557         memcpy(data, tmp, size);
558         kfree(tmp);
559 
560         return ret;
561 }
562 
563 static
564 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
565 {
566         int ret;
567         void *tmp;
568 
569         tmp = kmalloc(size, GFP_KERNEL);
570         if (!tmp)
571                 return -ENOMEM;
572 
573         memcpy(tmp, data, size);
574 
575         ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
576                                RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
577                                value, index, tmp, size, 500);
578 
579         kfree(tmp);
580         return ret;
581 }
582 
583 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
584                                 void *data, u16 type)
585 {
586         u16 limit = 64;
587         int ret = 0;
588 
589         if (test_bit(RTL8152_UNPLUG, &tp->flags))
590                 return -ENODEV;
591 
592         /* both size and indix must be 4 bytes align */
593         if ((size & 3) || !size || (index & 3) || !data)
594                 return -EPERM;
595 
596         if ((u32)index + (u32)size > 0xffff)
597                 return -EPERM;
598 
599         while (size) {
600                 if (size > limit) {
601                         ret = get_registers(tp, index, type, limit, data);
602                         if (ret < 0)
603                                 break;
604 
605                         index += limit;
606                         data += limit;
607                         size -= limit;
608                 } else {
609                         ret = get_registers(tp, index, type, size, data);
610                         if (ret < 0)
611                                 break;
612 
613                         index += size;
614                         data += size;
615                         size = 0;
616                         break;
617                 }
618         }
619 
620         return ret;
621 }
622 
623 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
624                                 u16 size, void *data, u16 type)
625 {
626         int ret;
627         u16 byteen_start, byteen_end, byen;
628         u16 limit = 512;
629 
630         if (test_bit(RTL8152_UNPLUG, &tp->flags))
631                 return -ENODEV;
632 
633         /* both size and indix must be 4 bytes align */
634         if ((size & 3) || !size || (index & 3) || !data)
635                 return -EPERM;
636 
637         if ((u32)index + (u32)size > 0xffff)
638                 return -EPERM;
639 
640         byteen_start = byteen & BYTE_EN_START_MASK;
641         byteen_end = byteen & BYTE_EN_END_MASK;
642 
643         byen = byteen_start | (byteen_start << 4);
644         ret = set_registers(tp, index, type | byen, 4, data);
645         if (ret < 0)
646                 goto error1;
647 
648         index += 4;
649         data += 4;
650         size -= 4;
651 
652         if (size) {
653                 size -= 4;
654 
655                 while (size) {
656                         if (size > limit) {
657                                 ret = set_registers(tp, index,
658                                         type | BYTE_EN_DWORD,
659                                         limit, data);
660                                 if (ret < 0)
661                                         goto error1;
662 
663                                 index += limit;
664                                 data += limit;
665                                 size -= limit;
666                         } else {
667                                 ret = set_registers(tp, index,
668                                         type | BYTE_EN_DWORD,
669                                         size, data);
670                                 if (ret < 0)
671                                         goto error1;
672 
673                                 index += size;
674                                 data += size;
675                                 size = 0;
676                                 break;
677                         }
678                 }
679 
680                 byen = byteen_end | (byteen_end >> 4);
681                 ret = set_registers(tp, index, type | byen, 4, data);
682                 if (ret < 0)
683                         goto error1;
684         }
685 
686 error1:
687         return ret;
688 }
689 
690 static inline
691 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
692 {
693         return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
694 }
695 
696 static inline
697 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
698 {
699         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
700 }
701 
702 static inline
703 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
704 {
705         return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
706 }
707 
708 static inline
709 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
710 {
711         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
712 }
713 
714 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
715 {
716         __le32 data;
717 
718         generic_ocp_read(tp, index, sizeof(data), &data, type);
719 
720         return __le32_to_cpu(data);
721 }
722 
723 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
724 {
725         __le32 tmp = __cpu_to_le32(data);
726 
727         generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
728 }
729 
730 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
731 {
732         u32 data;
733         __le32 tmp;
734         u8 shift = index & 2;
735 
736         index &= ~3;
737 
738         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
739 
740         data = __le32_to_cpu(tmp);
741         data >>= (shift * 8);
742         data &= 0xffff;
743 
744         return (u16)data;
745 }
746 
747 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
748 {
749         u32 mask = 0xffff;
750         __le32 tmp;
751         u16 byen = BYTE_EN_WORD;
752         u8 shift = index & 2;
753 
754         data &= mask;
755 
756         if (index & 2) {
757                 byen <<= shift;
758                 mask <<= (shift * 8);
759                 data <<= (shift * 8);
760                 index &= ~3;
761         }
762 
763         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
764 
765         data |= __le32_to_cpu(tmp) & ~mask;
766         tmp = __cpu_to_le32(data);
767 
768         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
769 }
770 
771 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
772 {
773         u32 data;
774         __le32 tmp;
775         u8 shift = index & 3;
776 
777         index &= ~3;
778 
779         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
780 
781         data = __le32_to_cpu(tmp);
782         data >>= (shift * 8);
783         data &= 0xff;
784 
785         return (u8)data;
786 }
787 
788 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
789 {
790         u32 mask = 0xff;
791         __le32 tmp;
792         u16 byen = BYTE_EN_BYTE;
793         u8 shift = index & 3;
794 
795         data &= mask;
796 
797         if (index & 3) {
798                 byen <<= shift;
799                 mask <<= (shift * 8);
800                 data <<= (shift * 8);
801                 index &= ~3;
802         }
803 
804         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
805 
806         data |= __le32_to_cpu(tmp) & ~mask;
807         tmp = __cpu_to_le32(data);
808 
809         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
810 }
811 
812 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
813 {
814         u16 ocp_base, ocp_index;
815 
816         ocp_base = addr & 0xf000;
817         if (ocp_base != tp->ocp_base) {
818                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
819                 tp->ocp_base = ocp_base;
820         }
821 
822         ocp_index = (addr & 0x0fff) | 0xb000;
823         return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
824 }
825 
826 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
827 {
828         u16 ocp_base, ocp_index;
829 
830         ocp_base = addr & 0xf000;
831         if (ocp_base != tp->ocp_base) {
832                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
833                 tp->ocp_base = ocp_base;
834         }
835 
836         ocp_index = (addr & 0x0fff) | 0xb000;
837         ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
838 }
839 
840 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
841 {
842         ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
843 }
844 
845 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
846 {
847         return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
848 }
849 
850 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
851 {
852         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
853         ocp_reg_write(tp, OCP_SRAM_DATA, data);
854 }
855 
856 static u16 sram_read(struct r8152 *tp, u16 addr)
857 {
858         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
859         return ocp_reg_read(tp, OCP_SRAM_DATA);
860 }
861 
862 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
863 {
864         struct r8152 *tp = netdev_priv(netdev);
865 
866         if (phy_id != R8152_PHY_ID)
867                 return -EINVAL;
868 
869         return r8152_mdio_read(tp, reg);
870 }
871 
872 static
873 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
874 {
875         struct r8152 *tp = netdev_priv(netdev);
876 
877         if (phy_id != R8152_PHY_ID)
878                 return;
879 
880         r8152_mdio_write(tp, reg, val);
881 }
882 
883 static
884 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
885 
886 static inline void set_ethernet_addr(struct r8152 *tp)
887 {
888         struct net_device *dev = tp->netdev;
889         u8 node_id[8] = {0};
890 
891         if (pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id) < 0)
892                 netif_notice(tp, probe, dev, "inet addr fail\n");
893         else {
894                 memcpy(dev->dev_addr, node_id, dev->addr_len);
895                 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
896         }
897 }
898 
899 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
900 {
901         struct r8152 *tp = netdev_priv(netdev);
902         struct sockaddr *addr = p;
903 
904         if (!is_valid_ether_addr(addr->sa_data))
905                 return -EADDRNOTAVAIL;
906 
907         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
908 
909         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
910         pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
911         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
912 
913         return 0;
914 }
915 
916 static struct net_device_stats *rtl8152_get_stats(struct net_device *dev)
917 {
918         return &dev->stats;
919 }
920 
921 static void read_bulk_callback(struct urb *urb)
922 {
923         struct net_device *netdev;
924         unsigned long flags;
925         int status = urb->status;
926         struct rx_agg *agg;
927         struct r8152 *tp;
928         int result;
929 
930         agg = urb->context;
931         if (!agg)
932                 return;
933 
934         tp = agg->context;
935         if (!tp)
936                 return;
937 
938         if (test_bit(RTL8152_UNPLUG, &tp->flags))
939                 return;
940 
941         if (!test_bit(WORK_ENABLE, &tp->flags))
942                 return;
943 
944         netdev = tp->netdev;
945 
946         /* When link down, the driver would cancel all bulks. */
947         /* This avoid the re-submitting bulk */
948         if (!netif_carrier_ok(netdev))
949                 return;
950 
951         switch (status) {
952         case 0:
953                 if (urb->actual_length < ETH_ZLEN)
954                         break;
955 
956                 spin_lock_irqsave(&tp->rx_lock, flags);
957                 list_add_tail(&agg->list, &tp->rx_done);
958                 spin_unlock_irqrestore(&tp->rx_lock, flags);
959                 tasklet_schedule(&tp->tl);
960                 return;
961         case -ESHUTDOWN:
962                 set_bit(RTL8152_UNPLUG, &tp->flags);
963                 netif_device_detach(tp->netdev);
964                 return;
965         case -ENOENT:
966                 return; /* the urb is in unlink state */
967         case -ETIME:
968                 if (net_ratelimit())
969                         netdev_warn(netdev, "maybe reset is needed?\n");
970                 break;
971         default:
972                 if (net_ratelimit())
973                         netdev_warn(netdev, "Rx status %d\n", status);
974                 break;
975         }
976 
977         result = r8152_submit_rx(tp, agg, GFP_ATOMIC);
978         if (result == -ENODEV) {
979                 netif_device_detach(tp->netdev);
980         } else if (result) {
981                 spin_lock_irqsave(&tp->rx_lock, flags);
982                 list_add_tail(&agg->list, &tp->rx_done);
983                 spin_unlock_irqrestore(&tp->rx_lock, flags);
984                 tasklet_schedule(&tp->tl);
985         }
986 }
987 
988 static void write_bulk_callback(struct urb *urb)
989 {
990         struct net_device_stats *stats;
991         unsigned long flags;
992         struct tx_agg *agg;
993         struct r8152 *tp;
994         int status = urb->status;
995 
996         agg = urb->context;
997         if (!agg)
998                 return;
999 
1000         tp = agg->context;
1001         if (!tp)
1002                 return;
1003 
1004         stats = rtl8152_get_stats(tp->netdev);
1005         if (status) {
1006                 if (net_ratelimit())
1007                         netdev_warn(tp->netdev, "Tx status %d\n", status);
1008                 stats->tx_errors += agg->skb_num;
1009         } else {
1010                 stats->tx_packets += agg->skb_num;
1011                 stats->tx_bytes += agg->skb_len;
1012         }
1013 
1014         spin_lock_irqsave(&tp->tx_lock, flags);
1015         list_add_tail(&agg->list, &tp->tx_free);
1016         spin_unlock_irqrestore(&tp->tx_lock, flags);
1017 
1018         if (!netif_carrier_ok(tp->netdev))
1019                 return;
1020 
1021         if (!test_bit(WORK_ENABLE, &tp->flags))
1022                 return;
1023 
1024         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1025                 return;
1026 
1027         if (!skb_queue_empty(&tp->tx_queue))
1028                 tasklet_schedule(&tp->tl);
1029 }
1030 
1031 static void intr_callback(struct urb *urb)
1032 {
1033         struct r8152 *tp;
1034         __le16 *d;
1035         int status = urb->status;
1036         int res;
1037 
1038         tp = urb->context;
1039         if (!tp)
1040                 return;
1041 
1042         if (!test_bit(WORK_ENABLE, &tp->flags))
1043                 return;
1044 
1045         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1046                 return;
1047 
1048         switch (status) {
1049         case 0:                 /* success */
1050                 break;
1051         case -ECONNRESET:       /* unlink */
1052         case -ESHUTDOWN:
1053                 netif_device_detach(tp->netdev);
1054         case -ENOENT:
1055                 return;
1056         case -EOVERFLOW:
1057                 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1058                 goto resubmit;
1059         /* -EPIPE:  should clear the halt */
1060         default:
1061                 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1062                 goto resubmit;
1063         }
1064 
1065         d = urb->transfer_buffer;
1066         if (INTR_LINK & __le16_to_cpu(d[0])) {
1067                 if (!(tp->speed & LINK_STATUS)) {
1068                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1069                         schedule_delayed_work(&tp->schedule, 0);
1070                 }
1071         } else {
1072                 if (tp->speed & LINK_STATUS) {
1073                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1074                         schedule_delayed_work(&tp->schedule, 0);
1075                 }
1076         }
1077 
1078 resubmit:
1079         res = usb_submit_urb(urb, GFP_ATOMIC);
1080         if (res == -ENODEV)
1081                 netif_device_detach(tp->netdev);
1082         else if (res)
1083                 netif_err(tp, intr, tp->netdev,
1084                           "can't resubmit intr, status %d\n", res);
1085 }
1086 
1087 static inline void *rx_agg_align(void *data)
1088 {
1089         return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1090 }
1091 
1092 static inline void *tx_agg_align(void *data)
1093 {
1094         return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1095 }
1096 
1097 static void free_all_mem(struct r8152 *tp)
1098 {
1099         int i;
1100 
1101         for (i = 0; i < RTL8152_MAX_RX; i++) {
1102                 usb_free_urb(tp->rx_info[i].urb);
1103                 tp->rx_info[i].urb = NULL;
1104 
1105                 kfree(tp->rx_info[i].buffer);
1106                 tp->rx_info[i].buffer = NULL;
1107                 tp->rx_info[i].head = NULL;
1108         }
1109 
1110         for (i = 0; i < RTL8152_MAX_TX; i++) {
1111                 usb_free_urb(tp->tx_info[i].urb);
1112                 tp->tx_info[i].urb = NULL;
1113 
1114                 kfree(tp->tx_info[i].buffer);
1115                 tp->tx_info[i].buffer = NULL;
1116                 tp->tx_info[i].head = NULL;
1117         }
1118 
1119         usb_free_urb(tp->intr_urb);
1120         tp->intr_urb = NULL;
1121 
1122         kfree(tp->intr_buff);
1123         tp->intr_buff = NULL;
1124 }
1125 
1126 static int alloc_all_mem(struct r8152 *tp)
1127 {
1128         struct net_device *netdev = tp->netdev;
1129         struct usb_interface *intf = tp->intf;
1130         struct usb_host_interface *alt = intf->cur_altsetting;
1131         struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1132         struct urb *urb;
1133         int node, i;
1134         u8 *buf;
1135 
1136         node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1137 
1138         spin_lock_init(&tp->rx_lock);
1139         spin_lock_init(&tp->tx_lock);
1140         INIT_LIST_HEAD(&tp->rx_done);
1141         INIT_LIST_HEAD(&tp->tx_free);
1142         skb_queue_head_init(&tp->tx_queue);
1143 
1144         for (i = 0; i < RTL8152_MAX_RX; i++) {
1145                 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
1146                 if (!buf)
1147                         goto err1;
1148 
1149                 if (buf != rx_agg_align(buf)) {
1150                         kfree(buf);
1151                         buf = kmalloc_node(rx_buf_sz + RX_ALIGN, GFP_KERNEL,
1152                                            node);
1153                         if (!buf)
1154                                 goto err1;
1155                 }
1156 
1157                 urb = usb_alloc_urb(0, GFP_KERNEL);
1158                 if (!urb) {
1159                         kfree(buf);
1160                         goto err1;
1161                 }
1162 
1163                 INIT_LIST_HEAD(&tp->rx_info[i].list);
1164                 tp->rx_info[i].context = tp;
1165                 tp->rx_info[i].urb = urb;
1166                 tp->rx_info[i].buffer = buf;
1167                 tp->rx_info[i].head = rx_agg_align(buf);
1168         }
1169 
1170         for (i = 0; i < RTL8152_MAX_TX; i++) {
1171                 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
1172                 if (!buf)
1173                         goto err1;
1174 
1175                 if (buf != tx_agg_align(buf)) {
1176                         kfree(buf);
1177                         buf = kmalloc_node(rx_buf_sz + TX_ALIGN, GFP_KERNEL,
1178                                            node);
1179                         if (!buf)
1180                                 goto err1;
1181                 }
1182 
1183                 urb = usb_alloc_urb(0, GFP_KERNEL);
1184                 if (!urb) {
1185                         kfree(buf);
1186                         goto err1;
1187                 }
1188 
1189                 INIT_LIST_HEAD(&tp->tx_info[i].list);
1190                 tp->tx_info[i].context = tp;
1191                 tp->tx_info[i].urb = urb;
1192                 tp->tx_info[i].buffer = buf;
1193                 tp->tx_info[i].head = tx_agg_align(buf);
1194 
1195                 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1196         }
1197 
1198         tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1199         if (!tp->intr_urb)
1200                 goto err1;
1201 
1202         tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1203         if (!tp->intr_buff)
1204                 goto err1;
1205 
1206         tp->intr_interval = (int)ep_intr->desc.bInterval;
1207         usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1208                      tp->intr_buff, INTBUFSIZE, intr_callback,
1209                      tp, tp->intr_interval);
1210 
1211         return 0;
1212 
1213 err1:
1214         free_all_mem(tp);
1215         return -ENOMEM;
1216 }
1217 
1218 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1219 {
1220         struct tx_agg *agg = NULL;
1221         unsigned long flags;
1222 
1223         spin_lock_irqsave(&tp->tx_lock, flags);
1224         if (!list_empty(&tp->tx_free)) {
1225                 struct list_head *cursor;
1226 
1227                 cursor = tp->tx_free.next;
1228                 list_del_init(cursor);
1229                 agg = list_entry(cursor, struct tx_agg, list);
1230         }
1231         spin_unlock_irqrestore(&tp->tx_lock, flags);
1232 
1233         return agg;
1234 }
1235 
1236 static void
1237 r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, struct sk_buff *skb)
1238 {
1239         memset(desc, 0, sizeof(*desc));
1240 
1241         desc->opts1 = cpu_to_le32((skb->len & TX_LEN_MASK) | TX_FS | TX_LS);
1242 
1243         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1244                 __be16 protocol;
1245                 u8 ip_protocol;
1246                 u32 opts2 = 0;
1247 
1248                 if (skb->protocol == htons(ETH_P_8021Q))
1249                         protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
1250                 else
1251                         protocol = skb->protocol;
1252 
1253                 switch (protocol) {
1254                 case htons(ETH_P_IP):
1255                         opts2 |= IPV4_CS;
1256                         ip_protocol = ip_hdr(skb)->protocol;
1257                         break;
1258 
1259                 case htons(ETH_P_IPV6):
1260                         opts2 |= IPV6_CS;
1261                         ip_protocol = ipv6_hdr(skb)->nexthdr;
1262                         break;
1263 
1264                 default:
1265                         ip_protocol = IPPROTO_RAW;
1266                         break;
1267                 }
1268 
1269                 if (ip_protocol == IPPROTO_TCP) {
1270                         opts2 |= TCP_CS;
1271                         opts2 |= (skb_transport_offset(skb) & 0x7fff) << 17;
1272                 } else if (ip_protocol == IPPROTO_UDP) {
1273                         opts2 |= UDP_CS;
1274                 } else {
1275                         WARN_ON_ONCE(1);
1276                 }
1277 
1278                 desc->opts2 = cpu_to_le32(opts2);
1279         }
1280 }
1281 
1282 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1283 {
1284         int remain;
1285         u8 *tx_data;
1286 
1287         tx_data = agg->head;
1288         agg->skb_num = agg->skb_len = 0;
1289         remain = rx_buf_sz;
1290 
1291         while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1292                 struct tx_desc *tx_desc;
1293                 struct sk_buff *skb;
1294                 unsigned int len;
1295 
1296                 skb = skb_dequeue(&tp->tx_queue);
1297                 if (!skb)
1298                         break;
1299 
1300                 remain -= sizeof(*tx_desc);
1301                 len = skb->len;
1302                 if (remain < len) {
1303                         skb_queue_head(&tp->tx_queue, skb);
1304                         break;
1305                 }
1306 
1307                 tx_data = tx_agg_align(tx_data);
1308                 tx_desc = (struct tx_desc *)tx_data;
1309                 tx_data += sizeof(*tx_desc);
1310 
1311                 r8152_tx_csum(tp, tx_desc, skb);
1312                 memcpy(tx_data, skb->data, len);
1313                 agg->skb_num++;
1314                 agg->skb_len += len;
1315                 dev_kfree_skb_any(skb);
1316 
1317                 tx_data += len;
1318                 remain = rx_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1319         }
1320 
1321         netif_tx_lock(tp->netdev);
1322 
1323         if (netif_queue_stopped(tp->netdev) &&
1324             skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1325                 netif_wake_queue(tp->netdev);
1326 
1327         netif_tx_unlock(tp->netdev);
1328 
1329         usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1330                           agg->head, (int)(tx_data - (u8 *)agg->head),
1331                           (usb_complete_t)write_bulk_callback, agg);
1332 
1333         return usb_submit_urb(agg->urb, GFP_ATOMIC);
1334 }
1335 
1336 static void rx_bottom(struct r8152 *tp)
1337 {
1338         unsigned long flags;
1339         struct list_head *cursor, *next;
1340 
1341         spin_lock_irqsave(&tp->rx_lock, flags);
1342         list_for_each_safe(cursor, next, &tp->rx_done) {
1343                 struct rx_desc *rx_desc;
1344                 struct rx_agg *agg;
1345                 int len_used = 0;
1346                 struct urb *urb;
1347                 u8 *rx_data;
1348                 int ret;
1349 
1350                 list_del_init(cursor);
1351                 spin_unlock_irqrestore(&tp->rx_lock, flags);
1352 
1353                 agg = list_entry(cursor, struct rx_agg, list);
1354                 urb = agg->urb;
1355                 if (urb->actual_length < ETH_ZLEN)
1356                         goto submit;
1357 
1358                 rx_desc = agg->head;
1359                 rx_data = agg->head;
1360                 len_used += sizeof(struct rx_desc);
1361 
1362                 while (urb->actual_length > len_used) {
1363                         struct net_device *netdev = tp->netdev;
1364                         struct net_device_stats *stats;
1365                         unsigned int pkt_len;
1366                         struct sk_buff *skb;
1367 
1368                         pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1369                         if (pkt_len < ETH_ZLEN)
1370                                 break;
1371 
1372                         len_used += pkt_len;
1373                         if (urb->actual_length < len_used)
1374                                 break;
1375 
1376                         stats = rtl8152_get_stats(netdev);
1377 
1378                         pkt_len -= CRC_SIZE;
1379                         rx_data += sizeof(struct rx_desc);
1380 
1381                         skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1382                         if (!skb) {
1383                                 stats->rx_dropped++;
1384                                 break;
1385                         }
1386                         memcpy(skb->data, rx_data, pkt_len);
1387                         skb_put(skb, pkt_len);
1388                         skb->protocol = eth_type_trans(skb, netdev);
1389                         netif_rx(skb);
1390                         stats->rx_packets++;
1391                         stats->rx_bytes += pkt_len;
1392 
1393                         rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
1394                         rx_desc = (struct rx_desc *)rx_data;
1395                         len_used = (int)(rx_data - (u8 *)agg->head);
1396                         len_used += sizeof(struct rx_desc);
1397                 }
1398 
1399 submit:
1400                 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1401                 spin_lock_irqsave(&tp->rx_lock, flags);
1402                 if (ret && ret != -ENODEV) {
1403                         list_add_tail(&agg->list, next);
1404                         tasklet_schedule(&tp->tl);
1405                 }
1406         }
1407         spin_unlock_irqrestore(&tp->rx_lock, flags);
1408 }
1409 
1410 static void tx_bottom(struct r8152 *tp)
1411 {
1412         int res;
1413 
1414         do {
1415                 struct tx_agg *agg;
1416 
1417                 if (skb_queue_empty(&tp->tx_queue))
1418                         break;
1419 
1420                 agg = r8152_get_tx_agg(tp);
1421                 if (!agg)
1422                         break;
1423 
1424                 res = r8152_tx_agg_fill(tp, agg);
1425                 if (res) {
1426                         struct net_device_stats *stats;
1427                         struct net_device *netdev;
1428                         unsigned long flags;
1429 
1430                         netdev = tp->netdev;
1431                         stats = rtl8152_get_stats(netdev);
1432 
1433                         if (res == -ENODEV) {
1434                                 netif_device_detach(netdev);
1435                         } else {
1436                                 netif_warn(tp, tx_err, netdev,
1437                                            "failed tx_urb %d\n", res);
1438                                 stats->tx_dropped += agg->skb_num;
1439                                 spin_lock_irqsave(&tp->tx_lock, flags);
1440                                 list_add_tail(&agg->list, &tp->tx_free);
1441                                 spin_unlock_irqrestore(&tp->tx_lock, flags);
1442                         }
1443                 }
1444         } while (res == 0);
1445 }
1446 
1447 static void bottom_half(unsigned long data)
1448 {
1449         struct r8152 *tp;
1450 
1451         tp = (struct r8152 *)data;
1452 
1453         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1454                 return;
1455 
1456         if (!test_bit(WORK_ENABLE, &tp->flags))
1457                 return;
1458 
1459         /* When link down, the driver would cancel all bulks. */
1460         /* This avoid the re-submitting bulk */
1461         if (!netif_carrier_ok(tp->netdev))
1462                 return;
1463 
1464         rx_bottom(tp);
1465         tx_bottom(tp);
1466 }
1467 
1468 static
1469 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1470 {
1471         usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1472                       agg->head, rx_buf_sz,
1473                       (usb_complete_t)read_bulk_callback, agg);
1474 
1475         return usb_submit_urb(agg->urb, mem_flags);
1476 }
1477 
1478 static void rtl8152_tx_timeout(struct net_device *netdev)
1479 {
1480         struct r8152 *tp = netdev_priv(netdev);
1481         int i;
1482 
1483         netif_warn(tp, tx_err, netdev, "Tx timeout\n");
1484         for (i = 0; i < RTL8152_MAX_TX; i++)
1485                 usb_unlink_urb(tp->tx_info[i].urb);
1486 }
1487 
1488 static void rtl8152_set_rx_mode(struct net_device *netdev)
1489 {
1490         struct r8152 *tp = netdev_priv(netdev);
1491 
1492         if (tp->speed & LINK_STATUS) {
1493                 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1494                 schedule_delayed_work(&tp->schedule, 0);
1495         }
1496 }
1497 
1498 static void _rtl8152_set_rx_mode(struct net_device *netdev)
1499 {
1500         struct r8152 *tp = netdev_priv(netdev);
1501         u32 mc_filter[2];       /* Multicast hash filter */
1502         __le32 tmp[2];
1503         u32 ocp_data;
1504 
1505         clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1506         netif_stop_queue(netdev);
1507         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1508         ocp_data &= ~RCR_ACPT_ALL;
1509         ocp_data |= RCR_AB | RCR_APM;
1510 
1511         if (netdev->flags & IFF_PROMISC) {
1512                 /* Unconditionally log net taps. */
1513                 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1514                 ocp_data |= RCR_AM | RCR_AAP;
1515                 mc_filter[1] = mc_filter[0] = 0xffffffff;
1516         } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1517                    (netdev->flags & IFF_ALLMULTI)) {
1518                 /* Too many to filter perfectly -- accept all multicasts. */
1519                 ocp_data |= RCR_AM;
1520                 mc_filter[1] = mc_filter[0] = 0xffffffff;
1521         } else {
1522                 struct netdev_hw_addr *ha;
1523 
1524                 mc_filter[1] = mc_filter[0] = 0;
1525                 netdev_for_each_mc_addr(ha, netdev) {
1526                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1527                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1528                         ocp_data |= RCR_AM;
1529                 }
1530         }
1531 
1532         tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1533         tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
1534 
1535         pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
1536         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1537         netif_wake_queue(netdev);
1538 }
1539 
1540 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
1541                                             struct net_device *netdev)
1542 {
1543         struct r8152 *tp = netdev_priv(netdev);
1544 
1545         skb_tx_timestamp(skb);
1546 
1547         skb_queue_tail(&tp->tx_queue, skb);
1548 
1549         if (list_empty(&tp->tx_free) &&
1550             skb_queue_len(&tp->tx_queue) > tp->tx_qlen)
1551                 netif_stop_queue(netdev);
1552 
1553         if (!list_empty(&tp->tx_free))
1554                 tasklet_schedule(&tp->tl);
1555 
1556         return NETDEV_TX_OK;
1557 }
1558 
1559 static void r8152b_reset_packet_filter(struct r8152 *tp)
1560 {
1561         u32     ocp_data;
1562 
1563         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1564         ocp_data &= ~FMC_FCR_MCU_EN;
1565         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1566         ocp_data |= FMC_FCR_MCU_EN;
1567         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1568 }
1569 
1570 static void rtl8152_nic_reset(struct r8152 *tp)
1571 {
1572         int     i;
1573 
1574         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1575 
1576         for (i = 0; i < 1000; i++) {
1577                 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1578                         break;
1579                 udelay(100);
1580         }
1581 }
1582 
1583 static void set_tx_qlen(struct r8152 *tp)
1584 {
1585         struct net_device *netdev = tp->netdev;
1586 
1587         tp->tx_qlen = rx_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
1588                                    sizeof(struct tx_desc));
1589 }
1590 
1591 static inline u8 rtl8152_get_speed(struct r8152 *tp)
1592 {
1593         return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
1594 }
1595 
1596 static void rtl_set_eee_plus(struct r8152 *tp)
1597 {
1598         u32 ocp_data;
1599         u8 speed;
1600 
1601         speed = rtl8152_get_speed(tp);
1602         if (speed & _10bps) {
1603                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1604                 ocp_data |= EEEP_CR_EEEP_TX;
1605                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1606         } else {
1607                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1608                 ocp_data &= ~EEEP_CR_EEEP_TX;
1609                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1610         }
1611 }
1612 
1613 static int rtl_enable(struct r8152 *tp)
1614 {
1615         u32 ocp_data;
1616         int i, ret;
1617 
1618         r8152b_reset_packet_filter(tp);
1619 
1620         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
1621         ocp_data |= CR_RE | CR_TE;
1622         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
1623 
1624         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1625         ocp_data &= ~RXDY_GATED_EN;
1626         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1627 
1628         INIT_LIST_HEAD(&tp->rx_done);
1629         ret = 0;
1630         for (i = 0; i < RTL8152_MAX_RX; i++) {
1631                 INIT_LIST_HEAD(&tp->rx_info[i].list);
1632                 ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
1633         }
1634 
1635         return ret;
1636 }
1637 
1638 static int rtl8152_enable(struct r8152 *tp)
1639 {
1640         set_tx_qlen(tp);
1641         rtl_set_eee_plus(tp);
1642 
1643         return rtl_enable(tp);
1644 }
1645 
1646 static void r8153_set_rx_agg(struct r8152 *tp)
1647 {
1648         u8 speed;
1649 
1650         speed = rtl8152_get_speed(tp);
1651         if (speed & _1000bps) {
1652                 if (tp->udev->speed == USB_SPEED_SUPER) {
1653                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
1654                                         RX_THR_SUPPER);
1655                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
1656                                         EARLY_AGG_SUPPER);
1657                 } else {
1658                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
1659                                         RX_THR_HIGH);
1660                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
1661                                         EARLY_AGG_HIGH);
1662                 }
1663         } else {
1664                 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
1665                 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
1666                                 EARLY_AGG_SLOW);
1667         }
1668 }
1669 
1670 static int rtl8153_enable(struct r8152 *tp)
1671 {
1672         set_tx_qlen(tp);
1673         rtl_set_eee_plus(tp);
1674         r8153_set_rx_agg(tp);
1675 
1676         return rtl_enable(tp);
1677 }
1678 
1679 static void rtl8152_disable(struct r8152 *tp)
1680 {
1681         struct net_device_stats *stats = rtl8152_get_stats(tp->netdev);
1682         struct sk_buff *skb;
1683         u32 ocp_data;
1684         int i;
1685 
1686         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1687         ocp_data &= ~RCR_ACPT_ALL;
1688         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1689 
1690         while ((skb = skb_dequeue(&tp->tx_queue))) {
1691                 dev_kfree_skb(skb);
1692                 stats->tx_dropped++;
1693         }
1694 
1695         for (i = 0; i < RTL8152_MAX_TX; i++)
1696                 usb_kill_urb(tp->tx_info[i].urb);
1697 
1698         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1699         ocp_data |= RXDY_GATED_EN;
1700         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1701 
1702         for (i = 0; i < 1000; i++) {
1703                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1704                 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
1705                         break;
1706                 mdelay(1);
1707         }
1708 
1709         for (i = 0; i < 1000; i++) {
1710                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
1711                         break;
1712                 mdelay(1);
1713         }
1714 
1715         for (i = 0; i < RTL8152_MAX_RX; i++)
1716                 usb_kill_urb(tp->rx_info[i].urb);
1717 
1718         rtl8152_nic_reset(tp);
1719 }
1720 
1721 static void r8152b_exit_oob(struct r8152 *tp)
1722 {
1723         u32     ocp_data;
1724         int     i;
1725 
1726         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1727         ocp_data &= ~RCR_ACPT_ALL;
1728         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1729 
1730         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1731         ocp_data |= RXDY_GATED_EN;
1732         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1733 
1734         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1735         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
1736 
1737         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1738         ocp_data &= ~NOW_IS_OOB;
1739         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1740 
1741         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1742         ocp_data &= ~MCU_BORW_EN;
1743         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1744 
1745         for (i = 0; i < 1000; i++) {
1746                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1747                 if (ocp_data & LINK_LIST_READY)
1748                         break;
1749                 mdelay(1);
1750         }
1751 
1752         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1753         ocp_data |= RE_INIT_LL;
1754         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1755 
1756         for (i = 0; i < 1000; i++) {
1757                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1758                 if (ocp_data & LINK_LIST_READY)
1759                         break;
1760                 mdelay(1);
1761         }
1762 
1763         rtl8152_nic_reset(tp);
1764 
1765         /* rx share fifo credit full threshold */
1766         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
1767 
1768         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT);
1769         ocp_data &= STAT_SPEED_MASK;
1770         if (ocp_data == STAT_SPEED_FULL) {
1771                 /* rx share fifo credit near full threshold */
1772                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
1773                                 RXFIFO_THR2_FULL);
1774                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
1775                                 RXFIFO_THR3_FULL);
1776         } else {
1777                 /* rx share fifo credit near full threshold */
1778                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
1779                                 RXFIFO_THR2_HIGH);
1780                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
1781                                 RXFIFO_THR3_HIGH);
1782         }
1783 
1784         /* TX share fifo free credit full threshold */
1785         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
1786 
1787         ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
1788         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
1789         ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
1790                         TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
1791 
1792         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
1793         ocp_data &= ~CPCR_RX_VLAN;
1794         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
1795 
1796         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
1797 
1798         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
1799         ocp_data |= TCR0_AUTO_FIFO;
1800         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
1801 }
1802 
1803 static void r8152b_enter_oob(struct r8152 *tp)
1804 {
1805         u32 ocp_data;
1806         int i;
1807 
1808         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1809         ocp_data &= ~NOW_IS_OOB;
1810         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1811 
1812         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
1813         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
1814         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
1815 
1816         rtl8152_disable(tp);
1817 
1818         for (i = 0; i < 1000; i++) {
1819                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1820                 if (ocp_data & LINK_LIST_READY)
1821                         break;
1822                 mdelay(1);
1823         }
1824 
1825         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1826         ocp_data |= RE_INIT_LL;
1827         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1828 
1829         for (i = 0; i < 1000; i++) {
1830                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1831                 if (ocp_data & LINK_LIST_READY)
1832                         break;
1833                 mdelay(1);
1834         }
1835 
1836         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
1837 
1838         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
1839         ocp_data |= MAGIC_EN;
1840         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
1841 
1842         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
1843         ocp_data |= CPCR_RX_VLAN;
1844         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
1845 
1846         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
1847         ocp_data |= ALDPS_PROXY_MODE;
1848         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
1849 
1850         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1851         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
1852         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1853 
1854         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN);
1855 
1856         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1857         ocp_data &= ~RXDY_GATED_EN;
1858         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1859 
1860         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1861         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
1862         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1863 }
1864 
1865 static void r8152b_disable_aldps(struct r8152 *tp)
1866 {
1867         ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
1868         msleep(20);
1869 }
1870 
1871 static inline void r8152b_enable_aldps(struct r8152 *tp)
1872 {
1873         ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
1874                                             LINKENA | DIS_SDSAVE);
1875 }
1876 
1877 static void r8153_hw_phy_cfg(struct r8152 *tp)
1878 {
1879         u32 ocp_data;
1880         u16 data;
1881 
1882         ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
1883         r8152_mdio_write(tp, MII_BMCR, BMCR_ANENABLE);
1884 
1885         if (tp->version == RTL_VER_03) {
1886                 data = ocp_reg_read(tp, OCP_EEE_CFG);
1887                 data &= ~CTAP_SHORT_EN;
1888                 ocp_reg_write(tp, OCP_EEE_CFG, data);
1889         }
1890 
1891         data = ocp_reg_read(tp, OCP_POWER_CFG);
1892         data |= EEE_CLKDIV_EN;
1893         ocp_reg_write(tp, OCP_POWER_CFG, data);
1894 
1895         data = ocp_reg_read(tp, OCP_DOWN_SPEED);
1896         data |= EN_10M_BGOFF;
1897         ocp_reg_write(tp, OCP_DOWN_SPEED, data);
1898         data = ocp_reg_read(tp, OCP_POWER_CFG);
1899         data |= EN_10M_PLLOFF;
1900         ocp_reg_write(tp, OCP_POWER_CFG, data);
1901         data = sram_read(tp, SRAM_IMPEDANCE);
1902         data &= ~RX_DRIVING_MASK;
1903         sram_write(tp, SRAM_IMPEDANCE, data);
1904 
1905         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
1906         ocp_data |= PFM_PWM_SWITCH;
1907         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
1908 
1909         data = sram_read(tp, SRAM_LPF_CFG);
1910         data |= LPF_AUTO_TUNE;
1911         sram_write(tp, SRAM_LPF_CFG, data);
1912 
1913         data = sram_read(tp, SRAM_10M_AMP1);
1914         data |= GDAC_IB_UPALL;
1915         sram_write(tp, SRAM_10M_AMP1, data);
1916         data = sram_read(tp, SRAM_10M_AMP2);
1917         data |= AMP_DN;
1918         sram_write(tp, SRAM_10M_AMP2, data);
1919 }
1920 
1921 static void r8153_u1u2en(struct r8152 *tp, int enable)
1922 {
1923         u8 u1u2[8];
1924 
1925         if (enable)
1926                 memset(u1u2, 0xff, sizeof(u1u2));
1927         else
1928                 memset(u1u2, 0x00, sizeof(u1u2));
1929 
1930         usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
1931 }
1932 
1933 static void r8153_u2p3en(struct r8152 *tp, int enable)
1934 {
1935         u32 ocp_data;
1936 
1937         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
1938         if (enable)
1939                 ocp_data |= U2P3_ENABLE;
1940         else
1941                 ocp_data &= ~U2P3_ENABLE;
1942         ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
1943 }
1944 
1945 static void r8153_power_cut_en(struct r8152 *tp, int enable)
1946 {
1947         u32 ocp_data;
1948 
1949         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
1950         if (enable)
1951                 ocp_data |= PWR_EN | PHASE2_EN;
1952         else
1953                 ocp_data &= ~(PWR_EN | PHASE2_EN);
1954         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
1955 
1956         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1957         ocp_data &= ~PCUT_STATUS;
1958         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
1959 }
1960 
1961 static void r8153_teredo_off(struct r8152 *tp)
1962 {
1963         u32 ocp_data;
1964 
1965         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
1966         ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
1967         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
1968 
1969         ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
1970         ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
1971         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
1972 }
1973 
1974 static void r8153_first_init(struct r8152 *tp)
1975 {
1976         u32 ocp_data;
1977         int i;
1978 
1979         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1980         ocp_data |= RXDY_GATED_EN;
1981         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1982 
1983         r8153_teredo_off(tp);
1984 
1985         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1986         ocp_data &= ~RCR_ACPT_ALL;
1987         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1988 
1989         r8153_hw_phy_cfg(tp);
1990 
1991         rtl8152_nic_reset(tp);
1992 
1993         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1994         ocp_data &= ~NOW_IS_OOB;
1995         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1996 
1997         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1998         ocp_data &= ~MCU_BORW_EN;
1999         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2000 
2001         for (i = 0; i < 1000; i++) {
2002                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2003                 if (ocp_data & LINK_LIST_READY)
2004                         break;
2005                 mdelay(1);
2006         }
2007 
2008         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2009         ocp_data |= RE_INIT_LL;
2010         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2011 
2012         for (i = 0; i < 1000; i++) {
2013                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2014                 if (ocp_data & LINK_LIST_READY)
2015                         break;
2016                 mdelay(1);
2017         }
2018 
2019         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2020         ocp_data &= ~CPCR_RX_VLAN;
2021         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2022 
2023         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2024 
2025         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2026         ocp_data |= TCR0_AUTO_FIFO;
2027         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2028 
2029         rtl8152_nic_reset(tp);
2030 
2031         /* rx share fifo credit full threshold */
2032         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2033         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2034         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2035         /* TX share fifo free credit full threshold */
2036         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2037 
2038         /* rx aggregation */
2039         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2040         ocp_data &= ~RX_AGG_DISABLE;
2041         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2042 }
2043 
2044 static void r8153_enter_oob(struct r8152 *tp)
2045 {
2046         u32 ocp_data;
2047         int i;
2048 
2049         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2050         ocp_data &= ~NOW_IS_OOB;
2051         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2052 
2053         rtl8152_disable(tp);
2054 
2055         for (i = 0; i < 1000; i++) {
2056                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2057                 if (ocp_data & LINK_LIST_READY)
2058                         break;
2059                 mdelay(1);
2060         }
2061 
2062         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2063         ocp_data |= RE_INIT_LL;
2064         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2065 
2066         for (i = 0; i < 1000; i++) {
2067                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2068                 if (ocp_data & LINK_LIST_READY)
2069                         break;
2070                 mdelay(1);
2071         }
2072 
2073         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2074 
2075         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2076         ocp_data |= MAGIC_EN;
2077         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2078 
2079         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2080         ocp_data &= ~TEREDO_WAKE_MASK;
2081         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2082 
2083         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2084         ocp_data |= CPCR_RX_VLAN;
2085         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2086 
2087         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2088         ocp_data |= ALDPS_PROXY_MODE;
2089         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2090 
2091         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2092         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2093         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2094 
2095         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN);
2096 
2097         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2098         ocp_data &= ~RXDY_GATED_EN;
2099         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2100 
2101         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2102         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2103         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2104 }
2105 
2106 static void r8153_disable_aldps(struct r8152 *tp)
2107 {
2108         u16 data;
2109 
2110         data = ocp_reg_read(tp, OCP_POWER_CFG);
2111         data &= ~EN_ALDPS;
2112         ocp_reg_write(tp, OCP_POWER_CFG, data);
2113         msleep(20);
2114 }
2115 
2116 static void r8153_enable_aldps(struct r8152 *tp)
2117 {
2118         u16 data;
2119 
2120         data = ocp_reg_read(tp, OCP_POWER_CFG);
2121         data |= EN_ALDPS;
2122         ocp_reg_write(tp, OCP_POWER_CFG, data);
2123 }
2124 
2125 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2126 {
2127         u16 bmcr, anar, gbcr;
2128         int ret = 0;
2129 
2130         cancel_delayed_work_sync(&tp->schedule);
2131         anar = r8152_mdio_read(tp, MII_ADVERTISE);
2132         anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2133                   ADVERTISE_100HALF | ADVERTISE_100FULL);
2134         if (tp->mii.supports_gmii) {
2135                 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2136                 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2137         } else {
2138                 gbcr = 0;
2139         }
2140 
2141         if (autoneg == AUTONEG_DISABLE) {
2142                 if (speed == SPEED_10) {
2143                         bmcr = 0;
2144                         anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2145                 } else if (speed == SPEED_100) {
2146                         bmcr = BMCR_SPEED100;
2147                         anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2148                 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2149                         bmcr = BMCR_SPEED1000;
2150                         gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2151                 } else {
2152                         ret = -EINVAL;
2153                         goto out;
2154                 }
2155 
2156                 if (duplex == DUPLEX_FULL)
2157                         bmcr |= BMCR_FULLDPLX;
2158         } else {
2159                 if (speed == SPEED_10) {
2160                         if (duplex == DUPLEX_FULL)
2161                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2162                         else
2163                                 anar |= ADVERTISE_10HALF;
2164                 } else if (speed == SPEED_100) {
2165                         if (duplex == DUPLEX_FULL) {
2166                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2167                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2168                         } else {
2169                                 anar |= ADVERTISE_10HALF;
2170                                 anar |= ADVERTISE_100HALF;
2171                         }
2172                 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2173                         if (duplex == DUPLEX_FULL) {
2174                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2175                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2176                                 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2177                         } else {
2178                                 anar |= ADVERTISE_10HALF;
2179                                 anar |= ADVERTISE_100HALF;
2180                                 gbcr |= ADVERTISE_1000HALF;
2181                         }
2182                 } else {
2183                         ret = -EINVAL;
2184                         goto out;
2185                 }
2186 
2187                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2188         }
2189 
2190         if (tp->mii.supports_gmii)
2191                 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2192 
2193         r8152_mdio_write(tp, MII_ADVERTISE, anar);
2194         r8152_mdio_write(tp, MII_BMCR, bmcr);
2195 
2196 out:
2197 
2198         return ret;
2199 }
2200 
2201 static void rtl8152_down(struct r8152 *tp)
2202 {
2203         u32     ocp_data;
2204 
2205         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2206         ocp_data &= ~POWER_CUT;
2207         ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2208 
2209         r8152b_disable_aldps(tp);
2210         r8152b_enter_oob(tp);
2211         r8152b_enable_aldps(tp);
2212 }
2213 
2214 static void rtl8153_down(struct r8152 *tp)
2215 {
2216         r8153_u1u2en(tp, 0);
2217         r8153_power_cut_en(tp, 0);
2218         r8153_disable_aldps(tp);
2219         r8153_enter_oob(tp);
2220         r8153_enable_aldps(tp);
2221 }
2222 
2223 static void set_carrier(struct r8152 *tp)
2224 {
2225         struct net_device *netdev = tp->netdev;
2226         u8 speed;
2227 
2228         clear_bit(RTL8152_LINK_CHG, &tp->flags);
2229         speed = rtl8152_get_speed(tp);
2230 
2231         if (speed & LINK_STATUS) {
2232                 if (!(tp->speed & LINK_STATUS)) {
2233                         tp->rtl_ops.enable(tp);
2234                         set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2235                         netif_carrier_on(netdev);
2236                 }
2237         } else {
2238                 if (tp->speed & LINK_STATUS) {
2239                         netif_carrier_off(netdev);
2240                         tasklet_disable(&tp->tl);
2241                         tp->rtl_ops.disable(tp);
2242                         tasklet_enable(&tp->tl);
2243                 }
2244         }
2245         tp->speed = speed;
2246 }
2247 
2248 static void rtl_work_func_t(struct work_struct *work)
2249 {
2250         struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2251 
2252         if (!test_bit(WORK_ENABLE, &tp->flags))
2253                 goto out1;
2254 
2255         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2256                 goto out1;
2257 
2258         if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2259                 set_carrier(tp);
2260 
2261         if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2262                 _rtl8152_set_rx_mode(tp->netdev);
2263 
2264 out1:
2265         return;
2266 }
2267 
2268 static int rtl8152_open(struct net_device *netdev)
2269 {
2270         struct r8152 *tp = netdev_priv(netdev);
2271         int res = 0;
2272 
2273         rtl8152_set_speed(tp, AUTONEG_ENABLE,
2274                           tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
2275                           DUPLEX_FULL);
2276         tp->speed = 0;
2277         netif_carrier_off(netdev);
2278         netif_start_queue(netdev);
2279         set_bit(WORK_ENABLE, &tp->flags);
2280         res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
2281         if (res) {
2282                 if (res == -ENODEV)
2283                         netif_device_detach(tp->netdev);
2284                 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
2285                            res);
2286         }
2287 
2288 
2289         return res;
2290 }
2291 
2292 static int rtl8152_close(struct net_device *netdev)
2293 {
2294         struct r8152 *tp = netdev_priv(netdev);
2295         int res = 0;
2296 
2297         clear_bit(WORK_ENABLE, &tp->flags);
2298         usb_kill_urb(tp->intr_urb);
2299         cancel_delayed_work_sync(&tp->schedule);
2300         netif_stop_queue(netdev);
2301         tasklet_disable(&tp->tl);
2302         tp->rtl_ops.disable(tp);
2303         tasklet_enable(&tp->tl);
2304 
2305         return res;
2306 }
2307 
2308 static void rtl_clear_bp(struct r8152 *tp)
2309 {
2310         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0);
2311         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0);
2312         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0);
2313         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0);
2314         ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0);
2315         ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0);
2316         ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0);
2317         ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0);
2318         mdelay(3);
2319         ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0);
2320         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0);
2321 }
2322 
2323 static void r8153_clear_bp(struct r8152 *tp)
2324 {
2325         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
2326         ocp_write_byte(tp, MCU_TYPE_USB, USB_BP_EN, 0);
2327         rtl_clear_bp(tp);
2328 }
2329 
2330 static void r8152b_enable_eee(struct r8152 *tp)
2331 {
2332         u32 ocp_data;
2333 
2334         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2335         ocp_data |= EEE_RX_EN | EEE_TX_EN;
2336         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2337         ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN |
2338                                            EEE_10_CAP | EEE_NWAY_EN |
2339                                            TX_QUIET_EN | RX_QUIET_EN |
2340                                            SDRISETIME | RG_RXLPI_MSK_HFDUP |
2341                                            SDFALLTIME);
2342         ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN |
2343                                            RG_LDVQUIET_EN | RG_CKRSEL |
2344                                            RG_EEEPRG_EN);
2345         ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH);
2346         ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR);
2347         ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR);
2348         ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR);
2349         ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA);
2350         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2351 }
2352 
2353 static void r8153_enable_eee(struct r8152 *tp)
2354 {
2355         u32 ocp_data;
2356         u16 data;
2357 
2358         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2359         ocp_data |= EEE_RX_EN | EEE_TX_EN;
2360         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2361         data = ocp_reg_read(tp, OCP_EEE_CFG);
2362         data |= EEE10_EN;
2363         ocp_reg_write(tp, OCP_EEE_CFG, data);
2364         data = ocp_reg_read(tp, OCP_EEE_CFG2);
2365         data |= MY1000_EEE | MY100_EEE;
2366         ocp_reg_write(tp, OCP_EEE_CFG2, data);
2367 }
2368 
2369 static void r8152b_enable_fc(struct r8152 *tp)
2370 {
2371         u16 anar;
2372 
2373         anar = r8152_mdio_read(tp, MII_ADVERTISE);
2374         anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
2375         r8152_mdio_write(tp, MII_ADVERTISE, anar);
2376 }
2377 
2378 static void r8152b_hw_phy_cfg(struct r8152 *tp)
2379 {
2380         r8152_mdio_write(tp, MII_BMCR, BMCR_ANENABLE);
2381         r8152b_disable_aldps(tp);
2382 }
2383 
2384 static void r8152b_init(struct r8152 *tp)
2385 {
2386         u32 ocp_data;
2387         int i;
2388 
2389         rtl_clear_bp(tp);
2390 
2391         if (tp->version == RTL_VER_01) {
2392                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
2393                 ocp_data &= ~LED_MODE_MASK;
2394                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
2395         }
2396 
2397         r8152b_hw_phy_cfg(tp);
2398 
2399         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2400         ocp_data &= ~POWER_CUT;
2401         ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2402 
2403         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2404         ocp_data &= ~RESUME_INDICATE;
2405         ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2406 
2407         r8152b_exit_oob(tp);
2408 
2409         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2410         ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
2411         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2412         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
2413         ocp_data &= ~MCU_CLK_RATIO_MASK;
2414         ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
2415         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
2416         ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
2417                    SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
2418         ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
2419 
2420         r8152b_enable_eee(tp);
2421         r8152b_enable_aldps(tp);
2422         r8152b_enable_fc(tp);
2423 
2424         r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE |
2425                                        BMCR_ANRESTART);
2426         for (i = 0; i < 100; i++) {
2427                 udelay(100);
2428                 if (!(r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET))
2429                         break;
2430         }
2431 
2432         /* enable rx aggregation */
2433         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2434         ocp_data &= ~RX_AGG_DISABLE;
2435         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2436 }
2437 
2438 static void r8153_init(struct r8152 *tp)
2439 {
2440         u32 ocp_data;
2441         int i;
2442 
2443         r8153_u1u2en(tp, 0);
2444 
2445         for (i = 0; i < 500; i++) {
2446                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
2447                     AUTOLOAD_DONE)
2448                         break;
2449                 msleep(20);
2450         }
2451 
2452         for (i = 0; i < 500; i++) {
2453                 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
2454                 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
2455                         break;
2456                 msleep(20);
2457         }
2458 
2459         r8153_u2p3en(tp, 0);
2460 
2461         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
2462         ocp_data &= ~TIMER11_EN;
2463         ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
2464 
2465         r8153_clear_bp(tp);
2466 
2467         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
2468         ocp_data &= ~LED_MODE_MASK;
2469         ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
2470 
2471         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL);
2472         ocp_data &= ~LPM_TIMER_MASK;
2473         if (tp->udev->speed == USB_SPEED_SUPER)
2474                 ocp_data |= LPM_TIMER_500US;
2475         else
2476                 ocp_data |= LPM_TIMER_500MS;
2477         ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
2478 
2479         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
2480         ocp_data &= ~SEN_VAL_MASK;
2481         ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
2482         ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
2483 
2484         r8153_power_cut_en(tp, 0);
2485         r8153_u1u2en(tp, 1);
2486 
2487         r8153_first_init(tp);
2488 
2489         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
2490         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
2491         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
2492                        PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
2493                        U1U2_SPDWN_EN | L1_SPDWN_EN);
2494         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
2495                        PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
2496                        TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
2497                        EEE_SPDWN_EN);
2498 
2499         r8153_enable_eee(tp);
2500         r8153_enable_aldps(tp);
2501         r8152b_enable_fc(tp);
2502 
2503         r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE |
2504                                        BMCR_ANRESTART);
2505 }
2506 
2507 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
2508 {
2509         struct r8152 *tp = usb_get_intfdata(intf);
2510 
2511         netif_device_detach(tp->netdev);
2512 
2513         if (netif_running(tp->netdev)) {
2514                 clear_bit(WORK_ENABLE, &tp->flags);
2515                 usb_kill_urb(tp->intr_urb);
2516                 cancel_delayed_work_sync(&tp->schedule);
2517                 tasklet_disable(&tp->tl);
2518         }
2519 
2520         tp->rtl_ops.down(tp);
2521 
2522         return 0;
2523 }
2524 
2525 static int rtl8152_resume(struct usb_interface *intf)
2526 {
2527         struct r8152 *tp = usb_get_intfdata(intf);
2528 
2529         tp->rtl_ops.init(tp);
2530         netif_device_attach(tp->netdev);
2531         if (netif_running(tp->netdev)) {
2532                 rtl8152_set_speed(tp, AUTONEG_ENABLE,
2533                                 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
2534                                 DUPLEX_FULL);
2535                 tp->speed = 0;
2536                 netif_carrier_off(tp->netdev);
2537                 set_bit(WORK_ENABLE, &tp->flags);
2538                 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
2539                 tasklet_enable(&tp->tl);
2540         }
2541 
2542         return 0;
2543 }
2544 
2545 static void rtl8152_get_drvinfo(struct net_device *netdev,
2546                                 struct ethtool_drvinfo *info)
2547 {
2548         struct r8152 *tp = netdev_priv(netdev);
2549 
2550         strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN);
2551         strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN);
2552         usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
2553 }
2554 
2555 static
2556 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2557 {
2558         struct r8152 *tp = netdev_priv(netdev);
2559 
2560         if (!tp->mii.mdio_read)
2561                 return -EOPNOTSUPP;
2562 
2563         return mii_ethtool_gset(&tp->mii, cmd);
2564 }
2565 
2566 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2567 {
2568         struct r8152 *tp = netdev_priv(dev);
2569 
2570         return rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
2571 }
2572 
2573 static struct ethtool_ops ops = {
2574         .get_drvinfo = rtl8152_get_drvinfo,
2575         .get_settings = rtl8152_get_settings,
2576         .set_settings = rtl8152_set_settings,
2577         .get_link = ethtool_op_get_link,
2578 };
2579 
2580 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2581 {
2582         struct r8152 *tp = netdev_priv(netdev);
2583         struct mii_ioctl_data *data = if_mii(rq);
2584         int res = 0;
2585 
2586         switch (cmd) {
2587         case SIOCGMIIPHY:
2588                 data->phy_id = R8152_PHY_ID; /* Internal PHY */
2589                 break;
2590 
2591         case SIOCGMIIREG:
2592                 data->val_out = r8152_mdio_read(tp, data->reg_num);
2593                 break;
2594 
2595         case SIOCSMIIREG:
2596                 if (!capable(CAP_NET_ADMIN)) {
2597                         res = -EPERM;
2598                         break;
2599                 }
2600                 r8152_mdio_write(tp, data->reg_num, data->val_in);
2601                 break;
2602 
2603         default:
2604                 res = -EOPNOTSUPP;
2605         }
2606 
2607         return res;
2608 }
2609 
2610 static const struct net_device_ops rtl8152_netdev_ops = {
2611         .ndo_open               = rtl8152_open,
2612         .ndo_stop               = rtl8152_close,
2613         .ndo_do_ioctl           = rtl8152_ioctl,
2614         .ndo_start_xmit         = rtl8152_start_xmit,
2615         .ndo_tx_timeout         = rtl8152_tx_timeout,
2616         .ndo_set_rx_mode        = rtl8152_set_rx_mode,
2617         .ndo_set_mac_address    = rtl8152_set_mac_address,
2618 
2619         .ndo_change_mtu         = eth_change_mtu,
2620         .ndo_validate_addr      = eth_validate_addr,
2621 };
2622 
2623 static void r8152b_get_version(struct r8152 *tp)
2624 {
2625         u32     ocp_data;
2626         u16     version;
2627 
2628         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
2629         version = (u16)(ocp_data & VERSION_MASK);
2630 
2631         switch (version) {
2632         case 0x4c00:
2633                 tp->version = RTL_VER_01;
2634                 break;
2635         case 0x4c10:
2636                 tp->version = RTL_VER_02;
2637                 break;
2638         case 0x5c00:
2639                 tp->version = RTL_VER_03;
2640                 tp->mii.supports_gmii = 1;
2641                 break;
2642         case 0x5c10:
2643                 tp->version = RTL_VER_04;
2644                 tp->mii.supports_gmii = 1;
2645                 break;
2646         case 0x5c20:
2647                 tp->version = RTL_VER_05;
2648                 tp->mii.supports_gmii = 1;
2649                 break;
2650         default:
2651                 netif_info(tp, probe, tp->netdev,
2652                            "Unknown version 0x%04x\n", version);
2653                 break;
2654         }
2655 }
2656 
2657 static void rtl8152_unload(struct r8152 *tp)
2658 {
2659         u32     ocp_data;
2660 
2661         if (tp->version != RTL_VER_01) {
2662                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2663                 ocp_data |= POWER_CUT;
2664                 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2665         }
2666 
2667         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2668         ocp_data &= ~RESUME_INDICATE;
2669         ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2670 }
2671 
2672 static void rtl8153_unload(struct r8152 *tp)
2673 {
2674         r8153_power_cut_en(tp, 1);
2675 }
2676 
2677 static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id)
2678 {
2679         struct rtl_ops *ops = &tp->rtl_ops;
2680         int ret = -ENODEV;
2681 
2682         switch (id->idVendor) {
2683         case VENDOR_ID_REALTEK:
2684                 switch (id->idProduct) {
2685                 case PRODUCT_ID_RTL8152:
2686                         ops->init               = r8152b_init;
2687                         ops->enable             = rtl8152_enable;
2688                         ops->disable            = rtl8152_disable;
2689                         ops->down               = rtl8152_down;
2690                         ops->unload             = rtl8152_unload;
2691                         ret = 0;
2692                         break;
2693                 case PRODUCT_ID_RTL8153:
2694                         ops->init               = r8153_init;
2695                         ops->enable             = rtl8153_enable;
2696                         ops->disable            = rtl8152_disable;
2697                         ops->down               = rtl8153_down;
2698                         ops->unload             = rtl8153_unload;
2699                         ret = 0;
2700                         break;
2701                 default:
2702                         break;
2703                 }
2704                 break;
2705 
2706         case VENDOR_ID_SAMSUNG:
2707                 switch (id->idProduct) {
2708                 case PRODUCT_ID_SAMSUNG:
2709                         ops->init               = r8153_init;
2710                         ops->enable             = rtl8153_enable;
2711                         ops->disable            = rtl8152_disable;
2712                         ops->down               = rtl8153_down;
2713                         ops->unload             = rtl8153_unload;
2714                         ret = 0;
2715                         break;
2716                 default:
2717                         break;
2718                 }
2719                 break;
2720 
2721         default:
2722                 break;
2723         }
2724 
2725         if (ret)
2726                 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
2727 
2728         return ret;
2729 }
2730 
2731 static int rtl8152_probe(struct usb_interface *intf,
2732                          const struct usb_device_id *id)
2733 {
2734         struct usb_device *udev = interface_to_usbdev(intf);
2735         struct r8152 *tp;
2736         struct net_device *netdev;
2737         int ret;
2738 
2739         if (udev->actconfig->desc.bConfigurationValue != 1) {
2740                 usb_driver_set_configuration(udev, 1);
2741                 return -ENODEV;
2742         }
2743 
2744         usb_reset_device(udev);
2745         netdev = alloc_etherdev(sizeof(struct r8152));
2746         if (!netdev) {
2747                 dev_err(&intf->dev, "Out of memory\n");
2748                 return -ENOMEM;
2749         }
2750 
2751         SET_NETDEV_DEV(netdev, &intf->dev);
2752         tp = netdev_priv(netdev);
2753         tp->msg_enable = 0x7FFF;
2754 
2755         tp->udev = udev;
2756         tp->netdev = netdev;
2757         tp->intf = intf;
2758 
2759         ret = rtl_ops_init(tp, id);
2760         if (ret)
2761                 goto out;
2762 
2763         tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
2764         INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
2765 
2766         netdev->netdev_ops = &rtl8152_netdev_ops;
2767         netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
2768 
2769         netdev->features |= NETIF_F_IP_CSUM;
2770         netdev->hw_features = NETIF_F_IP_CSUM;
2771         SET_ETHTOOL_OPS(netdev, &ops);
2772 
2773         tp->mii.dev = netdev;
2774         tp->mii.mdio_read = read_mii_word;
2775         tp->mii.mdio_write = write_mii_word;
2776         tp->mii.phy_id_mask = 0x3f;
2777         tp->mii.reg_num_mask = 0x1f;
2778         tp->mii.phy_id = R8152_PHY_ID;
2779         tp->mii.supports_gmii = 0;
2780 
2781         r8152b_get_version(tp);
2782         tp->rtl_ops.init(tp);
2783         set_ethernet_addr(tp);
2784 
2785         ret = alloc_all_mem(tp);
2786         if (ret)
2787                 goto out;
2788 
2789         usb_set_intfdata(intf, tp);
2790 
2791         ret = register_netdev(netdev);
2792         if (ret != 0) {
2793                 netif_err(tp, probe, netdev, "couldn't register the device\n");
2794                 goto out1;
2795         }
2796 
2797         netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
2798 
2799         return 0;
2800 
2801 out1:
2802         usb_set_intfdata(intf, NULL);
2803 out:
2804         free_netdev(netdev);
2805         return ret;
2806 }
2807 
2808 static void rtl8152_disconnect(struct usb_interface *intf)
2809 {
2810         struct r8152 *tp = usb_get_intfdata(intf);
2811 
2812         usb_set_intfdata(intf, NULL);
2813         if (tp) {
2814                 set_bit(RTL8152_UNPLUG, &tp->flags);
2815                 tasklet_kill(&tp->tl);
2816                 unregister_netdev(tp->netdev);
2817                 tp->rtl_ops.unload(tp);
2818                 free_all_mem(tp);
2819                 free_netdev(tp->netdev);
2820         }
2821 }
2822 
2823 /* table of devices that work with this driver */
2824 static struct usb_device_id rtl8152_table[] = {
2825         {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
2826         {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)},
2827         {USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)},
2828         {}
2829 };
2830 
2831 MODULE_DEVICE_TABLE(usb, rtl8152_table);
2832 
2833 static struct usb_driver rtl8152_driver = {
2834         .name =         MODULENAME,
2835         .id_table =     rtl8152_table,
2836         .probe =        rtl8152_probe,
2837         .disconnect =   rtl8152_disconnect,
2838         .suspend =      rtl8152_suspend,
2839         .resume =       rtl8152_resume,
2840         .reset_resume = rtl8152_resume,
2841 };
2842 
2843 module_usb_driver(rtl8152_driver);
2844 
2845 MODULE_AUTHOR(DRIVER_AUTHOR);
2846 MODULE_DESCRIPTION(DRIVER_DESC);
2847 MODULE_LICENSE("GPL");
2848 

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