Version:  2.0.40 2.2.26 2.4.37 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6

Linux/drivers/net/usb/r8152.c

  1 /*
  2  *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
  3  *
  4  * This program is free software; you can redistribute it and/or
  5  * modify it under the terms of the GNU General Public License
  6  * version 2 as published by the Free Software Foundation.
  7  *
  8  */
  9 
 10 #include <linux/signal.h>
 11 #include <linux/slab.h>
 12 #include <linux/module.h>
 13 #include <linux/netdevice.h>
 14 #include <linux/etherdevice.h>
 15 #include <linux/mii.h>
 16 #include <linux/ethtool.h>
 17 #include <linux/usb.h>
 18 #include <linux/crc32.h>
 19 #include <linux/if_vlan.h>
 20 #include <linux/uaccess.h>
 21 #include <linux/list.h>
 22 #include <linux/ip.h>
 23 #include <linux/ipv6.h>
 24 #include <net/ip6_checksum.h>
 25 #include <uapi/linux/mdio.h>
 26 #include <linux/mdio.h>
 27 #include <linux/usb/cdc.h>
 28 #include <linux/suspend.h>
 29 
 30 /* Information for net-next */
 31 #define NETNEXT_VERSION         "08"
 32 
 33 /* Information for net */
 34 #define NET_VERSION             "3"
 35 
 36 #define DRIVER_VERSION          "v1." NETNEXT_VERSION "." NET_VERSION
 37 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
 38 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
 39 #define MODULENAME "r8152"
 40 
 41 #define R8152_PHY_ID            32
 42 
 43 #define PLA_IDR                 0xc000
 44 #define PLA_RCR                 0xc010
 45 #define PLA_RMS                 0xc016
 46 #define PLA_RXFIFO_CTRL0        0xc0a0
 47 #define PLA_RXFIFO_CTRL1        0xc0a4
 48 #define PLA_RXFIFO_CTRL2        0xc0a8
 49 #define PLA_DMY_REG0            0xc0b0
 50 #define PLA_FMC                 0xc0b4
 51 #define PLA_CFG_WOL             0xc0b6
 52 #define PLA_TEREDO_CFG          0xc0bc
 53 #define PLA_MAR                 0xcd00
 54 #define PLA_BACKUP              0xd000
 55 #define PAL_BDC_CR              0xd1a0
 56 #define PLA_TEREDO_TIMER        0xd2cc
 57 #define PLA_REALWOW_TIMER       0xd2e8
 58 #define PLA_LEDSEL              0xdd90
 59 #define PLA_LED_FEATURE         0xdd92
 60 #define PLA_PHYAR               0xde00
 61 #define PLA_BOOT_CTRL           0xe004
 62 #define PLA_GPHY_INTR_IMR       0xe022
 63 #define PLA_EEE_CR              0xe040
 64 #define PLA_EEEP_CR             0xe080
 65 #define PLA_MAC_PWR_CTRL        0xe0c0
 66 #define PLA_MAC_PWR_CTRL2       0xe0ca
 67 #define PLA_MAC_PWR_CTRL3       0xe0cc
 68 #define PLA_MAC_PWR_CTRL4       0xe0ce
 69 #define PLA_WDT6_CTRL           0xe428
 70 #define PLA_TCR0                0xe610
 71 #define PLA_TCR1                0xe612
 72 #define PLA_MTPS                0xe615
 73 #define PLA_TXFIFO_CTRL         0xe618
 74 #define PLA_RSTTALLY            0xe800
 75 #define PLA_CR                  0xe813
 76 #define PLA_CRWECR              0xe81c
 77 #define PLA_CONFIG12            0xe81e  /* CONFIG1, CONFIG2 */
 78 #define PLA_CONFIG34            0xe820  /* CONFIG3, CONFIG4 */
 79 #define PLA_CONFIG5             0xe822
 80 #define PLA_PHY_PWR             0xe84c
 81 #define PLA_OOB_CTRL            0xe84f
 82 #define PLA_CPCR                0xe854
 83 #define PLA_MISC_0              0xe858
 84 #define PLA_MISC_1              0xe85a
 85 #define PLA_OCP_GPHY_BASE       0xe86c
 86 #define PLA_TALLYCNT            0xe890
 87 #define PLA_SFF_STS_7           0xe8de
 88 #define PLA_PHYSTATUS           0xe908
 89 #define PLA_BP_BA               0xfc26
 90 #define PLA_BP_0                0xfc28
 91 #define PLA_BP_1                0xfc2a
 92 #define PLA_BP_2                0xfc2c
 93 #define PLA_BP_3                0xfc2e
 94 #define PLA_BP_4                0xfc30
 95 #define PLA_BP_5                0xfc32
 96 #define PLA_BP_6                0xfc34
 97 #define PLA_BP_7                0xfc36
 98 #define PLA_BP_EN               0xfc38
 99 
100 #define USB_USB2PHY             0xb41e
101 #define USB_SSPHYLINK2          0xb428
102 #define USB_U2P3_CTRL           0xb460
103 #define USB_CSR_DUMMY1          0xb464
104 #define USB_CSR_DUMMY2          0xb466
105 #define USB_DEV_STAT            0xb808
106 #define USB_CONNECT_TIMER       0xcbf8
107 #define USB_BURST_SIZE          0xcfc0
108 #define USB_USB_CTRL            0xd406
109 #define USB_PHY_CTRL            0xd408
110 #define USB_TX_AGG              0xd40a
111 #define USB_RX_BUF_TH           0xd40c
112 #define USB_USB_TIMER           0xd428
113 #define USB_RX_EARLY_TIMEOUT    0xd42c
114 #define USB_RX_EARLY_SIZE       0xd42e
115 #define USB_PM_CTRL_STATUS      0xd432
116 #define USB_TX_DMA              0xd434
117 #define USB_TOLERANCE           0xd490
118 #define USB_LPM_CTRL            0xd41a
119 #define USB_UPS_CTRL            0xd800
120 #define USB_MISC_0              0xd81a
121 #define USB_POWER_CUT           0xd80a
122 #define USB_AFE_CTRL2           0xd824
123 #define USB_WDT11_CTRL          0xe43c
124 #define USB_BP_BA               0xfc26
125 #define USB_BP_0                0xfc28
126 #define USB_BP_1                0xfc2a
127 #define USB_BP_2                0xfc2c
128 #define USB_BP_3                0xfc2e
129 #define USB_BP_4                0xfc30
130 #define USB_BP_5                0xfc32
131 #define USB_BP_6                0xfc34
132 #define USB_BP_7                0xfc36
133 #define USB_BP_EN               0xfc38
134 
135 /* OCP Registers */
136 #define OCP_ALDPS_CONFIG        0x2010
137 #define OCP_EEE_CONFIG1         0x2080
138 #define OCP_EEE_CONFIG2         0x2092
139 #define OCP_EEE_CONFIG3         0x2094
140 #define OCP_BASE_MII            0xa400
141 #define OCP_EEE_AR              0xa41a
142 #define OCP_EEE_DATA            0xa41c
143 #define OCP_PHY_STATUS          0xa420
144 #define OCP_POWER_CFG           0xa430
145 #define OCP_EEE_CFG             0xa432
146 #define OCP_SRAM_ADDR           0xa436
147 #define OCP_SRAM_DATA           0xa438
148 #define OCP_DOWN_SPEED          0xa442
149 #define OCP_EEE_ABLE            0xa5c4
150 #define OCP_EEE_ADV             0xa5d0
151 #define OCP_EEE_LPABLE          0xa5d2
152 #define OCP_PHY_STATE           0xa708          /* nway state for 8153 */
153 #define OCP_ADC_CFG             0xbc06
154 
155 /* SRAM Register */
156 #define SRAM_LPF_CFG            0x8012
157 #define SRAM_10M_AMP1           0x8080
158 #define SRAM_10M_AMP2           0x8082
159 #define SRAM_IMPEDANCE          0x8084
160 
161 /* PLA_RCR */
162 #define RCR_AAP                 0x00000001
163 #define RCR_APM                 0x00000002
164 #define RCR_AM                  0x00000004
165 #define RCR_AB                  0x00000008
166 #define RCR_ACPT_ALL            (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
167 
168 /* PLA_RXFIFO_CTRL0 */
169 #define RXFIFO_THR1_NORMAL      0x00080002
170 #define RXFIFO_THR1_OOB         0x01800003
171 
172 /* PLA_RXFIFO_CTRL1 */
173 #define RXFIFO_THR2_FULL        0x00000060
174 #define RXFIFO_THR2_HIGH        0x00000038
175 #define RXFIFO_THR2_OOB         0x0000004a
176 #define RXFIFO_THR2_NORMAL      0x00a0
177 
178 /* PLA_RXFIFO_CTRL2 */
179 #define RXFIFO_THR3_FULL        0x00000078
180 #define RXFIFO_THR3_HIGH        0x00000048
181 #define RXFIFO_THR3_OOB         0x0000005a
182 #define RXFIFO_THR3_NORMAL      0x0110
183 
184 /* PLA_TXFIFO_CTRL */
185 #define TXFIFO_THR_NORMAL       0x00400008
186 #define TXFIFO_THR_NORMAL2      0x01000008
187 
188 /* PLA_DMY_REG0 */
189 #define ECM_ALDPS               0x0002
190 
191 /* PLA_FMC */
192 #define FMC_FCR_MCU_EN          0x0001
193 
194 /* PLA_EEEP_CR */
195 #define EEEP_CR_EEEP_TX         0x0002
196 
197 /* PLA_WDT6_CTRL */
198 #define WDT6_SET_MODE           0x0010
199 
200 /* PLA_TCR0 */
201 #define TCR0_TX_EMPTY           0x0800
202 #define TCR0_AUTO_FIFO          0x0080
203 
204 /* PLA_TCR1 */
205 #define VERSION_MASK            0x7cf0
206 
207 /* PLA_MTPS */
208 #define MTPS_JUMBO              (12 * 1024 / 64)
209 #define MTPS_DEFAULT            (6 * 1024 / 64)
210 
211 /* PLA_RSTTALLY */
212 #define TALLY_RESET             0x0001
213 
214 /* PLA_CR */
215 #define CR_RST                  0x10
216 #define CR_RE                   0x08
217 #define CR_TE                   0x04
218 
219 /* PLA_CRWECR */
220 #define CRWECR_NORAML           0x00
221 #define CRWECR_CONFIG           0xc0
222 
223 /* PLA_OOB_CTRL */
224 #define NOW_IS_OOB              0x80
225 #define TXFIFO_EMPTY            0x20
226 #define RXFIFO_EMPTY            0x10
227 #define LINK_LIST_READY         0x02
228 #define DIS_MCU_CLROOB          0x01
229 #define FIFO_EMPTY              (TXFIFO_EMPTY | RXFIFO_EMPTY)
230 
231 /* PLA_MISC_1 */
232 #define RXDY_GATED_EN           0x0008
233 
234 /* PLA_SFF_STS_7 */
235 #define RE_INIT_LL              0x8000
236 #define MCU_BORW_EN             0x4000
237 
238 /* PLA_CPCR */
239 #define CPCR_RX_VLAN            0x0040
240 
241 /* PLA_CFG_WOL */
242 #define MAGIC_EN                0x0001
243 
244 /* PLA_TEREDO_CFG */
245 #define TEREDO_SEL              0x8000
246 #define TEREDO_WAKE_MASK        0x7f00
247 #define TEREDO_RS_EVENT_MASK    0x00fe
248 #define OOB_TEREDO_EN           0x0001
249 
250 /* PAL_BDC_CR */
251 #define ALDPS_PROXY_MODE        0x0001
252 
253 /* PLA_CONFIG34 */
254 #define LINK_ON_WAKE_EN         0x0010
255 #define LINK_OFF_WAKE_EN        0x0008
256 
257 /* PLA_CONFIG5 */
258 #define BWF_EN                  0x0040
259 #define MWF_EN                  0x0020
260 #define UWF_EN                  0x0010
261 #define LAN_WAKE_EN             0x0002
262 
263 /* PLA_LED_FEATURE */
264 #define LED_MODE_MASK           0x0700
265 
266 /* PLA_PHY_PWR */
267 #define TX_10M_IDLE_EN          0x0080
268 #define PFM_PWM_SWITCH          0x0040
269 
270 /* PLA_MAC_PWR_CTRL */
271 #define D3_CLK_GATED_EN         0x00004000
272 #define MCU_CLK_RATIO           0x07010f07
273 #define MCU_CLK_RATIO_MASK      0x0f0f0f0f
274 #define ALDPS_SPDWN_RATIO       0x0f87
275 
276 /* PLA_MAC_PWR_CTRL2 */
277 #define EEE_SPDWN_RATIO         0x8007
278 
279 /* PLA_MAC_PWR_CTRL3 */
280 #define PKT_AVAIL_SPDWN_EN      0x0100
281 #define SUSPEND_SPDWN_EN        0x0004
282 #define U1U2_SPDWN_EN           0x0002
283 #define L1_SPDWN_EN             0x0001
284 
285 /* PLA_MAC_PWR_CTRL4 */
286 #define PWRSAVE_SPDWN_EN        0x1000
287 #define RXDV_SPDWN_EN           0x0800
288 #define TX10MIDLE_EN            0x0100
289 #define TP100_SPDWN_EN          0x0020
290 #define TP500_SPDWN_EN          0x0010
291 #define TP1000_SPDWN_EN         0x0008
292 #define EEE_SPDWN_EN            0x0001
293 
294 /* PLA_GPHY_INTR_IMR */
295 #define GPHY_STS_MSK            0x0001
296 #define SPEED_DOWN_MSK          0x0002
297 #define SPDWN_RXDV_MSK          0x0004
298 #define SPDWN_LINKCHG_MSK       0x0008
299 
300 /* PLA_PHYAR */
301 #define PHYAR_FLAG              0x80000000
302 
303 /* PLA_EEE_CR */
304 #define EEE_RX_EN               0x0001
305 #define EEE_TX_EN               0x0002
306 
307 /* PLA_BOOT_CTRL */
308 #define AUTOLOAD_DONE           0x0002
309 
310 /* USB_USB2PHY */
311 #define USB2PHY_SUSPEND         0x0001
312 #define USB2PHY_L1              0x0002
313 
314 /* USB_SSPHYLINK2 */
315 #define pwd_dn_scale_mask       0x3ffe
316 #define pwd_dn_scale(x)         ((x) << 1)
317 
318 /* USB_CSR_DUMMY1 */
319 #define DYNAMIC_BURST           0x0001
320 
321 /* USB_CSR_DUMMY2 */
322 #define EP4_FULL_FC             0x0001
323 
324 /* USB_DEV_STAT */
325 #define STAT_SPEED_MASK         0x0006
326 #define STAT_SPEED_HIGH         0x0000
327 #define STAT_SPEED_FULL         0x0002
328 
329 /* USB_TX_AGG */
330 #define TX_AGG_MAX_THRESHOLD    0x03
331 
332 /* USB_RX_BUF_TH */
333 #define RX_THR_SUPPER           0x0c350180
334 #define RX_THR_HIGH             0x7a120180
335 #define RX_THR_SLOW             0xffff0180
336 
337 /* USB_TX_DMA */
338 #define TEST_MODE_DISABLE       0x00000001
339 #define TX_SIZE_ADJUST1         0x00000100
340 
341 /* USB_UPS_CTRL */
342 #define POWER_CUT               0x0100
343 
344 /* USB_PM_CTRL_STATUS */
345 #define RESUME_INDICATE         0x0001
346 
347 /* USB_USB_CTRL */
348 #define RX_AGG_DISABLE          0x0010
349 #define RX_ZERO_EN              0x0080
350 
351 /* USB_U2P3_CTRL */
352 #define U2P3_ENABLE             0x0001
353 
354 /* USB_POWER_CUT */
355 #define PWR_EN                  0x0001
356 #define PHASE2_EN               0x0008
357 
358 /* USB_MISC_0 */
359 #define PCUT_STATUS             0x0001
360 
361 /* USB_RX_EARLY_TIMEOUT */
362 #define COALESCE_SUPER           85000U
363 #define COALESCE_HIGH           250000U
364 #define COALESCE_SLOW           524280U
365 
366 /* USB_WDT11_CTRL */
367 #define TIMER11_EN              0x0001
368 
369 /* USB_LPM_CTRL */
370 /* bit 4 ~ 5: fifo empty boundary */
371 #define FIFO_EMPTY_1FB          0x30    /* 0x1fb * 64 = 32448 bytes */
372 /* bit 2 ~ 3: LMP timer */
373 #define LPM_TIMER_MASK          0x0c
374 #define LPM_TIMER_500MS         0x04    /* 500 ms */
375 #define LPM_TIMER_500US         0x0c    /* 500 us */
376 #define ROK_EXIT_LPM            0x02
377 
378 /* USB_AFE_CTRL2 */
379 #define SEN_VAL_MASK            0xf800
380 #define SEN_VAL_NORMAL          0xa000
381 #define SEL_RXIDLE              0x0100
382 
383 /* OCP_ALDPS_CONFIG */
384 #define ENPWRSAVE               0x8000
385 #define ENPDNPS                 0x0200
386 #define LINKENA                 0x0100
387 #define DIS_SDSAVE              0x0010
388 
389 /* OCP_PHY_STATUS */
390 #define PHY_STAT_MASK           0x0007
391 #define PHY_STAT_LAN_ON         3
392 #define PHY_STAT_PWRDN          5
393 
394 /* OCP_POWER_CFG */
395 #define EEE_CLKDIV_EN           0x8000
396 #define EN_ALDPS                0x0004
397 #define EN_10M_PLLOFF           0x0001
398 
399 /* OCP_EEE_CONFIG1 */
400 #define RG_TXLPI_MSK_HFDUP      0x8000
401 #define RG_MATCLR_EN            0x4000
402 #define EEE_10_CAP              0x2000
403 #define EEE_NWAY_EN             0x1000
404 #define TX_QUIET_EN             0x0200
405 #define RX_QUIET_EN             0x0100
406 #define sd_rise_time_mask       0x0070
407 #define sd_rise_time(x)         (min(x, 7) << 4)        /* bit 4 ~ 6 */
408 #define RG_RXLPI_MSK_HFDUP      0x0008
409 #define SDFALLTIME              0x0007  /* bit 0 ~ 2 */
410 
411 /* OCP_EEE_CONFIG2 */
412 #define RG_LPIHYS_NUM           0x7000  /* bit 12 ~ 15 */
413 #define RG_DACQUIET_EN          0x0400
414 #define RG_LDVQUIET_EN          0x0200
415 #define RG_CKRSEL               0x0020
416 #define RG_EEEPRG_EN            0x0010
417 
418 /* OCP_EEE_CONFIG3 */
419 #define fast_snr_mask           0xff80
420 #define fast_snr(x)             (min(x, 0x1ff) << 7)    /* bit 7 ~ 15 */
421 #define RG_LFS_SEL              0x0060  /* bit 6 ~ 5 */
422 #define MSK_PH                  0x0006  /* bit 0 ~ 3 */
423 
424 /* OCP_EEE_AR */
425 /* bit[15:14] function */
426 #define FUN_ADDR                0x0000
427 #define FUN_DATA                0x4000
428 /* bit[4:0] device addr */
429 
430 /* OCP_EEE_CFG */
431 #define CTAP_SHORT_EN           0x0040
432 #define EEE10_EN                0x0010
433 
434 /* OCP_DOWN_SPEED */
435 #define EN_10M_BGOFF            0x0080
436 
437 /* OCP_PHY_STATE */
438 #define TXDIS_STATE             0x01
439 #define ABD_STATE               0x02
440 
441 /* OCP_ADC_CFG */
442 #define CKADSEL_L               0x0100
443 #define ADC_EN                  0x0080
444 #define EN_EMI_L                0x0040
445 
446 /* SRAM_LPF_CFG */
447 #define LPF_AUTO_TUNE           0x8000
448 
449 /* SRAM_10M_AMP1 */
450 #d