Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5

Linux/drivers/net/phy/mdio-octeon.c

  1 /*
  2  * This file is subject to the terms and conditions of the GNU General Public
  3  * License.  See the file "COPYING" in the main directory of this archive
  4  * for more details.
  5  *
  6  * Copyright (C) 2009-2012 Cavium, Inc.
  7  */
  8 
  9 #include <linux/platform_device.h>
 10 #include <linux/of_address.h>
 11 #include <linux/of_mdio.h>
 12 #include <linux/delay.h>
 13 #include <linux/module.h>
 14 #include <linux/gfp.h>
 15 #include <linux/phy.h>
 16 #include <linux/io.h>
 17 
 18 #ifdef CONFIG_CAVIUM_OCTEON_SOC
 19 #include <asm/octeon/octeon.h>
 20 #endif
 21 
 22 #define DRV_VERSION "1.1"
 23 #define DRV_DESCRIPTION "Cavium Networks Octeon/ThunderX SMI/MDIO driver"
 24 
 25 #define SMI_CMD         0x0
 26 #define SMI_WR_DAT      0x8
 27 #define SMI_RD_DAT      0x10
 28 #define SMI_CLK         0x18
 29 #define SMI_EN          0x20
 30 
 31 #ifdef __BIG_ENDIAN_BITFIELD
 32 #define OCT_MDIO_BITFIELD_FIELD(field, more)    \
 33         field;                                  \
 34         more
 35 
 36 #else
 37 #define OCT_MDIO_BITFIELD_FIELD(field, more)    \
 38         more                                    \
 39         field;
 40 
 41 #endif
 42 
 43 union cvmx_smix_clk {
 44         u64 u64;
 45         struct cvmx_smix_clk_s {
 46           OCT_MDIO_BITFIELD_FIELD(u64 reserved_25_63:39,
 47           OCT_MDIO_BITFIELD_FIELD(u64 mode:1,
 48           OCT_MDIO_BITFIELD_FIELD(u64 reserved_21_23:3,
 49           OCT_MDIO_BITFIELD_FIELD(u64 sample_hi:5,
 50           OCT_MDIO_BITFIELD_FIELD(u64 sample_mode:1,
 51           OCT_MDIO_BITFIELD_FIELD(u64 reserved_14_14:1,
 52           OCT_MDIO_BITFIELD_FIELD(u64 clk_idle:1,
 53           OCT_MDIO_BITFIELD_FIELD(u64 preamble:1,
 54           OCT_MDIO_BITFIELD_FIELD(u64 sample:4,
 55           OCT_MDIO_BITFIELD_FIELD(u64 phase:8,
 56           ;))))))))))
 57         } s;
 58 };
 59 
 60 union cvmx_smix_cmd {
 61         u64 u64;
 62         struct cvmx_smix_cmd_s {
 63           OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
 64           OCT_MDIO_BITFIELD_FIELD(u64 phy_op:2,
 65           OCT_MDIO_BITFIELD_FIELD(u64 reserved_13_15:3,
 66           OCT_MDIO_BITFIELD_FIELD(u64 phy_adr:5,
 67           OCT_MDIO_BITFIELD_FIELD(u64 reserved_5_7:3,
 68           OCT_MDIO_BITFIELD_FIELD(u64 reg_adr:5,
 69           ;))))))
 70         } s;
 71 };
 72 
 73 union cvmx_smix_en {
 74         u64 u64;
 75         struct cvmx_smix_en_s {
 76           OCT_MDIO_BITFIELD_FIELD(u64 reserved_1_63:63,
 77           OCT_MDIO_BITFIELD_FIELD(u64 en:1,
 78           ;))
 79         } s;
 80 };
 81 
 82 union cvmx_smix_rd_dat {
 83         u64 u64;
 84         struct cvmx_smix_rd_dat_s {
 85           OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
 86           OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
 87           OCT_MDIO_BITFIELD_FIELD(u64 val:1,
 88           OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
 89           ;))))
 90         } s;
 91 };
 92 
 93 union cvmx_smix_wr_dat {
 94         u64 u64;
 95         struct cvmx_smix_wr_dat_s {
 96           OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
 97           OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
 98           OCT_MDIO_BITFIELD_FIELD(u64 val:1,
 99           OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
100           ;))))
101         } s;
102 };
103 
104 enum octeon_mdiobus_mode {
105         UNINIT = 0,
106         C22,
107         C45
108 };
109 
110 struct octeon_mdiobus {
111         struct mii_bus *mii_bus;
112         u64 register_base;
113         resource_size_t mdio_phys;
114         resource_size_t regsize;
115         enum octeon_mdiobus_mode mode;
116 };
117 
118 #ifdef CONFIG_CAVIUM_OCTEON_SOC
119 static void oct_mdio_writeq(u64 val, u64 addr)
120 {
121         cvmx_write_csr(addr, val);
122 }
123 
124 static u64 oct_mdio_readq(u64 addr)
125 {
126         return cvmx_read_csr(addr);
127 }
128 #else
129 #define oct_mdio_writeq(val, addr)      writeq_relaxed(val, (void *)addr)
130 #define oct_mdio_readq(addr)            readq_relaxed((void *)addr)
131 #endif
132 
133 static void octeon_mdiobus_set_mode(struct octeon_mdiobus *p,
134                                     enum octeon_mdiobus_mode m)
135 {
136         union cvmx_smix_clk smi_clk;
137 
138         if (m == p->mode)
139                 return;
140 
141         smi_clk.u64 = oct_mdio_readq(p->register_base + SMI_CLK);
142         smi_clk.s.mode = (m == C45) ? 1 : 0;
143         smi_clk.s.preamble = 1;
144         oct_mdio_writeq(smi_clk.u64, p->register_base + SMI_CLK);
145         p->mode = m;
146 }
147 
148 static int octeon_mdiobus_c45_addr(struct octeon_mdiobus *p,
149                                    int phy_id, int regnum)
150 {
151         union cvmx_smix_cmd smi_cmd;
152         union cvmx_smix_wr_dat smi_wr;
153         int timeout = 1000;
154 
155         octeon_mdiobus_set_mode(p, C45);
156 
157         smi_wr.u64 = 0;
158         smi_wr.s.dat = regnum & 0xffff;
159         oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);
160 
161         regnum = (regnum >> 16) & 0x1f;
162 
163         smi_cmd.u64 = 0;
164         smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_45_ADDRESS */
165         smi_cmd.s.phy_adr = phy_id;
166         smi_cmd.s.reg_adr = regnum;
167         oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
168 
169         do {
170                 /* Wait 1000 clocks so we don't saturate the RSL bus
171                  * doing reads.
172                  */
173                 __delay(1000);
174                 smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT);
175         } while (smi_wr.s.pending && --timeout);
176 
177         if (timeout <= 0)
178                 return -EIO;
179         return 0;
180 }
181 
182 static int octeon_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum)
183 {
184         struct octeon_mdiobus *p = bus->priv;
185         union cvmx_smix_cmd smi_cmd;
186         union cvmx_smix_rd_dat smi_rd;
187         unsigned int op = 1; /* MDIO_CLAUSE_22_READ */
188         int timeout = 1000;
189 
190         if (regnum & MII_ADDR_C45) {
191                 int r = octeon_mdiobus_c45_addr(p, phy_id, regnum);
192                 if (r < 0)
193                         return r;
194 
195                 regnum = (regnum >> 16) & 0x1f;
196                 op = 3; /* MDIO_CLAUSE_45_READ */
197         } else {
198                 octeon_mdiobus_set_mode(p, C22);
199         }
200 
201 
202         smi_cmd.u64 = 0;
203         smi_cmd.s.phy_op = op;
204         smi_cmd.s.phy_adr = phy_id;
205         smi_cmd.s.reg_adr = regnum;
206         oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
207 
208         do {
209                 /* Wait 1000 clocks so we don't saturate the RSL bus
210                  * doing reads.
211                  */
212                 __delay(1000);
213                 smi_rd.u64 = oct_mdio_readq(p->register_base + SMI_RD_DAT);
214         } while (smi_rd.s.pending && --timeout);
215 
216         if (smi_rd.s.val)
217                 return smi_rd.s.dat;
218         else
219                 return -EIO;
220 }
221 
222 static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id,
223                                 int regnum, u16 val)
224 {
225         struct octeon_mdiobus *p = bus->priv;
226         union cvmx_smix_cmd smi_cmd;
227         union cvmx_smix_wr_dat smi_wr;
228         unsigned int op = 0; /* MDIO_CLAUSE_22_WRITE */
229         int timeout = 1000;
230 
231 
232         if (regnum & MII_ADDR_C45) {
233                 int r = octeon_mdiobus_c45_addr(p, phy_id, regnum);
234                 if (r < 0)
235                         return r;
236 
237                 regnum = (regnum >> 16) & 0x1f;
238                 op = 1; /* MDIO_CLAUSE_45_WRITE */
239         } else {
240                 octeon_mdiobus_set_mode(p, C22);
241         }
242 
243         smi_wr.u64 = 0;
244         smi_wr.s.dat = val;
245         oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);
246 
247         smi_cmd.u64 = 0;
248         smi_cmd.s.phy_op = op;
249         smi_cmd.s.phy_adr = phy_id;
250         smi_cmd.s.reg_adr = regnum;
251         oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
252 
253         do {
254                 /* Wait 1000 clocks so we don't saturate the RSL bus
255                  * doing reads.
256                  */
257                 __delay(1000);
258                 smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT);
259         } while (smi_wr.s.pending && --timeout);
260 
261         if (timeout <= 0)
262                 return -EIO;
263 
264         return 0;
265 }
266 
267 static int octeon_mdiobus_probe(struct platform_device *pdev)
268 {
269         struct octeon_mdiobus *bus;
270         struct mii_bus *mii_bus;
271         struct resource *res_mem;
272         union cvmx_smix_en smi_en;
273         int err = -ENOENT;
274 
275         mii_bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*bus));
276         if (!mii_bus)
277                 return -ENOMEM;
278 
279         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
280         if (res_mem == NULL) {
281                 dev_err(&pdev->dev, "found no memory resource\n");
282                 return -ENXIO;
283         }
284 
285         bus = mii_bus->priv;
286         bus->mii_bus = mii_bus;
287         bus->mdio_phys = res_mem->start;
288         bus->regsize = resource_size(res_mem);
289 
290         if (!devm_request_mem_region(&pdev->dev, bus->mdio_phys, bus->regsize,
291                                      res_mem->name)) {
292                 dev_err(&pdev->dev, "request_mem_region failed\n");
293                 return -ENXIO;
294         }
295 
296         bus->register_base =
297                 (u64)devm_ioremap(&pdev->dev, bus->mdio_phys, bus->regsize);
298         if (!bus->register_base) {
299                 dev_err(&pdev->dev, "dev_ioremap failed\n");
300                 return -ENOMEM;
301         }
302 
303         smi_en.u64 = 0;
304         smi_en.s.en = 1;
305         oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);
306 
307         bus->mii_bus->priv = bus;
308         bus->mii_bus->name = "mdio-octeon";
309         snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%llx", bus->register_base);
310         bus->mii_bus->parent = &pdev->dev;
311 
312         bus->mii_bus->read = octeon_mdiobus_read;
313         bus->mii_bus->write = octeon_mdiobus_write;
314 
315         platform_set_drvdata(pdev, bus);
316 
317         err = of_mdiobus_register(bus->mii_bus, pdev->dev.of_node);
318         if (err)
319                 goto fail_register;
320 
321         dev_info(&pdev->dev, "Version " DRV_VERSION "\n");
322 
323         return 0;
324 fail_register:
325         mdiobus_free(bus->mii_bus);
326         smi_en.u64 = 0;
327         oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);
328         return err;
329 }
330 
331 static int octeon_mdiobus_remove(struct platform_device *pdev)
332 {
333         struct octeon_mdiobus *bus;
334         union cvmx_smix_en smi_en;
335 
336         bus = platform_get_drvdata(pdev);
337 
338         mdiobus_unregister(bus->mii_bus);
339         mdiobus_free(bus->mii_bus);
340         smi_en.u64 = 0;
341         oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);
342         return 0;
343 }
344 
345 static const struct of_device_id octeon_mdiobus_match[] = {
346         {
347                 .compatible = "cavium,octeon-3860-mdio",
348         },
349         {},
350 };
351 MODULE_DEVICE_TABLE(of, octeon_mdiobus_match);
352 
353 static struct platform_driver octeon_mdiobus_driver = {
354         .driver = {
355                 .name           = "mdio-octeon",
356                 .of_match_table = octeon_mdiobus_match,
357         },
358         .probe          = octeon_mdiobus_probe,
359         .remove         = octeon_mdiobus_remove,
360 };
361 
362 void octeon_mdiobus_force_mod_depencency(void)
363 {
364         /* Let ethernet drivers force us to be loaded.  */
365 }
366 EXPORT_SYMBOL(octeon_mdiobus_force_mod_depencency);
367 
368 module_platform_driver(octeon_mdiobus_driver);
369 
370 MODULE_DESCRIPTION(DRV_DESCRIPTION);
371 MODULE_VERSION(DRV_VERSION);
372 MODULE_AUTHOR("David Daney");
373 MODULE_LICENSE("GPL");
374 

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