Version:  2.0.40 2.2.26 2.4.37 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9

Linux/drivers/net/ethernet/xilinx/xilinx_axienet_main.c

  1 /*
  2  * Xilinx Axi Ethernet device driver
  3  *
  4  * Copyright (c) 2008 Nissin Systems Co., Ltd.,  Yoshio Kashiwagi
  5  * Copyright (c) 2005-2008 DLA Systems,  David H. Lynch Jr. <dhlii@dlasys.net>
  6  * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
  7  * Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu>
  8  * Copyright (c) 2010 - 2011 PetaLogix
  9  * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
 10  *
 11  * This is a driver for the Xilinx Axi Ethernet which is used in the Virtex6
 12  * and Spartan6.
 13  *
 14  * TODO:
 15  *  - Add Axi Fifo support.
 16  *  - Factor out Axi DMA code into separate driver.
 17  *  - Test and fix basic multicast filtering.
 18  *  - Add support for extended multicast filtering.
 19  *  - Test basic VLAN support.
 20  *  - Add support for extended VLAN support.
 21  */
 22 
 23 #include <linux/delay.h>
 24 #include <linux/etherdevice.h>
 25 #include <linux/module.h>
 26 #include <linux/netdevice.h>
 27 #include <linux/of_mdio.h>
 28 #include <linux/of_platform.h>
 29 #include <linux/of_irq.h>
 30 #include <linux/of_address.h>
 31 #include <linux/skbuff.h>
 32 #include <linux/spinlock.h>
 33 #include <linux/phy.h>
 34 #include <linux/mii.h>
 35 #include <linux/ethtool.h>
 36 
 37 #include "xilinx_axienet.h"
 38 
 39 /* Descriptors defines for Tx and Rx DMA - 2^n for the best performance */
 40 #define TX_BD_NUM               64
 41 #define RX_BD_NUM               128
 42 
 43 /* Must be shorter than length of ethtool_drvinfo.driver field to fit */
 44 #define DRIVER_NAME             "xaxienet"
 45 #define DRIVER_DESCRIPTION      "Xilinx Axi Ethernet driver"
 46 #define DRIVER_VERSION          "1.00a"
 47 
 48 #define AXIENET_REGS_N          32
 49 
 50 /* Match table for of_platform binding */
 51 static const struct of_device_id axienet_of_match[] = {
 52         { .compatible = "xlnx,axi-ethernet-1.00.a", },
 53         { .compatible = "xlnx,axi-ethernet-1.01.a", },
 54         { .compatible = "xlnx,axi-ethernet-2.01.a", },
 55         {},
 56 };
 57 
 58 MODULE_DEVICE_TABLE(of, axienet_of_match);
 59 
 60 /* Option table for setting up Axi Ethernet hardware options */
 61 static struct axienet_option axienet_options[] = {
 62         /* Turn on jumbo packet support for both Rx and Tx */
 63         {
 64                 .opt = XAE_OPTION_JUMBO,
 65                 .reg = XAE_TC_OFFSET,
 66                 .m_or = XAE_TC_JUM_MASK,
 67         }, {
 68                 .opt = XAE_OPTION_JUMBO,
 69                 .reg = XAE_RCW1_OFFSET,
 70                 .m_or = XAE_RCW1_JUM_MASK,
 71         }, { /* Turn on VLAN packet support for both Rx and Tx */
 72                 .opt = XAE_OPTION_VLAN,
 73                 .reg = XAE_TC_OFFSET,
 74                 .m_or = XAE_TC_VLAN_MASK,
 75         }, {
 76                 .opt = XAE_OPTION_VLAN,
 77                 .reg = XAE_RCW1_OFFSET,
 78                 .m_or = XAE_RCW1_VLAN_MASK,
 79         }, { /* Turn on FCS stripping on receive packets */
 80                 .opt = XAE_OPTION_FCS_STRIP,
 81                 .reg = XAE_RCW1_OFFSET,
 82                 .m_or = XAE_RCW1_FCS_MASK,
 83         }, { /* Turn on FCS insertion on transmit packets */
 84                 .opt = XAE_OPTION_FCS_INSERT,
 85                 .reg = XAE_TC_OFFSET,
 86                 .m_or = XAE_TC_FCS_MASK,
 87         }, { /* Turn off length/type field checking on receive packets */
 88                 .opt = XAE_OPTION_LENTYPE_ERR,
 89                 .reg = XAE_RCW1_OFFSET,
 90                 .m_or = XAE_RCW1_LT_DIS_MASK,
 91         }, { /* Turn on Rx flow control */
 92                 .opt = XAE_OPTION_FLOW_CONTROL,
 93                 .reg = XAE_FCC_OFFSET,
 94                 .m_or = XAE_FCC_FCRX_MASK,
 95         }, { /* Turn on Tx flow control */
 96                 .opt = XAE_OPTION_FLOW_CONTROL,
 97                 .reg = XAE_FCC_OFFSET,
 98                 .m_or = XAE_FCC_FCTX_MASK,
 99         }, { /* Turn on promiscuous frame filtering */
100                 .opt = XAE_OPTION_PROMISC,
101                 .reg = XAE_FMI_OFFSET,
102                 .m_or = XAE_FMI_PM_MASK,
103         }, { /* Enable transmitter */
104                 .opt = XAE_OPTION_TXEN,
105                 .reg = XAE_TC_OFFSET,
106                 .m_or = XAE_TC_TX_MASK,
107         }, { /* Enable receiver */
108                 .opt = XAE_OPTION_RXEN,
109                 .reg = XAE_RCW1_OFFSET,
110                 .m_or = XAE_RCW1_RX_MASK,
111         },
112         {}
113 };
114 
115 /**
116  * axienet_dma_in32 - Memory mapped Axi DMA register read
117  * @lp:         Pointer to axienet local structure
118  * @reg:        Address offset from the base address of the Axi DMA core
119  *
120  * Return: The contents of the Axi DMA register
121  *
122  * This function returns the contents of the corresponding Axi DMA register.
123  */
124 static inline u32 axienet_dma_in32(struct axienet_local *lp, off_t reg)
125 {
126         return in_be32(lp->dma_regs + reg);
127 }
128 
129 /**
130  * axienet_dma_out32 - Memory mapped Axi DMA register write.
131  * @lp:         Pointer to axienet local structure
132  * @reg:        Address offset from the base address of the Axi DMA core
133  * @value:      Value to be written into the Axi DMA register
134  *
135  * This function writes the desired value into the corresponding Axi DMA
136  * register.
137  */
138 static inline void axienet_dma_out32(struct axienet_local *lp,
139                                      off_t reg, u32 value)
140 {
141         out_be32((lp->dma_regs + reg), value);
142 }
143 
144 /**
145  * axienet_dma_bd_release - Release buffer descriptor rings
146  * @ndev:       Pointer to the net_device structure
147  *
148  * This function is used to release the descriptors allocated in
149  * axienet_dma_bd_init. axienet_dma_bd_release is called when Axi Ethernet
150  * driver stop api is called.
151  */
152 static void axienet_dma_bd_release(struct net_device *ndev)
153 {
154         int i;
155         struct axienet_local *lp = netdev_priv(ndev);
156 
157         for (i = 0; i < RX_BD_NUM; i++) {
158                 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
159                                  lp->max_frm_size, DMA_FROM_DEVICE);
160                 dev_kfree_skb((struct sk_buff *)
161                               (lp->rx_bd_v[i].sw_id_offset));
162         }
163 
164         if (lp->rx_bd_v) {
165                 dma_free_coherent(ndev->dev.parent,
166                                   sizeof(*lp->rx_bd_v) * RX_BD_NUM,
167                                   lp->rx_bd_v,
168                                   lp->rx_bd_p);
169         }
170         if (lp->tx_bd_v) {
171                 dma_free_coherent(ndev->dev.parent,
172                                   sizeof(*lp->tx_bd_v) * TX_BD_NUM,
173                                   lp->tx_bd_v,
174                                   lp->tx_bd_p);
175         }
176 }
177 
178 /**
179  * axienet_dma_bd_init - Setup buffer descriptor rings for Axi DMA
180  * @ndev:       Pointer to the net_device structure
181  *
182  * Return: 0, on success -ENOMEM, on failure
183  *
184  * This function is called to initialize the Rx and Tx DMA descriptor
185  * rings. This initializes the descriptors with required default values
186  * and is called when Axi Ethernet driver reset is called.
187  */
188 static int axienet_dma_bd_init(struct net_device *ndev)
189 {
190         u32 cr;
191         int i;
192         struct sk_buff *skb;
193         struct axienet_local *lp = netdev_priv(ndev);
194 
195         /* Reset the indexes which are used for accessing the BDs */
196         lp->tx_bd_ci = 0;
197         lp->tx_bd_tail = 0;
198         lp->rx_bd_ci = 0;
199 
200         /* Allocate the Tx and Rx buffer descriptors. */
201         lp->tx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
202                                           sizeof(*lp->tx_bd_v) * TX_BD_NUM,
203                                           &lp->tx_bd_p, GFP_KERNEL);
204         if (!lp->tx_bd_v)
205                 goto out;
206 
207         lp->rx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
208                                           sizeof(*lp->rx_bd_v) * RX_BD_NUM,
209                                           &lp->rx_bd_p, GFP_KERNEL);
210         if (!lp->rx_bd_v)
211                 goto out;
212 
213         for (i = 0; i < TX_BD_NUM; i++) {
214                 lp->tx_bd_v[i].next = lp->tx_bd_p +
215                                       sizeof(*lp->tx_bd_v) *
216                                       ((i + 1) % TX_BD_NUM);
217         }
218 
219         for (i = 0; i < RX_BD_NUM; i++) {
220                 lp->rx_bd_v[i].next = lp->rx_bd_p +
221                                       sizeof(*lp->rx_bd_v) *
222                                       ((i + 1) % RX_BD_NUM);
223 
224                 skb = netdev_alloc_skb_ip_align(ndev, lp->max_frm_size);
225                 if (!skb)
226                         goto out;
227 
228                 lp->rx_bd_v[i].sw_id_offset = (u32) skb;
229                 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
230                                                      skb->data,
231                                                      lp->max_frm_size,
232                                                      DMA_FROM_DEVICE);
233                 lp->rx_bd_v[i].cntrl = lp->max_frm_size;
234         }
235 
236         /* Start updating the Rx channel control register */
237         cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
238         /* Update the interrupt coalesce count */
239         cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
240               ((lp->coalesce_count_rx) << XAXIDMA_COALESCE_SHIFT));
241         /* Update the delay timer count */
242         cr = ((cr & ~XAXIDMA_DELAY_MASK) |
243               (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
244         /* Enable coalesce, delay timer and error interrupts */
245         cr |= XAXIDMA_IRQ_ALL_MASK;
246         /* Write to the Rx channel control register */
247         axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
248 
249         /* Start updating the Tx channel control register */
250         cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
251         /* Update the interrupt coalesce count */
252         cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
253               ((lp->coalesce_count_tx) << XAXIDMA_COALESCE_SHIFT));
254         /* Update the delay timer count */
255         cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
256               (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
257         /* Enable coalesce, delay timer and error interrupts */
258         cr |= XAXIDMA_IRQ_ALL_MASK;
259         /* Write to the Tx channel control register */
260         axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
261 
262         /* Populate the tail pointer and bring the Rx Axi DMA engine out of
263          * halted state. This will make the Rx side ready for reception.
264          */
265         axienet_dma_out32(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
266         cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
267         axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
268                           cr | XAXIDMA_CR_RUNSTOP_MASK);
269         axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
270                           (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
271 
272         /* Write to the RS (Run-stop) bit in the Tx channel control register.
273          * Tx channel is now ready to run. But only after we write to the
274          * tail pointer register that the Tx channel will start transmitting.
275          */
276         axienet_dma_out32(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
277         cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
278         axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
279                           cr | XAXIDMA_CR_RUNSTOP_MASK);
280 
281         return 0;
282 out:
283         axienet_dma_bd_release(ndev);
284         return -ENOMEM;
285 }
286 
287 /**
288  * axienet_set_mac_address - Write the MAC address
289  * @ndev:       Pointer to the net_device structure
290  * @address:    6 byte Address to be written as MAC address
291  *
292  * This function is called to initialize the MAC address of the Axi Ethernet
293  * core. It writes to the UAW0 and UAW1 registers of the core.
294  */
295 static void axienet_set_mac_address(struct net_device *ndev, void *address)
296 {
297         struct axienet_local *lp = netdev_priv(ndev);
298 
299         if (address)
300                 memcpy(ndev->dev_addr, address, ETH_ALEN);
301         if (!is_valid_ether_addr(ndev->dev_addr))
302                 eth_random_addr(ndev->dev_addr);
303 
304         /* Set up unicast MAC address filter set its mac address */
305         axienet_iow(lp, XAE_UAW0_OFFSET,
306                     (ndev->dev_addr[0]) |
307                     (ndev->dev_addr[1] << 8) |
308                     (ndev->dev_addr[2] << 16) |
309                     (ndev->dev_addr[3] << 24));
310         axienet_iow(lp, XAE_UAW1_OFFSET,
311                     (((axienet_ior(lp, XAE_UAW1_OFFSET)) &
312                       ~XAE_UAW1_UNICASTADDR_MASK) |
313                      (ndev->dev_addr[4] |
314                      (ndev->dev_addr[5] << 8))));
315 }
316 
317 /**
318  * netdev_set_mac_address - Write the MAC address (from outside the driver)
319  * @ndev:       Pointer to the net_device structure
320  * @p:          6 byte Address to be written as MAC address
321  *
322  * Return: 0 for all conditions. Presently, there is no failure case.
323  *
324  * This function is called to initialize the MAC address of the Axi Ethernet
325  * core. It calls the core specific axienet_set_mac_address. This is the
326  * function that goes into net_device_ops structure entry ndo_set_mac_address.
327  */
328 static int netdev_set_mac_address(struct net_device *ndev, void *p)
329 {
330         struct sockaddr *addr = p;
331         axienet_set_mac_address(ndev, addr->sa_data);
332         return 0;
333 }
334 
335 /**
336  * axienet_set_multicast_list - Prepare the multicast table
337  * @ndev:       Pointer to the net_device structure
338  *
339  * This function is called to initialize the multicast table during
340  * initialization. The Axi Ethernet basic multicast support has a four-entry
341  * multicast table which is initialized here. Additionally this function
342  * goes into the net_device_ops structure entry ndo_set_multicast_list. This
343  * means whenever the multicast table entries need to be updated this
344  * function gets called.
345  */
346 static void axienet_set_multicast_list(struct net_device *ndev)
347 {
348         int i;
349         u32 reg, af0reg, af1reg;
350         struct axienet_local *lp = netdev_priv(ndev);
351 
352         if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
353             netdev_mc_count(ndev) > XAE_MULTICAST_CAM_TABLE_NUM) {
354                 /* We must make the kernel realize we had to move into
355                  * promiscuous mode. If it was a promiscuous mode request
356                  * the flag is already set. If not we set it.
357                  */
358                 ndev->flags |= IFF_PROMISC;
359                 reg = axienet_ior(lp, XAE_FMI_OFFSET);
360                 reg |= XAE_FMI_PM_MASK;
361                 axienet_iow(lp, XAE_FMI_OFFSET, reg);
362                 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
363         } else if (!netdev_mc_empty(ndev)) {
364                 struct netdev_hw_addr *ha;
365 
366                 i = 0;
367                 netdev_for_each_mc_addr(ha, ndev) {
368                         if (i >= XAE_MULTICAST_CAM_TABLE_NUM)
369                                 break;
370 
371                         af0reg = (ha->addr[0]);
372                         af0reg |= (ha->addr[1] << 8);
373                         af0reg |= (ha->addr[2] << 16);
374                         af0reg |= (ha->addr[3] << 24);
375 
376                         af1reg = (ha->addr[4]);
377                         af1reg |= (ha->addr[5] << 8);
378 
379                         reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00;
380                         reg |= i;
381 
382                         axienet_iow(lp, XAE_FMI_OFFSET, reg);
383                         axienet_iow(lp, XAE_AF0_OFFSET, af0reg);
384                         axienet_iow(lp, XAE_AF1_OFFSET, af1reg);
385                         i++;
386                 }
387         } else {
388                 reg = axienet_ior(lp, XAE_FMI_OFFSET);
389                 reg &= ~XAE_FMI_PM_MASK;
390 
391                 axienet_iow(lp, XAE_FMI_OFFSET, reg);
392 
393                 for (i = 0; i < XAE_MULTICAST_CAM_TABLE_NUM; i++) {
394                         reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00;
395                         reg |= i;
396 
397                         axienet_iow(lp, XAE_FMI_OFFSET, reg);
398                         axienet_iow(lp, XAE_AF0_OFFSET, 0);
399                         axienet_iow(lp, XAE_AF1_OFFSET, 0);
400                 }
401 
402                 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
403         }
404 }
405 
406 /**
407  * axienet_setoptions - Set an Axi Ethernet option
408  * @ndev:       Pointer to the net_device structure
409  * @options:    Option to be enabled/disabled
410  *
411  * The Axi Ethernet core has multiple features which can be selectively turned
412  * on or off. The typical options could be jumbo frame option, basic VLAN
413  * option, promiscuous mode option etc. This function is used to set or clear
414  * these options in the Axi Ethernet hardware. This is done through
415  * axienet_option structure .
416  */
417 static void axienet_setoptions(struct net_device *ndev, u32 options)
418 {
419         int reg;
420         struct axienet_local *lp = netdev_priv(ndev);
421         struct axienet_option *tp = &axienet_options[0];
422 
423         while (tp->opt) {
424                 reg = ((axienet_ior(lp, tp->reg)) & ~(tp->m_or));
425                 if (options & tp->opt)
426                         reg |= tp->m_or;
427                 axienet_iow(lp, tp->reg, reg);
428                 tp++;
429         }
430 
431         lp->options |= options;
432 }
433 
434 static void __axienet_device_reset(struct axienet_local *lp, off_t offset)
435 {
436         u32 timeout;
437         /* Reset Axi DMA. This would reset Axi Ethernet core as well. The reset
438          * process of Axi DMA takes a while to complete as all pending
439          * commands/transfers will be flushed or completed during this
440          * reset process.
441          */
442         axienet_dma_out32(lp, offset, XAXIDMA_CR_RESET_MASK);
443         timeout = DELAY_OF_ONE_MILLISEC;
444         while (axienet_dma_in32(lp, offset) & XAXIDMA_CR_RESET_MASK) {
445                 udelay(1);
446                 if (--timeout == 0) {
447                         netdev_err(lp->ndev, "%s: DMA reset timeout!\n",
448                                    __func__);
449                         break;
450                 }
451         }
452 }
453 
454 /**
455  * axienet_device_reset - Reset and initialize the Axi Ethernet hardware.
456  * @ndev:       Pointer to the net_device structure
457  *
458  * This function is called to reset and initialize the Axi Ethernet core. This
459  * is typically called during initialization. It does a reset of the Axi DMA
460  * Rx/Tx channels and initializes the Axi DMA BDs. Since Axi DMA reset lines
461  * areconnected to Axi Ethernet reset lines, this in turn resets the Axi
462  * Ethernet core. No separate hardware reset is done for the Axi Ethernet
463  * core.
464  */
465 static void axienet_device_reset(struct net_device *ndev)
466 {
467         u32 axienet_status;
468         struct axienet_local *lp = netdev_priv(ndev);
469 
470         __axienet_device_reset(lp, XAXIDMA_TX_CR_OFFSET);
471         __axienet_device_reset(lp, XAXIDMA_RX_CR_OFFSET);
472 
473         lp->max_frm_size = XAE_MAX_VLAN_FRAME_SIZE;
474         lp->options |= XAE_OPTION_VLAN;
475         lp->options &= (~XAE_OPTION_JUMBO);
476 
477         if ((ndev->mtu > XAE_MTU) &&
478                 (ndev->mtu <= XAE_JUMBO_MTU)) {
479                 lp->max_frm_size = ndev->mtu + VLAN_ETH_HLEN +
480                                         XAE_TRL_SIZE;
481 
482                 if (lp->max_frm_size <= lp->rxmem)
483                         lp->options |= XAE_OPTION_JUMBO;
484         }
485 
486         if (axienet_dma_bd_init(ndev)) {
487                 netdev_err(ndev, "%s: descriptor allocation failed\n",
488                            __func__);
489         }
490 
491         axienet_status = axienet_ior(lp, XAE_RCW1_OFFSET);
492         axienet_status &= ~XAE_RCW1_RX_MASK;
493         axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status);
494 
495         axienet_status = axienet_ior(lp, XAE_IP_OFFSET);
496         if (axienet_status & XAE_INT_RXRJECT_MASK)
497                 axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK);
498 
499         axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);
500 
501         /* Sync default options with HW but leave receiver and
502          * transmitter disabled.
503          */
504         axienet_setoptions(ndev, lp->options &
505                            ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
506         axienet_set_mac_address(ndev, NULL);
507         axienet_set_multicast_list(ndev);
508         axienet_setoptions(ndev, lp->options);
509 
510         netif_trans_update(ndev);
511 }
512 
513 /**
514  * axienet_adjust_link - Adjust the PHY link speed/duplex.
515  * @ndev:       Pointer to the net_device structure
516  *
517  * This function is called to change the speed and duplex setting after
518  * auto negotiation is done by the PHY. This is the function that gets
519  * registered with the PHY interface through the "of_phy_connect" call.
520  */
521 static void axienet_adjust_link(struct net_device *ndev)
522 {
523         u32 emmc_reg;
524         u32 link_state;
525         u32 setspeed = 1;
526         struct axienet_local *lp = netdev_priv(ndev);
527         struct phy_device *phy = ndev->phydev;
528 
529         link_state = phy->speed | (phy->duplex << 1) | phy->link;
530         if (lp->last_link != link_state) {
531                 if ((phy->speed == SPEED_10) || (phy->speed == SPEED_100)) {
532                         if (lp->phy_type == XAE_PHY_TYPE_1000BASE_X)
533                                 setspeed = 0;
534                 } else {
535                         if ((phy->speed == SPEED_1000) &&
536                             (lp->phy_type == XAE_PHY_TYPE_MII))
537                                 setspeed = 0;
538                 }
539 
540                 if (setspeed == 1) {
541                         emmc_reg = axienet_ior(lp, XAE_EMMC_OFFSET);
542                         emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
543 
544                         switch (phy->speed) {
545                         case SPEED_1000:
546                                 emmc_reg |= XAE_EMMC_LINKSPD_1000;
547                                 break;
548                         case SPEED_100:
549                                 emmc_reg |= XAE_EMMC_LINKSPD_100;
550                                 break;
551                         case SPEED_10:
552                                 emmc_reg |= XAE_EMMC_LINKSPD_10;
553                                 break;
554                         default:
555                                 dev_err(&ndev->dev, "Speed other than 10, 100 "
556                                         "or 1Gbps is not supported\n");
557                                 break;
558                         }
559 
560                         axienet_iow(lp, XAE_EMMC_OFFSET, emmc_reg);
561                         lp->last_link = link_state;
562                         phy_print_status(phy);
563                 } else {
564                         netdev_err(ndev,
565                                    "Error setting Axi Ethernet mac speed\n");
566                 }
567         }
568 }
569 
570 /**
571  * axienet_start_xmit_done - Invoked once a transmit is completed by the
572  * Axi DMA Tx channel.
573  * @ndev:       Pointer to the net_device structure
574  *
575  * This function is invoked from the Axi DMA Tx isr to notify the completion
576  * of transmit operation. It clears fields in the corresponding Tx BDs and
577  * unmaps the corresponding buffer so that CPU can regain ownership of the
578  * buffer. It finally invokes "netif_wake_queue" to restart transmission if
579  * required.
580  */
581 static void axienet_start_xmit_done(struct net_device *ndev)
582 {
583         u32 size = 0;
584         u32 packets = 0;
585         struct axienet_local *lp = netdev_priv(ndev);
586         struct axidma_bd *cur_p;
587         unsigned int status = 0;
588 
589         cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
590         status = cur_p->status;
591         while (status & XAXIDMA_BD_STS_COMPLETE_MASK) {
592                 dma_unmap_single(ndev->dev.parent, cur_p->phys,
593                                 (cur_p->cntrl & XAXIDMA_BD_CTRL_LENGTH_MASK),
594                                 DMA_TO_DEVICE);
595                 if (cur_p->app4)
596                         dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
597                 /*cur_p->phys = 0;*/
598                 cur_p->app0 = 0;
599                 cur_p->app1 = 0;
600                 cur_p->app2 = 0;
601                 cur_p->app4 = 0;
602                 cur_p->status = 0;
603 
604                 size += status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
605                 packets++;
606 
607                 ++lp->tx_bd_ci;
608                 lp->tx_bd_ci %= TX_BD_NUM;
609                 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
610                 status = cur_p->status;
611         }
612 
613         ndev->stats.tx_packets += packets;
614         ndev->stats.tx_bytes += size;
615         netif_wake_queue(ndev);
616 }
617 
618 /**
619  * axienet_check_tx_bd_space - Checks if a BD/group of BDs are currently busy
620  * @lp:         Pointer to the axienet_local structure
621  * @num_frag:   The number of BDs to check for
622  *
623  * Return: 0, on success
624  *          NETDEV_TX_BUSY, if any of the descriptors are not free
625  *
626  * This function is invoked before BDs are allocated and transmission starts.
627  * This function returns 0 if a BD or group of BDs can be allocated for
628  * transmission. If the BD or any of the BDs are not free the function
629  * returns a busy status. This is invoked from axienet_start_xmit.
630  */
631 static inline int axienet_check_tx_bd_space(struct axienet_local *lp,
632                                             int num_frag)
633 {
634         struct axidma_bd *cur_p;
635         cur_p = &lp->tx_bd_v[(lp->tx_bd_tail + num_frag) % TX_BD_NUM];
636         if (cur_p->status & XAXIDMA_BD_STS_ALL_MASK)
637                 return NETDEV_TX_BUSY;
638         return 0;
639 }
640 
641 /**
642  * axienet_start_xmit - Starts the transmission.
643  * @skb:        sk_buff pointer that contains data to be Txed.
644  * @ndev:       Pointer to net_device structure.
645  *
646  * Return: NETDEV_TX_OK, on success
647  *          NETDEV_TX_BUSY, if any of the descriptors are not free
648  *
649  * This function is invoked from upper layers to initiate transmission. The
650  * function uses the next available free BDs and populates their fields to
651  * start the transmission. Additionally if checksum offloading is supported,
652  * it populates AXI Stream Control fields with appropriate values.
653  */
654 static int axienet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
655 {
656         u32 ii;
657         u32 num_frag;
658         u32 csum_start_off;
659         u32 csum_index_off;
660         skb_frag_t *frag;
661         dma_addr_t tail_p;
662         struct axienet_local *lp = netdev_priv(ndev);
663         struct axidma_bd *cur_p;
664 
665         num_frag = skb_shinfo(skb)->nr_frags;
666         cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
667 
668         if (axienet_check_tx_bd_space(lp, num_frag)) {
669                 if (!netif_queue_stopped(ndev))
670                         netif_stop_queue(ndev);
671                 return NETDEV_TX_BUSY;
672         }
673 
674         if (skb->ip_summed == CHECKSUM_PARTIAL) {
675                 if (lp->features & XAE_FEATURE_FULL_TX_CSUM) {
676                         /* Tx Full Checksum Offload Enabled */
677                         cur_p->app0 |= 2;
678                 } else if (lp->features & XAE_FEATURE_PARTIAL_RX_CSUM) {
679                         csum_start_off = skb_transport_offset(skb);
680                         csum_index_off = csum_start_off + skb->csum_offset;
681                         /* Tx Partial Checksum Offload Enabled */
682                         cur_p->app0 |= 1;
683                         cur_p->app1 = (csum_start_off << 16) | csum_index_off;
684                 }
685         } else if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
686                 cur_p->app0 |= 2; /* Tx Full Checksum Offload Enabled */
687         }
688 
689         cur_p->cntrl = skb_headlen(skb) | XAXIDMA_BD_CTRL_TXSOF_MASK;
690         cur_p->phys = dma_map_single(ndev->dev.parent, skb->data,
691                                      skb_headlen(skb), DMA_TO_DEVICE);
692 
693         for (ii = 0; ii < num_frag; ii++) {
694                 ++lp->tx_bd_tail;
695                 lp->tx_bd_tail %= TX_BD_NUM;
696                 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
697                 frag = &skb_shinfo(skb)->frags[ii];
698                 cur_p->phys = dma_map_single(ndev->dev.parent,
699                                              skb_frag_address(frag),
700                                              skb_frag_size(frag),
701                                              DMA_TO_DEVICE);
702                 cur_p->cntrl = skb_frag_size(frag);
703         }
704 
705         cur_p->cntrl |= XAXIDMA_BD_CTRL_TXEOF_MASK;
706         cur_p->app4 = (unsigned long)skb;
707 
708         tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
709         /* Start the transfer */
710         axienet_dma_out32(lp, XAXIDMA_TX_TDESC_OFFSET, tail_p);
711         ++lp->tx_bd_tail;
712         lp->tx_bd_tail %= TX_BD_NUM;
713 
714         return NETDEV_TX_OK;
715 }
716 
717 /**
718  * axienet_recv - Is called from Axi DMA Rx Isr to complete the received
719  *                BD processing.
720  * @ndev:       Pointer to net_device structure.
721  *
722  * This function is invoked from the Axi DMA Rx isr to process the Rx BDs. It
723  * does minimal processing and invokes "netif_rx" to complete further
724  * processing.
725  */
726 static void axienet_recv(struct net_device *ndev)
727 {
728         u32 length;
729         u32 csumstatus;
730         u32 size = 0;
731         u32 packets = 0;
732         dma_addr_t tail_p = 0;
733         struct axienet_local *lp = netdev_priv(ndev);
734         struct sk_buff *skb, *new_skb;
735         struct axidma_bd *cur_p;
736 
737         cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
738 
739         while ((cur_p->status & XAXIDMA_BD_STS_COMPLETE_MASK)) {
740                 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
741                 skb = (struct sk_buff *) (cur_p->sw_id_offset);
742                 length = cur_p->app4 & 0x0000FFFF;
743 
744                 dma_unmap_single(ndev->dev.parent, cur_p->phys,
745                                  lp->max_frm_size,
746                                  DMA_FROM_DEVICE);
747 
748                 skb_put(skb, length);
749                 skb->protocol = eth_type_trans(skb, ndev);
750                 /*skb_checksum_none_assert(skb);*/
751                 skb->ip_summed = CHECKSUM_NONE;
752 
753                 /* if we're doing Rx csum offload, set it up */
754                 if (lp->features & XAE_FEATURE_FULL_RX_CSUM) {
755                         csumstatus = (cur_p->app2 &
756                                       XAE_FULL_CSUM_STATUS_MASK) >> 3;
757                         if ((csumstatus == XAE_IP_TCP_CSUM_VALIDATED) ||
758                             (csumstatus == XAE_IP_UDP_CSUM_VALIDATED)) {
759                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
760                         }
761                 } else if ((lp->features & XAE_FEATURE_PARTIAL_RX_CSUM) != 0 &&
762                            skb->protocol == htons(ETH_P_IP) &&
763                            skb->len > 64) {
764                         skb->csum = be32_to_cpu(cur_p->app3 & 0xFFFF);
765                         skb->ip_summed = CHECKSUM_COMPLETE;
766                 }
767 
768                 netif_rx(skb);
769 
770                 size += length;
771                 packets++;
772 
773                 new_skb = netdev_alloc_skb_ip_align(ndev, lp->max_frm_size);
774                 if (!new_skb)
775                         return;
776 
777                 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
778                                              lp->max_frm_size,
779                                              DMA_FROM_DEVICE);
780                 cur_p->cntrl = lp->max_frm_size;
781                 cur_p->status = 0;
782                 cur_p->sw_id_offset = (u32) new_skb;
783 
784                 ++lp->rx_bd_ci;
785                 lp->rx_bd_ci %= RX_BD_NUM;
786                 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
787         }
788 
789         ndev->stats.rx_packets += packets;
790         ndev->stats.rx_bytes += size;
791 
792         if (tail_p)
793                 axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, tail_p);
794 }
795 
796 /**
797  * axienet_tx_irq - Tx Done Isr.
798  * @irq:        irq number
799  * @_ndev:      net_device pointer
800  *
801  * Return: IRQ_HANDLED for all cases.
802  *
803  * This is the Axi DMA Tx done Isr. It invokes "axienet_start_xmit_done"
804  * to complete the BD processing.
805  */
806 static irqreturn_t axienet_tx_irq(int irq, void *_ndev)
807 {
808         u32 cr;
809         unsigned int status;
810         struct net_device *ndev = _ndev;
811         struct axienet_local *lp = netdev_priv(ndev);
812 
813         status = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET);
814         if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
815                 axienet_dma_out32(lp, XAXIDMA_TX_SR_OFFSET, status);
816                 axienet_start_xmit_done(lp->ndev);
817                 goto out;
818         }
819         if (!(status & XAXIDMA_IRQ_ALL_MASK))
820                 dev_err(&ndev->dev, "No interrupts asserted in Tx path\n");
821         if (status & XAXIDMA_IRQ_ERROR_MASK) {
822                 dev_err(&ndev->dev, "DMA Tx error 0x%x\n", status);
823                 dev_err(&ndev->dev, "Current BD is at: 0x%x\n",
824                         (lp->tx_bd_v[lp->tx_bd_ci]).phys);
825 
826                 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
827                 /* Disable coalesce, delay timer and error interrupts */
828                 cr &= (~XAXIDMA_IRQ_ALL_MASK);
829                 /* Write to the Tx channel control register */
830                 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
831 
832                 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
833                 /* Disable coalesce, delay timer and error interrupts */
834                 cr &= (~XAXIDMA_IRQ_ALL_MASK);
835                 /* Write to the Rx channel control register */
836                 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
837 
838                 tasklet_schedule(&lp->dma_err_tasklet);
839                 axienet_dma_out32(lp, XAXIDMA_TX_SR_OFFSET, status);
840         }
841 out:
842         return IRQ_HANDLED;
843 }
844 
845 /**
846  * axienet_rx_irq - Rx Isr.
847  * @irq:        irq number
848  * @_ndev:      net_device pointer
849  *
850  * Return: IRQ_HANDLED for all cases.
851  *
852  * This is the Axi DMA Rx Isr. It invokes "axienet_recv" to complete the BD
853  * processing.
854  */
855 static irqreturn_t axienet_rx_irq(int irq, void *_ndev)
856 {
857         u32 cr;
858         unsigned int status;
859         struct net_device *ndev = _ndev;
860         struct axienet_local *lp = netdev_priv(ndev);
861 
862         status = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET);
863         if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
864                 axienet_dma_out32(lp, XAXIDMA_RX_SR_OFFSET, status);
865                 axienet_recv(lp->ndev);
866                 goto out;
867         }
868         if (!(status & XAXIDMA_IRQ_ALL_MASK))
869                 dev_err(&ndev->dev, "No interrupts asserted in Rx path\n");
870         if (status & XAXIDMA_IRQ_ERROR_MASK) {
871                 dev_err(&ndev->dev, "DMA Rx error 0x%x\n", status);
872                 dev_err(&ndev->dev, "Current BD is at: 0x%x\n",
873                         (lp->rx_bd_v[lp->rx_bd_ci]).phys);
874 
875                 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
876                 /* Disable coalesce, delay timer and error interrupts */
877                 cr &= (~XAXIDMA_IRQ_ALL_MASK);
878                 /* Finally write to the Tx channel control register */
879                 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
880 
881                 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
882                 /* Disable coalesce, delay timer and error interrupts */
883                 cr &= (~XAXIDMA_IRQ_ALL_MASK);
884                 /* write to the Rx channel control register */
885                 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
886 
887                 tasklet_schedule(&lp->dma_err_tasklet);
888                 axienet_dma_out32(lp, XAXIDMA_RX_SR_OFFSET, status);
889         }
890 out:
891         return IRQ_HANDLED;
892 }
893 
894 static void axienet_dma_err_handler(unsigned long data);
895 
896 /**
897  * axienet_open - Driver open routine.
898  * @ndev:       Pointer to net_device structure
899  *
900  * Return: 0, on success.
901  *          -ENODEV, if PHY cannot be connected to
902  *          non-zero error value on failure
903  *
904  * This is the driver open routine. It calls phy_start to start the PHY device.
905  * It also allocates interrupt service routines, enables the interrupt lines
906  * and ISR handling. Axi Ethernet core is reset through Axi DMA core. Buffer
907  * descriptors are initialized.
908  */
909 static int axienet_open(struct net_device *ndev)
910 {
911         int ret, mdio_mcreg;
912         struct axienet_local *lp = netdev_priv(ndev);
913         struct phy_device *phydev = NULL;
914 
915         dev_dbg(&ndev->dev, "axienet_open()\n");
916 
917         mdio_mcreg = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
918         ret = axienet_mdio_wait_until_ready(lp);
919         if (ret < 0)
920                 return ret;
921         /* Disable the MDIO interface till Axi Ethernet Reset is completed.
922          * When we do an Axi Ethernet reset, it resets the complete core
923          * including the MDIO. If MDIO is not disabled when the reset
924          * process is started, MDIO will be broken afterwards.
925          */
926         axienet_iow(lp, XAE_MDIO_MC_OFFSET,
927                     (mdio_mcreg & (~XAE_MDIO_MC_MDIOEN_MASK)));
928         axienet_device_reset(ndev);
929         /* Enable the MDIO */
930         axienet_iow(lp, XAE_MDIO_MC_OFFSET, mdio_mcreg);
931         ret = axienet_mdio_wait_until_ready(lp);
932         if (ret < 0)
933                 return ret;
934 
935         if (lp->phy_node) {
936                 if (lp->phy_type == XAE_PHY_TYPE_GMII) {
937                         phydev = of_phy_connect(lp->ndev, lp->phy_node,
938                                                 axienet_adjust_link, 0,
939                                                 PHY_INTERFACE_MODE_GMII);
940                 } else if (lp->phy_type == XAE_PHY_TYPE_RGMII_2_0) {
941                         phydev = of_phy_connect(lp->ndev, lp->phy_node,
942                                                 axienet_adjust_link, 0,
943                                                 PHY_INTERFACE_MODE_RGMII_ID);
944                 }
945 
946                 if (!phydev)
947                         dev_err(lp->dev, "of_phy_connect() failed\n");
948                 else
949                         phy_start(phydev);
950         }
951 
952         /* Enable tasklets for Axi DMA error handling */
953         tasklet_init(&lp->dma_err_tasklet, axienet_dma_err_handler,
954                      (unsigned long) lp);
955 
956         /* Enable interrupts for Axi DMA Tx */
957         ret = request_irq(lp->tx_irq, axienet_tx_irq, 0, ndev->name, ndev);
958         if (ret)
959                 goto err_tx_irq;
960         /* Enable interrupts for Axi DMA Rx */
961         ret = request_irq(lp->rx_irq, axienet_rx_irq, 0, ndev->name, ndev);
962         if (ret)
963                 goto err_rx_irq;
964 
965         return 0;
966 
967 err_rx_irq:
968         free_irq(lp->tx_irq, ndev);
969 err_tx_irq:
970         if (phydev)
971                 phy_disconnect(phydev);
972         tasklet_kill(&lp->dma_err_tasklet);
973         dev_err(lp->dev, "request_irq() failed\n");
974         return ret;
975 }
976 
977 /**
978  * axienet_stop - Driver stop routine.
979  * @ndev:       Pointer to net_device structure
980  *
981  * Return: 0, on success.
982  *
983  * This is the driver stop routine. It calls phy_disconnect to stop the PHY
984  * device. It also removes the interrupt handlers and disables the interrupts.
985  * The Axi DMA Tx/Rx BDs are released.
986  */
987 static int axienet_stop(struct net_device *ndev)
988 {
989         u32 cr;
990         struct axienet_local *lp = netdev_priv(ndev);
991 
992         dev_dbg(&ndev->dev, "axienet_close()\n");
993 
994         cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
995         axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
996                           cr & (~XAXIDMA_CR_RUNSTOP_MASK));
997         cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
998         axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
999                           cr & (~XAXIDMA_CR_RUNSTOP_MASK));
1000         axienet_setoptions(ndev, lp->options &
1001                            ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1002 
1003         tasklet_kill(&lp->dma_err_tasklet);
1004 
1005         free_irq(lp->tx_irq, ndev);
1006         free_irq(lp->rx_irq, ndev);
1007 
1008         if (ndev->phydev)
1009                 phy_disconnect(ndev->phydev);
1010 
1011         axienet_dma_bd_release(ndev);
1012         return 0;
1013 }
1014 
1015 /**
1016  * axienet_change_mtu - Driver change mtu routine.
1017  * @ndev:       Pointer to net_device structure
1018  * @new_mtu:    New mtu value to be applied
1019  *
1020  * Return: Always returns 0 (success).
1021  *
1022  * This is the change mtu driver routine. It checks if the Axi Ethernet
1023  * hardware supports jumbo frames before changing the mtu. This can be
1024  * called only when the device is not up.
1025  */
1026 static int axienet_change_mtu(struct net_device *ndev, int new_mtu)
1027 {
1028         struct axienet_local *lp = netdev_priv(ndev);
1029 
1030         if (netif_running(ndev))
1031                 return -EBUSY;
1032 
1033         if ((new_mtu + VLAN_ETH_HLEN +
1034                 XAE_TRL_SIZE) > lp->rxmem)
1035                 return -EINVAL;
1036 
1037         if ((new_mtu > XAE_JUMBO_MTU) || (new_mtu < 64))
1038                 return -EINVAL;
1039 
1040         ndev->mtu = new_mtu;
1041 
1042         return 0;
1043 }
1044 
1045 #ifdef CONFIG_NET_POLL_CONTROLLER
1046 /**
1047  * axienet_poll_controller - Axi Ethernet poll mechanism.
1048  * @ndev:       Pointer to net_device structure
1049  *
1050  * This implements Rx/Tx ISR poll mechanisms. The interrupts are disabled prior
1051  * to polling the ISRs and are enabled back after the polling is done.
1052  */
1053 static void axienet_poll_controller(struct net_device *ndev)
1054 {
1055         struct axienet_local *lp = netdev_priv(ndev);
1056         disable_irq(lp->tx_irq);
1057         disable_irq(lp->rx_irq);
1058         axienet_rx_irq(lp->tx_irq, ndev);
1059         axienet_tx_irq(lp->rx_irq, ndev);
1060         enable_irq(lp->tx_irq);
1061         enable_irq(lp->rx_irq);
1062 }
1063 #endif
1064 
1065 static const struct net_device_ops axienet_netdev_ops = {
1066         .ndo_open = axienet_open,
1067         .ndo_stop = axienet_stop,
1068         .ndo_start_xmit = axienet_start_xmit,
1069         .ndo_change_mtu = axienet_change_mtu,
1070         .ndo_set_mac_address = netdev_set_mac_address,
1071         .ndo_validate_addr = eth_validate_addr,
1072         .ndo_set_rx_mode = axienet_set_multicast_list,
1073 #ifdef CONFIG_NET_POLL_CONTROLLER
1074         .ndo_poll_controller = axienet_poll_controller,
1075 #endif
1076 };
1077 
1078 /**
1079  * axienet_ethtools_get_drvinfo - Get various Axi Ethernet driver information.
1080  * @ndev:       Pointer to net_device structure
1081  * @ed:         Pointer to ethtool_drvinfo structure
1082  *
1083  * This implements ethtool command for getting the driver information.
1084  * Issue "ethtool -i ethX" under linux prompt to execute this function.
1085  */
1086 static void axienet_ethtools_get_drvinfo(struct net_device *ndev,
1087                                          struct ethtool_drvinfo *ed)
1088 {
1089         strlcpy(ed->driver, DRIVER_NAME, sizeof(ed->driver));
1090         strlcpy(ed->version, DRIVER_VERSION, sizeof(ed->version));
1091 }
1092 
1093 /**
1094  * axienet_ethtools_get_regs_len - Get the total regs length present in the
1095  *                                 AxiEthernet core.
1096  * @ndev:       Pointer to net_device structure
1097  *
1098  * This implements ethtool command for getting the total register length
1099  * information.
1100  *
1101  * Return: the total regs length
1102  */
1103 static int axienet_ethtools_get_regs_len(struct net_device *ndev)
1104 {
1105         return sizeof(u32) * AXIENET_REGS_N;
1106 }
1107 
1108 /**
1109  * axienet_ethtools_get_regs - Dump the contents of all registers present
1110  *                             in AxiEthernet core.
1111  * @ndev:       Pointer to net_device structure
1112  * @regs:       Pointer to ethtool_regs structure
1113  * @ret:        Void pointer used to return the contents of the registers.
1114  *
1115  * This implements ethtool command for getting the Axi Ethernet register dump.
1116  * Issue "ethtool -d ethX" to execute this function.
1117  */
1118 static void axienet_ethtools_get_regs(struct net_device *ndev,
1119                                       struct ethtool_regs *regs, void *ret)
1120 {
1121         u32 *data = (u32 *) ret;
1122         size_t len = sizeof(u32) * AXIENET_REGS_N;
1123         struct axienet_local *lp = netdev_priv(ndev);
1124 
1125         regs->version = 0;
1126         regs->len = len;
1127 
1128         memset(data, 0, len);
1129         data[0] = axienet_ior(lp, XAE_RAF_OFFSET);
1130         data[1] = axienet_ior(lp, XAE_TPF_OFFSET);
1131         data[2] = axienet_ior(lp, XAE_IFGP_OFFSET);
1132         data[3] = axienet_ior(lp, XAE_IS_OFFSET);
1133         data[4] = axienet_ior(lp, XAE_IP_OFFSET);
1134         data[5] = axienet_ior(lp, XAE_IE_OFFSET);
1135         data[6] = axienet_ior(lp, XAE_TTAG_OFFSET);
1136         data[7] = axienet_ior(lp, XAE_RTAG_OFFSET);
1137         data[8] = axienet_ior(lp, XAE_UAWL_OFFSET);
1138         data[9] = axienet_ior(lp, XAE_UAWU_OFFSET);
1139         data[10] = axienet_ior(lp, XAE_TPID0_OFFSET);
1140         data[11] = axienet_ior(lp, XAE_TPID1_OFFSET);
1141         data[12] = axienet_ior(lp, XAE_PPST_OFFSET);
1142         data[13] = axienet_ior(lp, XAE_RCW0_OFFSET);
1143         data[14] = axienet_ior(lp, XAE_RCW1_OFFSET);
1144         data[15] = axienet_ior(lp, XAE_TC_OFFSET);
1145         data[16] = axienet_ior(lp, XAE_FCC_OFFSET);
1146         data[17] = axienet_ior(lp, XAE_EMMC_OFFSET);
1147         data[18] = axienet_ior(lp, XAE_PHYC_OFFSET);
1148         data[19] = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
1149         data[20] = axienet_ior(lp, XAE_MDIO_MCR_OFFSET);
1150         data[21] = axienet_ior(lp, XAE_MDIO_MWD_OFFSET);
1151         data[22] = axienet_ior(lp, XAE_MDIO_MRD_OFFSET);
1152         data[23] = axienet_ior(lp, XAE_MDIO_MIS_OFFSET);
1153         data[24] = axienet_ior(lp, XAE_MDIO_MIP_OFFSET);
1154         data[25] = axienet_ior(lp, XAE_MDIO_MIE_OFFSET);
1155         data[26] = axienet_ior(lp, XAE_MDIO_MIC_OFFSET);
1156         data[27] = axienet_ior(lp, XAE_UAW0_OFFSET);
1157         data[28] = axienet_ior(lp, XAE_UAW1_OFFSET);
1158         data[29] = axienet_ior(lp, XAE_FMI_OFFSET);
1159         data[30] = axienet_ior(lp, XAE_AF0_OFFSET);
1160         data[31] = axienet_ior(lp, XAE_AF1_OFFSET);
1161 }
1162 
1163 /**
1164  * axienet_ethtools_get_pauseparam - Get the pause parameter setting for
1165  *                                   Tx and Rx paths.
1166  * @ndev:       Pointer to net_device structure
1167  * @epauseparm: Pointer to ethtool_pauseparam structure.
1168  *
1169  * This implements ethtool command for getting axi ethernet pause frame
1170  * setting. Issue "ethtool -a ethX" to execute this function.
1171  */
1172 static void
1173 axienet_ethtools_get_pauseparam(struct net_device *ndev,
1174                                 struct ethtool_pauseparam *epauseparm)
1175 {
1176         u32 regval;
1177         struct axienet_local *lp = netdev_priv(ndev);
1178         epauseparm->autoneg  = 0;
1179         regval = axienet_ior(lp, XAE_FCC_OFFSET);
1180         epauseparm->tx_pause = regval & XAE_FCC_FCTX_MASK;
1181         epauseparm->rx_pause = regval & XAE_FCC_FCRX_MASK;
1182 }
1183 
1184 /**
1185  * axienet_ethtools_set_pauseparam - Set device pause parameter(flow control)
1186  *                                   settings.
1187  * @ndev:       Pointer to net_device structure
1188  * @epauseparm:Pointer to ethtool_pauseparam structure
1189  *
1190  * This implements ethtool command for enabling flow control on Rx and Tx
1191  * paths. Issue "ethtool -A ethX tx on|off" under linux prompt to execute this
1192  * function.
1193  *
1194  * Return: 0 on success, -EFAULT if device is running
1195  */
1196 static int
1197 axienet_ethtools_set_pauseparam(struct net_device *ndev,
1198                                 struct ethtool_pauseparam *epauseparm)
1199 {
1200         u32 regval = 0;
1201         struct axienet_local *lp = netdev_priv(ndev);
1202 
1203         if (netif_running(ndev)) {
1204                 netdev_err(ndev,
1205                            "Please stop netif before applying configuration\n");
1206                 return -EFAULT;
1207         }
1208 
1209         regval = axienet_ior(lp, XAE_FCC_OFFSET);
1210         if (epauseparm->tx_pause)
1211                 regval |= XAE_FCC_FCTX_MASK;
1212         else
1213                 regval &= ~XAE_FCC_FCTX_MASK;
1214         if (epauseparm->rx_pause)
1215                 regval |= XAE_FCC_FCRX_MASK;
1216         else
1217                 regval &= ~XAE_FCC_FCRX_MASK;
1218         axienet_iow(lp, XAE_FCC_OFFSET, regval);
1219 
1220         return 0;
1221 }
1222 
1223 /**
1224  * axienet_ethtools_get_coalesce - Get DMA interrupt coalescing count.
1225  * @ndev:       Pointer to net_device structure
1226  * @ecoalesce:  Pointer to ethtool_coalesce structure
1227  *
1228  * This implements ethtool command for getting the DMA interrupt coalescing
1229  * count on Tx and Rx paths. Issue "ethtool -c ethX" under linux prompt to
1230  * execute this function.
1231  *
1232  * Return: 0 always
1233  */
1234 static int axienet_ethtools_get_coalesce(struct net_device *ndev,
1235                                          struct ethtool_coalesce *ecoalesce)
1236 {
1237         u32 regval = 0;
1238         struct axienet_local *lp = netdev_priv(ndev);
1239         regval = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1240         ecoalesce->rx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)
1241                                              >> XAXIDMA_COALESCE_SHIFT;
1242         regval = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1243         ecoalesce->tx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)
1244                                              >> XAXIDMA_COALESCE_SHIFT;
1245         return 0;
1246 }
1247 
1248 /**
1249  * axienet_ethtools_set_coalesce - Set DMA interrupt coalescing count.
1250  * @ndev:       Pointer to net_device structure
1251  * @ecoalesce:  Pointer to ethtool_coalesce structure
1252  *
1253  * This implements ethtool command for setting the DMA interrupt coalescing
1254  * count on Tx and Rx paths. Issue "ethtool -C ethX rx-frames 5" under linux
1255  * prompt to execute this function.
1256  *
1257  * Return: 0, on success, Non-zero error value on failure.
1258  */
1259 static int axienet_ethtools_set_coalesce(struct net_device *ndev,
1260                                          struct ethtool_coalesce *ecoalesce)
1261 {
1262         struct axienet_local *lp = netdev_priv(ndev);
1263 
1264         if (netif_running(ndev)) {
1265                 netdev_err(ndev,
1266                            "Please stop netif before applying configuration\n");
1267                 return -EFAULT;
1268         }
1269 
1270         if ((ecoalesce->rx_coalesce_usecs) ||
1271             (ecoalesce->rx_coalesce_usecs_irq) ||
1272             (ecoalesce->rx_max_coalesced_frames_irq) ||
1273             (ecoalesce->tx_coalesce_usecs) ||
1274             (ecoalesce->tx_coalesce_usecs_irq) ||
1275             (ecoalesce->tx_max_coalesced_frames_irq) ||
1276             (ecoalesce->stats_block_coalesce_usecs) ||
1277             (ecoalesce->use_adaptive_rx_coalesce) ||
1278             (ecoalesce->use_adaptive_tx_coalesce) ||
1279             (ecoalesce->pkt_rate_low) ||
1280             (ecoalesce->rx_coalesce_usecs_low) ||
1281             (ecoalesce->rx_max_coalesced_frames_low) ||
1282             (ecoalesce->tx_coalesce_usecs_low) ||
1283             (ecoalesce->tx_max_coalesced_frames_low) ||
1284             (ecoalesce->pkt_rate_high) ||
1285             (ecoalesce->rx_coalesce_usecs_high) ||
1286             (ecoalesce->rx_max_coalesced_frames_high) ||
1287             (ecoalesce->tx_coalesce_usecs_high) ||
1288             (ecoalesce->tx_max_coalesced_frames_high) ||
1289             (ecoalesce->rate_sample_interval))
1290                 return -EOPNOTSUPP;
1291         if (ecoalesce->rx_max_coalesced_frames)
1292                 lp->coalesce_count_rx = ecoalesce->rx_max_coalesced_frames;
1293         if (ecoalesce->tx_max_coalesced_frames)
1294                 lp->coalesce_count_tx = ecoalesce->tx_max_coalesced_frames;
1295 
1296         return 0;
1297 }
1298 
1299 static const struct ethtool_ops axienet_ethtool_ops = {
1300         .get_drvinfo    = axienet_ethtools_get_drvinfo,
1301         .get_regs_len   = axienet_ethtools_get_regs_len,
1302         .get_regs       = axienet_ethtools_get_regs,
1303         .get_link       = ethtool_op_get_link,
1304         .get_pauseparam = axienet_ethtools_get_pauseparam,
1305         .set_pauseparam = axienet_ethtools_set_pauseparam,
1306         .get_coalesce   = axienet_ethtools_get_coalesce,
1307         .set_coalesce   = axienet_ethtools_set_coalesce,
1308         .get_link_ksettings = phy_ethtool_get_link_ksettings,
1309         .set_link_ksettings = phy_ethtool_set_link_ksettings,
1310 };
1311 
1312 /**
1313  * axienet_dma_err_handler - Tasklet handler for Axi DMA Error
1314  * @data:       Data passed
1315  *
1316  * Resets the Axi DMA and Axi Ethernet devices, and reconfigures the
1317  * Tx/Rx BDs.
1318  */
1319 static void axienet_dma_err_handler(unsigned long data)
1320 {
1321         u32 axienet_status;
1322         u32 cr, i;
1323         int mdio_mcreg;
1324         struct axienet_local *lp = (struct axienet_local *) data;
1325         struct net_device *ndev = lp->ndev;
1326         struct axidma_bd *cur_p;
1327 
1328         axienet_setoptions(ndev, lp->options &
1329                            ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1330         mdio_mcreg = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
1331         axienet_mdio_wait_until_ready(lp);
1332         /* Disable the MDIO interface till Axi Ethernet Reset is completed.
1333          * When we do an Axi Ethernet reset, it resets the complete core
1334          * including the MDIO. So if MDIO is not disabled when the reset
1335          * process is started, MDIO will be broken afterwards.
1336          */
1337         axienet_iow(lp, XAE_MDIO_MC_OFFSET, (mdio_mcreg &
1338                     ~XAE_MDIO_MC_MDIOEN_MASK));
1339 
1340         __axienet_device_reset(lp, XAXIDMA_TX_CR_OFFSET);
1341         __axienet_device_reset(lp, XAXIDMA_RX_CR_OFFSET);
1342 
1343         axienet_iow(lp, XAE_MDIO_MC_OFFSET, mdio_mcreg);
1344         axienet_mdio_wait_until_ready(lp);
1345 
1346         for (i = 0; i < TX_BD_NUM; i++) {
1347                 cur_p = &lp->tx_bd_v[i];
1348                 if (cur_p->phys)
1349                         dma_unmap_single(ndev->dev.parent, cur_p->phys,
1350                                          (cur_p->cntrl &
1351                                           XAXIDMA_BD_CTRL_LENGTH_MASK),
1352                                          DMA_TO_DEVICE);
1353                 if (cur_p->app4)
1354                         dev_kfree_skb_irq((struct sk_buff *) cur_p->app4);
1355                 cur_p->phys = 0;
1356                 cur_p->cntrl = 0;
1357                 cur_p->status = 0;
1358                 cur_p->app0 = 0;
1359                 cur_p->app1 = 0;
1360                 cur_p->app2 = 0;
1361                 cur_p->app3 = 0;
1362                 cur_p->app4 = 0;
1363                 cur_p->sw_id_offset = 0;
1364         }
1365 
1366         for (i = 0; i < RX_BD_NUM; i++) {
1367                 cur_p = &lp->rx_bd_v[i];
1368                 cur_p->status = 0;
1369                 cur_p->app0 = 0;
1370                 cur_p->app1 = 0;
1371                 cur_p->app2 = 0;
1372                 cur_p->app3 = 0;
1373                 cur_p->app4 = 0;
1374         }
1375 
1376         lp->tx_bd_ci = 0;
1377         lp->tx_bd_tail = 0;
1378         lp->rx_bd_ci = 0;
1379 
1380         /* Start updating the Rx channel control register */
1381         cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1382         /* Update the interrupt coalesce count */
1383         cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
1384               (XAXIDMA_DFT_RX_THRESHOLD << XAXIDMA_COALESCE_SHIFT));
1385         /* Update the delay timer count */
1386         cr = ((cr & ~XAXIDMA_DELAY_MASK) |
1387               (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
1388         /* Enable coalesce, delay timer and error interrupts */
1389         cr |= XAXIDMA_IRQ_ALL_MASK;
1390         /* Finally write to the Rx channel control register */
1391         axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
1392 
1393         /* Start updating the Tx channel control register */
1394         cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1395         /* Update the interrupt coalesce count */
1396         cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
1397               (XAXIDMA_DFT_TX_THRESHOLD << XAXIDMA_COALESCE_SHIFT));
1398         /* Update the delay timer count */
1399         cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
1400               (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
1401         /* Enable coalesce, delay timer and error interrupts */
1402         cr |= XAXIDMA_IRQ_ALL_MASK;
1403         /* Finally write to the Tx channel control register */
1404         axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
1405 
1406         /* Populate the tail pointer and bring the Rx Axi DMA engine out of
1407          * halted state. This will make the Rx side ready for reception.
1408          */
1409         axienet_dma_out32(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
1410         cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1411         axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
1412                           cr | XAXIDMA_CR_RUNSTOP_MASK);
1413         axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
1414                           (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
1415 
1416         /* Write to the RS (Run-stop) bit in the Tx channel control register.
1417          * Tx channel is now ready to run. But only after we write to the
1418          * tail pointer register that the Tx channel will start transmitting
1419          */
1420         axienet_dma_out32(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
1421         cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1422         axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
1423                           cr | XAXIDMA_CR_RUNSTOP_MASK);
1424 
1425         axienet_status = axienet_ior(lp, XAE_RCW1_OFFSET);
1426         axienet_status &= ~XAE_RCW1_RX_MASK;
1427         axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status);
1428 
1429         axienet_status = axienet_ior(lp, XAE_IP_OFFSET);
1430         if (axienet_status & XAE_INT_RXRJECT_MASK)
1431                 axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK);
1432         axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);
1433 
1434         /* Sync default options with HW but leave receiver and
1435          * transmitter disabled.
1436          */
1437         axienet_setoptions(ndev, lp->options &
1438                            ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1439         axienet_set_mac_address(ndev, NULL);
1440         axienet_set_multicast_list(ndev);
1441         axienet_setoptions(ndev, lp->options);
1442 }
1443 
1444 /**
1445  * axienet_probe - Axi Ethernet probe function.
1446  * @pdev:       Pointer to platform device structure.
1447  *
1448  * Return: 0, on success
1449  *          Non-zero error value on failure.
1450  *
1451  * This is the probe routine for Axi Ethernet driver. This is called before
1452  * any other driver routines are invoked. It allocates and sets up the Ethernet
1453  * device. Parses through device tree and populates fields of
1454  * axienet_local. It registers the Ethernet device.
1455  */
1456 static int axienet_probe(struct platform_device *pdev)
1457 {
1458         int ret;
1459         struct device_node *np;
1460         struct axienet_local *lp;
1461         struct net_device *ndev;
1462         u8 mac_addr[6];
1463         struct resource *ethres, dmares;
1464         u32 value;
1465 
1466         ndev = alloc_etherdev(sizeof(*lp));
1467         if (!ndev)
1468                 return -ENOMEM;
1469 
1470         platform_set_drvdata(pdev, ndev);
1471 
1472         SET_NETDEV_DEV(ndev, &pdev->dev);
1473         ndev->flags &= ~IFF_MULTICAST;  /* clear multicast */
1474         ndev->features = NETIF_F_SG;
1475         ndev->netdev_ops = &axienet_netdev_ops;
1476         ndev->ethtool_ops = &axienet_ethtool_ops;
1477 
1478         lp = netdev_priv(ndev);
1479         lp->ndev = ndev;
1480         lp->dev = &pdev->dev;
1481         lp->options = XAE_OPTION_DEFAULTS;
1482         /* Map device registers */
1483         ethres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1484         lp->regs = devm_ioremap_resource(&pdev->dev, ethres);
1485         if (IS_ERR(lp->regs)) {
1486                 dev_err(&pdev->dev, "could not map Axi Ethernet regs.\n");
1487                 ret = PTR_ERR(lp->regs);
1488                 goto free_netdev;
1489         }
1490 
1491         /* Setup checksum offload, but default to off if not specified */
1492         lp->features = 0;
1493 
1494         ret = of_property_read_u32(pdev->dev.of_node, "xlnx,txcsum", &value);
1495         if (!ret) {
1496                 switch (value) {
1497                 case 1:
1498                         lp->csum_offload_on_tx_path =
1499                                 XAE_FEATURE_PARTIAL_TX_CSUM;
1500                         lp->features |= XAE_FEATURE_PARTIAL_TX_CSUM;
1501                         /* Can checksum TCP/UDP over IPv4. */
1502                         ndev->features |= NETIF_F_IP_CSUM;
1503                         break;
1504                 case 2:
1505                         lp->csum_offload_on_tx_path =
1506                                 XAE_FEATURE_FULL_TX_CSUM;
1507                         lp->features |= XAE_FEATURE_FULL_TX_CSUM;
1508                         /* Can checksum TCP/UDP over IPv4. */
1509                         ndev->features |= NETIF_F_IP_CSUM;
1510                         break;
1511                 default:
1512                         lp->csum_offload_on_tx_path = XAE_NO_CSUM_OFFLOAD;
1513                 }
1514         }
1515         ret = of_property_read_u32(pdev->dev.of_node, "xlnx,rxcsum", &value);
1516         if (!ret) {
1517                 switch (value) {
1518                 case 1:
1519                         lp->csum_offload_on_rx_path =
1520                                 XAE_FEATURE_PARTIAL_RX_CSUM;
1521                         lp->features |= XAE_FEATURE_PARTIAL_RX_CSUM;
1522                         break;
1523                 case 2:
1524                         lp->csum_offload_on_rx_path =
1525                                 XAE_FEATURE_FULL_RX_CSUM;
1526                         lp->features |= XAE_FEATURE_FULL_RX_CSUM;
1527                         break;
1528                 default:
1529                         lp->csum_offload_on_rx_path = XAE_NO_CSUM_OFFLOAD;
1530                 }
1531         }
1532         /* For supporting jumbo frames, the Axi Ethernet hardware must have
1533          * a larger Rx/Tx Memory. Typically, the size must be large so that
1534          * we can enable jumbo option and start supporting jumbo frames.
1535          * Here we check for memory allocated for Rx/Tx in the hardware from
1536          * the device-tree and accordingly set flags.
1537          */
1538         of_property_read_u32(pdev->dev.of_node, "xlnx,rxmem", &lp->rxmem);
1539         of_property_read_u32(pdev->dev.of_node, "xlnx,phy-type", &lp->phy_type);
1540 
1541         /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
1542         np = of_parse_phandle(pdev->dev.of_node, "axistream-connected", 0);
1543         if (!np) {
1544                 dev_err(&pdev->dev, "could not find DMA node\n");
1545                 ret = -ENODEV;
1546                 goto free_netdev;
1547         }
1548         ret = of_address_to_resource(np, 0, &dmares);
1549         if (ret) {
1550                 dev_err(&pdev->dev, "unable to get DMA resource\n");
1551                 goto free_netdev;
1552         }
1553         lp->dma_regs = devm_ioremap_resource(&pdev->dev, &dmares);
1554         if (IS_ERR(lp->dma_regs)) {
1555                 dev_err(&pdev->dev, "could not map DMA regs\n");
1556                 ret = PTR_ERR(lp->dma_regs);
1557                 goto free_netdev;
1558         }
1559         lp->rx_irq = irq_of_parse_and_map(np, 1);
1560         lp->tx_irq = irq_of_parse_and_map(np, 0);
1561         of_node_put(np);
1562         if ((lp->rx_irq <= 0) || (lp->tx_irq <= 0)) {
1563                 dev_err(&pdev->dev, "could not determine irqs\n");
1564                 ret = -ENOMEM;
1565                 goto free_netdev;
1566         }
1567 
1568         /* Retrieve the MAC address */
1569         ret = of_property_read_u8_array(pdev->dev.of_node,
1570                                         "local-mac-address", mac_addr, 6);
1571         if (ret) {
1572                 dev_err(&pdev->dev, "could not find MAC address\n");
1573                 goto free_netdev;
1574         }
1575         axienet_set_mac_address(ndev, (void *)mac_addr);
1576 
1577         lp->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD;
1578         lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
1579 
1580         lp->phy_node = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
1581         if (lp->phy_node) {
1582                 ret = axienet_mdio_setup(lp, pdev->dev.of_node);
1583                 if (ret)
1584                         dev_warn(&pdev->dev, "error registering MDIO bus\n");
1585         }
1586 
1587         ret = register_netdev(lp->ndev);
1588         if (ret) {
1589                 dev_err(lp->dev, "register_netdev() error (%i)\n", ret);
1590                 goto free_netdev;
1591         }
1592 
1593         return 0;
1594 
1595 free_netdev:
1596         free_netdev(ndev);
1597 
1598         return ret;
1599 }
1600 
1601 static int axienet_remove(struct platform_device *pdev)
1602 {
1603         struct net_device *ndev = platform_get_drvdata(pdev);
1604         struct axienet_local *lp = netdev_priv(ndev);
1605 
1606         axienet_mdio_teardown(lp);
1607         unregister_netdev(ndev);
1608 
1609         of_node_put(lp->phy_node);
1610         lp->phy_node = NULL;
1611 
1612         free_netdev(ndev);
1613 
1614         return 0;
1615 }
1616 
1617 static struct platform_driver axienet_driver = {
1618         .probe = axienet_probe,
1619         .remove = axienet_remove,
1620         .driver = {
1621                  .name = "xilinx_axienet",
1622                  .of_match_table = axienet_of_match,
1623         },
1624 };
1625 
1626 module_platform_driver(axienet_driver);
1627 
1628 MODULE_DESCRIPTION("Xilinx Axi Ethernet driver");
1629 MODULE_AUTHOR("Xilinx");
1630 MODULE_LICENSE("GPL");
1631 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us