Version:  2.0.40 2.2.26 2.4.37 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10

Linux/drivers/net/ethernet/xilinx/xilinx_axienet_main.c

  1 /*
  2  * Xilinx Axi Ethernet device driver
  3  *
  4  * Copyright (c) 2008 Nissin Systems Co., Ltd.,  Yoshio Kashiwagi
  5  * Copyright (c) 2005-2008 DLA Systems,  David H. Lynch Jr. <dhlii@dlasys.net>
  6  * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
  7  * Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu>
  8  * Copyright (c) 2010 - 2011 PetaLogix
  9  * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
 10  *
 11  * This is a driver for the Xilinx Axi Ethernet which is used in the Virtex6
 12  * and Spartan6.
 13  *
 14  * TODO:
 15  *  - Add Axi Fifo support.
 16  *  - Factor out Axi DMA code into separate driver.
 17  *  - Test and fix basic multicast filtering.
 18  *  - Add support for extended multicast filtering.
 19  *  - Test basic VLAN support.
 20  *  - Add support for extended VLAN support.
 21  */
 22 
 23 #include <linux/delay.h>
 24 #include <linux/etherdevice.h>
 25 #include <linux/module.h>
 26 #include <linux/netdevice.h>
 27 #include <linux/of_mdio.h>
 28 #include <linux/of_net.h>
 29 #include <linux/of_platform.h>
 30 #include <linux/of_irq.h>
 31 #include <linux/of_address.h>
 32 #include <linux/skbuff.h>
 33 #include <linux/spinlock.h>
 34 #include <linux/phy.h>
 35 #include <linux/mii.h>
 36 #include <linux/ethtool.h>
 37 
 38 #include "xilinx_axienet.h"
 39 
 40 /* Descriptors defines for Tx and Rx DMA - 2^n for the best performance */
 41 #define TX_BD_NUM               64
 42 #define RX_BD_NUM               128
 43 
 44 /* Must be shorter than length of ethtool_drvinfo.driver field to fit */
 45 #define DRIVER_NAME             "xaxienet"
 46 #define DRIVER_DESCRIPTION      "Xilinx Axi Ethernet driver"
 47 #define DRIVER_VERSION          "1.00a"
 48 
 49 #define AXIENET_REGS_N          32
 50 
 51 /* Match table for of_platform binding */
 52 static const struct of_device_id axienet_of_match[] = {
 53         { .compatible = "xlnx,axi-ethernet-1.00.a", },
 54         { .compatible = "xlnx,axi-ethernet-1.01.a", },
 55         { .compatible = "xlnx,axi-ethernet-2.01.a", },
 56         {},
 57 };
 58 
 59 MODULE_DEVICE_TABLE(of, axienet_of_match);
 60 
 61 /* Option table for setting up Axi Ethernet hardware options */
 62 static struct axienet_option axienet_options[] = {
 63         /* Turn on jumbo packet support for both Rx and Tx */
 64         {
 65                 .opt = XAE_OPTION_JUMBO,
 66                 .reg = XAE_TC_OFFSET,
 67                 .m_or = XAE_TC_JUM_MASK,
 68         }, {
 69                 .opt = XAE_OPTION_JUMBO,
 70                 .reg = XAE_RCW1_OFFSET,
 71                 .m_or = XAE_RCW1_JUM_MASK,
 72         }, { /* Turn on VLAN packet support for both Rx and Tx */
 73                 .opt = XAE_OPTION_VLAN,
 74                 .reg = XAE_TC_OFFSET,
 75                 .m_or = XAE_TC_VLAN_MASK,
 76         }, {
 77                 .opt = XAE_OPTION_VLAN,
 78                 .reg = XAE_RCW1_OFFSET,
 79                 .m_or = XAE_RCW1_VLAN_MASK,
 80         }, { /* Turn on FCS stripping on receive packets */
 81                 .opt = XAE_OPTION_FCS_STRIP,
 82                 .reg = XAE_RCW1_OFFSET,
 83                 .m_or = XAE_RCW1_FCS_MASK,
 84         }, { /* Turn on FCS insertion on transmit packets */
 85                 .opt = XAE_OPTION_FCS_INSERT,
 86                 .reg = XAE_TC_OFFSET,
 87                 .m_or = XAE_TC_FCS_MASK,
 88         }, { /* Turn off length/type field checking on receive packets */
 89                 .opt = XAE_OPTION_LENTYPE_ERR,
 90                 .reg = XAE_RCW1_OFFSET,
 91                 .m_or = XAE_RCW1_LT_DIS_MASK,
 92         }, { /* Turn on Rx flow control */
 93                 .opt = XAE_OPTION_FLOW_CONTROL,
 94                 .reg = XAE_FCC_OFFSET,
 95                 .m_or = XAE_FCC_FCRX_MASK,
 96         }, { /* Turn on Tx flow control */
 97                 .opt = XAE_OPTION_FLOW_CONTROL,
 98                 .reg = XAE_FCC_OFFSET,
 99                 .m_or = XAE_FCC_FCTX_MASK,
100         }, { /* Turn on promiscuous frame filtering */
101                 .opt = XAE_OPTION_PROMISC,
102                 .reg = XAE_FMI_OFFSET,
103                 .m_or = XAE_FMI_PM_MASK,
104         }, { /* Enable transmitter */
105                 .opt = XAE_OPTION_TXEN,
106                 .reg = XAE_TC_OFFSET,
107                 .m_or = XAE_TC_TX_MASK,
108         }, { /* Enable receiver */
109                 .opt = XAE_OPTION_RXEN,
110                 .reg = XAE_RCW1_OFFSET,
111                 .m_or = XAE_RCW1_RX_MASK,
112         },
113         {}
114 };
115 
116 /**
117  * axienet_dma_in32 - Memory mapped Axi DMA register read
118  * @lp:         Pointer to axienet local structure
119  * @reg:        Address offset from the base address of the Axi DMA core
120  *
121  * Return: The contents of the Axi DMA register
122  *
123  * This function returns the contents of the corresponding Axi DMA register.
124  */
125 static inline u32 axienet_dma_in32(struct axienet_local *lp, off_t reg)
126 {
127         return in_be32(lp->dma_regs + reg);
128 }
129 
130 /**
131  * axienet_dma_out32 - Memory mapped Axi DMA register write.
132  * @lp:         Pointer to axienet local structure
133  * @reg:        Address offset from the base address of the Axi DMA core
134  * @value:      Value to be written into the Axi DMA register
135  *
136  * This function writes the desired value into the corresponding Axi DMA
137  * register.
138  */
139 static inline void axienet_dma_out32(struct axienet_local *lp,
140                                      off_t reg, u32 value)
141 {
142         out_be32((lp->dma_regs + reg), value);
143 }
144 
145 /**
146  * axienet_dma_bd_release - Release buffer descriptor rings
147  * @ndev:       Pointer to the net_device structure
148  *
149  * This function is used to release the descriptors allocated in
150  * axienet_dma_bd_init. axienet_dma_bd_release is called when Axi Ethernet
151  * driver stop api is called.
152  */
153 static void axienet_dma_bd_release(struct net_device *ndev)
154 {
155         int i;
156         struct axienet_local *lp = netdev_priv(ndev);
157 
158         for (i = 0; i < RX_BD_NUM; i++) {
159                 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
160                                  lp->max_frm_size, DMA_FROM_DEVICE);
161                 dev_kfree_skb((struct sk_buff *)
162                               (lp->rx_bd_v[i].sw_id_offset));
163         }
164 
165         if (lp->rx_bd_v) {
166                 dma_free_coherent(ndev->dev.parent,
167                                   sizeof(*lp->rx_bd_v) * RX_BD_NUM,
168                                   lp->rx_bd_v,
169                                   lp->rx_bd_p);
170         }
171         if (lp->tx_bd_v) {
172                 dma_free_coherent(ndev->dev.parent,
173                                   sizeof(*lp->tx_bd_v) * TX_BD_NUM,
174                                   lp->tx_bd_v,
175                                   lp->tx_bd_p);
176         }
177 }
178 
179 /**
180  * axienet_dma_bd_init - Setup buffer descriptor rings for Axi DMA
181  * @ndev:       Pointer to the net_device structure
182  *
183  * Return: 0, on success -ENOMEM, on failure
184  *
185  * This function is called to initialize the Rx and Tx DMA descriptor
186  * rings. This initializes the descriptors with required default values
187  * and is called when Axi Ethernet driver reset is called.
188  */
189 static int axienet_dma_bd_init(struct net_device *ndev)
190 {
191         u32 cr;
192         int i;
193         struct sk_buff *skb;
194         struct axienet_local *lp = netdev_priv(ndev);
195 
196         /* Reset the indexes which are used for accessing the BDs */
197         lp->tx_bd_ci = 0;
198         lp->tx_bd_tail = 0;
199         lp->rx_bd_ci = 0;
200 
201         /* Allocate the Tx and Rx buffer descriptors. */
202         lp->tx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
203                                           sizeof(*lp->tx_bd_v) * TX_BD_NUM,
204                                           &lp->tx_bd_p, GFP_KERNEL);
205         if (!lp->tx_bd_v)
206                 goto out;
207 
208         lp->rx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
209                                           sizeof(*lp->rx_bd_v) * RX_BD_NUM,
210                                           &lp->rx_bd_p, GFP_KERNEL);
211         if (!lp->rx_bd_v)
212                 goto out;
213 
214         for (i = 0; i < TX_BD_NUM; i++) {
215                 lp->tx_bd_v[i].next = lp->tx_bd_p +
216                                       sizeof(*lp->tx_bd_v) *
217                                       ((i + 1) % TX_BD_NUM);
218         }
219 
220         for (i = 0; i < RX_BD_NUM; i++) {
221                 lp->rx_bd_v[i].next = lp->rx_bd_p +
222                                       sizeof(*lp->rx_bd_v) *
223                                       ((i + 1) % RX_BD_NUM);
224 
225                 skb = netdev_alloc_skb_ip_align(ndev, lp->max_frm_size);
226                 if (!skb)
227                         goto out;
228 
229                 lp->rx_bd_v[i].sw_id_offset = (u32) skb;
230                 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
231                                                      skb->data,
232                                                      lp->max_frm_size,
233                                                      DMA_FROM_DEVICE);
234                 lp->rx_bd_v[i].cntrl = lp->max_frm_size;
235         }
236 
237         /* Start updating the Rx channel control register */
238         cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
239         /* Update the interrupt coalesce count */
240         cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
241               ((lp->coalesce_count_rx) << XAXIDMA_COALESCE_SHIFT));
242         /* Update the delay timer count */
243         cr = ((cr & ~XAXIDMA_DELAY_MASK) |
244               (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
245         /* Enable coalesce, delay timer and error interrupts */
246         cr |= XAXIDMA_IRQ_ALL_MASK;
247         /* Write to the Rx channel control register */
248         axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
249 
250         /* Start updating the Tx channel control register */
251         cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
252         /* Update the interrupt coalesce count */
253         cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
254               ((lp->coalesce_count_tx) << XAXIDMA_COALESCE_SHIFT));
255         /* Update the delay timer count */
256         cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
257               (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
258         /* Enable coalesce, delay timer and error interrupts */
259         cr |= XAXIDMA_IRQ_ALL_MASK;
260         /* Write to the Tx channel control register */
261         axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
262 
263         /* Populate the tail pointer and bring the Rx Axi DMA engine out of
264          * halted state. This will make the Rx side ready for reception.
265          */
266         axienet_dma_out32(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
267         cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
268         axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
269                           cr | XAXIDMA_CR_RUNSTOP_MASK);
270         axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
271                           (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
272 
273         /* Write to the RS (Run-stop) bit in the Tx channel control register.
274          * Tx channel is now ready to run. But only after we write to the
275          * tail pointer register that the Tx channel will start transmitting.
276          */
277         axienet_dma_out32(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
278         cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
279         axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
280                           cr | XAXIDMA_CR_RUNSTOP_MASK);
281 
282         return 0;
283 out:
284         axienet_dma_bd_release(ndev);
285         return -ENOMEM;
286 }
287 
288 /**
289  * axienet_set_mac_address - Write the MAC address
290  * @ndev:       Pointer to the net_device structure
291  * @address:    6 byte Address to be written as MAC address
292  *
293  * This function is called to initialize the MAC address of the Axi Ethernet
294  * core. It writes to the UAW0 and UAW1 registers of the core.
295  */
296 static void axienet_set_mac_address(struct net_device *ndev,
297                                     const void *address)
298 {
299         struct axienet_local *lp = netdev_priv(ndev);
300 
301         if (address)
302                 memcpy(ndev->dev_addr, address, ETH_ALEN);
303         if (!is_valid_ether_addr(ndev->dev_addr))
304                 eth_random_addr(ndev->dev_addr);
305 
306         /* Set up unicast MAC address filter set its mac address */
307         axienet_iow(lp, XAE_UAW0_OFFSET,
308                     (ndev->dev_addr[0]) |
309                     (ndev->dev_addr[1] << 8) |
310                     (ndev->dev_addr[2] << 16) |
311                     (ndev->dev_addr[3] << 24));
312         axienet_iow(lp, XAE_UAW1_OFFSET,
313                     (((axienet_ior(lp, XAE_UAW1_OFFSET)) &
314                       ~XAE_UAW1_UNICASTADDR_MASK) |
315                      (ndev->dev_addr[4] |
316                      (ndev->dev_addr[5] << 8))));
317 }
318 
319 /**
320  * netdev_set_mac_address - Write the MAC address (from outside the driver)
321  * @ndev:       Pointer to the net_device structure
322  * @p:          6 byte Address to be written as MAC address
323  *
324  * Return: 0 for all conditions. Presently, there is no failure case.
325  *
326  * This function is called to initialize the MAC address of the Axi Ethernet
327  * core. It calls the core specific axienet_set_mac_address. This is the
328  * function that goes into net_device_ops structure entry ndo_set_mac_address.
329  */
330 static int netdev_set_mac_address(struct net_device *ndev, void *p)
331 {
332         struct sockaddr *addr = p;
333         axienet_set_mac_address(ndev, addr->sa_data);
334         return 0;
335 }
336 
337 /**
338  * axienet_set_multicast_list - Prepare the multicast table
339  * @ndev:       Pointer to the net_device structure
340  *
341  * This function is called to initialize the multicast table during
342  * initialization. The Axi Ethernet basic multicast support has a four-entry
343  * multicast table which is initialized here. Additionally this function
344  * goes into the net_device_ops structure entry ndo_set_multicast_list. This
345  * means whenever the multicast table entries need to be updated this
346  * function gets called.
347  */
348 static void axienet_set_multicast_list(struct net_device *ndev)
349 {
350         int i;
351         u32 reg, af0reg, af1reg;
352         struct axienet_local *lp = netdev_priv(ndev);
353 
354         if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
355             netdev_mc_count(ndev) > XAE_MULTICAST_CAM_TABLE_NUM) {
356                 /* We must make the kernel realize we had to move into
357                  * promiscuous mode. If it was a promiscuous mode request
358                  * the flag is already set. If not we set it.
359                  */
360                 ndev->flags |= IFF_PROMISC;
361                 reg = axienet_ior(lp, XAE_FMI_OFFSET);
362                 reg |= XAE_FMI_PM_MASK;
363                 axienet_iow(lp, XAE_FMI_OFFSET, reg);
364                 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
365         } else if (!netdev_mc_empty(ndev)) {
366                 struct netdev_hw_addr *ha;
367 
368                 i = 0;
369                 netdev_for_each_mc_addr(ha, ndev) {
370                         if (i >= XAE_MULTICAST_CAM_TABLE_NUM)
371                                 break;
372 
373                         af0reg = (ha->addr[0]);
374                         af0reg |= (ha->addr[1] << 8);
375                         af0reg |= (ha->addr[2] << 16);
376                         af0reg |= (ha->addr[3] << 24);
377 
378                         af1reg = (ha->addr[4]);
379                         af1reg |= (ha->addr[5] << 8);
380 
381                         reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00;
382                         reg |= i;
383 
384                         axienet_iow(lp, XAE_FMI_OFFSET, reg);
385                         axienet_iow(lp, XAE_AF0_OFFSET, af0reg);
386                         axienet_iow(lp, XAE_AF1_OFFSET, af1reg);
387                         i++;
388                 }
389         } else {
390                 reg = axienet_ior(lp, XAE_FMI_OFFSET);
391                 reg &= ~XAE_FMI_PM_MASK;
392 
393                 axienet_iow(lp, XAE_FMI_OFFSET, reg);
394 
395                 for (i = 0; i < XAE_MULTICAST_CAM_TABLE_NUM; i++) {
396                         reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00;
397                         reg |= i;
398 
399                         axienet_iow(lp, XAE_FMI_OFFSET, reg);
400                         axienet_iow(lp, XAE_AF0_OFFSET, 0);
401                         axienet_iow(lp, XAE_AF1_OFFSET, 0);
402                 }
403 
404                 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
405         }
406 }
407 
408 /**
409  * axienet_setoptions - Set an Axi Ethernet option
410  * @ndev:       Pointer to the net_device structure
411  * @options:    Option to be enabled/disabled
412  *
413  * The Axi Ethernet core has multiple features which can be selectively turned
414  * on or off. The typical options could be jumbo frame option, basic VLAN
415  * option, promiscuous mode option etc. This function is used to set or clear
416  * these options in the Axi Ethernet hardware. This is done through
417  * axienet_option structure .
418  */
419 static void axienet_setoptions(struct net_device *ndev, u32 options)
420 {
421         int reg;
422         struct axienet_local *lp = netdev_priv(ndev);
423         struct axienet_option *tp = &axienet_options[0];
424 
425         while (tp->opt) {
426                 reg = ((axienet_ior(lp, tp->reg)) & ~(tp->m_or));
427                 if (options & tp->opt)
428                         reg |= tp->m_or;
429                 axienet_iow(lp, tp->reg, reg);
430                 tp++;
431         }
432 
433         lp->options |= options;
434 }
435 
436 static void __axienet_device_reset(struct axienet_local *lp, off_t offset)
437 {
438         u32 timeout;
439         /* Reset Axi DMA. This would reset Axi Ethernet core as well. The reset
440          * process of Axi DMA takes a while to complete as all pending
441          * commands/transfers will be flushed or completed during this
442          * reset process.
443          */
444         axienet_dma_out32(lp, offset, XAXIDMA_CR_RESET_MASK);
445         timeout = DELAY_OF_ONE_MILLISEC;
446         while (axienet_dma_in32(lp, offset) & XAXIDMA_CR_RESET_MASK) {
447                 udelay(1);
448                 if (--timeout == 0) {
449                         netdev_err(lp->ndev, "%s: DMA reset timeout!\n",
450                                    __func__);
451                         break;
452                 }
453         }
454 }
455 
456 /**
457  * axienet_device_reset - Reset and initialize the Axi Ethernet hardware.
458  * @ndev:       Pointer to the net_device structure
459  *
460  * This function is called to reset and initialize the Axi Ethernet core. This
461  * is typically called during initialization. It does a reset of the Axi DMA
462  * Rx/Tx channels and initializes the Axi DMA BDs. Since Axi DMA reset lines
463  * areconnected to Axi Ethernet reset lines, this in turn resets the Axi
464  * Ethernet core. No separate hardware reset is done for the Axi Ethernet
465  * core.
466  */
467 static void axienet_device_reset(struct net_device *ndev)
468 {
469         u32 axienet_status;
470         struct axienet_local *lp = netdev_priv(ndev);
471 
472         __axienet_device_reset(lp, XAXIDMA_TX_CR_OFFSET);
473         __axienet_device_reset(lp, XAXIDMA_RX_CR_OFFSET);
474 
475         lp->max_frm_size = XAE_MAX_VLAN_FRAME_SIZE;
476         lp->options |= XAE_OPTION_VLAN;
477         lp->options &= (~XAE_OPTION_JUMBO);
478 
479         if ((ndev->mtu > XAE_MTU) &&
480                 (ndev->mtu <= XAE_JUMBO_MTU)) {
481                 lp->max_frm_size = ndev->mtu + VLAN_ETH_HLEN +
482                                         XAE_TRL_SIZE;
483 
484                 if (lp->max_frm_size <= lp->rxmem)
485                         lp->options |= XAE_OPTION_JUMBO;
486         }
487 
488         if (axienet_dma_bd_init(ndev)) {
489                 netdev_err(ndev, "%s: descriptor allocation failed\n",
490                            __func__);
491         }
492 
493         axienet_status = axienet_ior(lp, XAE_RCW1_OFFSET);
494         axienet_status &= ~XAE_RCW1_RX_MASK;
495         axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status);
496 
497         axienet_status = axienet_ior(lp, XAE_IP_OFFSET);
498         if (axienet_status & XAE_INT_RXRJECT_MASK)
499                 axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK);
500 
501         axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);
502 
503         /* Sync default options with HW but leave receiver and
504          * transmitter disabled.
505          */
506         axienet_setoptions(ndev, lp->options &
507                            ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
508         axienet_set_mac_address(ndev, NULL);
509         axienet_set_multicast_list(ndev);
510         axienet_setoptions(ndev, lp->options);
511 
512         netif_trans_update(ndev);
513 }
514 
515 /**
516  * axienet_adjust_link - Adjust the PHY link speed/duplex.
517  * @ndev:       Pointer to the net_device structure
518  *
519  * This function is called to change the speed and duplex setting after
520  * auto negotiation is done by the PHY. This is the function that gets
521  * registered with the PHY interface through the "of_phy_connect" call.
522  */
523 static void axienet_adjust_link(struct net_device *ndev)
524 {
525         u32 emmc_reg;
526         u32 link_state;
527         u32 setspeed = 1;
528         struct axienet_local *lp = netdev_priv(ndev);
529         struct phy_device *phy = ndev->phydev;
530 
531         link_state = phy->speed | (phy->duplex << 1) | phy->link;
532         if (lp->last_link != link_state) {
533                 if ((phy->speed == SPEED_10) || (phy->speed == SPEED_100)) {
534                         if (lp->phy_type == XAE_PHY_TYPE_1000BASE_X)
535                                 setspeed = 0;
536                 } else {
537                         if ((phy->speed == SPEED_1000) &&
538                             (lp->phy_type == XAE_PHY_TYPE_MII))
539                                 setspeed = 0;
540                 }
541 
542                 if (setspeed == 1) {
543                         emmc_reg = axienet_ior(lp, XAE_EMMC_OFFSET);
544                         emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
545 
546                         switch (phy->speed) {
547                         case SPEED_1000:
548                                 emmc_reg |= XAE_EMMC_LINKSPD_1000;
549                                 break;
550                         case SPEED_100:
551                                 emmc_reg |= XAE_EMMC_LINKSPD_100;
552                                 break;
553                         case SPEED_10:
554                                 emmc_reg |= XAE_EMMC_LINKSPD_10;
555                                 break;
556                         default:
557                                 dev_err(&ndev->dev, "Speed other than 10, 100 "
558                                         "or 1Gbps is not supported\n");
559                                 break;
560                         }
561 
562                         axienet_iow(lp, XAE_EMMC_OFFSET, emmc_reg);
563                         lp->last_link = link_state;
564                         phy_print_status(phy);
565                 } else {
566                         netdev_err(ndev,
567                                    "Error setting Axi Ethernet mac speed\n");
568                 }
569         }
570 }
571 
572 /**
573  * axienet_start_xmit_done - Invoked once a transmit is completed by the
574  * Axi DMA Tx channel.
575  * @ndev:       Pointer to the net_device structure
576  *
577  * This function is invoked from the Axi DMA Tx isr to notify the completion
578  * of transmit operation. It clears fields in the corresponding Tx BDs and
579  * unmaps the corresponding buffer so that CPU can regain ownership of the
580  * buffer. It finally invokes "netif_wake_queue" to restart transmission if
581  * required.
582  */
583 static void axienet_start_xmit_done(struct net_device *ndev)
584 {
585         u32 size = 0;
586         u32 packets = 0;
587         struct axienet_local *lp = netdev_priv(ndev);
588         struct axidma_bd *cur_p;
589         unsigned int status = 0;
590 
591         cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
592         status = cur_p->status;
593         while (status & XAXIDMA_BD_STS_COMPLETE_MASK) {
594                 dma_unmap_single(ndev->dev.parent, cur_p->phys,
595                                 (cur_p->cntrl & XAXIDMA_BD_CTRL_LENGTH_MASK),
596                                 DMA_TO_DEVICE);
597                 if (cur_p->app4)
598                         dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
599                 /*cur_p->phys = 0;*/
600                 cur_p->app0 = 0;
601                 cur_p->app1 = 0;
602                 cur_p->app2 = 0;
603                 cur_p->app4 = 0;
604                 cur_p->status = 0;
605 
606                 size += status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
607                 packets++;
608 
609                 ++lp->tx_bd_ci;
610                 lp->tx_bd_ci %= TX_BD_NUM;
611                 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
612                 status = cur_p->status;
613         }
614 
615         ndev->stats.tx_packets += packets;
616         ndev->stats.tx_bytes += size;
617         netif_wake_queue(ndev);
618 }
619 
620 /**
621  * axienet_check_tx_bd_space - Checks if a BD/group of BDs are currently busy
622  * @lp:         Pointer to the axienet_local structure
623  * @num_frag:   The number of BDs to check for
624  *
625  * Return: 0, on success
626  *          NETDEV_TX_BUSY, if any of the descriptors are not free
627  *
628  * This function is invoked before BDs are allocated and transmission starts.
629  * This function returns 0 if a BD or group of BDs can be allocated for
630  * transmission. If the BD or any of the BDs are not free the function
631  * returns a busy status. This is invoked from axienet_start_xmit.
632  */
633 static inline int axienet_check_tx_bd_space(struct axienet_local *lp,
634                                             int num_frag)
635 {
636         struct axidma_bd *cur_p;
637         cur_p = &lp->tx_bd_v[(lp->tx_bd_tail + num_frag) % TX_BD_NUM];
638         if (cur_p->status & XAXIDMA_BD_STS_ALL_MASK)
639                 return NETDEV_TX_BUSY;
640         return 0;
641 }
642 
643 /**
644  * axienet_start_xmit - Starts the transmission.
645  * @skb:        sk_buff pointer that contains data to be Txed.
646  * @ndev:       Pointer to net_device structure.
647  *
648  * Return: NETDEV_TX_OK, on success
649  *          NETDEV_TX_BUSY, if any of the descriptors are not free
650  *
651  * This function is invoked from upper layers to initiate transmission. The
652  * function uses the next available free BDs and populates their fields to
653  * start the transmission. Additionally if checksum offloading is supported,
654  * it populates AXI Stream Control fields with appropriate values.
655  */
656 static int axienet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
657 {
658         u32 ii;
659         u32 num_frag;
660         u32 csum_start_off;
661         u32 csum_index_off;
662         skb_frag_t *frag;
663         dma_addr_t tail_p;
664         struct axienet_local *lp = netdev_priv(ndev);
665         struct axidma_bd *cur_p;
666 
667         num_frag = skb_shinfo(skb)->nr_frags;
668         cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
669 
670         if (axienet_check_tx_bd_space(lp, num_frag)) {
671                 if (!netif_queue_stopped(ndev))
672                         netif_stop_queue(ndev);
673                 return NETDEV_TX_BUSY;
674         }
675 
676         if (skb->ip_summed == CHECKSUM_PARTIAL) {
677                 if (lp->features & XAE_FEATURE_FULL_TX_CSUM) {
678                         /* Tx Full Checksum Offload Enabled */
679                         cur_p->app0 |= 2;
680                 } else if (lp->features & XAE_FEATURE_PARTIAL_RX_CSUM) {
681                         csum_start_off = skb_transport_offset(skb);
682                         csum_index_off = csum_start_off + skb->csum_offset;
683                         /* Tx Partial Checksum Offload Enabled */
684                         cur_p->app0 |= 1;
685                         cur_p->app1 = (csum_start_off << 16) | csum_index_off;
686                 }
687         } else if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
688                 cur_p->app0 |= 2; /* Tx Full Checksum Offload Enabled */
689         }
690 
691         cur_p->cntrl = skb_headlen(skb) | XAXIDMA_BD_CTRL_TXSOF_MASK;
692         cur_p->phys = dma_map_single(ndev->dev.parent, skb->data,
693                                      skb_headlen(skb), DMA_TO_DEVICE);
694 
695         for (ii = 0; ii < num_frag; ii++) {
696                 ++lp->tx_bd_tail;
697                 lp->tx_bd_tail %= TX_BD_NUM;
698                 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
699                 frag = &skb_shinfo(skb)->frags[ii];
700                 cur_p->phys = dma_map_single(ndev->dev.parent,
701                                              skb_frag_address(frag),
702                                              skb_frag_size(frag),
703                                              DMA_TO_DEVICE);
704                 cur_p->cntrl = skb_frag_size(frag);
705         }
706 
707         cur_p->cntrl |= XAXIDMA_BD_CTRL_TXEOF_MASK;
708         cur_p->app4 = (unsigned long)skb;
709 
710         tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
711         /* Start the transfer */
712         axienet_dma_out32(lp, XAXIDMA_TX_TDESC_OFFSET, tail_p);
713         ++lp->tx_bd_tail;
714         lp->tx_bd_tail %= TX_BD_NUM;
715 
716         return NETDEV_TX_OK;
717 }
718 
719 /**
720  * axienet_recv - Is called from Axi DMA Rx Isr to complete the received
721  *                BD processing.
722  * @ndev:       Pointer to net_device structure.
723  *
724  * This function is invoked from the Axi DMA Rx isr to process the Rx BDs. It
725  * does minimal processing and invokes "netif_rx" to complete further
726  * processing.
727  */
728 static void axienet_recv(struct net_device *ndev)
729 {
730         u32 length;
731         u32 csumstatus;
732         u32 size = 0;
733         u32 packets = 0;
734         dma_addr_t tail_p = 0;
735         struct axienet_local *lp = netdev_priv(ndev);
736         struct sk_buff *skb, *new_skb;
737         struct axidma_bd *cur_p;
738 
739         cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
740 
741         while ((cur_p->status & XAXIDMA_BD_STS_COMPLETE_MASK)) {
742                 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
743                 skb = (struct sk_buff *) (cur_p->sw_id_offset);
744                 length = cur_p->app4 & 0x0000FFFF;
745 
746                 dma_unmap_single(ndev->dev.parent, cur_p->phys,
747                                  lp->max_frm_size,
748                                  DMA_FROM_DEVICE);
749 
750                 skb_put(skb, length);
751                 skb->protocol = eth_type_trans(skb, ndev);
752                 /*skb_checksum_none_assert(skb);*/
753                 skb->ip_summed = CHECKSUM_NONE;
754 
755                 /* if we're doing Rx csum offload, set it up */
756                 if (lp->features & XAE_FEATURE_FULL_RX_CSUM) {
757                         csumstatus = (cur_p->app2 &
758                                       XAE_FULL_CSUM_STATUS_MASK) >> 3;
759                         if ((csumstatus == XAE_IP_TCP_CSUM_VALIDATED) ||
760                             (csumstatus == XAE_IP_UDP_CSUM_VALIDATED)) {
761                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
762                         }
763                 } else if ((lp->features & XAE_FEATURE_PARTIAL_RX_CSUM) != 0 &&
764                            skb->protocol == htons(ETH_P_IP) &&
765                            skb->len > 64) {
766                         skb->csum = be32_to_cpu(cur_p->app3 & 0xFFFF);
767                         skb->ip_summed = CHECKSUM_COMPLETE;
768                 }
769 
770                 netif_rx(skb);
771 
772                 size += length;
773                 packets++;
774 
775                 new_skb = netdev_alloc_skb_ip_align(ndev, lp->max_frm_size);
776                 if (!new_skb)
777                         return;
778 
779                 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
780                                              lp->max_frm_size,
781                                              DMA_FROM_DEVICE);
782                 cur_p->cntrl = lp->max_frm_size;
783                 cur_p->status = 0;
784                 cur_p->sw_id_offset = (u32) new_skb;
785 
786                 ++lp->rx_bd_ci;
787                 lp->rx_bd_ci %= RX_BD_NUM;
788                 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
789         }
790 
791         ndev->stats.rx_packets += packets;
792         ndev->stats.rx_bytes += size;
793 
794         if (tail_p)
795                 axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, tail_p);
796 }
797 
798 /**
799  * axienet_tx_irq - Tx Done Isr.
800  * @irq:        irq number
801  * @_ndev:      net_device pointer
802  *
803  * Return: IRQ_HANDLED for all cases.
804  *
805  * This is the Axi DMA Tx done Isr. It invokes "axienet_start_xmit_done"
806  * to complete the BD processing.
807  */
808 static irqreturn_t axienet_tx_irq(int irq, void *_ndev)
809 {
810         u32 cr;
811         unsigned int status;
812         struct net_device *ndev = _ndev;
813         struct axienet_local *lp = netdev_priv(ndev);
814 
815         status = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET);
816         if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
817                 axienet_dma_out32(lp, XAXIDMA_TX_SR_OFFSET, status);
818                 axienet_start_xmit_done(lp->ndev);
819                 goto out;
820         }
821         if (!(status & XAXIDMA_IRQ_ALL_MASK))
822                 dev_err(&ndev->dev, "No interrupts asserted in Tx path\n");
823         if (status & XAXIDMA_IRQ_ERROR_MASK) {
824                 dev_err(&ndev->dev, "DMA Tx error 0x%x\n", status);
825                 dev_err(&ndev->dev, "Current BD is at: 0x%x\n",
826                         (lp->tx_bd_v[lp->tx_bd_ci]).phys);
827 
828                 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
829                 /* Disable coalesce, delay timer and error interrupts */
830                 cr &= (~XAXIDMA_IRQ_ALL_MASK);
831                 /* Write to the Tx channel control register */
832                 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
833 
834                 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
835                 /* Disable coalesce, delay timer and error interrupts */
836                 cr &= (~XAXIDMA_IRQ_ALL_MASK);
837                 /* Write to the Rx channel control register */
838                 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
839 
840                 tasklet_schedule(&lp->dma_err_tasklet);
841                 axienet_dma_out32(lp, XAXIDMA_TX_SR_OFFSET, status);
842         }
843 out:
844         return IRQ_HANDLED;
845 }
846 
847 /**
848  * axienet_rx_irq - Rx Isr.
849  * @irq:        irq number
850  * @_ndev:      net_device pointer
851  *
852  * Return: IRQ_HANDLED for all cases.
853  *
854  * This is the Axi DMA Rx Isr. It invokes "axienet_recv" to complete the BD
855  * processing.
856  */
857 static irqreturn_t axienet_rx_irq(int irq, void *_ndev)
858 {
859         u32 cr;
860         unsigned int status;
861         struct net_device *ndev = _ndev;
862         struct axienet_local *lp = netdev_priv(ndev);
863 
864         status = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET);
865         if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
866                 axienet_dma_out32(lp, XAXIDMA_RX_SR_OFFSET, status);
867                 axienet_recv(lp->ndev);
868                 goto out;
869         }
870         if (!(status & XAXIDMA_IRQ_ALL_MASK))
871                 dev_err(&ndev->dev, "No interrupts asserted in Rx path\n");
872         if (status & XAXIDMA_IRQ_ERROR_MASK) {
873                 dev_err(&ndev->dev, "DMA Rx error 0x%x\n", status);
874                 dev_err(&ndev->dev, "Current BD is at: 0x%x\n",
875                         (lp->rx_bd_v[lp->rx_bd_ci]).phys);
876 
877                 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
878                 /* Disable coalesce, delay timer and error interrupts */
879                 cr &= (~XAXIDMA_IRQ_ALL_MASK);
880                 /* Finally write to the Tx channel control register */
881                 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
882 
883                 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
884                 /* Disable coalesce, delay timer and error interrupts */
885                 cr &= (~XAXIDMA_IRQ_ALL_MASK);
886                 /* write to the Rx channel control register */
887                 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
888 
889                 tasklet_schedule(&lp->dma_err_tasklet);
890                 axienet_dma_out32(lp, XAXIDMA_RX_SR_OFFSET, status);
891         }
892 out:
893         return IRQ_HANDLED;
894 }
895 
896 static void axienet_dma_err_handler(unsigned long data);
897 
898 /**
899  * axienet_open - Driver open routine.
900  * @ndev:       Pointer to net_device structure
901  *
902  * Return: 0, on success.
903  *          -ENODEV, if PHY cannot be connected to
904  *          non-zero error value on failure
905  *
906  * This is the driver open routine. It calls phy_start to start the PHY device.
907  * It also allocates interrupt service routines, enables the interrupt lines
908  * and ISR handling. Axi Ethernet core is reset through Axi DMA core. Buffer
909  * descriptors are initialized.
910  */
911 static int axienet_open(struct net_device *ndev)
912 {
913         int ret, mdio_mcreg;
914         struct axienet_local *lp = netdev_priv(ndev);
915         struct phy_device *phydev = NULL;
916 
917         dev_dbg(&ndev->dev, "axienet_open()\n");
918 
919         mdio_mcreg = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
920         ret = axienet_mdio_wait_until_ready(lp);
921         if (ret < 0)
922                 return ret;
923         /* Disable the MDIO interface till Axi Ethernet Reset is completed.
924          * When we do an Axi Ethernet reset, it resets the complete core
925          * including the MDIO. If MDIO is not disabled when the reset
926          * process is started, MDIO will be broken afterwards.
927          */
928         axienet_iow(lp, XAE_MDIO_MC_OFFSET,
929                     (mdio_mcreg & (~XAE_MDIO_MC_MDIOEN_MASK)));
930         axienet_device_reset(ndev);
931         /* Enable the MDIO */
932         axienet_iow(lp, XAE_MDIO_MC_OFFSET, mdio_mcreg);
933         ret = axienet_mdio_wait_until_ready(lp);
934         if (ret < 0)
935                 return ret;
936 
937         if (lp->phy_node) {
938                 if (lp->phy_type == XAE_PHY_TYPE_GMII) {
939                         phydev = of_phy_connect(lp->ndev, lp->phy_node,
940                                                 axienet_adjust_link, 0,
941                                                 PHY_INTERFACE_MODE_GMII);
942                 } else if (lp->phy_type == XAE_PHY_TYPE_RGMII_2_0) {
943                         phydev = of_phy_connect(lp->ndev, lp->phy_node,
944                                                 axienet_adjust_link, 0,
945                                                 PHY_INTERFACE_MODE_RGMII_ID);
946                 }
947 
948                 if (!phydev)
949                         dev_err(lp->dev, "of_phy_connect() failed\n");
950                 else
951                         phy_start(phydev);
952         }
953 
954         /* Enable tasklets for Axi DMA error handling */
955         tasklet_init(&lp->dma_err_tasklet, axienet_dma_err_handler,
956                      (unsigned long) lp);
957 
958         /* Enable interrupts for Axi DMA Tx */
959         ret = request_irq(lp->tx_irq, axienet_tx_irq, 0, ndev->name, ndev);
960         if (ret)
961                 goto err_tx_irq;
962         /* Enable interrupts for Axi DMA Rx */
963         ret = request_irq(lp->rx_irq, axienet_rx_irq, 0, ndev->name, ndev);
964         if (ret)
965                 goto err_rx_irq;
966 
967         return 0;
968 
969 err_rx_irq:
970         free_irq(lp->tx_irq, ndev);
971 err_tx_irq:
972         if (phydev)
973                 phy_disconnect(phydev);
974         tasklet_kill(&lp->dma_err_tasklet);
975         dev_err(lp->dev, "request_irq() failed\n");
976         return ret;
977 }
978 
979 /**
980  * axienet_stop - Driver stop routine.
981  * @ndev:       Pointer to net_device structure
982  *
983  * Return: 0, on success.
984  *
985  * This is the driver stop routine. It calls phy_disconnect to stop the PHY
986  * device. It also removes the interrupt handlers and disables the interrupts.
987  * The Axi DMA Tx/Rx BDs are released.
988  */
989 static int axienet_stop(struct net_device *ndev)
990 {
991         u32 cr;
992         struct axienet_local *lp = netdev_priv(ndev);
993 
994         dev_dbg(&ndev->dev, "axienet_close()\n");
995 
996         cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
997         axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
998                           cr & (~XAXIDMA_CR_RUNSTOP_MASK));
999         cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1000         axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
1001                           cr & (~XAXIDMA_CR_RUNSTOP_MASK));
1002         axienet_setoptions(ndev, lp->options &
1003                            ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1004 
1005         tasklet_kill(&lp->dma_err_tasklet);
1006 
1007         free_irq(lp->tx_irq, ndev);
1008         free_irq(lp->rx_irq, ndev);
1009 
1010         if (ndev->phydev)
1011                 phy_disconnect(ndev->phydev);
1012 
1013         axienet_dma_bd_release(ndev);
1014         return 0;
1015 }
1016 
1017 /**
1018  * axienet_change_mtu - Driver change mtu routine.
1019  * @ndev:       Pointer to net_device structure
1020  * @new_mtu:    New mtu value to be applied
1021  *
1022  * Return: Always returns 0 (success).
1023  *
1024  * This is the change mtu driver routine. It checks if the Axi Ethernet
1025  * hardware supports jumbo frames before changing the mtu. This can be
1026  * called only when the device is not up.
1027  */
1028 static int axienet_change_mtu(struct net_device *ndev, int new_mtu)
1029 {
1030         struct axienet_local *lp = netdev_priv(ndev);
1031 
1032         if (netif_running(ndev))
1033                 return -EBUSY;
1034 
1035         if ((new_mtu + VLAN_ETH_HLEN +
1036                 XAE_TRL_SIZE) > lp->rxmem)
1037                 return -EINVAL;
1038 
1039         ndev->mtu = new_mtu;
1040 
1041         return 0;
1042 }
1043 
1044 #ifdef CONFIG_NET_POLL_CONTROLLER
1045 /**
1046  * axienet_poll_controller - Axi Ethernet poll mechanism.
1047  * @ndev:       Pointer to net_device structure
1048  *
1049  * This implements Rx/Tx ISR poll mechanisms. The interrupts are disabled prior
1050  * to polling the ISRs and are enabled back after the polling is done.
1051  */
1052 static void axienet_poll_controller(struct net_device *ndev)
1053 {
1054         struct axienet_local *lp = netdev_priv(ndev);
1055         disable_irq(lp->tx_irq);
1056         disable_irq(lp->rx_irq);
1057         axienet_rx_irq(lp->tx_irq, ndev);
1058         axienet_tx_irq(lp->rx_irq, ndev);
1059         enable_irq(lp->tx_irq);
1060         enable_irq(lp->rx_irq);
1061 }
1062 #endif
1063 
1064 static const struct net_device_ops axienet_netdev_ops = {
1065         .ndo_open = axienet_open,
1066         .ndo_stop = axienet_stop,
1067         .ndo_start_xmit = axienet_start_xmit,
1068         .ndo_change_mtu = axienet_change_mtu,
1069         .ndo_set_mac_address = netdev_set_mac_address,
1070         .ndo_validate_addr = eth_validate_addr,
1071         .ndo_set_rx_mode = axienet_set_multicast_list,
1072 #ifdef CONFIG_NET_POLL_CONTROLLER
1073         .ndo_poll_controller = axienet_poll_controller,
1074 #endif
1075 };
1076 
1077 /**
1078  * axienet_ethtools_get_drvinfo - Get various Axi Ethernet driver information.
1079  * @ndev:       Pointer to net_device structure
1080  * @ed:         Pointer to ethtool_drvinfo structure
1081  *
1082  * This implements ethtool command for getting the driver information.
1083  * Issue "ethtool -i ethX" under linux prompt to execute this function.
1084  */
1085 static void axienet_ethtools_get_drvinfo(struct net_device *ndev,
1086                                          struct ethtool_drvinfo *ed)
1087 {
1088         strlcpy(ed->driver, DRIVER_NAME, sizeof(ed->driver));
1089         strlcpy(ed->version, DRIVER_VERSION, sizeof(ed->version));
1090 }
1091 
1092 /**
1093  * axienet_ethtools_get_regs_len - Get the total regs length present in the
1094  *                                 AxiEthernet core.
1095  * @ndev:       Pointer to net_device structure
1096  *
1097  * This implements ethtool command for getting the total register length
1098  * information.
1099  *
1100  * Return: the total regs length
1101  */
1102 static int axienet_ethtools_get_regs_len(struct net_device *ndev)
1103 {
1104         return sizeof(u32) * AXIENET_REGS_N;
1105 }
1106 
1107 /**
1108  * axienet_ethtools_get_regs - Dump the contents of all registers present
1109  *                             in AxiEthernet core.
1110  * @ndev:       Pointer to net_device structure
1111  * @regs:       Pointer to ethtool_regs structure
1112  * @ret:        Void pointer used to return the contents of the registers.
1113  *
1114  * This implements ethtool command for getting the Axi Ethernet register dump.
1115  * Issue "ethtool -d ethX" to execute this function.
1116  */
1117 static void axienet_ethtools_get_regs(struct net_device *ndev,
1118                                       struct ethtool_regs *regs, void *ret)
1119 {
1120         u32 *data = (u32 *) ret;
1121         size_t len = sizeof(u32) * AXIENET_REGS_N;
1122         struct axienet_local *lp = netdev_priv(ndev);
1123 
1124         regs->version = 0;
1125         regs->len = len;
1126 
1127         memset(data, 0, len);
1128         data[0] = axienet_ior(lp, XAE_RAF_OFFSET);
1129         data[1] = axienet_ior(lp, XAE_TPF_OFFSET);
1130         data[2] = axienet_ior(lp, XAE_IFGP_OFFSET);
1131         data[3] = axienet_ior(lp, XAE_IS_OFFSET);
1132         data[4] = axienet_ior(lp, XAE_IP_OFFSET);
1133         data[5] = axienet_ior(lp, XAE_IE_OFFSET);
1134         data[6] = axienet_ior(lp, XAE_TTAG_OFFSET);
1135         data[7] = axienet_ior(lp, XAE_RTAG_OFFSET);
1136         data[8] = axienet_ior(lp, XAE_UAWL_OFFSET);
1137         data[9] = axienet_ior(lp, XAE_UAWU_OFFSET);
1138         data[10] = axienet_ior(lp, XAE_TPID0_OFFSET);
1139         data[11] = axienet_ior(lp, XAE_TPID1_OFFSET);
1140         data[12] = axienet_ior(lp, XAE_PPST_OFFSET);
1141         data[13] = axienet_ior(lp, XAE_RCW0_OFFSET);
1142         data[14] = axienet_ior(lp, XAE_RCW1_OFFSET);
1143         data[15] = axienet_ior(lp, XAE_TC_OFFSET);
1144         data[16] = axienet_ior(lp, XAE_FCC_OFFSET);
1145         data[17] = axienet_ior(lp, XAE_EMMC_OFFSET);
1146         data[18] = axienet_ior(lp, XAE_PHYC_OFFSET);
1147         data[19] = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
1148         data[20] = axienet_ior(lp, XAE_MDIO_MCR_OFFSET);
1149         data[21] = axienet_ior(lp, XAE_MDIO_MWD_OFFSET);
1150         data[22] = axienet_ior(lp, XAE_MDIO_MRD_OFFSET);
1151         data[23] = axienet_ior(lp, XAE_MDIO_MIS_OFFSET);
1152         data[24] = axienet_ior(lp, XAE_MDIO_MIP_OFFSET);
1153         data[25] = axienet_ior(lp, XAE_MDIO_MIE_OFFSET);
1154         data[26] = axienet_ior(lp, XAE_MDIO_MIC_OFFSET);
1155         data[27] = axienet_ior(lp, XAE_UAW0_OFFSET);
1156         data[28] = axienet_ior(lp, XAE_UAW1_OFFSET);
1157         data[29] = axienet_ior(lp, XAE_FMI_OFFSET);
1158         data[30] = axienet_ior(lp, XAE_AF0_OFFSET);
1159         data[31] = axienet_ior(lp, XAE_AF1_OFFSET);
1160 }
1161 
1162 /**
1163  * axienet_ethtools_get_pauseparam - Get the pause parameter setting for
1164  *                                   Tx and Rx paths.
1165  * @ndev:       Pointer to net_device structure
1166  * @epauseparm: Pointer to ethtool_pauseparam structure.
1167  *
1168  * This implements ethtool command for getting axi ethernet pause frame
1169  * setting. Issue "ethtool -a ethX" to execute this function.
1170  */
1171 static void
1172 axienet_ethtools_get_pauseparam(struct net_device *ndev,
1173                                 struct ethtool_pauseparam *epauseparm)
1174 {
1175         u32 regval;
1176         struct axienet_local *lp = netdev_priv(ndev);
1177         epauseparm->autoneg  = 0;
1178         regval = axienet_ior(lp, XAE_FCC_OFFSET);
1179         epauseparm->tx_pause = regval & XAE_FCC_FCTX_MASK;
1180         epauseparm->rx_pause = regval & XAE_FCC_FCRX_MASK;
1181 }
1182 
1183 /**
1184  * axienet_ethtools_set_pauseparam - Set device pause parameter(flow control)
1185  *                                   settings.
1186  * @ndev:       Pointer to net_device structure
1187  * @epauseparm:Pointer to ethtool_pauseparam structure
1188  *
1189  * This implements ethtool command for enabling flow control on Rx and Tx
1190  * paths. Issue "ethtool -A ethX tx on|off" under linux prompt to execute this
1191  * function.
1192  *
1193  * Return: 0 on success, -EFAULT if device is running
1194  */
1195 static int
1196 axienet_ethtools_set_pauseparam(struct net_device *ndev,
1197                                 struct ethtool_pauseparam *epauseparm)
1198 {
1199         u32 regval = 0;
1200         struct axienet_local *lp = netdev_priv(ndev);
1201 
1202         if (netif_running(ndev)) {
1203                 netdev_err(ndev,
1204                            "Please stop netif before applying configuration\n");
1205                 return -EFAULT;
1206         }
1207 
1208         regval = axienet_ior(lp, XAE_FCC_OFFSET);
1209         if (epauseparm->tx_pause)
1210                 regval |= XAE_FCC_FCTX_MASK;
1211         else
1212                 regval &= ~XAE_FCC_FCTX_MASK;
1213         if (epauseparm->rx_pause)
1214                 regval |= XAE_FCC_FCRX_MASK;
1215         else
1216                 regval &= ~XAE_FCC_FCRX_MASK;
1217         axienet_iow(lp, XAE_FCC_OFFSET, regval);
1218 
1219         return 0;
1220 }
1221 
1222 /**
1223  * axienet_ethtools_get_coalesce - Get DMA interrupt coalescing count.
1224  * @ndev:       Pointer to net_device structure
1225  * @ecoalesce:  Pointer to ethtool_coalesce structure
1226  *
1227  * This implements ethtool command for getting the DMA interrupt coalescing
1228  * count on Tx and Rx paths. Issue "ethtool -c ethX" under linux prompt to
1229  * execute this function.
1230  *
1231  * Return: 0 always
1232  */
1233 static int axienet_ethtools_get_coalesce(struct net_device *ndev,
1234                                          struct ethtool_coalesce *ecoalesce)
1235 {
1236         u32 regval = 0;
1237         struct axienet_local *lp = netdev_priv(ndev);
1238         regval = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1239         ecoalesce->rx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)
1240                                              >> XAXIDMA_COALESCE_SHIFT;
1241         regval = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1242         ecoalesce->tx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)
1243                                              >> XAXIDMA_COALESCE_SHIFT;
1244         return 0;
1245 }
1246 
1247 /**
1248  * axienet_ethtools_set_coalesce - Set DMA interrupt coalescing count.
1249  * @ndev:       Pointer to net_device structure
1250  * @ecoalesce:  Pointer to ethtool_coalesce structure
1251  *
1252  * This implements ethtool command for setting the DMA interrupt coalescing
1253  * count on Tx and Rx paths. Issue "ethtool -C ethX rx-frames 5" under linux
1254  * prompt to execute this function.
1255  *
1256  * Return: 0, on success, Non-zero error value on failure.
1257  */
1258 static int axienet_ethtools_set_coalesce(struct net_device *ndev,
1259                                          struct ethtool_coalesce *ecoalesce)
1260 {
1261         struct axienet_local *lp = netdev_priv(ndev);
1262 
1263         if (netif_running(ndev)) {
1264                 netdev_err(ndev,
1265                            "Please stop netif before applying configuration\n");
1266                 return -EFAULT;
1267         }
1268 
1269         if ((ecoalesce->rx_coalesce_usecs) ||
1270             (ecoalesce->rx_coalesce_usecs_irq) ||
1271             (ecoalesce->rx_max_coalesced_frames_irq) ||
1272             (ecoalesce->tx_coalesce_usecs) ||
1273             (ecoalesce->tx_coalesce_usecs_irq) ||
1274             (ecoalesce->tx_max_coalesced_frames_irq) ||
1275             (ecoalesce->stats_block_coalesce_usecs) ||
1276             (ecoalesce->use_adaptive_rx_coalesce) ||
1277             (ecoalesce->use_adaptive_tx_coalesce) ||
1278             (ecoalesce->pkt_rate_low) ||
1279             (ecoalesce->rx_coalesce_usecs_low) ||
1280             (ecoalesce->rx_max_coalesced_frames_low) ||
1281             (ecoalesce->tx_coalesce_usecs_low) ||
1282             (ecoalesce->tx_max_coalesced_frames_low) ||
1283             (ecoalesce->pkt_rate_high) ||
1284             (ecoalesce->rx_coalesce_usecs_high) ||
1285             (ecoalesce->rx_max_coalesced_frames_high) ||
1286             (ecoalesce->tx_coalesce_usecs_high) ||
1287             (ecoalesce->tx_max_coalesced_frames_high) ||
1288             (ecoalesce->rate_sample_interval))
1289                 return -EOPNOTSUPP;
1290         if (ecoalesce->rx_max_coalesced_frames)
1291                 lp->coalesce_count_rx = ecoalesce->rx_max_coalesced_frames;
1292         if (ecoalesce->tx_max_coalesced_frames)
1293                 lp->coalesce_count_tx = ecoalesce->tx_max_coalesced_frames;
1294 
1295         return 0;
1296 }
1297 
1298 static const struct ethtool_ops axienet_ethtool_ops = {
1299         .get_drvinfo    = axienet_ethtools_get_drvinfo,
1300         .get_regs_len   = axienet_ethtools_get_regs_len,
1301         .get_regs       = axienet_ethtools_get_regs,
1302         .get_link       = ethtool_op_get_link,
1303         .get_pauseparam = axienet_ethtools_get_pauseparam,
1304         .set_pauseparam = axienet_ethtools_set_pauseparam,
1305         .get_coalesce   = axienet_ethtools_get_coalesce,
1306         .set_coalesce   = axienet_ethtools_set_coalesce,
1307         .get_link_ksettings = phy_ethtool_get_link_ksettings,
1308         .set_link_ksettings = phy_ethtool_set_link_ksettings,
1309 };
1310 
1311 /**
1312  * axienet_dma_err_handler - Tasklet handler for Axi DMA Error
1313  * @data:       Data passed
1314  *
1315  * Resets the Axi DMA and Axi Ethernet devices, and reconfigures the
1316  * Tx/Rx BDs.
1317  */
1318 static void axienet_dma_err_handler(unsigned long data)
1319 {
1320         u32 axienet_status;
1321         u32 cr, i;
1322         int mdio_mcreg;
1323         struct axienet_local *lp = (struct axienet_local *) data;
1324         struct net_device *ndev = lp->ndev;
1325         struct axidma_bd *cur_p;
1326 
1327         axienet_setoptions(ndev, lp->options &
1328                            ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1329         mdio_mcreg = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
1330         axienet_mdio_wait_until_ready(lp);
1331         /* Disable the MDIO interface till Axi Ethernet Reset is completed.
1332          * When we do an Axi Ethernet reset, it resets the complete core
1333          * including the MDIO. So if MDIO is not disabled when the reset
1334          * process is started, MDIO will be broken afterwards.
1335          */
1336         axienet_iow(lp, XAE_MDIO_MC_OFFSET, (mdio_mcreg &
1337                     ~XAE_MDIO_MC_MDIOEN_MASK));
1338 
1339         __axienet_device_reset(lp, XAXIDMA_TX_CR_OFFSET);
1340         __axienet_device_reset(lp, XAXIDMA_RX_CR_OFFSET);
1341 
1342         axienet_iow(lp, XAE_MDIO_MC_OFFSET, mdio_mcreg);
1343         axienet_mdio_wait_until_ready(lp);
1344 
1345         for (i = 0; i < TX_BD_NUM; i++) {
1346                 cur_p = &lp->tx_bd_v[i];
1347                 if (cur_p->phys)
1348                         dma_unmap_single(ndev->dev.parent, cur_p->phys,
1349                                          (cur_p->cntrl &
1350                                           XAXIDMA_BD_CTRL_LENGTH_MASK),
1351                                          DMA_TO_DEVICE);
1352                 if (cur_p->app4)
1353                         dev_kfree_skb_irq((struct sk_buff *) cur_p->app4);
1354                 cur_p->phys = 0;
1355                 cur_p->cntrl = 0;
1356                 cur_p->status = 0;
1357                 cur_p->app0 = 0;
1358                 cur_p->app1 = 0;
1359                 cur_p->app2 = 0;
1360                 cur_p->app3 = 0;
1361                 cur_p->app4 = 0;
1362                 cur_p->sw_id_offset = 0;
1363         }
1364 
1365         for (i = 0; i < RX_BD_NUM; i++) {
1366                 cur_p = &lp->rx_bd_v[i];
1367                 cur_p->status = 0;
1368                 cur_p->app0 = 0;
1369                 cur_p->app1 = 0;
1370                 cur_p->app2 = 0;
1371                 cur_p->app3 = 0;
1372                 cur_p->app4 = 0;
1373         }
1374 
1375         lp->tx_bd_ci = 0;
1376         lp->tx_bd_tail = 0;
1377         lp->rx_bd_ci = 0;
1378 
1379         /* Start updating the Rx channel control register */
1380         cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1381         /* Update the interrupt coalesce count */
1382         cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
1383               (XAXIDMA_DFT_RX_THRESHOLD << XAXIDMA_COALESCE_SHIFT));
1384         /* Update the delay timer count */
1385         cr = ((cr & ~XAXIDMA_DELAY_MASK) |
1386               (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
1387         /* Enable coalesce, delay timer and error interrupts */
1388         cr |= XAXIDMA_IRQ_ALL_MASK;
1389         /* Finally write to the Rx channel control register */
1390         axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
1391 
1392         /* Start updating the Tx channel control register */
1393         cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1394         /* Update the interrupt coalesce count */
1395         cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
1396               (XAXIDMA_DFT_TX_THRESHOLD << XAXIDMA_COALESCE_SHIFT));
1397         /* Update the delay timer count */
1398         cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
1399               (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
1400         /* Enable coalesce, delay timer and error interrupts */
1401         cr |= XAXIDMA_IRQ_ALL_MASK;
1402         /* Finally write to the Tx channel control register */
1403         axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
1404 
1405         /* Populate the tail pointer and bring the Rx Axi DMA engine out of
1406          * halted state. This will make the Rx side ready for reception.
1407          */
1408         axienet_dma_out32(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
1409         cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1410         axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
1411                           cr | XAXIDMA_CR_RUNSTOP_MASK);
1412         axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
1413                           (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
1414 
1415         /* Write to the RS (Run-stop) bit in the Tx channel control register.
1416          * Tx channel is now ready to run. But only after we write to the
1417          * tail pointer register that the Tx channel will start transmitting
1418          */
1419         axienet_dma_out32(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
1420         cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1421         axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
1422                           cr | XAXIDMA_CR_RUNSTOP_MASK);
1423 
1424         axienet_status = axienet_ior(lp, XAE_RCW1_OFFSET);
1425         axienet_status &= ~XAE_RCW1_RX_MASK;
1426         axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status);
1427 
1428         axienet_status = axienet_ior(lp, XAE_IP_OFFSET);
1429         if (axienet_status & XAE_INT_RXRJECT_MASK)
1430                 axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK);
1431         axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);
1432 
1433         /* Sync default options with HW but leave receiver and
1434          * transmitter disabled.
1435          */
1436         axienet_setoptions(ndev, lp->options &
1437                            ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1438         axienet_set_mac_address(ndev, NULL);
1439         axienet_set_multicast_list(ndev);
1440         axienet_setoptions(ndev, lp->options);
1441 }
1442 
1443 /**
1444  * axienet_probe - Axi Ethernet probe function.
1445  * @pdev:       Pointer to platform device structure.
1446  *
1447  * Return: 0, on success
1448  *          Non-zero error value on failure.
1449  *
1450  * This is the probe routine for Axi Ethernet driver. This is called before
1451  * any other driver routines are invoked. It allocates and sets up the Ethernet
1452  * device. Parses through device tree and populates fields of
1453  * axienet_local. It registers the Ethernet device.
1454  */
1455 static int axienet_probe(struct platform_device *pdev)
1456 {
1457         int ret;
1458         struct device_node *np;
1459         struct axienet_local *lp;
1460         struct net_device *ndev;
1461         const void *mac_addr;
1462         struct resource *ethres, dmares;
1463         u32 value;
1464 
1465         ndev = alloc_etherdev(sizeof(*lp));
1466         if (!ndev)
1467                 return -ENOMEM;
1468 
1469         platform_set_drvdata(pdev, ndev);
1470 
1471         SET_NETDEV_DEV(ndev, &pdev->dev);
1472         ndev->flags &= ~IFF_MULTICAST;  /* clear multicast */
1473         ndev->features = NETIF_F_SG;
1474         ndev->netdev_ops = &axienet_netdev_ops;
1475         ndev->ethtool_ops = &axienet_ethtool_ops;
1476 
1477         /* MTU range: 64 - 9000 */
1478         ndev->min_mtu = 64;
1479         ndev->max_mtu = XAE_JUMBO_MTU;
1480 
1481         lp = netdev_priv(ndev);
1482         lp->ndev = ndev;
1483         lp->dev = &pdev->dev;
1484         lp->options = XAE_OPTION_DEFAULTS;
1485         /* Map device registers */
1486         ethres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1487         lp->regs = devm_ioremap_resource(&pdev->dev, ethres);
1488         if (IS_ERR(lp->regs)) {
1489                 dev_err(&pdev->dev, "could not map Axi Ethernet regs.\n");
1490                 ret = PTR_ERR(lp->regs);
1491                 goto free_netdev;
1492         }
1493 
1494         /* Setup checksum offload, but default to off if not specified */
1495         lp->features = 0;
1496 
1497         ret = of_property_read_u32(pdev->dev.of_node, "xlnx,txcsum", &value);
1498         if (!ret) {
1499                 switch (value) {
1500                 case 1:
1501                         lp->csum_offload_on_tx_path =
1502                                 XAE_FEATURE_PARTIAL_TX_CSUM;
1503                         lp->features |= XAE_FEATURE_PARTIAL_TX_CSUM;
1504                         /* Can checksum TCP/UDP over IPv4. */
1505                         ndev->features |= NETIF_F_IP_CSUM;
1506                         break;
1507                 case 2:
1508                         lp->csum_offload_on_tx_path =
1509                                 XAE_FEATURE_FULL_TX_CSUM;
1510                         lp->features |= XAE_FEATURE_FULL_TX_CSUM;
1511                         /* Can checksum TCP/UDP over IPv4. */
1512                         ndev->features |= NETIF_F_IP_CSUM;
1513                         break;
1514                 default:
1515                         lp->csum_offload_on_tx_path = XAE_NO_CSUM_OFFLOAD;
1516                 }
1517         }
1518         ret = of_property_read_u32(pdev->dev.of_node, "xlnx,rxcsum", &value);
1519         if (!ret) {
1520                 switch (value) {
1521                 case 1:
1522                         lp->csum_offload_on_rx_path =
1523                                 XAE_FEATURE_PARTIAL_RX_CSUM;
1524                         lp->features |= XAE_FEATURE_PARTIAL_RX_CSUM;
1525                         break;
1526                 case 2:
1527                         lp->csum_offload_on_rx_path =
1528                                 XAE_FEATURE_FULL_RX_CSUM;
1529                         lp->features |= XAE_FEATURE_FULL_RX_CSUM;
1530                         break;
1531                 default:
1532                         lp->csum_offload_on_rx_path = XAE_NO_CSUM_OFFLOAD;
1533                 }
1534         }
1535         /* For supporting jumbo frames, the Axi Ethernet hardware must have
1536          * a larger Rx/Tx Memory. Typically, the size must be large so that
1537          * we can enable jumbo option and start supporting jumbo frames.
1538          * Here we check for memory allocated for Rx/Tx in the hardware from
1539          * the device-tree and accordingly set flags.
1540          */
1541         of_property_read_u32(pdev->dev.of_node, "xlnx,rxmem", &lp->rxmem);
1542         of_property_read_u32(pdev->dev.of_node, "xlnx,phy-type", &lp->phy_type);
1543 
1544         /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
1545         np = of_parse_phandle(pdev->dev.of_node, "axistream-connected", 0);
1546         if (!np) {
1547                 dev_err(&pdev->dev, "could not find DMA node\n");
1548                 ret = -ENODEV;
1549                 goto free_netdev;
1550         }
1551         ret = of_address_to_resource(np, 0, &dmares);
1552         if (ret) {
1553                 dev_err(&pdev->dev, "unable to get DMA resource\n");
1554                 goto free_netdev;
1555         }
1556         lp->dma_regs = devm_ioremap_resource(&pdev->dev, &dmares);
1557         if (IS_ERR(lp->dma_regs)) {
1558                 dev_err(&pdev->dev, "could not map DMA regs\n");
1559                 ret = PTR_ERR(lp->dma_regs);
1560                 goto free_netdev;
1561         }
1562         lp->rx_irq = irq_of_parse_and_map(np, 1);
1563         lp->tx_irq = irq_of_parse_and_map(np, 0);
1564         of_node_put(np);
1565         if ((lp->rx_irq <= 0) || (lp->tx_irq <= 0)) {
1566                 dev_err(&pdev->dev, "could not determine irqs\n");
1567                 ret = -ENOMEM;
1568                 goto free_netdev;
1569         }
1570 
1571         /* Retrieve the MAC address */
1572         mac_addr = of_get_mac_address(pdev->dev.of_node);
1573         if (!mac_addr) {
1574                 dev_err(&pdev->dev, "could not find MAC address\n");
1575                 goto free_netdev;
1576         }
1577         axienet_set_mac_address(ndev, mac_addr);
1578 
1579         lp->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD;
1580         lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
1581 
1582         lp->phy_node = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
1583         if (lp->phy_node) {
1584                 ret = axienet_mdio_setup(lp, pdev->dev.of_node);
1585                 if (ret)
1586                         dev_warn(&pdev->dev, "error registering MDIO bus\n");
1587         }
1588 
1589         ret = register_netdev(lp->ndev);
1590         if (ret) {
1591                 dev_err(lp->dev, "register_netdev() error (%i)\n", ret);
1592                 goto free_netdev;
1593         }
1594 
1595         return 0;
1596 
1597 free_netdev:
1598         free_netdev(ndev);
1599 
1600         return ret;
1601 }
1602 
1603 static int axienet_remove(struct platform_device *pdev)
1604 {
1605         struct net_device *ndev = platform_get_drvdata(pdev);
1606         struct axienet_local *lp = netdev_priv(ndev);
1607 
1608         axienet_mdio_teardown(lp);
1609         unregister_netdev(ndev);
1610 
1611         of_node_put(lp->phy_node);
1612         lp->phy_node = NULL;
1613 
1614         free_netdev(ndev);
1615 
1616         return 0;
1617 }
1618 
1619 static struct platform_driver axienet_driver = {
1620         .probe = axienet_probe,
1621         .remove = axienet_remove,
1622         .driver = {
1623                  .name = "xilinx_axienet",
1624                  .of_match_table = axienet_of_match,
1625         },
1626 };
1627 
1628 module_platform_driver(axienet_driver);
1629 
1630 MODULE_DESCRIPTION("Xilinx Axi Ethernet driver");
1631 MODULE_AUTHOR("Xilinx");
1632 MODULE_LICENSE("GPL");
1633 

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