Version:  2.0.40 2.2.26 2.4.37 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1

Linux/drivers/net/ethernet/xilinx/ll_temac_main.c

  1 /*
  2  * Driver for Xilinx TEMAC Ethernet device
  3  *
  4  * Copyright (c) 2008 Nissin Systems Co., Ltd.,  Yoshio Kashiwagi
  5  * Copyright (c) 2005-2008 DLA Systems,  David H. Lynch Jr. <dhlii@dlasys.net>
  6  * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
  7  *
  8  * This is a driver for the Xilinx ll_temac ipcore which is often used
  9  * in the Virtex and Spartan series of chips.
 10  *
 11  * Notes:
 12  * - The ll_temac hardware uses indirect access for many of the TEMAC
 13  *   registers, include the MDIO bus.  However, indirect access to MDIO
 14  *   registers take considerably more clock cycles than to TEMAC registers.
 15  *   MDIO accesses are long, so threads doing them should probably sleep
 16  *   rather than busywait.  However, since only one indirect access can be
 17  *   in progress at any given time, that means that *all* indirect accesses
 18  *   could end up sleeping (to wait for an MDIO access to complete).
 19  *   Fortunately none of the indirect accesses are on the 'hot' path for tx
 20  *   or rx, so this should be okay.
 21  *
 22  * TODO:
 23  * - Factor out locallink DMA code into separate driver
 24  * - Fix multicast assignment.
 25  * - Fix support for hardware checksumming.
 26  * - Testing.  Lots and lots of testing.
 27  *
 28  */
 29 
 30 #include <linux/delay.h>
 31 #include <linux/etherdevice.h>
 32 #include <linux/mii.h>
 33 #include <linux/module.h>
 34 #include <linux/mutex.h>
 35 #include <linux/netdevice.h>
 36 #include <linux/of.h>
 37 #include <linux/of_device.h>
 38 #include <linux/of_irq.h>
 39 #include <linux/of_mdio.h>
 40 #include <linux/of_platform.h>
 41 #include <linux/of_address.h>
 42 #include <linux/skbuff.h>
 43 #include <linux/spinlock.h>
 44 #include <linux/tcp.h>      /* needed for sizeof(tcphdr) */
 45 #include <linux/udp.h>      /* needed for sizeof(udphdr) */
 46 #include <linux/phy.h>
 47 #include <linux/in.h>
 48 #include <linux/io.h>
 49 #include <linux/ip.h>
 50 #include <linux/slab.h>
 51 #include <linux/interrupt.h>
 52 #include <linux/dma-mapping.h>
 53 
 54 #include "ll_temac.h"
 55 
 56 #define TX_BD_NUM   64
 57 #define RX_BD_NUM   128
 58 
 59 /* ---------------------------------------------------------------------
 60  * Low level register access functions
 61  */
 62 
 63 u32 temac_ior(struct temac_local *lp, int offset)
 64 {
 65         return in_be32((u32 *)(lp->regs + offset));
 66 }
 67 
 68 void temac_iow(struct temac_local *lp, int offset, u32 value)
 69 {
 70         out_be32((u32 *) (lp->regs + offset), value);
 71 }
 72 
 73 int temac_indirect_busywait(struct temac_local *lp)
 74 {
 75         unsigned long end = jiffies + 2;
 76 
 77         while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) {
 78                 if (time_before_eq(end, jiffies)) {
 79                         WARN_ON(1);
 80                         return -ETIMEDOUT;
 81                 }
 82                 msleep(1);
 83         }
 84         return 0;
 85 }
 86 
 87 /**
 88  * temac_indirect_in32
 89  *
 90  * lp->indirect_mutex must be held when calling this function
 91  */
 92 u32 temac_indirect_in32(struct temac_local *lp, int reg)
 93 {
 94         u32 val;
 95 
 96         if (temac_indirect_busywait(lp))
 97                 return -ETIMEDOUT;
 98         temac_iow(lp, XTE_CTL0_OFFSET, reg);
 99         if (temac_indirect_busywait(lp))
100                 return -ETIMEDOUT;
101         val = temac_ior(lp, XTE_LSW0_OFFSET);
102 
103         return val;
104 }
105 
106 /**
107  * temac_indirect_out32
108  *
109  * lp->indirect_mutex must be held when calling this function
110  */
111 void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
112 {
113         if (temac_indirect_busywait(lp))
114                 return;
115         temac_iow(lp, XTE_LSW0_OFFSET, value);
116         temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
117         temac_indirect_busywait(lp);
118 }
119 
120 /**
121  * temac_dma_in32 - Memory mapped DMA read, this function expects a
122  * register input that is based on DCR word addresses which
123  * are then converted to memory mapped byte addresses
124  */
125 static u32 temac_dma_in32(struct temac_local *lp, int reg)
126 {
127         return in_be32((u32 *)(lp->sdma_regs + (reg << 2)));
128 }
129 
130 /**
131  * temac_dma_out32 - Memory mapped DMA read, this function expects a
132  * register input that is based on DCR word addresses which
133  * are then converted to memory mapped byte addresses
134  */
135 static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
136 {
137         out_be32((u32 *)(lp->sdma_regs + (reg << 2)), value);
138 }
139 
140 /* DMA register access functions can be DCR based or memory mapped.
141  * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
142  * memory mapped.
143  */
144 #ifdef CONFIG_PPC_DCR
145 
146 /**
147  * temac_dma_dcr_in32 - DCR based DMA read
148  */
149 static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
150 {
151         return dcr_read(lp->sdma_dcrs, reg);
152 }
153 
154 /**
155  * temac_dma_dcr_out32 - DCR based DMA write
156  */
157 static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
158 {
159         dcr_write(lp->sdma_dcrs, reg, value);
160 }
161 
162 /**
163  * temac_dcr_setup - If the DMA is DCR based, then setup the address and
164  * I/O  functions
165  */
166 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
167                                 struct device_node *np)
168 {
169         unsigned int dcrs;
170 
171         /* setup the dcr address mapping if it's in the device tree */
172 
173         dcrs = dcr_resource_start(np, 0);
174         if (dcrs != 0) {
175                 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
176                 lp->dma_in = temac_dma_dcr_in;
177                 lp->dma_out = temac_dma_dcr_out;
178                 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
179                 return 0;
180         }
181         /* no DCR in the device tree, indicate a failure */
182         return -1;
183 }
184 
185 #else
186 
187 /*
188  * temac_dcr_setup - This is a stub for when DCR is not supported,
189  * such as with MicroBlaze
190  */
191 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
192                                 struct device_node *np)
193 {
194         return -1;
195 }
196 
197 #endif
198 
199 /**
200  * temac_dma_bd_release - Release buffer descriptor rings
201  */
202 static void temac_dma_bd_release(struct net_device *ndev)
203 {
204         struct temac_local *lp = netdev_priv(ndev);
205         int i;
206 
207         /* Reset Local Link (DMA) */
208         lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
209 
210         for (i = 0; i < RX_BD_NUM; i++) {
211                 if (!lp->rx_skb[i])
212                         break;
213                 else {
214                         dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
215                                         XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
216                         dev_kfree_skb(lp->rx_skb[i]);
217                 }
218         }
219         if (lp->rx_bd_v)
220                 dma_free_coherent(ndev->dev.parent,
221                                 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
222                                 lp->rx_bd_v, lp->rx_bd_p);
223         if (lp->tx_bd_v)
224                 dma_free_coherent(ndev->dev.parent,
225                                 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
226                                 lp->tx_bd_v, lp->tx_bd_p);
227         kfree(lp->rx_skb);
228 }
229 
230 /**
231  * temac_dma_bd_init - Setup buffer descriptor rings
232  */
233 static int temac_dma_bd_init(struct net_device *ndev)
234 {
235         struct temac_local *lp = netdev_priv(ndev);
236         struct sk_buff *skb;
237         int i;
238 
239         lp->rx_skb = kcalloc(RX_BD_NUM, sizeof(*lp->rx_skb), GFP_KERNEL);
240         if (!lp->rx_skb)
241                 goto out;
242 
243         /* allocate the tx and rx ring buffer descriptors. */
244         /* returns a virtual address and a physical address. */
245         lp->tx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
246                                           sizeof(*lp->tx_bd_v) * TX_BD_NUM,
247                                           &lp->tx_bd_p, GFP_KERNEL);
248         if (!lp->tx_bd_v)
249                 goto out;
250 
251         lp->rx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
252                                           sizeof(*lp->rx_bd_v) * RX_BD_NUM,
253                                           &lp->rx_bd_p, GFP_KERNEL);
254         if (!lp->rx_bd_v)
255                 goto out;
256 
257         for (i = 0; i < TX_BD_NUM; i++) {
258                 lp->tx_bd_v[i].next = lp->tx_bd_p +
259                                 sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM);
260         }
261 
262         for (i = 0; i < RX_BD_NUM; i++) {
263                 lp->rx_bd_v[i].next = lp->rx_bd_p +
264                                 sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM);
265 
266                 skb = netdev_alloc_skb_ip_align(ndev,
267                                                 XTE_MAX_JUMBO_FRAME_SIZE);
268                 if (!skb)
269                         goto out;
270 
271                 lp->rx_skb[i] = skb;
272                 /* returns physical address of skb->data */
273                 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
274                                                      skb->data,
275                                                      XTE_MAX_JUMBO_FRAME_SIZE,
276                                                      DMA_FROM_DEVICE);
277                 lp->rx_bd_v[i].len = XTE_MAX_JUMBO_FRAME_SIZE;
278                 lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND;
279         }
280 
281         lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 |
282                                           CHNL_CTRL_IRQ_EN |
283                                           CHNL_CTRL_IRQ_DLY_EN |
284                                           CHNL_CTRL_IRQ_COAL_EN);
285         /* 0x10220483 */
286         /* 0x00100483 */
287         lp->dma_out(lp, RX_CHNL_CTRL, 0xff070000 |
288                                           CHNL_CTRL_IRQ_EN |
289                                           CHNL_CTRL_IRQ_DLY_EN |
290                                           CHNL_CTRL_IRQ_COAL_EN |
291                                           CHNL_CTRL_IRQ_IOE);
292         /* 0xff010283 */
293 
294         lp->dma_out(lp, RX_CURDESC_PTR,  lp->rx_bd_p);
295         lp->dma_out(lp, RX_TAILDESC_PTR,
296                        lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
297         lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
298 
299         /* Init descriptor indexes */
300         lp->tx_bd_ci = 0;
301         lp->tx_bd_next = 0;
302         lp->tx_bd_tail = 0;
303         lp->rx_bd_ci = 0;
304 
305         return 0;
306 
307 out:
308         temac_dma_bd_release(ndev);
309         return -ENOMEM;
310 }
311 
312 /* ---------------------------------------------------------------------
313  * net_device_ops
314  */
315 
316 static void temac_do_set_mac_address(struct net_device *ndev)
317 {
318         struct temac_local *lp = netdev_priv(ndev);
319 
320         /* set up unicast MAC address filter set its mac address */
321         mutex_lock(&lp->indirect_mutex);
322         temac_indirect_out32(lp, XTE_UAW0_OFFSET,
323                              (ndev->dev_addr[0]) |
324                              (ndev->dev_addr[1] << 8) |
325                              (ndev->dev_addr[2] << 16) |
326                              (ndev->dev_addr[3] << 24));
327         /* There are reserved bits in EUAW1
328          * so don't affect them Set MAC bits [47:32] in EUAW1 */
329         temac_indirect_out32(lp, XTE_UAW1_OFFSET,
330                              (ndev->dev_addr[4] & 0x000000ff) |
331                              (ndev->dev_addr[5] << 8));
332         mutex_unlock(&lp->indirect_mutex);
333 }
334 
335 static int temac_init_mac_address(struct net_device *ndev, void *address)
336 {
337         memcpy(ndev->dev_addr, address, ETH_ALEN);
338         if (!is_valid_ether_addr(ndev->dev_addr))
339                 eth_hw_addr_random(ndev);
340         temac_do_set_mac_address(ndev);
341         return 0;
342 }
343 
344 static int temac_set_mac_address(struct net_device *ndev, void *p)
345 {
346         struct sockaddr *addr = p;
347 
348         if (!is_valid_ether_addr(addr->sa_data))
349                 return -EADDRNOTAVAIL;
350         memcpy(ndev->dev_addr, addr->sa_data, ETH_ALEN);
351         temac_do_set_mac_address(ndev);
352         return 0;
353 }
354 
355 static void temac_set_multicast_list(struct net_device *ndev)
356 {
357         struct temac_local *lp = netdev_priv(ndev);
358         u32 multi_addr_msw, multi_addr_lsw, val;
359         int i;
360 
361         mutex_lock(&lp->indirect_mutex);
362         if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
363             netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) {
364                 /*
365                  *      We must make the kernel realise we had to move
366                  *      into promisc mode or we start all out war on
367                  *      the cable. If it was a promisc request the
368                  *      flag is already set. If not we assert it.
369                  */
370                 ndev->flags |= IFF_PROMISC;
371                 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
372                 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
373         } else if (!netdev_mc_empty(ndev)) {
374                 struct netdev_hw_addr *ha;
375 
376                 i = 0;
377                 netdev_for_each_mc_addr(ha, ndev) {
378                         if (i >= MULTICAST_CAM_TABLE_NUM)
379                                 break;
380                         multi_addr_msw = ((ha->addr[3] << 24) |
381                                           (ha->addr[2] << 16) |
382                                           (ha->addr[1] << 8) |
383                                           (ha->addr[0]));
384                         temac_indirect_out32(lp, XTE_MAW0_OFFSET,
385                                              multi_addr_msw);
386                         multi_addr_lsw = ((ha->addr[5] << 8) |
387                                           (ha->addr[4]) | (i << 16));
388                         temac_indirect_out32(lp, XTE_MAW1_OFFSET,
389                                              multi_addr_lsw);
390                         i++;
391                 }
392         } else {
393                 val = temac_indirect_in32(lp, XTE_AFM_OFFSET);
394                 temac_indirect_out32(lp, XTE_AFM_OFFSET,
395                                      val & ~XTE_AFM_EPPRM_MASK);
396                 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0);
397                 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0);
398                 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
399         }
400         mutex_unlock(&lp->indirect_mutex);
401 }
402 
403 struct temac_option {
404         int flg;
405         u32 opt;
406         u32 reg;
407         u32 m_or;
408         u32 m_and;
409 } temac_options[] = {
410         /* Turn on jumbo packet support for both Rx and Tx */
411         {
412                 .opt = XTE_OPTION_JUMBO,
413                 .reg = XTE_TXC_OFFSET,
414                 .m_or = XTE_TXC_TXJMBO_MASK,
415         },
416         {
417                 .opt = XTE_OPTION_JUMBO,
418                 .reg = XTE_RXC1_OFFSET,
419                 .m_or =XTE_RXC1_RXJMBO_MASK,
420         },
421         /* Turn on VLAN packet support for both Rx and Tx */
422         {
423                 .opt = XTE_OPTION_VLAN,
424                 .reg = XTE_TXC_OFFSET,
425                 .m_or =XTE_TXC_TXVLAN_MASK,
426         },
427         {
428                 .opt = XTE_OPTION_VLAN,
429                 .reg = XTE_RXC1_OFFSET,
430                 .m_or =XTE_RXC1_RXVLAN_MASK,
431         },
432         /* Turn on FCS stripping on receive packets */
433         {
434                 .opt = XTE_OPTION_FCS_STRIP,
435                 .reg = XTE_RXC1_OFFSET,
436                 .m_or =XTE_RXC1_RXFCS_MASK,
437         },
438         /* Turn on FCS insertion on transmit packets */
439         {
440                 .opt = XTE_OPTION_FCS_INSERT,
441                 .reg = XTE_TXC_OFFSET,
442                 .m_or =XTE_TXC_TXFCS_MASK,
443         },
444         /* Turn on length/type field checking on receive packets */
445         {
446                 .opt = XTE_OPTION_LENTYPE_ERR,
447                 .reg = XTE_RXC1_OFFSET,
448                 .m_or =XTE_RXC1_RXLT_MASK,
449         },
450         /* Turn on flow control */
451         {
452                 .opt = XTE_OPTION_FLOW_CONTROL,
453                 .reg = XTE_FCC_OFFSET,
454                 .m_or =XTE_FCC_RXFLO_MASK,
455         },
456         /* Turn on flow control */
457         {
458                 .opt = XTE_OPTION_FLOW_CONTROL,
459                 .reg = XTE_FCC_OFFSET,
460                 .m_or =XTE_FCC_TXFLO_MASK,
461         },
462         /* Turn on promiscuous frame filtering (all frames are received ) */
463         {
464                 .opt = XTE_OPTION_PROMISC,
465                 .reg = XTE_AFM_OFFSET,
466                 .m_or =XTE_AFM_EPPRM_MASK,
467         },
468         /* Enable transmitter if not already enabled */
469         {
470                 .opt = XTE_OPTION_TXEN,
471                 .reg = XTE_TXC_OFFSET,
472                 .m_or =XTE_TXC_TXEN_MASK,
473         },
474         /* Enable receiver? */
475         {
476                 .opt = XTE_OPTION_RXEN,
477                 .reg = XTE_RXC1_OFFSET,
478                 .m_or =XTE_RXC1_RXEN_MASK,
479         },
480         {}
481 };
482 
483 /**
484  * temac_setoptions
485  */
486 static u32 temac_setoptions(struct net_device *ndev, u32 options)
487 {
488         struct temac_local *lp = netdev_priv(ndev);
489         struct temac_option *tp = &temac_options[0];
490         int reg;
491 
492         mutex_lock(&lp->indirect_mutex);
493         while (tp->opt) {
494                 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or;
495                 if (options & tp->opt)
496                         reg |= tp->m_or;
497                 temac_indirect_out32(lp, tp->reg, reg);
498                 tp++;
499         }
500         lp->options |= options;
501         mutex_unlock(&lp->indirect_mutex);
502 
503         return 0;
504 }
505 
506 /* Initialize temac */
507 static void temac_device_reset(struct net_device *ndev)
508 {
509         struct temac_local *lp = netdev_priv(ndev);
510         u32 timeout;
511         u32 val;
512 
513         /* Perform a software reset */
514 
515         /* 0x300 host enable bit ? */
516         /* reset PHY through control register ?:1 */
517 
518         dev_dbg(&ndev->dev, "%s()\n", __func__);
519 
520         mutex_lock(&lp->indirect_mutex);
521         /* Reset the receiver and wait for it to finish reset */
522         temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
523         timeout = 1000;
524         while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
525                 udelay(1);
526                 if (--timeout == 0) {
527                         dev_err(&ndev->dev,
528                                 "temac_device_reset RX reset timeout!!\n");
529                         break;
530                 }
531         }
532 
533         /* Reset the transmitter and wait for it to finish reset */
534         temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
535         timeout = 1000;
536         while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
537                 udelay(1);
538                 if (--timeout == 0) {
539                         dev_err(&ndev->dev,
540                                 "temac_device_reset TX reset timeout!!\n");
541                         break;
542                 }
543         }
544 
545         /* Disable the receiver */
546         val = temac_indirect_in32(lp, XTE_RXC1_OFFSET);
547         temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK);
548 
549         /* Reset Local Link (DMA) */
550         lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
551         timeout = 1000;
552         while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
553                 udelay(1);
554                 if (--timeout == 0) {
555                         dev_err(&ndev->dev,
556                                 "temac_device_reset DMA reset timeout!!\n");
557                         break;
558                 }
559         }
560         lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
561 
562         if (temac_dma_bd_init(ndev)) {
563                 dev_err(&ndev->dev,
564                                 "temac_device_reset descriptor allocation failed\n");
565         }
566 
567         temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0);
568         temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0);
569         temac_indirect_out32(lp, XTE_TXC_OFFSET, 0);
570         temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
571 
572         mutex_unlock(&lp->indirect_mutex);
573 
574         /* Sync default options with HW
575          * but leave receiver and transmitter disabled.  */
576         temac_setoptions(ndev,
577                          lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
578 
579         temac_do_set_mac_address(ndev);
580 
581         /* Set address filter table */
582         temac_set_multicast_list(ndev);
583         if (temac_setoptions(ndev, lp->options))
584                 dev_err(&ndev->dev, "Error setting TEMAC options\n");
585 
586         /* Init Driver variable */
587         ndev->trans_start = jiffies; /* prevent tx timeout */
588 }
589 
590 void temac_adjust_link(struct net_device *ndev)
591 {
592         struct temac_local *lp = netdev_priv(ndev);
593         struct phy_device *phy = lp->phy_dev;
594         u32 mii_speed;
595         int link_state;
596 
597         /* hash together the state values to decide if something has changed */
598         link_state = phy->speed | (phy->duplex << 1) | phy->link;
599 
600         mutex_lock(&lp->indirect_mutex);
601         if (lp->last_link != link_state) {
602                 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET);
603                 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
604 
605                 switch (phy->speed) {
606                 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
607                 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
608                 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
609                 }
610 
611                 /* Write new speed setting out to TEMAC */
612                 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed);
613                 lp->last_link = link_state;
614                 phy_print_status(phy);
615         }
616         mutex_unlock(&lp->indirect_mutex);
617 }
618 
619 static void temac_start_xmit_done(struct net_device *ndev)
620 {
621         struct temac_local *lp = netdev_priv(ndev);
622         struct cdmac_bd *cur_p;
623         unsigned int stat = 0;
624 
625         cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
626         stat = cur_p->app0;
627 
628         while (stat & STS_CTRL_APP0_CMPLT) {
629                 dma_unmap_single(ndev->dev.parent, cur_p->phys, cur_p->len,
630                                  DMA_TO_DEVICE);
631                 if (cur_p->app4)
632                         dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
633                 cur_p->app0 = 0;
634                 cur_p->app1 = 0;
635                 cur_p->app2 = 0;
636                 cur_p->app3 = 0;
637                 cur_p->app4 = 0;
638 
639                 ndev->stats.tx_packets++;
640                 ndev->stats.tx_bytes += cur_p->len;
641 
642                 lp->tx_bd_ci++;
643                 if (lp->tx_bd_ci >= TX_BD_NUM)
644                         lp->tx_bd_ci = 0;
645 
646                 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
647                 stat = cur_p->app0;
648         }
649 
650         netif_wake_queue(ndev);
651 }
652 
653 static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag)
654 {
655         struct cdmac_bd *cur_p;
656         int tail;
657 
658         tail = lp->tx_bd_tail;
659         cur_p = &lp->tx_bd_v[tail];
660 
661         do {
662                 if (cur_p->app0)
663                         return NETDEV_TX_BUSY;
664 
665                 tail++;
666                 if (tail >= TX_BD_NUM)
667                         tail = 0;
668 
669                 cur_p = &lp->tx_bd_v[tail];
670                 num_frag--;
671         } while (num_frag >= 0);
672 
673         return 0;
674 }
675 
676 static int temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
677 {
678         struct temac_local *lp = netdev_priv(ndev);
679         struct cdmac_bd *cur_p;
680         dma_addr_t start_p, tail_p;
681         int ii;
682         unsigned long num_frag;
683         skb_frag_t *frag;
684 
685         num_frag = skb_shinfo(skb)->nr_frags;
686         frag = &skb_shinfo(skb)->frags[0];
687         start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
688         cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
689 
690         if (temac_check_tx_bd_space(lp, num_frag)) {
691                 if (!netif_queue_stopped(ndev)) {
692                         netif_stop_queue(ndev);
693                         return NETDEV_TX_BUSY;
694                 }
695                 return NETDEV_TX_BUSY;
696         }
697 
698         cur_p->app0 = 0;
699         if (skb->ip_summed == CHECKSUM_PARTIAL) {
700                 unsigned int csum_start_off = skb_checksum_start_offset(skb);
701                 unsigned int csum_index_off = csum_start_off + skb->csum_offset;
702 
703                 cur_p->app0 |= 1; /* TX Checksum Enabled */
704                 cur_p->app1 = (csum_start_off << 16) | csum_index_off;
705                 cur_p->app2 = 0;  /* initial checksum seed */
706         }
707 
708         cur_p->app0 |= STS_CTRL_APP0_SOP;
709         cur_p->len = skb_headlen(skb);
710         cur_p->phys = dma_map_single(ndev->dev.parent, skb->data,
711                                      skb_headlen(skb), DMA_TO_DEVICE);
712         cur_p->app4 = (unsigned long)skb;
713 
714         for (ii = 0; ii < num_frag; ii++) {
715                 lp->tx_bd_tail++;
716                 if (lp->tx_bd_tail >= TX_BD_NUM)
717                         lp->tx_bd_tail = 0;
718 
719                 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
720                 cur_p->phys = dma_map_single(ndev->dev.parent,
721                                              skb_frag_address(frag),
722                                              skb_frag_size(frag), DMA_TO_DEVICE);
723                 cur_p->len = skb_frag_size(frag);
724                 cur_p->app0 = 0;
725                 frag++;
726         }
727         cur_p->app0 |= STS_CTRL_APP0_EOP;
728 
729         tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
730         lp->tx_bd_tail++;
731         if (lp->tx_bd_tail >= TX_BD_NUM)
732                 lp->tx_bd_tail = 0;
733 
734         skb_tx_timestamp(skb);
735 
736         /* Kick off the transfer */
737         lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
738 
739         return NETDEV_TX_OK;
740 }
741 
742 
743 static void ll_temac_recv(struct net_device *ndev)
744 {
745         struct temac_local *lp = netdev_priv(ndev);
746         struct sk_buff *skb, *new_skb;
747         unsigned int bdstat;
748         struct cdmac_bd *cur_p;
749         dma_addr_t tail_p;
750         int length;
751         unsigned long flags;
752 
753         spin_lock_irqsave(&lp->rx_lock, flags);
754 
755         tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
756         cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
757 
758         bdstat = cur_p->app0;
759         while ((bdstat & STS_CTRL_APP0_CMPLT)) {
760 
761                 skb = lp->rx_skb[lp->rx_bd_ci];
762                 length = cur_p->app4 & 0x3FFF;
763 
764                 dma_unmap_single(ndev->dev.parent, cur_p->phys, length,
765                                  DMA_FROM_DEVICE);
766 
767                 skb_put(skb, length);
768                 skb->protocol = eth_type_trans(skb, ndev);
769                 skb_checksum_none_assert(skb);
770 
771                 /* if we're doing rx csum offload, set it up */
772                 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&
773                     (skb->protocol == htons(ETH_P_IP)) &&
774                     (skb->len > 64)) {
775 
776                         skb->csum = cur_p->app3 & 0xFFFF;
777                         skb->ip_summed = CHECKSUM_COMPLETE;
778                 }
779 
780                 if (!skb_defer_rx_timestamp(skb))
781                         netif_rx(skb);
782 
783                 ndev->stats.rx_packets++;
784                 ndev->stats.rx_bytes += length;
785 
786                 new_skb = netdev_alloc_skb_ip_align(ndev,
787                                                 XTE_MAX_JUMBO_FRAME_SIZE);
788                 if (!new_skb) {
789                         spin_unlock_irqrestore(&lp->rx_lock, flags);
790                         return;
791                 }
792 
793                 cur_p->app0 = STS_CTRL_APP0_IRQONEND;
794                 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
795                                              XTE_MAX_JUMBO_FRAME_SIZE,
796                                              DMA_FROM_DEVICE);
797                 cur_p->len = XTE_MAX_JUMBO_FRAME_SIZE;
798                 lp->rx_skb[lp->rx_bd_ci] = new_skb;
799 
800                 lp->rx_bd_ci++;
801                 if (lp->rx_bd_ci >= RX_BD_NUM)
802                         lp->rx_bd_ci = 0;
803 
804                 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
805                 bdstat = cur_p->app0;
806         }
807         lp->dma_out(lp, RX_TAILDESC_PTR, tail_p);
808 
809         spin_unlock_irqrestore(&lp->rx_lock, flags);
810 }
811 
812 static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
813 {
814         struct net_device *ndev = _ndev;
815         struct temac_local *lp = netdev_priv(ndev);
816         unsigned int status;
817 
818         status = lp->dma_in(lp, TX_IRQ_REG);
819         lp->dma_out(lp, TX_IRQ_REG, status);
820 
821         if (status & (IRQ_COAL | IRQ_DLY))
822                 temac_start_xmit_done(lp->ndev);
823         if (status & 0x080)
824                 dev_err(&ndev->dev, "DMA error 0x%x\n", status);
825 
826         return IRQ_HANDLED;
827 }
828 
829 static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
830 {
831         struct net_device *ndev = _ndev;
832         struct temac_local *lp = netdev_priv(ndev);
833         unsigned int status;
834 
835         /* Read and clear the status registers */
836         status = lp->dma_in(lp, RX_IRQ_REG);
837         lp->dma_out(lp, RX_IRQ_REG, status);
838 
839         if (status & (IRQ_COAL | IRQ_DLY))
840                 ll_temac_recv(lp->ndev);
841 
842         return IRQ_HANDLED;
843 }
844 
845 static int temac_open(struct net_device *ndev)
846 {
847         struct temac_local *lp = netdev_priv(ndev);
848         int rc;
849 
850         dev_dbg(&ndev->dev, "temac_open()\n");
851 
852         if (lp->phy_node) {
853                 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
854                                              temac_adjust_link, 0, 0);
855                 if (!lp->phy_dev) {
856                         dev_err(lp->dev, "of_phy_connect() failed\n");
857                         return -ENODEV;
858                 }
859 
860                 phy_start(lp->phy_dev);
861         }
862 
863         temac_device_reset(ndev);
864 
865         rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
866         if (rc)
867                 goto err_tx_irq;
868         rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
869         if (rc)
870                 goto err_rx_irq;
871 
872         return 0;
873 
874  err_rx_irq:
875         free_irq(lp->tx_irq, ndev);
876  err_tx_irq:
877         if (lp->phy_dev)
878                 phy_disconnect(lp->phy_dev);
879         lp->phy_dev = NULL;
880         dev_err(lp->dev, "request_irq() failed\n");
881         return rc;
882 }
883 
884 static int temac_stop(struct net_device *ndev)
885 {
886         struct temac_local *lp = netdev_priv(ndev);
887 
888         dev_dbg(&ndev->dev, "temac_close()\n");
889 
890         free_irq(lp->tx_irq, ndev);
891         free_irq(lp->rx_irq, ndev);
892 
893         if (lp->phy_dev)
894                 phy_disconnect(lp->phy_dev);
895         lp->phy_dev = NULL;
896 
897         temac_dma_bd_release(ndev);
898 
899         return 0;
900 }
901 
902 #ifdef CONFIG_NET_POLL_CONTROLLER
903 static void
904 temac_poll_controller(struct net_device *ndev)
905 {
906         struct temac_local *lp = netdev_priv(ndev);
907 
908         disable_irq(lp->tx_irq);
909         disable_irq(lp->rx_irq);
910 
911         ll_temac_rx_irq(lp->tx_irq, ndev);
912         ll_temac_tx_irq(lp->rx_irq, ndev);
913 
914         enable_irq(lp->tx_irq);
915         enable_irq(lp->rx_irq);
916 }
917 #endif
918 
919 static int temac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
920 {
921         struct temac_local *lp = netdev_priv(ndev);
922 
923         if (!netif_running(ndev))
924                 return -EINVAL;
925 
926         if (!lp->phy_dev)
927                 return -EINVAL;
928 
929         return phy_mii_ioctl(lp->phy_dev, rq, cmd);
930 }
931 
932 static const struct net_device_ops temac_netdev_ops = {
933         .ndo_open = temac_open,
934         .ndo_stop = temac_stop,
935         .ndo_start_xmit = temac_start_xmit,
936         .ndo_set_mac_address = temac_set_mac_address,
937         .ndo_validate_addr = eth_validate_addr,
938         .ndo_do_ioctl = temac_ioctl,
939 #ifdef CONFIG_NET_POLL_CONTROLLER
940         .ndo_poll_controller = temac_poll_controller,
941 #endif
942 };
943 
944 /* ---------------------------------------------------------------------
945  * SYSFS device attributes
946  */
947 static ssize_t temac_show_llink_regs(struct device *dev,
948                                      struct device_attribute *attr, char *buf)
949 {
950         struct net_device *ndev = dev_get_drvdata(dev);
951         struct temac_local *lp = netdev_priv(ndev);
952         int i, len = 0;
953 
954         for (i = 0; i < 0x11; i++)
955                 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
956                                (i % 8) == 7 ? "\n" : " ");
957         len += sprintf(buf + len, "\n");
958 
959         return len;
960 }
961 
962 static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
963 
964 static struct attribute *temac_device_attrs[] = {
965         &dev_attr_llink_regs.attr,
966         NULL,
967 };
968 
969 static const struct attribute_group temac_attr_group = {
970         .attrs = temac_device_attrs,
971 };
972 
973 /* ethtool support */
974 static int temac_get_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
975 {
976         struct temac_local *lp = netdev_priv(ndev);
977         return phy_ethtool_gset(lp->phy_dev, cmd);
978 }
979 
980 static int temac_set_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
981 {
982         struct temac_local *lp = netdev_priv(ndev);
983         return phy_ethtool_sset(lp->phy_dev, cmd);
984 }
985 
986 static int temac_nway_reset(struct net_device *ndev)
987 {
988         struct temac_local *lp = netdev_priv(ndev);
989         return phy_start_aneg(lp->phy_dev);
990 }
991 
992 static const struct ethtool_ops temac_ethtool_ops = {
993         .get_settings = temac_get_settings,
994         .set_settings = temac_set_settings,
995         .nway_reset = temac_nway_reset,
996         .get_link = ethtool_op_get_link,
997         .get_ts_info = ethtool_op_get_ts_info,
998 };
999 
1000 static int temac_of_probe(struct platform_device *op)
1001 {
1002         struct device_node *np;
1003         struct temac_local *lp;
1004         struct net_device *ndev;
1005         const void *addr;
1006         __be32 *p;
1007         int size, rc = 0;
1008 
1009         /* Init network device structure */
1010         ndev = alloc_etherdev(sizeof(*lp));
1011         if (!ndev)
1012                 return -ENOMEM;
1013 
1014         platform_set_drvdata(op, ndev);
1015         SET_NETDEV_DEV(ndev, &op->dev);
1016         ndev->flags &= ~IFF_MULTICAST;  /* clear multicast */
1017         ndev->features = NETIF_F_SG;
1018         ndev->netdev_ops = &temac_netdev_ops;
1019         ndev->ethtool_ops = &temac_ethtool_ops;
1020 #if 0
1021         ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
1022         ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
1023         ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
1024         ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
1025         ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; /* Transmit VLAN hw accel */
1026         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; /* Receive VLAN hw acceleration */
1027         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; /* Receive VLAN filtering */
1028         ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
1029         ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
1030         ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
1031         ndev->features |= NETIF_F_LRO; /* large receive offload */
1032 #endif
1033 
1034         /* setup temac private info structure */
1035         lp = netdev_priv(ndev);
1036         lp->ndev = ndev;
1037         lp->dev = &op->dev;
1038         lp->options = XTE_OPTION_DEFAULTS;
1039         spin_lock_init(&lp->rx_lock);
1040         mutex_init(&lp->indirect_mutex);
1041 
1042         /* map device registers */
1043         lp->regs = of_iomap(op->dev.of_node, 0);
1044         if (!lp->regs) {
1045                 dev_err(&op->dev, "could not map temac regs.\n");
1046                 rc = -ENOMEM;
1047                 goto nodev;
1048         }
1049 
1050         /* Setup checksum offload, but default to off if not specified */
1051         lp->temac_features = 0;
1052         p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,txcsum", NULL);
1053         if (p && be32_to_cpu(*p)) {
1054                 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1055                 /* Can checksum TCP/UDP over IPv4. */
1056                 ndev->features |= NETIF_F_IP_CSUM;
1057         }
1058         p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,rxcsum", NULL);
1059         if (p && be32_to_cpu(*p))
1060                 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1061 
1062         /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
1063         np = of_parse_phandle(op->dev.of_node, "llink-connected", 0);
1064         if (!np) {
1065                 dev_err(&op->dev, "could not find DMA node\n");
1066                 rc = -ENODEV;
1067                 goto err_iounmap;
1068         }
1069 
1070         /* Setup the DMA register accesses, could be DCR or memory mapped */
1071         if (temac_dcr_setup(lp, op, np)) {
1072 
1073                 /* no DCR in the device tree, try non-DCR */
1074                 lp->sdma_regs = of_iomap(np, 0);
1075                 if (lp->sdma_regs) {
1076                         lp->dma_in = temac_dma_in32;
1077                         lp->dma_out = temac_dma_out32;
1078                         dev_dbg(&op->dev, "MEM base: %p\n", lp->sdma_regs);
1079                 } else {
1080                         dev_err(&op->dev, "unable to map DMA registers\n");
1081                         of_node_put(np);
1082                         goto err_iounmap;
1083                 }
1084         }
1085 
1086         lp->rx_irq = irq_of_parse_and_map(np, 0);
1087         lp->tx_irq = irq_of_parse_and_map(np, 1);
1088 
1089         of_node_put(np); /* Finished with the DMA node; drop the reference */
1090 
1091         if (!lp->rx_irq || !lp->tx_irq) {
1092                 dev_err(&op->dev, "could not determine irqs\n");
1093                 rc = -ENOMEM;
1094                 goto err_iounmap_2;
1095         }
1096 
1097 
1098         /* Retrieve the MAC address */
1099         addr = of_get_property(op->dev.of_node, "local-mac-address", &size);
1100         if ((!addr) || (size != 6)) {
1101                 dev_err(&op->dev, "could not find MAC address\n");
1102                 rc = -ENODEV;
1103                 goto err_iounmap_2;
1104         }
1105         temac_init_mac_address(ndev, (void *)addr);
1106 
1107         rc = temac_mdio_setup(lp, op->dev.of_node);
1108         if (rc)
1109                 dev_warn(&op->dev, "error registering MDIO bus\n");
1110 
1111         lp->phy_node = of_parse_phandle(op->dev.of_node, "phy-handle", 0);
1112         if (lp->phy_node)
1113                 dev_dbg(lp->dev, "using PHY node %s (%p)\n", np->full_name, np);
1114 
1115         /* Add the device attributes */
1116         rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
1117         if (rc) {
1118                 dev_err(lp->dev, "Error creating sysfs files\n");
1119                 goto err_iounmap_2;
1120         }
1121 
1122         rc = register_netdev(lp->ndev);
1123         if (rc) {
1124                 dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
1125                 goto err_register_ndev;
1126         }
1127 
1128         return 0;
1129 
1130  err_register_ndev:
1131         sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1132  err_iounmap_2:
1133         if (lp->sdma_regs)
1134                 iounmap(lp->sdma_regs);
1135  err_iounmap:
1136         iounmap(lp->regs);
1137  nodev:
1138         free_netdev(ndev);
1139         ndev = NULL;
1140         return rc;
1141 }
1142 
1143 static int temac_of_remove(struct platform_device *op)
1144 {
1145         struct net_device *ndev = platform_get_drvdata(op);
1146         struct temac_local *lp = netdev_priv(ndev);
1147 
1148         temac_mdio_teardown(lp);
1149         unregister_netdev(ndev);
1150         sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1151         of_node_put(lp->phy_node);
1152         lp->phy_node = NULL;
1153         iounmap(lp->regs);
1154         if (lp->sdma_regs)
1155                 iounmap(lp->sdma_regs);
1156         free_netdev(ndev);
1157         return 0;
1158 }
1159 
1160 static const struct of_device_id temac_of_match[] = {
1161         { .compatible = "xlnx,xps-ll-temac-1.01.b", },
1162         { .compatible = "xlnx,xps-ll-temac-2.00.a", },
1163         { .compatible = "xlnx,xps-ll-temac-2.02.a", },
1164         { .compatible = "xlnx,xps-ll-temac-2.03.a", },
1165         {},
1166 };
1167 MODULE_DEVICE_TABLE(of, temac_of_match);
1168 
1169 static struct platform_driver temac_of_driver = {
1170         .probe = temac_of_probe,
1171         .remove = temac_of_remove,
1172         .driver = {
1173                 .name = "xilinx_temac",
1174                 .of_match_table = temac_of_match,
1175         },
1176 };
1177 
1178 module_platform_driver(temac_of_driver);
1179 
1180 MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1181 MODULE_AUTHOR("Yoshio Kashiwagi");
1182 MODULE_LICENSE("GPL");
1183 

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