Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/net/ethernet/wiznet/w5100.c

  1 /*
  2  * Ethernet driver for the WIZnet W5100 chip.
  3  *
  4  * Copyright (C) 2006-2008 WIZnet Co.,Ltd.
  5  * Copyright (C) 2012 Mike Sinkovsky <msink@permonline.ru>
  6  *
  7  * Licensed under the GPL-2 or later.
  8  */
  9 
 10 #include <linux/kernel.h>
 11 #include <linux/module.h>
 12 #include <linux/kconfig.h>
 13 #include <linux/netdevice.h>
 14 #include <linux/etherdevice.h>
 15 #include <linux/platform_device.h>
 16 #include <linux/platform_data/wiznet.h>
 17 #include <linux/ethtool.h>
 18 #include <linux/skbuff.h>
 19 #include <linux/types.h>
 20 #include <linux/errno.h>
 21 #include <linux/delay.h>
 22 #include <linux/slab.h>
 23 #include <linux/spinlock.h>
 24 #include <linux/io.h>
 25 #include <linux/ioport.h>
 26 #include <linux/interrupt.h>
 27 #include <linux/irq.h>
 28 #include <linux/gpio.h>
 29 
 30 #define DRV_NAME        "w5100"
 31 #define DRV_VERSION     "2012-04-04"
 32 
 33 MODULE_DESCRIPTION("WIZnet W5100 Ethernet driver v"DRV_VERSION);
 34 MODULE_AUTHOR("Mike Sinkovsky <msink@permonline.ru>");
 35 MODULE_ALIAS("platform:"DRV_NAME);
 36 MODULE_LICENSE("GPL");
 37 
 38 /*
 39  * Registers
 40  */
 41 #define W5100_COMMON_REGS       0x0000
 42 #define W5100_MR                0x0000 /* Mode Register */
 43 #define   MR_RST                  0x80 /* S/W reset */
 44 #define   MR_PB                   0x10 /* Ping block */
 45 #define   MR_AI                   0x02 /* Address Auto-Increment */
 46 #define   MR_IND                  0x01 /* Indirect mode */
 47 #define W5100_SHAR              0x0009 /* Source MAC address */
 48 #define W5100_IR                0x0015 /* Interrupt Register */
 49 #define W5100_IMR               0x0016 /* Interrupt Mask Register */
 50 #define   IR_S0                   0x01 /* S0 interrupt */
 51 #define W5100_RTR               0x0017 /* Retry Time-value Register */
 52 #define   RTR_DEFAULT             2000 /* =0x07d0 (2000) */
 53 #define W5100_RMSR              0x001a /* Receive Memory Size */
 54 #define W5100_TMSR              0x001b /* Transmit Memory Size */
 55 #define W5100_COMMON_REGS_LEN   0x0040
 56 
 57 #define W5100_S0_REGS           0x0400
 58 #define W5100_S0_MR             0x0400 /* S0 Mode Register */
 59 #define   S0_MR_MACRAW            0x04 /* MAC RAW mode (promiscous) */
 60 #define   S0_MR_MACRAW_MF         0x44 /* MAC RAW mode (filtered) */
 61 #define W5100_S0_CR             0x0401 /* S0 Command Register */
 62 #define   S0_CR_OPEN              0x01 /* OPEN command */
 63 #define   S0_CR_CLOSE             0x10 /* CLOSE command */
 64 #define   S0_CR_SEND              0x20 /* SEND command */
 65 #define   S0_CR_RECV              0x40 /* RECV command */
 66 #define W5100_S0_IR             0x0402 /* S0 Interrupt Register */
 67 #define   S0_IR_SENDOK            0x10 /* complete sending */
 68 #define   S0_IR_RECV              0x04 /* receiving data */
 69 #define W5100_S0_SR             0x0403 /* S0 Status Register */
 70 #define   S0_SR_MACRAW            0x42 /* mac raw mode */
 71 #define W5100_S0_TX_FSR         0x0420 /* S0 Transmit free memory size */
 72 #define W5100_S0_TX_RD          0x0422 /* S0 Transmit memory read pointer */
 73 #define W5100_S0_TX_WR          0x0424 /* S0 Transmit memory write pointer */
 74 #define W5100_S0_RX_RSR         0x0426 /* S0 Receive free memory size */
 75 #define W5100_S0_RX_RD          0x0428 /* S0 Receive memory read pointer */
 76 #define W5100_S0_REGS_LEN       0x0040
 77 
 78 #define W5100_TX_MEM_START      0x4000
 79 #define W5100_TX_MEM_END        0x5fff
 80 #define W5100_TX_MEM_MASK       0x1fff
 81 #define W5100_RX_MEM_START      0x6000
 82 #define W5100_RX_MEM_END        0x7fff
 83 #define W5100_RX_MEM_MASK       0x1fff
 84 
 85 /*
 86  * Device driver private data structure
 87  */
 88 struct w5100_priv {
 89         void __iomem *base;
 90         spinlock_t reg_lock;
 91         bool indirect;
 92         u8   (*read)(struct w5100_priv *priv, u16 addr);
 93         void (*write)(struct w5100_priv *priv, u16 addr, u8 data);
 94         u16  (*read16)(struct w5100_priv *priv, u16 addr);
 95         void (*write16)(struct w5100_priv *priv, u16 addr, u16 data);
 96         void (*readbuf)(struct w5100_priv *priv, u16 addr, u8 *buf, int len);
 97         void (*writebuf)(struct w5100_priv *priv, u16 addr, u8 *buf, int len);
 98         int irq;
 99         int link_irq;
100         int link_gpio;
101 
102         struct napi_struct napi;
103         struct net_device *ndev;
104         bool promisc;
105         u32 msg_enable;
106 };
107 
108 /************************************************************************
109  *
110  *  Lowlevel I/O functions
111  *
112  ***********************************************************************/
113 
114 /*
115  * In direct address mode host system can directly access W5100 registers
116  * after mapping to Memory-Mapped I/O space.
117  *
118  * 0x8000 bytes are required for memory space.
119  */
120 static inline u8 w5100_read_direct(struct w5100_priv *priv, u16 addr)
121 {
122         return ioread8(priv->base + (addr << CONFIG_WIZNET_BUS_SHIFT));
123 }
124 
125 static inline void w5100_write_direct(struct w5100_priv *priv,
126                                       u16 addr, u8 data)
127 {
128         iowrite8(data, priv->base + (addr << CONFIG_WIZNET_BUS_SHIFT));
129 }
130 
131 static u16 w5100_read16_direct(struct w5100_priv *priv, u16 addr)
132 {
133         u16 data;
134         data  = w5100_read_direct(priv, addr) << 8;
135         data |= w5100_read_direct(priv, addr + 1);
136         return data;
137 }
138 
139 static void w5100_write16_direct(struct w5100_priv *priv, u16 addr, u16 data)
140 {
141         w5100_write_direct(priv, addr, data >> 8);
142         w5100_write_direct(priv, addr + 1, data);
143 }
144 
145 static void w5100_readbuf_direct(struct w5100_priv *priv,
146                                  u16 offset, u8 *buf, int len)
147 {
148         u16 addr = W5100_RX_MEM_START + (offset & W5100_RX_MEM_MASK);
149         int i;
150 
151         for (i = 0; i < len; i++, addr++) {
152                 if (unlikely(addr > W5100_RX_MEM_END))
153                         addr = W5100_RX_MEM_START;
154                 *buf++ = w5100_read_direct(priv, addr);
155         }
156 }
157 
158 static void w5100_writebuf_direct(struct w5100_priv *priv,
159                                   u16 offset, u8 *buf, int len)
160 {
161         u16 addr = W5100_TX_MEM_START + (offset & W5100_TX_MEM_MASK);
162         int i;
163 
164         for (i = 0; i < len; i++, addr++) {
165                 if (unlikely(addr > W5100_TX_MEM_END))
166                         addr = W5100_TX_MEM_START;
167                 w5100_write_direct(priv, addr, *buf++);
168         }
169 }
170 
171 /*
172  * In indirect address mode host system indirectly accesses registers by
173  * using Indirect Mode Address Register (IDM_AR) and Indirect Mode Data
174  * Register (IDM_DR), which are directly mapped to Memory-Mapped I/O space.
175  * Mode Register (MR) is directly accessible.
176  *
177  * Only 0x04 bytes are required for memory space.
178  */
179 #define W5100_IDM_AR            0x01   /* Indirect Mode Address Register */
180 #define W5100_IDM_DR            0x03   /* Indirect Mode Data Register */
181 
182 static u8 w5100_read_indirect(struct w5100_priv *priv, u16 addr)
183 {
184         unsigned long flags;
185         u8 data;
186 
187         spin_lock_irqsave(&priv->reg_lock, flags);
188         w5100_write16_direct(priv, W5100_IDM_AR, addr);
189         mmiowb();
190         data = w5100_read_direct(priv, W5100_IDM_DR);
191         spin_unlock_irqrestore(&priv->reg_lock, flags);
192 
193         return data;
194 }
195 
196 static void w5100_write_indirect(struct w5100_priv *priv, u16 addr, u8 data)
197 {
198         unsigned long flags;
199 
200         spin_lock_irqsave(&priv->reg_lock, flags);
201         w5100_write16_direct(priv, W5100_IDM_AR, addr);
202         mmiowb();
203         w5100_write_direct(priv, W5100_IDM_DR, data);
204         mmiowb();
205         spin_unlock_irqrestore(&priv->reg_lock, flags);
206 }
207 
208 static u16 w5100_read16_indirect(struct w5100_priv *priv, u16 addr)
209 {
210         unsigned long flags;
211         u16 data;
212 
213         spin_lock_irqsave(&priv->reg_lock, flags);
214         w5100_write16_direct(priv, W5100_IDM_AR, addr);
215         mmiowb();
216         data  = w5100_read_direct(priv, W5100_IDM_DR) << 8;
217         data |= w5100_read_direct(priv, W5100_IDM_DR);
218         spin_unlock_irqrestore(&priv->reg_lock, flags);
219 
220         return data;
221 }
222 
223 static void w5100_write16_indirect(struct w5100_priv *priv, u16 addr, u16 data)
224 {
225         unsigned long flags;
226 
227         spin_lock_irqsave(&priv->reg_lock, flags);
228         w5100_write16_direct(priv, W5100_IDM_AR, addr);
229         mmiowb();
230         w5100_write_direct(priv, W5100_IDM_DR, data >> 8);
231         w5100_write_direct(priv, W5100_IDM_DR, data);
232         mmiowb();
233         spin_unlock_irqrestore(&priv->reg_lock, flags);
234 }
235 
236 static void w5100_readbuf_indirect(struct w5100_priv *priv,
237                                    u16 offset, u8 *buf, int len)
238 {
239         u16 addr = W5100_RX_MEM_START + (offset & W5100_RX_MEM_MASK);
240         unsigned long flags;
241         int i;
242 
243         spin_lock_irqsave(&priv->reg_lock, flags);
244         w5100_write16_direct(priv, W5100_IDM_AR, addr);
245         mmiowb();
246 
247         for (i = 0; i < len; i++, addr++) {
248                 if (unlikely(addr > W5100_RX_MEM_END)) {
249                         addr = W5100_RX_MEM_START;
250                         w5100_write16_direct(priv, W5100_IDM_AR, addr);
251                         mmiowb();
252                 }
253                 *buf++ = w5100_read_direct(priv, W5100_IDM_DR);
254         }
255         mmiowb();
256         spin_unlock_irqrestore(&priv->reg_lock, flags);
257 }
258 
259 static void w5100_writebuf_indirect(struct w5100_priv *priv,
260                                     u16 offset, u8 *buf, int len)
261 {
262         u16 addr = W5100_TX_MEM_START + (offset & W5100_TX_MEM_MASK);
263         unsigned long flags;
264         int i;
265 
266         spin_lock_irqsave(&priv->reg_lock, flags);
267         w5100_write16_direct(priv, W5100_IDM_AR, addr);
268         mmiowb();
269 
270         for (i = 0; i < len; i++, addr++) {
271                 if (unlikely(addr > W5100_TX_MEM_END)) {
272                         addr = W5100_TX_MEM_START;
273                         w5100_write16_direct(priv, W5100_IDM_AR, addr);
274                         mmiowb();
275                 }
276                 w5100_write_direct(priv, W5100_IDM_DR, *buf++);
277         }
278         mmiowb();
279         spin_unlock_irqrestore(&priv->reg_lock, flags);
280 }
281 
282 #if defined(CONFIG_WIZNET_BUS_DIRECT)
283 #define w5100_read      w5100_read_direct
284 #define w5100_write     w5100_write_direct
285 #define w5100_read16    w5100_read16_direct
286 #define w5100_write16   w5100_write16_direct
287 #define w5100_readbuf   w5100_readbuf_direct
288 #define w5100_writebuf  w5100_writebuf_direct
289 
290 #elif defined(CONFIG_WIZNET_BUS_INDIRECT)
291 #define w5100_read      w5100_read_indirect
292 #define w5100_write     w5100_write_indirect
293 #define w5100_read16    w5100_read16_indirect
294 #define w5100_write16   w5100_write16_indirect
295 #define w5100_readbuf   w5100_readbuf_indirect
296 #define w5100_writebuf  w5100_writebuf_indirect
297 
298 #else /* CONFIG_WIZNET_BUS_ANY */
299 #define w5100_read      priv->read
300 #define w5100_write     priv->write
301 #define w5100_read16    priv->read16
302 #define w5100_write16   priv->write16
303 #define w5100_readbuf   priv->readbuf
304 #define w5100_writebuf  priv->writebuf
305 #endif
306 
307 static int w5100_command(struct w5100_priv *priv, u16 cmd)
308 {
309         unsigned long timeout = jiffies + msecs_to_jiffies(100);
310 
311         w5100_write(priv, W5100_S0_CR, cmd);
312         mmiowb();
313 
314         while (w5100_read(priv, W5100_S0_CR) != 0) {
315                 if (time_after(jiffies, timeout))
316                         return -EIO;
317                 cpu_relax();
318         }
319 
320         return 0;
321 }
322 
323 static void w5100_write_macaddr(struct w5100_priv *priv)
324 {
325         struct net_device *ndev = priv->ndev;
326         int i;
327 
328         for (i = 0; i < ETH_ALEN; i++)
329                 w5100_write(priv, W5100_SHAR + i, ndev->dev_addr[i]);
330         mmiowb();
331 }
332 
333 static void w5100_hw_reset(struct w5100_priv *priv)
334 {
335         w5100_write_direct(priv, W5100_MR, MR_RST);
336         mmiowb();
337         mdelay(5);
338         w5100_write_direct(priv, W5100_MR, priv->indirect ?
339                                   MR_PB | MR_AI | MR_IND :
340                                   MR_PB);
341         mmiowb();
342         w5100_write(priv, W5100_IMR, 0);
343         w5100_write_macaddr(priv);
344 
345         /* Configure 16K of internal memory
346          * as 8K RX buffer and 8K TX buffer
347          */
348         w5100_write(priv, W5100_RMSR, 0x03);
349         w5100_write(priv, W5100_TMSR, 0x03);
350         mmiowb();
351 }
352 
353 static void w5100_hw_start(struct w5100_priv *priv)
354 {
355         w5100_write(priv, W5100_S0_MR, priv->promisc ?
356                           S0_MR_MACRAW : S0_MR_MACRAW_MF);
357         mmiowb();
358         w5100_command(priv, S0_CR_OPEN);
359         w5100_write(priv, W5100_IMR, IR_S0);
360         mmiowb();
361 }
362 
363 static void w5100_hw_close(struct w5100_priv *priv)
364 {
365         w5100_write(priv, W5100_IMR, 0);
366         mmiowb();
367         w5100_command(priv, S0_CR_CLOSE);
368 }
369 
370 /***********************************************************************
371  *
372  *   Device driver functions / callbacks
373  *
374  ***********************************************************************/
375 
376 static void w5100_get_drvinfo(struct net_device *ndev,
377                               struct ethtool_drvinfo *info)
378 {
379         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
380         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
381         strlcpy(info->bus_info, dev_name(ndev->dev.parent),
382                 sizeof(info->bus_info));
383 }
384 
385 static u32 w5100_get_link(struct net_device *ndev)
386 {
387         struct w5100_priv *priv = netdev_priv(ndev);
388 
389         if (gpio_is_valid(priv->link_gpio))
390                 return !!gpio_get_value(priv->link_gpio);
391 
392         return 1;
393 }
394 
395 static u32 w5100_get_msglevel(struct net_device *ndev)
396 {
397         struct w5100_priv *priv = netdev_priv(ndev);
398 
399         return priv->msg_enable;
400 }
401 
402 static void w5100_set_msglevel(struct net_device *ndev, u32 value)
403 {
404         struct w5100_priv *priv = netdev_priv(ndev);
405 
406         priv->msg_enable = value;
407 }
408 
409 static int w5100_get_regs_len(struct net_device *ndev)
410 {
411         return W5100_COMMON_REGS_LEN + W5100_S0_REGS_LEN;
412 }
413 
414 static void w5100_get_regs(struct net_device *ndev,
415                            struct ethtool_regs *regs, void *_buf)
416 {
417         struct w5100_priv *priv = netdev_priv(ndev);
418         u8 *buf = _buf;
419         u16 i;
420 
421         regs->version = 1;
422         for (i = 0; i < W5100_COMMON_REGS_LEN; i++)
423                 *buf++ = w5100_read(priv, W5100_COMMON_REGS + i);
424         for (i = 0; i < W5100_S0_REGS_LEN; i++)
425                 *buf++ = w5100_read(priv, W5100_S0_REGS + i);
426 }
427 
428 static void w5100_tx_timeout(struct net_device *ndev)
429 {
430         struct w5100_priv *priv = netdev_priv(ndev);
431 
432         netif_stop_queue(ndev);
433         w5100_hw_reset(priv);
434         w5100_hw_start(priv);
435         ndev->stats.tx_errors++;
436         ndev->trans_start = jiffies;
437         netif_wake_queue(ndev);
438 }
439 
440 static int w5100_start_tx(struct sk_buff *skb, struct net_device *ndev)
441 {
442         struct w5100_priv *priv = netdev_priv(ndev);
443         u16 offset;
444 
445         netif_stop_queue(ndev);
446 
447         offset = w5100_read16(priv, W5100_S0_TX_WR);
448         w5100_writebuf(priv, offset, skb->data, skb->len);
449         w5100_write16(priv, W5100_S0_TX_WR, offset + skb->len);
450         mmiowb();
451         ndev->stats.tx_bytes += skb->len;
452         ndev->stats.tx_packets++;
453         dev_kfree_skb(skb);
454 
455         w5100_command(priv, S0_CR_SEND);
456 
457         return NETDEV_TX_OK;
458 }
459 
460 static int w5100_napi_poll(struct napi_struct *napi, int budget)
461 {
462         struct w5100_priv *priv = container_of(napi, struct w5100_priv, napi);
463         struct net_device *ndev = priv->ndev;
464         struct sk_buff *skb;
465         int rx_count;
466         u16 rx_len;
467         u16 offset;
468         u8 header[2];
469 
470         for (rx_count = 0; rx_count < budget; rx_count++) {
471                 u16 rx_buf_len = w5100_read16(priv, W5100_S0_RX_RSR);
472                 if (rx_buf_len == 0)
473                         break;
474 
475                 offset = w5100_read16(priv, W5100_S0_RX_RD);
476                 w5100_readbuf(priv, offset, header, 2);
477                 rx_len = get_unaligned_be16(header) - 2;
478 
479                 skb = netdev_alloc_skb_ip_align(ndev, rx_len);
480                 if (unlikely(!skb)) {
481                         w5100_write16(priv, W5100_S0_RX_RD,
482                                             offset + rx_buf_len);
483                         w5100_command(priv, S0_CR_RECV);
484                         ndev->stats.rx_dropped++;
485                         return -ENOMEM;
486                 }
487 
488                 skb_put(skb, rx_len);
489                 w5100_readbuf(priv, offset + 2, skb->data, rx_len);
490                 w5100_write16(priv, W5100_S0_RX_RD, offset + 2 + rx_len);
491                 mmiowb();
492                 w5100_command(priv, S0_CR_RECV);
493                 skb->protocol = eth_type_trans(skb, ndev);
494 
495                 netif_receive_skb(skb);
496                 ndev->stats.rx_packets++;
497                 ndev->stats.rx_bytes += rx_len;
498         }
499 
500         if (rx_count < budget) {
501                 w5100_write(priv, W5100_IMR, IR_S0);
502                 mmiowb();
503                 napi_complete(napi);
504         }
505 
506         return rx_count;
507 }
508 
509 static irqreturn_t w5100_interrupt(int irq, void *ndev_instance)
510 {
511         struct net_device *ndev = ndev_instance;
512         struct w5100_priv *priv = netdev_priv(ndev);
513 
514         int ir = w5100_read(priv, W5100_S0_IR);
515         if (!ir)
516                 return IRQ_NONE;
517         w5100_write(priv, W5100_S0_IR, ir);
518         mmiowb();
519 
520         if (ir & S0_IR_SENDOK) {
521                 netif_dbg(priv, tx_done, ndev, "tx done\n");
522                 netif_wake_queue(ndev);
523         }
524 
525         if (ir & S0_IR_RECV) {
526                 if (napi_schedule_prep(&priv->napi)) {
527                         w5100_write(priv, W5100_IMR, 0);
528                         mmiowb();
529                         __napi_schedule(&priv->napi);
530                 }
531         }
532 
533         return IRQ_HANDLED;
534 }
535 
536 static irqreturn_t w5100_detect_link(int irq, void *ndev_instance)
537 {
538         struct net_device *ndev = ndev_instance;
539         struct w5100_priv *priv = netdev_priv(ndev);
540 
541         if (netif_running(ndev)) {
542                 if (gpio_get_value(priv->link_gpio) != 0) {
543                         netif_info(priv, link, ndev, "link is up\n");
544                         netif_carrier_on(ndev);
545                 } else {
546                         netif_info(priv, link, ndev, "link is down\n");
547                         netif_carrier_off(ndev);
548                 }
549         }
550 
551         return IRQ_HANDLED;
552 }
553 
554 static void w5100_set_rx_mode(struct net_device *ndev)
555 {
556         struct w5100_priv *priv = netdev_priv(ndev);
557         bool set_promisc = (ndev->flags & IFF_PROMISC) != 0;
558 
559         if (priv->promisc != set_promisc) {
560                 priv->promisc = set_promisc;
561                 w5100_hw_start(priv);
562         }
563 }
564 
565 static int w5100_set_macaddr(struct net_device *ndev, void *addr)
566 {
567         struct w5100_priv *priv = netdev_priv(ndev);
568         struct sockaddr *sock_addr = addr;
569 
570         if (!is_valid_ether_addr(sock_addr->sa_data))
571                 return -EADDRNOTAVAIL;
572         memcpy(ndev->dev_addr, sock_addr->sa_data, ETH_ALEN);
573         w5100_write_macaddr(priv);
574         return 0;
575 }
576 
577 static int w5100_open(struct net_device *ndev)
578 {
579         struct w5100_priv *priv = netdev_priv(ndev);
580 
581         netif_info(priv, ifup, ndev, "enabling\n");
582         w5100_hw_start(priv);
583         napi_enable(&priv->napi);
584         netif_start_queue(ndev);
585         if (!gpio_is_valid(priv->link_gpio) ||
586             gpio_get_value(priv->link_gpio) != 0)
587                 netif_carrier_on(ndev);
588         return 0;
589 }
590 
591 static int w5100_stop(struct net_device *ndev)
592 {
593         struct w5100_priv *priv = netdev_priv(ndev);
594 
595         netif_info(priv, ifdown, ndev, "shutting down\n");
596         w5100_hw_close(priv);
597         netif_carrier_off(ndev);
598         netif_stop_queue(ndev);
599         napi_disable(&priv->napi);
600         return 0;
601 }
602 
603 static const struct ethtool_ops w5100_ethtool_ops = {
604         .get_drvinfo            = w5100_get_drvinfo,
605         .get_msglevel           = w5100_get_msglevel,
606         .set_msglevel           = w5100_set_msglevel,
607         .get_link               = w5100_get_link,
608         .get_regs_len           = w5100_get_regs_len,
609         .get_regs               = w5100_get_regs,
610 };
611 
612 static const struct net_device_ops w5100_netdev_ops = {
613         .ndo_open               = w5100_open,
614         .ndo_stop               = w5100_stop,
615         .ndo_start_xmit         = w5100_start_tx,
616         .ndo_tx_timeout         = w5100_tx_timeout,
617         .ndo_set_rx_mode        = w5100_set_rx_mode,
618         .ndo_set_mac_address    = w5100_set_macaddr,
619         .ndo_validate_addr      = eth_validate_addr,
620         .ndo_change_mtu         = eth_change_mtu,
621 };
622 
623 static int w5100_hw_probe(struct platform_device *pdev)
624 {
625         struct wiznet_platform_data *data = dev_get_platdata(&pdev->dev);
626         struct net_device *ndev = platform_get_drvdata(pdev);
627         struct w5100_priv *priv = netdev_priv(ndev);
628         const char *name = netdev_name(ndev);
629         struct resource *mem;
630         int mem_size;
631         int irq;
632         int ret;
633 
634         if (data && is_valid_ether_addr(data->mac_addr)) {
635                 memcpy(ndev->dev_addr, data->mac_addr, ETH_ALEN);
636         } else {
637                 eth_hw_addr_random(ndev);
638         }
639 
640         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
641         if (!mem)
642                 return -ENXIO;
643         mem_size = resource_size(mem);
644 
645         priv->base = devm_ioremap_resource(&pdev->dev, mem);
646         if (IS_ERR(priv->base))
647                 return PTR_ERR(priv->base);
648 
649         spin_lock_init(&priv->reg_lock);
650         priv->indirect = mem_size < W5100_BUS_DIRECT_SIZE;
651         if (priv->indirect) {
652                 priv->read     = w5100_read_indirect;
653                 priv->write    = w5100_write_indirect;
654                 priv->read16   = w5100_read16_indirect;
655                 priv->write16  = w5100_write16_indirect;
656                 priv->readbuf  = w5100_readbuf_indirect;
657                 priv->writebuf = w5100_writebuf_indirect;
658         } else {
659                 priv->read     = w5100_read_direct;
660                 priv->write    = w5100_write_direct;
661                 priv->read16   = w5100_read16_direct;
662                 priv->write16  = w5100_write16_direct;
663                 priv->readbuf  = w5100_readbuf_direct;
664                 priv->writebuf = w5100_writebuf_direct;
665         }
666 
667         w5100_hw_reset(priv);
668         if (w5100_read16(priv, W5100_RTR) != RTR_DEFAULT)
669                 return -ENODEV;
670 
671         irq = platform_get_irq(pdev, 0);
672         if (irq < 0)
673                 return irq;
674         ret = request_irq(irq, w5100_interrupt,
675                           IRQ_TYPE_LEVEL_LOW, name, ndev);
676         if (ret < 0)
677                 return ret;
678         priv->irq = irq;
679 
680         priv->link_gpio = data ? data->link_gpio : -EINVAL;
681         if (gpio_is_valid(priv->link_gpio)) {
682                 char *link_name = devm_kzalloc(&pdev->dev, 16, GFP_KERNEL);
683                 if (!link_name)
684                         return -ENOMEM;
685                 snprintf(link_name, 16, "%s-link", name);
686                 priv->link_irq = gpio_to_irq(priv->link_gpio);
687                 if (request_any_context_irq(priv->link_irq, w5100_detect_link,
688                                 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
689                                 link_name, priv->ndev) < 0)
690                         priv->link_gpio = -EINVAL;
691         }
692 
693         netdev_info(ndev, "at 0x%llx irq %d\n", (u64)mem->start, irq);
694         return 0;
695 }
696 
697 static int w5100_probe(struct platform_device *pdev)
698 {
699         struct w5100_priv *priv;
700         struct net_device *ndev;
701         int err;
702 
703         ndev = alloc_etherdev(sizeof(*priv));
704         if (!ndev)
705                 return -ENOMEM;
706         SET_NETDEV_DEV(ndev, &pdev->dev);
707         platform_set_drvdata(pdev, ndev);
708         priv = netdev_priv(ndev);
709         priv->ndev = ndev;
710 
711         ether_setup(ndev);
712         ndev->netdev_ops = &w5100_netdev_ops;
713         ndev->ethtool_ops = &w5100_ethtool_ops;
714         ndev->watchdog_timeo = HZ;
715         netif_napi_add(ndev, &priv->napi, w5100_napi_poll, 16);
716 
717         /* This chip doesn't support VLAN packets with normal MTU,
718          * so disable VLAN for this device.
719          */
720         ndev->features |= NETIF_F_VLAN_CHALLENGED;
721 
722         err = register_netdev(ndev);
723         if (err < 0)
724                 goto err_register;
725 
726         err = w5100_hw_probe(pdev);
727         if (err < 0)
728                 goto err_hw_probe;
729 
730         return 0;
731 
732 err_hw_probe:
733         unregister_netdev(ndev);
734 err_register:
735         free_netdev(ndev);
736         return err;
737 }
738 
739 static int w5100_remove(struct platform_device *pdev)
740 {
741         struct net_device *ndev = platform_get_drvdata(pdev);
742         struct w5100_priv *priv = netdev_priv(ndev);
743 
744         w5100_hw_reset(priv);
745         free_irq(priv->irq, ndev);
746         if (gpio_is_valid(priv->link_gpio))
747                 free_irq(priv->link_irq, ndev);
748 
749         unregister_netdev(ndev);
750         free_netdev(ndev);
751         return 0;
752 }
753 
754 #ifdef CONFIG_PM_SLEEP
755 static int w5100_suspend(struct device *dev)
756 {
757         struct platform_device *pdev = to_platform_device(dev);
758         struct net_device *ndev = platform_get_drvdata(pdev);
759         struct w5100_priv *priv = netdev_priv(ndev);
760 
761         if (netif_running(ndev)) {
762                 netif_carrier_off(ndev);
763                 netif_device_detach(ndev);
764 
765                 w5100_hw_close(priv);
766         }
767         return 0;
768 }
769 
770 static int w5100_resume(struct device *dev)
771 {
772         struct platform_device *pdev = to_platform_device(dev);
773         struct net_device *ndev = platform_get_drvdata(pdev);
774         struct w5100_priv *priv = netdev_priv(ndev);
775 
776         if (netif_running(ndev)) {
777                 w5100_hw_reset(priv);
778                 w5100_hw_start(priv);
779 
780                 netif_device_attach(ndev);
781                 if (!gpio_is_valid(priv->link_gpio) ||
782                     gpio_get_value(priv->link_gpio) != 0)
783                         netif_carrier_on(ndev);
784         }
785         return 0;
786 }
787 #endif /* CONFIG_PM_SLEEP */
788 
789 static SIMPLE_DEV_PM_OPS(w5100_pm_ops, w5100_suspend, w5100_resume);
790 
791 static struct platform_driver w5100_driver = {
792         .driver         = {
793                 .name   = DRV_NAME,
794                 .owner  = THIS_MODULE,
795                 .pm     = &w5100_pm_ops,
796         },
797         .probe          = w5100_probe,
798         .remove         = w5100_remove,
799 };
800 
801 module_platform_driver(w5100_driver);
802 

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