Version:  2.0.40 2.2.26 2.4.37 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6

Linux/drivers/net/ethernet/ti/cpsw.c

  1 /*
  2  * Texas Instruments Ethernet Switch Driver
  3  *
  4  * Copyright (C) 2012 Texas Instruments
  5  *
  6  * This program is free software; you can redistribute it and/or
  7  * modify it under the terms of the GNU General Public License as
  8  * published by the Free Software Foundation version 2.
  9  *
 10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 11  * kind, whether express or implied; without even the implied warranty
 12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  */
 15 
 16 #include <linux/kernel.h>
 17 #include <linux/io.h>
 18 #include <linux/clk.h>
 19 #include <linux/timer.h>
 20 #include <linux/module.h>
 21 #include <linux/platform_device.h>
 22 #include <linux/irqreturn.h>
 23 #include <linux/interrupt.h>
 24 #include <linux/if_ether.h>
 25 #include <linux/etherdevice.h>
 26 #include <linux/netdevice.h>
 27 #include <linux/net_tstamp.h>
 28 #include <linux/phy.h>
 29 #include <linux/workqueue.h>
 30 #include <linux/delay.h>
 31 #include <linux/pm_runtime.h>
 32 #include <linux/gpio.h>
 33 #include <linux/of.h>
 34 #include <linux/of_mdio.h>
 35 #include <linux/of_net.h>
 36 #include <linux/of_device.h>
 37 #include <linux/if_vlan.h>
 38 
 39 #include <linux/pinctrl/consumer.h>
 40 
 41 #include "cpsw.h"
 42 #include "cpsw_ale.h"
 43 #include "cpts.h"
 44 #include "davinci_cpdma.h"
 45 
 46 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
 47                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
 48                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
 49                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
 50                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
 51                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
 52                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
 53                          NETIF_MSG_RX_STATUS)
 54 
 55 #define cpsw_info(priv, type, format, ...)              \
 56 do {                                                            \
 57         if (netif_msg_##type(priv) && net_ratelimit())          \
 58                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
 59 } while (0)
 60 
 61 #define cpsw_err(priv, type, format, ...)               \
 62 do {                                                            \
 63         if (netif_msg_##type(priv) && net_ratelimit())          \
 64                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
 65 } while (0)
 66 
 67 #define cpsw_dbg(priv, type, format, ...)               \
 68 do {                                                            \
 69         if (netif_msg_##type(priv) && net_ratelimit())          \
 70                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
 71 } while (0)
 72 
 73 #define cpsw_notice(priv, type, format, ...)            \
 74 do {                                                            \
 75         if (netif_msg_##type(priv) && net_ratelimit())          \
 76                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
 77 } while (0)
 78 
 79 #define ALE_ALL_PORTS           0x7
 80 
 81 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
 82 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
 83 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
 84 
 85 #define CPSW_VERSION_1          0x19010a
 86 #define CPSW_VERSION_2          0x19010c
 87 #define CPSW_VERSION_3          0x19010f
 88 #define CPSW_VERSION_4          0x190112
 89 
 90 #define HOST_PORT_NUM           0
 91 #define SLIVER_SIZE             0x40
 92 
 93 #define CPSW1_HOST_PORT_OFFSET  0x028
 94 #define CPSW1_SLAVE_OFFSET      0x050
 95 #define CPSW1_SLAVE_SIZE        0x040
 96 #define CPSW1_CPDMA_OFFSET      0x100
 97 #define CPSW1_STATERAM_OFFSET   0x200
 98 #define CPSW1_HW_STATS          0x400
 99 #define CPSW1_CPTS_OFFSET       0x500
100 #define CPSW1_ALE_OFFSET        0x600
101 #define CPSW1_SLIVER_OFFSET     0x700
102 
103 #define CPSW2_HOST_PORT_OFFSET  0x108
104 #define CPSW2_SLAVE_OFFSET      0x200
105 #define CPSW2_SLAVE_SIZE        0x100
106 #define CPSW2_CPDMA_OFFSET      0x800
107 #define CPSW2_HW_STATS          0x900
108 #define CPSW2_STATERAM_OFFSET   0xa00
109 #define CPSW2_CPTS_OFFSET       0xc00
110 #define CPSW2_ALE_OFFSET        0xd00
111 #define CPSW2_SLIVER_OFFSET     0xd80
112 #define CPSW2_BD_OFFSET         0x2000
113 
114 #define CPDMA_RXTHRESH          0x0c0
115 #define CPDMA_RXFREE            0x0e0
116 #define CPDMA_TXHDP             0x00
117 #define CPDMA_RXHDP             0x20
118 #define CPDMA_TXCP              0x40
119 #define CPDMA_RXCP              0x60
120 
121 #define CPSW_POLL_WEIGHT        64
122 #define CPSW_MIN_PACKET_SIZE    60
123 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
124 
125 #define RX_PRIORITY_MAPPING     0x76543210
126 #define TX_PRIORITY_MAPPING     0x33221100
127 #define CPDMA_TX_PRIORITY_MAP   0x76543210
128 
129 #define CPSW_VLAN_AWARE         BIT(1)
130 #define CPSW_ALE_VLAN_AWARE     1
131 
132 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
133 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
134 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
135 
136 #define CPSW_INTPACEEN          (0x3f << 16)
137 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
138 #define CPSW_CMINTMAX_CNT       63
139 #define CPSW_CMINTMIN_CNT       2
140 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
141 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
142 
143 #define cpsw_slave_index(priv)                          \
144                 ((priv->data.dual_emac) ? priv->emac_port :     \
145                 priv->data.active_slave)
146 
147 static int debug_level;
148 module_param(debug_level, int, 0);
149 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
150 
151 static int ale_ageout = 10;
152 module_param(ale_ageout, int, 0);
153 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
154 
155 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
156 module_param(rx_packet_max, int, 0);
157 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
158 
159 struct cpsw_wr_regs {
160         u32     id_ver;
161         u32     soft_reset;
162         u32     control;
163         u32     int_control;
164         u32     rx_thresh_en;
165         u32     rx_en;
166         u32     tx_en;
167         u32     misc_en;
168         u32     mem_allign1[8];
169         u32     rx_thresh_stat;
170         u32     rx_stat;
171         u32     tx_stat;
172         u32     misc_stat;
173         u32     mem_allign2[8];
174         u32     rx_imax;
175         u32     tx_imax;
176 
177 };
178 
179 struct cpsw_ss_regs {
180         u32     id_ver;
181         u32     control;
182         u32     soft_reset;
183         u32     stat_port_en;
184         u32     ptype;
185         u32     soft_idle;
186         u32     thru_rate;
187         u32     gap_thresh;
188         u32     tx_start_wds;
189         u32     flow_control;
190         u32     vlan_ltype;
191         u32     ts_ltype;
192         u32     dlr_ltype;
193 };
194 
195 /* CPSW_PORT_V1 */
196 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
197 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
198 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
199 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
200 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
201 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
202 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
203 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
204 
205 /* CPSW_PORT_V2 */
206 #define CPSW2_CONTROL       0x00 /* Control Register */
207 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
208 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
209 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
210 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
211 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
212 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
213 
214 /* CPSW_PORT_V1 and V2 */
215 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
216 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
217 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
218 
219 /* CPSW_PORT_V2 only */
220 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
221 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
222 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
223 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
224 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
225 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
226 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
227 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
228 
229 /* Bit definitions for the CPSW2_CONTROL register */
230 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
231 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
232 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
233 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
234 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
235 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
236 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
237 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
238 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
239 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
240 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
241 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
242 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
243 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
244 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
245 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
246 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
247 
248 #define CTRL_V2_TS_BITS \
249         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
250          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
251 
252 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
253 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
254 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
255 
256 
257 #define CTRL_V3_TS_BITS \
258         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
259          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
260          TS_LTYPE1_EN)
261 
262 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
263 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
264 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
265 
266 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
267 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
268 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
269 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
270 #define TS_MSG_TYPE_EN_MASK      (0xffff)
271 
272 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
273 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
274 
275 /* Bit definitions for the CPSW1_TS_CTL register */
276 #define CPSW_V1_TS_RX_EN                BIT(0)
277 #define CPSW_V1_TS_TX_EN                BIT(4)
278 #define CPSW_V1_MSG_TYPE_OFS            16
279 
280 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
281 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
282 
283 struct cpsw_host_regs {
284         u32     max_blks;
285         u32     blk_cnt;
286         u32     tx_in_ctl;
287         u32     port_vlan;
288         u32     tx_pri_map;
289         u32     cpdma_tx_pri_map;
290         u32     cpdma_rx_chan_map;
291 };
292 
293 struct cpsw_sliver_regs {
294         u32     id_ver;
295         u32     mac_control;
296         u32     mac_status;
297         u32     soft_reset;
298         u32     rx_maxlen;
299         u32     __reserved_0;
300         u32     rx_pause;
301         u32     tx_pause;
302         u32     __reserved_1;
303         u32     rx_pri_map;
304 };
305 
306 struct cpsw_hw_stats {
307         u32     rxgoodframes;
308         u32     rxbroadcastframes;
309         u32     rxmulticastframes;
310         u32     rxpauseframes;
311         u32     rxcrcerrors;
312         u32     rxaligncodeerrors;
313         u32     rxoversizedframes;
314         u32     rxjabberframes;
315         u32     rxundersizedframes;
316         u32     rxfragments;
317         u32     __pad_0[2];
318         u32     rxoctets;
319         u32     txgoodframes;
320         u32     txbroadcastframes;
321         u32     txmulticastframes;
322         u32     txpauseframes;
323         u32     txdeferredframes;
324         u32     txcollisionframes;
325         u32     txsinglecollframes;
326         u32     txmultcollframes;
327         u32     txexcessivecollisions;
328         u32     txlatecollisions;
329         u32     txunderrun;
330         u32     txcarriersenseerrors;
331         u32     txoctets;
332         u32     octetframes64;
333         u32     octetframes65t127;
334         u32     octetframes128t255;
335         u32     octetframes256t511;
336         u32     octetframes512t1023;
337         u32     octetframes1024tup;
338         u32     netoctets;
339         u32     rxsofoverruns;
340         u32     rxmofoverruns;
341         u32     rxdmaoverruns;
342 };
343 
344 struct cpsw_slave {
345         void __iomem                    *regs;
346         struct cpsw_sliver_regs __iomem *sliver;
347         int                             slave_num;
348         u32                             mac_control;
349         struct cpsw_slave_data          *data;
350         struct phy_device               *phy;
351         struct net_device               *ndev;
352         u32                             port_vlan;
353         u32                             open_stat;
354 };
355 
356 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
357 {
358         return __raw_readl(slave->regs + offset);
359 }
360 
361 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
362 {
363         __raw_writel(val, slave->regs + offset);
364 }
365 
366 struct cpsw_priv {
367         spinlock_t                      lock;
368         struct platform_device          *pdev;
369         struct net_device               *ndev;
370         struct napi_struct              napi_rx;
371         struct napi_struct              napi_tx;
372         struct device                   *dev;
373         struct cpsw_platform_data       data;
374         struct cpsw_ss_regs __iomem     *regs;
375         struct cpsw_wr_regs __iomem     *wr_regs;
376         u8 __iomem                      *hw_stats;
377         struct cpsw_host_regs __iomem   *host_port_regs;
378         u32                             msg_enable;
379         u32                             version;
380         u32                             coal_intvl;
381         u32                             bus_freq_mhz;
382         int                             rx_packet_max;
383         int                             host_port;
384         struct clk                      *clk;
385         u8                              mac_addr[ETH_ALEN];
386         struct cpsw_slave               *slaves;
387         struct cpdma_ctlr               *dma;
388         struct cpdma_chan               *txch, *rxch;
389         struct cpsw_ale                 *ale;
390         bool                            rx_pause;
391         bool                            tx_pause;
392         bool                            quirk_irq;
393         bool                            rx_irq_disabled;
394         bool                            tx_irq_disabled;
395         /* snapshot of IRQ numbers */
396         u32 irqs_table[4];
397         u32 num_irqs;
398         struct cpts *cpts;
399         u32 emac_port;
400 };
401 
402 struct cpsw_stats {
403         char stat_string[ETH_GSTRING_LEN];
404         int type;
405         int sizeof_stat;
406         int stat_offset;
407 };
408 
409 enum {
410         CPSW_STATS,
411         CPDMA_RX_STATS,
412         CPDMA_TX_STATS,
413 };
414 
415 #define CPSW_STAT(m)            CPSW_STATS,                             \
416                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
417                                 offsetof(struct cpsw_hw_stats, m)
418 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
419                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
420                                 offsetof(struct cpdma_chan_stats, m)
421 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
422                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
423                                 offsetof(struct cpdma_chan_stats, m)
424 
425 static const struct cpsw_stats cpsw_gstrings_stats[] = {
426         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
427         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
428         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
429         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
430         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
431         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
432         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
433         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
434         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
435         { "Rx Fragments", CPSW_STAT(rxfragments) },
436         { "Rx Octets", CPSW_STAT(rxoctets) },
437         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
438         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
439         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
440         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
441         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
442         { "Collisions", CPSW_STAT(txcollisionframes) },
443         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
444         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
445         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
446         { "Late Collisions", CPSW_STAT(txlatecollisions) },
447         { "Tx Underrun", CPSW_STAT(txunderrun) },
448         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
449         { "Tx Octets", CPSW_STAT(txoctets) },
450         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
451         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
452         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
453         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
454         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
455         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
456         { "Net Octets", CPSW_STAT(netoctets) },
457         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
458         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
459         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
460         { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
461         { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
462         { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
463         { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
464         { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
465         { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
466         { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
467         { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
468         { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
469         { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
470         { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
471         { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
472         { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
473         { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
474         { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
475         { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
476         { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
477         { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
478         { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
479         { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
480         { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
481         { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
482         { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
483         { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
484         { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
485         { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
486 };
487 
488 #define CPSW_STATS_LEN  ARRAY_SIZE(cpsw_gstrings_stats)
489 
490 #define napi_to_priv(napi)      container_of(napi, struct cpsw_priv, napi)
491 #define for_each_slave(priv, func, arg...)                              \
492         do {                                                            \
493                 struct cpsw_slave *slave;                               \
494                 int n;                                                  \
495                 if (priv->data.dual_emac)                               \
496                         (func)((priv)->slaves + priv->emac_port, ##arg);\
497                 else                                                    \
498                         for (n = (priv)->data.slaves,                   \
499                                         slave = (priv)->slaves;         \
500                                         n; n--)                         \
501                                 (func)(slave++, ##arg);                 \
502         } while (0)
503 #define cpsw_get_slave_ndev(priv, __slave_no__)                         \
504         ((__slave_no__ < priv->data.slaves) ?                           \
505                 priv->slaves[__slave_no__].ndev : NULL)
506 #define cpsw_get_slave_priv(priv, __slave_no__)                         \
507         (((__slave_no__ < priv->data.slaves) &&                         \
508                 (priv->slaves[__slave_no__].ndev)) ?                    \
509                 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL)    \
510 
511 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb)         \
512         do {                                                            \
513                 if (!priv->data.dual_emac)                              \
514                         break;                                          \
515                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
516                         ndev = cpsw_get_slave_ndev(priv, 0);            \
517                         priv = netdev_priv(ndev);                       \
518                         skb->dev = ndev;                                \
519                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
520                         ndev = cpsw_get_slave_ndev(priv, 1);            \
521                         priv = netdev_priv(ndev);                       \
522                         skb->dev = ndev;                                \
523                 }                                                       \
524         } while (0)
525 #define cpsw_add_mcast(priv, addr)                                      \
526         do {                                                            \
527                 if (priv->data.dual_emac) {                             \
528                         struct cpsw_slave *slave = priv->slaves +       \
529                                                 priv->emac_port;        \
530                         int slave_port = cpsw_get_slave_port(priv,      \
531                                                 slave->slave_num);      \
532                         cpsw_ale_add_mcast(priv->ale, addr,             \
533                                 1 << slave_port | 1 << priv->host_port, \
534                                 ALE_VLAN, slave->port_vlan, 0);         \
535                 } else {                                                \
536                         cpsw_ale_add_mcast(priv->ale, addr,             \
537                                 ALE_ALL_PORTS << priv->host_port,       \
538                                 0, 0, 0);                               \
539                 }                                                       \
540         } while (0)
541 
542 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
543 {
544         if (priv->host_port == 0)
545                 return slave_num + 1;
546         else
547                 return slave_num;
548 }
549 
550 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
551 {
552         struct cpsw_priv *priv = netdev_priv(ndev);
553         struct cpsw_ale *ale = priv->ale;
554         int i;
555 
556         if (priv->data.dual_emac) {
557                 bool flag = false;
558 
559                 /* Enabling promiscuous mode for one interface will be
560                  * common for both the interface as the interface shares
561                  * the same hardware resource.
562                  */
563                 for (i = 0; i < priv->data.slaves; i++)
564                         if (priv->slaves[i].ndev->flags & IFF_PROMISC)
565                                 flag = true;
566 
567                 if (!enable && flag) {
568                         enable = true;
569                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
570                 }
571 
572                 if (enable) {
573                         /* Enable Bypass */
574                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
575 
576                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
577                 } else {
578                         /* Disable Bypass */
579                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
580                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
581                 }
582         } else {
583                 if (enable) {
584                         unsigned long timeout = jiffies + HZ;
585 
586                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
587                         for (i = 0; i <= priv->data.slaves; i++) {
588                                 cpsw_ale_control_set(ale, i,
589                                                      ALE_PORT_NOLEARN, 1);
590                                 cpsw_ale_control_set(ale, i,
591                                                      ALE_PORT_NO_SA_UPDATE, 1);
592                         }
593 
594                         /* Clear All Untouched entries */
595                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
596                         do {
597                                 cpu_relax();
598                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
599                                         break;
600                         } while (time_after(timeout, jiffies));
601                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
602 
603                         /* Clear all mcast from ALE */
604                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<
605                                                  priv->host_port, -1);
606 
607                         /* Flood All Unicast Packets to Host port */
608                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
609                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
610                 } else {
611                         /* Don't Flood All Unicast Packets to Host port */
612                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
613 
614                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
615                         for (i = 0; i <= priv->data.slaves; i++) {
616                                 cpsw_ale_control_set(ale, i,
617                                                      ALE_PORT_NOLEARN, 0);
618                                 cpsw_ale_control_set(ale, i,
619                                                      ALE_PORT_NO_SA_UPDATE, 0);
620                         }
621                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
622                 }
623         }
624 }
625 
626 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
627 {
628         struct cpsw_priv *priv = netdev_priv(ndev);
629         int vid;
630 
631         if (priv->data.dual_emac)
632                 vid = priv->slaves[priv->emac_port].port_vlan;
633         else
634                 vid = priv->data.default_vlan;
635 
636         if (ndev->flags & IFF_PROMISC) {
637                 /* Enable promiscuous mode */
638                 cpsw_set_promiscious(ndev, true);
639                 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
640                 return;
641         } else {
642                 /* Disable promiscuous mode */
643                 cpsw_set_promiscious(ndev, false);
644         }
645 
646         /* Restore allmulti on vlans if necessary */
647         cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
648 
649         /* Clear all mcast from ALE */
650         cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port,
651                                  vid);
652 
653         if (!netdev_mc_empty(ndev)) {
654                 struct netdev_hw_addr *ha;
655 
656                 /* program multicast address list into ALE register */
657                 netdev_for_each_mc_addr(ha, ndev) {
658                         cpsw_add_mcast(priv, (u8 *)ha->addr);
659                 }
660         }
661 }
662 
663 static void cpsw_intr_enable(struct cpsw_priv *priv)
664 {
665         __raw_writel(0xFF, &priv->wr_regs->tx_en);
666         __raw_writel(0xFF, &priv->wr_regs->rx_en);
667 
668         cpdma_ctlr_int_ctrl(priv->dma, true);
669         return;
670 }
671 
672 static void cpsw_intr_disable(struct cpsw_priv *priv)
673 {
674         __raw_writel(0, &priv->wr_regs->tx_en);
675         __raw_writel(0, &priv->wr_regs->rx_en);
676 
677         cpdma_ctlr_int_ctrl(priv->dma, false);
678         return;
679 }
680 
681 static void cpsw_tx_handler(void *token, int len, int status)
682 {
683         struct sk_buff          *skb = token;
684         struct net_device       *ndev = skb->dev;
685         struct cpsw_priv        *priv = netdev_priv(ndev);
686 
687         /* Check whether the queue is stopped due to stalled tx dma, if the
688          * queue is stopped then start the queue as we have free desc for tx
689          */
690         if (unlikely(netif_queue_stopped(ndev)))
691                 netif_wake_queue(ndev);
692         cpts_tx_timestamp(priv->cpts, skb);
693         ndev->stats.tx_packets++;
694         ndev->stats.tx_bytes += len;
695         dev_kfree_skb_any(skb);
696 }
697 
698 static void cpsw_rx_handler(void *token, int len, int status)
699 {
700         struct sk_buff          *skb = token;
701         struct sk_buff          *new_skb;
702         struct net_device       *ndev = skb->dev;
703         struct cpsw_priv        *priv = netdev_priv(ndev);
704         int                     ret = 0;
705 
706         cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
707 
708         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
709                 bool ndev_status = false;
710                 struct cpsw_slave *slave = priv->slaves;
711                 int n;
712 
713                 if (priv->data.dual_emac) {
714                         /* In dual emac mode check for all interfaces */
715                         for (n = priv->data.slaves; n; n--, slave++)
716                                 if (netif_running(slave->ndev))
717                                         ndev_status = true;
718                 }
719 
720                 if (ndev_status && (status >= 0)) {
721                         /* The packet received is for the interface which
722                          * is already down and the other interface is up
723                          * and running, instead of freeing which results
724                          * in reducing of the number of rx descriptor in
725                          * DMA engine, requeue skb back to cpdma.
726                          */
727                         new_skb = skb;
728                         goto requeue;
729                 }
730 
731                 /* the interface is going down, skbs are purged */
732                 dev_kfree_skb_any(skb);
733                 return;
734         }
735 
736         new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
737         if (new_skb) {
738                 skb_put(skb, len);
739                 cpts_rx_timestamp(priv->cpts, skb);
740                 skb->protocol = eth_type_trans(skb, ndev);
741                 netif_receive_skb(skb);
742                 ndev->stats.rx_bytes += len;
743                 ndev->stats.rx_packets++;
744         } else {
745                 ndev->stats.rx_dropped++;
746                 new_skb = skb;
747         }
748 
749 requeue:
750         ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
751                         skb_tailroom(new_skb), 0);
752         if (WARN_ON(ret < 0))
753                 dev_kfree_skb_any(new_skb);
754 }
755 
756 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
757 {
758         struct cpsw_priv *priv = dev_id;
759 
760         writel(0, &priv->wr_regs->tx_en);
761         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
762 
763         if (priv->quirk_irq) {
764                 disable_irq_nosync(priv->irqs_table[1]);
765                 priv->tx_irq_disabled = true;
766         }
767 
768         napi_schedule(&priv->napi_tx);
769         return IRQ_HANDLED;
770 }
771 
772 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
773 {
774         struct cpsw_priv *priv = dev_id;
775 
776         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
777         writel(0, &priv->wr_regs->rx_en);
778 
779         if (priv->quirk_irq) {
780                 disable_irq_nosync(priv->irqs_table[0]);
781                 priv->rx_irq_disabled = true;
782         }
783 
784         napi_schedule(&priv->napi_rx);
785         return IRQ_HANDLED;
786 }
787 
788 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
789 {
790         struct cpsw_priv        *priv = napi_to_priv(napi_tx);
791         int                     num_tx;
792 
793         num_tx = cpdma_chan_process(priv->txch, budget);
794         if (num_tx < budget) {
795                 napi_complete(napi_tx);
796                 writel(0xff, &priv->wr_regs->tx_en);
797                 if (priv->quirk_irq && priv->tx_irq_disabled) {
798                         priv->tx_irq_disabled = false;
799                         enable_irq(priv->irqs_table[1]);
800                 }
801         }
802 
803         if (num_tx)
804                 cpsw_dbg(priv, intr, "poll %d tx pkts\n", num_tx);
805 
806         return num_tx;
807 }
808 
809 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
810 {
811         struct cpsw_priv        *priv = napi_to_priv(napi_rx);
812         int                     num_rx;
813 
814         num_rx = cpdma_chan_process(priv->rxch, budget);
815         if (num_rx < budget) {
816                 napi_complete(napi_rx);
817                 writel(0xff, &priv->wr_regs->rx_en);
818                 if (priv->quirk_irq && priv->rx_irq_disabled) {
819                         priv->rx_irq_disabled = false;
820                         enable_irq(priv->irqs_table[0]);
821                 }
822         }
823 
824         if (num_rx)
825                 cpsw_dbg(priv, intr, "poll %d rx pkts\n", num_rx);
826 
827         return num_rx;
828 }
829 
830 static inline void soft_reset(const char *module, void __iomem *reg)
831 {
832         unsigned long timeout = jiffies + HZ;
833 
834         __raw_writel(1, reg);
835         do {
836                 cpu_relax();
837         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
838 
839         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
840 }
841 
842 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
843                          ((mac)[2] << 16) | ((mac)[3] << 24))
844 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
845 
846 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
847                                struct cpsw_priv *priv)
848 {
849         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
850         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
851 }
852 
853 static void _cpsw_adjust_link(struct cpsw_slave *slave,
854                               struct cpsw_priv *priv, bool *link)
855 {
856         struct phy_device       *phy = slave->phy;
857         u32                     mac_control = 0;
858         u32                     slave_port;
859 
860         if (!phy)
861                 return;
862 
863         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
864 
865         if (phy->link) {
866                 mac_control = priv->data.mac_control;
867 
868                 /* enable forwarding */
869                 cpsw_ale_control_set(priv->ale, slave_port,
870                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
871 
872                 if (phy->speed == 1000)
873                         mac_control |= BIT(7);  /* GIGABITEN    */
874                 if (phy->duplex)
875                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
876 
877                 /* set speed_in input in case RMII mode is used in 100Mbps */
878                 if (phy->speed == 100)
879                         mac_control |= BIT(15);
880                 else if (phy->speed == 10)
881                         mac_control |= BIT(18); /* In Band mode */
882 
883                 if (priv->rx_pause)
884                         mac_control |= BIT(3);
885 
886                 if (priv->tx_pause)
887                         mac_control |= BIT(4);
888 
889                 *link = true;
890         } else {
891                 mac_control = 0;
892                 /* disable forwarding */
893                 cpsw_ale_control_set(priv->ale, slave_port,
894                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
895         }
896 
897         if (mac_control != slave->mac_control) {
898                 phy_print_status(phy);
899                 __raw_writel(mac_control, &slave->sliver->mac_control);
900         }
901 
902         slave->mac_control = mac_control;
903 }
904 
905 static void cpsw_adjust_link(struct net_device *ndev)
906 {
907         struct cpsw_priv        *priv = netdev_priv(ndev);
908         bool                    link = false;
909 
910         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
911 
912         if (link) {
913                 netif_carrier_on(ndev);
914                 if (netif_running(ndev))
915                         netif_wake_queue(ndev);
916         } else {
917                 netif_carrier_off(ndev);
918                 netif_stop_queue(ndev);
919         }
920 }
921 
922 static int cpsw_get_coalesce(struct net_device *ndev,
923                                 struct ethtool_coalesce *coal)
924 {
925         struct cpsw_priv *priv = netdev_priv(ndev);
926 
927         coal->rx_coalesce_usecs = priv->coal_intvl;
928         return 0;
929 }
930 
931 static int cpsw_set_coalesce(struct net_device *ndev,
932                                 struct ethtool_coalesce *coal)
933 {
934         struct cpsw_priv *priv = netdev_priv(ndev);
935         u32 int_ctrl;
936         u32 num_interrupts = 0;
937         u32 prescale = 0;
938         u32 addnl_dvdr = 1;
939         u32 coal_intvl = 0;
940 
941         coal_intvl = coal->rx_coalesce_usecs;
942 
943         int_ctrl =  readl(&priv->wr_regs->int_control);
944         prescale = priv->bus_freq_mhz * 4;
945 
946         if (!coal->rx_coalesce_usecs) {
947                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
948                 goto update_return;
949         }
950 
951         if (coal_intvl < CPSW_CMINTMIN_INTVL)
952                 coal_intvl = CPSW_CMINTMIN_INTVL;
953 
954         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
955                 /* Interrupt pacer works with 4us Pulse, we can
956                  * throttle further by dilating the 4us pulse.
957                  */
958                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
959 
960                 if (addnl_dvdr > 1) {
961                         prescale *= addnl_dvdr;
962                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
963                                 coal_intvl = (CPSW_CMINTMAX_INTVL
964                                                 * addnl_dvdr);
965                 } else {
966                         addnl_dvdr = 1;
967                         coal_intvl = CPSW_CMINTMAX_INTVL;
968                 }
969         }
970 
971         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
972         writel(num_interrupts, &priv->wr_regs->rx_imax);
973         writel(num_interrupts, &priv->wr_regs->tx_imax);
974 
975         int_ctrl |= CPSW_INTPACEEN;
976         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
977         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
978 
979 update_return:
980         writel(int_ctrl, &priv->wr_regs->int_control);
981 
982         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
983         if (priv->data.dual_emac) {
984                 int i;
985 
986                 for (i = 0; i < priv->data.slaves; i++) {
987                         priv = netdev_priv(priv->slaves[i].ndev);
988                         priv->coal_intvl = coal_intvl;
989                 }
990         } else {
991                 priv->coal_intvl = coal_intvl;
992         }
993 
994         return 0;
995 }
996 
997 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
998 {
999         switch (sset) {
1000         case ETH_SS_STATS:
1001                 return CPSW_STATS_LEN;
1002         default:
1003                 return -EOPNOTSUPP;
1004         }
1005 }
1006 
1007 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1008 {
1009         u8 *p = data;
1010         int i;
1011 
1012         switch (stringset) {
1013         case ETH_SS_STATS:
1014                 for (i = 0; i < CPSW_STATS_LEN; i++) {
1015                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
1016                                ETH_GSTRING_LEN);
1017                         p += ETH_GSTRING_LEN;
1018                 }
1019                 break;
1020         }
1021 }
1022 
1023 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1024                                     struct ethtool_stats *stats, u64 *data)
1025 {
1026         struct cpsw_priv *priv = netdev_priv(ndev);
1027         struct cpdma_chan_stats rx_stats;
1028         struct cpdma_chan_stats tx_stats;
1029         u32 val;
1030         u8 *p;
1031         int i;
1032 
1033         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1034         cpdma_chan_get_stats(priv->rxch, &rx_stats);
1035         cpdma_chan_get_stats(priv->txch, &tx_stats);
1036 
1037         for (i = 0; i < CPSW_STATS_LEN; i++) {
1038                 switch (cpsw_gstrings_stats[i].type) {
1039                 case CPSW_STATS:
1040                         val = readl(priv->hw_stats +
1041                                     cpsw_gstrings_stats[i].stat_offset);
1042                         data[i] = val;
1043                         break;
1044 
1045                 case CPDMA_RX_STATS:
1046                         p = (u8 *)&rx_stats +
1047                                 cpsw_gstrings_stats[i].stat_offset;
1048                         data[i] = *(u32 *)p;
1049                         break;
1050 
1051                 case CPDMA_TX_STATS:
1052                         p = (u8 *)&tx_stats +
1053                                 cpsw_gstrings_stats[i].stat_offset;
1054                         data[i] = *(u32 *)p;
1055                         break;
1056                 }
1057         }
1058 }
1059 
1060 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1061 {
1062         u32 i;
1063         u32 usage_count = 0;
1064 
1065         if (!priv->data.dual_emac)
1066                 return 0;
1067 
1068         for (i = 0; i < priv->data.slaves; i++)
1069                 if (priv->slaves[i].open_stat)
1070                         usage_count++;
1071 
1072         return usage_count;
1073 }
1074 
1075 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1076                         struct cpsw_priv *priv, struct sk_buff *skb)
1077 {
1078         if (!priv->data.dual_emac)
1079                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1080                                   skb->len, 0);
1081 
1082         if (ndev == cpsw_get_slave_ndev(priv, 0))
1083                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1084                                   skb->len, 1);
1085         else
1086                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1087                                   skb->len, 2);
1088 }
1089 
1090 static inline void cpsw_add_dual_emac_def_ale_entries(
1091                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1092                 u32 slave_port)
1093 {
1094         u32 port_mask = 1 << slave_port | 1 << priv->host_port;
1095 
1096         if (priv->version == CPSW_VERSION_1)
1097                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1098         else
1099                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1100         cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1101                           port_mask, port_mask, 0);
1102         cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1103                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1104         cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1105                 priv->host_port, ALE_VLAN | ALE_SECURE, slave->port_vlan);
1106 }
1107 
1108 static void soft_reset_slave(struct cpsw_slave *slave)
1109 {
1110         char name[32];
1111 
1112         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1113         soft_reset(name, &slave->sliver->soft_reset);
1114 }
1115 
1116 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1117 {
1118         u32 slave_port;
1119 
1120         soft_reset_slave(slave);
1121 
1122         /* setup priority mapping */
1123         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1124 
1125         switch (priv->version) {
1126         case CPSW_VERSION_1:
1127                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1128                 break;
1129         case CPSW_VERSION_2:
1130         case CPSW_VERSION_3:
1131         case CPSW_VERSION_4:
1132                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1133                 break;
1134         }
1135 
1136         /* setup max packet size, and mac address */
1137         __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1138         cpsw_set_slave_mac(slave, priv);
1139 
1140         slave->mac_control = 0; /* no link yet */
1141 
1142         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1143 
1144         if (priv->data.dual_emac)
1145                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1146         else
1147                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1148                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1149 
1150         if (slave->data->phy_node) {
1151                 slave->phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1152                                  &cpsw_adjust_link, 0, slave->data->phy_if);
1153                 if (!slave->phy) {
1154                         dev_err(priv->dev, "phy \"%s\" not found on slave %d\n",
1155                                 slave->data->phy_node->full_name,
1156                                 slave->slave_num);
1157                         return;
1158                 }
1159         } else {
1160                 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1161                                  &cpsw_adjust_link, slave->data->phy_if);
1162                 if (IS_ERR(slave->phy)) {
1163                         dev_err(priv->dev,
1164                                 "phy \"%s\" not found on slave %d, err %ld\n",
1165                                 slave->data->phy_id, slave->slave_num,
1166                                 PTR_ERR(slave->phy));
1167                         slave->phy = NULL;
1168                         return;
1169                 }
1170         }
1171 
1172         phy_attached_info(slave->phy);
1173 
1174         phy_start(slave->phy);
1175 
1176         /* Configure GMII_SEL register */
1177         cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface, slave->slave_num);
1178 }
1179 
1180 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1181 {
1182         const int vlan = priv->data.default_vlan;
1183         const int port = priv->host_port;
1184         u32 reg;
1185         int i;
1186         int unreg_mcast_mask;
1187 
1188         reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1189                CPSW2_PORT_VLAN;
1190 
1191         writel(vlan, &priv->host_port_regs->port_vlan);
1192 
1193         for (i = 0; i < priv->data.slaves; i++)
1194                 slave_write(priv->slaves + i, vlan, reg);
1195 
1196         if (priv->ndev->flags & IFF_ALLMULTI)
1197                 unreg_mcast_mask = ALE_ALL_PORTS;
1198         else
1199                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1200 
1201         cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1202                           ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1203                           unreg_mcast_mask << port);
1204 }
1205 
1206 static void cpsw_init_host_port(struct cpsw_priv *priv)
1207 {
1208         u32 control_reg;
1209         u32 fifo_mode;
1210 
1211         /* soft reset the controller and initialize ale */
1212         soft_reset("cpsw", &priv->regs->soft_reset);
1213         cpsw_ale_start(priv->ale);
1214 
1215         /* switch to vlan unaware mode */
1216         cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1217                              CPSW_ALE_VLAN_AWARE);
1218         control_reg = readl(&priv->regs->control);
1219         control_reg |= CPSW_VLAN_AWARE;
1220         writel(control_reg, &priv->regs->control);
1221         fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1222                      CPSW_FIFO_NORMAL_MODE;
1223         writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
1224 
1225         /* setup host port priority mapping */
1226         __raw_writel(CPDMA_TX_PRIORITY_MAP,
1227                      &priv->host_port_regs->cpdma_tx_pri_map);
1228         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1229 
1230         cpsw_ale_control_set(priv->ale, priv->host_port,
1231                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1232 
1233         if (!priv->data.dual_emac) {
1234                 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1235                                    0, 0);
1236                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1237                                    1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1238         }
1239 }
1240 
1241 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1242 {
1243         u32 slave_port;
1244 
1245         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1246 
1247         if (!slave->phy)
1248                 return;
1249         phy_stop(slave->phy);
1250         phy_disconnect(slave->phy);
1251         slave->phy = NULL;
1252         cpsw_ale_control_set(priv->ale, slave_port,
1253                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1254 }
1255 
1256 static int cpsw_ndo_open(struct net_device *ndev)
1257 {
1258         struct cpsw_priv *priv = netdev_priv(ndev);
1259         int i, ret;
1260         u32 reg;
1261 
1262         pm_runtime_get_sync(&priv->pdev->dev);
1263 
1264         if (!cpsw_common_res_usage_state(priv))
1265                 cpsw_intr_disable(priv);
1266         netif_carrier_off(ndev);
1267 
1268         reg = priv->version;
1269 
1270         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1271                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1272                  CPSW_RTL_VERSION(reg));
1273 
1274         /* initialize host and slave ports */
1275         if (!cpsw_common_res_usage_state(priv))
1276                 cpsw_init_host_port(priv);
1277         for_each_slave(priv, cpsw_slave_open, priv);
1278 
1279         /* Add default VLAN */
1280         if (!priv->data.dual_emac)
1281                 cpsw_add_default_vlan(priv);
1282         else
1283                 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1284                                   ALE_ALL_PORTS << priv->host_port,
1285                                   ALE_ALL_PORTS << priv->host_port, 0, 0);
1286 
1287         if (!cpsw_common_res_usage_state(priv)) {
1288                 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1289 
1290                 /* setup tx dma to fixed prio and zero offset */
1291                 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1292                 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1293 
1294                 /* disable priority elevation */
1295                 __raw_writel(0, &priv->regs->ptype);
1296 
1297                 /* enable statistics collection only on all ports */
1298                 __raw_writel(0x7, &priv->regs->stat_port_en);
1299 
1300                 /* Enable internal fifo flow control */
1301                 writel(0x7, &priv->regs->flow_control);
1302 
1303                 napi_enable(&priv_sl0->napi_rx);
1304                 napi_enable(&priv_sl0->napi_tx);
1305 
1306                 if (priv_sl0->tx_irq_disabled) {
1307                         priv_sl0->tx_irq_disabled = false;
1308                         enable_irq(priv->irqs_table[1]);
1309                 }
1310 
1311                 if (priv_sl0->rx_irq_disabled) {
1312                         priv_sl0->rx_irq_disabled = false;
1313                         enable_irq(priv->irqs_table[0]);
1314                 }
1315 
1316                 if (WARN_ON(!priv->data.rx_descs))
1317                         priv->data.rx_descs = 128;
1318 
1319                 for (i = 0; i < priv->data.rx_descs; i++) {
1320                         struct sk_buff *skb;
1321 
1322                         ret = -ENOMEM;
1323                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1324                                         priv->rx_packet_max, GFP_KERNEL);
1325                         if (!skb)
1326                                 goto err_cleanup;
1327                         ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
1328                                         skb_tailroom(skb), 0);
1329                         if (ret < 0) {
1330                                 kfree_skb(skb);
1331                                 goto err_cleanup;
1332                         }
1333                 }
1334                 /* continue even if we didn't manage to submit all
1335                  * receive descs
1336                  */
1337                 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
1338 
1339                 if (cpts_register(&priv->pdev->dev, priv->cpts,
1340                                   priv->data.cpts_clock_mult,
1341                                   priv->data.cpts_clock_shift))
1342                         dev_err(priv->dev, "error registering cpts device\n");
1343 
1344         }
1345 
1346         /* Enable Interrupt pacing if configured */
1347         if (priv->coal_intvl != 0) {
1348                 struct ethtool_coalesce coal;
1349 
1350                 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1351                 cpsw_set_coalesce(ndev, &coal);
1352         }
1353 
1354         cpdma_ctlr_start(priv->dma);
1355         cpsw_intr_enable(priv);
1356 
1357         if (priv->data.dual_emac)
1358                 priv->slaves[priv->emac_port].open_stat = true;
1359         return 0;
1360 
1361 err_cleanup:
1362         cpdma_ctlr_stop(priv->dma);
1363         for_each_slave(priv, cpsw_slave_stop, priv);
1364         pm_runtime_put_sync(&priv->pdev->dev);
1365         netif_carrier_off(priv->ndev);
1366         return ret;
1367 }
1368 
1369 static int cpsw_ndo_stop(struct net_device *ndev)
1370 {
1371         struct cpsw_priv *priv = netdev_priv(ndev);
1372 
1373         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1374         netif_stop_queue(priv->ndev);
1375         netif_carrier_off(priv->ndev);
1376 
1377         if (cpsw_common_res_usage_state(priv) <= 1) {
1378                 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1379 
1380                 napi_disable(&priv_sl0->napi_rx);
1381                 napi_disable(&priv_sl0->napi_tx);
1382                 cpts_unregister(priv->cpts);
1383                 cpsw_intr_disable(priv);
1384                 cpdma_ctlr_stop(priv->dma);
1385                 cpsw_ale_stop(priv->ale);
1386         }
1387         for_each_slave(priv, cpsw_slave_stop, priv);
1388         pm_runtime_put_sync(&priv->pdev->dev);
1389         if (priv->data.dual_emac)
1390                 priv->slaves[priv->emac_port].open_stat = false;
1391         return 0;
1392 }
1393 
1394 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1395                                        struct net_device *ndev)
1396 {
1397         struct cpsw_priv *priv = netdev_priv(ndev);
1398         int ret;
1399 
1400         ndev->trans_start = jiffies;
1401 
1402         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1403                 cpsw_err(priv, tx_err, "packet pad failed\n");
1404                 ndev->stats.tx_dropped++;
1405                 return NETDEV_TX_OK;
1406         }
1407 
1408         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1409                                 priv->cpts->tx_enable)
1410                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1411 
1412         skb_tx_timestamp(skb);
1413 
1414         ret = cpsw_tx_packet_submit(ndev, priv, skb);
1415         if (unlikely(ret != 0)) {
1416                 cpsw_err(priv, tx_err, "desc submit failed\n");
1417                 goto fail;
1418         }
1419 
1420         /* If there is no more tx desc left free then we need to
1421          * tell the kernel to stop sending us tx frames.
1422          */
1423         if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1424                 netif_stop_queue(ndev);
1425 
1426         return NETDEV_TX_OK;
1427 fail:
1428         ndev->stats.tx_dropped++;
1429         netif_stop_queue(ndev);
1430         return NETDEV_TX_BUSY;
1431 }
1432 
1433 #ifdef CONFIG_TI_CPTS
1434 
1435 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1436 {
1437         struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1438         u32 ts_en, seq_id;
1439 
1440         if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1441                 slave_write(slave, 0, CPSW1_TS_CTL);
1442                 return;
1443         }
1444 
1445         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1446         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1447 
1448         if (priv->cpts->tx_enable)
1449                 ts_en |= CPSW_V1_TS_TX_EN;
1450 
1451         if (priv->cpts->rx_enable)
1452                 ts_en |= CPSW_V1_TS_RX_EN;
1453 
1454         slave_write(slave, ts_en, CPSW1_TS_CTL);
1455         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1456 }
1457 
1458 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1459 {
1460         struct cpsw_slave *slave;
1461         u32 ctrl, mtype;
1462 
1463         if (priv->data.dual_emac)
1464                 slave = &priv->slaves[priv->emac_port];
1465         else
1466                 slave = &priv->slaves[priv->data.active_slave];
1467 
1468         ctrl = slave_read(slave, CPSW2_CONTROL);
1469         switch (priv->version) {
1470         case CPSW_VERSION_2:
1471                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1472 
1473                 if (priv->cpts->tx_enable)
1474                         ctrl |= CTRL_V2_TX_TS_BITS;
1475 
1476                 if (priv->cpts->rx_enable)
1477                         ctrl |= CTRL_V2_RX_TS_BITS;
1478                 break;
1479         case CPSW_VERSION_3:
1480         default:
1481                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1482 
1483                 if (priv->cpts->tx_enable)
1484                         ctrl |= CTRL_V3_TX_TS_BITS;
1485 
1486                 if (priv->cpts->rx_enable)
1487                         ctrl |= CTRL_V3_RX_TS_BITS;
1488                 break;
1489         }
1490 
1491         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1492 
1493         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1494         slave_write(slave, ctrl, CPSW2_CONTROL);
1495         __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1496 }
1497 
1498 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1499 {
1500         struct cpsw_priv *priv = netdev_priv(dev);
1501         struct cpts *cpts = priv->cpts;
1502         struct hwtstamp_config cfg;
1503 
1504         if (priv->version != CPSW_VERSION_1 &&
1505             priv->version != CPSW_VERSION_2 &&
1506             priv->version != CPSW_VERSION_3)
1507                 return -EOPNOTSUPP;
1508 
1509         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1510                 return -EFAULT;
1511 
1512         /* reserved for future extensions */
1513         if (cfg.flags)
1514                 return -EINVAL;
1515 
1516         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1517                 return -ERANGE;
1518 
1519         switch (cfg.rx_filter) {
1520         case HWTSTAMP_FILTER_NONE:
1521                 cpts->rx_enable = 0;
1522                 break;
1523         case HWTSTAMP_FILTER_ALL:
1524         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1525         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1526         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1527                 return -ERANGE;
1528         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1529         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1530         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1531         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1532         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1533         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1534         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1535         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1536         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1537                 cpts->rx_enable = 1;
1538                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1539                 break;
1540         default:
1541                 return -ERANGE;
1542         }
1543 
1544         cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1545 
1546         switch (priv->version) {
1547         case CPSW_VERSION_1:
1548                 cpsw_hwtstamp_v1(priv);
1549                 break;
1550         case CPSW_VERSION_2:
1551         case CPSW_VERSION_3:
1552                 cpsw_hwtstamp_v2(priv);
1553                 break;
1554         default:
1555                 WARN_ON(1);
1556         }
1557 
1558         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1559 }
1560 
1561 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1562 {
1563         struct cpsw_priv *priv = netdev_priv(dev);
1564         struct cpts *cpts = priv->cpts;
1565         struct hwtstamp_config cfg;
1566 
1567         if (priv->version != CPSW_VERSION_1 &&
1568             priv->version != CPSW_VERSION_2 &&
1569             priv->version != CPSW_VERSION_3)
1570                 return -EOPNOTSUPP;
1571 
1572         cfg.flags = 0;
1573         cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1574         cfg.rx_filter = (cpts->rx_enable ?
1575                          HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1576 
1577         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1578 }
1579 
1580 #endif /*CONFIG_TI_CPTS*/
1581 
1582 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1583 {
1584         struct cpsw_priv *priv = netdev_priv(dev);
1585         int slave_no = cpsw_slave_index(priv);
1586 
1587         if (!netif_running(dev))
1588                 return -EINVAL;
1589 
1590         switch (cmd) {
1591 #ifdef CONFIG_TI_CPTS
1592         case SIOCSHWTSTAMP:
1593                 return cpsw_hwtstamp_set(dev, req);
1594         case SIOCGHWTSTAMP:
1595                 return cpsw_hwtstamp_get(dev, req);
1596 #endif
1597         }
1598 
1599         if (!priv->slaves[slave_no].phy)
1600                 return -EOPNOTSUPP;
1601         return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
1602 }
1603 
1604 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1605 {
1606         struct cpsw_priv *priv = netdev_priv(ndev);
1607 
1608         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1609         ndev->stats.tx_errors++;
1610         cpsw_intr_disable(priv);
1611         cpdma_chan_stop(priv->txch);
1612         cpdma_chan_start(priv->txch);
1613         cpsw_intr_enable(priv);
1614 }
1615 
1616 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1617 {
1618         struct cpsw_priv *priv = netdev_priv(ndev);
1619         struct sockaddr *addr = (struct sockaddr *)p;
1620         int flags = 0;
1621         u16 vid = 0;
1622 
1623         if (!is_valid_ether_addr(addr->sa_data))
1624                 return -EADDRNOTAVAIL;
1625 
1626         if (priv->data.dual_emac) {
1627                 vid = priv->slaves[priv->emac_port].port_vlan;
1628                 flags = ALE_VLAN;
1629         }
1630 
1631         cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1632                            flags, vid);
1633         cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1634                            flags, vid);
1635 
1636         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1637         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1638         for_each_slave(priv, cpsw_set_slave_mac, priv);
1639 
1640         return 0;
1641 }
1642 
1643 #ifdef CONFIG_NET_POLL_CONTROLLER
1644 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1645 {
1646         struct cpsw_priv *priv = netdev_priv(ndev);
1647 
1648         cpsw_intr_disable(priv);
1649         cpsw_rx_interrupt(priv->irqs_table[0], priv);
1650         cpsw_tx_interrupt(priv->irqs_table[1], priv);
1651         cpsw_intr_enable(priv);
1652 }
1653 #endif
1654 
1655 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1656                                 unsigned short vid)
1657 {
1658         int ret;
1659         int unreg_mcast_mask = 0;
1660         u32 port_mask;
1661 
1662         if (priv->data.dual_emac) {
1663                 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1664 
1665                 if (priv->ndev->flags & IFF_ALLMULTI)
1666                         unreg_mcast_mask = port_mask;
1667         } else {
1668                 port_mask = ALE_ALL_PORTS;
1669 
1670                 if (priv->ndev->flags & IFF_ALLMULTI)
1671                         unreg_mcast_mask = ALE_ALL_PORTS;
1672                 else
1673                         unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1674         }
1675 
1676         ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask,
1677                                 unreg_mcast_mask << priv->host_port);
1678         if (ret != 0)
1679                 return ret;
1680 
1681         ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1682                                  priv->host_port, ALE_VLAN, vid);
1683         if (ret != 0)
1684                 goto clean_vid;
1685 
1686         ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1687                                  port_mask, ALE_VLAN, vid, 0);
1688         if (ret != 0)
1689                 goto clean_vlan_ucast;
1690         return 0;
1691 
1692 clean_vlan_ucast:
1693         cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1694                             priv->host_port, ALE_VLAN, vid);
1695 clean_vid:
1696         cpsw_ale_del_vlan(priv->ale, vid, 0);
1697         return ret;
1698 }
1699 
1700 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1701                                     __be16 proto, u16 vid)
1702 {
1703         struct cpsw_priv *priv = netdev_priv(ndev);
1704 
1705         if (vid == priv->data.default_vlan)
1706                 return 0;
1707 
1708         if (priv->data.dual_emac) {
1709                 /* In dual EMAC, reserved VLAN id should not be used for
1710                  * creating VLAN interfaces as this can break the dual
1711                  * EMAC port separation
1712                  */
1713                 int i;
1714 
1715                 for (i = 0; i < priv->data.slaves; i++) {
1716                         if (vid == priv->slaves[i].port_vlan)
1717                                 return -EINVAL;
1718                 }
1719         }
1720 
1721         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1722         return cpsw_add_vlan_ale_entry(priv, vid);
1723 }
1724 
1725 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1726                                      __be16 proto, u16 vid)
1727 {
1728         struct cpsw_priv *priv = netdev_priv(ndev);
1729         int ret;
1730 
1731         if (vid == priv->data.default_vlan)
1732                 return 0;
1733 
1734         if (priv->data.dual_emac) {
1735                 int i;
1736 
1737                 for (i = 0; i < priv->data.slaves; i++) {
1738                         if (vid == priv->slaves[i].port_vlan)
1739                                 return -EINVAL;
1740                 }
1741         }
1742 
1743         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1744         ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1745         if (ret != 0)
1746                 return ret;
1747 
1748         ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1749                                  priv->host_port, ALE_VLAN, vid);
1750         if (ret != 0)
1751                 return ret;
1752 
1753         return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1754                                   0, ALE_VLAN, vid);
1755 }
1756 
1757 static const struct net_device_ops cpsw_netdev_ops = {
1758         .ndo_open               = cpsw_ndo_open,
1759         .ndo_stop               = cpsw_ndo_stop,
1760         .ndo_start_xmit         = cpsw_ndo_start_xmit,
1761         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
1762         .ndo_do_ioctl           = cpsw_ndo_ioctl,
1763         .ndo_validate_addr      = eth_validate_addr,
1764         .ndo_change_mtu         = eth_change_mtu,
1765         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
1766         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
1767 #ifdef CONFIG_NET_POLL_CONTROLLER
1768         .ndo_poll_controller    = cpsw_ndo_poll_controller,
1769 #endif
1770         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
1771         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
1772 };
1773 
1774 static int cpsw_get_regs_len(struct net_device *ndev)
1775 {
1776         struct cpsw_priv *priv = netdev_priv(ndev);
1777 
1778         return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1779 }
1780 
1781 static void cpsw_get_regs(struct net_device *ndev,
1782                           struct ethtool_regs *regs, void *p)
1783 {
1784         struct cpsw_priv *priv = netdev_priv(ndev);
1785         u32 *reg = p;
1786 
1787         /* update CPSW IP version */
1788         regs->version = priv->version;
1789 
1790         cpsw_ale_dump(priv->ale, reg);
1791 }
1792 
1793 static void cpsw_get_drvinfo(struct net_device *ndev,
1794                              struct ethtool_drvinfo *info)
1795 {
1796         struct cpsw_priv *priv = netdev_priv(ndev);
1797 
1798         strlcpy(info->driver, "cpsw", sizeof(info->driver));
1799         strlcpy(info->version, "1.0", sizeof(info->version));
1800         strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1801 }
1802 
1803 static u32 cpsw_get_msglevel(struct net_device *ndev)
1804 {
1805         struct cpsw_priv *priv = netdev_priv(ndev);
1806         return priv->msg_enable;
1807 }
1808 
1809 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1810 {
1811         struct cpsw_priv *priv = netdev_priv(ndev);
1812         priv->msg_enable = value;
1813 }
1814 
1815 static int cpsw_get_ts_info(struct net_device *ndev,
1816                             struct ethtool_ts_info *info)
1817 {
1818 #ifdef CONFIG_TI_CPTS
1819         struct cpsw_priv *priv = netdev_priv(ndev);
1820 
1821         info->so_timestamping =
1822                 SOF_TIMESTAMPING_TX_HARDWARE |
1823                 SOF_TIMESTAMPING_TX_SOFTWARE |
1824                 SOF_TIMESTAMPING_RX_HARDWARE |
1825                 SOF_TIMESTAMPING_RX_SOFTWARE |
1826                 SOF_TIMESTAMPING_SOFTWARE |
1827                 SOF_TIMESTAMPING_RAW_HARDWARE;
1828         info->phc_index = priv->cpts->phc_index;
1829         info->tx_types =
1830                 (1 << HWTSTAMP_TX_OFF) |
1831                 (1 << HWTSTAMP_TX_ON);
1832         info->rx_filters =
1833                 (1 << HWTSTAMP_FILTER_NONE) |
1834                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1835 #else
1836         info->so_timestamping =
1837                 SOF_TIMESTAMPING_TX_SOFTWARE |
1838                 SOF_TIMESTAMPING_RX_SOFTWARE |
1839                 SOF_TIMESTAMPING_SOFTWARE;
1840         info->phc_index = -1;
1841         info->tx_types = 0;
1842         info->rx_filters = 0;
1843 #endif
1844         return 0;
1845 }
1846 
1847 static int cpsw_get_settings(struct net_device *ndev,
1848                              struct ethtool_cmd *ecmd)
1849 {
1850         struct cpsw_priv *priv = netdev_priv(ndev);
1851         int slave_no = cpsw_slave_index(priv);
1852 
1853         if (priv->slaves[slave_no].phy)
1854                 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1855         else
1856                 return -EOPNOTSUPP;
1857 }
1858 
1859 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1860 {
1861         struct cpsw_priv *priv = netdev_priv(ndev);
1862         int slave_no = cpsw_slave_index(priv);
1863 
1864         if (priv->slaves[slave_no].phy)
1865                 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1866         else
1867                 return -EOPNOTSUPP;
1868 }
1869 
1870 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1871 {
1872         struct cpsw_priv *priv = netdev_priv(ndev);
1873         int slave_no = cpsw_slave_index(priv);
1874 
1875         wol->supported = 0;
1876         wol->wolopts = 0;
1877 
1878         if (priv->slaves[slave_no].phy)
1879                 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1880 }
1881 
1882 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1883 {
1884         struct cpsw_priv *priv = netdev_priv(ndev);
1885         int slave_no = cpsw_slave_index(priv);
1886 
1887         if (priv->slaves[slave_no].phy)
1888                 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1889         else
1890                 return -EOPNOTSUPP;
1891 }
1892 
1893 static void cpsw_get_pauseparam(struct net_device *ndev,
1894                                 struct ethtool_pauseparam *pause)
1895 {
1896         struct cpsw_priv *priv = netdev_priv(ndev);
1897 
1898         pause->autoneg = AUTONEG_DISABLE;
1899         pause->rx_pause = priv->rx_pause ? true : false;
1900         pause->tx_pause = priv->tx_pause ? true : false;
1901 }
1902 
1903 static int cpsw_set_pauseparam(struct net_device *ndev,
1904                                struct ethtool_pauseparam *pause)
1905 {
1906         struct cpsw_priv *priv = netdev_priv(ndev);
1907         bool link;
1908 
1909         priv->rx_pause = pause->rx_pause ? true : false;
1910         priv->tx_pause = pause->tx_pause ? true : false;
1911 
1912         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1913 
1914         return 0;
1915 }
1916 
1917 static const struct ethtool_ops cpsw_ethtool_ops = {
1918         .get_drvinfo    = cpsw_get_drvinfo,
1919         .get_msglevel   = cpsw_get_msglevel,
1920         .set_msglevel   = cpsw_set_msglevel,
1921         .get_link       = ethtool_op_get_link,
1922         .get_ts_info    = cpsw_get_ts_info,
1923         .get_settings   = cpsw_get_settings,
1924         .set_settings   = cpsw_set_settings,
1925         .get_coalesce   = cpsw_get_coalesce,
1926         .set_coalesce   = cpsw_set_coalesce,
1927         .get_sset_count         = cpsw_get_sset_count,
1928         .get_strings            = cpsw_get_strings,
1929         .get_ethtool_stats      = cpsw_get_ethtool_stats,
1930         .get_pauseparam         = cpsw_get_pauseparam,
1931         .set_pauseparam         = cpsw_set_pauseparam,
1932         .get_wol        = cpsw_get_wol,
1933         .set_wol        = cpsw_set_wol,
1934         .get_regs_len   = cpsw_get_regs_len,
1935         .get_regs       = cpsw_get_regs,
1936 };
1937 
1938 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1939                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
1940 {
1941         void __iomem            *regs = priv->regs;
1942         int                     slave_num = slave->slave_num;
1943         struct cpsw_slave_data  *data = priv->data.slave_data + slave_num;
1944 
1945         slave->data     = data;
1946         slave->regs     = regs + slave_reg_ofs;
1947         slave->sliver   = regs + sliver_reg_ofs;
1948         slave->port_vlan = data->dual_emac_res_vlan;
1949 }
1950 
1951 static int cpsw_probe_dt(struct cpsw_platform_data *data,
1952                          struct platform_device *pdev)
1953 {
1954         struct device_node *node = pdev->dev.of_node;
1955         struct device_node *slave_node;
1956         int i = 0, ret;
1957         u32 prop;
1958 
1959         if (!node)
1960                 return -EINVAL;
1961 
1962         if (of_property_read_u32(node, "slaves", &prop)) {
1963                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
1964                 return -EINVAL;
1965         }
1966         data->slaves = prop;
1967 
1968         if (of_property_read_u32(node, "active_slave", &prop)) {
1969                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
1970                 return -EINVAL;
1971         }
1972         data->active_slave = prop;
1973 
1974         if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1975                 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
1976                 return -EINVAL;
1977         }
1978         data->cpts_clock_mult = prop;
1979 
1980         if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1981                 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
1982                 return -EINVAL;
1983         }
1984         data->cpts_clock_shift = prop;
1985 
1986         data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1987                                         * sizeof(struct cpsw_slave_data),
1988                                         GFP_KERNEL);
1989         if (!data->slave_data)
1990                 return -ENOMEM;
1991 
1992         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1993                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
1994                 return -EINVAL;
1995         }
1996         data->channels = prop;
1997 
1998         if (of_property_read_u32(node, "ale_entries", &prop)) {
1999                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
2000                 return -EINVAL;
2001         }
2002         data->ale_entries = prop;
2003 
2004         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
2005                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
2006                 return -EINVAL;
2007         }
2008         data->bd_ram_size = prop;
2009 
2010         if (of_property_read_u32(node, "rx_descs", &prop)) {
2011                 dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
2012                 return -EINVAL;
2013         }
2014         data->rx_descs = prop;
2015 
2016         if (of_property_read_u32(node, "mac_control", &prop)) {
2017                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2018                 return -EINVAL;
2019         }
2020         data->mac_control = prop;
2021 
2022         if (of_property_read_bool(node, "dual_emac"))
2023                 data->dual_emac = 1;
2024 
2025         /*
2026          * Populate all the child nodes here...
2027          */
2028         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2029         /* We do not want to force this, as in some cases may not have child */
2030         if (ret)
2031                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2032 
2033         for_each_child_of_node(node, slave_node) {
2034                 struct cpsw_slave_data *slave_data = data->slave_data + i;
2035                 const void *mac_addr = NULL;
2036                 int lenp;
2037                 const __be32 *parp;
2038 
2039                 /* This is no slave child node, continue */
2040                 if (strcmp(slave_node->name, "slave"))
2041                         continue;
2042 
2043                 slave_data->phy_node = of_parse_phandle(slave_node,
2044                                                         "phy-handle", 0);
2045                 parp = of_get_property(slave_node, "phy_id", &lenp);
2046                 if (slave_data->phy_node) {
2047                         dev_dbg(&pdev->dev,
2048                                 "slave[%d] using phy-handle=\"%s\"\n",
2049                                 i, slave_data->phy_node->full_name);
2050                 } else if (of_phy_is_fixed_link(slave_node)) {
2051                         /* In the case of a fixed PHY, the DT node associated
2052                          * to the PHY is the Ethernet MAC DT node.
2053                          */
2054                         ret = of_phy_register_fixed_link(slave_node);
2055                         if (ret)
2056                                 return ret;
2057                         slave_data->phy_node = of_node_get(slave_node);
2058                 } else if (parp) {
2059                         u32 phyid;
2060                         struct device_node *mdio_node;
2061                         struct platform_device *mdio;
2062 
2063                         if (lenp != (sizeof(__be32) * 2)) {
2064                                 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2065                                 goto no_phy_slave;
2066                         }
2067                         mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2068                         phyid = be32_to_cpup(parp+1);
2069                         mdio = of_find_device_by_node(mdio_node);
2070                         of_node_put(mdio_node);
2071                         if (!mdio) {
2072                                 dev_err(&pdev->dev, "Missing mdio platform device\n");
2073                                 return -EINVAL;
2074                         }
2075                         snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2076                                  PHY_ID_FMT, mdio->name, phyid);
2077                 } else {
2078                         dev_err(&pdev->dev,
2079                                 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2080                                 i);
2081                         goto no_phy_slave;
2082                 }
2083                 slave_data->phy_if = of_get_phy_mode(slave_node);
2084                 if (slave_data->phy_if < 0) {
2085                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2086                                 i);
2087                         return slave_data->phy_if;
2088                 }
2089 
2090 no_phy_slave:
2091                 mac_addr = of_get_mac_address(slave_node);
2092                 if (mac_addr) {
2093                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2094                 } else {
2095                         ret = ti_cm_get_macid(&pdev->dev, i,
2096                                               slave_data->mac_addr);
2097                         if (ret)
2098                                 return ret;
2099                 }
2100                 if (data->dual_emac) {
2101                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2102                                                  &prop)) {
2103                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2104                                 slave_data->dual_emac_res_vlan = i+1;
2105                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2106                                         slave_data->dual_emac_res_vlan, i);
2107                         } else {
2108                                 slave_data->dual_emac_res_vlan = prop;
2109                         }
2110                 }
2111 
2112                 i++;
2113                 if (i == data->slaves)
2114                         break;
2115         }
2116 
2117         return 0;
2118 }
2119 
2120 static int cpsw_probe_dual_emac(struct platform_device *pdev,
2121                                 struct cpsw_priv *priv)
2122 {
2123         struct cpsw_platform_data       *data = &priv->data;
2124         struct net_device               *ndev;
2125         struct cpsw_priv                *priv_sl2;
2126         int ret = 0, i;
2127 
2128         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2129         if (!ndev) {
2130                 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
2131                 return -ENOMEM;
2132         }
2133 
2134         priv_sl2 = netdev_priv(ndev);
2135         spin_lock_init(&priv_sl2->lock);
2136         priv_sl2->data = *data;
2137         priv_sl2->pdev = pdev;
2138         priv_sl2->ndev = ndev;
2139         priv_sl2->dev  = &ndev->dev;
2140         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2141         priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2142 
2143         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2144                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2145                         ETH_ALEN);
2146                 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
2147         } else {
2148                 random_ether_addr(priv_sl2->mac_addr);
2149                 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
2150         }
2151         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2152 
2153         priv_sl2->slaves = priv->slaves;
2154         priv_sl2->clk = priv->clk;
2155 
2156         priv_sl2->coal_intvl = 0;
2157         priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2158 
2159         priv_sl2->regs = priv->regs;
2160         priv_sl2->host_port = priv->host_port;
2161         priv_sl2->host_port_regs = priv->host_port_regs;
2162         priv_sl2->wr_regs = priv->wr_regs;
2163         priv_sl2->hw_stats = priv->hw_stats;
2164         priv_sl2->dma = priv->dma;
2165         priv_sl2->txch = priv->txch;
2166         priv_sl2->rxch = priv->rxch;
2167         priv_sl2->ale = priv->ale;
2168         priv_sl2->emac_port = 1;
2169         priv->slaves[1].ndev = ndev;
2170         priv_sl2->cpts = priv->cpts;
2171         priv_sl2->version = priv->version;
2172 
2173         for (i = 0; i < priv->num_irqs; i++) {
2174                 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2175                 priv_sl2->num_irqs = priv->num_irqs;
2176         }
2177         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2178 
2179         ndev->netdev_ops = &cpsw_netdev_ops;
2180         ndev->ethtool_ops = &cpsw_ethtool_ops;
2181 
2182         /* register the network device */
2183         SET_NETDEV_DEV(ndev, &pdev->dev);
2184         ret = register_netdev(ndev);
2185         if (ret) {
2186                 dev_err(&pdev->dev, "cpsw: error registering net device\n");
2187                 free_netdev(ndev);
2188                 ret = -ENODEV;
2189         }
2190 
2191         return ret;
2192 }
2193 
2194 #define CPSW_QUIRK_IRQ          BIT(0)
2195 
2196 static struct platform_device_id cpsw_devtype[] = {
2197         {
2198                 /* keep it for existing comaptibles */
2199                 .name = "cpsw",
2200                 .driver_data = CPSW_QUIRK_IRQ,
2201         }, {
2202                 .name = "am335x-cpsw",
2203                 .driver_data = CPSW_QUIRK_IRQ,
2204         }, {
2205                 .name = "am4372-cpsw",
2206                 .driver_data = 0,
2207         }, {
2208                 .name = "dra7-cpsw",
2209                 .driver_data = 0,
2210         }, {
2211                 /* sentinel */
2212         }
2213 };
2214 MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2215 
2216 enum ti_cpsw_type {
2217         CPSW = 0,
2218         AM335X_CPSW,
2219         AM4372_CPSW,
2220         DRA7_CPSW,
2221 };
2222 
2223 static const struct of_device_id cpsw_of_mtable[] = {
2224         { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2225         { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2226         { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2227         { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2228         { /* sentinel */ },
2229 };
2230 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2231 
2232 static int cpsw_probe(struct platform_device *pdev)
2233 {
2234         struct cpsw_platform_data       *data;
2235         struct net_device               *ndev;
2236         struct cpsw_priv                *priv;
2237         struct cpdma_params             dma_params;
2238         struct cpsw_ale_params          ale_params;
2239         void __iomem                    *ss_regs;
2240         struct resource                 *res, *ss_res;
2241         const struct of_device_id       *of_id;
2242         struct gpio_descs               *mode;
2243         u32 slave_offset, sliver_offset, slave_size;
2244         int ret = 0, i;
2245         int irq;
2246 
2247         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2248         if (!ndev) {
2249                 dev_err(&pdev->dev, "error allocating net_device\n");
2250                 return -ENOMEM;
2251         }
2252 
2253         platform_set_drvdata(pdev, ndev);
2254         priv = netdev_priv(ndev);
2255         spin_lock_init(&priv->lock);
2256         priv->pdev = pdev;
2257         priv->ndev = ndev;
2258         priv->dev  = &ndev->dev;
2259         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2260         priv->rx_packet_max = max(rx_packet_max, 128);
2261         priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2262         if (!priv->cpts) {
2263                 dev_err(&pdev->dev, "error allocating cpts\n");
2264                 ret = -ENOMEM;
2265                 goto clean_ndev_ret;
2266         }
2267 
2268         mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2269         if (IS_ERR(mode)) {
2270                 ret = PTR_ERR(mode);
2271                 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2272                 goto clean_ndev_ret;
2273         }
2274 
2275         /*
2276          * This may be required here for child devices.
2277          */
2278         pm_runtime_enable(&pdev->dev);
2279 
2280         /* Select default pin state */
2281         pinctrl_pm_select_default_state(&pdev->dev);
2282 
2283         if (cpsw_probe_dt(&priv->data, pdev)) {
2284                 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2285                 ret = -ENODEV;
2286                 goto clean_runtime_disable_ret;
2287         }
2288         data = &priv->data;
2289 
2290         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2291                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2292                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2293         } else {
2294                 eth_random_addr(priv->mac_addr);
2295                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2296         }
2297 
2298         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2299 
2300         priv->slaves = devm_kzalloc(&pdev->dev,
2301                                     sizeof(struct cpsw_slave) * data->slaves,
2302                                     GFP_KERNEL);
2303         if (!priv->slaves) {
2304                 ret = -ENOMEM;
2305                 goto clean_runtime_disable_ret;
2306         }
2307         for (i = 0; i < data->slaves; i++)
2308                 priv->slaves[i].slave_num = i;
2309 
2310         priv->slaves[0].ndev = ndev;
2311         priv->emac_port = 0;
2312 
2313         priv->clk = devm_clk_get(&pdev->dev, "fck");
2314         if (IS_ERR(priv->clk)) {
2315                 dev_err(priv->dev, "fck is not found\n");
2316                 ret = -ENODEV;
2317                 goto clean_runtime_disable_ret;
2318         }
2319         priv->coal_intvl = 0;
2320         priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
2321 
2322         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2323         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2324         if (IS_ERR(ss_regs)) {
2325                 ret = PTR_ERR(ss_regs);
2326                 goto clean_runtime_disable_ret;
2327         }
2328         priv->regs = ss_regs;
2329         priv->host_port = HOST_PORT_NUM;
2330 
2331         /* Need to enable clocks with runtime PM api to access module
2332          * registers
2333          */
2334         pm_runtime_get_sync(&pdev->dev);
2335         priv->version = readl(&priv->regs->id_ver);
2336         pm_runtime_put_sync(&pdev->dev);
2337 
2338         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2339         priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2340         if (IS_ERR(priv->wr_regs)) {
2341                 ret = PTR_ERR(priv->wr_regs);
2342                 goto clean_runtime_disable_ret;
2343         }
2344 
2345         memset(&dma_params, 0, sizeof(dma_params));
2346         memset(&ale_params, 0, sizeof(ale_params));
2347 
2348         switch (priv->version) {
2349         case CPSW_VERSION_1:
2350                 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2351                 priv->cpts->reg      = ss_regs + CPSW1_CPTS_OFFSET;
2352                 priv->hw_stats       = ss_regs + CPSW1_HW_STATS;
2353                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
2354                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
2355                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
2356                 slave_offset         = CPSW1_SLAVE_OFFSET;
2357                 slave_size           = CPSW1_SLAVE_SIZE;
2358                 sliver_offset        = CPSW1_SLIVER_OFFSET;
2359                 dma_params.desc_mem_phys = 0;
2360                 break;
2361         case CPSW_VERSION_2:
2362         case CPSW_VERSION_3:
2363         case CPSW_VERSION_4:
2364                 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2365                 priv->cpts->reg      = ss_regs + CPSW2_CPTS_OFFSET;
2366                 priv->hw_stats       = ss_regs + CPSW2_HW_STATS;
2367                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
2368                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
2369                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
2370                 slave_offset         = CPSW2_SLAVE_OFFSET;
2371                 slave_size           = CPSW2_SLAVE_SIZE;
2372                 sliver_offset        = CPSW2_SLIVER_OFFSET;
2373                 dma_params.desc_mem_phys =
2374                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2375                 break;
2376         default:
2377                 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2378                 ret = -ENODEV;
2379                 goto clean_runtime_disable_ret;
2380         }
2381         for (i = 0; i < priv->data.slaves; i++) {
2382                 struct cpsw_slave *slave = &priv->slaves[i];
2383                 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2384                 slave_offset  += slave_size;
2385                 sliver_offset += SLIVER_SIZE;
2386         }
2387 
2388         dma_params.dev          = &pdev->dev;
2389         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
2390         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
2391         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
2392         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
2393         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
2394 
2395         dma_params.num_chan             = data->channels;
2396         dma_params.has_soft_reset       = true;
2397         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
2398         dma_params.desc_mem_size        = data->bd_ram_size;
2399         dma_params.desc_align           = 16;
2400         dma_params.has_ext_regs         = true;
2401         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
2402 
2403         priv->dma = cpdma_ctlr_create(&dma_params);
2404         if (!priv->dma) {
2405                 dev_err(priv->dev, "error initializing dma\n");
2406                 ret = -ENOMEM;
2407                 goto clean_runtime_disable_ret;
2408         }
2409 
2410         priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2411                                        cpsw_tx_handler);
2412         priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2413                                        cpsw_rx_handler);
2414 
2415         if (WARN_ON(!priv->txch || !priv->rxch)) {
2416                 dev_err(priv->dev, "error initializing dma channels\n");
2417                 ret = -ENOMEM;
2418                 goto clean_dma_ret;
2419         }
2420 
2421         ale_params.dev                  = &ndev->dev;
2422         ale_params.ale_ageout           = ale_ageout;
2423         ale_params.ale_entries          = data->ale_entries;
2424         ale_params.ale_ports            = data->slaves;
2425 
2426         priv->ale = cpsw_ale_create(&ale_params);
2427         if (!priv->ale) {
2428                 dev_err(priv->dev, "error initializing ale engine\n");
2429                 ret = -ENODEV;
2430                 goto clean_dma_ret;
2431         }
2432 
2433         ndev->irq = platform_get_irq(pdev, 1);
2434         if (ndev->irq < 0) {
2435                 dev_err(priv->dev, "error getting irq resource\n");
2436                 ret = ndev->irq;
2437                 goto clean_ale_ret;
2438         }
2439 
2440         of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
2441         if (of_id) {
2442                 pdev->id_entry = of_id->data;
2443                 if (pdev->id_entry->driver_data)
2444                         priv->quirk_irq = true;
2445         }
2446 
2447         /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2448          * MISC IRQs which are always kept disabled with this driver so
2449          * we will not request them.
2450          *
2451          * If anyone wants to implement support for those, make sure to
2452          * first request and append them to irqs_table array.
2453          */
2454 
2455         /* RX IRQ */
2456         irq = platform_get_irq(pdev, 1);
2457         if (irq < 0) {
2458                 ret = irq;
2459                 goto clean_ale_ret;
2460         }
2461 
2462         priv->irqs_table[0] = irq;
2463         ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
2464                                0, dev_name(&pdev->dev), priv);
2465         if (ret < 0) {
2466                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2467                 goto clean_ale_ret;
2468         }
2469 
2470         /* TX IRQ */
2471         irq = platform_get_irq(pdev, 2);
2472         if (irq < 0) {
2473                 ret = irq;
2474                 goto clean_ale_ret;
2475         }
2476 
2477         priv->irqs_table[1] = irq;
2478         ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
2479                                0, dev_name(&pdev->dev), priv);
2480         if (ret < 0) {
2481                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2482                 goto clean_ale_ret;
2483         }
2484         priv->num_irqs = 2;
2485 
2486         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2487 
2488         ndev->netdev_ops = &cpsw_netdev_ops;
2489         ndev->ethtool_ops = &cpsw_ethtool_ops;
2490         netif_napi_add(ndev, &priv->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
2491         netif_tx_napi_add(ndev, &priv->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
2492 
2493         /* register the network device */
2494         SET_NETDEV_DEV(ndev, &pdev->dev);
2495         ret = register_netdev(ndev);
2496         if (ret) {
2497                 dev_err(priv->dev, "error registering net device\n");
2498                 ret = -ENODEV;
2499                 goto clean_ale_ret;
2500         }
2501 
2502         cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2503                     &ss_res->start, ndev->irq);
2504 
2505         if (priv->data.dual_emac) {
2506                 ret = cpsw_probe_dual_emac(pdev, priv);
2507                 if (ret) {
2508                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2509                         goto clean_ale_ret;
2510                 }
2511         }
2512 
2513         return 0;
2514 
2515 clean_ale_ret:
2516         cpsw_ale_destroy(priv->ale);
2517 clean_dma_ret:
2518         cpdma_chan_destroy(priv->txch);
2519         cpdma_chan_destroy(priv->rxch);
2520         cpdma_ctlr_destroy(priv->dma);
2521 clean_runtime_disable_ret:
2522         pm_runtime_disable(&pdev->dev);
2523 clean_ndev_ret:
2524         free_netdev(priv->ndev);
2525         return ret;
2526 }
2527 
2528 static int cpsw_remove_child_device(struct device *dev, void *c)
2529 {
2530         struct platform_device *pdev = to_platform_device(dev);
2531 
2532         of_device_unregister(pdev);
2533 
2534         return 0;
2535 }
2536 
2537 static int cpsw_remove(struct platform_device *pdev)
2538 {
2539         struct net_device *ndev = platform_get_drvdata(pdev);
2540         struct cpsw_priv *priv = netdev_priv(ndev);
2541 
2542         if (priv->data.dual_emac)
2543                 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2544         unregister_netdev(ndev);
2545 
2546         cpsw_ale_destroy(priv->ale);
2547         cpdma_chan_destroy(priv->txch);
2548         cpdma_chan_destroy(priv->rxch);
2549         cpdma_ctlr_destroy(priv->dma);
2550         pm_runtime_disable(&pdev->dev);
2551         device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device);
2552         if (priv->data.dual_emac)
2553                 free_netdev(cpsw_get_slave_ndev(priv, 1));
2554         free_netdev(ndev);
2555         return 0;
2556 }
2557 
2558 #ifdef CONFIG_PM_SLEEP
2559 static int cpsw_suspend(struct device *dev)
2560 {
2561         struct platform_device  *pdev = to_platform_device(dev);
2562         struct net_device       *ndev = platform_get_drvdata(pdev);
2563         struct cpsw_priv        *priv = netdev_priv(ndev);
2564 
2565         if (priv->data.dual_emac) {
2566                 int i;
2567 
2568                 for (i = 0; i < priv->data.slaves; i++) {
2569                         if (netif_running(priv->slaves[i].ndev))
2570                                 cpsw_ndo_stop(priv->slaves[i].ndev);
2571                         soft_reset_slave(priv->slaves + i);
2572                 }
2573         } else {
2574                 if (netif_running(ndev))
2575                         cpsw_ndo_stop(ndev);
2576                 for_each_slave(priv, soft_reset_slave);
2577         }
2578 
2579         pm_runtime_put_sync(&pdev->dev);
2580 
2581         /* Select sleep pin state */
2582         pinctrl_pm_select_sleep_state(&pdev->dev);
2583 
2584         return 0;
2585 }
2586 
2587 static int cpsw_resume(struct device *dev)
2588 {
2589         struct platform_device  *pdev = to_platform_device(dev);
2590         struct net_device       *ndev = platform_get_drvdata(pdev);
2591         struct cpsw_priv        *priv = netdev_priv(ndev);
2592 
2593         pm_runtime_get_sync(&pdev->dev);
2594 
2595         /* Select default pin state */
2596         pinctrl_pm_select_default_state(&pdev->dev);
2597 
2598         if (priv->data.dual_emac) {
2599                 int i;
2600 
2601                 for (i = 0; i < priv->data.slaves; i++) {
2602                         if (netif_running(priv->slaves[i].ndev))
2603                                 cpsw_ndo_open(priv->slaves[i].ndev);
2604                 }
2605         } else {
2606                 if (netif_running(ndev))
2607                         cpsw_ndo_open(ndev);
2608         }
2609         return 0;
2610 }
2611 #endif
2612 
2613 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
2614 
2615 static struct platform_driver cpsw_driver = {
2616         .driver = {
2617                 .name    = "cpsw",
2618                 .pm      = &cpsw_pm_ops,
2619                 .of_match_table = cpsw_of_mtable,
2620         },
2621         .probe = cpsw_probe,
2622         .remove = cpsw_remove,
2623 };
2624 
2625 module_platform_driver(cpsw_driver);
2626 
2627 MODULE_LICENSE("GPL");
2628 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2629 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2630 MODULE_DESCRIPTION("TI CPSW Ethernet driver");
2631 

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