Version:  2.0.40 2.2.26 2.4.37 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19

Linux/drivers/net/ethernet/ti/cpsw.c

  1 /*
  2  * Texas Instruments Ethernet Switch Driver
  3  *
  4  * Copyright (C) 2012 Texas Instruments
  5  *
  6  * This program is free software; you can redistribute it and/or
  7  * modify it under the terms of the GNU General Public License as
  8  * published by the Free Software Foundation version 2.
  9  *
 10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 11  * kind, whether express or implied; without even the implied warranty
 12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  */
 15 
 16 #include <linux/kernel.h>
 17 #include <linux/io.h>
 18 #include <linux/clk.h>
 19 #include <linux/timer.h>
 20 #include <linux/module.h>
 21 #include <linux/platform_device.h>
 22 #include <linux/irqreturn.h>
 23 #include <linux/interrupt.h>
 24 #include <linux/if_ether.h>
 25 #include <linux/etherdevice.h>
 26 #include <linux/netdevice.h>
 27 #include <linux/net_tstamp.h>
 28 #include <linux/phy.h>
 29 #include <linux/workqueue.h>
 30 #include <linux/delay.h>
 31 #include <linux/pm_runtime.h>
 32 #include <linux/of.h>
 33 #include <linux/of_net.h>
 34 #include <linux/of_device.h>
 35 #include <linux/if_vlan.h>
 36 #include <linux/mfd/syscon.h>
 37 #include <linux/regmap.h>
 38 
 39 #include <linux/pinctrl/consumer.h>
 40 
 41 #include "cpsw.h"
 42 #include "cpsw_ale.h"
 43 #include "cpts.h"
 44 #include "davinci_cpdma.h"
 45 
 46 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
 47                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
 48                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
 49                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
 50                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
 51                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
 52                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
 53                          NETIF_MSG_RX_STATUS)
 54 
 55 #define cpsw_info(priv, type, format, ...)              \
 56 do {                                                            \
 57         if (netif_msg_##type(priv) && net_ratelimit())          \
 58                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
 59 } while (0)
 60 
 61 #define cpsw_err(priv, type, format, ...)               \
 62 do {                                                            \
 63         if (netif_msg_##type(priv) && net_ratelimit())          \
 64                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
 65 } while (0)
 66 
 67 #define cpsw_dbg(priv, type, format, ...)               \
 68 do {                                                            \
 69         if (netif_msg_##type(priv) && net_ratelimit())          \
 70                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
 71 } while (0)
 72 
 73 #define cpsw_notice(priv, type, format, ...)            \
 74 do {                                                            \
 75         if (netif_msg_##type(priv) && net_ratelimit())          \
 76                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
 77 } while (0)
 78 
 79 #define ALE_ALL_PORTS           0x7
 80 
 81 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
 82 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
 83 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
 84 
 85 #define CPSW_VERSION_1          0x19010a
 86 #define CPSW_VERSION_2          0x19010c
 87 #define CPSW_VERSION_3          0x19010f
 88 #define CPSW_VERSION_4          0x190112
 89 
 90 #define HOST_PORT_NUM           0
 91 #define SLIVER_SIZE             0x40
 92 
 93 #define CPSW1_HOST_PORT_OFFSET  0x028
 94 #define CPSW1_SLAVE_OFFSET      0x050
 95 #define CPSW1_SLAVE_SIZE        0x040
 96 #define CPSW1_CPDMA_OFFSET      0x100
 97 #define CPSW1_STATERAM_OFFSET   0x200
 98 #define CPSW1_HW_STATS          0x400
 99 #define CPSW1_CPTS_OFFSET       0x500
100 #define CPSW1_ALE_OFFSET        0x600
101 #define CPSW1_SLIVER_OFFSET     0x700
102 
103 #define CPSW2_HOST_PORT_OFFSET  0x108
104 #define CPSW2_SLAVE_OFFSET      0x200
105 #define CPSW2_SLAVE_SIZE        0x100
106 #define CPSW2_CPDMA_OFFSET      0x800
107 #define CPSW2_HW_STATS          0x900
108 #define CPSW2_STATERAM_OFFSET   0xa00
109 #define CPSW2_CPTS_OFFSET       0xc00
110 #define CPSW2_ALE_OFFSET        0xd00
111 #define CPSW2_SLIVER_OFFSET     0xd80
112 #define CPSW2_BD_OFFSET         0x2000
113 
114 #define CPDMA_RXTHRESH          0x0c0
115 #define CPDMA_RXFREE            0x0e0
116 #define CPDMA_TXHDP             0x00
117 #define CPDMA_RXHDP             0x20
118 #define CPDMA_TXCP              0x40
119 #define CPDMA_RXCP              0x60
120 
121 #define CPSW_POLL_WEIGHT        64
122 #define CPSW_MIN_PACKET_SIZE    60
123 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
124 
125 #define RX_PRIORITY_MAPPING     0x76543210
126 #define TX_PRIORITY_MAPPING     0x33221100
127 #define CPDMA_TX_PRIORITY_MAP   0x76543210
128 
129 #define CPSW_VLAN_AWARE         BIT(1)
130 #define CPSW_ALE_VLAN_AWARE     1
131 
132 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
133 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
134 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
135 
136 #define CPSW_INTPACEEN          (0x3f << 16)
137 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
138 #define CPSW_CMINTMAX_CNT       63
139 #define CPSW_CMINTMIN_CNT       2
140 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
141 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
142 
143 #define cpsw_enable_irq(priv)   \
144         do {                    \
145                 u32 i;          \
146                 for (i = 0; i < priv->num_irqs; i++) \
147                         enable_irq(priv->irqs_table[i]); \
148         } while (0)
149 #define cpsw_disable_irq(priv)  \
150         do {                    \
151                 u32 i;          \
152                 for (i = 0; i < priv->num_irqs; i++) \
153                         disable_irq_nosync(priv->irqs_table[i]); \
154         } while (0)
155 
156 #define cpsw_slave_index(priv)                          \
157                 ((priv->data.dual_emac) ? priv->emac_port :     \
158                 priv->data.active_slave)
159 
160 static int debug_level;
161 module_param(debug_level, int, 0);
162 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
163 
164 static int ale_ageout = 10;
165 module_param(ale_ageout, int, 0);
166 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
167 
168 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
169 module_param(rx_packet_max, int, 0);
170 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
171 
172 struct cpsw_wr_regs {
173         u32     id_ver;
174         u32     soft_reset;
175         u32     control;
176         u32     int_control;
177         u32     rx_thresh_en;
178         u32     rx_en;
179         u32     tx_en;
180         u32     misc_en;
181         u32     mem_allign1[8];
182         u32     rx_thresh_stat;
183         u32     rx_stat;
184         u32     tx_stat;
185         u32     misc_stat;
186         u32     mem_allign2[8];
187         u32     rx_imax;
188         u32     tx_imax;
189 
190 };
191 
192 struct cpsw_ss_regs {
193         u32     id_ver;
194         u32     control;
195         u32     soft_reset;
196         u32     stat_port_en;
197         u32     ptype;
198         u32     soft_idle;
199         u32     thru_rate;
200         u32     gap_thresh;
201         u32     tx_start_wds;
202         u32     flow_control;
203         u32     vlan_ltype;
204         u32     ts_ltype;
205         u32     dlr_ltype;
206 };
207 
208 /* CPSW_PORT_V1 */
209 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
210 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
211 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
212 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
213 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
214 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
215 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
216 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
217 
218 /* CPSW_PORT_V2 */
219 #define CPSW2_CONTROL       0x00 /* Control Register */
220 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
221 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
222 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
223 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
224 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
225 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
226 
227 /* CPSW_PORT_V1 and V2 */
228 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
229 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
230 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
231 
232 /* CPSW_PORT_V2 only */
233 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
234 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
235 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
236 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
237 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
238 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
239 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
240 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
241 
242 /* Bit definitions for the CPSW2_CONTROL register */
243 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
244 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
245 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
246 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
247 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
248 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
249 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
250 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
251 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
252 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
253 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
254 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
255 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
256 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
257 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
258 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
259 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
260 
261 #define CTRL_V2_TS_BITS \
262         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
263          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
264 
265 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
266 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
267 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
268 
269 
270 #define CTRL_V3_TS_BITS \
271         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
272          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
273          TS_LTYPE1_EN)
274 
275 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
276 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
277 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
278 
279 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
280 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
281 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
282 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
283 #define TS_MSG_TYPE_EN_MASK      (0xffff)
284 
285 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
286 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
287 
288 /* Bit definitions for the CPSW1_TS_CTL register */
289 #define CPSW_V1_TS_RX_EN                BIT(0)
290 #define CPSW_V1_TS_TX_EN                BIT(4)
291 #define CPSW_V1_MSG_TYPE_OFS            16
292 
293 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
294 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
295 
296 struct cpsw_host_regs {
297         u32     max_blks;
298         u32     blk_cnt;
299         u32     tx_in_ctl;
300         u32     port_vlan;
301         u32     tx_pri_map;
302         u32     cpdma_tx_pri_map;
303         u32     cpdma_rx_chan_map;
304 };
305 
306 struct cpsw_sliver_regs {
307         u32     id_ver;
308         u32     mac_control;
309         u32     mac_status;
310         u32     soft_reset;
311         u32     rx_maxlen;
312         u32     __reserved_0;
313         u32     rx_pause;
314         u32     tx_pause;
315         u32     __reserved_1;
316         u32     rx_pri_map;
317 };
318 
319 struct cpsw_hw_stats {
320         u32     rxgoodframes;
321         u32     rxbroadcastframes;
322         u32     rxmulticastframes;
323         u32     rxpauseframes;
324         u32     rxcrcerrors;
325         u32     rxaligncodeerrors;
326         u32     rxoversizedframes;
327         u32     rxjabberframes;
328         u32     rxundersizedframes;
329         u32     rxfragments;
330         u32     __pad_0[2];
331         u32     rxoctets;
332         u32     txgoodframes;
333         u32     txbroadcastframes;
334         u32     txmulticastframes;
335         u32     txpauseframes;
336         u32     txdeferredframes;
337         u32     txcollisionframes;
338         u32     txsinglecollframes;
339         u32     txmultcollframes;
340         u32     txexcessivecollisions;
341         u32     txlatecollisions;
342         u32     txunderrun;
343         u32     txcarriersenseerrors;
344         u32     txoctets;
345         u32     octetframes64;
346         u32     octetframes65t127;
347         u32     octetframes128t255;
348         u32     octetframes256t511;
349         u32     octetframes512t1023;
350         u32     octetframes1024tup;
351         u32     netoctets;
352         u32     rxsofoverruns;
353         u32     rxmofoverruns;
354         u32     rxdmaoverruns;
355 };
356 
357 struct cpsw_slave {
358         void __iomem                    *regs;
359         struct cpsw_sliver_regs __iomem *sliver;
360         int                             slave_num;
361         u32                             mac_control;
362         struct cpsw_slave_data          *data;
363         struct phy_device               *phy;
364         struct net_device               *ndev;
365         u32                             port_vlan;
366         u32                             open_stat;
367 };
368 
369 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
370 {
371         return __raw_readl(slave->regs + offset);
372 }
373 
374 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
375 {
376         __raw_writel(val, slave->regs + offset);
377 }
378 
379 struct cpsw_priv {
380         spinlock_t                      lock;
381         struct platform_device          *pdev;
382         struct net_device               *ndev;
383         struct napi_struct              napi;
384         struct device                   *dev;
385         struct cpsw_platform_data       data;
386         struct cpsw_ss_regs __iomem     *regs;
387         struct cpsw_wr_regs __iomem     *wr_regs;
388         u8 __iomem                      *hw_stats;
389         struct cpsw_host_regs __iomem   *host_port_regs;
390         u32                             msg_enable;
391         u32                             version;
392         u32                             coal_intvl;
393         u32                             bus_freq_mhz;
394         int                             rx_packet_max;
395         int                             host_port;
396         struct clk                      *clk;
397         u8                              mac_addr[ETH_ALEN];
398         struct cpsw_slave               *slaves;
399         struct cpdma_ctlr               *dma;
400         struct cpdma_chan               *txch, *rxch;
401         struct cpsw_ale                 *ale;
402         bool                            rx_pause;
403         bool                            tx_pause;
404         /* snapshot of IRQ numbers */
405         u32 irqs_table[4];
406         u32 num_irqs;
407         bool irq_enabled;
408         struct cpts *cpts;
409         u32 emac_port;
410 };
411 
412 struct cpsw_stats {
413         char stat_string[ETH_GSTRING_LEN];
414         int type;
415         int sizeof_stat;
416         int stat_offset;
417 };
418 
419 enum {
420         CPSW_STATS,
421         CPDMA_RX_STATS,
422         CPDMA_TX_STATS,
423 };
424 
425 #define CPSW_STAT(m)            CPSW_STATS,                             \
426                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
427                                 offsetof(struct cpsw_hw_stats, m)
428 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
429                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
430                                 offsetof(struct cpdma_chan_stats, m)
431 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
432                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
433                                 offsetof(struct cpdma_chan_stats, m)
434 
435 static const struct cpsw_stats cpsw_gstrings_stats[] = {
436         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
437         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
438         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
439         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
440         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
441         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
442         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
443         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
444         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
445         { "Rx Fragments", CPSW_STAT(rxfragments) },
446         { "Rx Octets", CPSW_STAT(rxoctets) },
447         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
448         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
449         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
450         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
451         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
452         { "Collisions", CPSW_STAT(txcollisionframes) },
453         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
454         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
455         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
456         { "Late Collisions", CPSW_STAT(txlatecollisions) },
457         { "Tx Underrun", CPSW_STAT(txunderrun) },
458         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
459         { "Tx Octets", CPSW_STAT(txoctets) },
460         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
461         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
462         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
463         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
464         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
465         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
466         { "Net Octets", CPSW_STAT(netoctets) },
467         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
468         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
469         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
470         { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
471         { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
472         { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
473         { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
474         { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
475         { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
476         { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
477         { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
478         { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
479         { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
480         { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
481         { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
482         { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
483         { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
484         { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
485         { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
486         { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
487         { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
488         { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
489         { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
490         { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
491         { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
492         { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
493         { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
494         { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
495         { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
496 };
497 
498 #define CPSW_STATS_LEN  ARRAY_SIZE(cpsw_gstrings_stats)
499 
500 #define napi_to_priv(napi)      container_of(napi, struct cpsw_priv, napi)
501 #define for_each_slave(priv, func, arg...)                              \
502         do {                                                            \
503                 struct cpsw_slave *slave;                               \
504                 int n;                                                  \
505                 if (priv->data.dual_emac)                               \
506                         (func)((priv)->slaves + priv->emac_port, ##arg);\
507                 else                                                    \
508                         for (n = (priv)->data.slaves,                   \
509                                         slave = (priv)->slaves;         \
510                                         n; n--)                         \
511                                 (func)(slave++, ##arg);                 \
512         } while (0)
513 #define cpsw_get_slave_ndev(priv, __slave_no__)                         \
514         (priv->slaves[__slave_no__].ndev)
515 #define cpsw_get_slave_priv(priv, __slave_no__)                         \
516         ((priv->slaves[__slave_no__].ndev) ?                            \
517                 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL)    \
518 
519 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb)         \
520         do {                                                            \
521                 if (!priv->data.dual_emac)                              \
522                         break;                                          \
523                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
524                         ndev = cpsw_get_slave_ndev(priv, 0);            \
525                         priv = netdev_priv(ndev);                       \
526                         skb->dev = ndev;                                \
527                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
528                         ndev = cpsw_get_slave_ndev(priv, 1);            \
529                         priv = netdev_priv(ndev);                       \
530                         skb->dev = ndev;                                \
531                 }                                                       \
532         } while (0)
533 #define cpsw_add_mcast(priv, addr)                                      \
534         do {                                                            \
535                 if (priv->data.dual_emac) {                             \
536                         struct cpsw_slave *slave = priv->slaves +       \
537                                                 priv->emac_port;        \
538                         int slave_port = cpsw_get_slave_port(priv,      \
539                                                 slave->slave_num);      \
540                         cpsw_ale_add_mcast(priv->ale, addr,             \
541                                 1 << slave_port | 1 << priv->host_port, \
542                                 ALE_VLAN, slave->port_vlan, 0);         \
543                 } else {                                                \
544                         cpsw_ale_add_mcast(priv->ale, addr,             \
545                                 ALE_ALL_PORTS << priv->host_port,       \
546                                 0, 0, 0);                               \
547                 }                                                       \
548         } while (0)
549 
550 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
551 {
552         if (priv->host_port == 0)
553                 return slave_num + 1;
554         else
555                 return slave_num;
556 }
557 
558 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
559 {
560         struct cpsw_priv *priv = netdev_priv(ndev);
561         struct cpsw_ale *ale = priv->ale;
562         int i;
563 
564         if (priv->data.dual_emac) {
565                 bool flag = false;
566 
567                 /* Enabling promiscuous mode for one interface will be
568                  * common for both the interface as the interface shares
569                  * the same hardware resource.
570                  */
571                 for (i = 0; i < priv->data.slaves; i++)
572                         if (priv->slaves[i].ndev->flags & IFF_PROMISC)
573                                 flag = true;
574 
575                 if (!enable && flag) {
576                         enable = true;
577                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
578                 }
579 
580                 if (enable) {
581                         /* Enable Bypass */
582                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
583 
584                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
585                 } else {
586                         /* Disable Bypass */
587                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
588                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
589                 }
590         } else {
591                 if (enable) {
592                         unsigned long timeout = jiffies + HZ;
593 
594                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
595                         for (i = 0; i <= priv->data.slaves; i++) {
596                                 cpsw_ale_control_set(ale, i,
597                                                      ALE_PORT_NOLEARN, 1);
598                                 cpsw_ale_control_set(ale, i,
599                                                      ALE_PORT_NO_SA_UPDATE, 1);
600                         }
601 
602                         /* Clear All Untouched entries */
603                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
604                         do {
605                                 cpu_relax();
606                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
607                                         break;
608                         } while (time_after(timeout, jiffies));
609                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
610 
611                         /* Clear all mcast from ALE */
612                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<
613                                                  priv->host_port, -1);
614 
615                         /* Flood All Unicast Packets to Host port */
616                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
617                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
618                 } else {
619                         /* Don't Flood All Unicast Packets to Host port */
620                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
621 
622                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
623                         for (i = 0; i <= priv->data.slaves; i++) {
624                                 cpsw_ale_control_set(ale, i,
625                                                      ALE_PORT_NOLEARN, 0);
626                                 cpsw_ale_control_set(ale, i,
627                                                      ALE_PORT_NO_SA_UPDATE, 0);
628                         }
629                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
630                 }
631         }
632 }
633 
634 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
635 {
636         struct cpsw_priv *priv = netdev_priv(ndev);
637         int vid;
638 
639         if (priv->data.dual_emac)
640                 vid = priv->slaves[priv->emac_port].port_vlan;
641         else
642                 vid = priv->data.default_vlan;
643 
644         if (ndev->flags & IFF_PROMISC) {
645                 /* Enable promiscuous mode */
646                 cpsw_set_promiscious(ndev, true);
647                 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
648                 return;
649         } else {
650                 /* Disable promiscuous mode */
651                 cpsw_set_promiscious(ndev, false);
652         }
653 
654         /* Restore allmulti on vlans if necessary */
655         cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
656 
657         /* Clear all mcast from ALE */
658         cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port,
659                                  vid);
660 
661         if (!netdev_mc_empty(ndev)) {
662                 struct netdev_hw_addr *ha;
663 
664                 /* program multicast address list into ALE register */
665                 netdev_for_each_mc_addr(ha, ndev) {
666                         cpsw_add_mcast(priv, (u8 *)ha->addr);
667                 }
668         }
669 }
670 
671 static void cpsw_intr_enable(struct cpsw_priv *priv)
672 {
673         __raw_writel(0xFF, &priv->wr_regs->tx_en);
674         __raw_writel(0xFF, &priv->wr_regs->rx_en);
675 
676         cpdma_ctlr_int_ctrl(priv->dma, true);
677         return;
678 }
679 
680 static void cpsw_intr_disable(struct cpsw_priv *priv)
681 {
682         __raw_writel(0, &priv->wr_regs->tx_en);
683         __raw_writel(0, &priv->wr_regs->rx_en);
684 
685         cpdma_ctlr_int_ctrl(priv->dma, false);
686         return;
687 }
688 
689 static void cpsw_tx_handler(void *token, int len, int status)
690 {
691         struct sk_buff          *skb = token;
692         struct net_device       *ndev = skb->dev;
693         struct cpsw_priv        *priv = netdev_priv(ndev);
694 
695         /* Check whether the queue is stopped due to stalled tx dma, if the
696          * queue is stopped then start the queue as we have free desc for tx
697          */
698         if (unlikely(netif_queue_stopped(ndev)))
699                 netif_wake_queue(ndev);
700         cpts_tx_timestamp(priv->cpts, skb);
701         ndev->stats.tx_packets++;
702         ndev->stats.tx_bytes += len;
703         dev_kfree_skb_any(skb);
704 }
705 
706 static void cpsw_rx_handler(void *token, int len, int status)
707 {
708         struct sk_buff          *skb = token;
709         struct sk_buff          *new_skb;
710         struct net_device       *ndev = skb->dev;
711         struct cpsw_priv        *priv = netdev_priv(ndev);
712         int                     ret = 0;
713 
714         cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
715 
716         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
717                 bool ndev_status = false;
718                 struct cpsw_slave *slave = priv->slaves;
719                 int n;
720 
721                 if (priv->data.dual_emac) {
722                         /* In dual emac mode check for all interfaces */
723                         for (n = priv->data.slaves; n; n--, slave++)
724                                 if (netif_running(slave->ndev))
725                                         ndev_status = true;
726                 }
727 
728                 if (ndev_status && (status >= 0)) {
729                         /* The packet received is for the interface which
730                          * is already down and the other interface is up
731                          * and running, intead of freeing which results
732                          * in reducing of the number of rx descriptor in
733                          * DMA engine, requeue skb back to cpdma.
734                          */
735                         new_skb = skb;
736                         goto requeue;
737                 }
738 
739                 /* the interface is going down, skbs are purged */
740                 dev_kfree_skb_any(skb);
741                 return;
742         }
743 
744         new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
745         if (new_skb) {
746                 skb_put(skb, len);
747                 cpts_rx_timestamp(priv->cpts, skb);
748                 skb->protocol = eth_type_trans(skb, ndev);
749                 netif_receive_skb(skb);
750                 ndev->stats.rx_bytes += len;
751                 ndev->stats.rx_packets++;
752         } else {
753                 ndev->stats.rx_dropped++;
754                 new_skb = skb;
755         }
756 
757 requeue:
758         ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
759                         skb_tailroom(new_skb), 0);
760         if (WARN_ON(ret < 0))
761                 dev_kfree_skb_any(new_skb);
762 }
763 
764 static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
765 {
766         struct cpsw_priv *priv = dev_id;
767         int value = irq - priv->irqs_table[0];
768 
769         /* NOTICE: Ending IRQ here. The trick with the 'value' variable above
770          * is to make sure we will always write the correct value to the EOI
771          * register. Namely 0 for RX_THRESH Interrupt, 1 for RX Interrupt, 2
772          * for TX Interrupt and 3 for MISC Interrupt.
773          */
774         cpdma_ctlr_eoi(priv->dma, value);
775 
776         cpsw_intr_disable(priv);
777         if (priv->irq_enabled == true) {
778                 cpsw_disable_irq(priv);
779                 priv->irq_enabled = false;
780         }
781 
782         if (netif_running(priv->ndev)) {
783                 napi_schedule(&priv->napi);
784                 return IRQ_HANDLED;
785         }
786 
787         priv = cpsw_get_slave_priv(priv, 1);
788         if (!priv)
789                 return IRQ_NONE;
790 
791         if (netif_running(priv->ndev)) {
792                 napi_schedule(&priv->napi);
793                 return IRQ_HANDLED;
794         }
795         return IRQ_NONE;
796 }
797 
798 static int cpsw_poll(struct napi_struct *napi, int budget)
799 {
800         struct cpsw_priv        *priv = napi_to_priv(napi);
801         int                     num_tx, num_rx;
802 
803         num_tx = cpdma_chan_process(priv->txch, 128);
804 
805         num_rx = cpdma_chan_process(priv->rxch, budget);
806         if (num_rx < budget) {
807                 struct cpsw_priv *prim_cpsw;
808 
809                 napi_complete(napi);
810                 cpsw_intr_enable(priv);
811                 prim_cpsw = cpsw_get_slave_priv(priv, 0);
812                 if (prim_cpsw->irq_enabled == false) {
813                         prim_cpsw->irq_enabled = true;
814                         cpsw_enable_irq(priv);
815                 }
816         }
817 
818         if (num_rx || num_tx)
819                 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
820                          num_rx, num_tx);
821 
822         return num_rx;
823 }
824 
825 static inline void soft_reset(const char *module, void __iomem *reg)
826 {
827         unsigned long timeout = jiffies + HZ;
828 
829         __raw_writel(1, reg);
830         do {
831                 cpu_relax();
832         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
833 
834         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
835 }
836 
837 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
838                          ((mac)[2] << 16) | ((mac)[3] << 24))
839 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
840 
841 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
842                                struct cpsw_priv *priv)
843 {
844         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
845         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
846 }
847 
848 static void _cpsw_adjust_link(struct cpsw_slave *slave,
849                               struct cpsw_priv *priv, bool *link)
850 {
851         struct phy_device       *phy = slave->phy;
852         u32                     mac_control = 0;
853         u32                     slave_port;
854 
855         if (!phy)
856                 return;
857 
858         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
859 
860         if (phy->link) {
861                 mac_control = priv->data.mac_control;
862 
863                 /* enable forwarding */
864                 cpsw_ale_control_set(priv->ale, slave_port,
865                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
866 
867                 if (phy->speed == 1000)
868                         mac_control |= BIT(7);  /* GIGABITEN    */
869                 if (phy->duplex)
870                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
871 
872                 /* set speed_in input in case RMII mode is used in 100Mbps */
873                 if (phy->speed == 100)
874                         mac_control |= BIT(15);
875                 else if (phy->speed == 10)
876                         mac_control |= BIT(18); /* In Band mode */
877 
878                 if (priv->rx_pause)
879                         mac_control |= BIT(3);
880 
881                 if (priv->tx_pause)
882                         mac_control |= BIT(4);
883 
884                 *link = true;
885         } else {
886                 mac_control = 0;
887                 /* disable forwarding */
888                 cpsw_ale_control_set(priv->ale, slave_port,
889                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
890         }
891 
892         if (mac_control != slave->mac_control) {
893                 phy_print_status(phy);
894                 __raw_writel(mac_control, &slave->sliver->mac_control);
895         }
896 
897         slave->mac_control = mac_control;
898 }
899 
900 static void cpsw_adjust_link(struct net_device *ndev)
901 {
902         struct cpsw_priv        *priv = netdev_priv(ndev);
903         bool                    link = false;
904 
905         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
906 
907         if (link) {
908                 netif_carrier_on(ndev);
909                 if (netif_running(ndev))
910                         netif_wake_queue(ndev);
911         } else {
912                 netif_carrier_off(ndev);
913                 netif_stop_queue(ndev);
914         }
915 }
916 
917 static int cpsw_get_coalesce(struct net_device *ndev,
918                                 struct ethtool_coalesce *coal)
919 {
920         struct cpsw_priv *priv = netdev_priv(ndev);
921 
922         coal->rx_coalesce_usecs = priv->coal_intvl;
923         return 0;
924 }
925 
926 static int cpsw_set_coalesce(struct net_device *ndev,
927                                 struct ethtool_coalesce *coal)
928 {
929         struct cpsw_priv *priv = netdev_priv(ndev);
930         u32 int_ctrl;
931         u32 num_interrupts = 0;
932         u32 prescale = 0;
933         u32 addnl_dvdr = 1;
934         u32 coal_intvl = 0;
935 
936         coal_intvl = coal->rx_coalesce_usecs;
937 
938         int_ctrl =  readl(&priv->wr_regs->int_control);
939         prescale = priv->bus_freq_mhz * 4;
940 
941         if (!coal->rx_coalesce_usecs) {
942                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
943                 goto update_return;
944         }
945 
946         if (coal_intvl < CPSW_CMINTMIN_INTVL)
947                 coal_intvl = CPSW_CMINTMIN_INTVL;
948 
949         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
950                 /* Interrupt pacer works with 4us Pulse, we can
951                  * throttle further by dilating the 4us pulse.
952                  */
953                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
954 
955                 if (addnl_dvdr > 1) {
956                         prescale *= addnl_dvdr;
957                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
958                                 coal_intvl = (CPSW_CMINTMAX_INTVL
959                                                 * addnl_dvdr);
960                 } else {
961                         addnl_dvdr = 1;
962                         coal_intvl = CPSW_CMINTMAX_INTVL;
963                 }
964         }
965 
966         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
967         writel(num_interrupts, &priv->wr_regs->rx_imax);
968         writel(num_interrupts, &priv->wr_regs->tx_imax);
969 
970         int_ctrl |= CPSW_INTPACEEN;
971         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
972         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
973 
974 update_return:
975         writel(int_ctrl, &priv->wr_regs->int_control);
976 
977         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
978         if (priv->data.dual_emac) {
979                 int i;
980 
981                 for (i = 0; i < priv->data.slaves; i++) {
982                         priv = netdev_priv(priv->slaves[i].ndev);
983                         priv->coal_intvl = coal_intvl;
984                 }
985         } else {
986                 priv->coal_intvl = coal_intvl;
987         }
988 
989         return 0;
990 }
991 
992 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
993 {
994         switch (sset) {
995         case ETH_SS_STATS:
996                 return CPSW_STATS_LEN;
997         default:
998                 return -EOPNOTSUPP;
999         }
1000 }
1001 
1002 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1003 {
1004         u8 *p = data;
1005         int i;
1006 
1007         switch (stringset) {
1008         case ETH_SS_STATS:
1009                 for (i = 0; i < CPSW_STATS_LEN; i++) {
1010                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
1011                                ETH_GSTRING_LEN);
1012                         p += ETH_GSTRING_LEN;
1013                 }
1014                 break;
1015         }
1016 }
1017 
1018 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1019                                     struct ethtool_stats *stats, u64 *data)
1020 {
1021         struct cpsw_priv *priv = netdev_priv(ndev);
1022         struct cpdma_chan_stats rx_stats;
1023         struct cpdma_chan_stats tx_stats;
1024         u32 val;
1025         u8 *p;
1026         int i;
1027 
1028         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1029         cpdma_chan_get_stats(priv->rxch, &rx_stats);
1030         cpdma_chan_get_stats(priv->txch, &tx_stats);
1031 
1032         for (i = 0; i < CPSW_STATS_LEN; i++) {
1033                 switch (cpsw_gstrings_stats[i].type) {
1034                 case CPSW_STATS:
1035                         val = readl(priv->hw_stats +
1036                                     cpsw_gstrings_stats[i].stat_offset);
1037                         data[i] = val;
1038                         break;
1039 
1040                 case CPDMA_RX_STATS:
1041                         p = (u8 *)&rx_stats +
1042                                 cpsw_gstrings_stats[i].stat_offset;
1043                         data[i] = *(u32 *)p;
1044                         break;
1045 
1046                 case CPDMA_TX_STATS:
1047                         p = (u8 *)&tx_stats +
1048                                 cpsw_gstrings_stats[i].stat_offset;
1049                         data[i] = *(u32 *)p;
1050                         break;
1051                 }
1052         }
1053 }
1054 
1055 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1056 {
1057         u32 i;
1058         u32 usage_count = 0;
1059 
1060         if (!priv->data.dual_emac)
1061                 return 0;
1062 
1063         for (i = 0; i < priv->data.slaves; i++)
1064                 if (priv->slaves[i].open_stat)
1065                         usage_count++;
1066 
1067         return usage_count;
1068 }
1069 
1070 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1071                         struct cpsw_priv *priv, struct sk_buff *skb)
1072 {
1073         if (!priv->data.dual_emac)
1074                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1075                                   skb->len, 0);
1076 
1077         if (ndev == cpsw_get_slave_ndev(priv, 0))
1078                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1079                                   skb->len, 1);
1080         else
1081                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1082                                   skb->len, 2);
1083 }
1084 
1085 static inline void cpsw_add_dual_emac_def_ale_entries(
1086                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1087                 u32 slave_port)
1088 {
1089         u32 port_mask = 1 << slave_port | 1 << priv->host_port;
1090 
1091         if (priv->version == CPSW_VERSION_1)
1092                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1093         else
1094                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1095         cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1096                           port_mask, port_mask, 0);
1097         cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1098                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1099         cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1100                 priv->host_port, ALE_VLAN, slave->port_vlan);
1101 }
1102 
1103 static void soft_reset_slave(struct cpsw_slave *slave)
1104 {
1105         char name[32];
1106 
1107         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1108         soft_reset(name, &slave->sliver->soft_reset);
1109 }
1110 
1111 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1112 {
1113         u32 slave_port;
1114 
1115         soft_reset_slave(slave);
1116 
1117         /* setup priority mapping */
1118         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1119 
1120         switch (priv->version) {
1121         case CPSW_VERSION_1:
1122                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1123                 break;
1124         case CPSW_VERSION_2:
1125         case CPSW_VERSION_3:
1126         case CPSW_VERSION_4:
1127                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1128                 break;
1129         }
1130 
1131         /* setup max packet size, and mac address */
1132         __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1133         cpsw_set_slave_mac(slave, priv);
1134 
1135         slave->mac_control = 0; /* no link yet */
1136 
1137         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1138 
1139         if (priv->data.dual_emac)
1140                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1141         else
1142                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1143                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1144 
1145         slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1146                                  &cpsw_adjust_link, slave->data->phy_if);
1147         if (IS_ERR(slave->phy)) {
1148                 dev_err(priv->dev, "phy %s not found on slave %d\n",
1149                         slave->data->phy_id, slave->slave_num);
1150                 slave->phy = NULL;
1151         } else {
1152                 dev_info(priv->dev, "phy found : id is : 0x%x\n",
1153                          slave->phy->phy_id);
1154                 phy_start(slave->phy);
1155 
1156                 /* Configure GMII_SEL register */
1157                 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
1158                              slave->slave_num);
1159         }
1160 }
1161 
1162 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1163 {
1164         const int vlan = priv->data.default_vlan;
1165         const int port = priv->host_port;
1166         u32 reg;
1167         int i;
1168         int unreg_mcast_mask;
1169 
1170         reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1171                CPSW2_PORT_VLAN;
1172 
1173         writel(vlan, &priv->host_port_regs->port_vlan);
1174 
1175         for (i = 0; i < priv->data.slaves; i++)
1176                 slave_write(priv->slaves + i, vlan, reg);
1177 
1178         if (priv->ndev->flags & IFF_ALLMULTI)
1179                 unreg_mcast_mask = ALE_ALL_PORTS;
1180         else
1181                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1182 
1183         cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1184                           ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1185                           unreg_mcast_mask << port);
1186 }
1187 
1188 static void cpsw_init_host_port(struct cpsw_priv *priv)
1189 {
1190         u32 control_reg;
1191         u32 fifo_mode;
1192 
1193         /* soft reset the controller and initialize ale */
1194         soft_reset("cpsw", &priv->regs->soft_reset);
1195         cpsw_ale_start(priv->ale);
1196 
1197         /* switch to vlan unaware mode */
1198         cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1199                              CPSW_ALE_VLAN_AWARE);
1200         control_reg = readl(&priv->regs->control);
1201         control_reg |= CPSW_VLAN_AWARE;
1202         writel(control_reg, &priv->regs->control);
1203         fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1204                      CPSW_FIFO_NORMAL_MODE;
1205         writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
1206 
1207         /* setup host port priority mapping */
1208         __raw_writel(CPDMA_TX_PRIORITY_MAP,
1209                      &priv->host_port_regs->cpdma_tx_pri_map);
1210         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1211 
1212         cpsw_ale_control_set(priv->ale, priv->host_port,
1213                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1214 
1215         if (!priv->data.dual_emac) {
1216                 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1217                                    0, 0);
1218                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1219                                    1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1220         }
1221 }
1222 
1223 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1224 {
1225         u32 slave_port;
1226 
1227         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1228 
1229         if (!slave->phy)
1230                 return;
1231         phy_stop(slave->phy);
1232         phy_disconnect(slave->phy);
1233         slave->phy = NULL;
1234         cpsw_ale_control_set(priv->ale, slave_port,
1235                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1236 }
1237 
1238 static int cpsw_ndo_open(struct net_device *ndev)
1239 {
1240         struct cpsw_priv *priv = netdev_priv(ndev);
1241         struct cpsw_priv *prim_cpsw;
1242         int i, ret;
1243         u32 reg;
1244 
1245         if (!cpsw_common_res_usage_state(priv))
1246                 cpsw_intr_disable(priv);
1247         netif_carrier_off(ndev);
1248 
1249         pm_runtime_get_sync(&priv->pdev->dev);
1250 
1251         reg = priv->version;
1252 
1253         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1254                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1255                  CPSW_RTL_VERSION(reg));
1256 
1257         /* initialize host and slave ports */
1258         if (!cpsw_common_res_usage_state(priv))
1259                 cpsw_init_host_port(priv);
1260         for_each_slave(priv, cpsw_slave_open, priv);
1261 
1262         /* Add default VLAN */
1263         if (!priv->data.dual_emac)
1264                 cpsw_add_default_vlan(priv);
1265         else
1266                 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1267                                   ALE_ALL_PORTS << priv->host_port,
1268                                   ALE_ALL_PORTS << priv->host_port, 0, 0);
1269 
1270         if (!cpsw_common_res_usage_state(priv)) {
1271                 /* setup tx dma to fixed prio and zero offset */
1272                 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1273                 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1274 
1275                 /* disable priority elevation */
1276                 __raw_writel(0, &priv->regs->ptype);
1277 
1278                 /* enable statistics collection only on all ports */
1279                 __raw_writel(0x7, &priv->regs->stat_port_en);
1280 
1281                 /* Enable internal fifo flow control */
1282                 writel(0x7, &priv->regs->flow_control);
1283 
1284                 if (WARN_ON(!priv->data.rx_descs))
1285                         priv->data.rx_descs = 128;
1286 
1287                 for (i = 0; i < priv->data.rx_descs; i++) {
1288                         struct sk_buff *skb;
1289 
1290                         ret = -ENOMEM;
1291                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1292                                         priv->rx_packet_max, GFP_KERNEL);
1293                         if (!skb)
1294                                 goto err_cleanup;
1295                         ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
1296                                         skb_tailroom(skb), 0);
1297                         if (ret < 0) {
1298                                 kfree_skb(skb);
1299                                 goto err_cleanup;
1300                         }
1301                 }
1302                 /* continue even if we didn't manage to submit all
1303                  * receive descs
1304                  */
1305                 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
1306 
1307                 if (cpts_register(&priv->pdev->dev, priv->cpts,
1308                                   priv->data.cpts_clock_mult,
1309                                   priv->data.cpts_clock_shift))
1310                         dev_err(priv->dev, "error registering cpts device\n");
1311 
1312         }
1313 
1314         /* Enable Interrupt pacing if configured */
1315         if (priv->coal_intvl != 0) {
1316                 struct ethtool_coalesce coal;
1317 
1318                 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1319                 cpsw_set_coalesce(ndev, &coal);
1320         }
1321 
1322         napi_enable(&priv->napi);
1323         cpdma_ctlr_start(priv->dma);
1324         cpsw_intr_enable(priv);
1325 
1326         prim_cpsw = cpsw_get_slave_priv(priv, 0);
1327         if (prim_cpsw->irq_enabled == false) {
1328                 if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) {
1329                         prim_cpsw->irq_enabled = true;
1330                         cpsw_enable_irq(prim_cpsw);
1331                 }
1332         }
1333 
1334         if (priv->data.dual_emac)
1335                 priv->slaves[priv->emac_port].open_stat = true;
1336         return 0;
1337 
1338 err_cleanup:
1339         cpdma_ctlr_stop(priv->dma);
1340         for_each_slave(priv, cpsw_slave_stop, priv);
1341         pm_runtime_put_sync(&priv->pdev->dev);
1342         netif_carrier_off(priv->ndev);
1343         return ret;
1344 }
1345 
1346 static int cpsw_ndo_stop(struct net_device *ndev)
1347 {
1348         struct cpsw_priv *priv = netdev_priv(ndev);
1349 
1350         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1351         netif_stop_queue(priv->ndev);
1352         napi_disable(&priv->napi);
1353         netif_carrier_off(priv->ndev);
1354 
1355         if (cpsw_common_res_usage_state(priv) <= 1) {
1356                 cpts_unregister(priv->cpts);
1357                 cpsw_intr_disable(priv);
1358                 cpdma_ctlr_int_ctrl(priv->dma, false);
1359                 cpdma_ctlr_stop(priv->dma);
1360                 cpsw_ale_stop(priv->ale);
1361         }
1362         for_each_slave(priv, cpsw_slave_stop, priv);
1363         pm_runtime_put_sync(&priv->pdev->dev);
1364         if (priv->data.dual_emac)
1365                 priv->slaves[priv->emac_port].open_stat = false;
1366         return 0;
1367 }
1368 
1369 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1370                                        struct net_device *ndev)
1371 {
1372         struct cpsw_priv *priv = netdev_priv(ndev);
1373         int ret;
1374 
1375         ndev->trans_start = jiffies;
1376 
1377         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1378                 cpsw_err(priv, tx_err, "packet pad failed\n");
1379                 ndev->stats.tx_dropped++;
1380                 return NETDEV_TX_OK;
1381         }
1382 
1383         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1384                                 priv->cpts->tx_enable)
1385                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1386 
1387         skb_tx_timestamp(skb);
1388 
1389         ret = cpsw_tx_packet_submit(ndev, priv, skb);
1390         if (unlikely(ret != 0)) {
1391                 cpsw_err(priv, tx_err, "desc submit failed\n");
1392                 goto fail;
1393         }
1394 
1395         /* If there is no more tx desc left free then we need to
1396          * tell the kernel to stop sending us tx frames.
1397          */
1398         if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1399                 netif_stop_queue(ndev);
1400 
1401         return NETDEV_TX_OK;
1402 fail:
1403         ndev->stats.tx_dropped++;
1404         netif_stop_queue(ndev);
1405         return NETDEV_TX_BUSY;
1406 }
1407 
1408 #ifdef CONFIG_TI_CPTS
1409 
1410 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1411 {
1412         struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1413         u32 ts_en, seq_id;
1414 
1415         if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1416                 slave_write(slave, 0, CPSW1_TS_CTL);
1417                 return;
1418         }
1419 
1420         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1421         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1422 
1423         if (priv->cpts->tx_enable)
1424                 ts_en |= CPSW_V1_TS_TX_EN;
1425 
1426         if (priv->cpts->rx_enable)
1427                 ts_en |= CPSW_V1_TS_RX_EN;
1428 
1429         slave_write(slave, ts_en, CPSW1_TS_CTL);
1430         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1431 }
1432 
1433 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1434 {
1435         struct cpsw_slave *slave;
1436         u32 ctrl, mtype;
1437 
1438         if (priv->data.dual_emac)
1439                 slave = &priv->slaves[priv->emac_port];
1440         else
1441                 slave = &priv->slaves[priv->data.active_slave];
1442 
1443         ctrl = slave_read(slave, CPSW2_CONTROL);
1444         switch (priv->version) {
1445         case CPSW_VERSION_2:
1446                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1447 
1448                 if (priv->cpts->tx_enable)
1449                         ctrl |= CTRL_V2_TX_TS_BITS;
1450 
1451                 if (priv->cpts->rx_enable)
1452                         ctrl |= CTRL_V2_RX_TS_BITS;
1453         break;
1454         case CPSW_VERSION_3:
1455         default:
1456                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1457 
1458                 if (priv->cpts->tx_enable)
1459                         ctrl |= CTRL_V3_TX_TS_BITS;
1460 
1461                 if (priv->cpts->rx_enable)
1462                         ctrl |= CTRL_V3_RX_TS_BITS;
1463         break;
1464         }
1465 
1466         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1467 
1468         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1469         slave_write(slave, ctrl, CPSW2_CONTROL);
1470         __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1471 }
1472 
1473 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1474 {
1475         struct cpsw_priv *priv = netdev_priv(dev);
1476         struct cpts *cpts = priv->cpts;
1477         struct hwtstamp_config cfg;
1478 
1479         if (priv->version != CPSW_VERSION_1 &&
1480             priv->version != CPSW_VERSION_2 &&
1481             priv->version != CPSW_VERSION_3)
1482                 return -EOPNOTSUPP;
1483 
1484         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1485                 return -EFAULT;
1486 
1487         /* reserved for future extensions */
1488         if (cfg.flags)
1489                 return -EINVAL;
1490 
1491         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1492                 return -ERANGE;
1493 
1494         switch (cfg.rx_filter) {
1495         case HWTSTAMP_FILTER_NONE:
1496                 cpts->rx_enable = 0;
1497                 break;
1498         case HWTSTAMP_FILTER_ALL:
1499         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1500         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1501         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1502                 return -ERANGE;
1503         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1504         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1505         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1506         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1507         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1508         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1509         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1510         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1511         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1512                 cpts->rx_enable = 1;
1513                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1514                 break;
1515         default:
1516                 return -ERANGE;
1517         }
1518 
1519         cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1520 
1521         switch (priv->version) {
1522         case CPSW_VERSION_1:
1523                 cpsw_hwtstamp_v1(priv);
1524                 break;
1525         case CPSW_VERSION_2:
1526         case CPSW_VERSION_3:
1527                 cpsw_hwtstamp_v2(priv);
1528                 break;
1529         default:
1530                 WARN_ON(1);
1531         }
1532 
1533         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1534 }
1535 
1536 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1537 {
1538         struct cpsw_priv *priv = netdev_priv(dev);
1539         struct cpts *cpts = priv->cpts;
1540         struct hwtstamp_config cfg;
1541 
1542         if (priv->version != CPSW_VERSION_1 &&
1543             priv->version != CPSW_VERSION_2 &&
1544             priv->version != CPSW_VERSION_3)
1545                 return -EOPNOTSUPP;
1546 
1547         cfg.flags = 0;
1548         cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1549         cfg.rx_filter = (cpts->rx_enable ?
1550                          HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1551 
1552         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1553 }
1554 
1555 #endif /*CONFIG_TI_CPTS*/
1556 
1557 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1558 {
1559         struct cpsw_priv *priv = netdev_priv(dev);
1560         int slave_no = cpsw_slave_index(priv);
1561 
1562         if (!netif_running(dev))
1563                 return -EINVAL;
1564 
1565         switch (cmd) {
1566 #ifdef CONFIG_TI_CPTS
1567         case SIOCSHWTSTAMP:
1568                 return cpsw_hwtstamp_set(dev, req);
1569         case SIOCGHWTSTAMP:
1570                 return cpsw_hwtstamp_get(dev, req);
1571 #endif
1572         }
1573 
1574         if (!priv->slaves[slave_no].phy)
1575                 return -EOPNOTSUPP;
1576         return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
1577 }
1578 
1579 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1580 {
1581         struct cpsw_priv *priv = netdev_priv(ndev);
1582 
1583         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1584         ndev->stats.tx_errors++;
1585         cpsw_intr_disable(priv);
1586         cpdma_ctlr_int_ctrl(priv->dma, false);
1587         cpdma_chan_stop(priv->txch);
1588         cpdma_chan_start(priv->txch);
1589         cpdma_ctlr_int_ctrl(priv->dma, true);
1590         cpsw_intr_enable(priv);
1591 }
1592 
1593 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1594 {
1595         struct cpsw_priv *priv = netdev_priv(ndev);
1596         struct sockaddr *addr = (struct sockaddr *)p;
1597         int flags = 0;
1598         u16 vid = 0;
1599 
1600         if (!is_valid_ether_addr(addr->sa_data))
1601                 return -EADDRNOTAVAIL;
1602 
1603         if (priv->data.dual_emac) {
1604                 vid = priv->slaves[priv->emac_port].port_vlan;
1605                 flags = ALE_VLAN;
1606         }
1607 
1608         cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1609                            flags, vid);
1610         cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1611                            flags, vid);
1612 
1613         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1614         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1615         for_each_slave(priv, cpsw_set_slave_mac, priv);
1616 
1617         return 0;
1618 }
1619 
1620 #ifdef CONFIG_NET_POLL_CONTROLLER
1621 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1622 {
1623         struct cpsw_priv *priv = netdev_priv(ndev);
1624 
1625         cpsw_intr_disable(priv);
1626         cpdma_ctlr_int_ctrl(priv->dma, false);
1627         cpsw_interrupt(ndev->irq, priv);
1628         cpdma_ctlr_int_ctrl(priv->dma, true);
1629         cpsw_intr_enable(priv);
1630 }
1631 #endif
1632 
1633 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1634                                 unsigned short vid)
1635 {
1636         int ret;
1637         int unreg_mcast_mask = 0;
1638         u32 port_mask;
1639 
1640         if (priv->data.dual_emac) {
1641                 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1642 
1643                 if (priv->ndev->flags & IFF_ALLMULTI)
1644                         unreg_mcast_mask = port_mask;
1645         } else {
1646                 port_mask = ALE_ALL_PORTS;
1647 
1648                 if (priv->ndev->flags & IFF_ALLMULTI)
1649                         unreg_mcast_mask = ALE_ALL_PORTS;
1650                 else
1651                         unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1652         }
1653 
1654         ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask,
1655                                 unreg_mcast_mask << priv->host_port);
1656         if (ret != 0)
1657                 return ret;
1658 
1659         ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1660                                  priv->host_port, ALE_VLAN, vid);
1661         if (ret != 0)
1662                 goto clean_vid;
1663 
1664         ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1665                                  port_mask, ALE_VLAN, vid, 0);
1666         if (ret != 0)
1667                 goto clean_vlan_ucast;
1668         return 0;
1669 
1670 clean_vlan_ucast:
1671         cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1672                             priv->host_port, ALE_VLAN, vid);
1673 clean_vid:
1674         cpsw_ale_del_vlan(priv->ale, vid, 0);
1675         return ret;
1676 }
1677 
1678 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1679                                     __be16 proto, u16 vid)
1680 {
1681         struct cpsw_priv *priv = netdev_priv(ndev);
1682 
1683         if (vid == priv->data.default_vlan)
1684                 return 0;
1685 
1686         if (priv->data.dual_emac) {
1687                 /* In dual EMAC, reserved VLAN id should not be used for
1688                  * creating VLAN interfaces as this can break the dual
1689                  * EMAC port separation
1690                  */
1691                 int i;
1692 
1693                 for (i = 0; i < priv->data.slaves; i++) {
1694                         if (vid == priv->slaves[i].port_vlan)
1695                                 return -EINVAL;
1696                 }
1697         }
1698 
1699         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1700         return cpsw_add_vlan_ale_entry(priv, vid);
1701 }
1702 
1703 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1704                                      __be16 proto, u16 vid)
1705 {
1706         struct cpsw_priv *priv = netdev_priv(ndev);
1707         int ret;
1708 
1709         if (vid == priv->data.default_vlan)
1710                 return 0;
1711 
1712         if (priv->data.dual_emac) {
1713                 int i;
1714 
1715                 for (i = 0; i < priv->data.slaves; i++) {
1716                         if (vid == priv->slaves[i].port_vlan)
1717                                 return -EINVAL;
1718                 }
1719         }
1720 
1721         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1722         ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1723         if (ret != 0)
1724                 return ret;
1725 
1726         ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1727                                  priv->host_port, ALE_VLAN, vid);
1728         if (ret != 0)
1729                 return ret;
1730 
1731         return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1732                                   0, ALE_VLAN, vid);
1733 }
1734 
1735 static const struct net_device_ops cpsw_netdev_ops = {
1736         .ndo_open               = cpsw_ndo_open,
1737         .ndo_stop               = cpsw_ndo_stop,
1738         .ndo_start_xmit         = cpsw_ndo_start_xmit,
1739         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
1740         .ndo_do_ioctl           = cpsw_ndo_ioctl,
1741         .ndo_validate_addr      = eth_validate_addr,
1742         .ndo_change_mtu         = eth_change_mtu,
1743         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
1744         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
1745 #ifdef CONFIG_NET_POLL_CONTROLLER
1746         .ndo_poll_controller    = cpsw_ndo_poll_controller,
1747 #endif
1748         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
1749         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
1750 };
1751 
1752 static int cpsw_get_regs_len(struct net_device *ndev)
1753 {
1754         struct cpsw_priv *priv = netdev_priv(ndev);
1755 
1756         return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1757 }
1758 
1759 static void cpsw_get_regs(struct net_device *ndev,
1760                           struct ethtool_regs *regs, void *p)
1761 {
1762         struct cpsw_priv *priv = netdev_priv(ndev);
1763         u32 *reg = p;
1764 
1765         /* update CPSW IP version */
1766         regs->version = priv->version;
1767 
1768         cpsw_ale_dump(priv->ale, reg);
1769 }
1770 
1771 static void cpsw_get_drvinfo(struct net_device *ndev,
1772                              struct ethtool_drvinfo *info)
1773 {
1774         struct cpsw_priv *priv = netdev_priv(ndev);
1775 
1776         strlcpy(info->driver, "cpsw", sizeof(info->driver));
1777         strlcpy(info->version, "1.0", sizeof(info->version));
1778         strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1779         info->regdump_len = cpsw_get_regs_len(ndev);
1780 }
1781 
1782 static u32 cpsw_get_msglevel(struct net_device *ndev)
1783 {
1784         struct cpsw_priv *priv = netdev_priv(ndev);
1785         return priv->msg_enable;
1786 }
1787 
1788 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1789 {
1790         struct cpsw_priv *priv = netdev_priv(ndev);
1791         priv->msg_enable = value;
1792 }
1793 
1794 static int cpsw_get_ts_info(struct net_device *ndev,
1795                             struct ethtool_ts_info *info)
1796 {
1797 #ifdef CONFIG_TI_CPTS
1798         struct cpsw_priv *priv = netdev_priv(ndev);
1799 
1800         info->so_timestamping =
1801                 SOF_TIMESTAMPING_TX_HARDWARE |
1802                 SOF_TIMESTAMPING_TX_SOFTWARE |
1803                 SOF_TIMESTAMPING_RX_HARDWARE |
1804                 SOF_TIMESTAMPING_RX_SOFTWARE |
1805                 SOF_TIMESTAMPING_SOFTWARE |
1806                 SOF_TIMESTAMPING_RAW_HARDWARE;
1807         info->phc_index = priv->cpts->phc_index;
1808         info->tx_types =
1809                 (1 << HWTSTAMP_TX_OFF) |
1810                 (1 << HWTSTAMP_TX_ON);
1811         info->rx_filters =
1812                 (1 << HWTSTAMP_FILTER_NONE) |
1813                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1814 #else
1815         info->so_timestamping =
1816                 SOF_TIMESTAMPING_TX_SOFTWARE |
1817                 SOF_TIMESTAMPING_RX_SOFTWARE |
1818                 SOF_TIMESTAMPING_SOFTWARE;
1819         info->phc_index = -1;
1820         info->tx_types = 0;
1821         info->rx_filters = 0;
1822 #endif
1823         return 0;
1824 }
1825 
1826 static int cpsw_get_settings(struct net_device *ndev,
1827                              struct ethtool_cmd *ecmd)
1828 {
1829         struct cpsw_priv *priv = netdev_priv(ndev);
1830         int slave_no = cpsw_slave_index(priv);
1831 
1832         if (priv->slaves[slave_no].phy)
1833                 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1834         else
1835                 return -EOPNOTSUPP;
1836 }
1837 
1838 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1839 {
1840         struct cpsw_priv *priv = netdev_priv(ndev);
1841         int slave_no = cpsw_slave_index(priv);
1842 
1843         if (priv->slaves[slave_no].phy)
1844                 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1845         else
1846                 return -EOPNOTSUPP;
1847 }
1848 
1849 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1850 {
1851         struct cpsw_priv *priv = netdev_priv(ndev);
1852         int slave_no = cpsw_slave_index(priv);
1853 
1854         wol->supported = 0;
1855         wol->wolopts = 0;
1856 
1857         if (priv->slaves[slave_no].phy)
1858                 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1859 }
1860 
1861 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1862 {
1863         struct cpsw_priv *priv = netdev_priv(ndev);
1864         int slave_no = cpsw_slave_index(priv);
1865 
1866         if (priv->slaves[slave_no].phy)
1867                 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1868         else
1869                 return -EOPNOTSUPP;
1870 }
1871 
1872 static void cpsw_get_pauseparam(struct net_device *ndev,
1873                                 struct ethtool_pauseparam *pause)
1874 {
1875         struct cpsw_priv *priv = netdev_priv(ndev);
1876 
1877         pause->autoneg = AUTONEG_DISABLE;
1878         pause->rx_pause = priv->rx_pause ? true : false;
1879         pause->tx_pause = priv->tx_pause ? true : false;
1880 }
1881 
1882 static int cpsw_set_pauseparam(struct net_device *ndev,
1883                                struct ethtool_pauseparam *pause)
1884 {
1885         struct cpsw_priv *priv = netdev_priv(ndev);
1886         bool link;
1887 
1888         priv->rx_pause = pause->rx_pause ? true : false;
1889         priv->tx_pause = pause->tx_pause ? true : false;
1890 
1891         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1892 
1893         return 0;
1894 }
1895 
1896 static const struct ethtool_ops cpsw_ethtool_ops = {
1897         .get_drvinfo    = cpsw_get_drvinfo,
1898         .get_msglevel   = cpsw_get_msglevel,
1899         .set_msglevel   = cpsw_set_msglevel,
1900         .get_link       = ethtool_op_get_link,
1901         .get_ts_info    = cpsw_get_ts_info,
1902         .get_settings   = cpsw_get_settings,
1903         .set_settings   = cpsw_set_settings,
1904         .get_coalesce   = cpsw_get_coalesce,
1905         .set_coalesce   = cpsw_set_coalesce,
1906         .get_sset_count         = cpsw_get_sset_count,
1907         .get_strings            = cpsw_get_strings,
1908         .get_ethtool_stats      = cpsw_get_ethtool_stats,
1909         .get_pauseparam         = cpsw_get_pauseparam,
1910         .set_pauseparam         = cpsw_set_pauseparam,
1911         .get_wol        = cpsw_get_wol,
1912         .set_wol        = cpsw_set_wol,
1913         .get_regs_len   = cpsw_get_regs_len,
1914         .get_regs       = cpsw_get_regs,
1915 };
1916 
1917 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1918                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
1919 {
1920         void __iomem            *regs = priv->regs;
1921         int                     slave_num = slave->slave_num;
1922         struct cpsw_slave_data  *data = priv->data.slave_data + slave_num;
1923 
1924         slave->data     = data;
1925         slave->regs     = regs + slave_reg_ofs;
1926         slave->sliver   = regs + sliver_reg_ofs;
1927         slave->port_vlan = data->dual_emac_res_vlan;
1928 }
1929 
1930 #define AM33XX_CTRL_MAC_LO_REG(id) (0x630 + 0x8 * id)
1931 #define AM33XX_CTRL_MAC_HI_REG(id) (0x630 + 0x8 * id + 0x4)
1932 
1933 static int cpsw_am33xx_cm_get_macid(struct device *dev, int slave,
1934                 u8 *mac_addr)
1935 {
1936         u32 macid_lo;
1937         u32 macid_hi;
1938         struct regmap *syscon;
1939 
1940         syscon = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon");
1941         if (IS_ERR(syscon)) {
1942                 if (PTR_ERR(syscon) == -ENODEV)
1943                         return 0;
1944                 return PTR_ERR(syscon);
1945         }
1946 
1947         regmap_read(syscon, AM33XX_CTRL_MAC_LO_REG(slave), &macid_lo);
1948         regmap_read(syscon, AM33XX_CTRL_MAC_HI_REG(slave), &macid_hi);
1949 
1950         mac_addr[5] = (macid_lo >> 8) & 0xff;
1951         mac_addr[4] = macid_lo & 0xff;
1952         mac_addr[3] = (macid_hi >> 24) & 0xff;
1953         mac_addr[2] = (macid_hi >> 16) & 0xff;
1954         mac_addr[1] = (macid_hi >> 8) & 0xff;
1955         mac_addr[0] = macid_hi & 0xff;
1956 
1957         return 0;
1958 }
1959 
1960 static int cpsw_probe_dt(struct cpsw_platform_data *data,
1961                          struct platform_device *pdev)
1962 {
1963         struct device_node *node = pdev->dev.of_node;
1964         struct device_node *slave_node;
1965         int i = 0, ret;
1966         u32 prop;
1967 
1968         if (!node)
1969                 return -EINVAL;
1970 
1971         if (of_property_read_u32(node, "slaves", &prop)) {
1972                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
1973                 return -EINVAL;
1974         }
1975         data->slaves = prop;
1976 
1977         if (of_property_read_u32(node, "active_slave", &prop)) {
1978                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
1979                 return -EINVAL;
1980         }
1981         data->active_slave = prop;
1982 
1983         if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1984                 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
1985                 return -EINVAL;
1986         }
1987         data->cpts_clock_mult = prop;
1988 
1989         if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1990                 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
1991                 return -EINVAL;
1992         }
1993         data->cpts_clock_shift = prop;
1994 
1995         data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1996                                         * sizeof(struct cpsw_slave_data),
1997                                         GFP_KERNEL);
1998         if (!data->slave_data)
1999                 return -ENOMEM;
2000 
2001         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
2002                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
2003                 return -EINVAL;
2004         }
2005         data->channels = prop;
2006 
2007         if (of_property_read_u32(node, "ale_entries", &prop)) {
2008                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
2009                 return -EINVAL;
2010         }
2011         data->ale_entries = prop;
2012 
2013         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
2014                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
2015                 return -EINVAL;
2016         }
2017         data->bd_ram_size = prop;
2018 
2019         if (of_property_read_u32(node, "rx_descs", &prop)) {
2020                 dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
2021                 return -EINVAL;
2022         }
2023         data->rx_descs = prop;
2024 
2025         if (of_property_read_u32(node, "mac_control", &prop)) {
2026                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2027                 return -EINVAL;
2028         }
2029         data->mac_control = prop;
2030 
2031         if (of_property_read_bool(node, "dual_emac"))
2032                 data->dual_emac = 1;
2033 
2034         /*
2035          * Populate all the child nodes here...
2036          */
2037         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2038         /* We do not want to force this, as in some cases may not have child */
2039         if (ret)
2040                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2041 
2042         for_each_child_of_node(node, slave_node) {
2043                 struct cpsw_slave_data *slave_data = data->slave_data + i;
2044                 const void *mac_addr = NULL;
2045                 u32 phyid;
2046                 int lenp;
2047                 const __be32 *parp;
2048                 struct device_node *mdio_node;
2049                 struct platform_device *mdio;
2050 
2051                 /* This is no slave child node, continue */
2052                 if (strcmp(slave_node->name, "slave"))
2053                         continue;
2054 
2055                 parp = of_get_property(slave_node, "phy_id", &lenp);
2056                 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
2057                         dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i);
2058                         goto no_phy_slave;
2059                 }
2060                 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2061                 phyid = be32_to_cpup(parp+1);
2062                 mdio = of_find_device_by_node(mdio_node);
2063                 of_node_put(mdio_node);
2064                 if (!mdio) {
2065                         dev_err(&pdev->dev, "Missing mdio platform device\n");
2066                         return -EINVAL;
2067                 }
2068                 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2069                          PHY_ID_FMT, mdio->name, phyid);
2070 
2071                 slave_data->phy_if = of_get_phy_mode(slave_node);
2072                 if (slave_data->phy_if < 0) {
2073                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2074                                 i);
2075                         return slave_data->phy_if;
2076                 }
2077 
2078 no_phy_slave:
2079                 mac_addr = of_get_mac_address(slave_node);
2080                 if (mac_addr) {
2081                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2082                 } else {
2083                         if (of_machine_is_compatible("ti,am33xx")) {
2084                                 ret = cpsw_am33xx_cm_get_macid(&pdev->dev, i,
2085                                                         slave_data->mac_addr);
2086                                 if (ret)
2087                                         return ret;
2088                         }
2089                 }
2090                 if (data->dual_emac) {
2091                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2092                                                  &prop)) {
2093                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2094                                 slave_data->dual_emac_res_vlan = i+1;
2095                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2096                                         slave_data->dual_emac_res_vlan, i);
2097                         } else {
2098                                 slave_data->dual_emac_res_vlan = prop;
2099                         }
2100                 }
2101 
2102                 i++;
2103                 if (i == data->slaves)
2104                         break;
2105         }
2106 
2107         return 0;
2108 }
2109 
2110 static int cpsw_probe_dual_emac(struct platform_device *pdev,
2111                                 struct cpsw_priv *priv)
2112 {
2113         struct cpsw_platform_data       *data = &priv->data;
2114         struct net_device               *ndev;
2115         struct cpsw_priv                *priv_sl2;
2116         int ret = 0, i;
2117 
2118         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2119         if (!ndev) {
2120                 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
2121                 return -ENOMEM;
2122         }
2123 
2124         priv_sl2 = netdev_priv(ndev);
2125         spin_lock_init(&priv_sl2->lock);
2126         priv_sl2->data = *data;
2127         priv_sl2->pdev = pdev;
2128         priv_sl2->ndev = ndev;
2129         priv_sl2->dev  = &ndev->dev;
2130         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2131         priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2132 
2133         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2134                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2135                         ETH_ALEN);
2136                 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
2137         } else {
2138                 random_ether_addr(priv_sl2->mac_addr);
2139                 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
2140         }
2141         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2142 
2143         priv_sl2->slaves = priv->slaves;
2144         priv_sl2->clk = priv->clk;
2145 
2146         priv_sl2->coal_intvl = 0;
2147         priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2148 
2149         priv_sl2->regs = priv->regs;
2150         priv_sl2->host_port = priv->host_port;
2151         priv_sl2->host_port_regs = priv->host_port_regs;
2152         priv_sl2->wr_regs = priv->wr_regs;
2153         priv_sl2->hw_stats = priv->hw_stats;
2154         priv_sl2->dma = priv->dma;
2155         priv_sl2->txch = priv->txch;
2156         priv_sl2->rxch = priv->rxch;
2157         priv_sl2->ale = priv->ale;
2158         priv_sl2->emac_port = 1;
2159         priv->slaves[1].ndev = ndev;
2160         priv_sl2->cpts = priv->cpts;
2161         priv_sl2->version = priv->version;
2162 
2163         for (i = 0; i < priv->num_irqs; i++) {
2164                 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2165                 priv_sl2->num_irqs = priv->num_irqs;
2166         }
2167         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2168 
2169         ndev->netdev_ops = &cpsw_netdev_ops;
2170         ndev->ethtool_ops = &cpsw_ethtool_ops;
2171         netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2172 
2173         /* register the network device */
2174         SET_NETDEV_DEV(ndev, &pdev->dev);
2175         ret = register_netdev(ndev);
2176         if (ret) {
2177                 dev_err(&pdev->dev, "cpsw: error registering net device\n");
2178                 free_netdev(ndev);
2179                 ret = -ENODEV;
2180         }
2181 
2182         return ret;
2183 }
2184 
2185 static int cpsw_probe(struct platform_device *pdev)
2186 {
2187         struct cpsw_platform_data       *data;
2188         struct net_device               *ndev;
2189         struct cpsw_priv                *priv;
2190         struct cpdma_params             dma_params;
2191         struct cpsw_ale_params          ale_params;
2192         void __iomem                    *ss_regs;
2193         struct resource                 *res, *ss_res;
2194         u32 slave_offset, sliver_offset, slave_size;
2195         int ret = 0, i, k = 0;
2196 
2197         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2198         if (!ndev) {
2199                 dev_err(&pdev->dev, "error allocating net_device\n");
2200                 return -ENOMEM;
2201         }
2202 
2203         platform_set_drvdata(pdev, ndev);
2204         priv = netdev_priv(ndev);
2205         spin_lock_init(&priv->lock);
2206         priv->pdev = pdev;
2207         priv->ndev = ndev;
2208         priv->dev  = &ndev->dev;
2209         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2210         priv->rx_packet_max = max(rx_packet_max, 128);
2211         priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2212         priv->irq_enabled = true;
2213         if (!priv->cpts) {
2214                 dev_err(&pdev->dev, "error allocating cpts\n");
2215                 ret = -ENOMEM;
2216                 goto clean_ndev_ret;
2217         }
2218 
2219         /*
2220          * This may be required here for child devices.
2221          */
2222         pm_runtime_enable(&pdev->dev);
2223 
2224         /* Select default pin state */
2225         pinctrl_pm_select_default_state(&pdev->dev);
2226 
2227         if (cpsw_probe_dt(&priv->data, pdev)) {
2228                 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2229                 ret = -ENODEV;
2230                 goto clean_runtime_disable_ret;
2231         }
2232         data = &priv->data;
2233 
2234         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2235                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2236                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2237         } else {
2238                 eth_random_addr(priv->mac_addr);
2239                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2240         }
2241 
2242         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2243 
2244         priv->slaves = devm_kzalloc(&pdev->dev,
2245                                     sizeof(struct cpsw_slave) * data->slaves,
2246                                     GFP_KERNEL);
2247         if (!priv->slaves) {
2248                 ret = -ENOMEM;
2249                 goto clean_runtime_disable_ret;
2250         }
2251         for (i = 0; i < data->slaves; i++)
2252                 priv->slaves[i].slave_num = i;
2253 
2254         priv->slaves[0].ndev = ndev;
2255         priv->emac_port = 0;
2256 
2257         priv->clk = devm_clk_get(&pdev->dev, "fck");
2258         if (IS_ERR(priv->clk)) {
2259                 dev_err(priv->dev, "fck is not found\n");
2260                 ret = -ENODEV;
2261                 goto clean_runtime_disable_ret;
2262         }
2263         priv->coal_intvl = 0;
2264         priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
2265 
2266         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2267         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2268         if (IS_ERR(ss_regs)) {
2269                 ret = PTR_ERR(ss_regs);
2270                 goto clean_runtime_disable_ret;
2271         }
2272         priv->regs = ss_regs;
2273         priv->host_port = HOST_PORT_NUM;
2274 
2275         /* Need to enable clocks with runtime PM api to access module
2276          * registers
2277          */
2278         pm_runtime_get_sync(&pdev->dev);
2279         priv->version = readl(&priv->regs->id_ver);
2280         pm_runtime_put_sync(&pdev->dev);
2281 
2282         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2283         priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2284         if (IS_ERR(priv->wr_regs)) {
2285                 ret = PTR_ERR(priv->wr_regs);
2286                 goto clean_runtime_disable_ret;
2287         }
2288 
2289         memset(&dma_params, 0, sizeof(dma_params));
2290         memset(&ale_params, 0, sizeof(ale_params));
2291 
2292         switch (priv->version) {
2293         case CPSW_VERSION_1:
2294                 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2295                 priv->cpts->reg      = ss_regs + CPSW1_CPTS_OFFSET;
2296                 priv->hw_stats       = ss_regs + CPSW1_HW_STATS;
2297                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
2298                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
2299                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
2300                 slave_offset         = CPSW1_SLAVE_OFFSET;
2301                 slave_size           = CPSW1_SLAVE_SIZE;
2302                 sliver_offset        = CPSW1_SLIVER_OFFSET;
2303                 dma_params.desc_mem_phys = 0;
2304                 break;
2305         case CPSW_VERSION_2:
2306         case CPSW_VERSION_3:
2307         case CPSW_VERSION_4:
2308                 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2309                 priv->cpts->reg      = ss_regs + CPSW2_CPTS_OFFSET;
2310                 priv->hw_stats       = ss_regs + CPSW2_HW_STATS;
2311                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
2312                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
2313                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
2314                 slave_offset         = CPSW2_SLAVE_OFFSET;
2315                 slave_size           = CPSW2_SLAVE_SIZE;
2316                 sliver_offset        = CPSW2_SLIVER_OFFSET;
2317                 dma_params.desc_mem_phys =
2318                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2319                 break;
2320         default:
2321                 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2322                 ret = -ENODEV;
2323                 goto clean_runtime_disable_ret;
2324         }
2325         for (i = 0; i < priv->data.slaves; i++) {
2326                 struct cpsw_slave *slave = &priv->slaves[i];
2327                 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2328                 slave_offset  += slave_size;
2329                 sliver_offset += SLIVER_SIZE;
2330         }
2331 
2332         dma_params.dev          = &pdev->dev;
2333         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
2334         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
2335         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
2336         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
2337         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
2338 
2339         dma_params.num_chan             = data->channels;
2340         dma_params.has_soft_reset       = true;
2341         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
2342         dma_params.desc_mem_size        = data->bd_ram_size;
2343         dma_params.desc_align           = 16;
2344         dma_params.has_ext_regs         = true;
2345         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
2346 
2347         priv->dma = cpdma_ctlr_create(&dma_params);
2348         if (!priv->dma) {
2349                 dev_err(priv->dev, "error initializing dma\n");
2350                 ret = -ENOMEM;
2351                 goto clean_runtime_disable_ret;
2352         }
2353 
2354         priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2355                                        cpsw_tx_handler);
2356         priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2357                                        cpsw_rx_handler);
2358 
2359         if (WARN_ON(!priv->txch || !priv->rxch)) {
2360                 dev_err(priv->dev, "error initializing dma channels\n");
2361                 ret = -ENOMEM;
2362                 goto clean_dma_ret;
2363         }
2364 
2365         ale_params.dev                  = &ndev->dev;
2366         ale_params.ale_ageout           = ale_ageout;
2367         ale_params.ale_entries          = data->ale_entries;
2368         ale_params.ale_ports            = data->slaves;
2369 
2370         priv->ale = cpsw_ale_create(&ale_params);
2371         if (!priv->ale) {
2372                 dev_err(priv->dev, "error initializing ale engine\n");
2373                 ret = -ENODEV;
2374                 goto clean_dma_ret;
2375         }
2376 
2377         ndev->irq = platform_get_irq(pdev, 0);
2378         if (ndev->irq < 0) {
2379                 dev_err(priv->dev, "error getting irq resource\n");
2380                 ret = -ENOENT;
2381                 goto clean_ale_ret;
2382         }
2383 
2384         while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
2385                 if (k >= ARRAY_SIZE(priv->irqs_table)) {
2386                         ret = -EINVAL;
2387                         goto clean_ale_ret;
2388                 }
2389 
2390                 ret = devm_request_irq(&pdev->dev, res->start, cpsw_interrupt,
2391                                        0, dev_name(&pdev->dev), priv);
2392                 if (ret < 0) {
2393                         dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2394                         goto clean_ale_ret;
2395                 }
2396 
2397                 priv->irqs_table[k] = res->start;
2398                 k++;
2399         }
2400 
2401         priv->num_irqs = k;
2402 
2403         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2404 
2405         ndev->netdev_ops = &cpsw_netdev_ops;
2406         ndev->ethtool_ops = &cpsw_ethtool_ops;
2407         netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2408 
2409         /* register the network device */
2410         SET_NETDEV_DEV(ndev, &pdev->dev);
2411         ret = register_netdev(ndev);
2412         if (ret) {
2413                 dev_err(priv->dev, "error registering net device\n");
2414                 ret = -ENODEV;
2415                 goto clean_ale_ret;
2416         }
2417 
2418         cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2419                     &ss_res->start, ndev->irq);
2420 
2421         if (priv->data.dual_emac) {
2422                 ret = cpsw_probe_dual_emac(pdev, priv);
2423                 if (ret) {
2424                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2425                         goto clean_ale_ret;
2426                 }
2427         }
2428 
2429         return 0;
2430 
2431 clean_ale_ret:
2432         cpsw_ale_destroy(priv->ale);
2433 clean_dma_ret:
2434         cpdma_chan_destroy(priv->txch);
2435         cpdma_chan_destroy(priv->rxch);
2436         cpdma_ctlr_destroy(priv->dma);
2437 clean_runtime_disable_ret:
2438         pm_runtime_disable(&pdev->dev);
2439 clean_ndev_ret:
2440         free_netdev(priv->ndev);
2441         return ret;
2442 }
2443 
2444 static int cpsw_remove_child_device(struct device *dev, void *c)
2445 {
2446         struct platform_device *pdev = to_platform_device(dev);
2447 
2448         of_device_unregister(pdev);
2449 
2450         return 0;
2451 }
2452 
2453 static int cpsw_remove(struct platform_device *pdev)
2454 {
2455         struct net_device *ndev = platform_get_drvdata(pdev);
2456         struct cpsw_priv *priv = netdev_priv(ndev);
2457 
2458         if (priv->data.dual_emac)
2459                 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2460         unregister_netdev(ndev);
2461 
2462         cpsw_ale_destroy(priv->ale);
2463         cpdma_chan_destroy(priv->txch);
2464         cpdma_chan_destroy(priv->rxch);
2465         cpdma_ctlr_destroy(priv->dma);
2466         pm_runtime_disable(&pdev->dev);
2467         device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device);
2468         if (priv->data.dual_emac)
2469                 free_netdev(cpsw_get_slave_ndev(priv, 1));
2470         free_netdev(ndev);
2471         return 0;
2472 }
2473 
2474 static int cpsw_suspend(struct device *dev)
2475 {
2476         struct platform_device  *pdev = to_platform_device(dev);
2477         struct net_device       *ndev = platform_get_drvdata(pdev);
2478         struct cpsw_priv        *priv = netdev_priv(ndev);
2479 
2480         if (priv->data.dual_emac) {
2481                 int i;
2482 
2483                 for (i = 0; i < priv->data.slaves; i++) {
2484                         if (netif_running(priv->slaves[i].ndev))
2485                                 cpsw_ndo_stop(priv->slaves[i].ndev);
2486                         soft_reset_slave(priv->slaves + i);
2487                 }
2488         } else {
2489                 if (netif_running(ndev))
2490                         cpsw_ndo_stop(ndev);
2491                 for_each_slave(priv, soft_reset_slave);
2492         }
2493 
2494         pm_runtime_put_sync(&pdev->dev);
2495 
2496         /* Select sleep pin state */
2497         pinctrl_pm_select_sleep_state(&pdev->dev);
2498 
2499         return 0;
2500 }
2501 
2502 static int cpsw_resume(struct device *dev)
2503 {
2504         struct platform_device  *pdev = to_platform_device(dev);
2505         struct net_device       *ndev = platform_get_drvdata(pdev);
2506         struct cpsw_priv        *priv = netdev_priv(ndev);
2507 
2508         pm_runtime_get_sync(&pdev->dev);
2509 
2510         /* Select default pin state */
2511         pinctrl_pm_select_default_state(&pdev->dev);
2512 
2513         if (priv->data.dual_emac) {
2514                 int i;
2515 
2516                 for (i = 0; i < priv->data.slaves; i++) {
2517                         if (netif_running(priv->slaves[i].ndev))
2518                                 cpsw_ndo_open(priv->slaves[i].ndev);
2519                 }
2520         } else {
2521                 if (netif_running(ndev))
2522                         cpsw_ndo_open(ndev);
2523         }
2524         return 0;
2525 }
2526 
2527 static const struct dev_pm_ops cpsw_pm_ops = {
2528         .suspend        = cpsw_suspend,
2529         .resume         = cpsw_resume,
2530 };
2531 
2532 static const struct of_device_id cpsw_of_mtable[] = {
2533         { .compatible = "ti,cpsw", },
2534         { /* sentinel */ },
2535 };
2536 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2537 
2538 static struct platform_driver cpsw_driver = {
2539         .driver = {
2540                 .name    = "cpsw",
2541                 .pm      = &cpsw_pm_ops,
2542                 .of_match_table = cpsw_of_mtable,
2543         },
2544         .probe = cpsw_probe,
2545         .remove = cpsw_remove,
2546 };
2547 
2548 static int __init cpsw_init(void)
2549 {
2550         return platform_driver_register(&cpsw_driver);
2551 }
2552 late_initcall(cpsw_init);
2553 
2554 static void __exit cpsw_exit(void)
2555 {
2556         platform_driver_unregister(&cpsw_driver);
2557 }
2558 module_exit(cpsw_exit);
2559 
2560 MODULE_LICENSE("GPL");
2561 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2562 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2563 MODULE_DESCRIPTION("TI CPSW Ethernet driver");
2564 

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