Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/drivers/net/ethernet/ti/cpsw.c

  1 /*
  2  * Texas Instruments Ethernet Switch Driver
  3  *
  4  * Copyright (C) 2012 Texas Instruments
  5  *
  6  * This program is free software; you can redistribute it and/or
  7  * modify it under the terms of the GNU General Public License as
  8  * published by the Free Software Foundation version 2.
  9  *
 10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 11  * kind, whether express or implied; without even the implied warranty
 12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  */
 15 
 16 #include <linux/kernel.h>
 17 #include <linux/io.h>
 18 #include <linux/clk.h>
 19 #include <linux/timer.h>
 20 #include <linux/module.h>
 21 #include <linux/platform_device.h>
 22 #include <linux/irqreturn.h>
 23 #include <linux/interrupt.h>
 24 #include <linux/if_ether.h>
 25 #include <linux/etherdevice.h>
 26 #include <linux/netdevice.h>
 27 #include <linux/net_tstamp.h>
 28 #include <linux/phy.h>
 29 #include <linux/workqueue.h>
 30 #include <linux/delay.h>
 31 #include <linux/pm_runtime.h>
 32 #include <linux/of.h>
 33 #include <linux/of_net.h>
 34 #include <linux/of_device.h>
 35 #include <linux/if_vlan.h>
 36 #include <linux/mfd/syscon.h>
 37 #include <linux/regmap.h>
 38 
 39 #include <linux/pinctrl/consumer.h>
 40 
 41 #include "cpsw.h"
 42 #include "cpsw_ale.h"
 43 #include "cpts.h"
 44 #include "davinci_cpdma.h"
 45 
 46 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
 47                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
 48                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
 49                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
 50                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
 51                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
 52                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
 53                          NETIF_MSG_RX_STATUS)
 54 
 55 #define cpsw_info(priv, type, format, ...)              \
 56 do {                                                            \
 57         if (netif_msg_##type(priv) && net_ratelimit())          \
 58                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
 59 } while (0)
 60 
 61 #define cpsw_err(priv, type, format, ...)               \
 62 do {                                                            \
 63         if (netif_msg_##type(priv) && net_ratelimit())          \
 64                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
 65 } while (0)
 66 
 67 #define cpsw_dbg(priv, type, format, ...)               \
 68 do {                                                            \
 69         if (netif_msg_##type(priv) && net_ratelimit())          \
 70                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
 71 } while (0)
 72 
 73 #define cpsw_notice(priv, type, format, ...)            \
 74 do {                                                            \
 75         if (netif_msg_##type(priv) && net_ratelimit())          \
 76                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
 77 } while (0)
 78 
 79 #define ALE_ALL_PORTS           0x7
 80 
 81 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
 82 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
 83 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
 84 
 85 #define CPSW_VERSION_1          0x19010a
 86 #define CPSW_VERSION_2          0x19010c
 87 #define CPSW_VERSION_3          0x19010f
 88 #define CPSW_VERSION_4          0x190112
 89 
 90 #define HOST_PORT_NUM           0
 91 #define SLIVER_SIZE             0x40
 92 
 93 #define CPSW1_HOST_PORT_OFFSET  0x028
 94 #define CPSW1_SLAVE_OFFSET      0x050
 95 #define CPSW1_SLAVE_SIZE        0x040
 96 #define CPSW1_CPDMA_OFFSET      0x100
 97 #define CPSW1_STATERAM_OFFSET   0x200
 98 #define CPSW1_HW_STATS          0x400
 99 #define CPSW1_CPTS_OFFSET       0x500
100 #define CPSW1_ALE_OFFSET        0x600
101 #define CPSW1_SLIVER_OFFSET     0x700
102 
103 #define CPSW2_HOST_PORT_OFFSET  0x108
104 #define CPSW2_SLAVE_OFFSET      0x200
105 #define CPSW2_SLAVE_SIZE        0x100
106 #define CPSW2_CPDMA_OFFSET      0x800
107 #define CPSW2_HW_STATS          0x900
108 #define CPSW2_STATERAM_OFFSET   0xa00
109 #define CPSW2_CPTS_OFFSET       0xc00
110 #define CPSW2_ALE_OFFSET        0xd00
111 #define CPSW2_SLIVER_OFFSET     0xd80
112 #define CPSW2_BD_OFFSET         0x2000
113 
114 #define CPDMA_RXTHRESH          0x0c0
115 #define CPDMA_RXFREE            0x0e0
116 #define CPDMA_TXHDP             0x00
117 #define CPDMA_RXHDP             0x20
118 #define CPDMA_TXCP              0x40
119 #define CPDMA_RXCP              0x60
120 
121 #define CPSW_POLL_WEIGHT        64
122 #define CPSW_MIN_PACKET_SIZE    60
123 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
124 
125 #define RX_PRIORITY_MAPPING     0x76543210
126 #define TX_PRIORITY_MAPPING     0x33221100
127 #define CPDMA_TX_PRIORITY_MAP   0x76543210
128 
129 #define CPSW_VLAN_AWARE         BIT(1)
130 #define CPSW_ALE_VLAN_AWARE     1
131 
132 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
133 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
134 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
135 
136 #define CPSW_INTPACEEN          (0x3f << 16)
137 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
138 #define CPSW_CMINTMAX_CNT       63
139 #define CPSW_CMINTMIN_CNT       2
140 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
141 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
142 
143 #define cpsw_enable_irq(priv)   \
144         do {                    \
145                 u32 i;          \
146                 for (i = 0; i < priv->num_irqs; i++) \
147                         enable_irq(priv->irqs_table[i]); \
148         } while (0)
149 #define cpsw_disable_irq(priv)  \
150         do {                    \
151                 u32 i;          \
152                 for (i = 0; i < priv->num_irqs; i++) \
153                         disable_irq_nosync(priv->irqs_table[i]); \
154         } while (0)
155 
156 #define cpsw_slave_index(priv)                          \
157                 ((priv->data.dual_emac) ? priv->emac_port :     \
158                 priv->data.active_slave)
159 
160 static int debug_level;
161 module_param(debug_level, int, 0);
162 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
163 
164 static int ale_ageout = 10;
165 module_param(ale_ageout, int, 0);
166 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
167 
168 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
169 module_param(rx_packet_max, int, 0);
170 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
171 
172 struct cpsw_wr_regs {
173         u32     id_ver;
174         u32     soft_reset;
175         u32     control;
176         u32     int_control;
177         u32     rx_thresh_en;
178         u32     rx_en;
179         u32     tx_en;
180         u32     misc_en;
181         u32     mem_allign1[8];
182         u32     rx_thresh_stat;
183         u32     rx_stat;
184         u32     tx_stat;
185         u32     misc_stat;
186         u32     mem_allign2[8];
187         u32     rx_imax;
188         u32     tx_imax;
189 
190 };
191 
192 struct cpsw_ss_regs {
193         u32     id_ver;
194         u32     control;
195         u32     soft_reset;
196         u32     stat_port_en;
197         u32     ptype;
198         u32     soft_idle;
199         u32     thru_rate;
200         u32     gap_thresh;
201         u32     tx_start_wds;
202         u32     flow_control;
203         u32     vlan_ltype;
204         u32     ts_ltype;
205         u32     dlr_ltype;
206 };
207 
208 /* CPSW_PORT_V1 */
209 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
210 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
211 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
212 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
213 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
214 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
215 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
216 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
217 
218 /* CPSW_PORT_V2 */
219 #define CPSW2_CONTROL       0x00 /* Control Register */
220 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
221 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
222 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
223 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
224 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
225 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
226 
227 /* CPSW_PORT_V1 and V2 */
228 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
229 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
230 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
231 
232 /* CPSW_PORT_V2 only */
233 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
234 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
235 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
236 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
237 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
238 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
239 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
240 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
241 
242 /* Bit definitions for the CPSW2_CONTROL register */
243 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
244 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
245 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
246 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
247 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
248 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
249 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
250 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
251 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
252 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
253 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
254 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
255 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
256 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
257 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
258 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
259 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
260 
261 #define CTRL_V2_TS_BITS \
262         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
263          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
264 
265 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
266 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
267 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
268 
269 
270 #define CTRL_V3_TS_BITS \
271         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
272          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
273          TS_LTYPE1_EN)
274 
275 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
276 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
277 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
278 
279 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
280 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
281 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
282 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
283 #define TS_MSG_TYPE_EN_MASK      (0xffff)
284 
285 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
286 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
287 
288 /* Bit definitions for the CPSW1_TS_CTL register */
289 #define CPSW_V1_TS_RX_EN                BIT(0)
290 #define CPSW_V1_TS_TX_EN                BIT(4)
291 #define CPSW_V1_MSG_TYPE_OFS            16
292 
293 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
294 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
295 
296 struct cpsw_host_regs {
297         u32     max_blks;
298         u32     blk_cnt;
299         u32     tx_in_ctl;
300         u32     port_vlan;
301         u32     tx_pri_map;
302         u32     cpdma_tx_pri_map;
303         u32     cpdma_rx_chan_map;
304 };
305 
306 struct cpsw_sliver_regs {
307         u32     id_ver;
308         u32     mac_control;
309         u32     mac_status;
310         u32     soft_reset;
311         u32     rx_maxlen;
312         u32     __reserved_0;
313         u32     rx_pause;
314         u32     tx_pause;
315         u32     __reserved_1;
316         u32     rx_pri_map;
317 };
318 
319 struct cpsw_hw_stats {
320         u32     rxgoodframes;
321         u32     rxbroadcastframes;
322         u32     rxmulticastframes;
323         u32     rxpauseframes;
324         u32     rxcrcerrors;
325         u32     rxaligncodeerrors;
326         u32     rxoversizedframes;
327         u32     rxjabberframes;
328         u32     rxundersizedframes;
329         u32     rxfragments;
330         u32     __pad_0[2];
331         u32     rxoctets;
332         u32     txgoodframes;
333         u32     txbroadcastframes;
334         u32     txmulticastframes;
335         u32     txpauseframes;
336         u32     txdeferredframes;
337         u32     txcollisionframes;
338         u32     txsinglecollframes;
339         u32     txmultcollframes;
340         u32     txexcessivecollisions;
341         u32     txlatecollisions;
342         u32     txunderrun;
343         u32     txcarriersenseerrors;
344         u32     txoctets;
345         u32     octetframes64;
346         u32     octetframes65t127;
347         u32     octetframes128t255;
348         u32     octetframes256t511;
349         u32     octetframes512t1023;
350         u32     octetframes1024tup;
351         u32     netoctets;
352         u32     rxsofoverruns;
353         u32     rxmofoverruns;
354         u32     rxdmaoverruns;
355 };
356 
357 struct cpsw_slave {
358         void __iomem                    *regs;
359         struct cpsw_sliver_regs __iomem *sliver;
360         int                             slave_num;
361         u32                             mac_control;
362         struct cpsw_slave_data          *data;
363         struct phy_device               *phy;
364         struct net_device               *ndev;
365         u32                             port_vlan;
366         u32                             open_stat;
367 };
368 
369 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
370 {
371         return __raw_readl(slave->regs + offset);
372 }
373 
374 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
375 {
376         __raw_writel(val, slave->regs + offset);
377 }
378 
379 struct cpsw_priv {
380         spinlock_t                      lock;
381         struct platform_device          *pdev;
382         struct net_device               *ndev;
383         struct napi_struct              napi;
384         struct device                   *dev;
385         struct cpsw_platform_data       data;
386         struct cpsw_ss_regs __iomem     *regs;
387         struct cpsw_wr_regs __iomem     *wr_regs;
388         u8 __iomem                      *hw_stats;
389         struct cpsw_host_regs __iomem   *host_port_regs;
390         u32                             msg_enable;
391         u32                             version;
392         u32                             coal_intvl;
393         u32                             bus_freq_mhz;
394         int                             rx_packet_max;
395         int                             host_port;
396         struct clk                      *clk;
397         u8                              mac_addr[ETH_ALEN];
398         struct cpsw_slave               *slaves;
399         struct cpdma_ctlr               *dma;
400         struct cpdma_chan               *txch, *rxch;
401         struct cpsw_ale                 *ale;
402         bool                            rx_pause;
403         bool                            tx_pause;
404         /* snapshot of IRQ numbers */
405         u32 irqs_table[4];
406         u32 num_irqs;
407         bool irq_enabled;
408         struct cpts *cpts;
409         u32 emac_port;
410 };
411 
412 struct cpsw_stats {
413         char stat_string[ETH_GSTRING_LEN];
414         int type;
415         int sizeof_stat;
416         int stat_offset;
417 };
418 
419 enum {
420         CPSW_STATS,
421         CPDMA_RX_STATS,
422         CPDMA_TX_STATS,
423 };
424 
425 #define CPSW_STAT(m)            CPSW_STATS,                             \
426                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
427                                 offsetof(struct cpsw_hw_stats, m)
428 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
429                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
430                                 offsetof(struct cpdma_chan_stats, m)
431 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
432                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
433                                 offsetof(struct cpdma_chan_stats, m)
434 
435 static const struct cpsw_stats cpsw_gstrings_stats[] = {
436         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
437         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
438         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
439         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
440         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
441         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
442         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
443         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
444         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
445         { "Rx Fragments", CPSW_STAT(rxfragments) },
446         { "Rx Octets", CPSW_STAT(rxoctets) },
447         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
448         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
449         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
450         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
451         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
452         { "Collisions", CPSW_STAT(txcollisionframes) },
453         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
454         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
455         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
456         { "Late Collisions", CPSW_STAT(txlatecollisions) },
457         { "Tx Underrun", CPSW_STAT(txunderrun) },
458         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
459         { "Tx Octets", CPSW_STAT(txoctets) },
460         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
461         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
462         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
463         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
464         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
465         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
466         { "Net Octets", CPSW_STAT(netoctets) },
467         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
468         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
469         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
470         { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
471         { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
472         { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
473         { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
474         { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
475         { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
476         { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
477         { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
478         { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
479         { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
480         { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
481         { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
482         { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
483         { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
484         { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
485         { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
486         { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
487         { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
488         { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
489         { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
490         { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
491         { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
492         { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
493         { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
494         { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
495         { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
496 };
497 
498 #define CPSW_STATS_LEN  ARRAY_SIZE(cpsw_gstrings_stats)
499 
500 #define napi_to_priv(napi)      container_of(napi, struct cpsw_priv, napi)
501 #define for_each_slave(priv, func, arg...)                              \
502         do {                                                            \
503                 struct cpsw_slave *slave;                               \
504                 int n;                                                  \
505                 if (priv->data.dual_emac)                               \
506                         (func)((priv)->slaves + priv->emac_port, ##arg);\
507                 else                                                    \
508                         for (n = (priv)->data.slaves,                   \
509                                         slave = (priv)->slaves;         \
510                                         n; n--)                         \
511                                 (func)(slave++, ##arg);                 \
512         } while (0)
513 #define cpsw_get_slave_ndev(priv, __slave_no__)                         \
514         (priv->slaves[__slave_no__].ndev)
515 #define cpsw_get_slave_priv(priv, __slave_no__)                         \
516         ((priv->slaves[__slave_no__].ndev) ?                            \
517                 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL)    \
518 
519 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb)         \
520         do {                                                            \
521                 if (!priv->data.dual_emac)                              \
522                         break;                                          \
523                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
524                         ndev = cpsw_get_slave_ndev(priv, 0);            \
525                         priv = netdev_priv(ndev);                       \
526                         skb->dev = ndev;                                \
527                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
528                         ndev = cpsw_get_slave_ndev(priv, 1);            \
529                         priv = netdev_priv(ndev);                       \
530                         skb->dev = ndev;                                \
531                 }                                                       \
532         } while (0)
533 #define cpsw_add_mcast(priv, addr)                                      \
534         do {                                                            \
535                 if (priv->data.dual_emac) {                             \
536                         struct cpsw_slave *slave = priv->slaves +       \
537                                                 priv->emac_port;        \
538                         int slave_port = cpsw_get_slave_port(priv,      \
539                                                 slave->slave_num);      \
540                         cpsw_ale_add_mcast(priv->ale, addr,             \
541                                 1 << slave_port | 1 << priv->host_port, \
542                                 ALE_VLAN, slave->port_vlan, 0);         \
543                 } else {                                                \
544                         cpsw_ale_add_mcast(priv->ale, addr,             \
545                                 ALE_ALL_PORTS << priv->host_port,       \
546                                 0, 0, 0);                               \
547                 }                                                       \
548         } while (0)
549 
550 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
551 {
552         if (priv->host_port == 0)
553                 return slave_num + 1;
554         else
555                 return slave_num;
556 }
557 
558 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
559 {
560         struct cpsw_priv *priv = netdev_priv(ndev);
561         struct cpsw_ale *ale = priv->ale;
562         int i;
563 
564         if (priv->data.dual_emac) {
565                 bool flag = false;
566 
567                 /* Enabling promiscuous mode for one interface will be
568                  * common for both the interface as the interface shares
569                  * the same hardware resource.
570                  */
571                 for (i = 0; i < priv->data.slaves; i++)
572                         if (priv->slaves[i].ndev->flags & IFF_PROMISC)
573                                 flag = true;
574 
575                 if (!enable && flag) {
576                         enable = true;
577                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
578                 }
579 
580                 if (enable) {
581                         /* Enable Bypass */
582                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
583 
584                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
585                 } else {
586                         /* Disable Bypass */
587                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
588                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
589                 }
590         } else {
591                 if (enable) {
592                         unsigned long timeout = jiffies + HZ;
593 
594                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
595                         for (i = 0; i <= priv->data.slaves; i++) {
596                                 cpsw_ale_control_set(ale, i,
597                                                      ALE_PORT_NOLEARN, 1);
598                                 cpsw_ale_control_set(ale, i,
599                                                      ALE_PORT_NO_SA_UPDATE, 1);
600                         }
601 
602                         /* Clear All Untouched entries */
603                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
604                         do {
605                                 cpu_relax();
606                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
607                                         break;
608                         } while (time_after(timeout, jiffies));
609                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
610 
611                         /* Clear all mcast from ALE */
612                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<
613                                                  priv->host_port);
614 
615                         /* Flood All Unicast Packets to Host port */
616                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
617                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
618                 } else {
619                         /* Don't Flood All Unicast Packets to Host port */
620                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
621 
622                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
623                         for (i = 0; i <= priv->data.slaves; i++) {
624                                 cpsw_ale_control_set(ale, i,
625                                                      ALE_PORT_NOLEARN, 0);
626                                 cpsw_ale_control_set(ale, i,
627                                                      ALE_PORT_NO_SA_UPDATE, 0);
628                         }
629                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
630                 }
631         }
632 }
633 
634 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
635 {
636         struct cpsw_priv *priv = netdev_priv(ndev);
637 
638         if (ndev->flags & IFF_PROMISC) {
639                 /* Enable promiscuous mode */
640                 cpsw_set_promiscious(ndev, true);
641                 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
642                 return;
643         } else {
644                 /* Disable promiscuous mode */
645                 cpsw_set_promiscious(ndev, false);
646         }
647 
648         /* Restore allmulti on vlans if necessary */
649         cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
650 
651         /* Clear all mcast from ALE */
652         cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port);
653 
654         if (!netdev_mc_empty(ndev)) {
655                 struct netdev_hw_addr *ha;
656 
657                 /* program multicast address list into ALE register */
658                 netdev_for_each_mc_addr(ha, ndev) {
659                         cpsw_add_mcast(priv, (u8 *)ha->addr);
660                 }
661         }
662 }
663 
664 static void cpsw_intr_enable(struct cpsw_priv *priv)
665 {
666         __raw_writel(0xFF, &priv->wr_regs->tx_en);
667         __raw_writel(0xFF, &priv->wr_regs->rx_en);
668 
669         cpdma_ctlr_int_ctrl(priv->dma, true);
670         return;
671 }
672 
673 static void cpsw_intr_disable(struct cpsw_priv *priv)
674 {
675         __raw_writel(0, &priv->wr_regs->tx_en);
676         __raw_writel(0, &priv->wr_regs->rx_en);
677 
678         cpdma_ctlr_int_ctrl(priv->dma, false);
679         return;
680 }
681 
682 static void cpsw_tx_handler(void *token, int len, int status)
683 {
684         struct sk_buff          *skb = token;
685         struct net_device       *ndev = skb->dev;
686         struct cpsw_priv        *priv = netdev_priv(ndev);
687 
688         /* Check whether the queue is stopped due to stalled tx dma, if the
689          * queue is stopped then start the queue as we have free desc for tx
690          */
691         if (unlikely(netif_queue_stopped(ndev)))
692                 netif_wake_queue(ndev);
693         cpts_tx_timestamp(priv->cpts, skb);
694         ndev->stats.tx_packets++;
695         ndev->stats.tx_bytes += len;
696         dev_kfree_skb_any(skb);
697 }
698 
699 static void cpsw_rx_handler(void *token, int len, int status)
700 {
701         struct sk_buff          *skb = token;
702         struct sk_buff          *new_skb;
703         struct net_device       *ndev = skb->dev;
704         struct cpsw_priv        *priv = netdev_priv(ndev);
705         int                     ret = 0;
706 
707         cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
708 
709         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
710                 bool ndev_status = false;
711                 struct cpsw_slave *slave = priv->slaves;
712                 int n;
713 
714                 if (priv->data.dual_emac) {
715                         /* In dual emac mode check for all interfaces */
716                         for (n = priv->data.slaves; n; n--, slave++)
717                                 if (netif_running(slave->ndev))
718                                         ndev_status = true;
719                 }
720 
721                 if (ndev_status && (status >= 0)) {
722                         /* The packet received is for the interface which
723                          * is already down and the other interface is up
724                          * and running, intead of freeing which results
725                          * in reducing of the number of rx descriptor in
726                          * DMA engine, requeue skb back to cpdma.
727                          */
728                         new_skb = skb;
729                         goto requeue;
730                 }
731 
732                 /* the interface is going down, skbs are purged */
733                 dev_kfree_skb_any(skb);
734                 return;
735         }
736 
737         new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
738         if (new_skb) {
739                 skb_put(skb, len);
740                 cpts_rx_timestamp(priv->cpts, skb);
741                 skb->protocol = eth_type_trans(skb, ndev);
742                 netif_receive_skb(skb);
743                 ndev->stats.rx_bytes += len;
744                 ndev->stats.rx_packets++;
745         } else {
746                 ndev->stats.rx_dropped++;
747                 new_skb = skb;
748         }
749 
750 requeue:
751         ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
752                         skb_tailroom(new_skb), 0);
753         if (WARN_ON(ret < 0))
754                 dev_kfree_skb_any(new_skb);
755 }
756 
757 static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
758 {
759         struct cpsw_priv *priv = dev_id;
760 
761         cpsw_intr_disable(priv);
762         if (priv->irq_enabled == true) {
763                 cpsw_disable_irq(priv);
764                 priv->irq_enabled = false;
765         }
766 
767         if (netif_running(priv->ndev)) {
768                 napi_schedule(&priv->napi);
769                 return IRQ_HANDLED;
770         }
771 
772         priv = cpsw_get_slave_priv(priv, 1);
773         if (!priv)
774                 return IRQ_NONE;
775 
776         if (netif_running(priv->ndev)) {
777                 napi_schedule(&priv->napi);
778                 return IRQ_HANDLED;
779         }
780         return IRQ_NONE;
781 }
782 
783 static int cpsw_poll(struct napi_struct *napi, int budget)
784 {
785         struct cpsw_priv        *priv = napi_to_priv(napi);
786         int                     num_tx, num_rx;
787 
788         num_tx = cpdma_chan_process(priv->txch, 128);
789         if (num_tx)
790                 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
791 
792         num_rx = cpdma_chan_process(priv->rxch, budget);
793         if (num_rx < budget) {
794                 struct cpsw_priv *prim_cpsw;
795 
796                 napi_complete(napi);
797                 cpsw_intr_enable(priv);
798                 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
799                 prim_cpsw = cpsw_get_slave_priv(priv, 0);
800                 if (prim_cpsw->irq_enabled == false) {
801                         prim_cpsw->irq_enabled = true;
802                         cpsw_enable_irq(priv);
803                 }
804         }
805 
806         if (num_rx || num_tx)
807                 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
808                          num_rx, num_tx);
809 
810         return num_rx;
811 }
812 
813 static inline void soft_reset(const char *module, void __iomem *reg)
814 {
815         unsigned long timeout = jiffies + HZ;
816 
817         __raw_writel(1, reg);
818         do {
819                 cpu_relax();
820         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
821 
822         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
823 }
824 
825 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
826                          ((mac)[2] << 16) | ((mac)[3] << 24))
827 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
828 
829 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
830                                struct cpsw_priv *priv)
831 {
832         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
833         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
834 }
835 
836 static void _cpsw_adjust_link(struct cpsw_slave *slave,
837                               struct cpsw_priv *priv, bool *link)
838 {
839         struct phy_device       *phy = slave->phy;
840         u32                     mac_control = 0;
841         u32                     slave_port;
842 
843         if (!phy)
844                 return;
845 
846         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
847 
848         if (phy->link) {
849                 mac_control = priv->data.mac_control;
850 
851                 /* enable forwarding */
852                 cpsw_ale_control_set(priv->ale, slave_port,
853                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
854 
855                 if (phy->speed == 1000)
856                         mac_control |= BIT(7);  /* GIGABITEN    */
857                 if (phy->duplex)
858                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
859 
860                 /* set speed_in input in case RMII mode is used in 100Mbps */
861                 if (phy->speed == 100)
862                         mac_control |= BIT(15);
863                 else if (phy->speed == 10)
864                         mac_control |= BIT(18); /* In Band mode */
865 
866                 if (priv->rx_pause)
867                         mac_control |= BIT(3);
868 
869                 if (priv->tx_pause)
870                         mac_control |= BIT(4);
871 
872                 *link = true;
873         } else {
874                 mac_control = 0;
875                 /* disable forwarding */
876                 cpsw_ale_control_set(priv->ale, slave_port,
877                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
878         }
879 
880         if (mac_control != slave->mac_control) {
881                 phy_print_status(phy);
882                 __raw_writel(mac_control, &slave->sliver->mac_control);
883         }
884 
885         slave->mac_control = mac_control;
886 }
887 
888 static void cpsw_adjust_link(struct net_device *ndev)
889 {
890         struct cpsw_priv        *priv = netdev_priv(ndev);
891         bool                    link = false;
892 
893         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
894 
895         if (link) {
896                 netif_carrier_on(ndev);
897                 if (netif_running(ndev))
898                         netif_wake_queue(ndev);
899         } else {
900                 netif_carrier_off(ndev);
901                 netif_stop_queue(ndev);
902         }
903 }
904 
905 static int cpsw_get_coalesce(struct net_device *ndev,
906                                 struct ethtool_coalesce *coal)
907 {
908         struct cpsw_priv *priv = netdev_priv(ndev);
909 
910         coal->rx_coalesce_usecs = priv->coal_intvl;
911         return 0;
912 }
913 
914 static int cpsw_set_coalesce(struct net_device *ndev,
915                                 struct ethtool_coalesce *coal)
916 {
917         struct cpsw_priv *priv = netdev_priv(ndev);
918         u32 int_ctrl;
919         u32 num_interrupts = 0;
920         u32 prescale = 0;
921         u32 addnl_dvdr = 1;
922         u32 coal_intvl = 0;
923 
924         coal_intvl = coal->rx_coalesce_usecs;
925 
926         int_ctrl =  readl(&priv->wr_regs->int_control);
927         prescale = priv->bus_freq_mhz * 4;
928 
929         if (!coal->rx_coalesce_usecs) {
930                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
931                 goto update_return;
932         }
933 
934         if (coal_intvl < CPSW_CMINTMIN_INTVL)
935                 coal_intvl = CPSW_CMINTMIN_INTVL;
936 
937         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
938                 /* Interrupt pacer works with 4us Pulse, we can
939                  * throttle further by dilating the 4us pulse.
940                  */
941                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
942 
943                 if (addnl_dvdr > 1) {
944                         prescale *= addnl_dvdr;
945                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
946                                 coal_intvl = (CPSW_CMINTMAX_INTVL
947                                                 * addnl_dvdr);
948                 } else {
949                         addnl_dvdr = 1;
950                         coal_intvl = CPSW_CMINTMAX_INTVL;
951                 }
952         }
953 
954         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
955         writel(num_interrupts, &priv->wr_regs->rx_imax);
956         writel(num_interrupts, &priv->wr_regs->tx_imax);
957 
958         int_ctrl |= CPSW_INTPACEEN;
959         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
960         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
961 
962 update_return:
963         writel(int_ctrl, &priv->wr_regs->int_control);
964 
965         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
966         if (priv->data.dual_emac) {
967                 int i;
968 
969                 for (i = 0; i < priv->data.slaves; i++) {
970                         priv = netdev_priv(priv->slaves[i].ndev);
971                         priv->coal_intvl = coal_intvl;
972                 }
973         } else {
974                 priv->coal_intvl = coal_intvl;
975         }
976 
977         return 0;
978 }
979 
980 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
981 {
982         switch (sset) {
983         case ETH_SS_STATS:
984                 return CPSW_STATS_LEN;
985         default:
986                 return -EOPNOTSUPP;
987         }
988 }
989 
990 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
991 {
992         u8 *p = data;
993         int i;
994 
995         switch (stringset) {
996         case ETH_SS_STATS:
997                 for (i = 0; i < CPSW_STATS_LEN; i++) {
998                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
999                                ETH_GSTRING_LEN);
1000                         p += ETH_GSTRING_LEN;
1001                 }
1002                 break;
1003         }
1004 }
1005 
1006 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1007                                     struct ethtool_stats *stats, u64 *data)
1008 {
1009         struct cpsw_priv *priv = netdev_priv(ndev);
1010         struct cpdma_chan_stats rx_stats;
1011         struct cpdma_chan_stats tx_stats;
1012         u32 val;
1013         u8 *p;
1014         int i;
1015 
1016         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1017         cpdma_chan_get_stats(priv->rxch, &rx_stats);
1018         cpdma_chan_get_stats(priv->txch, &tx_stats);
1019 
1020         for (i = 0; i < CPSW_STATS_LEN; i++) {
1021                 switch (cpsw_gstrings_stats[i].type) {
1022                 case CPSW_STATS:
1023                         val = readl(priv->hw_stats +
1024                                     cpsw_gstrings_stats[i].stat_offset);
1025                         data[i] = val;
1026                         break;
1027 
1028                 case CPDMA_RX_STATS:
1029                         p = (u8 *)&rx_stats +
1030                                 cpsw_gstrings_stats[i].stat_offset;
1031                         data[i] = *(u32 *)p;
1032                         break;
1033 
1034                 case CPDMA_TX_STATS:
1035                         p = (u8 *)&tx_stats +
1036                                 cpsw_gstrings_stats[i].stat_offset;
1037                         data[i] = *(u32 *)p;
1038                         break;
1039                 }
1040         }
1041 }
1042 
1043 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1044 {
1045         u32 i;
1046         u32 usage_count = 0;
1047 
1048         if (!priv->data.dual_emac)
1049                 return 0;
1050 
1051         for (i = 0; i < priv->data.slaves; i++)
1052                 if (priv->slaves[i].open_stat)
1053                         usage_count++;
1054 
1055         return usage_count;
1056 }
1057 
1058 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1059                         struct cpsw_priv *priv, struct sk_buff *skb)
1060 {
1061         if (!priv->data.dual_emac)
1062                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1063                                   skb->len, 0);
1064 
1065         if (ndev == cpsw_get_slave_ndev(priv, 0))
1066                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1067                                   skb->len, 1);
1068         else
1069                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1070                                   skb->len, 2);
1071 }
1072 
1073 static inline void cpsw_add_dual_emac_def_ale_entries(
1074                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1075                 u32 slave_port)
1076 {
1077         u32 port_mask = 1 << slave_port | 1 << priv->host_port;
1078 
1079         if (priv->version == CPSW_VERSION_1)
1080                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1081         else
1082                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1083         cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1084                           port_mask, port_mask, 0);
1085         cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1086                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1087         cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1088                 priv->host_port, ALE_VLAN, slave->port_vlan);
1089 }
1090 
1091 static void soft_reset_slave(struct cpsw_slave *slave)
1092 {
1093         char name[32];
1094 
1095         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1096         soft_reset(name, &slave->sliver->soft_reset);
1097 }
1098 
1099 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1100 {
1101         u32 slave_port;
1102 
1103         soft_reset_slave(slave);
1104 
1105         /* setup priority mapping */
1106         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1107 
1108         switch (priv->version) {
1109         case CPSW_VERSION_1:
1110                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1111                 break;
1112         case CPSW_VERSION_2:
1113         case CPSW_VERSION_3:
1114         case CPSW_VERSION_4:
1115                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1116                 break;
1117         }
1118 
1119         /* setup max packet size, and mac address */
1120         __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1121         cpsw_set_slave_mac(slave, priv);
1122 
1123         slave->mac_control = 0; /* no link yet */
1124 
1125         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1126 
1127         if (priv->data.dual_emac)
1128                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1129         else
1130                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1131                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1132 
1133         slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1134                                  &cpsw_adjust_link, slave->data->phy_if);
1135         if (IS_ERR(slave->phy)) {
1136                 dev_err(priv->dev, "phy %s not found on slave %d\n",
1137                         slave->data->phy_id, slave->slave_num);
1138                 slave->phy = NULL;
1139         } else {
1140                 dev_info(priv->dev, "phy found : id is : 0x%x\n",
1141                          slave->phy->phy_id);
1142                 phy_start(slave->phy);
1143 
1144                 /* Configure GMII_SEL register */
1145                 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
1146                              slave->slave_num);
1147         }
1148 }
1149 
1150 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1151 {
1152         const int vlan = priv->data.default_vlan;
1153         const int port = priv->host_port;
1154         u32 reg;
1155         int i;
1156         int unreg_mcast_mask;
1157 
1158         reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1159                CPSW2_PORT_VLAN;
1160 
1161         writel(vlan, &priv->host_port_regs->port_vlan);
1162 
1163         for (i = 0; i < priv->data.slaves; i++)
1164                 slave_write(priv->slaves + i, vlan, reg);
1165 
1166         if (priv->ndev->flags & IFF_ALLMULTI)
1167                 unreg_mcast_mask = ALE_ALL_PORTS;
1168         else
1169                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1170 
1171         cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1172                           ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1173                           unreg_mcast_mask << port);
1174 }
1175 
1176 static void cpsw_init_host_port(struct cpsw_priv *priv)
1177 {
1178         u32 control_reg;
1179         u32 fifo_mode;
1180 
1181         /* soft reset the controller and initialize ale */
1182         soft_reset("cpsw", &priv->regs->soft_reset);
1183         cpsw_ale_start(priv->ale);
1184 
1185         /* switch to vlan unaware mode */
1186         cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1187                              CPSW_ALE_VLAN_AWARE);
1188         control_reg = readl(&priv->regs->control);
1189         control_reg |= CPSW_VLAN_AWARE;
1190         writel(control_reg, &priv->regs->control);
1191         fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1192                      CPSW_FIFO_NORMAL_MODE;
1193         writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
1194 
1195         /* setup host port priority mapping */
1196         __raw_writel(CPDMA_TX_PRIORITY_MAP,
1197                      &priv->host_port_regs->cpdma_tx_pri_map);
1198         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1199 
1200         cpsw_ale_control_set(priv->ale, priv->host_port,
1201                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1202 
1203         if (!priv->data.dual_emac) {
1204                 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1205                                    0, 0);
1206                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1207                                    1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1208         }
1209 }
1210 
1211 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1212 {
1213         u32 slave_port;
1214 
1215         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1216 
1217         if (!slave->phy)
1218                 return;
1219         phy_stop(slave->phy);
1220         phy_disconnect(slave->phy);
1221         slave->phy = NULL;
1222         cpsw_ale_control_set(priv->ale, slave_port,
1223                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1224 }
1225 
1226 static int cpsw_ndo_open(struct net_device *ndev)
1227 {
1228         struct cpsw_priv *priv = netdev_priv(ndev);
1229         struct cpsw_priv *prim_cpsw;
1230         int i, ret;
1231         u32 reg;
1232 
1233         if (!cpsw_common_res_usage_state(priv))
1234                 cpsw_intr_disable(priv);
1235         netif_carrier_off(ndev);
1236 
1237         pm_runtime_get_sync(&priv->pdev->dev);
1238 
1239         reg = priv->version;
1240 
1241         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1242                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1243                  CPSW_RTL_VERSION(reg));
1244 
1245         /* initialize host and slave ports */
1246         if (!cpsw_common_res_usage_state(priv))
1247                 cpsw_init_host_port(priv);
1248         for_each_slave(priv, cpsw_slave_open, priv);
1249 
1250         /* Add default VLAN */
1251         if (!priv->data.dual_emac)
1252                 cpsw_add_default_vlan(priv);
1253         else
1254                 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1255                                   ALE_ALL_PORTS << priv->host_port,
1256                                   ALE_ALL_PORTS << priv->host_port, 0, 0);
1257 
1258         if (!cpsw_common_res_usage_state(priv)) {
1259                 /* setup tx dma to fixed prio and zero offset */
1260                 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1261                 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1262 
1263                 /* disable priority elevation */
1264                 __raw_writel(0, &priv->regs->ptype);
1265 
1266                 /* enable statistics collection only on all ports */
1267                 __raw_writel(0x7, &priv->regs->stat_port_en);
1268 
1269                 /* Enable internal fifo flow control */
1270                 writel(0x7, &priv->regs->flow_control);
1271 
1272                 if (WARN_ON(!priv->data.rx_descs))
1273                         priv->data.rx_descs = 128;
1274 
1275                 for (i = 0; i < priv->data.rx_descs; i++) {
1276                         struct sk_buff *skb;
1277 
1278                         ret = -ENOMEM;
1279                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1280                                         priv->rx_packet_max, GFP_KERNEL);
1281                         if (!skb)
1282                                 goto err_cleanup;
1283                         ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
1284                                         skb_tailroom(skb), 0);
1285                         if (ret < 0) {
1286                                 kfree_skb(skb);
1287                                 goto err_cleanup;
1288                         }
1289                 }
1290                 /* continue even if we didn't manage to submit all
1291                  * receive descs
1292                  */
1293                 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
1294 
1295                 if (cpts_register(&priv->pdev->dev, priv->cpts,
1296                                   priv->data.cpts_clock_mult,
1297                                   priv->data.cpts_clock_shift))
1298                         dev_err(priv->dev, "error registering cpts device\n");
1299 
1300         }
1301 
1302         /* Enable Interrupt pacing if configured */
1303         if (priv->coal_intvl != 0) {
1304                 struct ethtool_coalesce coal;
1305 
1306                 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1307                 cpsw_set_coalesce(ndev, &coal);
1308         }
1309 
1310         napi_enable(&priv->napi);
1311         cpdma_ctlr_start(priv->dma);
1312         cpsw_intr_enable(priv);
1313         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1314         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1315 
1316         prim_cpsw = cpsw_get_slave_priv(priv, 0);
1317         if (prim_cpsw->irq_enabled == false) {
1318                 if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) {
1319                         prim_cpsw->irq_enabled = true;
1320                         cpsw_enable_irq(prim_cpsw);
1321                 }
1322         }
1323 
1324         if (priv->data.dual_emac)
1325                 priv->slaves[priv->emac_port].open_stat = true;
1326         return 0;
1327 
1328 err_cleanup:
1329         cpdma_ctlr_stop(priv->dma);
1330         for_each_slave(priv, cpsw_slave_stop, priv);
1331         pm_runtime_put_sync(&priv->pdev->dev);
1332         netif_carrier_off(priv->ndev);
1333         return ret;
1334 }
1335 
1336 static int cpsw_ndo_stop(struct net_device *ndev)
1337 {
1338         struct cpsw_priv *priv = netdev_priv(ndev);
1339 
1340         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1341         netif_stop_queue(priv->ndev);
1342         napi_disable(&priv->napi);
1343         netif_carrier_off(priv->ndev);
1344 
1345         if (cpsw_common_res_usage_state(priv) <= 1) {
1346                 cpts_unregister(priv->cpts);
1347                 cpsw_intr_disable(priv);
1348                 cpdma_ctlr_int_ctrl(priv->dma, false);
1349                 cpdma_ctlr_stop(priv->dma);
1350                 cpsw_ale_stop(priv->ale);
1351         }
1352         for_each_slave(priv, cpsw_slave_stop, priv);
1353         pm_runtime_put_sync(&priv->pdev->dev);
1354         if (priv->data.dual_emac)
1355                 priv->slaves[priv->emac_port].open_stat = false;
1356         return 0;
1357 }
1358 
1359 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1360                                        struct net_device *ndev)
1361 {
1362         struct cpsw_priv *priv = netdev_priv(ndev);
1363         int ret;
1364 
1365         ndev->trans_start = jiffies;
1366 
1367         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1368                 cpsw_err(priv, tx_err, "packet pad failed\n");
1369                 ndev->stats.tx_dropped++;
1370                 return NETDEV_TX_OK;
1371         }
1372 
1373         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1374                                 priv->cpts->tx_enable)
1375                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1376 
1377         skb_tx_timestamp(skb);
1378 
1379         ret = cpsw_tx_packet_submit(ndev, priv, skb);
1380         if (unlikely(ret != 0)) {
1381                 cpsw_err(priv, tx_err, "desc submit failed\n");
1382                 goto fail;
1383         }
1384 
1385         /* If there is no more tx desc left free then we need to
1386          * tell the kernel to stop sending us tx frames.
1387          */
1388         if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1389                 netif_stop_queue(ndev);
1390 
1391         return NETDEV_TX_OK;
1392 fail:
1393         ndev->stats.tx_dropped++;
1394         netif_stop_queue(ndev);
1395         return NETDEV_TX_BUSY;
1396 }
1397 
1398 #ifdef CONFIG_TI_CPTS
1399 
1400 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1401 {
1402         struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1403         u32 ts_en, seq_id;
1404 
1405         if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1406                 slave_write(slave, 0, CPSW1_TS_CTL);
1407                 return;
1408         }
1409 
1410         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1411         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1412 
1413         if (priv->cpts->tx_enable)
1414                 ts_en |= CPSW_V1_TS_TX_EN;
1415 
1416         if (priv->cpts->rx_enable)
1417                 ts_en |= CPSW_V1_TS_RX_EN;
1418 
1419         slave_write(slave, ts_en, CPSW1_TS_CTL);
1420         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1421 }
1422 
1423 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1424 {
1425         struct cpsw_slave *slave;
1426         u32 ctrl, mtype;
1427 
1428         if (priv->data.dual_emac)
1429                 slave = &priv->slaves[priv->emac_port];
1430         else
1431                 slave = &priv->slaves[priv->data.active_slave];
1432 
1433         ctrl = slave_read(slave, CPSW2_CONTROL);
1434         switch (priv->version) {
1435         case CPSW_VERSION_2:
1436                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1437 
1438                 if (priv->cpts->tx_enable)
1439                         ctrl |= CTRL_V2_TX_TS_BITS;
1440 
1441                 if (priv->cpts->rx_enable)
1442                         ctrl |= CTRL_V2_RX_TS_BITS;
1443         break;
1444         case CPSW_VERSION_3:
1445         default:
1446                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1447 
1448                 if (priv->cpts->tx_enable)
1449                         ctrl |= CTRL_V3_TX_TS_BITS;
1450 
1451                 if (priv->cpts->rx_enable)
1452                         ctrl |= CTRL_V3_RX_TS_BITS;
1453         break;
1454         }
1455 
1456         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1457 
1458         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1459         slave_write(slave, ctrl, CPSW2_CONTROL);
1460         __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1461 }
1462 
1463 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1464 {
1465         struct cpsw_priv *priv = netdev_priv(dev);
1466         struct cpts *cpts = priv->cpts;
1467         struct hwtstamp_config cfg;
1468 
1469         if (priv->version != CPSW_VERSION_1 &&
1470             priv->version != CPSW_VERSION_2 &&
1471             priv->version != CPSW_VERSION_3)
1472                 return -EOPNOTSUPP;
1473 
1474         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1475                 return -EFAULT;
1476 
1477         /* reserved for future extensions */
1478         if (cfg.flags)
1479                 return -EINVAL;
1480 
1481         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1482                 return -ERANGE;
1483 
1484         switch (cfg.rx_filter) {
1485         case HWTSTAMP_FILTER_NONE:
1486                 cpts->rx_enable = 0;
1487                 break;
1488         case HWTSTAMP_FILTER_ALL:
1489         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1490         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1491         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1492                 return -ERANGE;
1493         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1494         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1495         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1496         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1497         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1498         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1499         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1500         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1501         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1502                 cpts->rx_enable = 1;
1503                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1504                 break;
1505         default:
1506                 return -ERANGE;
1507         }
1508 
1509         cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1510 
1511         switch (priv->version) {
1512         case CPSW_VERSION_1:
1513                 cpsw_hwtstamp_v1(priv);
1514                 break;
1515         case CPSW_VERSION_2:
1516         case CPSW_VERSION_3:
1517                 cpsw_hwtstamp_v2(priv);
1518                 break;
1519         default:
1520                 WARN_ON(1);
1521         }
1522 
1523         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1524 }
1525 
1526 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1527 {
1528         struct cpsw_priv *priv = netdev_priv(dev);
1529         struct cpts *cpts = priv->cpts;
1530         struct hwtstamp_config cfg;
1531 
1532         if (priv->version != CPSW_VERSION_1 &&
1533             priv->version != CPSW_VERSION_2 &&
1534             priv->version != CPSW_VERSION_3)
1535                 return -EOPNOTSUPP;
1536 
1537         cfg.flags = 0;
1538         cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1539         cfg.rx_filter = (cpts->rx_enable ?
1540                          HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1541 
1542         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1543 }
1544 
1545 #endif /*CONFIG_TI_CPTS*/
1546 
1547 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1548 {
1549         struct cpsw_priv *priv = netdev_priv(dev);
1550         int slave_no = cpsw_slave_index(priv);
1551 
1552         if (!netif_running(dev))
1553                 return -EINVAL;
1554 
1555         switch (cmd) {
1556 #ifdef CONFIG_TI_CPTS
1557         case SIOCSHWTSTAMP:
1558                 return cpsw_hwtstamp_set(dev, req);
1559         case SIOCGHWTSTAMP:
1560                 return cpsw_hwtstamp_get(dev, req);
1561 #endif
1562         }
1563 
1564         if (!priv->slaves[slave_no].phy)
1565                 return -EOPNOTSUPP;
1566         return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
1567 }
1568 
1569 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1570 {
1571         struct cpsw_priv *priv = netdev_priv(ndev);
1572 
1573         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1574         ndev->stats.tx_errors++;
1575         cpsw_intr_disable(priv);
1576         cpdma_ctlr_int_ctrl(priv->dma, false);
1577         cpdma_chan_stop(priv->txch);
1578         cpdma_chan_start(priv->txch);
1579         cpdma_ctlr_int_ctrl(priv->dma, true);
1580         cpsw_intr_enable(priv);
1581         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1582         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1583 
1584 }
1585 
1586 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1587 {
1588         struct cpsw_priv *priv = netdev_priv(ndev);
1589         struct sockaddr *addr = (struct sockaddr *)p;
1590         int flags = 0;
1591         u16 vid = 0;
1592 
1593         if (!is_valid_ether_addr(addr->sa_data))
1594                 return -EADDRNOTAVAIL;
1595 
1596         if (priv->data.dual_emac) {
1597                 vid = priv->slaves[priv->emac_port].port_vlan;
1598                 flags = ALE_VLAN;
1599         }
1600 
1601         cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1602                            flags, vid);
1603         cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1604                            flags, vid);
1605 
1606         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1607         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1608         for_each_slave(priv, cpsw_set_slave_mac, priv);
1609 
1610         return 0;
1611 }
1612 
1613 #ifdef CONFIG_NET_POLL_CONTROLLER
1614 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1615 {
1616         struct cpsw_priv *priv = netdev_priv(ndev);
1617 
1618         cpsw_intr_disable(priv);
1619         cpdma_ctlr_int_ctrl(priv->dma, false);
1620         cpsw_interrupt(ndev->irq, priv);
1621         cpdma_ctlr_int_ctrl(priv->dma, true);
1622         cpsw_intr_enable(priv);
1623         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1624         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1625 
1626 }
1627 #endif
1628 
1629 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1630                                 unsigned short vid)
1631 {
1632         int ret;
1633         int unreg_mcast_mask;
1634 
1635         if (priv->ndev->flags & IFF_ALLMULTI)
1636                 unreg_mcast_mask = ALE_ALL_PORTS;
1637         else
1638                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1639 
1640         ret = cpsw_ale_add_vlan(priv->ale, vid,
1641                                 ALE_ALL_PORTS << priv->host_port,
1642                                 0, ALE_ALL_PORTS << priv->host_port,
1643                                 unreg_mcast_mask << priv->host_port);
1644         if (ret != 0)
1645                 return ret;
1646 
1647         ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1648                                  priv->host_port, ALE_VLAN, vid);
1649         if (ret != 0)
1650                 goto clean_vid;
1651 
1652         ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1653                                  ALE_ALL_PORTS << priv->host_port,
1654                                  ALE_VLAN, vid, 0);
1655         if (ret != 0)
1656                 goto clean_vlan_ucast;
1657         return 0;
1658 
1659 clean_vlan_ucast:
1660         cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1661                             priv->host_port, ALE_VLAN, vid);
1662 clean_vid:
1663         cpsw_ale_del_vlan(priv->ale, vid, 0);
1664         return ret;
1665 }
1666 
1667 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1668                                     __be16 proto, u16 vid)
1669 {
1670         struct cpsw_priv *priv = netdev_priv(ndev);
1671 
1672         if (vid == priv->data.default_vlan)
1673                 return 0;
1674 
1675         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1676         return cpsw_add_vlan_ale_entry(priv, vid);
1677 }
1678 
1679 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1680                                      __be16 proto, u16 vid)
1681 {
1682         struct cpsw_priv *priv = netdev_priv(ndev);
1683         int ret;
1684 
1685         if (vid == priv->data.default_vlan)
1686                 return 0;
1687 
1688         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1689         ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1690         if (ret != 0)
1691                 return ret;
1692 
1693         ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1694                                  priv->host_port, ALE_VLAN, vid);
1695         if (ret != 0)
1696                 return ret;
1697 
1698         return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1699                                   0, ALE_VLAN, vid);
1700 }
1701 
1702 static const struct net_device_ops cpsw_netdev_ops = {
1703         .ndo_open               = cpsw_ndo_open,
1704         .ndo_stop               = cpsw_ndo_stop,
1705         .ndo_start_xmit         = cpsw_ndo_start_xmit,
1706         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
1707         .ndo_do_ioctl           = cpsw_ndo_ioctl,
1708         .ndo_validate_addr      = eth_validate_addr,
1709         .ndo_change_mtu         = eth_change_mtu,
1710         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
1711         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
1712 #ifdef CONFIG_NET_POLL_CONTROLLER
1713         .ndo_poll_controller    = cpsw_ndo_poll_controller,
1714 #endif
1715         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
1716         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
1717 };
1718 
1719 static int cpsw_get_regs_len(struct net_device *ndev)
1720 {
1721         struct cpsw_priv *priv = netdev_priv(ndev);
1722 
1723         return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1724 }
1725 
1726 static void cpsw_get_regs(struct net_device *ndev,
1727                           struct ethtool_regs *regs, void *p)
1728 {
1729         struct cpsw_priv *priv = netdev_priv(ndev);
1730         u32 *reg = p;
1731 
1732         /* update CPSW IP version */
1733         regs->version = priv->version;
1734 
1735         cpsw_ale_dump(priv->ale, reg);
1736 }
1737 
1738 static void cpsw_get_drvinfo(struct net_device *ndev,
1739                              struct ethtool_drvinfo *info)
1740 {
1741         struct cpsw_priv *priv = netdev_priv(ndev);
1742 
1743         strlcpy(info->driver, "cpsw", sizeof(info->driver));
1744         strlcpy(info->version, "1.0", sizeof(info->version));
1745         strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1746         info->regdump_len = cpsw_get_regs_len(ndev);
1747 }
1748 
1749 static u32 cpsw_get_msglevel(struct net_device *ndev)
1750 {
1751         struct cpsw_priv *priv = netdev_priv(ndev);
1752         return priv->msg_enable;
1753 }
1754 
1755 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1756 {
1757         struct cpsw_priv *priv = netdev_priv(ndev);
1758         priv->msg_enable = value;
1759 }
1760 
1761 static int cpsw_get_ts_info(struct net_device *ndev,
1762                             struct ethtool_ts_info *info)
1763 {
1764 #ifdef CONFIG_TI_CPTS
1765         struct cpsw_priv *priv = netdev_priv(ndev);
1766 
1767         info->so_timestamping =
1768                 SOF_TIMESTAMPING_TX_HARDWARE |
1769                 SOF_TIMESTAMPING_TX_SOFTWARE |
1770                 SOF_TIMESTAMPING_RX_HARDWARE |
1771                 SOF_TIMESTAMPING_RX_SOFTWARE |
1772                 SOF_TIMESTAMPING_SOFTWARE |
1773                 SOF_TIMESTAMPING_RAW_HARDWARE;
1774         info->phc_index = priv->cpts->phc_index;
1775         info->tx_types =
1776                 (1 << HWTSTAMP_TX_OFF) |
1777                 (1 << HWTSTAMP_TX_ON);
1778         info->rx_filters =
1779                 (1 << HWTSTAMP_FILTER_NONE) |
1780                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1781 #else
1782         info->so_timestamping =
1783                 SOF_TIMESTAMPING_TX_SOFTWARE |
1784                 SOF_TIMESTAMPING_RX_SOFTWARE |
1785                 SOF_TIMESTAMPING_SOFTWARE;
1786         info->phc_index = -1;
1787         info->tx_types = 0;
1788         info->rx_filters = 0;
1789 #endif
1790         return 0;
1791 }
1792 
1793 static int cpsw_get_settings(struct net_device *ndev,
1794                              struct ethtool_cmd *ecmd)
1795 {
1796         struct cpsw_priv *priv = netdev_priv(ndev);
1797         int slave_no = cpsw_slave_index(priv);
1798 
1799         if (priv->slaves[slave_no].phy)
1800                 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1801         else
1802                 return -EOPNOTSUPP;
1803 }
1804 
1805 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1806 {
1807         struct cpsw_priv *priv = netdev_priv(ndev);
1808         int slave_no = cpsw_slave_index(priv);
1809 
1810         if (priv->slaves[slave_no].phy)
1811                 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1812         else
1813                 return -EOPNOTSUPP;
1814 }
1815 
1816 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1817 {
1818         struct cpsw_priv *priv = netdev_priv(ndev);
1819         int slave_no = cpsw_slave_index(priv);
1820 
1821         wol->supported = 0;
1822         wol->wolopts = 0;
1823 
1824         if (priv->slaves[slave_no].phy)
1825                 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1826 }
1827 
1828 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1829 {
1830         struct cpsw_priv *priv = netdev_priv(ndev);
1831         int slave_no = cpsw_slave_index(priv);
1832 
1833         if (priv->slaves[slave_no].phy)
1834                 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1835         else
1836                 return -EOPNOTSUPP;
1837 }
1838 
1839 static void cpsw_get_pauseparam(struct net_device *ndev,
1840                                 struct ethtool_pauseparam *pause)
1841 {
1842         struct cpsw_priv *priv = netdev_priv(ndev);
1843 
1844         pause->autoneg = AUTONEG_DISABLE;
1845         pause->rx_pause = priv->rx_pause ? true : false;
1846         pause->tx_pause = priv->tx_pause ? true : false;
1847 }
1848 
1849 static int cpsw_set_pauseparam(struct net_device *ndev,
1850                                struct ethtool_pauseparam *pause)
1851 {
1852         struct cpsw_priv *priv = netdev_priv(ndev);
1853         bool link;
1854 
1855         priv->rx_pause = pause->rx_pause ? true : false;
1856         priv->tx_pause = pause->tx_pause ? true : false;
1857 
1858         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1859 
1860         return 0;
1861 }
1862 
1863 static const struct ethtool_ops cpsw_ethtool_ops = {
1864         .get_drvinfo    = cpsw_get_drvinfo,
1865         .get_msglevel   = cpsw_get_msglevel,
1866         .set_msglevel   = cpsw_set_msglevel,
1867         .get_link       = ethtool_op_get_link,
1868         .get_ts_info    = cpsw_get_ts_info,
1869         .get_settings   = cpsw_get_settings,
1870         .set_settings   = cpsw_set_settings,
1871         .get_coalesce   = cpsw_get_coalesce,
1872         .set_coalesce   = cpsw_set_coalesce,
1873         .get_sset_count         = cpsw_get_sset_count,
1874         .get_strings            = cpsw_get_strings,
1875         .get_ethtool_stats      = cpsw_get_ethtool_stats,
1876         .get_pauseparam         = cpsw_get_pauseparam,
1877         .set_pauseparam         = cpsw_set_pauseparam,
1878         .get_wol        = cpsw_get_wol,
1879         .set_wol        = cpsw_set_wol,
1880         .get_regs_len   = cpsw_get_regs_len,
1881         .get_regs       = cpsw_get_regs,
1882 };
1883 
1884 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1885                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
1886 {
1887         void __iomem            *regs = priv->regs;
1888         int                     slave_num = slave->slave_num;
1889         struct cpsw_slave_data  *data = priv->data.slave_data + slave_num;
1890 
1891         slave->data     = data;
1892         slave->regs     = regs + slave_reg_ofs;
1893         slave->sliver   = regs + sliver_reg_ofs;
1894         slave->port_vlan = data->dual_emac_res_vlan;
1895 }
1896 
1897 #define AM33XX_CTRL_MAC_LO_REG(id) (0x630 + 0x8 * id)
1898 #define AM33XX_CTRL_MAC_HI_REG(id) (0x630 + 0x8 * id + 0x4)
1899 
1900 static int cpsw_am33xx_cm_get_macid(struct device *dev, int slave,
1901                 u8 *mac_addr)
1902 {
1903         u32 macid_lo;
1904         u32 macid_hi;
1905         struct regmap *syscon;
1906 
1907         syscon = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon");
1908         if (IS_ERR(syscon)) {
1909                 if (PTR_ERR(syscon) == -ENODEV)
1910                         return 0;
1911                 return PTR_ERR(syscon);
1912         }
1913 
1914         regmap_read(syscon, AM33XX_CTRL_MAC_LO_REG(slave), &macid_lo);
1915         regmap_read(syscon, AM33XX_CTRL_MAC_HI_REG(slave), &macid_hi);
1916 
1917         mac_addr[5] = (macid_lo >> 8) & 0xff;
1918         mac_addr[4] = macid_lo & 0xff;
1919         mac_addr[3] = (macid_hi >> 24) & 0xff;
1920         mac_addr[2] = (macid_hi >> 16) & 0xff;
1921         mac_addr[1] = (macid_hi >> 8) & 0xff;
1922         mac_addr[0] = macid_hi & 0xff;
1923 
1924         return 0;
1925 }
1926 
1927 static int cpsw_probe_dt(struct cpsw_platform_data *data,
1928                          struct platform_device *pdev)
1929 {
1930         struct device_node *node = pdev->dev.of_node;
1931         struct device_node *slave_node;
1932         int i = 0, ret;
1933         u32 prop;
1934 
1935         if (!node)
1936                 return -EINVAL;
1937 
1938         if (of_property_read_u32(node, "slaves", &prop)) {
1939                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
1940                 return -EINVAL;
1941         }
1942         data->slaves = prop;
1943 
1944         if (of_property_read_u32(node, "active_slave", &prop)) {
1945                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
1946                 return -EINVAL;
1947         }
1948         data->active_slave = prop;
1949 
1950         if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1951                 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
1952                 return -EINVAL;
1953         }
1954         data->cpts_clock_mult = prop;
1955 
1956         if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1957                 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
1958                 return -EINVAL;
1959         }
1960         data->cpts_clock_shift = prop;
1961 
1962         data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1963                                         * sizeof(struct cpsw_slave_data),
1964                                         GFP_KERNEL);
1965         if (!data->slave_data)
1966                 return -ENOMEM;
1967 
1968         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1969                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
1970                 return -EINVAL;
1971         }
1972         data->channels = prop;
1973 
1974         if (of_property_read_u32(node, "ale_entries", &prop)) {
1975                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
1976                 return -EINVAL;
1977         }
1978         data->ale_entries = prop;
1979 
1980         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1981                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
1982                 return -EINVAL;
1983         }
1984         data->bd_ram_size = prop;
1985 
1986         if (of_property_read_u32(node, "rx_descs", &prop)) {
1987                 dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
1988                 return -EINVAL;
1989         }
1990         data->rx_descs = prop;
1991 
1992         if (of_property_read_u32(node, "mac_control", &prop)) {
1993                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
1994                 return -EINVAL;
1995         }
1996         data->mac_control = prop;
1997 
1998         if (of_property_read_bool(node, "dual_emac"))
1999                 data->dual_emac = 1;
2000 
2001         /*
2002          * Populate all the child nodes here...
2003          */
2004         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2005         /* We do not want to force this, as in some cases may not have child */
2006         if (ret)
2007                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2008 
2009         for_each_child_of_node(node, slave_node) {
2010                 struct cpsw_slave_data *slave_data = data->slave_data + i;
2011                 const void *mac_addr = NULL;
2012                 u32 phyid;
2013                 int lenp;
2014                 const __be32 *parp;
2015                 struct device_node *mdio_node;
2016                 struct platform_device *mdio;
2017 
2018                 /* This is no slave child node, continue */
2019                 if (strcmp(slave_node->name, "slave"))
2020                         continue;
2021 
2022                 parp = of_get_property(slave_node, "phy_id", &lenp);
2023                 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
2024                         dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i);
2025                         goto no_phy_slave;
2026                 }
2027                 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2028                 phyid = be32_to_cpup(parp+1);
2029                 mdio = of_find_device_by_node(mdio_node);
2030                 of_node_put(mdio_node);
2031                 if (!mdio) {
2032                         dev_err(&pdev->dev, "Missing mdio platform device\n");
2033                         return -EINVAL;
2034                 }
2035                 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2036                          PHY_ID_FMT, mdio->name, phyid);
2037 
2038                 slave_data->phy_if = of_get_phy_mode(slave_node);
2039                 if (slave_data->phy_if < 0) {
2040                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2041                                 i);
2042                         return slave_data->phy_if;
2043                 }
2044 
2045 no_phy_slave:
2046                 mac_addr = of_get_mac_address(slave_node);
2047                 if (mac_addr) {
2048                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2049                 } else {
2050                         if (of_machine_is_compatible("ti,am33xx")) {
2051                                 ret = cpsw_am33xx_cm_get_macid(&pdev->dev, i,
2052                                                         slave_data->mac_addr);
2053                                 if (ret)
2054                                         return ret;
2055                         }
2056                 }
2057                 if (data->dual_emac) {
2058                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2059                                                  &prop)) {
2060                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2061                                 slave_data->dual_emac_res_vlan = i+1;
2062                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2063                                         slave_data->dual_emac_res_vlan, i);
2064                         } else {
2065                                 slave_data->dual_emac_res_vlan = prop;
2066                         }
2067                 }
2068 
2069                 i++;
2070                 if (i == data->slaves)
2071                         break;
2072         }
2073 
2074         return 0;
2075 }
2076 
2077 static int cpsw_probe_dual_emac(struct platform_device *pdev,
2078                                 struct cpsw_priv *priv)
2079 {
2080         struct cpsw_platform_data       *data = &priv->data;
2081         struct net_device               *ndev;
2082         struct cpsw_priv                *priv_sl2;
2083         int ret = 0, i;
2084 
2085         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2086         if (!ndev) {
2087                 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
2088                 return -ENOMEM;
2089         }
2090 
2091         priv_sl2 = netdev_priv(ndev);
2092         spin_lock_init(&priv_sl2->lock);
2093         priv_sl2->data = *data;
2094         priv_sl2->pdev = pdev;
2095         priv_sl2->ndev = ndev;
2096         priv_sl2->dev  = &ndev->dev;
2097         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2098         priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2099 
2100         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2101                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2102                         ETH_ALEN);
2103                 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
2104         } else {
2105                 random_ether_addr(priv_sl2->mac_addr);
2106                 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
2107         }
2108         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2109 
2110         priv_sl2->slaves = priv->slaves;
2111         priv_sl2->clk = priv->clk;
2112 
2113         priv_sl2->coal_intvl = 0;
2114         priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2115 
2116         priv_sl2->regs = priv->regs;
2117         priv_sl2->host_port = priv->host_port;
2118         priv_sl2->host_port_regs = priv->host_port_regs;
2119         priv_sl2->wr_regs = priv->wr_regs;
2120         priv_sl2->hw_stats = priv->hw_stats;
2121         priv_sl2->dma = priv->dma;
2122         priv_sl2->txch = priv->txch;
2123         priv_sl2->rxch = priv->rxch;
2124         priv_sl2->ale = priv->ale;
2125         priv_sl2->emac_port = 1;
2126         priv->slaves[1].ndev = ndev;
2127         priv_sl2->cpts = priv->cpts;
2128         priv_sl2->version = priv->version;
2129 
2130         for (i = 0; i < priv->num_irqs; i++) {
2131                 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2132                 priv_sl2->num_irqs = priv->num_irqs;
2133         }
2134         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2135 
2136         ndev->netdev_ops = &cpsw_netdev_ops;
2137         ndev->ethtool_ops = &cpsw_ethtool_ops;
2138         netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2139 
2140         /* register the network device */
2141         SET_NETDEV_DEV(ndev, &pdev->dev);
2142         ret = register_netdev(ndev);
2143         if (ret) {
2144                 dev_err(&pdev->dev, "cpsw: error registering net device\n");
2145                 free_netdev(ndev);
2146                 ret = -ENODEV;
2147         }
2148 
2149         return ret;
2150 }
2151 
2152 static int cpsw_probe(struct platform_device *pdev)
2153 {
2154         struct cpsw_platform_data       *data;
2155         struct net_device               *ndev;
2156         struct cpsw_priv                *priv;
2157         struct cpdma_params             dma_params;
2158         struct cpsw_ale_params          ale_params;
2159         void __iomem                    *ss_regs;
2160         struct resource                 *res, *ss_res;
2161         u32 slave_offset, sliver_offset, slave_size;
2162         int ret = 0, i, k = 0;
2163 
2164         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2165         if (!ndev) {
2166                 dev_err(&pdev->dev, "error allocating net_device\n");
2167                 return -ENOMEM;
2168         }
2169 
2170         platform_set_drvdata(pdev, ndev);
2171         priv = netdev_priv(ndev);
2172         spin_lock_init(&priv->lock);
2173         priv->pdev = pdev;
2174         priv->ndev = ndev;
2175         priv->dev  = &ndev->dev;
2176         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2177         priv->rx_packet_max = max(rx_packet_max, 128);
2178         priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2179         priv->irq_enabled = true;
2180         if (!priv->cpts) {
2181                 dev_err(&pdev->dev, "error allocating cpts\n");
2182                 ret = -ENOMEM;
2183                 goto clean_ndev_ret;
2184         }
2185 
2186         /*
2187          * This may be required here for child devices.
2188          */
2189         pm_runtime_enable(&pdev->dev);
2190 
2191         /* Select default pin state */
2192         pinctrl_pm_select_default_state(&pdev->dev);
2193 
2194         if (cpsw_probe_dt(&priv->data, pdev)) {
2195                 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2196                 ret = -ENODEV;
2197                 goto clean_runtime_disable_ret;
2198         }
2199         data = &priv->data;
2200 
2201         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2202                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2203                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2204         } else {
2205                 eth_random_addr(priv->mac_addr);
2206                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2207         }
2208 
2209         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2210 
2211         priv->slaves = devm_kzalloc(&pdev->dev,
2212                                     sizeof(struct cpsw_slave) * data->slaves,
2213                                     GFP_KERNEL);
2214         if (!priv->slaves) {
2215                 ret = -ENOMEM;
2216                 goto clean_runtime_disable_ret;
2217         }
2218         for (i = 0; i < data->slaves; i++)
2219                 priv->slaves[i].slave_num = i;
2220 
2221         priv->slaves[0].ndev = ndev;
2222         priv->emac_port = 0;
2223 
2224         priv->clk = devm_clk_get(&pdev->dev, "fck");
2225         if (IS_ERR(priv->clk)) {
2226                 dev_err(priv->dev, "fck is not found\n");
2227                 ret = -ENODEV;
2228                 goto clean_runtime_disable_ret;
2229         }
2230         priv->coal_intvl = 0;
2231         priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
2232 
2233         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2234         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2235         if (IS_ERR(ss_regs)) {
2236                 ret = PTR_ERR(ss_regs);
2237                 goto clean_runtime_disable_ret;
2238         }
2239         priv->regs = ss_regs;
2240         priv->host_port = HOST_PORT_NUM;
2241 
2242         /* Need to enable clocks with runtime PM api to access module
2243          * registers
2244          */
2245         pm_runtime_get_sync(&pdev->dev);
2246         priv->version = readl(&priv->regs->id_ver);
2247         pm_runtime_put_sync(&pdev->dev);
2248 
2249         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2250         priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2251         if (IS_ERR(priv->wr_regs)) {
2252                 ret = PTR_ERR(priv->wr_regs);
2253                 goto clean_runtime_disable_ret;
2254         }
2255 
2256         memset(&dma_params, 0, sizeof(dma_params));
2257         memset(&ale_params, 0, sizeof(ale_params));
2258 
2259         switch (priv->version) {
2260         case CPSW_VERSION_1:
2261                 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2262                 priv->cpts->reg      = ss_regs + CPSW1_CPTS_OFFSET;
2263                 priv->hw_stats       = ss_regs + CPSW1_HW_STATS;
2264                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
2265                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
2266                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
2267                 slave_offset         = CPSW1_SLAVE_OFFSET;
2268                 slave_size           = CPSW1_SLAVE_SIZE;
2269                 sliver_offset        = CPSW1_SLIVER_OFFSET;
2270                 dma_params.desc_mem_phys = 0;
2271                 break;
2272         case CPSW_VERSION_2:
2273         case CPSW_VERSION_3:
2274         case CPSW_VERSION_4:
2275                 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2276                 priv->cpts->reg      = ss_regs + CPSW2_CPTS_OFFSET;
2277                 priv->hw_stats       = ss_regs + CPSW2_HW_STATS;
2278                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
2279                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
2280                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
2281                 slave_offset         = CPSW2_SLAVE_OFFSET;
2282                 slave_size           = CPSW2_SLAVE_SIZE;
2283                 sliver_offset        = CPSW2_SLIVER_OFFSET;
2284                 dma_params.desc_mem_phys =
2285                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2286                 break;
2287         default:
2288                 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2289                 ret = -ENODEV;
2290                 goto clean_runtime_disable_ret;
2291         }
2292         for (i = 0; i < priv->data.slaves; i++) {
2293                 struct cpsw_slave *slave = &priv->slaves[i];
2294                 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2295                 slave_offset  += slave_size;
2296                 sliver_offset += SLIVER_SIZE;
2297         }
2298 
2299         dma_params.dev          = &pdev->dev;
2300         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
2301         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
2302         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
2303         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
2304         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
2305 
2306         dma_params.num_chan             = data->channels;
2307         dma_params.has_soft_reset       = true;
2308         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
2309         dma_params.desc_mem_size        = data->bd_ram_size;
2310         dma_params.desc_align           = 16;
2311         dma_params.has_ext_regs         = true;
2312         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
2313 
2314         priv->dma = cpdma_ctlr_create(&dma_params);
2315         if (!priv->dma) {
2316                 dev_err(priv->dev, "error initializing dma\n");
2317                 ret = -ENOMEM;
2318                 goto clean_runtime_disable_ret;
2319         }
2320 
2321         priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2322                                        cpsw_tx_handler);
2323         priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2324                                        cpsw_rx_handler);
2325 
2326         if (WARN_ON(!priv->txch || !priv->rxch)) {
2327                 dev_err(priv->dev, "error initializing dma channels\n");
2328                 ret = -ENOMEM;
2329                 goto clean_dma_ret;
2330         }
2331 
2332         ale_params.dev                  = &ndev->dev;
2333         ale_params.ale_ageout           = ale_ageout;
2334         ale_params.ale_entries          = data->ale_entries;
2335         ale_params.ale_ports            = data->slaves;
2336 
2337         priv->ale = cpsw_ale_create(&ale_params);
2338         if (!priv->ale) {
2339                 dev_err(priv->dev, "error initializing ale engine\n");
2340                 ret = -ENODEV;
2341                 goto clean_dma_ret;
2342         }
2343 
2344         ndev->irq = platform_get_irq(pdev, 0);
2345         if (ndev->irq < 0) {
2346                 dev_err(priv->dev, "error getting irq resource\n");
2347                 ret = -ENOENT;
2348                 goto clean_ale_ret;
2349         }
2350 
2351         while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
2352                 if (k >= ARRAY_SIZE(priv->irqs_table)) {
2353                         ret = -EINVAL;
2354                         goto clean_ale_ret;
2355                 }
2356 
2357                 ret = devm_request_irq(&pdev->dev, res->start, cpsw_interrupt,
2358                                        0, dev_name(&pdev->dev), priv);
2359                 if (ret < 0) {
2360                         dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2361                         goto clean_ale_ret;
2362                 }
2363 
2364                 priv->irqs_table[k] = res->start;
2365                 k++;
2366         }
2367 
2368         priv->num_irqs = k;
2369 
2370         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2371 
2372         ndev->netdev_ops = &cpsw_netdev_ops;
2373         ndev->ethtool_ops = &cpsw_ethtool_ops;
2374         netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2375 
2376         /* register the network device */
2377         SET_NETDEV_DEV(ndev, &pdev->dev);
2378         ret = register_netdev(ndev);
2379         if (ret) {
2380                 dev_err(priv->dev, "error registering net device\n");
2381                 ret = -ENODEV;
2382                 goto clean_ale_ret;
2383         }
2384 
2385         cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2386                     &ss_res->start, ndev->irq);
2387 
2388         if (priv->data.dual_emac) {
2389                 ret = cpsw_probe_dual_emac(pdev, priv);
2390                 if (ret) {
2391                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2392                         goto clean_ale_ret;
2393                 }
2394         }
2395 
2396         return 0;
2397 
2398 clean_ale_ret:
2399         cpsw_ale_destroy(priv->ale);
2400 clean_dma_ret:
2401         cpdma_chan_destroy(priv->txch);
2402         cpdma_chan_destroy(priv->rxch);
2403         cpdma_ctlr_destroy(priv->dma);
2404 clean_runtime_disable_ret:
2405         pm_runtime_disable(&pdev->dev);
2406 clean_ndev_ret:
2407         free_netdev(priv->ndev);
2408         return ret;
2409 }
2410 
2411 static int cpsw_remove_child_device(struct device *dev, void *c)
2412 {
2413         struct platform_device *pdev = to_platform_device(dev);
2414 
2415         of_device_unregister(pdev);
2416 
2417         return 0;
2418 }
2419 
2420 static int cpsw_remove(struct platform_device *pdev)
2421 {
2422         struct net_device *ndev = platform_get_drvdata(pdev);
2423         struct cpsw_priv *priv = netdev_priv(ndev);
2424 
2425         if (priv->data.dual_emac)
2426                 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2427         unregister_netdev(ndev);
2428 
2429         cpsw_ale_destroy(priv->ale);
2430         cpdma_chan_destroy(priv->txch);
2431         cpdma_chan_destroy(priv->rxch);
2432         cpdma_ctlr_destroy(priv->dma);
2433         pm_runtime_disable(&pdev->dev);
2434         device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device);
2435         if (priv->data.dual_emac)
2436                 free_netdev(cpsw_get_slave_ndev(priv, 1));
2437         free_netdev(ndev);
2438         return 0;
2439 }
2440 
2441 static int cpsw_suspend(struct device *dev)
2442 {
2443         struct platform_device  *pdev = to_platform_device(dev);
2444         struct net_device       *ndev = platform_get_drvdata(pdev);
2445         struct cpsw_priv        *priv = netdev_priv(ndev);
2446 
2447         if (priv->data.dual_emac) {
2448                 int i;
2449 
2450                 for (i = 0; i < priv->data.slaves; i++) {
2451                         if (netif_running(priv->slaves[i].ndev))
2452                                 cpsw_ndo_stop(priv->slaves[i].ndev);
2453                         soft_reset_slave(priv->slaves + i);
2454                 }
2455         } else {
2456                 if (netif_running(ndev))
2457                         cpsw_ndo_stop(ndev);
2458                 for_each_slave(priv, soft_reset_slave);
2459         }
2460 
2461         pm_runtime_put_sync(&pdev->dev);
2462 
2463         /* Select sleep pin state */
2464         pinctrl_pm_select_sleep_state(&pdev->dev);
2465 
2466         return 0;
2467 }
2468 
2469 static int cpsw_resume(struct device *dev)
2470 {
2471         struct platform_device  *pdev = to_platform_device(dev);
2472         struct net_device       *ndev = platform_get_drvdata(pdev);
2473         struct cpsw_priv        *priv = netdev_priv(ndev);
2474 
2475         pm_runtime_get_sync(&pdev->dev);
2476 
2477         /* Select default pin state */
2478         pinctrl_pm_select_default_state(&pdev->dev);
2479 
2480         if (priv->data.dual_emac) {
2481                 int i;
2482 
2483                 for (i = 0; i < priv->data.slaves; i++) {
2484                         if (netif_running(priv->slaves[i].ndev))
2485                                 cpsw_ndo_open(priv->slaves[i].ndev);
2486                 }
2487         } else {
2488                 if (netif_running(ndev))
2489                         cpsw_ndo_open(ndev);
2490         }
2491         return 0;
2492 }
2493 
2494 static const struct dev_pm_ops cpsw_pm_ops = {
2495         .suspend        = cpsw_suspend,
2496         .resume         = cpsw_resume,
2497 };
2498 
2499 static const struct of_device_id cpsw_of_mtable[] = {
2500         { .compatible = "ti,cpsw", },
2501         { /* sentinel */ },
2502 };
2503 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2504 
2505 static struct platform_driver cpsw_driver = {
2506         .driver = {
2507                 .name    = "cpsw",
2508                 .pm      = &cpsw_pm_ops,
2509                 .of_match_table = cpsw_of_mtable,
2510         },
2511         .probe = cpsw_probe,
2512         .remove = cpsw_remove,
2513 };
2514 
2515 static int __init cpsw_init(void)
2516 {
2517         return platform_driver_register(&cpsw_driver);
2518 }
2519 late_initcall(cpsw_init);
2520 
2521 static void __exit cpsw_exit(void)
2522 {
2523         platform_driver_unregister(&cpsw_driver);
2524 }
2525 module_exit(cpsw_exit);
2526 
2527 MODULE_LICENSE("GPL");
2528 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2529 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2530 MODULE_DESCRIPTION("TI CPSW Ethernet driver");
2531 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us