Version:  2.0.40 2.2.26 2.4.37 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9

Linux/drivers/net/ethernet/ti/cpsw.c

  1 /*
  2  * Texas Instruments Ethernet Switch Driver
  3  *
  4  * Copyright (C) 2012 Texas Instruments
  5  *
  6  * This program is free software; you can redistribute it and/or
  7  * modify it under the terms of the GNU General Public License as
  8  * published by the Free Software Foundation version 2.
  9  *
 10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 11  * kind, whether express or implied; without even the implied warranty
 12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  */
 15 
 16 #include <linux/kernel.h>
 17 #include <linux/io.h>
 18 #include <linux/clk.h>
 19 #include <linux/timer.h>
 20 #include <linux/module.h>
 21 #include <linux/platform_device.h>
 22 #include <linux/irqreturn.h>
 23 #include <linux/interrupt.h>
 24 #include <linux/if_ether.h>
 25 #include <linux/etherdevice.h>
 26 #include <linux/netdevice.h>
 27 #include <linux/net_tstamp.h>
 28 #include <linux/phy.h>
 29 #include <linux/workqueue.h>
 30 #include <linux/delay.h>
 31 #include <linux/pm_runtime.h>
 32 #include <linux/gpio.h>
 33 #include <linux/of.h>
 34 #include <linux/of_mdio.h>
 35 #include <linux/of_net.h>
 36 #include <linux/of_device.h>
 37 #include <linux/if_vlan.h>
 38 
 39 #include <linux/pinctrl/consumer.h>
 40 
 41 #include "cpsw.h"
 42 #include "cpsw_ale.h"
 43 #include "cpts.h"
 44 #include "davinci_cpdma.h"
 45 
 46 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
 47                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
 48                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
 49                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
 50                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
 51                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
 52                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
 53                          NETIF_MSG_RX_STATUS)
 54 
 55 #define cpsw_info(priv, type, format, ...)              \
 56 do {                                                            \
 57         if (netif_msg_##type(priv) && net_ratelimit())          \
 58                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
 59 } while (0)
 60 
 61 #define cpsw_err(priv, type, format, ...)               \
 62 do {                                                            \
 63         if (netif_msg_##type(priv) && net_ratelimit())          \
 64                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
 65 } while (0)
 66 
 67 #define cpsw_dbg(priv, type, format, ...)               \
 68 do {                                                            \
 69         if (netif_msg_##type(priv) && net_ratelimit())          \
 70                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
 71 } while (0)
 72 
 73 #define cpsw_notice(priv, type, format, ...)            \
 74 do {                                                            \
 75         if (netif_msg_##type(priv) && net_ratelimit())          \
 76                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
 77 } while (0)
 78 
 79 #define ALE_ALL_PORTS           0x7
 80 
 81 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
 82 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
 83 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
 84 
 85 #define CPSW_VERSION_1          0x19010a
 86 #define CPSW_VERSION_2          0x19010c
 87 #define CPSW_VERSION_3          0x19010f
 88 #define CPSW_VERSION_4          0x190112
 89 
 90 #define HOST_PORT_NUM           0
 91 #define SLIVER_SIZE             0x40
 92 
 93 #define CPSW1_HOST_PORT_OFFSET  0x028
 94 #define CPSW1_SLAVE_OFFSET      0x050
 95 #define CPSW1_SLAVE_SIZE        0x040
 96 #define CPSW1_CPDMA_OFFSET      0x100
 97 #define CPSW1_STATERAM_OFFSET   0x200
 98 #define CPSW1_HW_STATS          0x400
 99 #define CPSW1_CPTS_OFFSET       0x500
100 #define CPSW1_ALE_OFFSET        0x600
101 #define CPSW1_SLIVER_OFFSET     0x700
102 
103 #define CPSW2_HOST_PORT_OFFSET  0x108
104 #define CPSW2_SLAVE_OFFSET      0x200
105 #define CPSW2_SLAVE_SIZE        0x100
106 #define CPSW2_CPDMA_OFFSET      0x800
107 #define CPSW2_HW_STATS          0x900
108 #define CPSW2_STATERAM_OFFSET   0xa00
109 #define CPSW2_CPTS_OFFSET       0xc00
110 #define CPSW2_ALE_OFFSET        0xd00
111 #define CPSW2_SLIVER_OFFSET     0xd80
112 #define CPSW2_BD_OFFSET         0x2000
113 
114 #define CPDMA_RXTHRESH          0x0c0
115 #define CPDMA_RXFREE            0x0e0
116 #define CPDMA_TXHDP             0x00
117 #define CPDMA_RXHDP             0x20
118 #define CPDMA_TXCP              0x40
119 #define CPDMA_RXCP              0x60
120 
121 #define CPSW_POLL_WEIGHT        64
122 #define CPSW_MIN_PACKET_SIZE    60
123 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
124 
125 #define RX_PRIORITY_MAPPING     0x76543210
126 #define TX_PRIORITY_MAPPING     0x33221100
127 #define CPDMA_TX_PRIORITY_MAP   0x01234567
128 
129 #define CPSW_VLAN_AWARE         BIT(1)
130 #define CPSW_ALE_VLAN_AWARE     1
131 
132 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
133 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
134 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
135 
136 #define CPSW_INTPACEEN          (0x3f << 16)
137 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
138 #define CPSW_CMINTMAX_CNT       63
139 #define CPSW_CMINTMIN_CNT       2
140 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
141 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
142 
143 #define cpsw_slave_index(cpsw, priv)                            \
144                 ((cpsw->data.dual_emac) ? priv->emac_port :     \
145                 cpsw->data.active_slave)
146 #define IRQ_NUM                 2
147 #define CPSW_MAX_QUEUES         8
148 
149 static int debug_level;
150 module_param(debug_level, int, 0);
151 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
152 
153 static int ale_ageout = 10;
154 module_param(ale_ageout, int, 0);
155 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
156 
157 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
158 module_param(rx_packet_max, int, 0);
159 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
160 
161 struct cpsw_wr_regs {
162         u32     id_ver;
163         u32     soft_reset;
164         u32     control;
165         u32     int_control;
166         u32     rx_thresh_en;
167         u32     rx_en;
168         u32     tx_en;
169         u32     misc_en;
170         u32     mem_allign1[8];
171         u32     rx_thresh_stat;
172         u32     rx_stat;
173         u32     tx_stat;
174         u32     misc_stat;
175         u32     mem_allign2[8];
176         u32     rx_imax;
177         u32     tx_imax;
178 
179 };
180 
181 struct cpsw_ss_regs {
182         u32     id_ver;
183         u32     control;
184         u32     soft_reset;
185         u32     stat_port_en;
186         u32     ptype;
187         u32     soft_idle;
188         u32     thru_rate;
189         u32     gap_thresh;
190         u32     tx_start_wds;
191         u32     flow_control;
192         u32     vlan_ltype;
193         u32     ts_ltype;
194         u32     dlr_ltype;
195 };
196 
197 /* CPSW_PORT_V1 */
198 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
199 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
200 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
201 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
202 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
203 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
204 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
205 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
206 
207 /* CPSW_PORT_V2 */
208 #define CPSW2_CONTROL       0x00 /* Control Register */
209 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
210 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
211 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
212 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
213 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
214 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
215 
216 /* CPSW_PORT_V1 and V2 */
217 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
218 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
219 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
220 
221 /* CPSW_PORT_V2 only */
222 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
223 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
224 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
225 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
226 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
227 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
228 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
229 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
230 
231 /* Bit definitions for the CPSW2_CONTROL register */
232 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
233 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
234 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
235 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
236 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
237 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
238 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
239 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
240 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
241 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
242 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
243 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
244 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
245 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
246 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
247 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
248 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
249 
250 #define CTRL_V2_TS_BITS \
251         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
252          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
253 
254 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
255 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
256 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
257 
258 
259 #define CTRL_V3_TS_BITS \
260         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
261          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
262          TS_LTYPE1_EN)
263 
264 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
265 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
266 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
267 
268 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
269 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
270 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
271 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
272 #define TS_MSG_TYPE_EN_MASK      (0xffff)
273 
274 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
275 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
276 
277 /* Bit definitions for the CPSW1_TS_CTL register */
278 #define CPSW_V1_TS_RX_EN                BIT(0)
279 #define CPSW_V1_TS_TX_EN                BIT(4)
280 #define CPSW_V1_MSG_TYPE_OFS            16
281 
282 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
283 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
284 
285 struct cpsw_host_regs {
286         u32     max_blks;
287         u32     blk_cnt;
288         u32     tx_in_ctl;
289         u32     port_vlan;
290         u32     tx_pri_map;
291         u32     cpdma_tx_pri_map;
292         u32     cpdma_rx_chan_map;
293 };
294 
295 struct cpsw_sliver_regs {
296         u32     id_ver;
297         u32     mac_control;
298         u32     mac_status;
299         u32     soft_reset;
300         u32     rx_maxlen;
301         u32     __reserved_0;
302         u32     rx_pause;
303         u32     tx_pause;
304         u32     __reserved_1;
305         u32     rx_pri_map;
306 };
307 
308 struct cpsw_hw_stats {
309         u32     rxgoodframes;
310         u32     rxbroadcastframes;
311         u32     rxmulticastframes;
312         u32     rxpauseframes;
313         u32     rxcrcerrors;
314         u32     rxaligncodeerrors;
315         u32     rxoversizedframes;
316         u32     rxjabberframes;
317         u32     rxundersizedframes;
318         u32     rxfragments;
319         u32     __pad_0[2];
320         u32     rxoctets;
321         u32     txgoodframes;
322         u32     txbroadcastframes;
323         u32     txmulticastframes;
324         u32     txpauseframes;
325         u32     txdeferredframes;
326         u32     txcollisionframes;
327         u32     txsinglecollframes;
328         u32     txmultcollframes;
329         u32     txexcessivecollisions;
330         u32     txlatecollisions;
331         u32     txunderrun;
332         u32     txcarriersenseerrors;
333         u32     txoctets;
334         u32     octetframes64;
335         u32     octetframes65t127;
336         u32     octetframes128t255;
337         u32     octetframes256t511;
338         u32     octetframes512t1023;
339         u32     octetframes1024tup;
340         u32     netoctets;
341         u32     rxsofoverruns;
342         u32     rxmofoverruns;
343         u32     rxdmaoverruns;
344 };
345 
346 struct cpsw_slave {
347         void __iomem                    *regs;
348         struct cpsw_sliver_regs __iomem *sliver;
349         int                             slave_num;
350         u32                             mac_control;
351         struct cpsw_slave_data          *data;
352         struct phy_device               *phy;
353         struct net_device               *ndev;
354         u32                             port_vlan;
355         u32                             open_stat;
356 };
357 
358 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
359 {
360         return __raw_readl(slave->regs + offset);
361 }
362 
363 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
364 {
365         __raw_writel(val, slave->regs + offset);
366 }
367 
368 struct cpsw_common {
369         struct device                   *dev;
370         struct cpsw_platform_data       data;
371         struct napi_struct              napi_rx;
372         struct napi_struct              napi_tx;
373         struct cpsw_ss_regs __iomem     *regs;
374         struct cpsw_wr_regs __iomem     *wr_regs;
375         u8 __iomem                      *hw_stats;
376         struct cpsw_host_regs __iomem   *host_port_regs;
377         u32                             version;
378         u32                             coal_intvl;
379         u32                             bus_freq_mhz;
380         int                             rx_packet_max;
381         struct cpsw_slave               *slaves;
382         struct cpdma_ctlr               *dma;
383         struct cpdma_chan               *txch[CPSW_MAX_QUEUES];
384         struct cpdma_chan               *rxch[CPSW_MAX_QUEUES];
385         struct cpsw_ale                 *ale;
386         bool                            quirk_irq;
387         bool                            rx_irq_disabled;
388         bool                            tx_irq_disabled;
389         u32 irqs_table[IRQ_NUM];
390         struct cpts                     *cpts;
391         int                             rx_ch_num, tx_ch_num;
392 };
393 
394 struct cpsw_priv {
395         struct net_device               *ndev;
396         struct device                   *dev;
397         u32                             msg_enable;
398         u8                              mac_addr[ETH_ALEN];
399         bool                            rx_pause;
400         bool                            tx_pause;
401         u32 emac_port;
402         struct cpsw_common *cpsw;
403 };
404 
405 struct cpsw_stats {
406         char stat_string[ETH_GSTRING_LEN];
407         int type;
408         int sizeof_stat;
409         int stat_offset;
410 };
411 
412 enum {
413         CPSW_STATS,
414         CPDMA_RX_STATS,
415         CPDMA_TX_STATS,
416 };
417 
418 #define CPSW_STAT(m)            CPSW_STATS,                             \
419                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
420                                 offsetof(struct cpsw_hw_stats, m)
421 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
422                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
423                                 offsetof(struct cpdma_chan_stats, m)
424 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
425                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
426                                 offsetof(struct cpdma_chan_stats, m)
427 
428 static const struct cpsw_stats cpsw_gstrings_stats[] = {
429         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
430         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
431         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
432         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
433         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
434         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
435         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
436         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
437         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
438         { "Rx Fragments", CPSW_STAT(rxfragments) },
439         { "Rx Octets", CPSW_STAT(rxoctets) },
440         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
441         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
442         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
443         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
444         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
445         { "Collisions", CPSW_STAT(txcollisionframes) },
446         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
447         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
448         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
449         { "Late Collisions", CPSW_STAT(txlatecollisions) },
450         { "Tx Underrun", CPSW_STAT(txunderrun) },
451         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
452         { "Tx Octets", CPSW_STAT(txoctets) },
453         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
454         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
455         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
456         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
457         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
458         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
459         { "Net Octets", CPSW_STAT(netoctets) },
460         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
461         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
462         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
463 };
464 
465 static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
466         { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
467         { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
468         { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
469         { "misqueued", CPDMA_RX_STAT(misqueued) },
470         { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
471         { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
472         { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
473         { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
474         { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
475         { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
476         { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
477         { "requeue", CPDMA_RX_STAT(requeue) },
478         { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
479 };
480 
481 #define CPSW_STATS_COMMON_LEN   ARRAY_SIZE(cpsw_gstrings_stats)
482 #define CPSW_STATS_CH_LEN       ARRAY_SIZE(cpsw_gstrings_ch_stats)
483 
484 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
485 #define napi_to_cpsw(napi)      container_of(napi, struct cpsw_common, napi)
486 #define for_each_slave(priv, func, arg...)                              \
487         do {                                                            \
488                 struct cpsw_slave *slave;                               \
489                 struct cpsw_common *cpsw = (priv)->cpsw;                \
490                 int n;                                                  \
491                 if (cpsw->data.dual_emac)                               \
492                         (func)((cpsw)->slaves + priv->emac_port, ##arg);\
493                 else                                                    \
494                         for (n = cpsw->data.slaves,                     \
495                                         slave = cpsw->slaves;           \
496                                         n; n--)                         \
497                                 (func)(slave++, ##arg);                 \
498         } while (0)
499 
500 #define cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb)         \
501         do {                                                            \
502                 if (!cpsw->data.dual_emac)                              \
503                         break;                                          \
504                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
505                         ndev = cpsw->slaves[0].ndev;                    \
506                         skb->dev = ndev;                                \
507                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
508                         ndev = cpsw->slaves[1].ndev;                    \
509                         skb->dev = ndev;                                \
510                 }                                                       \
511         } while (0)
512 #define cpsw_add_mcast(cpsw, priv, addr)                                \
513         do {                                                            \
514                 if (cpsw->data.dual_emac) {                             \
515                         struct cpsw_slave *slave = cpsw->slaves +       \
516                                                 priv->emac_port;        \
517                         int slave_port = cpsw_get_slave_port(           \
518                                                 slave->slave_num);      \
519                         cpsw_ale_add_mcast(cpsw->ale, addr,             \
520                                 1 << slave_port | ALE_PORT_HOST,        \
521                                 ALE_VLAN, slave->port_vlan, 0);         \
522                 } else {                                                \
523                         cpsw_ale_add_mcast(cpsw->ale, addr,             \
524                                 ALE_ALL_PORTS,                          \
525                                 0, 0, 0);                               \
526                 }                                                       \
527         } while (0)
528 
529 static inline int cpsw_get_slave_port(u32 slave_num)
530 {
531         return slave_num + 1;
532 }
533 
534 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
535 {
536         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
537         struct cpsw_ale *ale = cpsw->ale;
538         int i;
539 
540         if (cpsw->data.dual_emac) {
541                 bool flag = false;
542 
543                 /* Enabling promiscuous mode for one interface will be
544                  * common for both the interface as the interface shares
545                  * the same hardware resource.
546                  */
547                 for (i = 0; i < cpsw->data.slaves; i++)
548                         if (cpsw->slaves[i].ndev->flags & IFF_PROMISC)
549                                 flag = true;
550 
551                 if (!enable && flag) {
552                         enable = true;
553                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
554                 }
555 
556                 if (enable) {
557                         /* Enable Bypass */
558                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
559 
560                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
561                 } else {
562                         /* Disable Bypass */
563                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
564                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
565                 }
566         } else {
567                 if (enable) {
568                         unsigned long timeout = jiffies + HZ;
569 
570                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
571                         for (i = 0; i <= cpsw->data.slaves; i++) {
572                                 cpsw_ale_control_set(ale, i,
573                                                      ALE_PORT_NOLEARN, 1);
574                                 cpsw_ale_control_set(ale, i,
575                                                      ALE_PORT_NO_SA_UPDATE, 1);
576                         }
577 
578                         /* Clear All Untouched entries */
579                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
580                         do {
581                                 cpu_relax();
582                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
583                                         break;
584                         } while (time_after(timeout, jiffies));
585                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
586 
587                         /* Clear all mcast from ALE */
588                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
589 
590                         /* Flood All Unicast Packets to Host port */
591                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
592                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
593                 } else {
594                         /* Don't Flood All Unicast Packets to Host port */
595                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
596 
597                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
598                         for (i = 0; i <= cpsw->data.slaves; i++) {
599                                 cpsw_ale_control_set(ale, i,
600                                                      ALE_PORT_NOLEARN, 0);
601                                 cpsw_ale_control_set(ale, i,
602                                                      ALE_PORT_NO_SA_UPDATE, 0);
603                         }
604                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
605                 }
606         }
607 }
608 
609 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
610 {
611         struct cpsw_priv *priv = netdev_priv(ndev);
612         struct cpsw_common *cpsw = priv->cpsw;
613         int vid;
614 
615         if (cpsw->data.dual_emac)
616                 vid = cpsw->slaves[priv->emac_port].port_vlan;
617         else
618                 vid = cpsw->data.default_vlan;
619 
620         if (ndev->flags & IFF_PROMISC) {
621                 /* Enable promiscuous mode */
622                 cpsw_set_promiscious(ndev, true);
623                 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI);
624                 return;
625         } else {
626                 /* Disable promiscuous mode */
627                 cpsw_set_promiscious(ndev, false);
628         }
629 
630         /* Restore allmulti on vlans if necessary */
631         cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI);
632 
633         /* Clear all mcast from ALE */
634         cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid);
635 
636         if (!netdev_mc_empty(ndev)) {
637                 struct netdev_hw_addr *ha;
638 
639                 /* program multicast address list into ALE register */
640                 netdev_for_each_mc_addr(ha, ndev) {
641                         cpsw_add_mcast(cpsw, priv, (u8 *)ha->addr);
642                 }
643         }
644 }
645 
646 static void cpsw_intr_enable(struct cpsw_common *cpsw)
647 {
648         __raw_writel(0xFF, &cpsw->wr_regs->tx_en);
649         __raw_writel(0xFF, &cpsw->wr_regs->rx_en);
650 
651         cpdma_ctlr_int_ctrl(cpsw->dma, true);
652         return;
653 }
654 
655 static void cpsw_intr_disable(struct cpsw_common *cpsw)
656 {
657         __raw_writel(0, &cpsw->wr_regs->tx_en);
658         __raw_writel(0, &cpsw->wr_regs->rx_en);
659 
660         cpdma_ctlr_int_ctrl(cpsw->dma, false);
661         return;
662 }
663 
664 static void cpsw_tx_handler(void *token, int len, int status)
665 {
666         struct netdev_queue     *txq;
667         struct sk_buff          *skb = token;
668         struct net_device       *ndev = skb->dev;
669         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
670 
671         /* Check whether the queue is stopped due to stalled tx dma, if the
672          * queue is stopped then start the queue as we have free desc for tx
673          */
674         txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
675         if (unlikely(netif_tx_queue_stopped(txq)))
676                 netif_tx_wake_queue(txq);
677 
678         cpts_tx_timestamp(cpsw->cpts, skb);
679         ndev->stats.tx_packets++;
680         ndev->stats.tx_bytes += len;
681         dev_kfree_skb_any(skb);
682 }
683 
684 static void cpsw_rx_handler(void *token, int len, int status)
685 {
686         struct cpdma_chan       *ch;
687         struct sk_buff          *skb = token;
688         struct sk_buff          *new_skb;
689         struct net_device       *ndev = skb->dev;
690         int                     ret = 0;
691         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
692 
693         cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb);
694 
695         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
696                 bool ndev_status = false;
697                 struct cpsw_slave *slave = cpsw->slaves;
698                 int n;
699 
700                 if (cpsw->data.dual_emac) {
701                         /* In dual emac mode check for all interfaces */
702                         for (n = cpsw->data.slaves; n; n--, slave++)
703                                 if (netif_running(slave->ndev))
704                                         ndev_status = true;
705                 }
706 
707                 if (ndev_status && (status >= 0)) {
708                         /* The packet received is for the interface which
709                          * is already down and the other interface is up
710                          * and running, instead of freeing which results
711                          * in reducing of the number of rx descriptor in
712                          * DMA engine, requeue skb back to cpdma.
713                          */
714                         new_skb = skb;
715                         goto requeue;
716                 }
717 
718                 /* the interface is going down, skbs are purged */
719                 dev_kfree_skb_any(skb);
720                 return;
721         }
722 
723         new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max);
724         if (new_skb) {
725                 skb_copy_queue_mapping(new_skb, skb);
726                 skb_put(skb, len);
727                 cpts_rx_timestamp(cpsw->cpts, skb);
728                 skb->protocol = eth_type_trans(skb, ndev);
729                 netif_receive_skb(skb);
730                 ndev->stats.rx_bytes += len;
731                 ndev->stats.rx_packets++;
732                 kmemleak_not_leak(new_skb);
733         } else {
734                 ndev->stats.rx_dropped++;
735                 new_skb = skb;
736         }
737 
738 requeue:
739         if (netif_dormant(ndev)) {
740                 dev_kfree_skb_any(new_skb);
741                 return;
742         }
743 
744         ch = cpsw->rxch[skb_get_queue_mapping(new_skb)];
745         ret = cpdma_chan_submit(ch, new_skb, new_skb->data,
746                                 skb_tailroom(new_skb), 0);
747         if (WARN_ON(ret < 0))
748                 dev_kfree_skb_any(new_skb);
749 }
750 
751 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
752 {
753         struct cpsw_common *cpsw = dev_id;
754 
755         writel(0, &cpsw->wr_regs->tx_en);
756         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
757 
758         if (cpsw->quirk_irq) {
759                 disable_irq_nosync(cpsw->irqs_table[1]);
760                 cpsw->tx_irq_disabled = true;
761         }
762 
763         napi_schedule(&cpsw->napi_tx);
764         return IRQ_HANDLED;
765 }
766 
767 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
768 {
769         struct cpsw_common *cpsw = dev_id;
770 
771         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
772         writel(0, &cpsw->wr_regs->rx_en);
773 
774         if (cpsw->quirk_irq) {
775                 disable_irq_nosync(cpsw->irqs_table[0]);
776                 cpsw->rx_irq_disabled = true;
777         }
778 
779         napi_schedule(&cpsw->napi_rx);
780         return IRQ_HANDLED;
781 }
782 
783 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
784 {
785         u32                     ch_map;
786         int                     num_tx, ch;
787         struct cpsw_common      *cpsw = napi_to_cpsw(napi_tx);
788 
789         /* process every unprocessed channel */
790         ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
791         for (ch = 0, num_tx = 0; num_tx < budget; ch_map >>= 1, ch++) {
792                 if (!ch_map) {
793                         ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
794                         if (!ch_map)
795                                 break;
796 
797                         ch = 0;
798                 }
799 
800                 if (!(ch_map & 0x01))
801                         continue;
802 
803                 num_tx += cpdma_chan_process(cpsw->txch[ch], budget - num_tx);
804         }
805 
806         if (num_tx < budget) {
807                 napi_complete(napi_tx);
808                 writel(0xff, &cpsw->wr_regs->tx_en);
809                 if (cpsw->quirk_irq && cpsw->tx_irq_disabled) {
810                         cpsw->tx_irq_disabled = false;
811                         enable_irq(cpsw->irqs_table[1]);
812                 }
813         }
814 
815         return num_tx;
816 }
817 
818 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
819 {
820         u32                     ch_map;
821         int                     num_rx, ch;
822         struct cpsw_common      *cpsw = napi_to_cpsw(napi_rx);
823 
824         /* process every unprocessed channel */
825         ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
826         for (ch = 0, num_rx = 0; num_rx < budget; ch_map >>= 1, ch++) {
827                 if (!ch_map) {
828                         ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
829                         if (!ch_map)
830                                 break;
831 
832                         ch = 0;
833                 }
834 
835                 if (!(ch_map & 0x01))
836                         continue;
837 
838                 num_rx += cpdma_chan_process(cpsw->rxch[ch], budget - num_rx);
839         }
840 
841         if (num_rx < budget) {
842                 napi_complete(napi_rx);
843                 writel(0xff, &cpsw->wr_regs->rx_en);
844                 if (cpsw->quirk_irq && cpsw->rx_irq_disabled) {
845                         cpsw->rx_irq_disabled = false;
846                         enable_irq(cpsw->irqs_table[0]);
847                 }
848         }
849 
850         return num_rx;
851 }
852 
853 static inline void soft_reset(const char *module, void __iomem *reg)
854 {
855         unsigned long timeout = jiffies + HZ;
856 
857         __raw_writel(1, reg);
858         do {
859                 cpu_relax();
860         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
861 
862         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
863 }
864 
865 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
866                          ((mac)[2] << 16) | ((mac)[3] << 24))
867 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
868 
869 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
870                                struct cpsw_priv *priv)
871 {
872         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
873         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
874 }
875 
876 static void _cpsw_adjust_link(struct cpsw_slave *slave,
877                               struct cpsw_priv *priv, bool *link)
878 {
879         struct phy_device       *phy = slave->phy;
880         u32                     mac_control = 0;
881         u32                     slave_port;
882         struct cpsw_common *cpsw = priv->cpsw;
883 
884         if (!phy)
885                 return;
886 
887         slave_port = cpsw_get_slave_port(slave->slave_num);
888 
889         if (phy->link) {
890                 mac_control = cpsw->data.mac_control;
891 
892                 /* enable forwarding */
893                 cpsw_ale_control_set(cpsw->ale, slave_port,
894                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
895 
896                 if (phy->speed == 1000)
897                         mac_control |= BIT(7);  /* GIGABITEN    */
898                 if (phy->duplex)
899                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
900 
901                 /* set speed_in input in case RMII mode is used in 100Mbps */
902                 if (phy->speed == 100)
903                         mac_control |= BIT(15);
904                 else if (phy->speed == 10)
905                         mac_control |= BIT(18); /* In Band mode */
906 
907                 if (priv->rx_pause)
908                         mac_control |= BIT(3);
909 
910                 if (priv->tx_pause)
911                         mac_control |= BIT(4);
912 
913                 *link = true;
914         } else {
915                 mac_control = 0;
916                 /* disable forwarding */
917                 cpsw_ale_control_set(cpsw->ale, slave_port,
918                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
919         }
920 
921         if (mac_control != slave->mac_control) {
922                 phy_print_status(phy);
923                 __raw_writel(mac_control, &slave->sliver->mac_control);
924         }
925 
926         slave->mac_control = mac_control;
927 }
928 
929 static void cpsw_adjust_link(struct net_device *ndev)
930 {
931         struct cpsw_priv        *priv = netdev_priv(ndev);
932         bool                    link = false;
933 
934         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
935 
936         if (link) {
937                 netif_carrier_on(ndev);
938                 if (netif_running(ndev))
939                         netif_tx_wake_all_queues(ndev);
940         } else {
941                 netif_carrier_off(ndev);
942                 netif_tx_stop_all_queues(ndev);
943         }
944 }
945 
946 static int cpsw_get_coalesce(struct net_device *ndev,
947                                 struct ethtool_coalesce *coal)
948 {
949         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
950 
951         coal->rx_coalesce_usecs = cpsw->coal_intvl;
952         return 0;
953 }
954 
955 static int cpsw_set_coalesce(struct net_device *ndev,
956                                 struct ethtool_coalesce *coal)
957 {
958         struct cpsw_priv *priv = netdev_priv(ndev);
959         u32 int_ctrl;
960         u32 num_interrupts = 0;
961         u32 prescale = 0;
962         u32 addnl_dvdr = 1;
963         u32 coal_intvl = 0;
964         struct cpsw_common *cpsw = priv->cpsw;
965 
966         coal_intvl = coal->rx_coalesce_usecs;
967 
968         int_ctrl =  readl(&cpsw->wr_regs->int_control);
969         prescale = cpsw->bus_freq_mhz * 4;
970 
971         if (!coal->rx_coalesce_usecs) {
972                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
973                 goto update_return;
974         }
975 
976         if (coal_intvl < CPSW_CMINTMIN_INTVL)
977                 coal_intvl = CPSW_CMINTMIN_INTVL;
978 
979         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
980                 /* Interrupt pacer works with 4us Pulse, we can
981                  * throttle further by dilating the 4us pulse.
982                  */
983                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
984 
985                 if (addnl_dvdr > 1) {
986                         prescale *= addnl_dvdr;
987                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
988                                 coal_intvl = (CPSW_CMINTMAX_INTVL
989                                                 * addnl_dvdr);
990                 } else {
991                         addnl_dvdr = 1;
992                         coal_intvl = CPSW_CMINTMAX_INTVL;
993                 }
994         }
995 
996         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
997         writel(num_interrupts, &cpsw->wr_regs->rx_imax);
998         writel(num_interrupts, &cpsw->wr_regs->tx_imax);
999 
1000         int_ctrl |= CPSW_INTPACEEN;
1001         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
1002         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
1003 
1004 update_return:
1005         writel(int_ctrl, &cpsw->wr_regs->int_control);
1006 
1007         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
1008         cpsw->coal_intvl = coal_intvl;
1009 
1010         return 0;
1011 }
1012 
1013 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1014 {
1015         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1016 
1017         switch (sset) {
1018         case ETH_SS_STATS:
1019                 return (CPSW_STATS_COMMON_LEN +
1020                        (cpsw->rx_ch_num + cpsw->tx_ch_num) *
1021                        CPSW_STATS_CH_LEN);
1022         default:
1023                 return -EOPNOTSUPP;
1024         }
1025 }
1026 
1027 static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
1028 {
1029         int ch_stats_len;
1030         int line;
1031         int i;
1032 
1033         ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
1034         for (i = 0; i < ch_stats_len; i++) {
1035                 line = i % CPSW_STATS_CH_LEN;
1036                 snprintf(*p, ETH_GSTRING_LEN,
1037                          "%s DMA chan %d: %s", rx_dir ? "Rx" : "Tx",
1038                          i / CPSW_STATS_CH_LEN,
1039                          cpsw_gstrings_ch_stats[line].stat_string);
1040                 *p += ETH_GSTRING_LEN;
1041         }
1042 }
1043 
1044 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1045 {
1046         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1047         u8 *p = data;
1048         int i;
1049 
1050         switch (stringset) {
1051         case ETH_SS_STATS:
1052                 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
1053                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
1054                                ETH_GSTRING_LEN);
1055                         p += ETH_GSTRING_LEN;
1056                 }
1057 
1058                 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
1059                 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
1060                 break;
1061         }
1062 }
1063 
1064 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1065                                     struct ethtool_stats *stats, u64 *data)
1066 {
1067         u8 *p;
1068         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1069         struct cpdma_chan_stats ch_stats;
1070         int i, l, ch;
1071 
1072         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1073         for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
1074                 data[l] = readl(cpsw->hw_stats +
1075                                 cpsw_gstrings_stats[l].stat_offset);
1076 
1077         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1078                 cpdma_chan_get_stats(cpsw->rxch[ch], &ch_stats);
1079                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1080                         p = (u8 *)&ch_stats +
1081                                 cpsw_gstrings_ch_stats[i].stat_offset;
1082                         data[l] = *(u32 *)p;
1083                 }
1084         }
1085 
1086         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1087                 cpdma_chan_get_stats(cpsw->txch[ch], &ch_stats);
1088                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1089                         p = (u8 *)&ch_stats +
1090                                 cpsw_gstrings_ch_stats[i].stat_offset;
1091                         data[l] = *(u32 *)p;
1092                 }
1093         }
1094 }
1095 
1096 static int cpsw_common_res_usage_state(struct cpsw_common *cpsw)
1097 {
1098         u32 i;
1099         u32 usage_count = 0;
1100 
1101         if (!cpsw->data.dual_emac)
1102                 return 0;
1103 
1104         for (i = 0; i < cpsw->data.slaves; i++)
1105                 if (cpsw->slaves[i].open_stat)
1106                         usage_count++;
1107 
1108         return usage_count;
1109 }
1110 
1111 static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
1112                                         struct sk_buff *skb,
1113                                         struct cpdma_chan *txch)
1114 {
1115         struct cpsw_common *cpsw = priv->cpsw;
1116 
1117         return cpdma_chan_submit(txch, skb, skb->data, skb->len,
1118                                  priv->emac_port + cpsw->data.dual_emac);
1119 }
1120 
1121 static inline void cpsw_add_dual_emac_def_ale_entries(
1122                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1123                 u32 slave_port)
1124 {
1125         struct cpsw_common *cpsw = priv->cpsw;
1126         u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1127 
1128         if (cpsw->version == CPSW_VERSION_1)
1129                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1130         else
1131                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1132         cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask,
1133                           port_mask, port_mask, 0);
1134         cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1135                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1136         cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1137                            HOST_PORT_NUM, ALE_VLAN |
1138                            ALE_SECURE, slave->port_vlan);
1139 }
1140 
1141 static void soft_reset_slave(struct cpsw_slave *slave)
1142 {
1143         char name[32];
1144 
1145         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1146         soft_reset(name, &slave->sliver->soft_reset);
1147 }
1148 
1149 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1150 {
1151         u32 slave_port;
1152         struct cpsw_common *cpsw = priv->cpsw;
1153 
1154         soft_reset_slave(slave);
1155 
1156         /* setup priority mapping */
1157         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1158 
1159         switch (cpsw->version) {
1160         case CPSW_VERSION_1:
1161                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1162                 break;
1163         case CPSW_VERSION_2:
1164         case CPSW_VERSION_3:
1165         case CPSW_VERSION_4:
1166                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1167                 break;
1168         }
1169 
1170         /* setup max packet size, and mac address */
1171         __raw_writel(cpsw->rx_packet_max, &slave->sliver->rx_maxlen);
1172         cpsw_set_slave_mac(slave, priv);
1173 
1174         slave->mac_control = 0; /* no link yet */
1175 
1176         slave_port = cpsw_get_slave_port(slave->slave_num);
1177 
1178         if (cpsw->data.dual_emac)
1179                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1180         else
1181                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1182                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1183 
1184         if (slave->data->phy_node) {
1185                 slave->phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1186                                  &cpsw_adjust_link, 0, slave->data->phy_if);
1187                 if (!slave->phy) {
1188                         dev_err(priv->dev, "phy \"%s\" not found on slave %d\n",
1189                                 slave->data->phy_node->full_name,
1190                                 slave->slave_num);
1191                         return;
1192                 }
1193         } else {
1194                 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1195                                  &cpsw_adjust_link, slave->data->phy_if);
1196                 if (IS_ERR(slave->phy)) {
1197                         dev_err(priv->dev,
1198                                 "phy \"%s\" not found on slave %d, err %ld\n",
1199                                 slave->data->phy_id, slave->slave_num,
1200                                 PTR_ERR(slave->phy));
1201                         slave->phy = NULL;
1202                         return;
1203                 }
1204         }
1205 
1206         phy_attached_info(slave->phy);
1207 
1208         phy_start(slave->phy);
1209 
1210         /* Configure GMII_SEL register */
1211         cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num);
1212 }
1213 
1214 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1215 {
1216         struct cpsw_common *cpsw = priv->cpsw;
1217         const int vlan = cpsw->data.default_vlan;
1218         u32 reg;
1219         int i;
1220         int unreg_mcast_mask;
1221 
1222         reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1223                CPSW2_PORT_VLAN;
1224 
1225         writel(vlan, &cpsw->host_port_regs->port_vlan);
1226 
1227         for (i = 0; i < cpsw->data.slaves; i++)
1228                 slave_write(cpsw->slaves + i, vlan, reg);
1229 
1230         if (priv->ndev->flags & IFF_ALLMULTI)
1231                 unreg_mcast_mask = ALE_ALL_PORTS;
1232         else
1233                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1234 
1235         cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS,
1236                           ALE_ALL_PORTS, ALE_ALL_PORTS,
1237                           unreg_mcast_mask);
1238 }
1239 
1240 static void cpsw_init_host_port(struct cpsw_priv *priv)
1241 {
1242         u32 fifo_mode;
1243         u32 control_reg;
1244         struct cpsw_common *cpsw = priv->cpsw;
1245 
1246         /* soft reset the controller and initialize ale */
1247         soft_reset("cpsw", &cpsw->regs->soft_reset);
1248         cpsw_ale_start(cpsw->ale);
1249 
1250         /* switch to vlan unaware mode */
1251         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1252                              CPSW_ALE_VLAN_AWARE);
1253         control_reg = readl(&cpsw->regs->control);
1254         control_reg |= CPSW_VLAN_AWARE;
1255         writel(control_reg, &cpsw->regs->control);
1256         fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1257                      CPSW_FIFO_NORMAL_MODE;
1258         writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
1259 
1260         /* setup host port priority mapping */
1261         __raw_writel(CPDMA_TX_PRIORITY_MAP,
1262                      &cpsw->host_port_regs->cpdma_tx_pri_map);
1263         __raw_writel(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
1264 
1265         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM,
1266                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1267 
1268         if (!cpsw->data.dual_emac) {
1269                 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1270                                    0, 0);
1271                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1272                                    ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1273         }
1274 }
1275 
1276 static int cpsw_fill_rx_channels(struct cpsw_priv *priv)
1277 {
1278         struct cpsw_common *cpsw = priv->cpsw;
1279         struct sk_buff *skb;
1280         int ch_buf_num;
1281         int ch, i, ret;
1282 
1283         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1284                 ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxch[ch]);
1285                 for (i = 0; i < ch_buf_num; i++) {
1286                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1287                                                           cpsw->rx_packet_max,
1288                                                           GFP_KERNEL);
1289                         if (!skb) {
1290                                 cpsw_err(priv, ifup, "cannot allocate skb\n");
1291                                 return -ENOMEM;
1292                         }
1293 
1294                         skb_set_queue_mapping(skb, ch);
1295                         ret = cpdma_chan_submit(cpsw->rxch[ch], skb, skb->data,
1296                                                 skb_tailroom(skb), 0);
1297                         if (ret < 0) {
1298                                 cpsw_err(priv, ifup,
1299                                          "cannot submit skb to channel %d rx, error %d\n",
1300                                          ch, ret);
1301                                 kfree_skb(skb);
1302                                 return ret;
1303                         }
1304                         kmemleak_not_leak(skb);
1305                 }
1306 
1307                 cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n",
1308                           ch, ch_buf_num);
1309         }
1310 
1311         return 0;
1312 }
1313 
1314 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
1315 {
1316         u32 slave_port;
1317 
1318         slave_port = cpsw_get_slave_port(slave->slave_num);
1319 
1320         if (!slave->phy)
1321                 return;
1322         phy_stop(slave->phy);
1323         phy_disconnect(slave->phy);
1324         slave->phy = NULL;
1325         cpsw_ale_control_set(cpsw->ale, slave_port,
1326                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1327         soft_reset_slave(slave);
1328 }
1329 
1330 static int cpsw_ndo_open(struct net_device *ndev)
1331 {
1332         struct cpsw_priv *priv = netdev_priv(ndev);
1333         struct cpsw_common *cpsw = priv->cpsw;
1334         int ret;
1335         u32 reg;
1336 
1337         ret = pm_runtime_get_sync(cpsw->dev);
1338         if (ret < 0) {
1339                 pm_runtime_put_noidle(cpsw->dev);
1340                 return ret;
1341         }
1342 
1343         if (!cpsw_common_res_usage_state(cpsw))
1344                 cpsw_intr_disable(cpsw);
1345         netif_carrier_off(ndev);
1346 
1347         /* Notify the stack of the actual queue counts. */
1348         ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num);
1349         if (ret) {
1350                 dev_err(priv->dev, "cannot set real number of tx queues\n");
1351                 goto err_cleanup;
1352         }
1353 
1354         ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num);
1355         if (ret) {
1356                 dev_err(priv->dev, "cannot set real number of rx queues\n");
1357                 goto err_cleanup;
1358         }
1359 
1360         reg = cpsw->version;
1361 
1362         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1363                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1364                  CPSW_RTL_VERSION(reg));
1365 
1366         /* initialize host and slave ports */
1367         if (!cpsw_common_res_usage_state(cpsw))
1368                 cpsw_init_host_port(priv);
1369         for_each_slave(priv, cpsw_slave_open, priv);
1370 
1371         /* Add default VLAN */
1372         if (!cpsw->data.dual_emac)
1373                 cpsw_add_default_vlan(priv);
1374         else
1375                 cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan,
1376                                   ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
1377 
1378         if (!cpsw_common_res_usage_state(cpsw)) {
1379                 /* setup tx dma to fixed prio and zero offset */
1380                 cpdma_control_set(cpsw->dma, CPDMA_TX_PRIO_FIXED, 1);
1381                 cpdma_control_set(cpsw->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1382 
1383                 /* disable priority elevation */
1384                 __raw_writel(0, &cpsw->regs->ptype);
1385 
1386                 /* enable statistics collection only on all ports */
1387                 __raw_writel(0x7, &cpsw->regs->stat_port_en);
1388 
1389                 /* Enable internal fifo flow control */
1390                 writel(0x7, &cpsw->regs->flow_control);
1391 
1392                 napi_enable(&cpsw->napi_rx);
1393                 napi_enable(&cpsw->napi_tx);
1394 
1395                 if (cpsw->tx_irq_disabled) {
1396                         cpsw->tx_irq_disabled = false;
1397                         enable_irq(cpsw->irqs_table[1]);
1398                 }
1399 
1400                 if (cpsw->rx_irq_disabled) {
1401                         cpsw->rx_irq_disabled = false;
1402                         enable_irq(cpsw->irqs_table[0]);
1403                 }
1404 
1405                 ret = cpsw_fill_rx_channels(priv);
1406                 if (ret < 0)
1407                         goto err_cleanup;
1408 
1409                 if (cpts_register(cpsw->dev, cpsw->cpts,
1410                                   cpsw->data.cpts_clock_mult,
1411                                   cpsw->data.cpts_clock_shift))
1412                         dev_err(priv->dev, "error registering cpts device\n");
1413 
1414         }
1415 
1416         /* Enable Interrupt pacing if configured */
1417         if (cpsw->coal_intvl != 0) {
1418                 struct ethtool_coalesce coal;
1419 
1420                 coal.rx_coalesce_usecs = cpsw->coal_intvl;
1421                 cpsw_set_coalesce(ndev, &coal);
1422         }
1423 
1424         cpdma_ctlr_start(cpsw->dma);
1425         cpsw_intr_enable(cpsw);
1426 
1427         if (cpsw->data.dual_emac)
1428                 cpsw->slaves[priv->emac_port].open_stat = true;
1429 
1430         netif_tx_start_all_queues(ndev);
1431 
1432         return 0;
1433 
1434 err_cleanup:
1435         cpdma_ctlr_stop(cpsw->dma);
1436         for_each_slave(priv, cpsw_slave_stop, cpsw);
1437         pm_runtime_put_sync(cpsw->dev);
1438         netif_carrier_off(priv->ndev);
1439         return ret;
1440 }
1441 
1442 static int cpsw_ndo_stop(struct net_device *ndev)
1443 {
1444         struct cpsw_priv *priv = netdev_priv(ndev);
1445         struct cpsw_common *cpsw = priv->cpsw;
1446 
1447         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1448         netif_tx_stop_all_queues(priv->ndev);
1449         netif_carrier_off(priv->ndev);
1450 
1451         if (cpsw_common_res_usage_state(cpsw) <= 1) {
1452                 napi_disable(&cpsw->napi_rx);
1453                 napi_disable(&cpsw->napi_tx);
1454                 cpts_unregister(cpsw->cpts);
1455                 cpsw_intr_disable(cpsw);
1456                 cpdma_ctlr_stop(cpsw->dma);
1457                 cpsw_ale_stop(cpsw->ale);
1458         }
1459         for_each_slave(priv, cpsw_slave_stop, cpsw);
1460         pm_runtime_put_sync(cpsw->dev);
1461         if (cpsw->data.dual_emac)
1462                 cpsw->slaves[priv->emac_port].open_stat = false;
1463         return 0;
1464 }
1465 
1466 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1467                                        struct net_device *ndev)
1468 {
1469         struct cpsw_priv *priv = netdev_priv(ndev);
1470         struct cpsw_common *cpsw = priv->cpsw;
1471         struct netdev_queue *txq;
1472         struct cpdma_chan *txch;
1473         int ret, q_idx;
1474 
1475         netif_trans_update(ndev);
1476 
1477         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1478                 cpsw_err(priv, tx_err, "packet pad failed\n");
1479                 ndev->stats.tx_dropped++;
1480                 return NETDEV_TX_OK;
1481         }
1482 
1483         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1484                                 cpsw->cpts->tx_enable)
1485                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1486 
1487         skb_tx_timestamp(skb);
1488 
1489         q_idx = skb_get_queue_mapping(skb);
1490         if (q_idx >= cpsw->tx_ch_num)
1491                 q_idx = q_idx % cpsw->tx_ch_num;
1492 
1493         txch = cpsw->txch[q_idx];
1494         ret = cpsw_tx_packet_submit(priv, skb, txch);
1495         if (unlikely(ret != 0)) {
1496                 cpsw_err(priv, tx_err, "desc submit failed\n");
1497                 goto fail;
1498         }
1499 
1500         /* If there is no more tx desc left free then we need to
1501          * tell the kernel to stop sending us tx frames.
1502          */
1503         if (unlikely(!cpdma_check_free_tx_desc(txch))) {
1504                 txq = netdev_get_tx_queue(ndev, q_idx);
1505                 netif_tx_stop_queue(txq);
1506         }
1507 
1508         return NETDEV_TX_OK;
1509 fail:
1510         ndev->stats.tx_dropped++;
1511         txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
1512         netif_tx_stop_queue(txq);
1513         return NETDEV_TX_BUSY;
1514 }
1515 
1516 #ifdef CONFIG_TI_CPTS
1517 
1518 static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw)
1519 {
1520         struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave];
1521         u32 ts_en, seq_id;
1522 
1523         if (!cpsw->cpts->tx_enable && !cpsw->cpts->rx_enable) {
1524                 slave_write(slave, 0, CPSW1_TS_CTL);
1525                 return;
1526         }
1527 
1528         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1529         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1530 
1531         if (cpsw->cpts->tx_enable)
1532                 ts_en |= CPSW_V1_TS_TX_EN;
1533 
1534         if (cpsw->cpts->rx_enable)
1535                 ts_en |= CPSW_V1_TS_RX_EN;
1536 
1537         slave_write(slave, ts_en, CPSW1_TS_CTL);
1538         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1539 }
1540 
1541 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1542 {
1543         struct cpsw_slave *slave;
1544         struct cpsw_common *cpsw = priv->cpsw;
1545         u32 ctrl, mtype;
1546 
1547         if (cpsw->data.dual_emac)
1548                 slave = &cpsw->slaves[priv->emac_port];
1549         else
1550                 slave = &cpsw->slaves[cpsw->data.active_slave];
1551 
1552         ctrl = slave_read(slave, CPSW2_CONTROL);
1553         switch (cpsw->version) {
1554         case CPSW_VERSION_2:
1555                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1556 
1557                 if (cpsw->cpts->tx_enable)
1558                         ctrl |= CTRL_V2_TX_TS_BITS;
1559 
1560                 if (cpsw->cpts->rx_enable)
1561                         ctrl |= CTRL_V2_RX_TS_BITS;
1562                 break;
1563         case CPSW_VERSION_3:
1564         default:
1565                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1566 
1567                 if (cpsw->cpts->tx_enable)
1568                         ctrl |= CTRL_V3_TX_TS_BITS;
1569 
1570                 if (cpsw->cpts->rx_enable)
1571                         ctrl |= CTRL_V3_RX_TS_BITS;
1572                 break;
1573         }
1574 
1575         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1576 
1577         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1578         slave_write(slave, ctrl, CPSW2_CONTROL);
1579         __raw_writel(ETH_P_1588, &cpsw->regs->ts_ltype);
1580 }
1581 
1582 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1583 {
1584         struct cpsw_priv *priv = netdev_priv(dev);
1585         struct hwtstamp_config cfg;
1586         struct cpsw_common *cpsw = priv->cpsw;
1587         struct cpts *cpts = cpsw->cpts;
1588 
1589         if (cpsw->version != CPSW_VERSION_1 &&
1590             cpsw->version != CPSW_VERSION_2 &&
1591             cpsw->version != CPSW_VERSION_3)
1592                 return -EOPNOTSUPP;
1593 
1594         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1595                 return -EFAULT;
1596 
1597         /* reserved for future extensions */
1598         if (cfg.flags)
1599                 return -EINVAL;
1600 
1601         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1602                 return -ERANGE;
1603 
1604         switch (cfg.rx_filter) {
1605         case HWTSTAMP_FILTER_NONE:
1606                 cpts->rx_enable = 0;
1607                 break;
1608         case HWTSTAMP_FILTER_ALL:
1609         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1610         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1611         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1612                 return -ERANGE;
1613         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1614         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1615         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1616         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1617         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1618         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1619         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1620         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1621         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1622                 cpts->rx_enable = 1;
1623                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1624                 break;
1625         default:
1626                 return -ERANGE;
1627         }
1628 
1629         cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1630 
1631         switch (cpsw->version) {
1632         case CPSW_VERSION_1:
1633                 cpsw_hwtstamp_v1(cpsw);
1634                 break;
1635         case CPSW_VERSION_2:
1636         case CPSW_VERSION_3:
1637                 cpsw_hwtstamp_v2(priv);
1638                 break;
1639         default:
1640                 WARN_ON(1);
1641         }
1642 
1643         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1644 }
1645 
1646 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1647 {
1648         struct cpsw_common *cpsw = ndev_to_cpsw(dev);
1649         struct cpts *cpts = cpsw->cpts;
1650         struct hwtstamp_config cfg;
1651 
1652         if (cpsw->version != CPSW_VERSION_1 &&
1653             cpsw->version != CPSW_VERSION_2 &&
1654             cpsw->version != CPSW_VERSION_3)
1655                 return -EOPNOTSUPP;
1656 
1657         cfg.flags = 0;
1658         cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1659         cfg.rx_filter = (cpts->rx_enable ?
1660                          HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1661 
1662         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1663 }
1664 
1665 #endif /*CONFIG_TI_CPTS*/
1666 
1667 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1668 {
1669         struct cpsw_priv *priv = netdev_priv(dev);
1670         struct cpsw_common *cpsw = priv->cpsw;
1671         int slave_no = cpsw_slave_index(cpsw, priv);
1672 
1673         if (!netif_running(dev))
1674                 return -EINVAL;
1675 
1676         switch (cmd) {
1677 #ifdef CONFIG_TI_CPTS
1678         case SIOCSHWTSTAMP:
1679                 return cpsw_hwtstamp_set(dev, req);
1680         case SIOCGHWTSTAMP:
1681                 return cpsw_hwtstamp_get(dev, req);
1682 #endif
1683         }
1684 
1685         if (!cpsw->slaves[slave_no].phy)
1686                 return -EOPNOTSUPP;
1687         return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd);
1688 }
1689 
1690 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1691 {
1692         struct cpsw_priv *priv = netdev_priv(ndev);
1693         struct cpsw_common *cpsw = priv->cpsw;
1694         int ch;
1695 
1696         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1697         ndev->stats.tx_errors++;
1698         cpsw_intr_disable(cpsw);
1699         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1700                 cpdma_chan_stop(cpsw->txch[ch]);
1701                 cpdma_chan_start(cpsw->txch[ch]);
1702         }
1703 
1704         cpsw_intr_enable(cpsw);
1705 }
1706 
1707 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1708 {
1709         struct cpsw_priv *priv = netdev_priv(ndev);
1710         struct sockaddr *addr = (struct sockaddr *)p;
1711         struct cpsw_common *cpsw = priv->cpsw;
1712         int flags = 0;
1713         u16 vid = 0;
1714         int ret;
1715 
1716         if (!is_valid_ether_addr(addr->sa_data))
1717                 return -EADDRNOTAVAIL;
1718 
1719         ret = pm_runtime_get_sync(cpsw->dev);
1720         if (ret < 0) {
1721                 pm_runtime_put_noidle(cpsw->dev);
1722                 return ret;
1723         }
1724 
1725         if (cpsw->data.dual_emac) {
1726                 vid = cpsw->slaves[priv->emac_port].port_vlan;
1727                 flags = ALE_VLAN;
1728         }
1729 
1730         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1731                            flags, vid);
1732         cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM,
1733                            flags, vid);
1734 
1735         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1736         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1737         for_each_slave(priv, cpsw_set_slave_mac, priv);
1738 
1739         pm_runtime_put(cpsw->dev);
1740 
1741         return 0;
1742 }
1743 
1744 #ifdef CONFIG_NET_POLL_CONTROLLER
1745 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1746 {
1747         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1748 
1749         cpsw_intr_disable(cpsw);
1750         cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw);
1751         cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw);
1752         cpsw_intr_enable(cpsw);
1753 }
1754 #endif
1755 
1756 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1757                                 unsigned short vid)
1758 {
1759         int ret;
1760         int unreg_mcast_mask = 0;
1761         u32 port_mask;
1762         struct cpsw_common *cpsw = priv->cpsw;
1763 
1764         if (cpsw->data.dual_emac) {
1765                 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1766 
1767                 if (priv->ndev->flags & IFF_ALLMULTI)
1768                         unreg_mcast_mask = port_mask;
1769         } else {
1770                 port_mask = ALE_ALL_PORTS;
1771 
1772                 if (priv->ndev->flags & IFF_ALLMULTI)
1773                         unreg_mcast_mask = ALE_ALL_PORTS;
1774                 else
1775                         unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1776         }
1777 
1778         ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask,
1779                                 unreg_mcast_mask);
1780         if (ret != 0)
1781                 return ret;
1782 
1783         ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1784                                  HOST_PORT_NUM, ALE_VLAN, vid);
1785         if (ret != 0)
1786                 goto clean_vid;
1787 
1788         ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1789                                  port_mask, ALE_VLAN, vid, 0);
1790         if (ret != 0)
1791                 goto clean_vlan_ucast;
1792         return 0;
1793 
1794 clean_vlan_ucast:
1795         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
1796                            HOST_PORT_NUM, ALE_VLAN, vid);
1797 clean_vid:
1798         cpsw_ale_del_vlan(cpsw->ale, vid, 0);
1799         return ret;
1800 }
1801 
1802 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1803                                     __be16 proto, u16 vid)
1804 {
1805         struct cpsw_priv *priv = netdev_priv(ndev);
1806         struct cpsw_common *cpsw = priv->cpsw;
1807         int ret;
1808 
1809         if (vid == cpsw->data.default_vlan)
1810                 return 0;
1811 
1812         ret = pm_runtime_get_sync(cpsw->dev);
1813         if (ret < 0) {
1814                 pm_runtime_put_noidle(cpsw->dev);
1815                 return ret;
1816         }
1817 
1818         if (cpsw->data.dual_emac) {
1819                 /* In dual EMAC, reserved VLAN id should not be used for
1820                  * creating VLAN interfaces as this can break the dual
1821                  * EMAC port separation
1822                  */
1823                 int i;
1824 
1825                 for (i = 0; i < cpsw->data.slaves; i++) {
1826                         if (vid == cpsw->slaves[i].port_vlan)
1827                                 return -EINVAL;
1828                 }
1829         }
1830 
1831         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1832         ret = cpsw_add_vlan_ale_entry(priv, vid);
1833 
1834         pm_runtime_put(cpsw->dev);
1835         return ret;
1836 }
1837 
1838 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1839                                      __be16 proto, u16 vid)
1840 {
1841         struct cpsw_priv *priv = netdev_priv(ndev);
1842         struct cpsw_common *cpsw = priv->cpsw;
1843         int ret;
1844 
1845         if (vid == cpsw->data.default_vlan)
1846                 return 0;
1847 
1848         ret = pm_runtime_get_sync(cpsw->dev);
1849         if (ret < 0) {
1850                 pm_runtime_put_noidle(cpsw->dev);
1851                 return ret;
1852         }
1853 
1854         if (cpsw->data.dual_emac) {
1855                 int i;
1856 
1857                 for (i = 0; i < cpsw->data.slaves; i++) {
1858                         if (vid == cpsw->slaves[i].port_vlan)
1859                                 return -EINVAL;
1860                 }
1861         }
1862 
1863         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1864         ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0);
1865         if (ret != 0)
1866                 return ret;
1867 
1868         ret = cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
1869                                  HOST_PORT_NUM, ALE_VLAN, vid);
1870         if (ret != 0)
1871                 return ret;
1872 
1873         ret = cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast,
1874                                  0, ALE_VLAN, vid);
1875         pm_runtime_put(cpsw->dev);
1876         return ret;
1877 }
1878 
1879 static const struct net_device_ops cpsw_netdev_ops = {
1880         .ndo_open               = cpsw_ndo_open,
1881         .ndo_stop               = cpsw_ndo_stop,
1882         .ndo_start_xmit         = cpsw_ndo_start_xmit,
1883         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
1884         .ndo_do_ioctl           = cpsw_ndo_ioctl,
1885         .ndo_validate_addr      = eth_validate_addr,
1886         .ndo_change_mtu         = eth_change_mtu,
1887         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
1888         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
1889 #ifdef CONFIG_NET_POLL_CONTROLLER
1890         .ndo_poll_controller    = cpsw_ndo_poll_controller,
1891 #endif
1892         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
1893         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
1894 };
1895 
1896 static int cpsw_get_regs_len(struct net_device *ndev)
1897 {
1898         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1899 
1900         return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1901 }
1902 
1903 static void cpsw_get_regs(struct net_device *ndev,
1904                           struct ethtool_regs *regs, void *p)
1905 {
1906         u32 *reg = p;
1907         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1908 
1909         /* update CPSW IP version */
1910         regs->version = cpsw->version;
1911 
1912         cpsw_ale_dump(cpsw->ale, reg);
1913 }
1914 
1915 static void cpsw_get_drvinfo(struct net_device *ndev,
1916                              struct ethtool_drvinfo *info)
1917 {
1918         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1919         struct platform_device  *pdev = to_platform_device(cpsw->dev);
1920 
1921         strlcpy(info->driver, "cpsw", sizeof(info->driver));
1922         strlcpy(info->version, "1.0", sizeof(info->version));
1923         strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
1924 }
1925 
1926 static u32 cpsw_get_msglevel(struct net_device *ndev)
1927 {
1928         struct cpsw_priv *priv = netdev_priv(ndev);
1929         return priv->msg_enable;
1930 }
1931 
1932 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1933 {
1934         struct cpsw_priv *priv = netdev_priv(ndev);
1935         priv->msg_enable = value;
1936 }
1937 
1938 static int cpsw_get_ts_info(struct net_device *ndev,
1939                             struct ethtool_ts_info *info)
1940 {
1941 #ifdef CONFIG_TI_CPTS
1942         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1943 
1944         info->so_timestamping =
1945                 SOF_TIMESTAMPING_TX_HARDWARE |
1946                 SOF_TIMESTAMPING_TX_SOFTWARE |
1947                 SOF_TIMESTAMPING_RX_HARDWARE |
1948                 SOF_TIMESTAMPING_RX_SOFTWARE |
1949                 SOF_TIMESTAMPING_SOFTWARE |
1950                 SOF_TIMESTAMPING_RAW_HARDWARE;
1951         info->phc_index = cpsw->cpts->phc_index;
1952         info->tx_types =
1953                 (1 << HWTSTAMP_TX_OFF) |
1954                 (1 << HWTSTAMP_TX_ON);
1955         info->rx_filters =
1956                 (1 << HWTSTAMP_FILTER_NONE) |
1957                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1958 #else
1959         info->so_timestamping =
1960                 SOF_TIMESTAMPING_TX_SOFTWARE |
1961                 SOF_TIMESTAMPING_RX_SOFTWARE |
1962                 SOF_TIMESTAMPING_SOFTWARE;
1963         info->phc_index = -1;
1964         info->tx_types = 0;
1965         info->rx_filters = 0;
1966 #endif
1967         return 0;
1968 }
1969 
1970 static int cpsw_get_settings(struct net_device *ndev,
1971                              struct ethtool_cmd *ecmd)
1972 {
1973         struct cpsw_priv *priv = netdev_priv(ndev);
1974         struct cpsw_common *cpsw = priv->cpsw;
1975         int slave_no = cpsw_slave_index(cpsw, priv);
1976 
1977         if (cpsw->slaves[slave_no].phy)
1978                 return phy_ethtool_gset(cpsw->slaves[slave_no].phy, ecmd);
1979         else
1980                 return -EOPNOTSUPP;
1981 }
1982 
1983 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1984 {
1985         struct cpsw_priv *priv = netdev_priv(ndev);
1986         struct cpsw_common *cpsw = priv->cpsw;
1987         int slave_no = cpsw_slave_index(cpsw, priv);
1988 
1989         if (cpsw->slaves[slave_no].phy)
1990                 return phy_ethtool_sset(cpsw->slaves[slave_no].phy, ecmd);
1991         else
1992                 return -EOPNOTSUPP;
1993 }
1994 
1995 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1996 {
1997         struct cpsw_priv *priv = netdev_priv(ndev);
1998         struct cpsw_common *cpsw = priv->cpsw;
1999         int slave_no = cpsw_slave_index(cpsw, priv);
2000 
2001         wol->supported = 0;
2002         wol->wolopts = 0;
2003 
2004         if (cpsw->slaves[slave_no].phy)
2005                 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
2006 }
2007 
2008 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2009 {
2010         struct cpsw_priv *priv = netdev_priv(ndev);
2011         struct cpsw_common *cpsw = priv->cpsw;
2012         int slave_no = cpsw_slave_index(cpsw, priv);
2013 
2014         if (cpsw->slaves[slave_no].phy)
2015                 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
2016         else
2017                 return -EOPNOTSUPP;
2018 }
2019 
2020 static void cpsw_get_pauseparam(struct net_device *ndev,
2021                                 struct ethtool_pauseparam *pause)
2022 {
2023         struct cpsw_priv *priv = netdev_priv(ndev);
2024 
2025         pause->autoneg = AUTONEG_DISABLE;
2026         pause->rx_pause = priv->rx_pause ? true : false;
2027         pause->tx_pause = priv->tx_pause ? true : false;
2028 }
2029 
2030 static int cpsw_set_pauseparam(struct net_device *ndev,
2031                                struct ethtool_pauseparam *pause)
2032 {
2033         struct cpsw_priv *priv = netdev_priv(ndev);
2034         bool link;
2035 
2036         priv->rx_pause = pause->rx_pause ? true : false;
2037         priv->tx_pause = pause->tx_pause ? true : false;
2038 
2039         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
2040         return 0;
2041 }
2042 
2043 static int cpsw_ethtool_op_begin(struct net_device *ndev)
2044 {
2045         struct cpsw_priv *priv = netdev_priv(ndev);
2046         struct cpsw_common *cpsw = priv->cpsw;
2047         int ret;
2048 
2049         ret = pm_runtime_get_sync(cpsw->dev);
2050         if (ret < 0) {
2051                 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
2052                 pm_runtime_put_noidle(cpsw->dev);
2053         }
2054 
2055         return ret;
2056 }
2057 
2058 static void cpsw_ethtool_op_complete(struct net_device *ndev)
2059 {
2060         struct cpsw_priv *priv = netdev_priv(ndev);
2061         int ret;
2062 
2063         ret = pm_runtime_put(priv->cpsw->dev);
2064         if (ret < 0)
2065                 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
2066 }
2067 
2068 static void cpsw_get_channels(struct net_device *ndev,
2069                               struct ethtool_channels *ch)
2070 {
2071         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2072 
2073         ch->max_combined = 0;
2074         ch->max_rx = CPSW_MAX_QUEUES;
2075         ch->max_tx = CPSW_MAX_QUEUES;
2076         ch->max_other = 0;
2077         ch->other_count = 0;
2078         ch->rx_count = cpsw->rx_ch_num;
2079         ch->tx_count = cpsw->tx_ch_num;
2080         ch->combined_count = 0;
2081 }
2082 
2083 static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
2084                                   struct ethtool_channels *ch)
2085 {
2086         if (ch->combined_count)
2087                 return -EINVAL;
2088 
2089         /* verify we have at least one channel in each direction */
2090         if (!ch->rx_count || !ch->tx_count)
2091                 return -EINVAL;
2092 
2093         if (ch->rx_count > cpsw->data.channels ||
2094             ch->tx_count > cpsw->data.channels)
2095                 return -EINVAL;
2096 
2097         return 0;
2098 }
2099 
2100 static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
2101 {
2102         int (*poll)(struct napi_struct *, int);
2103         struct cpsw_common *cpsw = priv->cpsw;
2104         void (*handler)(void *, int, int);
2105         struct cpdma_chan **chan;
2106         int ret, *ch;
2107 
2108         if (rx) {
2109                 ch = &cpsw->rx_ch_num;
2110                 chan = cpsw->rxch;
2111                 handler = cpsw_rx_handler;
2112                 poll = cpsw_rx_poll;
2113         } else {
2114                 ch = &cpsw->tx_ch_num;
2115                 chan = cpsw->txch;
2116                 handler = cpsw_tx_handler;
2117                 poll = cpsw_tx_poll;
2118         }
2119 
2120         while (*ch < ch_num) {
2121                 chan[*ch] = cpdma_chan_create(cpsw->dma, *ch, handler, rx);
2122 
2123                 if (IS_ERR(chan[*ch]))
2124                         return PTR_ERR(chan[*ch]);
2125 
2126                 if (!chan[*ch])
2127                         return -EINVAL;
2128 
2129                 cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
2130                           (rx ? "rx" : "tx"));
2131                 (*ch)++;
2132         }
2133 
2134         while (*ch > ch_num) {
2135                 (*ch)--;
2136 
2137                 ret = cpdma_chan_destroy(chan[*ch]);
2138                 if (ret)
2139                         return ret;
2140 
2141                 cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
2142                           (rx ? "rx" : "tx"));
2143         }
2144 
2145         return 0;
2146 }
2147 
2148 static int cpsw_update_channels(struct cpsw_priv *priv,
2149                                 struct ethtool_channels *ch)
2150 {
2151         int ret;
2152 
2153         ret = cpsw_update_channels_res(priv, ch->rx_count, 1);
2154         if (ret)
2155                 return ret;
2156 
2157         ret = cpsw_update_channels_res(priv, ch->tx_count, 0);
2158         if (ret)
2159                 return ret;
2160 
2161         return 0;
2162 }
2163 
2164 static int cpsw_set_channels(struct net_device *ndev,
2165                              struct ethtool_channels *chs)
2166 {
2167         struct cpsw_priv *priv = netdev_priv(ndev);
2168         struct cpsw_common *cpsw = priv->cpsw;
2169         struct cpsw_slave *slave;
2170         int i, ret;
2171 
2172         ret = cpsw_check_ch_settings(cpsw, chs);
2173         if (ret < 0)
2174                 return ret;
2175 
2176         /* Disable NAPI scheduling */
2177         cpsw_intr_disable(cpsw);
2178 
2179         /* Stop all transmit queues for every network device.
2180          * Disable re-using rx descriptors with dormant_on.
2181          */
2182         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2183                 if (!(slave->ndev && netif_running(slave->ndev)))
2184                         continue;
2185 
2186                 netif_tx_stop_all_queues(slave->ndev);
2187                 netif_dormant_on(slave->ndev);
2188         }
2189 
2190         /* Handle rest of tx packets and stop cpdma channels */
2191         cpdma_ctlr_stop(cpsw->dma);
2192         ret = cpsw_update_channels(priv, chs);
2193         if (ret)
2194                 goto err;
2195 
2196         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2197                 if (!(slave->ndev && netif_running(slave->ndev)))
2198                         continue;
2199 
2200                 /* Inform stack about new count of queues */
2201                 ret = netif_set_real_num_tx_queues(slave->ndev,
2202                                                    cpsw->tx_ch_num);
2203                 if (ret) {
2204                         dev_err(priv->dev, "cannot set real number of tx queues\n");
2205                         goto err;
2206                 }
2207 
2208                 ret = netif_set_real_num_rx_queues(slave->ndev,
2209                                                    cpsw->rx_ch_num);
2210                 if (ret) {
2211                         dev_err(priv->dev, "cannot set real number of rx queues\n");
2212                         goto err;
2213                 }
2214 
2215                 /* Enable rx packets handling */
2216                 netif_dormant_off(slave->ndev);
2217         }
2218 
2219         if (cpsw_common_res_usage_state(cpsw)) {
2220                 ret = cpsw_fill_rx_channels(priv);
2221                 if (ret)
2222                         goto err;
2223 
2224                 /* After this receive is started */
2225                 cpdma_ctlr_start(cpsw->dma);
2226                 cpsw_intr_enable(cpsw);
2227         }
2228 
2229         /* Resume transmit for every affected interface */
2230         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2231                 if (!(slave->ndev && netif_running(slave->ndev)))
2232                         continue;
2233                 netif_tx_start_all_queues(slave->ndev);
2234         }
2235         return 0;
2236 err:
2237         dev_err(priv->dev, "cannot update channels number, closing device\n");
2238         dev_close(ndev);
2239         return ret;
2240 }
2241 
2242 static const struct ethtool_ops cpsw_ethtool_ops = {
2243         .get_drvinfo    = cpsw_get_drvinfo,
2244         .get_msglevel   = cpsw_get_msglevel,
2245         .set_msglevel   = cpsw_set_msglevel,
2246         .get_link       = ethtool_op_get_link,
2247         .get_ts_info    = cpsw_get_ts_info,
2248         .get_settings   = cpsw_get_settings,
2249         .set_settings   = cpsw_set_settings,
2250         .get_coalesce   = cpsw_get_coalesce,
2251         .set_coalesce   = cpsw_set_coalesce,
2252         .get_sset_count         = cpsw_get_sset_count,
2253         .get_strings            = cpsw_get_strings,
2254         .get_ethtool_stats      = cpsw_get_ethtool_stats,
2255         .get_pauseparam         = cpsw_get_pauseparam,
2256         .set_pauseparam         = cpsw_set_pauseparam,
2257         .get_wol        = cpsw_get_wol,
2258         .set_wol        = cpsw_set_wol,
2259         .get_regs_len   = cpsw_get_regs_len,
2260         .get_regs       = cpsw_get_regs,
2261         .begin          = cpsw_ethtool_op_begin,
2262         .complete       = cpsw_ethtool_op_complete,
2263         .get_channels   = cpsw_get_channels,
2264         .set_channels   = cpsw_set_channels,
2265 };
2266 
2267 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw,
2268                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
2269 {
2270         void __iomem            *regs = cpsw->regs;
2271         int                     slave_num = slave->slave_num;
2272         struct cpsw_slave_data  *data = cpsw->data.slave_data + slave_num;
2273 
2274         slave->data     = data;
2275         slave->regs     = regs + slave_reg_ofs;
2276         slave->sliver   = regs + sliver_reg_ofs;
2277         slave->port_vlan = data->dual_emac_res_vlan;
2278 }
2279 
2280 static int cpsw_probe_dt(struct cpsw_platform_data *data,
2281                          struct platform_device *pdev)
2282 {
2283         struct device_node *node = pdev->dev.of_node;
2284         struct device_node *slave_node;
2285         int i = 0, ret;
2286         u32 prop;
2287 
2288         if (!node)
2289                 return -EINVAL;
2290 
2291         if (of_property_read_u32(node, "slaves", &prop)) {
2292                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2293                 return -EINVAL;
2294         }
2295         data->slaves = prop;
2296 
2297         if (of_property_read_u32(node, "active_slave", &prop)) {
2298                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
2299                 return -EINVAL;
2300         }
2301         data->active_slave = prop;
2302 
2303         if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
2304                 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
2305                 return -EINVAL;
2306         }
2307         data->cpts_clock_mult = prop;
2308 
2309         if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
2310                 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
2311                 return -EINVAL;
2312         }
2313         data->cpts_clock_shift = prop;
2314 
2315         data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
2316                                         * sizeof(struct cpsw_slave_data),
2317                                         GFP_KERNEL);
2318         if (!data->slave_data)
2319                 return -ENOMEM;
2320 
2321         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
2322                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
2323                 return -EINVAL;
2324         }
2325         data->channels = prop;
2326 
2327         if (of_property_read_u32(node, "ale_entries", &prop)) {
2328                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
2329                 return -EINVAL;
2330         }
2331         data->ale_entries = prop;
2332 
2333         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
2334                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
2335                 return -EINVAL;
2336         }
2337         data->bd_ram_size = prop;
2338 
2339         if (of_property_read_u32(node, "mac_control", &prop)) {
2340                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2341                 return -EINVAL;
2342         }
2343         data->mac_control = prop;
2344 
2345         if (of_property_read_bool(node, "dual_emac"))
2346                 data->dual_emac = 1;
2347 
2348         /*
2349          * Populate all the child nodes here...
2350          */
2351         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2352         /* We do not want to force this, as in some cases may not have child */
2353         if (ret)
2354                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2355 
2356         for_each_available_child_of_node(node, slave_node) {
2357                 struct cpsw_slave_data *slave_data = data->slave_data + i;
2358                 const void *mac_addr = NULL;
2359                 int lenp;
2360                 const __be32 *parp;
2361 
2362                 /* This is no slave child node, continue */
2363                 if (strcmp(slave_node->name, "slave"))
2364                         continue;
2365 
2366                 slave_data->phy_node = of_parse_phandle(slave_node,
2367                                                         "phy-handle", 0);
2368                 parp = of_get_property(slave_node, "phy_id", &lenp);
2369                 if (slave_data->phy_node) {
2370                         dev_dbg(&pdev->dev,
2371                                 "slave[%d] using phy-handle=\"%s\"\n",
2372                                 i, slave_data->phy_node->full_name);
2373                 } else if (of_phy_is_fixed_link(slave_node)) {
2374                         /* In the case of a fixed PHY, the DT node associated
2375                          * to the PHY is the Ethernet MAC DT node.
2376                          */
2377                         ret = of_phy_register_fixed_link(slave_node);
2378                         if (ret) {
2379                                 if (ret != -EPROBE_DEFER)
2380                                         dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret);
2381                                 return ret;
2382                         }
2383                         slave_data->phy_node = of_node_get(slave_node);
2384                 } else if (parp) {
2385                         u32 phyid;
2386                         struct device_node *mdio_node;
2387                         struct platform_device *mdio;
2388 
2389                         if (lenp != (sizeof(__be32) * 2)) {
2390                                 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2391                                 goto no_phy_slave;
2392                         }
2393                         mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2394                         phyid = be32_to_cpup(parp+1);
2395                         mdio = of_find_device_by_node(mdio_node);
2396                         of_node_put(mdio_node);
2397                         if (!mdio) {
2398                                 dev_err(&pdev->dev, "Missing mdio platform device\n");
2399                                 return -EINVAL;
2400                         }
2401                         snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2402                                  PHY_ID_FMT, mdio->name, phyid);
2403                         put_device(&mdio->dev);
2404                 } else {
2405                         dev_err(&pdev->dev,
2406                                 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2407                                 i);
2408                         goto no_phy_slave;
2409                 }
2410                 slave_data->phy_if = of_get_phy_mode(slave_node);
2411                 if (slave_data->phy_if < 0) {
2412                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2413                                 i);
2414                         return slave_data->phy_if;
2415                 }
2416 
2417 no_phy_slave:
2418                 mac_addr = of_get_mac_address(slave_node);
2419                 if (mac_addr) {
2420                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2421                 } else {
2422                         ret = ti_cm_get_macid(&pdev->dev, i,
2423                                               slave_data->mac_addr);
2424                         if (ret)
2425                                 return ret;
2426                 }
2427                 if (data->dual_emac) {
2428                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2429                                                  &prop)) {
2430                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2431                                 slave_data->dual_emac_res_vlan = i+1;
2432                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2433                                         slave_data->dual_emac_res_vlan, i);
2434                         } else {
2435                                 slave_data->dual_emac_res_vlan = prop;
2436                         }
2437                 }
2438 
2439                 i++;
2440                 if (i == data->slaves)
2441                         break;
2442         }
2443 
2444         return 0;
2445 }
2446 
2447 static void cpsw_remove_dt(struct platform_device *pdev)
2448 {
2449         struct net_device *ndev = platform_get_drvdata(pdev);
2450         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2451         struct cpsw_platform_data *data = &cpsw->data;
2452         struct device_node *node = pdev->dev.of_node;
2453         struct device_node *slave_node;
2454         int i = 0;
2455 
2456         for_each_available_child_of_node(node, slave_node) {
2457                 struct cpsw_slave_data *slave_data = &data->slave_data[i];
2458 
2459                 if (strcmp(slave_node->name, "slave"))
2460                         continue;
2461 
2462                 if (of_phy_is_fixed_link(slave_node))
2463                         of_phy_deregister_fixed_link(slave_node);
2464 
2465                 of_node_put(slave_data->phy_node);
2466 
2467                 i++;
2468                 if (i == data->slaves)
2469                         break;
2470         }
2471 
2472         of_platform_depopulate(&pdev->dev);
2473 }
2474 
2475 static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
2476 {
2477         struct cpsw_common              *cpsw = priv->cpsw;
2478         struct cpsw_platform_data       *data = &cpsw->data;
2479         struct net_device               *ndev;
2480         struct cpsw_priv                *priv_sl2;
2481         int ret = 0;
2482 
2483         ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2484         if (!ndev) {
2485                 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
2486                 return -ENOMEM;
2487         }
2488 
2489         priv_sl2 = netdev_priv(ndev);
2490         priv_sl2->cpsw = cpsw;
2491         priv_sl2->ndev = ndev;
2492         priv_sl2->dev  = &ndev->dev;
2493         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2494 
2495         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2496                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2497                         ETH_ALEN);
2498                 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n",
2499                          priv_sl2->mac_addr);
2500         } else {
2501                 random_ether_addr(priv_sl2->mac_addr);
2502                 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n",
2503                          priv_sl2->mac_addr);
2504         }
2505         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2506 
2507         priv_sl2->emac_port = 1;
2508         cpsw->slaves[1].ndev = ndev;
2509         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2510 
2511         ndev->netdev_ops = &cpsw_netdev_ops;
2512         ndev->ethtool_ops = &cpsw_ethtool_ops;
2513 
2514         /* register the network device */
2515         SET_NETDEV_DEV(ndev, cpsw->dev);
2516         ret = register_netdev(ndev);
2517         if (ret) {
2518                 dev_err(cpsw->dev, "cpsw: error registering net device\n");
2519                 free_netdev(ndev);
2520                 ret = -ENODEV;
2521         }
2522 
2523         return ret;
2524 }
2525 
2526 #define CPSW_QUIRK_IRQ          BIT(0)
2527 
2528 static struct platform_device_id cpsw_devtype[] = {
2529         {
2530                 /* keep it for existing comaptibles */
2531                 .name = "cpsw",
2532                 .driver_data = CPSW_QUIRK_IRQ,
2533         }, {
2534                 .name = "am335x-cpsw",
2535                 .driver_data = CPSW_QUIRK_IRQ,
2536         }, {
2537                 .name = "am4372-cpsw",
2538                 .driver_data = 0,
2539         }, {
2540                 .name = "dra7-cpsw",
2541                 .driver_data = 0,
2542         }, {
2543                 /* sentinel */
2544         }
2545 };
2546 MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2547 
2548 enum ti_cpsw_type {
2549         CPSW = 0,
2550         AM335X_CPSW,
2551         AM4372_CPSW,
2552         DRA7_CPSW,
2553 };
2554 
2555 static const struct of_device_id cpsw_of_mtable[] = {
2556         { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2557         { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2558         { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2559         { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2560         { /* sentinel */ },
2561 };
2562 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2563 
2564 static int cpsw_probe(struct platform_device *pdev)
2565 {
2566         struct clk                      *clk;
2567         struct cpsw_platform_data       *data;
2568         struct net_device               *ndev;
2569         struct cpsw_priv                *priv;
2570         struct cpdma_params             dma_params;
2571         struct cpsw_ale_params          ale_params;
2572         void __iomem                    *ss_regs;
2573         struct resource                 *res, *ss_res;
2574         const struct of_device_id       *of_id;
2575         struct gpio_descs               *mode;
2576         u32 slave_offset, sliver_offset, slave_size;
2577         struct cpsw_common              *cpsw;
2578         int ret = 0, i;
2579         int irq;
2580 
2581         cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL);
2582         if (!cpsw)
2583                 return -ENOMEM;
2584 
2585         cpsw->dev = &pdev->dev;
2586 
2587         ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2588         if (!ndev) {
2589                 dev_err(&pdev->dev, "error allocating net_device\n");
2590                 return -ENOMEM;
2591         }
2592 
2593         platform_set_drvdata(pdev, ndev);
2594         priv = netdev_priv(ndev);
2595         priv->cpsw = cpsw;
2596         priv->ndev = ndev;
2597         priv->dev  = &ndev->dev;
2598         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2599         cpsw->rx_packet_max = max(rx_packet_max, 128);
2600         cpsw->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2601         if (!cpsw->cpts) {
2602                 dev_err(&pdev->dev, "error allocating cpts\n");
2603                 ret = -ENOMEM;
2604                 goto clean_ndev_ret;
2605         }
2606 
2607         mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2608         if (IS_ERR(mode)) {
2609                 ret = PTR_ERR(mode);
2610                 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2611                 goto clean_ndev_ret;
2612         }
2613 
2614         /*
2615          * This may be required here for child devices.
2616          */
2617         pm_runtime_enable(&pdev->dev);
2618 
2619         /* Select default pin state */
2620         pinctrl_pm_select_default_state(&pdev->dev);
2621 
2622         /* Need to enable clocks with runtime PM api to access module
2623          * registers
2624          */
2625         ret = pm_runtime_get_sync(&pdev->dev);
2626         if (ret < 0) {
2627                 pm_runtime_put_noidle(&pdev->dev);
2628                 goto clean_runtime_disable_ret;
2629         }
2630 
2631         ret = cpsw_probe_dt(&cpsw->data, pdev);
2632         if (ret)
2633                 goto clean_dt_ret;
2634 
2635         data = &cpsw->data;
2636         cpsw->rx_ch_num = 1;
2637         cpsw->tx_ch_num = 1;
2638 
2639         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2640                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2641                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2642         } else {
2643                 eth_random_addr(priv->mac_addr);
2644                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2645         }
2646 
2647         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2648 
2649         cpsw->slaves = devm_kzalloc(&pdev->dev,
2650                                     sizeof(struct cpsw_slave) * data->slaves,
2651                                     GFP_KERNEL);
2652         if (!cpsw->slaves) {
2653                 ret = -ENOMEM;
2654                 goto clean_dt_ret;
2655         }
2656         for (i = 0; i < data->slaves; i++)
2657                 cpsw->slaves[i].slave_num = i;
2658 
2659         cpsw->slaves[0].ndev = ndev;
2660         priv->emac_port = 0;
2661 
2662         clk = devm_clk_get(&pdev->dev, "fck");
2663         if (IS_ERR(clk)) {
2664                 dev_err(priv->dev, "fck is not found\n");
2665                 ret = -ENODEV;
2666                 goto clean_dt_ret;
2667         }
2668         cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000;
2669 
2670         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2671         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2672         if (IS_ERR(ss_regs)) {
2673                 ret = PTR_ERR(ss_regs);
2674                 goto clean_dt_ret;
2675         }
2676         cpsw->regs = ss_regs;
2677 
2678         cpsw->version = readl(&cpsw->regs->id_ver);
2679 
2680         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2681         cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2682         if (IS_ERR(cpsw->wr_regs)) {
2683                 ret = PTR_ERR(cpsw->wr_regs);
2684                 goto clean_dt_ret;
2685         }
2686 
2687         memset(&dma_params, 0, sizeof(dma_params));
2688         memset(&ale_params, 0, sizeof(ale_params));
2689 
2690         switch (cpsw->version) {
2691         case CPSW_VERSION_1:
2692                 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2693                 cpsw->cpts->reg      = ss_regs + CPSW1_CPTS_OFFSET;
2694                 cpsw->hw_stats       = ss_regs + CPSW1_HW_STATS;
2695                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
2696                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
2697                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
2698                 slave_offset         = CPSW1_SLAVE_OFFSET;
2699                 slave_size           = CPSW1_SLAVE_SIZE;
2700                 sliver_offset        = CPSW1_SLIVER_OFFSET;
2701                 dma_params.desc_mem_phys = 0;
2702                 break;
2703         case CPSW_VERSION_2:
2704         case CPSW_VERSION_3:
2705         case CPSW_VERSION_4:
2706                 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2707                 cpsw->cpts->reg      = ss_regs + CPSW2_CPTS_OFFSET;
2708                 cpsw->hw_stats       = ss_regs + CPSW2_HW_STATS;
2709                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
2710                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
2711                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
2712                 slave_offset         = CPSW2_SLAVE_OFFSET;
2713                 slave_size           = CPSW2_SLAVE_SIZE;
2714                 sliver_offset        = CPSW2_SLIVER_OFFSET;
2715                 dma_params.desc_mem_phys =
2716                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2717                 break;
2718         default:
2719                 dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version);
2720                 ret = -ENODEV;
2721                 goto clean_dt_ret;
2722         }
2723         for (i = 0; i < cpsw->data.slaves; i++) {
2724                 struct cpsw_slave *slave = &cpsw->slaves[i];
2725 
2726                 cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset);
2727                 slave_offset  += slave_size;
2728                 sliver_offset += SLIVER_SIZE;
2729         }
2730 
2731         dma_params.dev          = &pdev->dev;
2732         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
2733         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
2734         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
2735         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
2736         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
2737 
2738         dma_params.num_chan             = data->channels;
2739         dma_params.has_soft_reset       = true;
2740         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
2741         dma_params.desc_mem_size        = data->bd_ram_size;
2742         dma_params.desc_align           = 16;
2743         dma_params.has_ext_regs         = true;
2744         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
2745 
2746         cpsw->dma = cpdma_ctlr_create(&dma_params);
2747         if (!cpsw->dma) {
2748                 dev_err(priv->dev, "error initializing dma\n");
2749                 ret = -ENOMEM;
2750                 goto clean_dt_ret;
2751         }
2752 
2753         cpsw->txch[0] = cpdma_chan_create(cpsw->dma, 0, cpsw_tx_handler, 0);
2754         cpsw->rxch[0] = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1);
2755         if (WARN_ON(!cpsw->rxch[0] || !cpsw->txch[0])) {
2756                 dev_err(priv->dev, "error initializing dma channels\n");
2757                 ret = -ENOMEM;
2758                 goto clean_dma_ret;
2759         }
2760 
2761         ale_params.dev                  = &ndev->dev;
2762         ale_params.ale_ageout           = ale_ageout;
2763         ale_params.ale_entries          = data->ale_entries;
2764         ale_params.ale_ports            = data->slaves;
2765 
2766         cpsw->ale = cpsw_ale_create(&ale_params);
2767         if (!cpsw->ale) {
2768                 dev_err(priv->dev, "error initializing ale engine\n");
2769                 ret = -ENODEV;
2770                 goto clean_dma_ret;
2771         }
2772 
2773         ndev->irq = platform_get_irq(pdev, 1);
2774         if (ndev->irq < 0) {
2775                 dev_err(priv->dev, "error getting irq resource\n");
2776                 ret = ndev->irq;
2777                 goto clean_ale_ret;
2778         }
2779 
2780         of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
2781         if (of_id) {
2782                 pdev->id_entry = of_id->data;
2783                 if (pdev->id_entry->driver_data)
2784                         cpsw->quirk_irq = true;
2785         }
2786 
2787         /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2788          * MISC IRQs which are always kept disabled with this driver so
2789          * we will not request them.
2790          *
2791          * If anyone wants to implement support for those, make sure to
2792          * first request and append them to irqs_table array.
2793          */
2794 
2795         /* RX IRQ */
2796         irq = platform_get_irq(pdev, 1);
2797         if (irq < 0) {
2798                 ret = irq;
2799                 goto clean_ale_ret;
2800         }
2801 
2802         cpsw->irqs_table[0] = irq;
2803         ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
2804                                0, dev_name(&pdev->dev), cpsw);
2805         if (ret < 0) {
2806                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2807                 goto clean_ale_ret;
2808         }
2809 
2810         /* TX IRQ */
2811         irq = platform_get_irq(pdev, 2);
2812         if (irq < 0) {
2813                 ret = irq;
2814                 goto clean_ale_ret;
2815         }
2816 
2817         cpsw->irqs_table[1] = irq;
2818         ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
2819                                0, dev_name(&pdev->dev), cpsw);
2820         if (ret < 0) {
2821                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2822                 goto clean_ale_ret;
2823         }
2824 
2825         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2826 
2827         ndev->netdev_ops = &cpsw_netdev_ops;
2828         ndev->ethtool_ops = &cpsw_ethtool_ops;
2829         netif_napi_add(ndev, &cpsw->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
2830         netif_tx_napi_add(ndev, &cpsw->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
2831 
2832         /* register the network device */
2833         SET_NETDEV_DEV(ndev, &pdev->dev);
2834         ret = register_netdev(ndev);
2835         if (ret) {
2836                 dev_err(priv->dev, "error registering net device\n");
2837                 ret = -ENODEV;
2838                 goto clean_ale_ret;
2839         }
2840 
2841         cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2842                     &ss_res->start, ndev->irq);
2843 
2844         if (cpsw->data.dual_emac) {
2845                 ret = cpsw_probe_dual_emac(priv);
2846                 if (ret) {
2847                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2848                         goto clean_unregister_netdev_ret;
2849                 }
2850         }
2851 
2852         pm_runtime_put(&pdev->dev);
2853 
2854         return 0;
2855 
2856 clean_unregister_netdev_ret:
2857         unregister_netdev(ndev);
2858 clean_ale_ret:
2859         cpsw_ale_destroy(cpsw->ale);
2860 clean_dma_ret:
2861         cpdma_ctlr_destroy(cpsw->dma);
2862 clean_dt_ret:
2863         cpsw_remove_dt(pdev);
2864         pm_runtime_put_sync(&pdev->dev);
2865 clean_runtime_disable_ret:
2866         pm_runtime_disable(&pdev->dev);
2867 clean_ndev_ret:
2868         free_netdev(priv->ndev);
2869         return ret;
2870 }
2871 
2872 static int cpsw_remove(struct platform_device *pdev)
2873 {
2874         struct net_device *ndev = platform_get_drvdata(pdev);
2875         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2876         int ret;
2877 
2878         ret = pm_runtime_get_sync(&pdev->dev);
2879         if (ret < 0) {
2880                 pm_runtime_put_noidle(&pdev->dev);
2881                 return ret;
2882         }
2883 
2884         if (cpsw->data.dual_emac)
2885                 unregister_netdev(cpsw->slaves[1].ndev);
2886         unregister_netdev(ndev);
2887 
2888         cpsw_ale_destroy(cpsw->ale);
2889         cpdma_ctlr_destroy(cpsw->dma);
2890         cpsw_remove_dt(pdev);
2891         pm_runtime_put_sync(&pdev->dev);
2892         pm_runtime_disable(&pdev->dev);
2893         if (cpsw->data.dual_emac)
2894                 free_netdev(cpsw->slaves[1].ndev);
2895         free_netdev(ndev);
2896         return 0;
2897 }
2898 
2899 #ifdef CONFIG_PM_SLEEP
2900 static int cpsw_suspend(struct device *dev)
2901 {
2902         struct platform_device  *pdev = to_platform_device(dev);
2903         struct net_device       *ndev = platform_get_drvdata(pdev);
2904         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
2905 
2906         if (cpsw->data.dual_emac) {
2907                 int i;
2908 
2909                 for (i = 0; i < cpsw->data.slaves; i++) {
2910                         if (netif_running(cpsw->slaves[i].ndev))
2911                                 cpsw_ndo_stop(cpsw->slaves[i].ndev);
2912                 }
2913         } else {
2914                 if (netif_running(ndev))
2915                         cpsw_ndo_stop(ndev);
2916         }
2917 
2918         /* Select sleep pin state */
2919         pinctrl_pm_select_sleep_state(dev);
2920 
2921         return 0;
2922 }
2923 
2924 static int cpsw_resume(struct device *dev)
2925 {
2926         struct platform_device  *pdev = to_platform_device(dev);
2927         struct net_device       *ndev = platform_get_drvdata(pdev);
2928         struct cpsw_common      *cpsw = netdev_priv(ndev);
2929 
2930         /* Select default pin state */
2931         pinctrl_pm_select_default_state(dev);
2932 
2933         /* shut up ASSERT_RTNL() warning in netif_set_real_num_tx/rx_queues */
2934         rtnl_lock();
2935         if (cpsw->data.dual_emac) {
2936                 int i;
2937 
2938                 for (i = 0; i < cpsw->data.slaves; i++) {
2939                         if (netif_running(cpsw->slaves[i].ndev))
2940                                 cpsw_ndo_open(cpsw->slaves[i].ndev);
2941                 }
2942         } else {
2943                 if (netif_running(ndev))
2944                         cpsw_ndo_open(ndev);
2945         }
2946         rtnl_unlock();
2947 
2948         return 0;
2949 }
2950 #endif
2951 
2952 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
2953 
2954 static struct platform_driver cpsw_driver = {
2955         .driver = {
2956                 .name    = "cpsw",
2957                 .pm      = &cpsw_pm_ops,
2958                 .of_match_table = cpsw_of_mtable,
2959         },
2960         .probe = cpsw_probe,
2961         .remove = cpsw_remove,
2962 };
2963 
2964 module_platform_driver(cpsw_driver);
2965 
2966 MODULE_LICENSE("GPL");
2967 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2968 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2969 MODULE_DESCRIPTION("TI CPSW Ethernet driver");
2970 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us