Version:  2.0.40 2.2.26 2.4.37 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8

Linux/drivers/net/ethernet/ti/cpmac.c

  1 /*
  2  * Copyright (C) 2006, 2007 Eugene Konev
  3  *
  4  * This program is free software; you can redistribute it and/or modify
  5  * it under the terms of the GNU General Public License as published by
  6  * the Free Software Foundation; either version 2 of the License, or
  7  * (at your option) any later version.
  8  *
  9  * This program is distributed in the hope that it will be useful,
 10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 12  * GNU General Public License for more details.
 13  *
 14  * You should have received a copy of the GNU General Public License
 15  * along with this program; if not, write to the Free Software
 16  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 17  */
 18 
 19 #include <linux/module.h>
 20 #include <linux/interrupt.h>
 21 #include <linux/moduleparam.h>
 22 
 23 #include <linux/sched.h>
 24 #include <linux/kernel.h>
 25 #include <linux/slab.h>
 26 #include <linux/errno.h>
 27 #include <linux/types.h>
 28 #include <linux/delay.h>
 29 
 30 #include <linux/netdevice.h>
 31 #include <linux/if_vlan.h>
 32 #include <linux/etherdevice.h>
 33 #include <linux/ethtool.h>
 34 #include <linux/skbuff.h>
 35 #include <linux/mii.h>
 36 #include <linux/phy.h>
 37 #include <linux/phy_fixed.h>
 38 #include <linux/platform_device.h>
 39 #include <linux/dma-mapping.h>
 40 #include <linux/clk.h>
 41 #include <linux/gpio.h>
 42 #include <linux/atomic.h>
 43 
 44 #include <asm/mach-ar7/ar7.h>
 45 
 46 MODULE_AUTHOR("Eugene Konev <ejka@imfi.kspu.ru>");
 47 MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
 48 MODULE_LICENSE("GPL");
 49 MODULE_ALIAS("platform:cpmac");
 50 
 51 static int debug_level = 8;
 52 static int dumb_switch;
 53 
 54 /* Next 2 are only used in cpmac_probe, so it's pointless to change them */
 55 module_param(debug_level, int, 0444);
 56 module_param(dumb_switch, int, 0444);
 57 
 58 MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable");
 59 MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus");
 60 
 61 #define CPMAC_VERSION "0.5.2"
 62 /* frame size + 802.1q tag + FCS size */
 63 #define CPMAC_SKB_SIZE          (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
 64 #define CPMAC_QUEUES    8
 65 
 66 /* Ethernet registers */
 67 #define CPMAC_TX_CONTROL                0x0004
 68 #define CPMAC_TX_TEARDOWN               0x0008
 69 #define CPMAC_RX_CONTROL                0x0014
 70 #define CPMAC_RX_TEARDOWN               0x0018
 71 #define CPMAC_MBP                       0x0100
 72 #define MBP_RXPASSCRC                   0x40000000
 73 #define MBP_RXQOS                       0x20000000
 74 #define MBP_RXNOCHAIN                   0x10000000
 75 #define MBP_RXCMF                       0x01000000
 76 #define MBP_RXSHORT                     0x00800000
 77 #define MBP_RXCEF                       0x00400000
 78 #define MBP_RXPROMISC                   0x00200000
 79 #define MBP_PROMISCCHAN(channel)        (((channel) & 0x7) << 16)
 80 #define MBP_RXBCAST                     0x00002000
 81 #define MBP_BCASTCHAN(channel)          (((channel) & 0x7) << 8)
 82 #define MBP_RXMCAST                     0x00000020
 83 #define MBP_MCASTCHAN(channel)          ((channel) & 0x7)
 84 #define CPMAC_UNICAST_ENABLE            0x0104
 85 #define CPMAC_UNICAST_CLEAR             0x0108
 86 #define CPMAC_MAX_LENGTH                0x010c
 87 #define CPMAC_BUFFER_OFFSET             0x0110
 88 #define CPMAC_MAC_CONTROL               0x0160
 89 #define MAC_TXPTYPE                     0x00000200
 90 #define MAC_TXPACE                      0x00000040
 91 #define MAC_MII                         0x00000020
 92 #define MAC_TXFLOW                      0x00000010
 93 #define MAC_RXFLOW                      0x00000008
 94 #define MAC_MTEST                       0x00000004
 95 #define MAC_LOOPBACK                    0x00000002
 96 #define MAC_FDX                         0x00000001
 97 #define CPMAC_MAC_STATUS                0x0164
 98 #define MAC_STATUS_QOS                  0x00000004
 99 #define MAC_STATUS_RXFLOW               0x00000002
100 #define MAC_STATUS_TXFLOW               0x00000001
101 #define CPMAC_TX_INT_ENABLE             0x0178
102 #define CPMAC_TX_INT_CLEAR              0x017c
103 #define CPMAC_MAC_INT_VECTOR            0x0180
104 #define MAC_INT_STATUS                  0x00080000
105 #define MAC_INT_HOST                    0x00040000
106 #define MAC_INT_RX                      0x00020000
107 #define MAC_INT_TX                      0x00010000
108 #define CPMAC_MAC_EOI_VECTOR            0x0184
109 #define CPMAC_RX_INT_ENABLE             0x0198
110 #define CPMAC_RX_INT_CLEAR              0x019c
111 #define CPMAC_MAC_INT_ENABLE            0x01a8
112 #define CPMAC_MAC_INT_CLEAR             0x01ac
113 #define CPMAC_MAC_ADDR_LO(channel)      (0x01b0 + (channel) * 4)
114 #define CPMAC_MAC_ADDR_MID              0x01d0
115 #define CPMAC_MAC_ADDR_HI               0x01d4
116 #define CPMAC_MAC_HASH_LO               0x01d8
117 #define CPMAC_MAC_HASH_HI               0x01dc
118 #define CPMAC_TX_PTR(channel)           (0x0600 + (channel) * 4)
119 #define CPMAC_RX_PTR(channel)           (0x0620 + (channel) * 4)
120 #define CPMAC_TX_ACK(channel)           (0x0640 + (channel) * 4)
121 #define CPMAC_RX_ACK(channel)           (0x0660 + (channel) * 4)
122 #define CPMAC_REG_END                   0x0680
123 
124 /* Rx/Tx statistics
125  * TODO: use some of them to fill stats in cpmac_stats()
126  */
127 #define CPMAC_STATS_RX_GOOD             0x0200
128 #define CPMAC_STATS_RX_BCAST            0x0204
129 #define CPMAC_STATS_RX_MCAST            0x0208
130 #define CPMAC_STATS_RX_PAUSE            0x020c
131 #define CPMAC_STATS_RX_CRC              0x0210
132 #define CPMAC_STATS_RX_ALIGN            0x0214
133 #define CPMAC_STATS_RX_OVER             0x0218
134 #define CPMAC_STATS_RX_JABBER           0x021c
135 #define CPMAC_STATS_RX_UNDER            0x0220
136 #define CPMAC_STATS_RX_FRAG             0x0224
137 #define CPMAC_STATS_RX_FILTER           0x0228
138 #define CPMAC_STATS_RX_QOSFILTER        0x022c
139 #define CPMAC_STATS_RX_OCTETS           0x0230
140 
141 #define CPMAC_STATS_TX_GOOD             0x0234
142 #define CPMAC_STATS_TX_BCAST            0x0238
143 #define CPMAC_STATS_TX_MCAST            0x023c
144 #define CPMAC_STATS_TX_PAUSE            0x0240
145 #define CPMAC_STATS_TX_DEFER            0x0244
146 #define CPMAC_STATS_TX_COLLISION        0x0248
147 #define CPMAC_STATS_TX_SINGLECOLL       0x024c
148 #define CPMAC_STATS_TX_MULTICOLL        0x0250
149 #define CPMAC_STATS_TX_EXCESSCOLL       0x0254
150 #define CPMAC_STATS_TX_LATECOLL         0x0258
151 #define CPMAC_STATS_TX_UNDERRUN         0x025c
152 #define CPMAC_STATS_TX_CARRIERSENSE     0x0260
153 #define CPMAC_STATS_TX_OCTETS           0x0264
154 
155 #define cpmac_read(base, reg)           (readl((void __iomem *)(base) + (reg)))
156 #define cpmac_write(base, reg, val)     (writel(val, (void __iomem *)(base) + \
157                                                 (reg)))
158 
159 /* MDIO bus */
160 #define CPMAC_MDIO_VERSION              0x0000
161 #define CPMAC_MDIO_CONTROL              0x0004
162 #define MDIOC_IDLE                      0x80000000
163 #define MDIOC_ENABLE                    0x40000000
164 #define MDIOC_PREAMBLE                  0x00100000
165 #define MDIOC_FAULT                     0x00080000
166 #define MDIOC_FAULTDETECT               0x00040000
167 #define MDIOC_INTTEST                   0x00020000
168 #define MDIOC_CLKDIV(div)               ((div) & 0xff)
169 #define CPMAC_MDIO_ALIVE                0x0008
170 #define CPMAC_MDIO_LINK                 0x000c
171 #define CPMAC_MDIO_ACCESS(channel)      (0x0080 + (channel) * 8)
172 #define MDIO_BUSY                       0x80000000
173 #define MDIO_WRITE                      0x40000000
174 #define MDIO_REG(reg)                   (((reg) & 0x1f) << 21)
175 #define MDIO_PHY(phy)                   (((phy) & 0x1f) << 16)
176 #define MDIO_DATA(data)                 ((data) & 0xffff)
177 #define CPMAC_MDIO_PHYSEL(channel)      (0x0084 + (channel) * 8)
178 #define PHYSEL_LINKSEL                  0x00000040
179 #define PHYSEL_LINKINT                  0x00000020
180 
181 struct cpmac_desc {
182         u32 hw_next;
183         u32 hw_data;
184         u16 buflen;
185         u16 bufflags;
186         u16 datalen;
187         u16 dataflags;
188 #define CPMAC_SOP                       0x8000
189 #define CPMAC_EOP                       0x4000
190 #define CPMAC_OWN                       0x2000
191 #define CPMAC_EOQ                       0x1000
192         struct sk_buff *skb;
193         struct cpmac_desc *next;
194         struct cpmac_desc *prev;
195         dma_addr_t mapping;
196         dma_addr_t data_mapping;
197 };
198 
199 struct cpmac_priv {
200         spinlock_t lock;
201         spinlock_t rx_lock;
202         struct cpmac_desc *rx_head;
203         int ring_size;
204         struct cpmac_desc *desc_ring;
205         dma_addr_t dma_ring;
206         void __iomem *regs;
207         struct mii_bus *mii_bus;
208         char phy_name[MII_BUS_ID_SIZE + 3];
209         int oldlink, oldspeed, oldduplex;
210         u32 msg_enable;
211         struct net_device *dev;
212         struct work_struct reset_work;
213         struct platform_device *pdev;
214         struct napi_struct napi;
215         atomic_t reset_pending;
216 };
217 
218 static irqreturn_t cpmac_irq(int, void *);
219 static void cpmac_hw_start(struct net_device *dev);
220 static void cpmac_hw_stop(struct net_device *dev);
221 static int cpmac_stop(struct net_device *dev);
222 static int cpmac_open(struct net_device *dev);
223 
224 static void cpmac_dump_regs(struct net_device *dev)
225 {
226         int i;
227         struct cpmac_priv *priv = netdev_priv(dev);
228 
229         for (i = 0; i < CPMAC_REG_END; i += 4) {
230                 if (i % 16 == 0) {
231                         if (i)
232                                 printk("\n");
233                         printk("%s: reg[%p]:", dev->name, priv->regs + i);
234                 }
235                 printk(" %08x", cpmac_read(priv->regs, i));
236         }
237         printk("\n");
238 }
239 
240 static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc)
241 {
242         int i;
243 
244         printk("%s: desc[%p]:", dev->name, desc);
245         for (i = 0; i < sizeof(*desc) / 4; i++)
246                 printk(" %08x", ((u32 *)desc)[i]);
247         printk("\n");
248 }
249 
250 static void cpmac_dump_all_desc(struct net_device *dev)
251 {
252         struct cpmac_priv *priv = netdev_priv(dev);
253         struct cpmac_desc *dump = priv->rx_head;
254 
255         do {
256                 cpmac_dump_desc(dev, dump);
257                 dump = dump->next;
258         } while (dump != priv->rx_head);
259 }
260 
261 static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb)
262 {
263         int i;
264 
265         printk("%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len);
266         for (i = 0; i < skb->len; i++) {
267                 if (i % 16 == 0) {
268                         if (i)
269                                 printk("\n");
270                         printk("%s: data[%p]:", dev->name, skb->data + i);
271                 }
272                 printk(" %02x", ((u8 *)skb->data)[i]);
273         }
274         printk("\n");
275 }
276 
277 static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
278 {
279         u32 val;
280 
281         while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
282                 cpu_relax();
283         cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |
284                     MDIO_PHY(phy_id));
285         while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY)
286                 cpu_relax();
287 
288         return MDIO_DATA(val);
289 }
290 
291 static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
292                             int reg, u16 val)
293 {
294         while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
295                 cpu_relax();
296         cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
297                     MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val));
298 
299         return 0;
300 }
301 
302 static int cpmac_mdio_reset(struct mii_bus *bus)
303 {
304         struct clk *cpmac_clk;
305 
306         cpmac_clk = clk_get(&bus->dev, "cpmac");
307         if (IS_ERR(cpmac_clk)) {
308                 pr_err("unable to get cpmac clock\n");
309                 return -1;
310         }
311         ar7_device_reset(AR7_RESET_BIT_MDIO);
312         cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
313                     MDIOC_CLKDIV(clk_get_rate(cpmac_clk) / 2200000 - 1));
314 
315         return 0;
316 }
317 
318 static struct mii_bus *cpmac_mii;
319 
320 static void cpmac_set_multicast_list(struct net_device *dev)
321 {
322         struct netdev_hw_addr *ha;
323         u8 tmp;
324         u32 mbp, bit, hash[2] = { 0, };
325         struct cpmac_priv *priv = netdev_priv(dev);
326 
327         mbp = cpmac_read(priv->regs, CPMAC_MBP);
328         if (dev->flags & IFF_PROMISC) {
329                 cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) |
330                             MBP_RXPROMISC);
331         } else {
332                 cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC);
333                 if (dev->flags & IFF_ALLMULTI) {
334                         /* enable all multicast mode */
335                         cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff);
336                         cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff);
337                 } else {
338                         /* cpmac uses some strange mac address hashing
339                          * (not crc32)
340                          */
341                         netdev_for_each_mc_addr(ha, dev) {
342                                 bit = 0;
343                                 tmp = ha->addr[0];
344                                 bit  ^= (tmp >> 2) ^ (tmp << 4);
345                                 tmp = ha->addr[1];
346                                 bit  ^= (tmp >> 4) ^ (tmp << 2);
347                                 tmp = ha->addr[2];
348                                 bit  ^= (tmp >> 6) ^ tmp;
349                                 tmp = ha->addr[3];
350                                 bit  ^= (tmp >> 2) ^ (tmp << 4);
351                                 tmp = ha->addr[4];
352                                 bit  ^= (tmp >> 4) ^ (tmp << 2);
353                                 tmp = ha->addr[5];
354                                 bit  ^= (tmp >> 6) ^ tmp;
355                                 bit &= 0x3f;
356                                 hash[bit / 32] |= 1 << (bit % 32);
357                         }
358 
359                         cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]);
360                         cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]);
361                 }
362         }
363 }
364 
365 static struct sk_buff *cpmac_rx_one(struct cpmac_priv *priv,
366                                     struct cpmac_desc *desc)
367 {
368         struct sk_buff *skb, *result = NULL;
369 
370         if (unlikely(netif_msg_hw(priv)))
371                 cpmac_dump_desc(priv->dev, desc);
372         cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping);
373         if (unlikely(!desc->datalen)) {
374                 if (netif_msg_rx_err(priv) && net_ratelimit())
375                         netdev_warn(priv->dev, "rx: spurious interrupt\n");
376 
377                 return NULL;
378         }
379 
380         skb = netdev_alloc_skb_ip_align(priv->dev, CPMAC_SKB_SIZE);
381         if (likely(skb)) {
382                 skb_put(desc->skb, desc->datalen);
383                 desc->skb->protocol = eth_type_trans(desc->skb, priv->dev);
384                 skb_checksum_none_assert(desc->skb);
385                 priv->dev->stats.rx_packets++;
386                 priv->dev->stats.rx_bytes += desc->datalen;
387                 result = desc->skb;
388                 dma_unmap_single(&priv->dev->dev, desc->data_mapping,
389                                  CPMAC_SKB_SIZE, DMA_FROM_DEVICE);
390                 desc->skb = skb;
391                 desc->data_mapping = dma_map_single(&priv->dev->dev, skb->data,
392                                                     CPMAC_SKB_SIZE,
393                                                     DMA_FROM_DEVICE);
394                 desc->hw_data = (u32)desc->data_mapping;
395                 if (unlikely(netif_msg_pktdata(priv))) {
396                         netdev_dbg(priv->dev, "received packet:\n");
397                         cpmac_dump_skb(priv->dev, result);
398                 }
399         } else {
400                 if (netif_msg_rx_err(priv) && net_ratelimit())
401                         netdev_warn(priv->dev,
402                                     "low on skbs, dropping packet\n");
403 
404                 priv->dev->stats.rx_dropped++;
405         }
406 
407         desc->buflen = CPMAC_SKB_SIZE;
408         desc->dataflags = CPMAC_OWN;
409 
410         return result;
411 }
412 
413 static int cpmac_poll(struct napi_struct *napi, int budget)
414 {
415         struct sk_buff *skb;
416         struct cpmac_desc *desc, *restart;
417         struct cpmac_priv *priv = container_of(napi, struct cpmac_priv, napi);
418         int received = 0, processed = 0;
419 
420         spin_lock(&priv->rx_lock);
421         if (unlikely(!priv->rx_head)) {
422                 if (netif_msg_rx_err(priv) && net_ratelimit())
423                         netdev_warn(priv->dev, "rx: polling, but no queue\n");
424 
425                 spin_unlock(&priv->rx_lock);
426                 napi_complete(napi);
427                 return 0;
428         }
429 
430         desc = priv->rx_head;
431         restart = NULL;
432         while (((desc->dataflags & CPMAC_OWN) == 0) && (received < budget)) {
433                 processed++;
434 
435                 if ((desc->dataflags & CPMAC_EOQ) != 0) {
436                         /* The last update to eoq->hw_next didn't happen
437                          * soon enough, and the receiver stopped here.
438                          * Remember this descriptor so we can restart
439                          * the receiver after freeing some space.
440                          */
441                         if (unlikely(restart)) {
442                                 if (netif_msg_rx_err(priv))
443                                         netdev_err(priv->dev, "poll found a"
444                                                    " duplicate EOQ: %p and %p\n",
445                                                    restart, desc);
446                                 goto fatal_error;
447                         }
448 
449                         restart = desc->next;
450                 }
451 
452                 skb = cpmac_rx_one(priv, desc);
453                 if (likely(skb)) {
454                         netif_receive_skb(skb);
455                         received++;
456                 }
457                 desc = desc->next;
458         }
459 
460         if (desc != priv->rx_head) {
461                 /* We freed some buffers, but not the whole ring,
462                  * add what we did free to the rx list
463                  */
464                 desc->prev->hw_next = (u32)0;
465                 priv->rx_head->prev->hw_next = priv->rx_head->mapping;
466         }
467 
468         /* Optimization: If we did not actually process an EOQ (perhaps because
469          * of quota limits), check to see if the tail of the queue has EOQ set.
470          * We should immediately restart in that case so that the receiver can
471          * restart and run in parallel with more packet processing.
472          * This lets us handle slightly larger bursts before running
473          * out of ring space (assuming dev->weight < ring_size)
474          */
475 
476         if (!restart &&
477              (priv->rx_head->prev->dataflags & (CPMAC_OWN|CPMAC_EOQ))
478                     == CPMAC_EOQ &&
479              (priv->rx_head->dataflags & CPMAC_OWN) != 0) {
480                 /* reset EOQ so the poll loop (above) doesn't try to
481                  * restart this when it eventually gets to this descriptor.
482                  */
483                 priv->rx_head->prev->dataflags &= ~CPMAC_EOQ;
484                 restart = priv->rx_head;
485         }
486 
487         if (restart) {
488                 priv->dev->stats.rx_errors++;
489                 priv->dev->stats.rx_fifo_errors++;
490                 if (netif_msg_rx_err(priv) && net_ratelimit())
491                         netdev_warn(priv->dev, "rx dma ring overrun\n");
492 
493                 if (unlikely((restart->dataflags & CPMAC_OWN) == 0)) {
494                         if (netif_msg_drv(priv))
495                                 netdev_err(priv->dev, "cpmac_poll is trying "
496                                         "to restart rx from a descriptor "
497                                         "that's not free: %p\n", restart);
498                         goto fatal_error;
499                 }
500 
501                 cpmac_write(priv->regs, CPMAC_RX_PTR(0), restart->mapping);
502         }
503 
504         priv->rx_head = desc;
505         spin_unlock(&priv->rx_lock);
506         if (unlikely(netif_msg_rx_status(priv)))
507                 netdev_dbg(priv->dev, "poll processed %d packets\n", received);
508 
509         if (processed == 0) {
510                 /* we ran out of packets to read,
511                  * revert to interrupt-driven mode
512                  */
513                 napi_complete(napi);
514                 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
515                 return 0;
516         }
517 
518         return 1;
519 
520 fatal_error:
521         /* Something went horribly wrong.
522          * Reset hardware to try to recover rather than wedging.
523          */
524         if (netif_msg_drv(priv)) {
525                 netdev_err(priv->dev, "cpmac_poll is confused. "
526                            "Resetting hardware\n");
527                 cpmac_dump_all_desc(priv->dev);
528                 netdev_dbg(priv->dev, "RX_PTR(0)=0x%08x RX_ACK(0)=0x%08x\n",
529                            cpmac_read(priv->regs, CPMAC_RX_PTR(0)),
530                            cpmac_read(priv->regs, CPMAC_RX_ACK(0)));
531         }
532 
533         spin_unlock(&priv->rx_lock);
534         napi_complete(napi);
535         netif_tx_stop_all_queues(priv->dev);
536         napi_disable(&priv->napi);
537 
538         atomic_inc(&priv->reset_pending);
539         cpmac_hw_stop(priv->dev);
540         if (!schedule_work(&priv->reset_work))
541                 atomic_dec(&priv->reset_pending);
542 
543         return 0;
544 
545 }
546 
547 static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
548 {
549         int queue, len;
550         struct cpmac_desc *desc;
551         struct cpmac_priv *priv = netdev_priv(dev);
552 
553         if (unlikely(atomic_read(&priv->reset_pending)))
554                 return NETDEV_TX_BUSY;
555 
556         if (unlikely(skb_padto(skb, ETH_ZLEN)))
557                 return NETDEV_TX_OK;
558 
559         len = max(skb->len, ETH_ZLEN);
560         queue = skb_get_queue_mapping(skb);
561         netif_stop_subqueue(dev, queue);
562 
563         desc = &priv->desc_ring[queue];
564         if (unlikely(desc->dataflags & CPMAC_OWN)) {
565                 if (netif_msg_tx_err(priv) && net_ratelimit())
566                         netdev_warn(dev, "tx dma ring full\n");
567 
568                 return NETDEV_TX_BUSY;
569         }
570 
571         spin_lock(&priv->lock);
572         spin_unlock(&priv->lock);
573         desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN;
574         desc->skb = skb;
575         desc->data_mapping = dma_map_single(&dev->dev, skb->data, len,
576                                             DMA_TO_DEVICE);
577         desc->hw_data = (u32)desc->data_mapping;
578         desc->datalen = len;
579         desc->buflen = len;
580         if (unlikely(netif_msg_tx_queued(priv)))
581                 netdev_dbg(dev, "sending 0x%p, len=%d\n", skb, skb->len);
582         if (unlikely(netif_msg_hw(priv)))
583                 cpmac_dump_desc(dev, desc);
584         if (unlikely(netif_msg_pktdata(priv)))
585                 cpmac_dump_skb(dev, skb);
586         cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping);
587 
588         return NETDEV_TX_OK;
589 }
590 
591 static void cpmac_end_xmit(struct net_device *dev, int queue)
592 {
593         struct cpmac_desc *desc;
594         struct cpmac_priv *priv = netdev_priv(dev);
595 
596         desc = &priv->desc_ring[queue];
597         cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping);
598         if (likely(desc->skb)) {
599                 spin_lock(&priv->lock);
600                 dev->stats.tx_packets++;
601                 dev->stats.tx_bytes += desc->skb->len;
602                 spin_unlock(&priv->lock);
603                 dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len,
604                                  DMA_TO_DEVICE);
605 
606                 if (unlikely(netif_msg_tx_done(priv)))
607                         netdev_dbg(dev, "sent 0x%p, len=%d\n",
608                                    desc->skb, desc->skb->len);
609 
610                 dev_kfree_skb_irq(desc->skb);
611                 desc->skb = NULL;
612                 if (__netif_subqueue_stopped(dev, queue))
613                         netif_wake_subqueue(dev, queue);
614         } else {
615                 if (netif_msg_tx_err(priv) && net_ratelimit())
616                         netdev_warn(dev, "end_xmit: spurious interrupt\n");
617                 if (__netif_subqueue_stopped(dev, queue))
618                         netif_wake_subqueue(dev, queue);
619         }
620 }
621 
622 static void cpmac_hw_stop(struct net_device *dev)
623 {
624         int i;
625         struct cpmac_priv *priv = netdev_priv(dev);
626         struct plat_cpmac_data *pdata = dev_get_platdata(&priv->pdev->dev);
627 
628         ar7_device_reset(pdata->reset_bit);
629         cpmac_write(priv->regs, CPMAC_RX_CONTROL,
630                     cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1);
631         cpmac_write(priv->regs, CPMAC_TX_CONTROL,
632                     cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1);
633         for (i = 0; i < 8; i++) {
634                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
635                 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
636         }
637         cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
638         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
639         cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
640         cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
641         cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
642                     cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII);
643 }
644 
645 static void cpmac_hw_start(struct net_device *dev)
646 {
647         int i;
648         struct cpmac_priv *priv = netdev_priv(dev);
649         struct plat_cpmac_data *pdata = dev_get_platdata(&priv->pdev->dev);
650 
651         ar7_device_reset(pdata->reset_bit);
652         for (i = 0; i < 8; i++) {
653                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
654                 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
655         }
656         cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);
657 
658         cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
659                     MBP_RXMCAST);
660         cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);
661         for (i = 0; i < 8; i++)
662                 cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
663         cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
664         cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |
665                     (dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) |
666                     (dev->dev_addr[3] << 24));
667         cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
668         cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
669         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
670         cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
671         cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
672         cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);
673         cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
674         cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);
675         cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
676 
677         cpmac_write(priv->regs, CPMAC_RX_CONTROL,
678                     cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1);
679         cpmac_write(priv->regs, CPMAC_TX_CONTROL,
680                     cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1);
681         cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
682                     cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII |
683                     MAC_FDX);
684 }
685 
686 static void cpmac_clear_rx(struct net_device *dev)
687 {
688         struct cpmac_priv *priv = netdev_priv(dev);
689         struct cpmac_desc *desc;
690         int i;
691 
692         if (unlikely(!priv->rx_head))
693                 return;
694         desc = priv->rx_head;
695         for (i = 0; i < priv->ring_size; i++) {
696                 if ((desc->dataflags & CPMAC_OWN) == 0) {
697                         if (netif_msg_rx_err(priv) && net_ratelimit())
698                                 netdev_warn(dev, "packet dropped\n");
699                         if (unlikely(netif_msg_hw(priv)))
700                                 cpmac_dump_desc(dev, desc);
701                         desc->dataflags = CPMAC_OWN;
702                         dev->stats.rx_dropped++;
703                 }
704                 desc->hw_next = desc->next->mapping;
705                 desc = desc->next;
706         }
707         priv->rx_head->prev->hw_next = 0;
708 }
709 
710 static void cpmac_clear_tx(struct net_device *dev)
711 {
712         struct cpmac_priv *priv = netdev_priv(dev);
713         int i;
714 
715         if (unlikely(!priv->desc_ring))
716                 return;
717         for (i = 0; i < CPMAC_QUEUES; i++) {
718                 priv->desc_ring[i].dataflags = 0;
719                 if (priv->desc_ring[i].skb) {
720                         dev_kfree_skb_any(priv->desc_ring[i].skb);
721                         priv->desc_ring[i].skb = NULL;
722                 }
723         }
724 }
725 
726 static void cpmac_hw_error(struct work_struct *work)
727 {
728         struct cpmac_priv *priv =
729                 container_of(work, struct cpmac_priv, reset_work);
730 
731         spin_lock(&priv->rx_lock);
732         cpmac_clear_rx(priv->dev);
733         spin_unlock(&priv->rx_lock);
734         cpmac_clear_tx(priv->dev);
735         cpmac_hw_start(priv->dev);
736         barrier();
737         atomic_dec(&priv->reset_pending);
738 
739         netif_tx_wake_all_queues(priv->dev);
740         cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
741 }
742 
743 static void cpmac_check_status(struct net_device *dev)
744 {
745         struct cpmac_priv *priv = netdev_priv(dev);
746 
747         u32 macstatus = cpmac_read(priv->regs, CPMAC_MAC_STATUS);
748         int rx_channel = (macstatus >> 8) & 7;
749         int rx_code = (macstatus >> 12) & 15;
750         int tx_channel = (macstatus >> 16) & 7;
751         int tx_code = (macstatus >> 20) & 15;
752 
753         if (rx_code || tx_code) {
754                 if (netif_msg_drv(priv) && net_ratelimit()) {
755                         /* Can't find any documentation on what these
756                          * error codes actually are. So just log them and hope..
757                          */
758                         if (rx_code)
759                                 netdev_warn(dev, "host error %d on rx "
760                                         "channel %d (macstatus %08x), resetting\n",
761                                         rx_code, rx_channel, macstatus);
762                         if (tx_code)
763                                 netdev_warn(dev, "host error %d on tx "
764                                         "channel %d (macstatus %08x), resetting\n",
765                                         tx_code, tx_channel, macstatus);
766                 }
767 
768                 netif_tx_stop_all_queues(dev);
769                 cpmac_hw_stop(dev);
770                 if (schedule_work(&priv->reset_work))
771                         atomic_inc(&priv->reset_pending);
772                 if (unlikely(netif_msg_hw(priv)))
773                         cpmac_dump_regs(dev);
774         }
775         cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
776 }
777 
778 static irqreturn_t cpmac_irq(int irq, void *dev_id)
779 {
780         struct net_device *dev = dev_id;
781         struct cpmac_priv *priv;
782         int queue;
783         u32 status;
784 
785         priv = netdev_priv(dev);
786 
787         status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR);
788 
789         if (unlikely(netif_msg_intr(priv)))
790                 netdev_dbg(dev, "interrupt status: 0x%08x\n", status);
791 
792         if (status & MAC_INT_TX)
793                 cpmac_end_xmit(dev, (status & 7));
794 
795         if (status & MAC_INT_RX) {
796                 queue = (status >> 8) & 7;
797                 if (napi_schedule_prep(&priv->napi)) {
798                         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue);
799                         __napi_schedule(&priv->napi);
800                 }
801         }
802 
803         cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0);
804 
805         if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS)))
806                 cpmac_check_status(dev);
807 
808         return IRQ_HANDLED;
809 }
810 
811 static void cpmac_tx_timeout(struct net_device *dev)
812 {
813         struct cpmac_priv *priv = netdev_priv(dev);
814 
815         spin_lock(&priv->lock);
816         dev->stats.tx_errors++;
817         spin_unlock(&priv->lock);
818         if (netif_msg_tx_err(priv) && net_ratelimit())
819                 netdev_warn(dev, "transmit timeout\n");
820 
821         atomic_inc(&priv->reset_pending);
822         barrier();
823         cpmac_clear_tx(dev);
824         barrier();
825         atomic_dec(&priv->reset_pending);
826 
827         netif_tx_wake_all_queues(priv->dev);
828 }
829 
830 static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
831 {
832         if (!(netif_running(dev)))
833                 return -EINVAL;
834         if (!dev->phydev)
835                 return -EINVAL;
836 
837         return phy_mii_ioctl(dev->phydev, ifr, cmd);
838 }
839 
840 static void cpmac_get_ringparam(struct net_device *dev,
841                                                 struct ethtool_ringparam *ring)
842 {
843         struct cpmac_priv *priv = netdev_priv(dev);
844 
845         ring->rx_max_pending = 1024;
846         ring->rx_mini_max_pending = 1;
847         ring->rx_jumbo_max_pending = 1;
848         ring->tx_max_pending = 1;
849 
850         ring->rx_pending = priv->ring_size;
851         ring->rx_mini_pending = 1;
852         ring->rx_jumbo_pending = 1;
853         ring->tx_pending = 1;
854 }
855 
856 static int cpmac_set_ringparam(struct net_device *dev,
857                                                 struct ethtool_ringparam *ring)
858 {
859         struct cpmac_priv *priv = netdev_priv(dev);
860 
861         if (netif_running(dev))
862                 return -EBUSY;
863         priv->ring_size = ring->rx_pending;
864 
865         return 0;
866 }
867 
868 static void cpmac_get_drvinfo(struct net_device *dev,
869                               struct ethtool_drvinfo *info)
870 {
871         strlcpy(info->driver, "cpmac", sizeof(info->driver));
872         strlcpy(info->version, CPMAC_VERSION, sizeof(info->version));
873         snprintf(info->bus_info, sizeof(info->bus_info), "%s", "cpmac");
874 }
875 
876 static const struct ethtool_ops cpmac_ethtool_ops = {
877         .get_drvinfo = cpmac_get_drvinfo,
878         .get_link = ethtool_op_get_link,
879         .get_ringparam = cpmac_get_ringparam,
880         .set_ringparam = cpmac_set_ringparam,
881         .get_link_ksettings = phy_ethtool_get_link_ksettings,
882         .set_link_ksettings = phy_ethtool_set_link_ksettings,
883 };
884 
885 static void cpmac_adjust_link(struct net_device *dev)
886 {
887         struct cpmac_priv *priv = netdev_priv(dev);
888         int new_state = 0;
889 
890         spin_lock(&priv->lock);
891         if (dev->phydev->link) {
892                 netif_tx_start_all_queues(dev);
893                 if (dev->phydev->duplex != priv->oldduplex) {
894                         new_state = 1;
895                         priv->oldduplex = dev->phydev->duplex;
896                 }
897 
898                 if (dev->phydev->speed != priv->oldspeed) {
899                         new_state = 1;
900                         priv->oldspeed = dev->phydev->speed;
901                 }
902 
903                 if (!priv->oldlink) {
904                         new_state = 1;
905                         priv->oldlink = 1;
906                 }
907         } else if (priv->oldlink) {
908                 new_state = 1;
909                 priv->oldlink = 0;
910                 priv->oldspeed = 0;
911                 priv->oldduplex = -1;
912         }
913 
914         if (new_state && netif_msg_link(priv) && net_ratelimit())
915                 phy_print_status(dev->phydev);
916 
917         spin_unlock(&priv->lock);
918 }
919 
920 static int cpmac_open(struct net_device *dev)
921 {
922         int i, size, res;
923         struct cpmac_priv *priv = netdev_priv(dev);
924         struct resource *mem;
925         struct cpmac_desc *desc;
926         struct sk_buff *skb;
927 
928         mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
929         if (!request_mem_region(mem->start, resource_size(mem), dev->name)) {
930                 if (netif_msg_drv(priv))
931                         netdev_err(dev, "failed to request registers\n");
932 
933                 res = -ENXIO;
934                 goto fail_reserve;
935         }
936 
937         priv->regs = ioremap(mem->start, resource_size(mem));
938         if (!priv->regs) {
939                 if (netif_msg_drv(priv))
940                         netdev_err(dev, "failed to remap registers\n");
941 
942                 res = -ENXIO;
943                 goto fail_remap;
944         }
945 
946         size = priv->ring_size + CPMAC_QUEUES;
947         priv->desc_ring = dma_alloc_coherent(&dev->dev,
948                                              sizeof(struct cpmac_desc) * size,
949                                              &priv->dma_ring,
950                                              GFP_KERNEL);
951         if (!priv->desc_ring) {
952                 res = -ENOMEM;
953                 goto fail_alloc;
954         }
955 
956         for (i = 0; i < size; i++)
957                 priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i;
958 
959         priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
960         for (i = 0, desc = priv->rx_head; i < priv->ring_size; i++, desc++) {
961                 skb = netdev_alloc_skb_ip_align(dev, CPMAC_SKB_SIZE);
962                 if (unlikely(!skb)) {
963                         res = -ENOMEM;
964                         goto fail_desc;
965                 }
966                 desc->skb = skb;
967                 desc->data_mapping = dma_map_single(&dev->dev, skb->data,
968                                                     CPMAC_SKB_SIZE,
969                                                     DMA_FROM_DEVICE);
970                 desc->hw_data = (u32)desc->data_mapping;
971                 desc->buflen = CPMAC_SKB_SIZE;
972                 desc->dataflags = CPMAC_OWN;
973                 desc->next = &priv->rx_head[(i + 1) % priv->ring_size];
974                 desc->next->prev = desc;
975                 desc->hw_next = (u32)desc->next->mapping;
976         }
977 
978         priv->rx_head->prev->hw_next = (u32)0;
979 
980         res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED, dev->name, dev);
981         if (res) {
982                 if (netif_msg_drv(priv))
983                         netdev_err(dev, "failed to obtain irq\n");
984 
985                 goto fail_irq;
986         }
987 
988         atomic_set(&priv->reset_pending, 0);
989         INIT_WORK(&priv->reset_work, cpmac_hw_error);
990         cpmac_hw_start(dev);
991 
992         napi_enable(&priv->napi);
993         dev->phydev->state = PHY_CHANGELINK;
994         phy_start(dev->phydev);
995 
996         return 0;
997 
998 fail_irq:
999 fail_desc:
1000         for (i = 0; i < priv->ring_size; i++) {
1001                 if (priv->rx_head[i].skb) {
1002                         dma_unmap_single(&dev->dev,
1003                                          priv->rx_head[i].data_mapping,
1004                                          CPMAC_SKB_SIZE,
1005                                          DMA_FROM_DEVICE);
1006                         kfree_skb(priv->rx_head[i].skb);
1007                 }
1008         }
1009         dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) * size,
1010                           priv->desc_ring, priv->dma_ring);
1011 
1012 fail_alloc:
1013         iounmap(priv->regs);
1014 
1015 fail_remap:
1016         release_mem_region(mem->start, resource_size(mem));
1017 
1018 fail_reserve:
1019         return res;
1020 }
1021 
1022 static int cpmac_stop(struct net_device *dev)
1023 {
1024         int i;
1025         struct cpmac_priv *priv = netdev_priv(dev);
1026         struct resource *mem;
1027 
1028         netif_tx_stop_all_queues(dev);
1029 
1030         cancel_work_sync(&priv->reset_work);
1031         napi_disable(&priv->napi);
1032         phy_stop(dev->phydev);
1033 
1034         cpmac_hw_stop(dev);
1035 
1036         for (i = 0; i < 8; i++)
1037                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
1038         cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0);
1039         cpmac_write(priv->regs, CPMAC_MBP, 0);
1040 
1041         free_irq(dev->irq, dev);
1042         iounmap(priv->regs);
1043         mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
1044         release_mem_region(mem->start, resource_size(mem));
1045         priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
1046         for (i = 0; i < priv->ring_size; i++) {
1047                 if (priv->rx_head[i].skb) {
1048                         dma_unmap_single(&dev->dev,
1049                                          priv->rx_head[i].data_mapping,
1050                                          CPMAC_SKB_SIZE,
1051                                          DMA_FROM_DEVICE);
1052                         kfree_skb(priv->rx_head[i].skb);
1053                 }
1054         }
1055 
1056         dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) *
1057                           (CPMAC_QUEUES + priv->ring_size),
1058                           priv->desc_ring, priv->dma_ring);
1059 
1060         return 0;
1061 }
1062 
1063 static const struct net_device_ops cpmac_netdev_ops = {
1064         .ndo_open               = cpmac_open,
1065         .ndo_stop               = cpmac_stop,
1066         .ndo_start_xmit         = cpmac_start_xmit,
1067         .ndo_tx_timeout         = cpmac_tx_timeout,
1068         .ndo_set_rx_mode        = cpmac_set_multicast_list,
1069         .ndo_do_ioctl           = cpmac_ioctl,
1070         .ndo_change_mtu         = eth_change_mtu,
1071         .ndo_validate_addr      = eth_validate_addr,
1072         .ndo_set_mac_address    = eth_mac_addr,
1073 };
1074 
1075 static int external_switch;
1076 
1077 static int cpmac_probe(struct platform_device *pdev)
1078 {
1079         int rc, phy_id;
1080         char mdio_bus_id[MII_BUS_ID_SIZE];
1081         struct resource *mem;
1082         struct cpmac_priv *priv;
1083         struct net_device *dev;
1084         struct plat_cpmac_data *pdata;
1085         struct phy_device *phydev = NULL;
1086 
1087         pdata = dev_get_platdata(&pdev->dev);
1088 
1089         if (external_switch || dumb_switch) {
1090                 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); /* fixed phys bus */
1091                 phy_id = pdev->id;
1092         } else {
1093                 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1094                         if (!(pdata->phy_mask & (1 << phy_id)))
1095                                 continue;
1096                         if (!mdiobus_get_phy(cpmac_mii, phy_id))
1097                                 continue;
1098                         strncpy(mdio_bus_id, cpmac_mii->id, MII_BUS_ID_SIZE);
1099                         break;
1100                 }
1101         }
1102 
1103         if (phy_id == PHY_MAX_ADDR) {
1104                 dev_err(&pdev->dev, "no PHY present, falling back "
1105                         "to switch on MDIO bus 0\n");
1106                 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); /* fixed phys bus */
1107                 phy_id = pdev->id;
1108         }
1109         mdio_bus_id[sizeof(mdio_bus_id) - 1] = '\0';
1110 
1111         dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES);
1112         if (!dev)
1113                 return -ENOMEM;
1114 
1115         platform_set_drvdata(pdev, dev);
1116         priv = netdev_priv(dev);
1117 
1118         priv->pdev = pdev;
1119         mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1120         if (!mem) {
1121                 rc = -ENODEV;
1122                 goto fail;
1123         }
1124 
1125         dev->irq = platform_get_irq_byname(pdev, "irq");
1126 
1127         dev->netdev_ops = &cpmac_netdev_ops;
1128         dev->ethtool_ops = &cpmac_ethtool_ops;
1129 
1130         netif_napi_add(dev, &priv->napi, cpmac_poll, 64);
1131 
1132         spin_lock_init(&priv->lock);
1133         spin_lock_init(&priv->rx_lock);
1134         priv->dev = dev;
1135         priv->ring_size = 64;
1136         priv->msg_enable = netif_msg_init(debug_level, 0xff);
1137         memcpy(dev->dev_addr, pdata->dev_addr, sizeof(pdata->dev_addr));
1138 
1139         snprintf(priv->phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT,
1140                                                 mdio_bus_id, phy_id);
1141 
1142         phydev = phy_connect(dev, priv->phy_name, cpmac_adjust_link,
1143                              PHY_INTERFACE_MODE_MII);
1144 
1145         if (IS_ERR(phydev)) {
1146                 if (netif_msg_drv(priv))
1147                         dev_err(&pdev->dev, "Could not attach to PHY\n");
1148 
1149                 rc = PTR_ERR(phydev);
1150                 goto fail;
1151         }
1152 
1153         rc = register_netdev(dev);
1154         if (rc) {
1155                 dev_err(&pdev->dev, "Could not register net device\n");
1156                 goto fail;
1157         }
1158 
1159         if (netif_msg_probe(priv)) {
1160                 dev_info(&pdev->dev, "regs: %p, irq: %d, phy: %s, "
1161                          "mac: %pM\n", (void *)mem->start, dev->irq,
1162                          priv->phy_name, dev->dev_addr);
1163         }
1164 
1165         return 0;
1166 
1167 fail:
1168         free_netdev(dev);
1169         return rc;
1170 }
1171 
1172 static int cpmac_remove(struct platform_device *pdev)
1173 {
1174         struct net_device *dev = platform_get_drvdata(pdev);
1175 
1176         unregister_netdev(dev);
1177         free_netdev(dev);
1178 
1179         return 0;
1180 }
1181 
1182 static struct platform_driver cpmac_driver = {
1183         .driver = {
1184                 .name   = "cpmac",
1185         },
1186         .probe  = cpmac_probe,
1187         .remove = cpmac_remove,
1188 };
1189 
1190 int cpmac_init(void)
1191 {
1192         u32 mask;
1193         int i, res;
1194 
1195         cpmac_mii = mdiobus_alloc();
1196         if (cpmac_mii == NULL)
1197                 return -ENOMEM;
1198 
1199         cpmac_mii->name = "cpmac-mii";
1200         cpmac_mii->read = cpmac_mdio_read;
1201         cpmac_mii->write = cpmac_mdio_write;
1202         cpmac_mii->reset = cpmac_mdio_reset;
1203 
1204         cpmac_mii->priv = ioremap(AR7_REGS_MDIO, 256);
1205 
1206         if (!cpmac_mii->priv) {
1207                 pr_err("Can't ioremap mdio registers\n");
1208                 res = -ENXIO;
1209                 goto fail_alloc;
1210         }
1211 
1212 #warning FIXME: unhardcode gpio&reset bits
1213         ar7_gpio_disable(26);
1214         ar7_gpio_disable(27);
1215         ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);
1216         ar7_device_reset(AR7_RESET_BIT_CPMAC_HI);
1217         ar7_device_reset(AR7_RESET_BIT_EPHY);
1218 
1219         cpmac_mii->reset(cpmac_mii);
1220 
1221         for (i = 0; i < 300; i++) {
1222                 mask = cpmac_read(cpmac_mii->priv, CPMAC_MDIO_ALIVE);
1223                 if (mask)
1224                         break;
1225                 else
1226                         msleep(10);
1227         }
1228 
1229         mask &= 0x7fffffff;
1230         if (mask & (mask - 1)) {
1231                 external_switch = 1;
1232                 mask = 0;
1233         }
1234 
1235         cpmac_mii->phy_mask = ~(mask | 0x80000000);
1236         snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "cpmac-1");
1237 
1238         res = mdiobus_register(cpmac_mii);
1239         if (res)
1240                 goto fail_mii;
1241 
1242         res = platform_driver_register(&cpmac_driver);
1243         if (res)
1244                 goto fail_cpmac;
1245 
1246         return 0;
1247 
1248 fail_cpmac:
1249         mdiobus_unregister(cpmac_mii);
1250 
1251 fail_mii:
1252         iounmap(cpmac_mii->priv);
1253 
1254 fail_alloc:
1255         mdiobus_free(cpmac_mii);
1256 
1257         return res;
1258 }
1259 
1260 void cpmac_exit(void)
1261 {
1262         platform_driver_unregister(&cpmac_driver);
1263         mdiobus_unregister(cpmac_mii);
1264         iounmap(cpmac_mii->priv);
1265         mdiobus_free(cpmac_mii);
1266 }
1267 
1268 module_init(cpmac_init);
1269 module_exit(cpmac_exit);
1270 

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