Version:  2.0.40 2.2.26 2.4.37 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9

Linux/drivers/net/ethernet/ti/cpmac.c

  1 /*
  2  * Copyright (C) 2006, 2007 Eugene Konev
  3  *
  4  * This program is free software; you can redistribute it and/or modify
  5  * it under the terms of the GNU General Public License as published by
  6  * the Free Software Foundation; either version 2 of the License, or
  7  * (at your option) any later version.
  8  *
  9  * This program is distributed in the hope that it will be useful,
 10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 12  * GNU General Public License for more details.
 13  *
 14  * You should have received a copy of the GNU General Public License
 15  * along with this program; if not, write to the Free Software
 16  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 17  */
 18 
 19 #include <linux/module.h>
 20 #include <linux/interrupt.h>
 21 #include <linux/moduleparam.h>
 22 
 23 #include <linux/sched.h>
 24 #include <linux/kernel.h>
 25 #include <linux/slab.h>
 26 #include <linux/errno.h>
 27 #include <linux/types.h>
 28 #include <linux/delay.h>
 29 
 30 #include <linux/netdevice.h>
 31 #include <linux/if_vlan.h>
 32 #include <linux/etherdevice.h>
 33 #include <linux/ethtool.h>
 34 #include <linux/skbuff.h>
 35 #include <linux/mii.h>
 36 #include <linux/phy.h>
 37 #include <linux/phy_fixed.h>
 38 #include <linux/platform_device.h>
 39 #include <linux/dma-mapping.h>
 40 #include <linux/clk.h>
 41 #include <linux/gpio.h>
 42 #include <linux/atomic.h>
 43 
 44 #include <asm/mach-ar7/ar7.h>
 45 
 46 MODULE_AUTHOR("Eugene Konev <ejka@imfi.kspu.ru>");
 47 MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
 48 MODULE_LICENSE("GPL");
 49 MODULE_ALIAS("platform:cpmac");
 50 
 51 static int debug_level = 8;
 52 static int dumb_switch;
 53 
 54 /* Next 2 are only used in cpmac_probe, so it's pointless to change them */
 55 module_param(debug_level, int, 0444);
 56 module_param(dumb_switch, int, 0444);
 57 
 58 MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable");
 59 MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus");
 60 
 61 #define CPMAC_VERSION "0.5.2"
 62 /* frame size + 802.1q tag + FCS size */
 63 #define CPMAC_SKB_SIZE          (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
 64 #define CPMAC_QUEUES    8
 65 
 66 /* Ethernet registers */
 67 #define CPMAC_TX_CONTROL                0x0004
 68 #define CPMAC_TX_TEARDOWN               0x0008
 69 #define CPMAC_RX_CONTROL                0x0014
 70 #define CPMAC_RX_TEARDOWN               0x0018
 71 #define CPMAC_MBP                       0x0100
 72 #define MBP_RXPASSCRC                   0x40000000
 73 #define MBP_RXQOS                       0x20000000
 74 #define MBP_RXNOCHAIN                   0x10000000
 75 #define MBP_RXCMF                       0x01000000
 76 #define MBP_RXSHORT                     0x00800000
 77 #define MBP_RXCEF                       0x00400000
 78 #define MBP_RXPROMISC                   0x00200000
 79 #define MBP_PROMISCCHAN(channel)        (((channel) & 0x7) << 16)
 80 #define MBP_RXBCAST                     0x00002000
 81 #define MBP_BCASTCHAN(channel)          (((channel) & 0x7) << 8)
 82 #define MBP_RXMCAST                     0x00000020
 83 #define MBP_MCASTCHAN(channel)          ((channel) & 0x7)
 84 #define CPMAC_UNICAST_ENABLE            0x0104
 85 #define CPMAC_UNICAST_CLEAR             0x0108
 86 #define CPMAC_MAX_LENGTH                0x010c
 87 #define CPMAC_BUFFER_OFFSET             0x0110
 88 #define CPMAC_MAC_CONTROL               0x0160
 89 #define MAC_TXPTYPE                     0x00000200
 90 #define MAC_TXPACE                      0x00000040
 91 #define MAC_MII                         0x00000020
 92 #define MAC_TXFLOW                      0x00000010
 93 #define MAC_RXFLOW                      0x00000008
 94 #define MAC_MTEST                       0x00000004
 95 #define MAC_LOOPBACK                    0x00000002
 96 #define MAC_FDX                         0x00000001
 97 #define CPMAC_MAC_STATUS                0x0164
 98 #define MAC_STATUS_QOS                  0x00000004
 99 #define MAC_STATUS_RXFLOW               0x00000002
100 #define MAC_STATUS_TXFLOW               0x00000001
101 #define CPMAC_TX_INT_ENABLE             0x0178
102 #define CPMAC_TX_INT_CLEAR              0x017c
103 #define CPMAC_MAC_INT_VECTOR            0x0180
104 #define MAC_INT_STATUS                  0x00080000
105 #define MAC_INT_HOST                    0x00040000
106 #define MAC_INT_RX                      0x00020000
107 #define MAC_INT_TX                      0x00010000
108 #define CPMAC_MAC_EOI_VECTOR            0x0184
109 #define CPMAC_RX_INT_ENABLE             0x0198
110 #define CPMAC_RX_INT_CLEAR              0x019c
111 #define CPMAC_MAC_INT_ENABLE            0x01a8
112 #define CPMAC_MAC_INT_CLEAR             0x01ac
113 #define CPMAC_MAC_ADDR_LO(channel)      (0x01b0 + (channel) * 4)
114 #define CPMAC_MAC_ADDR_MID              0x01d0
115 #define CPMAC_MAC_ADDR_HI               0x01d4
116 #define CPMAC_MAC_HASH_LO               0x01d8
117 #define CPMAC_MAC_HASH_HI               0x01dc
118 #define CPMAC_TX_PTR(channel)           (0x0600 + (channel) * 4)
119 #define CPMAC_RX_PTR(channel)           (0x0620 + (channel) * 4)
120 #define CPMAC_TX_ACK(channel)           (0x0640 + (channel) * 4)
121 #define CPMAC_RX_ACK(channel)           (0x0660 + (channel) * 4)
122 #define CPMAC_REG_END                   0x0680
123 
124 /* Rx/Tx statistics
125  * TODO: use some of them to fill stats in cpmac_stats()
126  */
127 #define CPMAC_STATS_RX_GOOD             0x0200
128 #define CPMAC_STATS_RX_BCAST            0x0204
129 #define CPMAC_STATS_RX_MCAST            0x0208
130 #define CPMAC_STATS_RX_PAUSE            0x020c
131 #define CPMAC_STATS_RX_CRC              0x0210
132 #define CPMAC_STATS_RX_ALIGN            0x0214
133 #define CPMAC_STATS_RX_OVER             0x0218
134 #define CPMAC_STATS_RX_JABBER           0x021c
135 #define CPMAC_STATS_RX_UNDER            0x0220
136 #define CPMAC_STATS_RX_FRAG             0x0224
137 #define CPMAC_STATS_RX_FILTER           0x0228
138 #define CPMAC_STATS_RX_QOSFILTER        0x022c
139 #define CPMAC_STATS_RX_OCTETS           0x0230
140 
141 #define CPMAC_STATS_TX_GOOD             0x0234
142 #define CPMAC_STATS_TX_BCAST            0x0238
143 #define CPMAC_STATS_TX_MCAST            0x023c
144 #define CPMAC_STATS_TX_PAUSE            0x0240
145 #define CPMAC_STATS_TX_DEFER            0x0244
146 #define CPMAC_STATS_TX_COLLISION        0x0248
147 #define CPMAC_STATS_TX_SINGLECOLL       0x024c
148 #define CPMAC_STATS_TX_MULTICOLL        0x0250
149 #define CPMAC_STATS_TX_EXCESSCOLL       0x0254
150 #define CPMAC_STATS_TX_LATECOLL         0x0258
151 #define CPMAC_STATS_TX_UNDERRUN         0x025c
152 #define CPMAC_STATS_TX_CARRIERSENSE     0x0260
153 #define CPMAC_STATS_TX_OCTETS           0x0264
154 
155 #define cpmac_read(base, reg)           (readl((void __iomem *)(base) + (reg)))
156 #define cpmac_write(base, reg, val)     (writel(val, (void __iomem *)(base) + \
157                                                 (reg)))
158 
159 /* MDIO bus */
160 #define CPMAC_MDIO_VERSION              0x0000
161 #define CPMAC_MDIO_CONTROL              0x0004
162 #define MDIOC_IDLE                      0x80000000
163 #define MDIOC_ENABLE                    0x40000000
164 #define MDIOC_PREAMBLE                  0x00100000
165 #define MDIOC_FAULT                     0x00080000
166 #define MDIOC_FAULTDETECT               0x00040000
167 #define MDIOC_INTTEST                   0x00020000
168 #define MDIOC_CLKDIV(div)               ((div) & 0xff)
169 #define CPMAC_MDIO_ALIVE                0x0008
170 #define CPMAC_MDIO_LINK                 0x000c
171 #define CPMAC_MDIO_ACCESS(channel)      (0x0080 + (channel) * 8)
172 #define MDIO_BUSY                       0x80000000
173 #define MDIO_WRITE                      0x40000000
174 #define MDIO_REG(reg)                   (((reg) & 0x1f) << 21)
175 #define MDIO_PHY(phy)                   (((phy) & 0x1f) << 16)
176 #define MDIO_DATA(data)                 ((data) & 0xffff)
177 #define CPMAC_MDIO_PHYSEL(channel)      (0x0084 + (channel) * 8)
178 #define PHYSEL_LINKSEL                  0x00000040
179 #define PHYSEL_LINKINT                  0x00000020
180 
181 struct cpmac_desc {
182         u32 hw_next;
183         u32 hw_data;
184         u16 buflen;
185         u16 bufflags;
186         u16 datalen;
187         u16 dataflags;
188 #define CPMAC_SOP                       0x8000
189 #define CPMAC_EOP                       0x4000
190 #define CPMAC_OWN                       0x2000
191 #define CPMAC_EOQ                       0x1000
192         struct sk_buff *skb;
193         struct cpmac_desc *next;
194         struct cpmac_desc *prev;
195         dma_addr_t mapping;
196         dma_addr_t data_mapping;
197 };
198 
199 struct cpmac_priv {
200         spinlock_t lock;
201         spinlock_t rx_lock;
202         struct cpmac_desc *rx_head;
203         int ring_size;
204         struct cpmac_desc *desc_ring;
205         dma_addr_t dma_ring;
206         void __iomem *regs;
207         struct mii_bus *mii_bus;
208         char phy_name[MII_BUS_ID_SIZE + 3];
209         int oldlink, oldspeed, oldduplex;
210         u32 msg_enable;
211         struct net_device *dev;
212         struct work_struct reset_work;
213         struct platform_device *pdev;
214         struct napi_struct napi;
215         atomic_t reset_pending;
216 };
217 
218 static irqreturn_t cpmac_irq(int, void *);
219 static void cpmac_hw_start(struct net_device *dev);
220 static void cpmac_hw_stop(struct net_device *dev);
221 static int cpmac_stop(struct net_device *dev);
222 static int cpmac_open(struct net_device *dev);
223 
224 static void cpmac_dump_regs(struct net_device *dev)
225 {
226         int i;
227         struct cpmac_priv *priv = netdev_priv(dev);
228 
229         for (i = 0; i < CPMAC_REG_END; i += 4) {
230                 if (i % 16 == 0) {
231                         if (i)
232                                 printk("\n");
233                         printk("%s: reg[%p]:", dev->name, priv->regs + i);
234                 }
235                 printk(" %08x", cpmac_read(priv->regs, i));
236         }
237         printk("\n");
238 }
239 
240 static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc)
241 {
242         int i;
243 
244         printk("%s: desc[%p]:", dev->name, desc);
245         for (i = 0; i < sizeof(*desc) / 4; i++)
246                 printk(" %08x", ((u32 *)desc)[i]);
247         printk("\n");
248 }
249 
250 static void cpmac_dump_all_desc(struct net_device *dev)
251 {
252         struct cpmac_priv *priv = netdev_priv(dev);
253         struct cpmac_desc *dump = priv->rx_head;
254 
255         do {
256                 cpmac_dump_desc(dev, dump);
257                 dump = dump->next;
258         } while (dump != priv->rx_head);
259 }
260 
261 static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb)
262 {
263         int i;
264 
265         printk("%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len);
266         for (i = 0; i < skb->len; i++) {
267                 if (i % 16 == 0) {
268                         if (i)
269                                 printk("\n");
270                         printk("%s: data[%p]:", dev->name, skb->data + i);
271                 }
272                 printk(" %02x", ((u8 *)skb->data)[i]);
273         }
274         printk("\n");
275 }
276 
277 static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
278 {
279         u32 val;
280 
281         while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
282                 cpu_relax();
283         cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |
284                     MDIO_PHY(phy_id));
285         while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY)
286                 cpu_relax();
287 
288         return MDIO_DATA(val);
289 }
290 
291 static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
292                             int reg, u16 val)
293 {
294         while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
295                 cpu_relax();
296         cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
297                     MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val));
298 
299         return 0;
300 }
301 
302 static int cpmac_mdio_reset(struct mii_bus *bus)
303 {
304         struct clk *cpmac_clk;
305 
306         cpmac_clk = clk_get(&bus->dev, "cpmac");
307         if (IS_ERR(cpmac_clk)) {
308                 pr_err("unable to get cpmac clock\n");
309                 return -1;
310         }
311         ar7_device_reset(AR7_RESET_BIT_MDIO);
312         cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
313                     MDIOC_CLKDIV(clk_get_rate(cpmac_clk) / 2200000 - 1));
314 
315         return 0;
316 }
317 
318 static struct mii_bus *cpmac_mii;
319 
320 static void cpmac_set_multicast_list(struct net_device *dev)
321 {
322         struct netdev_hw_addr *ha;
323         u8 tmp;
324         u32 mbp, bit, hash[2] = { 0, };
325         struct cpmac_priv *priv = netdev_priv(dev);
326 
327         mbp = cpmac_read(priv->regs, CPMAC_MBP);
328         if (dev->flags & IFF_PROMISC) {
329                 cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) |
330                             MBP_RXPROMISC);
331         } else {
332                 cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC);
333                 if (dev->flags & IFF_ALLMULTI) {
334                         /* enable all multicast mode */
335                         cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff);
336                         cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff);
337                 } else {
338                         /* cpmac uses some strange mac address hashing
339                          * (not crc32)
340                          */
341                         netdev_for_each_mc_addr(ha, dev) {
342                                 bit = 0;
343                                 tmp = ha->addr[0];
344                                 bit  ^= (tmp >> 2) ^ (tmp << 4);
345                                 tmp = ha->addr[1];
346                                 bit  ^= (tmp >> 4) ^ (tmp << 2);
347                                 tmp = ha->addr[2];
348                                 bit  ^= (tmp >> 6) ^ tmp;
349                                 tmp = ha->addr[3];
350                                 bit  ^= (tmp >> 2) ^ (tmp << 4);
351                                 tmp = ha->addr[4];
352                                 bit  ^= (tmp >> 4) ^ (tmp << 2);
353                                 tmp = ha->addr[5];
354                                 bit  ^= (tmp >> 6) ^ tmp;
355                                 bit &= 0x3f;
356                                 hash[bit / 32] |= 1 << (bit % 32);
357                         }
358 
359                         cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]);
360                         cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]);
361                 }
362         }
363 }
364 
365 static struct sk_buff *cpmac_rx_one(struct cpmac_priv *priv,
366                                     struct cpmac_desc *desc)
367 {
368         struct sk_buff *skb, *result = NULL;
369 
370         if (unlikely(netif_msg_hw(priv)))
371                 cpmac_dump_desc(priv->dev, desc);
372         cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping);
373         if (unlikely(!desc->datalen)) {
374                 if (netif_msg_rx_err(priv) && net_ratelimit())
375                         netdev_warn(priv->dev, "rx: spurious interrupt\n");
376 
377                 return NULL;
378         }
379 
380         skb = netdev_alloc_skb_ip_align(priv->dev, CPMAC_SKB_SIZE);
381         if (likely(skb)) {
382                 skb_put(desc->skb, desc->datalen);
383                 desc->skb->protocol = eth_type_trans(desc->skb, priv->dev);
384                 skb_checksum_none_assert(desc->skb);
385                 priv->dev->stats.rx_packets++;
386                 priv->dev->stats.rx_bytes += desc->datalen;
387                 result = desc->skb;
388                 dma_unmap_single(&priv->dev->dev, desc->data_mapping,
389                                  CPMAC_SKB_SIZE, DMA_FROM_DEVICE);
390                 desc->skb = skb;
391                 desc->data_mapping = dma_map_single(&priv->dev->dev, skb->data,
392                                                     CPMAC_SKB_SIZE,
393                                                     DMA_FROM_DEVICE);
394                 desc->hw_data = (u32)desc->data_mapping;
395                 if (unlikely(netif_msg_pktdata(priv))) {
396                         netdev_dbg(priv->dev, "received packet:\n");
397                         cpmac_dump_skb(priv->dev, result);
398                 }
399         } else {
400                 if (netif_msg_rx_err(priv) && net_ratelimit())
401                         netdev_warn(priv->dev,
402                                     "low on skbs, dropping packet\n");
403 
404                 priv->dev->stats.rx_dropped++;
405         }
406 
407         desc->buflen = CPMAC_SKB_SIZE;
408         desc->dataflags = CPMAC_OWN;
409 
410         return result;
411 }
412 
413 static int cpmac_poll(struct napi_struct *napi, int budget)
414 {
415         struct sk_buff *skb;
416         struct cpmac_desc *desc, *restart;
417         struct cpmac_priv *priv = container_of(napi, struct cpmac_priv, napi);
418         int received = 0, processed = 0;
419 
420         spin_lock(&priv->rx_lock);
421         if (unlikely(!priv->rx_head)) {
422                 if (netif_msg_rx_err(priv) && net_ratelimit())
423                         netdev_warn(priv->dev, "rx: polling, but no queue\n");
424 
425                 spin_unlock(&priv->rx_lock);
426                 napi_complete(napi);
427                 return 0;
428         }
429 
430         desc = priv->rx_head;
431         restart = NULL;
432         while (((desc->dataflags & CPMAC_OWN) == 0) && (received < budget)) {
433                 processed++;
434 
435                 if ((desc->dataflags & CPMAC_EOQ) != 0) {
436                         /* The last update to eoq->hw_next didn't happen
437                          * soon enough, and the receiver stopped here.
438                          * Remember this descriptor so we can restart
439                          * the receiver after freeing some space.
440                          */
441                         if (unlikely(restart)) {
442                                 if (netif_msg_rx_err(priv))
443                                         netdev_err(priv->dev, "poll found a"
444                                                    " duplicate EOQ: %p and %p\n",
445                                                    restart, desc);
446                                 goto fatal_error;
447                         }
448 
449                         restart = desc->next;
450                 }
451 
452                 skb = cpmac_rx_one(priv, desc);
453                 if (likely(skb)) {
454                         netif_receive_skb(skb);
455                         received++;
456                 }
457                 desc = desc->next;
458         }
459 
460         if (desc != priv->rx_head) {
461                 /* We freed some buffers, but not the whole ring,
462                  * add what we did free to the rx list
463                  */
464                 desc->prev->hw_next = (u32)0;
465                 priv->rx_head->prev->hw_next = priv->rx_head->mapping;
466         }
467 
468         /* Optimization: If we did not actually process an EOQ (perhaps because
469          * of quota limits), check to see if the tail of the queue has EOQ set.
470          * We should immediately restart in that case so that the receiver can
471          * restart and run in parallel with more packet processing.
472          * This lets us handle slightly larger bursts before running
473          * out of ring space (assuming dev->weight < ring_size)
474          */
475 
476         if (!restart &&
477              (priv->rx_head->prev->dataflags & (CPMAC_OWN|CPMAC_EOQ))
478                     == CPMAC_EOQ &&
479              (priv->rx_head->dataflags & CPMAC_OWN) != 0) {
480                 /* reset EOQ so the poll loop (above) doesn't try to
481                  * restart this when it eventually gets to this descriptor.
482                  */
483                 priv->rx_head->prev->dataflags &= ~CPMAC_EOQ;
484                 restart = priv->rx_head;
485         }
486 
487         if (restart) {
488                 priv->dev->stats.rx_errors++;
489                 priv->dev->stats.rx_fifo_errors++;
490                 if (netif_msg_rx_err(priv) && net_ratelimit())
491                         netdev_warn(priv->dev, "rx dma ring overrun\n");
492 
493                 if (unlikely((restart->dataflags & CPMAC_OWN) == 0)) {
494                         if (netif_msg_drv(priv))
495                                 netdev_err(priv->dev, "cpmac_poll is trying "
496                                         "to restart rx from a descriptor "
497                                         "that's not free: %p\n", restart);
498                         goto fatal_error;
499                 }
500 
501                 cpmac_write(priv->regs, CPMAC_RX_PTR(0), restart->mapping);
502         }
503 
504         priv->rx_head = desc;
505         spin_unlock(&priv->rx_lock);
506         if (unlikely(netif_msg_rx_status(priv)))
507                 netdev_dbg(priv->dev, "poll processed %d packets\n", received);
508 
509         if (processed == 0) {
510                 /* we ran out of packets to read,
511                  * revert to interrupt-driven mode
512                  */
513                 napi_complete(napi);
514                 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
515                 return 0;
516         }
517 
518         return 1;
519 
520 fatal_error:
521         /* Something went horribly wrong.
522          * Reset hardware to try to recover rather than wedging.
523          */
524         if (netif_msg_drv(priv)) {
525                 netdev_err(priv->dev, "cpmac_poll is confused. "
526                            "Resetting hardware\n");
527                 cpmac_dump_all_desc(priv->dev);
528                 netdev_dbg(priv->dev, "RX_PTR(0)=0x%08x RX_ACK(0)=0x%08x\n",
529                            cpmac_read(priv->regs, CPMAC_RX_PTR(0)),
530                            cpmac_read(priv->regs, CPMAC_RX_ACK(0)));
531         }
532 
533         spin_unlock(&priv->rx_lock);
534         napi_complete(napi);
535         netif_tx_stop_all_queues(priv->dev);
536         napi_disable(&priv->napi);
537 
538         atomic_inc(&priv->reset_pending);
539         cpmac_hw_stop(priv->dev);
540         if (!schedule_work(&priv->reset_work))
541                 atomic_dec(&priv->reset_pending);
542 
543         return 0;
544 
545 }
546 
547 static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
548 {
549         int queue;
550         unsigned int len;
551         struct cpmac_desc *desc;
552         struct cpmac_priv *priv = netdev_priv(dev);
553 
554         if (unlikely(atomic_read(&priv->reset_pending)))
555                 return NETDEV_TX_BUSY;
556 
557         if (unlikely(skb_padto(skb, ETH_ZLEN)))
558                 return NETDEV_TX_OK;
559 
560         len = max_t(unsigned int, skb->len, ETH_ZLEN);
561         queue = skb_get_queue_mapping(skb);
562         netif_stop_subqueue(dev, queue);
563 
564         desc = &priv->desc_ring[queue];
565         if (unlikely(desc->dataflags & CPMAC_OWN)) {
566                 if (netif_msg_tx_err(priv) && net_ratelimit())
567                         netdev_warn(dev, "tx dma ring full\n");
568 
569                 return NETDEV_TX_BUSY;
570         }
571 
572         spin_lock(&priv->lock);
573         spin_unlock(&priv->lock);
574         desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN;
575         desc->skb = skb;
576         desc->data_mapping = dma_map_single(&dev->dev, skb->data, len,
577                                             DMA_TO_DEVICE);
578         desc->hw_data = (u32)desc->data_mapping;
579         desc->datalen = len;
580         desc->buflen = len;
581         if (unlikely(netif_msg_tx_queued(priv)))
582                 netdev_dbg(dev, "sending 0x%p, len=%d\n", skb, skb->len);
583         if (unlikely(netif_msg_hw(priv)))
584                 cpmac_dump_desc(dev, desc);
585         if (unlikely(netif_msg_pktdata(priv)))
586                 cpmac_dump_skb(dev, skb);
587         cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping);
588 
589         return NETDEV_TX_OK;
590 }
591 
592 static void cpmac_end_xmit(struct net_device *dev, int queue)
593 {
594         struct cpmac_desc *desc;
595         struct cpmac_priv *priv = netdev_priv(dev);
596 
597         desc = &priv->desc_ring[queue];
598         cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping);
599         if (likely(desc->skb)) {
600                 spin_lock(&priv->lock);
601                 dev->stats.tx_packets++;
602                 dev->stats.tx_bytes += desc->skb->len;
603                 spin_unlock(&priv->lock);
604                 dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len,
605                                  DMA_TO_DEVICE);
606 
607                 if (unlikely(netif_msg_tx_done(priv)))
608                         netdev_dbg(dev, "sent 0x%p, len=%d\n",
609                                    desc->skb, desc->skb->len);
610 
611                 dev_kfree_skb_irq(desc->skb);
612                 desc->skb = NULL;
613                 if (__netif_subqueue_stopped(dev, queue))
614                         netif_wake_subqueue(dev, queue);
615         } else {
616                 if (netif_msg_tx_err(priv) && net_ratelimit())
617                         netdev_warn(dev, "end_xmit: spurious interrupt\n");
618                 if (__netif_subqueue_stopped(dev, queue))
619                         netif_wake_subqueue(dev, queue);
620         }
621 }
622 
623 static void cpmac_hw_stop(struct net_device *dev)
624 {
625         int i;
626         struct cpmac_priv *priv = netdev_priv(dev);
627         struct plat_cpmac_data *pdata = dev_get_platdata(&priv->pdev->dev);
628 
629         ar7_device_reset(pdata->reset_bit);
630         cpmac_write(priv->regs, CPMAC_RX_CONTROL,
631                     cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1);
632         cpmac_write(priv->regs, CPMAC_TX_CONTROL,
633                     cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1);
634         for (i = 0; i < 8; i++) {
635                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
636                 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
637         }
638         cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
639         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
640         cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
641         cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
642         cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
643                     cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII);
644 }
645 
646 static void cpmac_hw_start(struct net_device *dev)
647 {
648         int i;
649         struct cpmac_priv *priv = netdev_priv(dev);
650         struct plat_cpmac_data *pdata = dev_get_platdata(&priv->pdev->dev);
651 
652         ar7_device_reset(pdata->reset_bit);
653         for (i = 0; i < 8; i++) {
654                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
655                 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
656         }
657         cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);
658 
659         cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
660                     MBP_RXMCAST);
661         cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);
662         for (i = 0; i < 8; i++)
663                 cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
664         cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
665         cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |
666                     (dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) |
667                     (dev->dev_addr[3] << 24));
668         cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
669         cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
670         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
671         cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
672         cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
673         cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);
674         cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
675         cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);
676         cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
677 
678         cpmac_write(priv->regs, CPMAC_RX_CONTROL,
679                     cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1);
680         cpmac_write(priv->regs, CPMAC_TX_CONTROL,
681                     cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1);
682         cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
683                     cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII |
684                     MAC_FDX);
685 }
686 
687 static void cpmac_clear_rx(struct net_device *dev)
688 {
689         struct cpmac_priv *priv = netdev_priv(dev);
690         struct cpmac_desc *desc;
691         int i;
692 
693         if (unlikely(!priv->rx_head))
694                 return;
695         desc = priv->rx_head;
696         for (i = 0; i < priv->ring_size; i++) {
697                 if ((desc->dataflags & CPMAC_OWN) == 0) {
698                         if (netif_msg_rx_err(priv) && net_ratelimit())
699                                 netdev_warn(dev, "packet dropped\n");
700                         if (unlikely(netif_msg_hw(priv)))
701                                 cpmac_dump_desc(dev, desc);
702                         desc->dataflags = CPMAC_OWN;
703                         dev->stats.rx_dropped++;
704                 }
705                 desc->hw_next = desc->next->mapping;
706                 desc = desc->next;
707         }
708         priv->rx_head->prev->hw_next = 0;
709 }
710 
711 static void cpmac_clear_tx(struct net_device *dev)
712 {
713         struct cpmac_priv *priv = netdev_priv(dev);
714         int i;
715 
716         if (unlikely(!priv->desc_ring))
717                 return;
718         for (i = 0; i < CPMAC_QUEUES; i++) {
719                 priv->desc_ring[i].dataflags = 0;
720                 if (priv->desc_ring[i].skb) {
721                         dev_kfree_skb_any(priv->desc_ring[i].skb);
722                         priv->desc_ring[i].skb = NULL;
723                 }
724         }
725 }
726 
727 static void cpmac_hw_error(struct work_struct *work)
728 {
729         struct cpmac_priv *priv =
730                 container_of(work, struct cpmac_priv, reset_work);
731 
732         spin_lock(&priv->rx_lock);
733         cpmac_clear_rx(priv->dev);
734         spin_unlock(&priv->rx_lock);
735         cpmac_clear_tx(priv->dev);
736         cpmac_hw_start(priv->dev);
737         barrier();
738         atomic_dec(&priv->reset_pending);
739 
740         netif_tx_wake_all_queues(priv->dev);
741         cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
742 }
743 
744 static void cpmac_check_status(struct net_device *dev)
745 {
746         struct cpmac_priv *priv = netdev_priv(dev);
747 
748         u32 macstatus = cpmac_read(priv->regs, CPMAC_MAC_STATUS);
749         int rx_channel = (macstatus >> 8) & 7;
750         int rx_code = (macstatus >> 12) & 15;
751         int tx_channel = (macstatus >> 16) & 7;
752         int tx_code = (macstatus >> 20) & 15;
753 
754         if (rx_code || tx_code) {
755                 if (netif_msg_drv(priv) && net_ratelimit()) {
756                         /* Can't find any documentation on what these
757                          * error codes actually are. So just log them and hope..
758                          */
759                         if (rx_code)
760                                 netdev_warn(dev, "host error %d on rx "
761                                         "channel %d (macstatus %08x), resetting\n",
762                                         rx_code, rx_channel, macstatus);
763                         if (tx_code)
764                                 netdev_warn(dev, "host error %d on tx "
765                                         "channel %d (macstatus %08x), resetting\n",
766                                         tx_code, tx_channel, macstatus);
767                 }
768 
769                 netif_tx_stop_all_queues(dev);
770                 cpmac_hw_stop(dev);
771                 if (schedule_work(&priv->reset_work))
772                         atomic_inc(&priv->reset_pending);
773                 if (unlikely(netif_msg_hw(priv)))
774                         cpmac_dump_regs(dev);
775         }
776         cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
777 }
778 
779 static irqreturn_t cpmac_irq(int irq, void *dev_id)
780 {
781         struct net_device *dev = dev_id;
782         struct cpmac_priv *priv;
783         int queue;
784         u32 status;
785 
786         priv = netdev_priv(dev);
787 
788         status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR);
789 
790         if (unlikely(netif_msg_intr(priv)))
791                 netdev_dbg(dev, "interrupt status: 0x%08x\n", status);
792 
793         if (status & MAC_INT_TX)
794                 cpmac_end_xmit(dev, (status & 7));
795 
796         if (status & MAC_INT_RX) {
797                 queue = (status >> 8) & 7;
798                 if (napi_schedule_prep(&priv->napi)) {
799                         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue);
800                         __napi_schedule(&priv->napi);
801                 }
802         }
803 
804         cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0);
805 
806         if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS)))
807                 cpmac_check_status(dev);
808 
809         return IRQ_HANDLED;
810 }
811 
812 static void cpmac_tx_timeout(struct net_device *dev)
813 {
814         struct cpmac_priv *priv = netdev_priv(dev);
815 
816         spin_lock(&priv->lock);
817         dev->stats.tx_errors++;
818         spin_unlock(&priv->lock);
819         if (netif_msg_tx_err(priv) && net_ratelimit())
820                 netdev_warn(dev, "transmit timeout\n");
821 
822         atomic_inc(&priv->reset_pending);
823         barrier();
824         cpmac_clear_tx(dev);
825         barrier();
826         atomic_dec(&priv->reset_pending);
827 
828         netif_tx_wake_all_queues(priv->dev);
829 }
830 
831 static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
832 {
833         if (!(netif_running(dev)))
834                 return -EINVAL;
835         if (!dev->phydev)
836                 return -EINVAL;
837 
838         return phy_mii_ioctl(dev->phydev, ifr, cmd);
839 }
840 
841 static void cpmac_get_ringparam(struct net_device *dev,
842                                                 struct ethtool_ringparam *ring)
843 {
844         struct cpmac_priv *priv = netdev_priv(dev);
845 
846         ring->rx_max_pending = 1024;
847         ring->rx_mini_max_pending = 1;
848         ring->rx_jumbo_max_pending = 1;
849         ring->tx_max_pending = 1;
850 
851         ring->rx_pending = priv->ring_size;
852         ring->rx_mini_pending = 1;
853         ring->rx_jumbo_pending = 1;
854         ring->tx_pending = 1;
855 }
856 
857 static int cpmac_set_ringparam(struct net_device *dev,
858                                                 struct ethtool_ringparam *ring)
859 {
860         struct cpmac_priv *priv = netdev_priv(dev);
861 
862         if (netif_running(dev))
863                 return -EBUSY;
864         priv->ring_size = ring->rx_pending;
865 
866         return 0;
867 }
868 
869 static void cpmac_get_drvinfo(struct net_device *dev,
870                               struct ethtool_drvinfo *info)
871 {
872         strlcpy(info->driver, "cpmac", sizeof(info->driver));
873         strlcpy(info->version, CPMAC_VERSION, sizeof(info->version));
874         snprintf(info->bus_info, sizeof(info->bus_info), "%s", "cpmac");
875 }
876 
877 static const struct ethtool_ops cpmac_ethtool_ops = {
878         .get_drvinfo = cpmac_get_drvinfo,
879         .get_link = ethtool_op_get_link,
880         .get_ringparam = cpmac_get_ringparam,
881         .set_ringparam = cpmac_set_ringparam,
882         .get_link_ksettings = phy_ethtool_get_link_ksettings,
883         .set_link_ksettings = phy_ethtool_set_link_ksettings,
884 };
885 
886 static void cpmac_adjust_link(struct net_device *dev)
887 {
888         struct cpmac_priv *priv = netdev_priv(dev);
889         int new_state = 0;
890 
891         spin_lock(&priv->lock);
892         if (dev->phydev->link) {
893                 netif_tx_start_all_queues(dev);
894                 if (dev->phydev->duplex != priv->oldduplex) {
895                         new_state = 1;
896                         priv->oldduplex = dev->phydev->duplex;
897                 }
898 
899                 if (dev->phydev->speed != priv->oldspeed) {
900                         new_state = 1;
901                         priv->oldspeed = dev->phydev->speed;
902                 }
903 
904                 if (!priv->oldlink) {
905                         new_state = 1;
906                         priv->oldlink = 1;
907                 }
908         } else if (priv->oldlink) {
909                 new_state = 1;
910                 priv->oldlink = 0;
911                 priv->oldspeed = 0;
912                 priv->oldduplex = -1;
913         }
914 
915         if (new_state && netif_msg_link(priv) && net_ratelimit())
916                 phy_print_status(dev->phydev);
917 
918         spin_unlock(&priv->lock);
919 }
920 
921 static int cpmac_open(struct net_device *dev)
922 {
923         int i, size, res;
924         struct cpmac_priv *priv = netdev_priv(dev);
925         struct resource *mem;
926         struct cpmac_desc *desc;
927         struct sk_buff *skb;
928 
929         mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
930         if (!request_mem_region(mem->start, resource_size(mem), dev->name)) {
931                 if (netif_msg_drv(priv))
932                         netdev_err(dev, "failed to request registers\n");
933 
934                 res = -ENXIO;
935                 goto fail_reserve;
936         }
937 
938         priv->regs = ioremap(mem->start, resource_size(mem));
939         if (!priv->regs) {
940                 if (netif_msg_drv(priv))
941                         netdev_err(dev, "failed to remap registers\n");
942 
943                 res = -ENXIO;
944                 goto fail_remap;
945         }
946 
947         size = priv->ring_size + CPMAC_QUEUES;
948         priv->desc_ring = dma_alloc_coherent(&dev->dev,
949                                              sizeof(struct cpmac_desc) * size,
950                                              &priv->dma_ring,
951                                              GFP_KERNEL);
952         if (!priv->desc_ring) {
953                 res = -ENOMEM;
954                 goto fail_alloc;
955         }
956 
957         for (i = 0; i < size; i++)
958                 priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i;
959 
960         priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
961         for (i = 0, desc = priv->rx_head; i < priv->ring_size; i++, desc++) {
962                 skb = netdev_alloc_skb_ip_align(dev, CPMAC_SKB_SIZE);
963                 if (unlikely(!skb)) {
964                         res = -ENOMEM;
965                         goto fail_desc;
966                 }
967                 desc->skb = skb;
968                 desc->data_mapping = dma_map_single(&dev->dev, skb->data,
969                                                     CPMAC_SKB_SIZE,
970                                                     DMA_FROM_DEVICE);
971                 desc->hw_data = (u32)desc->data_mapping;
972                 desc->buflen = CPMAC_SKB_SIZE;
973                 desc->dataflags = CPMAC_OWN;
974                 desc->next = &priv->rx_head[(i + 1) % priv->ring_size];
975                 desc->next->prev = desc;
976                 desc->hw_next = (u32)desc->next->mapping;
977         }
978 
979         priv->rx_head->prev->hw_next = (u32)0;
980 
981         res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED, dev->name, dev);
982         if (res) {
983                 if (netif_msg_drv(priv))
984                         netdev_err(dev, "failed to obtain irq\n");
985 
986                 goto fail_irq;
987         }
988 
989         atomic_set(&priv->reset_pending, 0);
990         INIT_WORK(&priv->reset_work, cpmac_hw_error);
991         cpmac_hw_start(dev);
992 
993         napi_enable(&priv->napi);
994         dev->phydev->state = PHY_CHANGELINK;
995         phy_start(dev->phydev);
996 
997         return 0;
998 
999 fail_irq:
1000 fail_desc:
1001         for (i = 0; i < priv->ring_size; i++) {
1002                 if (priv->rx_head[i].skb) {
1003                         dma_unmap_single(&dev->dev,
1004                                          priv->rx_head[i].data_mapping,
1005                                          CPMAC_SKB_SIZE,
1006                                          DMA_FROM_DEVICE);
1007                         kfree_skb(priv->rx_head[i].skb);
1008                 }
1009         }
1010         dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) * size,
1011                           priv->desc_ring, priv->dma_ring);
1012 
1013 fail_alloc:
1014         iounmap(priv->regs);
1015 
1016 fail_remap:
1017         release_mem_region(mem->start, resource_size(mem));
1018 
1019 fail_reserve:
1020         return res;
1021 }
1022 
1023 static int cpmac_stop(struct net_device *dev)
1024 {
1025         int i;
1026         struct cpmac_priv *priv = netdev_priv(dev);
1027         struct resource *mem;
1028 
1029         netif_tx_stop_all_queues(dev);
1030 
1031         cancel_work_sync(&priv->reset_work);
1032         napi_disable(&priv->napi);
1033         phy_stop(dev->phydev);
1034 
1035         cpmac_hw_stop(dev);
1036 
1037         for (i = 0; i < 8; i++)
1038                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
1039         cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0);
1040         cpmac_write(priv->regs, CPMAC_MBP, 0);
1041 
1042         free_irq(dev->irq, dev);
1043         iounmap(priv->regs);
1044         mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
1045         release_mem_region(mem->start, resource_size(mem));
1046         priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
1047         for (i = 0; i < priv->ring_size; i++) {
1048                 if (priv->rx_head[i].skb) {
1049                         dma_unmap_single(&dev->dev,
1050                                          priv->rx_head[i].data_mapping,
1051                                          CPMAC_SKB_SIZE,
1052                                          DMA_FROM_DEVICE);
1053                         kfree_skb(priv->rx_head[i].skb);
1054                 }
1055         }
1056 
1057         dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) *
1058                           (CPMAC_QUEUES + priv->ring_size),
1059                           priv->desc_ring, priv->dma_ring);
1060 
1061         return 0;
1062 }
1063 
1064 static const struct net_device_ops cpmac_netdev_ops = {
1065         .ndo_open               = cpmac_open,
1066         .ndo_stop               = cpmac_stop,
1067         .ndo_start_xmit         = cpmac_start_xmit,
1068         .ndo_tx_timeout         = cpmac_tx_timeout,
1069         .ndo_set_rx_mode        = cpmac_set_multicast_list,
1070         .ndo_do_ioctl           = cpmac_ioctl,
1071         .ndo_change_mtu         = eth_change_mtu,
1072         .ndo_validate_addr      = eth_validate_addr,
1073         .ndo_set_mac_address    = eth_mac_addr,
1074 };
1075 
1076 static int external_switch;
1077 
1078 static int cpmac_probe(struct platform_device *pdev)
1079 {
1080         int rc, phy_id;
1081         char mdio_bus_id[MII_BUS_ID_SIZE];
1082         struct resource *mem;
1083         struct cpmac_priv *priv;
1084         struct net_device *dev;
1085         struct plat_cpmac_data *pdata;
1086         struct phy_device *phydev = NULL;
1087 
1088         pdata = dev_get_platdata(&pdev->dev);
1089 
1090         if (external_switch || dumb_switch) {
1091                 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); /* fixed phys bus */
1092                 phy_id = pdev->id;
1093         } else {
1094                 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1095                         if (!(pdata->phy_mask & (1 << phy_id)))
1096                                 continue;
1097                         if (!mdiobus_get_phy(cpmac_mii, phy_id))
1098                                 continue;
1099                         strncpy(mdio_bus_id, cpmac_mii->id, MII_BUS_ID_SIZE);
1100                         break;
1101                 }
1102         }
1103 
1104         if (phy_id == PHY_MAX_ADDR) {
1105                 dev_err(&pdev->dev, "no PHY present, falling back "
1106                         "to switch on MDIO bus 0\n");
1107                 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); /* fixed phys bus */
1108                 phy_id = pdev->id;
1109         }
1110         mdio_bus_id[sizeof(mdio_bus_id) - 1] = '\0';
1111 
1112         dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES);
1113         if (!dev)
1114                 return -ENOMEM;
1115 
1116         SET_NETDEV_DEV(dev, &pdev->dev);
1117         platform_set_drvdata(pdev, dev);
1118         priv = netdev_priv(dev);
1119 
1120         priv->pdev = pdev;
1121         mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1122         if (!mem) {
1123                 rc = -ENODEV;
1124                 goto fail;
1125         }
1126 
1127         dev->irq = platform_get_irq_byname(pdev, "irq");
1128 
1129         dev->netdev_ops = &cpmac_netdev_ops;
1130         dev->ethtool_ops = &cpmac_ethtool_ops;
1131 
1132         netif_napi_add(dev, &priv->napi, cpmac_poll, 64);
1133 
1134         spin_lock_init(&priv->lock);
1135         spin_lock_init(&priv->rx_lock);
1136         priv->dev = dev;
1137         priv->ring_size = 64;
1138         priv->msg_enable = netif_msg_init(debug_level, 0xff);
1139         memcpy(dev->dev_addr, pdata->dev_addr, sizeof(pdata->dev_addr));
1140 
1141         snprintf(priv->phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT,
1142                                                 mdio_bus_id, phy_id);
1143 
1144         phydev = phy_connect(dev, priv->phy_name, cpmac_adjust_link,
1145                              PHY_INTERFACE_MODE_MII);
1146 
1147         if (IS_ERR(phydev)) {
1148                 if (netif_msg_drv(priv))
1149                         dev_err(&pdev->dev, "Could not attach to PHY\n");
1150 
1151                 rc = PTR_ERR(phydev);
1152                 goto fail;
1153         }
1154 
1155         rc = register_netdev(dev);
1156         if (rc) {
1157                 dev_err(&pdev->dev, "Could not register net device\n");
1158                 goto fail;
1159         }
1160 
1161         if (netif_msg_probe(priv)) {
1162                 dev_info(&pdev->dev, "regs: %p, irq: %d, phy: %s, "
1163                          "mac: %pM\n", (void *)mem->start, dev->irq,
1164                          priv->phy_name, dev->dev_addr);
1165         }
1166 
1167         return 0;
1168 
1169 fail:
1170         free_netdev(dev);
1171         return rc;
1172 }
1173 
1174 static int cpmac_remove(struct platform_device *pdev)
1175 {
1176         struct net_device *dev = platform_get_drvdata(pdev);
1177 
1178         unregister_netdev(dev);
1179         free_netdev(dev);
1180 
1181         return 0;
1182 }
1183 
1184 static struct platform_driver cpmac_driver = {
1185         .driver = {
1186                 .name   = "cpmac",
1187         },
1188         .probe  = cpmac_probe,
1189         .remove = cpmac_remove,
1190 };
1191 
1192 int cpmac_init(void)
1193 {
1194         u32 mask;
1195         int i, res;
1196 
1197         cpmac_mii = mdiobus_alloc();
1198         if (cpmac_mii == NULL)
1199                 return -ENOMEM;
1200 
1201         cpmac_mii->name = "cpmac-mii";
1202         cpmac_mii->read = cpmac_mdio_read;
1203         cpmac_mii->write = cpmac_mdio_write;
1204         cpmac_mii->reset = cpmac_mdio_reset;
1205 
1206         cpmac_mii->priv = ioremap(AR7_REGS_MDIO, 256);
1207 
1208         if (!cpmac_mii->priv) {
1209                 pr_err("Can't ioremap mdio registers\n");
1210                 res = -ENXIO;
1211                 goto fail_alloc;
1212         }
1213 
1214 #warning FIXME: unhardcode gpio&reset bits
1215         ar7_gpio_disable(26);
1216         ar7_gpio_disable(27);
1217         ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);
1218         ar7_device_reset(AR7_RESET_BIT_CPMAC_HI);
1219         ar7_device_reset(AR7_RESET_BIT_EPHY);
1220 
1221         cpmac_mii->reset(cpmac_mii);
1222 
1223         for (i = 0; i < 300; i++) {
1224                 mask = cpmac_read(cpmac_mii->priv, CPMAC_MDIO_ALIVE);
1225                 if (mask)
1226                         break;
1227                 else
1228                         msleep(10);
1229         }
1230 
1231         mask &= 0x7fffffff;
1232         if (mask & (mask - 1)) {
1233                 external_switch = 1;
1234                 mask = 0;
1235         }
1236 
1237         cpmac_mii->phy_mask = ~(mask | 0x80000000);
1238         snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "cpmac-1");
1239 
1240         res = mdiobus_register(cpmac_mii);
1241         if (res)
1242                 goto fail_mii;
1243 
1244         res = platform_driver_register(&cpmac_driver);
1245         if (res)
1246                 goto fail_cpmac;
1247 
1248         return 0;
1249 
1250 fail_cpmac:
1251         mdiobus_unregister(cpmac_mii);
1252 
1253 fail_mii:
1254         iounmap(cpmac_mii->priv);
1255 
1256 fail_alloc:
1257         mdiobus_free(cpmac_mii);
1258 
1259         return res;
1260 }
1261 
1262 void cpmac_exit(void)
1263 {
1264         platform_driver_unregister(&cpmac_driver);
1265         mdiobus_unregister(cpmac_mii);
1266         iounmap(cpmac_mii->priv);
1267         mdiobus_free(cpmac_mii);
1268 }
1269 
1270 module_init(cpmac_init);
1271 module_exit(cpmac_exit);
1272 

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