Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4

Linux/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

  1 /*******************************************************************************
  2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
  3   ST Ethernet IPs are built around a Synopsys IP Core.
  4 
  5         Copyright(C) 2007-2011 STMicroelectronics Ltd
  6 
  7   This program is free software; you can redistribute it and/or modify it
  8   under the terms and conditions of the GNU General Public License,
  9   version 2, as published by the Free Software Foundation.
 10 
 11   This program is distributed in the hope it will be useful, but WITHOUT
 12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 14   more details.
 15 
 16   You should have received a copy of the GNU General Public License along with
 17   this program; if not, write to the Free Software Foundation, Inc.,
 18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 19 
 20   The full GNU General Public License is included in this distribution in
 21   the file called "COPYING".
 22 
 23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
 24 
 25   Documentation available at:
 26         http://www.stlinux.com
 27   Support available at:
 28         https://bugzilla.stlinux.com/
 29 *******************************************************************************/
 30 
 31 #include <linux/clk.h>
 32 #include <linux/kernel.h>
 33 #include <linux/interrupt.h>
 34 #include <linux/ip.h>
 35 #include <linux/tcp.h>
 36 #include <linux/skbuff.h>
 37 #include <linux/ethtool.h>
 38 #include <linux/if_ether.h>
 39 #include <linux/crc32.h>
 40 #include <linux/mii.h>
 41 #include <linux/if.h>
 42 #include <linux/if_vlan.h>
 43 #include <linux/dma-mapping.h>
 44 #include <linux/slab.h>
 45 #include <linux/prefetch.h>
 46 #include <linux/pinctrl/consumer.h>
 47 #ifdef CONFIG_DEBUG_FS
 48 #include <linux/debugfs.h>
 49 #include <linux/seq_file.h>
 50 #endif /* CONFIG_DEBUG_FS */
 51 #include <linux/net_tstamp.h>
 52 #include "stmmac_ptp.h"
 53 #include "stmmac.h"
 54 #include <linux/reset.h>
 55 #include <linux/of_mdio.h>
 56 
 57 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
 58 
 59 /* Module parameters */
 60 #define TX_TIMEO        5000
 61 static int watchdog = TX_TIMEO;
 62 module_param(watchdog, int, S_IRUGO | S_IWUSR);
 63 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
 64 
 65 static int debug = -1;
 66 module_param(debug, int, S_IRUGO | S_IWUSR);
 67 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
 68 
 69 static int phyaddr = -1;
 70 module_param(phyaddr, int, S_IRUGO);
 71 MODULE_PARM_DESC(phyaddr, "Physical device address");
 72 
 73 #define DMA_TX_SIZE 256
 74 static int dma_txsize = DMA_TX_SIZE;
 75 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
 76 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
 77 
 78 #define DMA_RX_SIZE 256
 79 static int dma_rxsize = DMA_RX_SIZE;
 80 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
 81 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
 82 
 83 static int flow_ctrl = FLOW_OFF;
 84 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
 85 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
 86 
 87 static int pause = PAUSE_TIME;
 88 module_param(pause, int, S_IRUGO | S_IWUSR);
 89 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
 90 
 91 #define TC_DEFAULT 64
 92 static int tc = TC_DEFAULT;
 93 module_param(tc, int, S_IRUGO | S_IWUSR);
 94 MODULE_PARM_DESC(tc, "DMA threshold control value");
 95 
 96 #define DEFAULT_BUFSIZE 1536
 97 static int buf_sz = DEFAULT_BUFSIZE;
 98 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
 99 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
100 
101 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
102                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
103                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
104 
105 #define STMMAC_DEFAULT_LPI_TIMER        1000
106 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
107 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
108 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
109 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
110 
111 /* By default the driver will use the ring mode to manage tx and rx descriptors
112  * but passing this value so user can force to use the chain instead of the ring
113  */
114 static unsigned int chain_mode;
115 module_param(chain_mode, int, S_IRUGO);
116 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
117 
118 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
119 
120 #ifdef CONFIG_DEBUG_FS
121 static int stmmac_init_fs(struct net_device *dev);
122 static void stmmac_exit_fs(struct net_device *dev);
123 #endif
124 
125 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
126 
127 /**
128  * stmmac_verify_args - verify the driver parameters.
129  * Description: it checks the driver parameters and set a default in case of
130  * errors.
131  */
132 static void stmmac_verify_args(void)
133 {
134         if (unlikely(watchdog < 0))
135                 watchdog = TX_TIMEO;
136         if (unlikely(dma_rxsize < 0))
137                 dma_rxsize = DMA_RX_SIZE;
138         if (unlikely(dma_txsize < 0))
139                 dma_txsize = DMA_TX_SIZE;
140         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
141                 buf_sz = DEFAULT_BUFSIZE;
142         if (unlikely(flow_ctrl > 1))
143                 flow_ctrl = FLOW_AUTO;
144         else if (likely(flow_ctrl < 0))
145                 flow_ctrl = FLOW_OFF;
146         if (unlikely((pause < 0) || (pause > 0xffff)))
147                 pause = PAUSE_TIME;
148         if (eee_timer < 0)
149                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
150 }
151 
152 /**
153  * stmmac_clk_csr_set - dynamically set the MDC clock
154  * @priv: driver private structure
155  * Description: this is to dynamically set the MDC clock according to the csr
156  * clock input.
157  * Note:
158  *      If a specific clk_csr value is passed from the platform
159  *      this means that the CSR Clock Range selection cannot be
160  *      changed at run-time and it is fixed (as reported in the driver
161  *      documentation). Viceversa the driver will try to set the MDC
162  *      clock dynamically according to the actual clock input.
163  */
164 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
165 {
166         u32 clk_rate;
167 
168         clk_rate = clk_get_rate(priv->stmmac_clk);
169 
170         /* Platform provided default clk_csr would be assumed valid
171          * for all other cases except for the below mentioned ones.
172          * For values higher than the IEEE 802.3 specified frequency
173          * we can not estimate the proper divider as it is not known
174          * the frequency of clk_csr_i. So we do not change the default
175          * divider.
176          */
177         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
178                 if (clk_rate < CSR_F_35M)
179                         priv->clk_csr = STMMAC_CSR_20_35M;
180                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
181                         priv->clk_csr = STMMAC_CSR_35_60M;
182                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
183                         priv->clk_csr = STMMAC_CSR_60_100M;
184                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
185                         priv->clk_csr = STMMAC_CSR_100_150M;
186                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
187                         priv->clk_csr = STMMAC_CSR_150_250M;
188                 else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))
189                         priv->clk_csr = STMMAC_CSR_250_300M;
190         }
191 }
192 
193 static void print_pkt(unsigned char *buf, int len)
194 {
195         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
196         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
197 }
198 
199 /* minimum number of free TX descriptors required to wake up TX process */
200 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
201 
202 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
203 {
204         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
205 }
206 
207 /**
208  * stmmac_hw_fix_mac_speed - callback for speed selection
209  * @priv: driver private structure
210  * Description: on some platforms (e.g. ST), some HW system configuraton
211  * registers have to be set according to the link speed negotiated.
212  */
213 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
214 {
215         struct phy_device *phydev = priv->phydev;
216 
217         if (likely(priv->plat->fix_mac_speed))
218                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
219 }
220 
221 /**
222  * stmmac_enable_eee_mode - check and enter in LPI mode
223  * @priv: driver private structure
224  * Description: this function is to verify and enter in LPI mode in case of
225  * EEE.
226  */
227 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
228 {
229         /* Check and enter in LPI mode */
230         if ((priv->dirty_tx == priv->cur_tx) &&
231             (priv->tx_path_in_lpi_mode == false))
232                 priv->hw->mac->set_eee_mode(priv->hw);
233 }
234 
235 /**
236  * stmmac_disable_eee_mode - disable and exit from LPI mode
237  * @priv: driver private structure
238  * Description: this function is to exit and disable EEE in case of
239  * LPI state is true. This is called by the xmit.
240  */
241 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
242 {
243         priv->hw->mac->reset_eee_mode(priv->hw);
244         del_timer_sync(&priv->eee_ctrl_timer);
245         priv->tx_path_in_lpi_mode = false;
246 }
247 
248 /**
249  * stmmac_eee_ctrl_timer - EEE TX SW timer.
250  * @arg : data hook
251  * Description:
252  *  if there is no data transfer and if we are not in LPI state,
253  *  then MAC Transmitter can be moved to LPI state.
254  */
255 static void stmmac_eee_ctrl_timer(unsigned long arg)
256 {
257         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
258 
259         stmmac_enable_eee_mode(priv);
260         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
261 }
262 
263 /**
264  * stmmac_eee_init - init EEE
265  * @priv: driver private structure
266  * Description:
267  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
268  *  can also manage EEE, this function enable the LPI state and start related
269  *  timer.
270  */
271 bool stmmac_eee_init(struct stmmac_priv *priv)
272 {
273         char *phy_bus_name = priv->plat->phy_bus_name;
274         unsigned long flags;
275         bool ret = false;
276 
277         /* Using PCS we cannot dial with the phy registers at this stage
278          * so we do not support extra feature like EEE.
279          */
280         if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
281             (priv->pcs == STMMAC_PCS_RTBI))
282                 goto out;
283 
284         /* Never init EEE in case of a switch is attached */
285         if (phy_bus_name && (!strcmp(phy_bus_name, "fixed")))
286                 goto out;
287 
288         /* MAC core supports the EEE feature. */
289         if (priv->dma_cap.eee) {
290                 int tx_lpi_timer = priv->tx_lpi_timer;
291 
292                 /* Check if the PHY supports EEE */
293                 if (phy_init_eee(priv->phydev, 1)) {
294                         /* To manage at run-time if the EEE cannot be supported
295                          * anymore (for example because the lp caps have been
296                          * changed).
297                          * In that case the driver disable own timers.
298                          */
299                         spin_lock_irqsave(&priv->lock, flags);
300                         if (priv->eee_active) {
301                                 pr_debug("stmmac: disable EEE\n");
302                                 del_timer_sync(&priv->eee_ctrl_timer);
303                                 priv->hw->mac->set_eee_timer(priv->hw, 0,
304                                                              tx_lpi_timer);
305                         }
306                         priv->eee_active = 0;
307                         spin_unlock_irqrestore(&priv->lock, flags);
308                         goto out;
309                 }
310                 /* Activate the EEE and start timers */
311                 spin_lock_irqsave(&priv->lock, flags);
312                 if (!priv->eee_active) {
313                         priv->eee_active = 1;
314                         setup_timer(&priv->eee_ctrl_timer,
315                                     stmmac_eee_ctrl_timer,
316                                     (unsigned long)priv);
317                         mod_timer(&priv->eee_ctrl_timer,
318                                   STMMAC_LPI_T(eee_timer));
319 
320                         priv->hw->mac->set_eee_timer(priv->hw,
321                                                      STMMAC_DEFAULT_LIT_LS,
322                                                      tx_lpi_timer);
323                 }
324                 /* Set HW EEE according to the speed */
325                 priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link);
326 
327                 ret = true;
328                 spin_unlock_irqrestore(&priv->lock, flags);
329 
330                 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
331         }
332 out:
333         return ret;
334 }
335 
336 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
337  * @priv: driver private structure
338  * @entry : descriptor index to be used.
339  * @skb : the socket buffer
340  * Description :
341  * This function will read timestamp from the descriptor & pass it to stack.
342  * and also perform some sanity checks.
343  */
344 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
345                                    unsigned int entry, struct sk_buff *skb)
346 {
347         struct skb_shared_hwtstamps shhwtstamp;
348         u64 ns;
349         void *desc = NULL;
350 
351         if (!priv->hwts_tx_en)
352                 return;
353 
354         /* exit if skb doesn't support hw tstamp */
355         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
356                 return;
357 
358         if (priv->adv_ts)
359                 desc = (priv->dma_etx + entry);
360         else
361                 desc = (priv->dma_tx + entry);
362 
363         /* check tx tstamp status */
364         if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
365                 return;
366 
367         /* get the valid tstamp */
368         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
369 
370         memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
371         shhwtstamp.hwtstamp = ns_to_ktime(ns);
372         /* pass tstamp to stack */
373         skb_tstamp_tx(skb, &shhwtstamp);
374 
375         return;
376 }
377 
378 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
379  * @priv: driver private structure
380  * @entry : descriptor index to be used.
381  * @skb : the socket buffer
382  * Description :
383  * This function will read received packet's timestamp from the descriptor
384  * and pass it to stack. It also perform some sanity checks.
385  */
386 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
387                                    unsigned int entry, struct sk_buff *skb)
388 {
389         struct skb_shared_hwtstamps *shhwtstamp = NULL;
390         u64 ns;
391         void *desc = NULL;
392 
393         if (!priv->hwts_rx_en)
394                 return;
395 
396         if (priv->adv_ts)
397                 desc = (priv->dma_erx + entry);
398         else
399                 desc = (priv->dma_rx + entry);
400 
401         /* exit if rx tstamp is not valid */
402         if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
403                 return;
404 
405         /* get valid tstamp */
406         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
407         shhwtstamp = skb_hwtstamps(skb);
408         memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
409         shhwtstamp->hwtstamp = ns_to_ktime(ns);
410 }
411 
412 /**
413  *  stmmac_hwtstamp_ioctl - control hardware timestamping.
414  *  @dev: device pointer.
415  *  @ifr: An IOCTL specefic structure, that can contain a pointer to
416  *  a proprietary structure used to pass information to the driver.
417  *  Description:
418  *  This function configures the MAC to enable/disable both outgoing(TX)
419  *  and incoming(RX) packets time stamping based on user input.
420  *  Return Value:
421  *  0 on success and an appropriate -ve integer on failure.
422  */
423 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
424 {
425         struct stmmac_priv *priv = netdev_priv(dev);
426         struct hwtstamp_config config;
427         struct timespec64 now;
428         u64 temp = 0;
429         u32 ptp_v2 = 0;
430         u32 tstamp_all = 0;
431         u32 ptp_over_ipv4_udp = 0;
432         u32 ptp_over_ipv6_udp = 0;
433         u32 ptp_over_ethernet = 0;
434         u32 snap_type_sel = 0;
435         u32 ts_master_en = 0;
436         u32 ts_event_en = 0;
437         u32 value = 0;
438 
439         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
440                 netdev_alert(priv->dev, "No support for HW time stamping\n");
441                 priv->hwts_tx_en = 0;
442                 priv->hwts_rx_en = 0;
443 
444                 return -EOPNOTSUPP;
445         }
446 
447         if (copy_from_user(&config, ifr->ifr_data,
448                            sizeof(struct hwtstamp_config)))
449                 return -EFAULT;
450 
451         pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
452                  __func__, config.flags, config.tx_type, config.rx_filter);
453 
454         /* reserved for future extensions */
455         if (config.flags)
456                 return -EINVAL;
457 
458         if (config.tx_type != HWTSTAMP_TX_OFF &&
459             config.tx_type != HWTSTAMP_TX_ON)
460                 return -ERANGE;
461 
462         if (priv->adv_ts) {
463                 switch (config.rx_filter) {
464                 case HWTSTAMP_FILTER_NONE:
465                         /* time stamp no incoming packet at all */
466                         config.rx_filter = HWTSTAMP_FILTER_NONE;
467                         break;
468 
469                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
470                         /* PTP v1, UDP, any kind of event packet */
471                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
472                         /* take time stamp for all event messages */
473                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
474 
475                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
476                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
477                         break;
478 
479                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
480                         /* PTP v1, UDP, Sync packet */
481                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
482                         /* take time stamp for SYNC messages only */
483                         ts_event_en = PTP_TCR_TSEVNTENA;
484 
485                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
486                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
487                         break;
488 
489                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
490                         /* PTP v1, UDP, Delay_req packet */
491                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
492                         /* take time stamp for Delay_Req messages only */
493                         ts_master_en = PTP_TCR_TSMSTRENA;
494                         ts_event_en = PTP_TCR_TSEVNTENA;
495 
496                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
497                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
498                         break;
499 
500                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
501                         /* PTP v2, UDP, any kind of event packet */
502                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
503                         ptp_v2 = PTP_TCR_TSVER2ENA;
504                         /* take time stamp for all event messages */
505                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
506 
507                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
508                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
509                         break;
510 
511                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
512                         /* PTP v2, UDP, Sync packet */
513                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
514                         ptp_v2 = PTP_TCR_TSVER2ENA;
515                         /* take time stamp for SYNC messages only */
516                         ts_event_en = PTP_TCR_TSEVNTENA;
517 
518                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
519                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
520                         break;
521 
522                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
523                         /* PTP v2, UDP, Delay_req packet */
524                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
525                         ptp_v2 = PTP_TCR_TSVER2ENA;
526                         /* take time stamp for Delay_Req messages only */
527                         ts_master_en = PTP_TCR_TSMSTRENA;
528                         ts_event_en = PTP_TCR_TSEVNTENA;
529 
530                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
531                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
532                         break;
533 
534                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
535                         /* PTP v2/802.AS1 any layer, any kind of event packet */
536                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
537                         ptp_v2 = PTP_TCR_TSVER2ENA;
538                         /* take time stamp for all event messages */
539                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
540 
541                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
542                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
543                         ptp_over_ethernet = PTP_TCR_TSIPENA;
544                         break;
545 
546                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
547                         /* PTP v2/802.AS1, any layer, Sync packet */
548                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
549                         ptp_v2 = PTP_TCR_TSVER2ENA;
550                         /* take time stamp for SYNC messages only */
551                         ts_event_en = PTP_TCR_TSEVNTENA;
552 
553                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
554                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
555                         ptp_over_ethernet = PTP_TCR_TSIPENA;
556                         break;
557 
558                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
559                         /* PTP v2/802.AS1, any layer, Delay_req packet */
560                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
561                         ptp_v2 = PTP_TCR_TSVER2ENA;
562                         /* take time stamp for Delay_Req messages only */
563                         ts_master_en = PTP_TCR_TSMSTRENA;
564                         ts_event_en = PTP_TCR_TSEVNTENA;
565 
566                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
567                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
568                         ptp_over_ethernet = PTP_TCR_TSIPENA;
569                         break;
570 
571                 case HWTSTAMP_FILTER_ALL:
572                         /* time stamp any incoming packet */
573                         config.rx_filter = HWTSTAMP_FILTER_ALL;
574                         tstamp_all = PTP_TCR_TSENALL;
575                         break;
576 
577                 default:
578                         return -ERANGE;
579                 }
580         } else {
581                 switch (config.rx_filter) {
582                 case HWTSTAMP_FILTER_NONE:
583                         config.rx_filter = HWTSTAMP_FILTER_NONE;
584                         break;
585                 default:
586                         /* PTP v1, UDP, any kind of event packet */
587                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
588                         break;
589                 }
590         }
591         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
592         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
593 
594         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
595                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
596         else {
597                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
598                          tstamp_all | ptp_v2 | ptp_over_ethernet |
599                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
600                          ts_master_en | snap_type_sel);
601 
602                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
603 
604                 /* program Sub Second Increment reg */
605                 priv->hw->ptp->config_sub_second_increment(priv->ioaddr);
606 
607                 /* calculate default added value:
608                  * formula is :
609                  * addend = (2^32)/freq_div_ratio;
610                  * where, freq_div_ratio = clk_ptp_ref_i/50MHz
611                  * hence, addend = ((2^32) * 50MHz)/clk_ptp_ref_i;
612                  * NOTE: clk_ptp_ref_i should be >= 50MHz to
613                  *       achieve 20ns accuracy.
614                  *
615                  * 2^x * y == (y << x), hence
616                  * 2^32 * 50000000 ==> (50000000 << 32)
617                  */
618                 temp = (u64) (50000000ULL << 32);
619                 priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
620                 priv->hw->ptp->config_addend(priv->ioaddr,
621                                              priv->default_addend);
622 
623                 /* initialize system time */
624                 ktime_get_real_ts64(&now);
625 
626                 /* lower 32 bits of tv_sec are safe until y2106 */
627                 priv->hw->ptp->init_systime(priv->ioaddr, (u32)now.tv_sec,
628                                             now.tv_nsec);
629         }
630 
631         return copy_to_user(ifr->ifr_data, &config,
632                             sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
633 }
634 
635 /**
636  * stmmac_init_ptp - init PTP
637  * @priv: driver private structure
638  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
639  * This is done by looking at the HW cap. register.
640  * This function also registers the ptp driver.
641  */
642 static int stmmac_init_ptp(struct stmmac_priv *priv)
643 {
644         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
645                 return -EOPNOTSUPP;
646 
647         /* Fall-back to main clock in case of no PTP ref is passed */
648         priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref");
649         if (IS_ERR(priv->clk_ptp_ref)) {
650                 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk);
651                 priv->clk_ptp_ref = NULL;
652         } else {
653                 clk_prepare_enable(priv->clk_ptp_ref);
654                 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref);
655         }
656 
657         priv->adv_ts = 0;
658         if (priv->dma_cap.atime_stamp && priv->extend_desc)
659                 priv->adv_ts = 1;
660 
661         if (netif_msg_hw(priv) && priv->dma_cap.time_stamp)
662                 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
663 
664         if (netif_msg_hw(priv) && priv->adv_ts)
665                 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
666 
667         priv->hw->ptp = &stmmac_ptp;
668         priv->hwts_tx_en = 0;
669         priv->hwts_rx_en = 0;
670 
671         return stmmac_ptp_register(priv);
672 }
673 
674 static void stmmac_release_ptp(struct stmmac_priv *priv)
675 {
676         if (priv->clk_ptp_ref)
677                 clk_disable_unprepare(priv->clk_ptp_ref);
678         stmmac_ptp_unregister(priv);
679 }
680 
681 /**
682  * stmmac_adjust_link - adjusts the link parameters
683  * @dev: net device structure
684  * Description: this is the helper called by the physical abstraction layer
685  * drivers to communicate the phy link status. According the speed and duplex
686  * this driver can invoke registered glue-logic as well.
687  * It also invoke the eee initialization because it could happen when switch
688  * on different networks (that are eee capable).
689  */
690 static void stmmac_adjust_link(struct net_device *dev)
691 {
692         struct stmmac_priv *priv = netdev_priv(dev);
693         struct phy_device *phydev = priv->phydev;
694         unsigned long flags;
695         int new_state = 0;
696         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
697 
698         if (phydev == NULL)
699                 return;
700 
701         spin_lock_irqsave(&priv->lock, flags);
702 
703         if (phydev->link) {
704                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
705 
706                 /* Now we make sure that we can be in full duplex mode.
707                  * If not, we operate in half-duplex mode. */
708                 if (phydev->duplex != priv->oldduplex) {
709                         new_state = 1;
710                         if (!(phydev->duplex))
711                                 ctrl &= ~priv->hw->link.duplex;
712                         else
713                                 ctrl |= priv->hw->link.duplex;
714                         priv->oldduplex = phydev->duplex;
715                 }
716                 /* Flow Control operation */
717                 if (phydev->pause)
718                         priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex,
719                                                  fc, pause_time);
720 
721                 if (phydev->speed != priv->speed) {
722                         new_state = 1;
723                         switch (phydev->speed) {
724                         case 1000:
725                                 if (likely(priv->plat->has_gmac))
726                                         ctrl &= ~priv->hw->link.port;
727                                 stmmac_hw_fix_mac_speed(priv);
728                                 break;
729                         case 100:
730                         case 10:
731                                 if (priv->plat->has_gmac) {
732                                         ctrl |= priv->hw->link.port;
733                                         if (phydev->speed == SPEED_100) {
734                                                 ctrl |= priv->hw->link.speed;
735                                         } else {
736                                                 ctrl &= ~(priv->hw->link.speed);
737                                         }
738                                 } else {
739                                         ctrl &= ~priv->hw->link.port;
740                                 }
741                                 stmmac_hw_fix_mac_speed(priv);
742                                 break;
743                         default:
744                                 if (netif_msg_link(priv))
745                                         pr_warn("%s: Speed (%d) not 10/100\n",
746                                                 dev->name, phydev->speed);
747                                 break;
748                         }
749 
750                         priv->speed = phydev->speed;
751                 }
752 
753                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
754 
755                 if (!priv->oldlink) {
756                         new_state = 1;
757                         priv->oldlink = 1;
758                 }
759         } else if (priv->oldlink) {
760                 new_state = 1;
761                 priv->oldlink = 0;
762                 priv->speed = 0;
763                 priv->oldduplex = -1;
764         }
765 
766         if (new_state && netif_msg_link(priv))
767                 phy_print_status(phydev);
768 
769         spin_unlock_irqrestore(&priv->lock, flags);
770 
771         /* At this stage, it could be needed to setup the EEE or adjust some
772          * MAC related HW registers.
773          */
774         priv->eee_enabled = stmmac_eee_init(priv);
775 }
776 
777 /**
778  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
779  * @priv: driver private structure
780  * Description: this is to verify if the HW supports the PCS.
781  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
782  * configured for the TBI, RTBI, or SGMII PHY interface.
783  */
784 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
785 {
786         int interface = priv->plat->interface;
787 
788         if (priv->dma_cap.pcs) {
789                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
790                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
791                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
792                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
793                         pr_debug("STMMAC: PCS RGMII support enable\n");
794                         priv->pcs = STMMAC_PCS_RGMII;
795                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
796                         pr_debug("STMMAC: PCS SGMII support enable\n");
797                         priv->pcs = STMMAC_PCS_SGMII;
798                 }
799         }
800 }
801 
802 /**
803  * stmmac_init_phy - PHY initialization
804  * @dev: net device structure
805  * Description: it initializes the driver's PHY state, and attaches the PHY
806  * to the mac driver.
807  *  Return value:
808  *  0 on success
809  */
810 static int stmmac_init_phy(struct net_device *dev)
811 {
812         struct stmmac_priv *priv = netdev_priv(dev);
813         struct phy_device *phydev;
814         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
815         char bus_id[MII_BUS_ID_SIZE];
816         int interface = priv->plat->interface;
817         int max_speed = priv->plat->max_speed;
818         priv->oldlink = 0;
819         priv->speed = 0;
820         priv->oldduplex = -1;
821 
822         if (priv->plat->phy_node) {
823                 phydev = of_phy_connect(dev, priv->plat->phy_node,
824                                         &stmmac_adjust_link, 0, interface);
825         } else {
826                 if (priv->plat->phy_bus_name)
827                         snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
828                                  priv->plat->phy_bus_name, priv->plat->bus_id);
829                 else
830                         snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
831                                  priv->plat->bus_id);
832 
833                 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
834                          priv->plat->phy_addr);
835                 pr_debug("stmmac_init_phy:  trying to attach to %s\n",
836                          phy_id_fmt);
837 
838                 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
839                                      interface);
840         }
841 
842         if (IS_ERR_OR_NULL(phydev)) {
843                 pr_err("%s: Could not attach to PHY\n", dev->name);
844                 if (!phydev)
845                         return -ENODEV;
846 
847                 return PTR_ERR(phydev);
848         }
849 
850         /* Stop Advertising 1000BASE Capability if interface is not GMII */
851         if ((interface == PHY_INTERFACE_MODE_MII) ||
852             (interface == PHY_INTERFACE_MODE_RMII) ||
853                 (max_speed < 1000 && max_speed > 0))
854                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
855                                          SUPPORTED_1000baseT_Full);
856 
857         /*
858          * Broken HW is sometimes missing the pull-up resistor on the
859          * MDIO line, which results in reads to non-existent devices returning
860          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
861          * device as well.
862          * Note: phydev->phy_id is the result of reading the UID PHY registers.
863          */
864         if (!priv->plat->phy_node && phydev->phy_id == 0) {
865                 phy_disconnect(phydev);
866                 return -ENODEV;
867         }
868         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
869                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
870 
871         priv->phydev = phydev;
872 
873         return 0;
874 }
875 
876 /**
877  * stmmac_display_ring - display ring
878  * @head: pointer to the head of the ring passed.
879  * @size: size of the ring.
880  * @extend_desc: to verify if extended descriptors are used.
881  * Description: display the control/status and buffer descriptors.
882  */
883 static void stmmac_display_ring(void *head, int size, int extend_desc)
884 {
885         int i;
886         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
887         struct dma_desc *p = (struct dma_desc *)head;
888 
889         for (i = 0; i < size; i++) {
890                 u64 x;
891                 if (extend_desc) {
892                         x = *(u64 *) ep;
893                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
894                                 i, (unsigned int)virt_to_phys(ep),
895                                 (unsigned int)x, (unsigned int)(x >> 32),
896                                 ep->basic.des2, ep->basic.des3);
897                         ep++;
898                 } else {
899                         x = *(u64 *) p;
900                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
901                                 i, (unsigned int)virt_to_phys(p),
902                                 (unsigned int)x, (unsigned int)(x >> 32),
903                                 p->des2, p->des3);
904                         p++;
905                 }
906                 pr_info("\n");
907         }
908 }
909 
910 static void stmmac_display_rings(struct stmmac_priv *priv)
911 {
912         unsigned int txsize = priv->dma_tx_size;
913         unsigned int rxsize = priv->dma_rx_size;
914 
915         if (priv->extend_desc) {
916                 pr_info("Extended RX descriptor ring:\n");
917                 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
918                 pr_info("Extended TX descriptor ring:\n");
919                 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
920         } else {
921                 pr_info("RX descriptor ring:\n");
922                 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
923                 pr_info("TX descriptor ring:\n");
924                 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
925         }
926 }
927 
928 static int stmmac_set_bfsize(int mtu, int bufsize)
929 {
930         int ret = bufsize;
931 
932         if (mtu >= BUF_SIZE_4KiB)
933                 ret = BUF_SIZE_8KiB;
934         else if (mtu >= BUF_SIZE_2KiB)
935                 ret = BUF_SIZE_4KiB;
936         else if (mtu > DEFAULT_BUFSIZE)
937                 ret = BUF_SIZE_2KiB;
938         else
939                 ret = DEFAULT_BUFSIZE;
940 
941         return ret;
942 }
943 
944 /**
945  * stmmac_clear_descriptors - clear descriptors
946  * @priv: driver private structure
947  * Description: this function is called to clear the tx and rx descriptors
948  * in case of both basic and extended descriptors are used.
949  */
950 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
951 {
952         int i;
953         unsigned int txsize = priv->dma_tx_size;
954         unsigned int rxsize = priv->dma_rx_size;
955 
956         /* Clear the Rx/Tx descriptors */
957         for (i = 0; i < rxsize; i++)
958                 if (priv->extend_desc)
959                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
960                                                      priv->use_riwt, priv->mode,
961                                                      (i == rxsize - 1));
962                 else
963                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
964                                                      priv->use_riwt, priv->mode,
965                                                      (i == rxsize - 1));
966         for (i = 0; i < txsize; i++)
967                 if (priv->extend_desc)
968                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
969                                                      priv->mode,
970                                                      (i == txsize - 1));
971                 else
972                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
973                                                      priv->mode,
974                                                      (i == txsize - 1));
975 }
976 
977 /**
978  * stmmac_init_rx_buffers - init the RX descriptor buffer.
979  * @priv: driver private structure
980  * @p: descriptor pointer
981  * @i: descriptor index
982  * @flags: gfp flag.
983  * Description: this function is called to allocate a receive buffer, perform
984  * the DMA mapping and init the descriptor.
985  */
986 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
987                                   int i, gfp_t flags)
988 {
989         struct sk_buff *skb;
990 
991         skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
992         if (!skb) {
993                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
994                 return -ENOMEM;
995         }
996         priv->rx_skbuff[i] = skb;
997         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
998                                                 priv->dma_buf_sz,
999                                                 DMA_FROM_DEVICE);
1000         if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
1001                 pr_err("%s: DMA mapping error\n", __func__);
1002                 dev_kfree_skb_any(skb);
1003                 return -EINVAL;
1004         }
1005 
1006         p->des2 = priv->rx_skbuff_dma[i];
1007 
1008         if ((priv->hw->mode->init_desc3) &&
1009             (priv->dma_buf_sz == BUF_SIZE_16KiB))
1010                 priv->hw->mode->init_desc3(p);
1011 
1012         return 0;
1013 }
1014 
1015 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
1016 {
1017         if (priv->rx_skbuff[i]) {
1018                 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1019                                  priv->dma_buf_sz, DMA_FROM_DEVICE);
1020                 dev_kfree_skb_any(priv->rx_skbuff[i]);
1021         }
1022         priv->rx_skbuff[i] = NULL;
1023 }
1024 
1025 /**
1026  * init_dma_desc_rings - init the RX/TX descriptor rings
1027  * @dev: net device structure
1028  * @flags: gfp flag.
1029  * Description: this function initializes the DMA RX/TX descriptors
1030  * and allocates the socket buffers. It suppors the chained and ring
1031  * modes.
1032  */
1033 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1034 {
1035         int i;
1036         struct stmmac_priv *priv = netdev_priv(dev);
1037         unsigned int txsize = priv->dma_tx_size;
1038         unsigned int rxsize = priv->dma_rx_size;
1039         unsigned int bfsize = 0;
1040         int ret = -ENOMEM;
1041 
1042         if (priv->hw->mode->set_16kib_bfsize)
1043                 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1044 
1045         if (bfsize < BUF_SIZE_16KiB)
1046                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1047 
1048         priv->dma_buf_sz = bfsize;
1049 
1050         if (netif_msg_probe(priv))
1051                 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__,
1052                          txsize, rxsize, bfsize);
1053 
1054         if (netif_msg_probe(priv)) {
1055                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1056                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1057 
1058                 /* RX INITIALIZATION */
1059                 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1060         }
1061         for (i = 0; i < rxsize; i++) {
1062                 struct dma_desc *p;
1063                 if (priv->extend_desc)
1064                         p = &((priv->dma_erx + i)->basic);
1065                 else
1066                         p = priv->dma_rx + i;
1067 
1068                 ret = stmmac_init_rx_buffers(priv, p, i, flags);
1069                 if (ret)
1070                         goto err_init_rx_buffers;
1071 
1072                 if (netif_msg_probe(priv))
1073                         pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1074                                  priv->rx_skbuff[i]->data,
1075                                  (unsigned int)priv->rx_skbuff_dma[i]);
1076         }
1077         priv->cur_rx = 0;
1078         priv->dirty_rx = (unsigned int)(i - rxsize);
1079         buf_sz = bfsize;
1080 
1081         /* Setup the chained descriptor addresses */
1082         if (priv->mode == STMMAC_CHAIN_MODE) {
1083                 if (priv->extend_desc) {
1084                         priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1085                                              rxsize, 1);
1086                         priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1087                                              txsize, 1);
1088                 } else {
1089                         priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1090                                              rxsize, 0);
1091                         priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1092                                              txsize, 0);
1093                 }
1094         }
1095 
1096         /* TX INITIALIZATION */
1097         for (i = 0; i < txsize; i++) {
1098                 struct dma_desc *p;
1099                 if (priv->extend_desc)
1100                         p = &((priv->dma_etx + i)->basic);
1101                 else
1102                         p = priv->dma_tx + i;
1103                 p->des2 = 0;
1104                 priv->tx_skbuff_dma[i].buf = 0;
1105                 priv->tx_skbuff_dma[i].map_as_page = false;
1106                 priv->tx_skbuff[i] = NULL;
1107         }
1108 
1109         priv->dirty_tx = 0;
1110         priv->cur_tx = 0;
1111         netdev_reset_queue(priv->dev);
1112 
1113         stmmac_clear_descriptors(priv);
1114 
1115         if (netif_msg_hw(priv))
1116                 stmmac_display_rings(priv);
1117 
1118         return 0;
1119 err_init_rx_buffers:
1120         while (--i >= 0)
1121                 stmmac_free_rx_buffers(priv, i);
1122         return ret;
1123 }
1124 
1125 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1126 {
1127         int i;
1128 
1129         for (i = 0; i < priv->dma_rx_size; i++)
1130                 stmmac_free_rx_buffers(priv, i);
1131 }
1132 
1133 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1134 {
1135         int i;
1136 
1137         for (i = 0; i < priv->dma_tx_size; i++) {
1138                 struct dma_desc *p;
1139 
1140                 if (priv->extend_desc)
1141                         p = &((priv->dma_etx + i)->basic);
1142                 else
1143                         p = priv->dma_tx + i;
1144 
1145                 if (priv->tx_skbuff_dma[i].buf) {
1146                         if (priv->tx_skbuff_dma[i].map_as_page)
1147                                 dma_unmap_page(priv->device,
1148                                                priv->tx_skbuff_dma[i].buf,
1149                                                priv->hw->desc->get_tx_len(p),
1150                                                DMA_TO_DEVICE);
1151                         else
1152                                 dma_unmap_single(priv->device,
1153                                                  priv->tx_skbuff_dma[i].buf,
1154                                                  priv->hw->desc->get_tx_len(p),
1155                                                  DMA_TO_DEVICE);
1156                 }
1157 
1158                 if (priv->tx_skbuff[i] != NULL) {
1159                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1160                         priv->tx_skbuff[i] = NULL;
1161                         priv->tx_skbuff_dma[i].buf = 0;
1162                         priv->tx_skbuff_dma[i].map_as_page = false;
1163                 }
1164         }
1165 }
1166 
1167 /**
1168  * alloc_dma_desc_resources - alloc TX/RX resources.
1169  * @priv: private structure
1170  * Description: according to which descriptor can be used (extend or basic)
1171  * this function allocates the resources for TX and RX paths. In case of
1172  * reception, for example, it pre-allocated the RX socket buffer in order to
1173  * allow zero-copy mechanism.
1174  */
1175 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1176 {
1177         unsigned int txsize = priv->dma_tx_size;
1178         unsigned int rxsize = priv->dma_rx_size;
1179         int ret = -ENOMEM;
1180 
1181         priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
1182                                             GFP_KERNEL);
1183         if (!priv->rx_skbuff_dma)
1184                 return -ENOMEM;
1185 
1186         priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
1187                                         GFP_KERNEL);
1188         if (!priv->rx_skbuff)
1189                 goto err_rx_skbuff;
1190 
1191         priv->tx_skbuff_dma = kmalloc_array(txsize,
1192                                             sizeof(*priv->tx_skbuff_dma),
1193                                             GFP_KERNEL);
1194         if (!priv->tx_skbuff_dma)
1195                 goto err_tx_skbuff_dma;
1196 
1197         priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
1198                                         GFP_KERNEL);
1199         if (!priv->tx_skbuff)
1200                 goto err_tx_skbuff;
1201 
1202         if (priv->extend_desc) {
1203                 priv->dma_erx = dma_zalloc_coherent(priv->device, rxsize *
1204                                                     sizeof(struct
1205                                                            dma_extended_desc),
1206                                                     &priv->dma_rx_phy,
1207                                                     GFP_KERNEL);
1208                 if (!priv->dma_erx)
1209                         goto err_dma;
1210 
1211                 priv->dma_etx = dma_zalloc_coherent(priv->device, txsize *
1212                                                     sizeof(struct
1213                                                            dma_extended_desc),
1214                                                     &priv->dma_tx_phy,
1215                                                     GFP_KERNEL);
1216                 if (!priv->dma_etx) {
1217                         dma_free_coherent(priv->device, priv->dma_rx_size *
1218                                           sizeof(struct dma_extended_desc),
1219                                           priv->dma_erx, priv->dma_rx_phy);
1220                         goto err_dma;
1221                 }
1222         } else {
1223                 priv->dma_rx = dma_zalloc_coherent(priv->device, rxsize *
1224                                                    sizeof(struct dma_desc),
1225                                                    &priv->dma_rx_phy,
1226                                                    GFP_KERNEL);
1227                 if (!priv->dma_rx)
1228                         goto err_dma;
1229 
1230                 priv->dma_tx = dma_zalloc_coherent(priv->device, txsize *
1231                                                    sizeof(struct dma_desc),
1232                                                    &priv->dma_tx_phy,
1233                                                    GFP_KERNEL);
1234                 if (!priv->dma_tx) {
1235                         dma_free_coherent(priv->device, priv->dma_rx_size *
1236                                           sizeof(struct dma_desc),
1237                                           priv->dma_rx, priv->dma_rx_phy);
1238                         goto err_dma;
1239                 }
1240         }
1241 
1242         return 0;
1243 
1244 err_dma:
1245         kfree(priv->tx_skbuff);
1246 err_tx_skbuff:
1247         kfree(priv->tx_skbuff_dma);
1248 err_tx_skbuff_dma:
1249         kfree(priv->rx_skbuff);
1250 err_rx_skbuff:
1251         kfree(priv->rx_skbuff_dma);
1252         return ret;
1253 }
1254 
1255 static void free_dma_desc_resources(struct stmmac_priv *priv)
1256 {
1257         /* Release the DMA TX/RX socket buffers */
1258         dma_free_rx_skbufs(priv);
1259         dma_free_tx_skbufs(priv);
1260 
1261         /* Free DMA regions of consistent memory previously allocated */
1262         if (!priv->extend_desc) {
1263                 dma_free_coherent(priv->device,
1264                                   priv->dma_tx_size * sizeof(struct dma_desc),
1265                                   priv->dma_tx, priv->dma_tx_phy);
1266                 dma_free_coherent(priv->device,
1267                                   priv->dma_rx_size * sizeof(struct dma_desc),
1268                                   priv->dma_rx, priv->dma_rx_phy);
1269         } else {
1270                 dma_free_coherent(priv->device, priv->dma_tx_size *
1271                                   sizeof(struct dma_extended_desc),
1272                                   priv->dma_etx, priv->dma_tx_phy);
1273                 dma_free_coherent(priv->device, priv->dma_rx_size *
1274                                   sizeof(struct dma_extended_desc),
1275                                   priv->dma_erx, priv->dma_rx_phy);
1276         }
1277         kfree(priv->rx_skbuff_dma);
1278         kfree(priv->rx_skbuff);
1279         kfree(priv->tx_skbuff_dma);
1280         kfree(priv->tx_skbuff);
1281 }
1282 
1283 /**
1284  *  stmmac_dma_operation_mode - HW DMA operation mode
1285  *  @priv: driver private structure
1286  *  Description: it is used for configuring the DMA operation mode register in
1287  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1288  */
1289 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1290 {
1291         int rxfifosz = priv->plat->rx_fifo_size;
1292 
1293         if (priv->plat->force_thresh_dma_mode)
1294                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz);
1295         else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1296                 /*
1297                  * In case of GMAC, SF mode can be enabled
1298                  * to perform the TX COE in HW. This depends on:
1299                  * 1) TX COE if actually supported
1300                  * 2) There is no bugged Jumbo frame support
1301                  *    that needs to not insert csum in the TDES.
1302                  */
1303                 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE,
1304                                         rxfifosz);
1305                 priv->xstats.threshold = SF_DMA_MODE;
1306         } else
1307                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE,
1308                                         rxfifosz);
1309 }
1310 
1311 /**
1312  * stmmac_tx_clean - to manage the transmission completion
1313  * @priv: driver private structure
1314  * Description: it reclaims the transmit resources after transmission completes.
1315  */
1316 static void stmmac_tx_clean(struct stmmac_priv *priv)
1317 {
1318         unsigned int txsize = priv->dma_tx_size;
1319         unsigned int bytes_compl = 0, pkts_compl = 0;
1320 
1321         spin_lock(&priv->tx_lock);
1322 
1323         priv->xstats.tx_clean++;
1324 
1325         while (priv->dirty_tx != priv->cur_tx) {
1326                 int last;
1327                 unsigned int entry = priv->dirty_tx % txsize;
1328                 struct sk_buff *skb = priv->tx_skbuff[entry];
1329                 struct dma_desc *p;
1330 
1331                 if (priv->extend_desc)
1332                         p = (struct dma_desc *)(priv->dma_etx + entry);
1333                 else
1334                         p = priv->dma_tx + entry;
1335 
1336                 /* Check if the descriptor is owned by the DMA. */
1337                 if (priv->hw->desc->get_tx_owner(p))
1338                         break;
1339 
1340                 /* Verify tx error by looking at the last segment. */
1341                 last = priv->hw->desc->get_tx_ls(p);
1342                 if (likely(last)) {
1343                         int tx_error =
1344                             priv->hw->desc->tx_status(&priv->dev->stats,
1345                                                       &priv->xstats, p,
1346                                                       priv->ioaddr);
1347                         if (likely(tx_error == 0)) {
1348                                 priv->dev->stats.tx_packets++;
1349                                 priv->xstats.tx_pkt_n++;
1350                         } else
1351                                 priv->dev->stats.tx_errors++;
1352 
1353                         stmmac_get_tx_hwtstamp(priv, entry, skb);
1354                 }
1355                 if (netif_msg_tx_done(priv))
1356                         pr_debug("%s: curr %d, dirty %d\n", __func__,
1357                                  priv->cur_tx, priv->dirty_tx);
1358 
1359                 if (likely(priv->tx_skbuff_dma[entry].buf)) {
1360                         if (priv->tx_skbuff_dma[entry].map_as_page)
1361                                 dma_unmap_page(priv->device,
1362                                                priv->tx_skbuff_dma[entry].buf,
1363                                                priv->hw->desc->get_tx_len(p),
1364                                                DMA_TO_DEVICE);
1365                         else
1366                                 dma_unmap_single(priv->device,
1367                                                  priv->tx_skbuff_dma[entry].buf,
1368                                                  priv->hw->desc->get_tx_len(p),
1369                                                  DMA_TO_DEVICE);
1370                         priv->tx_skbuff_dma[entry].buf = 0;
1371                         priv->tx_skbuff_dma[entry].map_as_page = false;
1372                 }
1373                 priv->hw->mode->clean_desc3(priv, p);
1374 
1375                 if (likely(skb != NULL)) {
1376                         pkts_compl++;
1377                         bytes_compl += skb->len;
1378                         dev_consume_skb_any(skb);
1379                         priv->tx_skbuff[entry] = NULL;
1380                 }
1381 
1382                 priv->hw->desc->release_tx_desc(p, priv->mode);
1383 
1384                 priv->dirty_tx++;
1385         }
1386 
1387         netdev_completed_queue(priv->dev, pkts_compl, bytes_compl);
1388 
1389         if (unlikely(netif_queue_stopped(priv->dev) &&
1390                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
1391                 netif_tx_lock(priv->dev);
1392                 if (netif_queue_stopped(priv->dev) &&
1393                     stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
1394                         if (netif_msg_tx_done(priv))
1395                                 pr_debug("%s: restart transmit\n", __func__);
1396                         netif_wake_queue(priv->dev);
1397                 }
1398                 netif_tx_unlock(priv->dev);
1399         }
1400 
1401         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1402                 stmmac_enable_eee_mode(priv);
1403                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1404         }
1405         spin_unlock(&priv->tx_lock);
1406 }
1407 
1408 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1409 {
1410         priv->hw->dma->enable_dma_irq(priv->ioaddr);
1411 }
1412 
1413 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1414 {
1415         priv->hw->dma->disable_dma_irq(priv->ioaddr);
1416 }
1417 
1418 /**
1419  * stmmac_tx_err - to manage the tx error
1420  * @priv: driver private structure
1421  * Description: it cleans the descriptors and restarts the transmission
1422  * in case of transmission errors.
1423  */
1424 static void stmmac_tx_err(struct stmmac_priv *priv)
1425 {
1426         int i;
1427         int txsize = priv->dma_tx_size;
1428         netif_stop_queue(priv->dev);
1429 
1430         priv->hw->dma->stop_tx(priv->ioaddr);
1431         dma_free_tx_skbufs(priv);
1432         for (i = 0; i < txsize; i++)
1433                 if (priv->extend_desc)
1434                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1435                                                      priv->mode,
1436                                                      (i == txsize - 1));
1437                 else
1438                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1439                                                      priv->mode,
1440                                                      (i == txsize - 1));
1441         priv->dirty_tx = 0;
1442         priv->cur_tx = 0;
1443         netdev_reset_queue(priv->dev);
1444         priv->hw->dma->start_tx(priv->ioaddr);
1445 
1446         priv->dev->stats.tx_errors++;
1447         netif_wake_queue(priv->dev);
1448 }
1449 
1450 /**
1451  * stmmac_dma_interrupt - DMA ISR
1452  * @priv: driver private structure
1453  * Description: this is the DMA ISR. It is called by the main ISR.
1454  * It calls the dwmac dma routine and schedule poll method in case of some
1455  * work can be done.
1456  */
1457 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1458 {
1459         int status;
1460         int rxfifosz = priv->plat->rx_fifo_size;
1461 
1462         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1463         if (likely((status & handle_rx)) || (status & handle_tx)) {
1464                 if (likely(napi_schedule_prep(&priv->napi))) {
1465                         stmmac_disable_dma_irq(priv);
1466                         __napi_schedule(&priv->napi);
1467                 }
1468         }
1469         if (unlikely(status & tx_hard_error_bump_tc)) {
1470                 /* Try to bump up the dma threshold on this failure */
1471                 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
1472                     (tc <= 256)) {
1473                         tc += 64;
1474                         if (priv->plat->force_thresh_dma_mode)
1475                                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc,
1476                                                         rxfifosz);
1477                         else
1478                                 priv->hw->dma->dma_mode(priv->ioaddr, tc,
1479                                                         SF_DMA_MODE, rxfifosz);
1480                         priv->xstats.threshold = tc;
1481                 }
1482         } else if (unlikely(status == tx_hard_error))
1483                 stmmac_tx_err(priv);
1484 }
1485 
1486 /**
1487  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1488  * @priv: driver private structure
1489  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1490  */
1491 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1492 {
1493         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1494             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1495 
1496         dwmac_mmc_intr_all_mask(priv->ioaddr);
1497 
1498         if (priv->dma_cap.rmon) {
1499                 dwmac_mmc_ctrl(priv->ioaddr, mode);
1500                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1501         } else
1502                 pr_info(" No MAC Management Counters available\n");
1503 }
1504 
1505 /**
1506  * stmmac_get_synopsys_id - return the SYINID.
1507  * @priv: driver private structure
1508  * Description: this simple function is to decode and return the SYINID
1509  * starting from the HW core register.
1510  */
1511 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1512 {
1513         u32 hwid = priv->hw->synopsys_uid;
1514 
1515         /* Check Synopsys Id (not available on old chips) */
1516         if (likely(hwid)) {
1517                 u32 uid = ((hwid & 0x0000ff00) >> 8);
1518                 u32 synid = (hwid & 0x000000ff);
1519 
1520                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1521                         uid, synid);
1522 
1523                 return synid;
1524         }
1525         return 0;
1526 }
1527 
1528 /**
1529  * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1530  * @priv: driver private structure
1531  * Description: select the Enhanced/Alternate or Normal descriptors.
1532  * In case of Enhanced/Alternate, it checks if the extended descriptors are
1533  * supported by the HW capability register.
1534  */
1535 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1536 {
1537         if (priv->plat->enh_desc) {
1538                 pr_info(" Enhanced/Alternate descriptors\n");
1539 
1540                 /* GMAC older than 3.50 has no extended descriptors */
1541                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1542                         pr_info("\tEnabled extended descriptors\n");
1543                         priv->extend_desc = 1;
1544                 } else
1545                         pr_warn("Extended descriptors not supported\n");
1546 
1547                 priv->hw->desc = &enh_desc_ops;
1548         } else {
1549                 pr_info(" Normal descriptors\n");
1550                 priv->hw->desc = &ndesc_ops;
1551         }
1552 }
1553 
1554 /**
1555  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1556  * @priv: driver private structure
1557  * Description:
1558  *  new GMAC chip generations have a new register to indicate the
1559  *  presence of the optional feature/functions.
1560  *  This can be also used to override the value passed through the
1561  *  platform and necessary for old MAC10/100 and GMAC chips.
1562  */
1563 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1564 {
1565         u32 hw_cap = 0;
1566 
1567         if (priv->hw->dma->get_hw_feature) {
1568                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1569 
1570                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1571                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1572                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1573                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1574                 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1575                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1576                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1577                 priv->dma_cap.pmt_remote_wake_up =
1578                     (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1579                 priv->dma_cap.pmt_magic_frame =
1580                     (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1581                 /* MMC */
1582                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1583                 /* IEEE 1588-2002 */
1584                 priv->dma_cap.time_stamp =
1585                     (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1586                 /* IEEE 1588-2008 */
1587                 priv->dma_cap.atime_stamp =
1588                     (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1589                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1590                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1591                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1592                 /* TX and RX csum */
1593                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1594                 priv->dma_cap.rx_coe_type1 =
1595                     (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1596                 priv->dma_cap.rx_coe_type2 =
1597                     (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1598                 priv->dma_cap.rxfifo_over_2048 =
1599                     (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1600                 /* TX and RX number of channels */
1601                 priv->dma_cap.number_rx_channel =
1602                     (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1603                 priv->dma_cap.number_tx_channel =
1604                     (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1605                 /* Alternate (enhanced) DESC mode */
1606                 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1607         }
1608 
1609         return hw_cap;
1610 }
1611 
1612 /**
1613  * stmmac_check_ether_addr - check if the MAC addr is valid
1614  * @priv: driver private structure
1615  * Description:
1616  * it is to verify if the MAC address is valid, in case of failures it
1617  * generates a random MAC address
1618  */
1619 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1620 {
1621         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1622                 priv->hw->mac->get_umac_addr(priv->hw,
1623                                              priv->dev->dev_addr, 0);
1624                 if (!is_valid_ether_addr(priv->dev->dev_addr))
1625                         eth_hw_addr_random(priv->dev);
1626                 pr_info("%s: device MAC address %pM\n", priv->dev->name,
1627                         priv->dev->dev_addr);
1628         }
1629 }
1630 
1631 /**
1632  * stmmac_init_dma_engine - DMA init.
1633  * @priv: driver private structure
1634  * Description:
1635  * It inits the DMA invoking the specific MAC/GMAC callback.
1636  * Some DMA parameters can be passed from the platform;
1637  * in case of these are not passed a default is kept for the MAC or GMAC.
1638  */
1639 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1640 {
1641         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1642         int mixed_burst = 0;
1643         int atds = 0;
1644 
1645         if (priv->plat->dma_cfg) {
1646                 pbl = priv->plat->dma_cfg->pbl;
1647                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1648                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1649                 burst_len = priv->plat->dma_cfg->burst_len;
1650         }
1651 
1652         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1653                 atds = 1;
1654 
1655         return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1656                                    burst_len, priv->dma_tx_phy,
1657                                    priv->dma_rx_phy, atds);
1658 }
1659 
1660 /**
1661  * stmmac_tx_timer - mitigation sw timer for tx.
1662  * @data: data pointer
1663  * Description:
1664  * This is the timer handler to directly invoke the stmmac_tx_clean.
1665  */
1666 static void stmmac_tx_timer(unsigned long data)
1667 {
1668         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1669 
1670         stmmac_tx_clean(priv);
1671 }
1672 
1673 /**
1674  * stmmac_init_tx_coalesce - init tx mitigation options.
1675  * @priv: driver private structure
1676  * Description:
1677  * This inits the transmit coalesce parameters: i.e. timer rate,
1678  * timer handler and default threshold used for enabling the
1679  * interrupt on completion bit.
1680  */
1681 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1682 {
1683         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1684         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1685         init_timer(&priv->txtimer);
1686         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1687         priv->txtimer.data = (unsigned long)priv;
1688         priv->txtimer.function = stmmac_tx_timer;
1689         add_timer(&priv->txtimer);
1690 }
1691 
1692 /**
1693  * stmmac_hw_setup - setup mac in a usable state.
1694  *  @dev : pointer to the device structure.
1695  *  Description:
1696  *  this is the main function to setup the HW in a usable state because the
1697  *  dma engine is reset, the core registers are configured (e.g. AXI,
1698  *  Checksum features, timers). The DMA is ready to start receiving and
1699  *  transmitting.
1700  *  Return value:
1701  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1702  *  file on failure.
1703  */
1704 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
1705 {
1706         struct stmmac_priv *priv = netdev_priv(dev);
1707         int ret;
1708 
1709         /* DMA initialization and SW reset */
1710         ret = stmmac_init_dma_engine(priv);
1711         if (ret < 0) {
1712                 pr_err("%s: DMA engine initialization failed\n", __func__);
1713                 return ret;
1714         }
1715 
1716         /* Copy the MAC addr into the HW  */
1717         priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1718 
1719         /* If required, perform hw setup of the bus. */
1720         if (priv->plat->bus_setup)
1721                 priv->plat->bus_setup(priv->ioaddr);
1722 
1723         /* Initialize the MAC Core */
1724         priv->hw->mac->core_init(priv->hw, dev->mtu);
1725 
1726         ret = priv->hw->mac->rx_ipc(priv->hw);
1727         if (!ret) {
1728                 pr_warn(" RX IPC Checksum Offload disabled\n");
1729                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1730                 priv->hw->rx_csum = 0;
1731         }
1732 
1733         /* Enable the MAC Rx/Tx */
1734         stmmac_set_mac(priv->ioaddr, true);
1735 
1736         /* Set the HW DMA mode and the COE */
1737         stmmac_dma_operation_mode(priv);
1738 
1739         stmmac_mmc_setup(priv);
1740 
1741         if (init_ptp) {
1742                 ret = stmmac_init_ptp(priv);
1743                 if (ret && ret != -EOPNOTSUPP)
1744                         pr_warn("%s: failed PTP initialisation\n", __func__);
1745         }
1746 
1747 #ifdef CONFIG_DEBUG_FS
1748         ret = stmmac_init_fs(dev);
1749         if (ret < 0)
1750                 pr_warn("%s: failed debugFS registration\n", __func__);
1751 #endif
1752         /* Start the ball rolling... */
1753         pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
1754         priv->hw->dma->start_tx(priv->ioaddr);
1755         priv->hw->dma->start_rx(priv->ioaddr);
1756 
1757         /* Dump DMA/MAC registers */
1758         if (netif_msg_hw(priv)) {
1759                 priv->hw->mac->dump_regs(priv->hw);
1760                 priv->hw->dma->dump_regs(priv->ioaddr);
1761         }
1762         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1763 
1764         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1765                 priv->rx_riwt = MAX_DMA_RIWT;
1766                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1767         }
1768 
1769         if (priv->pcs && priv->hw->mac->ctrl_ane)
1770                 priv->hw->mac->ctrl_ane(priv->hw, 0);
1771 
1772         return 0;
1773 }
1774 
1775 /**
1776  *  stmmac_open - open entry point of the driver
1777  *  @dev : pointer to the device structure.
1778  *  Description:
1779  *  This function is the open entry point of the driver.
1780  *  Return value:
1781  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1782  *  file on failure.
1783  */
1784 static int stmmac_open(struct net_device *dev)
1785 {
1786         struct stmmac_priv *priv = netdev_priv(dev);
1787         int ret;
1788 
1789         stmmac_check_ether_addr(priv);
1790 
1791         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1792             priv->pcs != STMMAC_PCS_RTBI) {
1793                 ret = stmmac_init_phy(dev);
1794                 if (ret) {
1795                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1796                                __func__, ret);
1797                         return ret;
1798                 }
1799         }
1800 
1801         /* Extra statistics */
1802         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1803         priv->xstats.threshold = tc;
1804 
1805         /* Create and initialize the TX/RX descriptors chains. */
1806         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1807         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1808         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1809 
1810         ret = alloc_dma_desc_resources(priv);
1811         if (ret < 0) {
1812                 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1813                 goto dma_desc_error;
1814         }
1815 
1816         ret = init_dma_desc_rings(dev, GFP_KERNEL);
1817         if (ret < 0) {
1818                 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1819                 goto init_error;
1820         }
1821 
1822         ret = stmmac_hw_setup(dev, true);
1823         if (ret < 0) {
1824                 pr_err("%s: Hw setup failed\n", __func__);
1825                 goto init_error;
1826         }
1827 
1828         stmmac_init_tx_coalesce(priv);
1829 
1830         if (priv->phydev)
1831                 phy_start(priv->phydev);
1832 
1833         /* Request the IRQ lines */
1834         ret = request_irq(dev->irq, stmmac_interrupt,
1835                           IRQF_SHARED, dev->name, dev);
1836         if (unlikely(ret < 0)) {
1837                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1838                        __func__, dev->irq, ret);
1839                 goto init_error;
1840         }
1841 
1842         /* Request the Wake IRQ in case of another line is used for WoL */
1843         if (priv->wol_irq != dev->irq) {
1844                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1845                                   IRQF_SHARED, dev->name, dev);
1846                 if (unlikely(ret < 0)) {
1847                         pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1848                                __func__, priv->wol_irq, ret);
1849                         goto wolirq_error;
1850                 }
1851         }
1852 
1853         /* Request the IRQ lines */
1854         if (priv->lpi_irq > 0) {
1855                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1856                                   dev->name, dev);
1857                 if (unlikely(ret < 0)) {
1858                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1859                                __func__, priv->lpi_irq, ret);
1860                         goto lpiirq_error;
1861                 }
1862         }
1863 
1864         napi_enable(&priv->napi);
1865         netif_start_queue(dev);
1866 
1867         return 0;
1868 
1869 lpiirq_error:
1870         if (priv->wol_irq != dev->irq)
1871                 free_irq(priv->wol_irq, dev);
1872 wolirq_error:
1873         free_irq(dev->irq, dev);
1874 
1875 init_error:
1876         free_dma_desc_resources(priv);
1877 dma_desc_error:
1878         if (priv->phydev)
1879                 phy_disconnect(priv->phydev);
1880 
1881         return ret;
1882 }
1883 
1884 /**
1885  *  stmmac_release - close entry point of the driver
1886  *  @dev : device pointer.
1887  *  Description:
1888  *  This is the stop entry point of the driver.
1889  */
1890 static int stmmac_release(struct net_device *dev)
1891 {
1892         struct stmmac_priv *priv = netdev_priv(dev);
1893 
1894         if (priv->eee_enabled)
1895                 del_timer_sync(&priv->eee_ctrl_timer);
1896 
1897         /* Stop and disconnect the PHY */
1898         if (priv->phydev) {
1899                 phy_stop(priv->phydev);
1900                 phy_disconnect(priv->phydev);
1901                 priv->phydev = NULL;
1902         }
1903 
1904         netif_stop_queue(dev);
1905 
1906         napi_disable(&priv->napi);
1907 
1908         del_timer_sync(&priv->txtimer);
1909 
1910         /* Free the IRQ lines */
1911         free_irq(dev->irq, dev);
1912         if (priv->wol_irq != dev->irq)
1913                 free_irq(priv->wol_irq, dev);
1914         if (priv->lpi_irq > 0)
1915                 free_irq(priv->lpi_irq, dev);
1916 
1917         /* Stop TX/RX DMA and clear the descriptors */
1918         priv->hw->dma->stop_tx(priv->ioaddr);
1919         priv->hw->dma->stop_rx(priv->ioaddr);
1920 
1921         /* Release and free the Rx/Tx resources */
1922         free_dma_desc_resources(priv);
1923 
1924         /* Disable the MAC Rx/Tx */
1925         stmmac_set_mac(priv->ioaddr, false);
1926 
1927         netif_carrier_off(dev);
1928 
1929 #ifdef CONFIG_DEBUG_FS
1930         stmmac_exit_fs(dev);
1931 #endif
1932 
1933         stmmac_release_ptp(priv);
1934 
1935         return 0;
1936 }
1937 
1938 /**
1939  *  stmmac_xmit - Tx entry point of the driver
1940  *  @skb : the socket buffer
1941  *  @dev : device pointer
1942  *  Description : this is the tx entry point of the driver.
1943  *  It programs the chain or the ring and supports oversized frames
1944  *  and SG feature.
1945  */
1946 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1947 {
1948         struct stmmac_priv *priv = netdev_priv(dev);
1949         unsigned int txsize = priv->dma_tx_size;
1950         int entry;
1951         int i, csum_insertion = 0, is_jumbo = 0;
1952         int nfrags = skb_shinfo(skb)->nr_frags;
1953         struct dma_desc *desc, *first;
1954         unsigned int nopaged_len = skb_headlen(skb);
1955         unsigned int enh_desc = priv->plat->enh_desc;
1956 
1957         spin_lock(&priv->tx_lock);
1958 
1959         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1960                 spin_unlock(&priv->tx_lock);
1961                 if (!netif_queue_stopped(dev)) {
1962                         netif_stop_queue(dev);
1963                         /* This is a hard error, log it. */
1964                         pr_err("%s: Tx Ring full when queue awake\n", __func__);
1965                 }
1966                 return NETDEV_TX_BUSY;
1967         }
1968 
1969         if (priv->tx_path_in_lpi_mode)
1970                 stmmac_disable_eee_mode(priv);
1971 
1972         entry = priv->cur_tx % txsize;
1973 
1974         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1975 
1976         if (priv->extend_desc)
1977                 desc = (struct dma_desc *)(priv->dma_etx + entry);
1978         else
1979                 desc = priv->dma_tx + entry;
1980 
1981         first = desc;
1982 
1983         /* To program the descriptors according to the size of the frame */
1984         if (enh_desc)
1985                 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
1986 
1987         if (likely(!is_jumbo)) {
1988                 desc->des2 = dma_map_single(priv->device, skb->data,
1989                                             nopaged_len, DMA_TO_DEVICE);
1990                 if (dma_mapping_error(priv->device, desc->des2))
1991                         goto dma_map_err;
1992                 priv->tx_skbuff_dma[entry].buf = desc->des2;
1993                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1994                                                 csum_insertion, priv->mode);
1995         } else {
1996                 desc = first;
1997                 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
1998                 if (unlikely(entry < 0))
1999                         goto dma_map_err;
2000         }
2001 
2002         for (i = 0; i < nfrags; i++) {
2003                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2004                 int len = skb_frag_size(frag);
2005 
2006                 priv->tx_skbuff[entry] = NULL;
2007                 entry = (++priv->cur_tx) % txsize;
2008                 if (priv->extend_desc)
2009                         desc = (struct dma_desc *)(priv->dma_etx + entry);
2010                 else
2011                         desc = priv->dma_tx + entry;
2012 
2013                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
2014                                               DMA_TO_DEVICE);
2015                 if (dma_mapping_error(priv->device, desc->des2))
2016                         goto dma_map_err; /* should reuse desc w/o issues */
2017 
2018                 priv->tx_skbuff_dma[entry].buf = desc->des2;
2019                 priv->tx_skbuff_dma[entry].map_as_page = true;
2020                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
2021                                                 priv->mode);
2022                 wmb();
2023                 priv->hw->desc->set_tx_owner(desc);
2024                 wmb();
2025         }
2026 
2027         priv->tx_skbuff[entry] = skb;
2028 
2029         /* Finalize the latest segment. */
2030         priv->hw->desc->close_tx_desc(desc);
2031 
2032         wmb();
2033         /* According to the coalesce parameter the IC bit for the latest
2034          * segment could be reset and the timer re-started to invoke the
2035          * stmmac_tx function. This approach takes care about the fragments.
2036          */
2037         priv->tx_count_frames += nfrags + 1;
2038         if (priv->tx_coal_frames > priv->tx_count_frames) {
2039                 priv->hw->desc->clear_tx_ic(desc);
2040                 priv->xstats.tx_reset_ic_bit++;
2041                 mod_timer(&priv->txtimer,
2042                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
2043         } else
2044                 priv->tx_count_frames = 0;
2045 
2046         /* To avoid raise condition */
2047         priv->hw->desc->set_tx_owner(first);
2048         wmb();
2049 
2050         priv->cur_tx++;
2051 
2052         if (netif_msg_pktdata(priv)) {
2053                 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
2054                         __func__, (priv->cur_tx % txsize),
2055                         (priv->dirty_tx % txsize), entry, first, nfrags);
2056 
2057                 if (priv->extend_desc)
2058                         stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
2059                 else
2060                         stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
2061 
2062                 pr_debug(">>> frame to be transmitted: ");
2063                 print_pkt(skb->data, skb->len);
2064         }
2065         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2066                 if (netif_msg_hw(priv))
2067                         pr_debug("%s: stop transmitted packets\n", __func__);
2068                 netif_stop_queue(dev);
2069         }
2070 
2071         dev->stats.tx_bytes += skb->len;
2072 
2073         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2074                      priv->hwts_tx_en)) {
2075                 /* declare that device is doing timestamping */
2076                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2077                 priv->hw->desc->enable_tx_timestamp(first);
2078         }
2079 
2080         if (!priv->hwts_tx_en)
2081                 skb_tx_timestamp(skb);
2082 
2083         netdev_sent_queue(dev, skb->len);
2084         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
2085 
2086         spin_unlock(&priv->tx_lock);
2087         return NETDEV_TX_OK;
2088 
2089 dma_map_err:
2090         spin_unlock(&priv->tx_lock);
2091         dev_err(priv->device, "Tx dma map failed\n");
2092         dev_kfree_skb(skb);
2093         priv->dev->stats.tx_dropped++;
2094         return NETDEV_TX_OK;
2095 }
2096 
2097 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
2098 {
2099         struct ethhdr *ehdr;
2100         u16 vlanid;
2101 
2102         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
2103             NETIF_F_HW_VLAN_CTAG_RX &&
2104             !__vlan_get_tag(skb, &vlanid)) {
2105                 /* pop the vlan tag */
2106                 ehdr = (struct ethhdr *)skb->data;
2107                 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
2108                 skb_pull(skb, VLAN_HLEN);
2109                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
2110         }
2111 }
2112 
2113 
2114 /**
2115  * stmmac_rx_refill - refill used skb preallocated buffers
2116  * @priv: driver private structure
2117  * Description : this is to reallocate the skb for the reception process
2118  * that is based on zero-copy.
2119  */
2120 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2121 {
2122         unsigned int rxsize = priv->dma_rx_size;
2123         int bfsize = priv->dma_buf_sz;
2124 
2125         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
2126                 unsigned int entry = priv->dirty_rx % rxsize;
2127                 struct dma_desc *p;
2128 
2129                 if (priv->extend_desc)
2130                         p = (struct dma_desc *)(priv->dma_erx + entry);
2131                 else
2132                         p = priv->dma_rx + entry;
2133 
2134                 if (likely(priv->rx_skbuff[entry] == NULL)) {
2135                         struct sk_buff *skb;
2136 
2137                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2138 
2139                         if (unlikely(skb == NULL))
2140                                 break;
2141 
2142                         priv->rx_skbuff[entry] = skb;
2143                         priv->rx_skbuff_dma[entry] =
2144                             dma_map_single(priv->device, skb->data, bfsize,
2145                                            DMA_FROM_DEVICE);
2146                         if (dma_mapping_error(priv->device,
2147                                               priv->rx_skbuff_dma[entry])) {
2148                                 dev_err(priv->device, "Rx dma map failed\n");
2149                                 dev_kfree_skb(skb);
2150                                 break;
2151                         }
2152                         p->des2 = priv->rx_skbuff_dma[entry];
2153 
2154                         priv->hw->mode->refill_desc3(priv, p);
2155 
2156                         if (netif_msg_rx_status(priv))
2157                                 pr_debug("\trefill entry #%d\n", entry);
2158                 }
2159                 wmb();
2160                 priv->hw->desc->set_rx_owner(p);
2161                 wmb();
2162         }
2163 }
2164 
2165 /**
2166  * stmmac_rx - manage the receive process
2167  * @priv: driver private structure
2168  * @limit: napi bugget.
2169  * Description :  this the function called by the napi poll method.
2170  * It gets all the frames inside the ring.
2171  */
2172 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2173 {
2174         unsigned int rxsize = priv->dma_rx_size;
2175         unsigned int entry = priv->cur_rx % rxsize;
2176         unsigned int next_entry;
2177         unsigned int count = 0;
2178         int coe = priv->hw->rx_csum;
2179 
2180         if (netif_msg_rx_status(priv)) {
2181                 pr_debug("%s: descriptor ring:\n", __func__);
2182                 if (priv->extend_desc)
2183                         stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
2184                 else
2185                         stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
2186         }
2187         while (count < limit) {
2188                 int status;
2189                 struct dma_desc *p;
2190 
2191                 if (priv->extend_desc)
2192                         p = (struct dma_desc *)(priv->dma_erx + entry);
2193                 else
2194                         p = priv->dma_rx + entry;
2195 
2196                 if (priv->hw->desc->get_rx_owner(p))
2197                         break;
2198 
2199                 count++;
2200 
2201                 next_entry = (++priv->cur_rx) % rxsize;
2202                 if (priv->extend_desc)
2203                         prefetch(priv->dma_erx + next_entry);
2204                 else
2205                         prefetch(priv->dma_rx + next_entry);
2206 
2207                 /* read the status of the incoming frame */
2208                 status = priv->hw->desc->rx_status(&priv->dev->stats,
2209                                                    &priv->xstats, p);
2210                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2211                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
2212                                                            &priv->xstats,
2213                                                            priv->dma_erx +
2214                                                            entry);
2215                 if (unlikely(status == discard_frame)) {
2216                         priv->dev->stats.rx_errors++;
2217                         if (priv->hwts_rx_en && !priv->extend_desc) {
2218                                 /* DESC2 & DESC3 will be overwitten by device
2219                                  * with timestamp value, hence reinitialize
2220                                  * them in stmmac_rx_refill() function so that
2221                                  * device can reuse it.
2222                                  */
2223                                 priv->rx_skbuff[entry] = NULL;
2224                                 dma_unmap_single(priv->device,
2225                                                  priv->rx_skbuff_dma[entry],
2226                                                  priv->dma_buf_sz,
2227                                                  DMA_FROM_DEVICE);
2228                         }
2229                 } else {
2230                         struct sk_buff *skb;
2231                         int frame_len;
2232 
2233                         frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2234 
2235                         /*  check if frame_len fits the preallocated memory */
2236                         if (frame_len > priv->dma_buf_sz) {
2237                                 priv->dev->stats.rx_length_errors++;
2238                                 break;
2239                         }
2240 
2241                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2242                          * Type frames (LLC/LLC-SNAP)
2243                          */
2244                         if (unlikely(status != llc_snap))
2245                                 frame_len -= ETH_FCS_LEN;
2246 
2247                         if (netif_msg_rx_status(priv)) {
2248                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2249                                          p, entry, p->des2);
2250                                 if (frame_len > ETH_FRAME_LEN)
2251                                         pr_debug("\tframe size %d, COE: %d\n",
2252                                                  frame_len, status);
2253                         }
2254                         skb = priv->rx_skbuff[entry];
2255                         if (unlikely(!skb)) {
2256                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
2257                                        priv->dev->name);
2258                                 priv->dev->stats.rx_dropped++;
2259                                 break;
2260                         }
2261                         prefetch(skb->data - NET_IP_ALIGN);
2262                         priv->rx_skbuff[entry] = NULL;
2263 
2264                         stmmac_get_rx_hwtstamp(priv, entry, skb);
2265 
2266                         skb_put(skb, frame_len);
2267                         dma_unmap_single(priv->device,
2268                                          priv->rx_skbuff_dma[entry],
2269                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
2270 
2271                         if (netif_msg_pktdata(priv)) {
2272                                 pr_debug("frame received (%dbytes)", frame_len);
2273                                 print_pkt(skb->data, frame_len);
2274                         }
2275 
2276                         stmmac_rx_vlan(priv->dev, skb);
2277 
2278                         skb->protocol = eth_type_trans(skb, priv->dev);
2279 
2280                         if (unlikely(!coe))
2281                                 skb_checksum_none_assert(skb);
2282                         else
2283                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2284 
2285                         napi_gro_receive(&priv->napi, skb);
2286 
2287                         priv->dev->stats.rx_packets++;
2288                         priv->dev->stats.rx_bytes += frame_len;
2289                 }
2290                 entry = next_entry;
2291         }
2292 
2293         stmmac_rx_refill(priv);
2294 
2295         priv->xstats.rx_pkt_n += count;
2296 
2297         return count;
2298 }
2299 
2300 /**
2301  *  stmmac_poll - stmmac poll method (NAPI)
2302  *  @napi : pointer to the napi structure.
2303  *  @budget : maximum number of packets that the current CPU can receive from
2304  *            all interfaces.
2305  *  Description :
2306  *  To look at the incoming frames and clear the tx resources.
2307  */
2308 static int stmmac_poll(struct napi_struct *napi, int budget)
2309 {
2310         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2311         int work_done = 0;
2312 
2313         priv->xstats.napi_poll++;
2314         stmmac_tx_clean(priv);
2315 
2316         work_done = stmmac_rx(priv, budget);
2317         if (work_done < budget) {
2318                 napi_complete(napi);
2319                 stmmac_enable_dma_irq(priv);
2320         }
2321         return work_done;
2322 }
2323 
2324 /**
2325  *  stmmac_tx_timeout
2326  *  @dev : Pointer to net device structure
2327  *  Description: this function is called when a packet transmission fails to
2328  *   complete within a reasonable time. The driver will mark the error in the
2329  *   netdev structure and arrange for the device to be reset to a sane state
2330  *   in order to transmit a new packet.
2331  */
2332 static void stmmac_tx_timeout(struct net_device *dev)
2333 {
2334         struct stmmac_priv *priv = netdev_priv(dev);
2335 
2336         /* Clear Tx resources and restart transmitting again */
2337         stmmac_tx_err(priv);
2338 }
2339 
2340 /**
2341  *  stmmac_set_rx_mode - entry point for multicast addressing
2342  *  @dev : pointer to the device structure
2343  *  Description:
2344  *  This function is a driver entry point which gets called by the kernel
2345  *  whenever multicast addresses must be enabled/disabled.
2346  *  Return value:
2347  *  void.
2348  */
2349 static void stmmac_set_rx_mode(struct net_device *dev)
2350 {
2351         struct stmmac_priv *priv = netdev_priv(dev);
2352 
2353         priv->hw->mac->set_filter(priv->hw, dev);
2354 }
2355 
2356 /**
2357  *  stmmac_change_mtu - entry point to change MTU size for the device.
2358  *  @dev : device pointer.
2359  *  @new_mtu : the new MTU size for the device.
2360  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
2361  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
2362  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
2363  *  Return value:
2364  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2365  *  file on failure.
2366  */
2367 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2368 {
2369         struct stmmac_priv *priv = netdev_priv(dev);
2370         int max_mtu;
2371 
2372         if (netif_running(dev)) {
2373                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2374                 return -EBUSY;
2375         }
2376 
2377         if (priv->plat->enh_desc)
2378                 max_mtu = JUMBO_LEN;
2379         else
2380                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2381 
2382         if (priv->plat->maxmtu < max_mtu)
2383                 max_mtu = priv->plat->maxmtu;
2384 
2385         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2386                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2387                 return -EINVAL;
2388         }
2389 
2390         dev->mtu = new_mtu;
2391         netdev_update_features(dev);
2392 
2393         return 0;
2394 }
2395 
2396 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2397                                              netdev_features_t features)
2398 {
2399         struct stmmac_priv *priv = netdev_priv(dev);
2400 
2401         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2402                 features &= ~NETIF_F_RXCSUM;
2403 
2404         if (!priv->plat->tx_coe)
2405                 features &= ~NETIF_F_ALL_CSUM;
2406 
2407         /* Some GMAC devices have a bugged Jumbo frame support that
2408          * needs to have the Tx COE disabled for oversized frames
2409          * (due to limited buffer sizes). In this case we disable
2410          * the TX csum insertionin the TDES and not use SF.
2411          */
2412         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2413                 features &= ~NETIF_F_ALL_CSUM;
2414 
2415         return features;
2416 }
2417 
2418 static int stmmac_set_features(struct net_device *netdev,
2419                                netdev_features_t features)
2420 {
2421         struct stmmac_priv *priv = netdev_priv(netdev);
2422 
2423         /* Keep the COE Type in case of csum is supporting */
2424         if (features & NETIF_F_RXCSUM)
2425                 priv->hw->rx_csum = priv->plat->rx_coe;
2426         else
2427                 priv->hw->rx_csum = 0;
2428         /* No check needed because rx_coe has been set before and it will be
2429          * fixed in case of issue.
2430          */
2431         priv->hw->mac->rx_ipc(priv->hw);
2432 
2433         return 0;
2434 }
2435 
2436 /**
2437  *  stmmac_interrupt - main ISR
2438  *  @irq: interrupt number.
2439  *  @dev_id: to pass the net device pointer.
2440  *  Description: this is the main driver interrupt service routine.
2441  *  It can call:
2442  *  o DMA service routine (to manage incoming frame reception and transmission
2443  *    status)
2444  *  o Core interrupts to manage: remote wake-up, management counter, LPI
2445  *    interrupts.
2446  */
2447 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2448 {
2449         struct net_device *dev = (struct net_device *)dev_id;
2450         struct stmmac_priv *priv = netdev_priv(dev);
2451 
2452         if (priv->irq_wake)
2453                 pm_wakeup_event(priv->device, 0);
2454 
2455         if (unlikely(!dev)) {
2456                 pr_err("%s: invalid dev pointer\n", __func__);
2457                 return IRQ_NONE;
2458         }
2459 
2460         /* To handle GMAC own interrupts */
2461         if (priv->plat->has_gmac) {
2462                 int status = priv->hw->mac->host_irq_status(priv->hw,
2463                                                             &priv->xstats);
2464                 if (unlikely(status)) {
2465                         /* For LPI we need to save the tx status */
2466                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2467                                 priv->tx_path_in_lpi_mode = true;
2468                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2469                                 priv->tx_path_in_lpi_mode = false;
2470                 }
2471         }
2472 
2473         /* To handle DMA interrupts */
2474         stmmac_dma_interrupt(priv);
2475 
2476         return IRQ_HANDLED;
2477 }
2478 
2479 #ifdef CONFIG_NET_POLL_CONTROLLER
2480 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2481  * to allow network I/O with interrupts disabled.
2482  */
2483 static void stmmac_poll_controller(struct net_device *dev)
2484 {
2485         disable_irq(dev->irq);
2486         stmmac_interrupt(dev->irq, dev);
2487         enable_irq(dev->irq);
2488 }
2489 #endif
2490 
2491 /**
2492  *  stmmac_ioctl - Entry point for the Ioctl
2493  *  @dev: Device pointer.
2494  *  @rq: An IOCTL specefic structure, that can contain a pointer to
2495  *  a proprietary structure used to pass information to the driver.
2496  *  @cmd: IOCTL command
2497  *  Description:
2498  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2499  */
2500 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2501 {
2502         struct stmmac_priv *priv = netdev_priv(dev);
2503         int ret = -EOPNOTSUPP;
2504 
2505         if (!netif_running(dev))
2506                 return -EINVAL;
2507 
2508         switch (cmd) {
2509         case SIOCGMIIPHY:
2510         case SIOCGMIIREG:
2511         case SIOCSMIIREG:
2512                 if (!priv->phydev)
2513                         return -EINVAL;
2514                 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2515                 break;
2516         case SIOCSHWTSTAMP:
2517                 ret = stmmac_hwtstamp_ioctl(dev, rq);
2518                 break;
2519         default:
2520                 break;
2521         }
2522 
2523         return ret;
2524 }
2525 
2526 #ifdef CONFIG_DEBUG_FS
2527 static struct dentry *stmmac_fs_dir;
2528 
2529 static void sysfs_display_ring(void *head, int size, int extend_desc,
2530                                struct seq_file *seq)
2531 {
2532         int i;
2533         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2534         struct dma_desc *p = (struct dma_desc *)head;
2535 
2536         for (i = 0; i < size; i++) {
2537                 u64 x;
2538                 if (extend_desc) {
2539                         x = *(u64 *) ep;
2540                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2541                                    i, (unsigned int)virt_to_phys(ep),
2542                                    (unsigned int)x, (unsigned int)(x >> 32),
2543                                    ep->basic.des2, ep->basic.des3);
2544                         ep++;
2545                 } else {
2546                         x = *(u64 *) p;
2547                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2548                                    i, (unsigned int)virt_to_phys(ep),
2549                                    (unsigned int)x, (unsigned int)(x >> 32),
2550                                    p->des2, p->des3);
2551                         p++;
2552                 }
2553                 seq_printf(seq, "\n");
2554         }
2555 }
2556 
2557 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2558 {
2559         struct net_device *dev = seq->private;
2560         struct stmmac_priv *priv = netdev_priv(dev);
2561         unsigned int txsize = priv->dma_tx_size;
2562         unsigned int rxsize = priv->dma_rx_size;
2563 
2564         if (priv->extend_desc) {
2565                 seq_printf(seq, "Extended RX descriptor ring:\n");
2566                 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq);
2567                 seq_printf(seq, "Extended TX descriptor ring:\n");
2568                 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq);
2569         } else {
2570                 seq_printf(seq, "RX descriptor ring:\n");
2571                 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
2572                 seq_printf(seq, "TX descriptor ring:\n");
2573                 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
2574         }
2575 
2576         return 0;
2577 }
2578 
2579 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2580 {
2581         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2582 }
2583 
2584 static const struct file_operations stmmac_rings_status_fops = {
2585         .owner = THIS_MODULE,
2586         .open = stmmac_sysfs_ring_open,
2587         .read = seq_read,
2588         .llseek = seq_lseek,
2589         .release = single_release,
2590 };
2591 
2592 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2593 {
2594         struct net_device *dev = seq->private;
2595         struct stmmac_priv *priv = netdev_priv(dev);
2596 
2597         if (!priv->hw_cap_support) {
2598                 seq_printf(seq, "DMA HW features not supported\n");
2599                 return 0;
2600         }
2601 
2602         seq_printf(seq, "==============================\n");
2603         seq_printf(seq, "\tDMA HW features\n");
2604         seq_printf(seq, "==============================\n");
2605 
2606         seq_printf(seq, "\t10/100 Mbps %s\n",
2607                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2608         seq_printf(seq, "\t1000 Mbps %s\n",
2609                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
2610         seq_printf(seq, "\tHalf duple %s\n",
2611                    (priv->dma_cap.half_duplex) ? "Y" : "N");
2612         seq_printf(seq, "\tHash Filter: %s\n",
2613                    (priv->dma_cap.hash_filter) ? "Y" : "N");
2614         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2615                    (priv->dma_cap.multi_addr) ? "Y" : "N");
2616         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2617                    (priv->dma_cap.pcs) ? "Y" : "N");
2618         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2619                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
2620         seq_printf(seq, "\tPMT Remote wake up: %s\n",
2621                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2622         seq_printf(seq, "\tPMT Magic Frame: %s\n",
2623                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2624         seq_printf(seq, "\tRMON module: %s\n",
2625                    (priv->dma_cap.rmon) ? "Y" : "N");
2626         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2627                    (priv->dma_cap.time_stamp) ? "Y" : "N");
2628         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2629                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
2630         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2631                    (priv->dma_cap.eee) ? "Y" : "N");
2632         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2633         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2634                    (priv->dma_cap.tx_coe) ? "Y" : "N");
2635         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2636                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2637         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2638                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2639         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2640                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2641         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2642                    priv->dma_cap.number_rx_channel);
2643         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2644                    priv->dma_cap.number_tx_channel);
2645         seq_printf(seq, "\tEnhanced descriptors: %s\n",
2646                    (priv->dma_cap.enh_desc) ? "Y" : "N");
2647 
2648         return 0;
2649 }
2650 
2651 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2652 {
2653         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2654 }
2655 
2656 static const struct file_operations stmmac_dma_cap_fops = {
2657         .owner = THIS_MODULE,
2658         .open = stmmac_sysfs_dma_cap_open,
2659         .read = seq_read,
2660         .llseek = seq_lseek,
2661         .release = single_release,
2662 };
2663 
2664 static int stmmac_init_fs(struct net_device *dev)
2665 {
2666         struct stmmac_priv *priv = netdev_priv(dev);
2667 
2668         /* Create per netdev entries */
2669         priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
2670 
2671         if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
2672                 pr_err("ERROR %s/%s, debugfs create directory failed\n",
2673                        STMMAC_RESOURCE_NAME, dev->name);
2674 
2675                 return -ENOMEM;
2676         }
2677 
2678         /* Entry to report DMA RX/TX rings */
2679         priv->dbgfs_rings_status =
2680                 debugfs_create_file("descriptors_status", S_IRUGO,
2681                                     priv->dbgfs_dir, dev,
2682                                     &stmmac_rings_status_fops);
2683 
2684         if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
2685                 pr_info("ERROR creating stmmac ring debugfs file\n");
2686                 debugfs_remove_recursive(priv->dbgfs_dir);
2687 
2688                 return -ENOMEM;
2689         }
2690 
2691         /* Entry to report the DMA HW features */
2692         priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO,
2693                                             priv->dbgfs_dir,
2694                                             dev, &stmmac_dma_cap_fops);
2695 
2696         if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
2697                 pr_info("ERROR creating stmmac MMC debugfs file\n");
2698                 debugfs_remove_recursive(priv->dbgfs_dir);
2699 
2700                 return -ENOMEM;
2701         }
2702 
2703         return 0;
2704 }
2705 
2706 static void stmmac_exit_fs(struct net_device *dev)
2707 {
2708         struct stmmac_priv *priv = netdev_priv(dev);
2709 
2710         debugfs_remove_recursive(priv->dbgfs_dir);
2711 }
2712 #endif /* CONFIG_DEBUG_FS */
2713 
2714 static const struct net_device_ops stmmac_netdev_ops = {
2715         .ndo_open = stmmac_open,
2716         .ndo_start_xmit = stmmac_xmit,
2717         .ndo_stop = stmmac_release,
2718         .ndo_change_mtu = stmmac_change_mtu,
2719         .ndo_fix_features = stmmac_fix_features,
2720         .ndo_set_features = stmmac_set_features,
2721         .ndo_set_rx_mode = stmmac_set_rx_mode,
2722         .ndo_tx_timeout = stmmac_tx_timeout,
2723         .ndo_do_ioctl = stmmac_ioctl,
2724 #ifdef CONFIG_NET_POLL_CONTROLLER
2725         .ndo_poll_controller = stmmac_poll_controller,
2726 #endif
2727         .ndo_set_mac_address = eth_mac_addr,
2728 };
2729 
2730 /**
2731  *  stmmac_hw_init - Init the MAC device
2732  *  @priv: driver private structure
2733  *  Description: this function is to configure the MAC device according to
2734  *  some platform parameters or the HW capability register. It prepares the
2735  *  driver to use either ring or chain modes and to setup either enhanced or
2736  *  normal descriptors.
2737  */
2738 static int stmmac_hw_init(struct stmmac_priv *priv)
2739 {
2740         struct mac_device_info *mac;
2741 
2742         /* Identify the MAC HW device */
2743         if (priv->plat->has_gmac) {
2744                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2745                 mac = dwmac1000_setup(priv->ioaddr,
2746                                       priv->plat->multicast_filter_bins,
2747                                       priv->plat->unicast_filter_entries);
2748         } else {
2749                 mac = dwmac100_setup(priv->ioaddr);
2750         }
2751         if (!mac)
2752                 return -ENOMEM;
2753 
2754         priv->hw = mac;
2755 
2756         /* Get and dump the chip ID */
2757         priv->synopsys_id = stmmac_get_synopsys_id(priv);
2758 
2759         /* To use the chained or ring mode */
2760         if (chain_mode) {
2761                 priv->hw->mode = &chain_mode_ops;
2762                 pr_info(" Chain mode enabled\n");
2763                 priv->mode = STMMAC_CHAIN_MODE;
2764         } else {
2765                 priv->hw->mode = &ring_mode_ops;
2766                 pr_info(" Ring mode enabled\n");
2767                 priv->mode = STMMAC_RING_MODE;
2768         }
2769 
2770         /* Get the HW capability (new GMAC newer than 3.50a) */
2771         priv->hw_cap_support = stmmac_get_hw_features(priv);
2772         if (priv->hw_cap_support) {
2773                 pr_info(" DMA HW capability register supported");
2774 
2775                 /* We can override some gmac/dma configuration fields: e.g.
2776                  * enh_desc, tx_coe (e.g. that are passed through the
2777                  * platform) with the values from the HW capability
2778                  * register (if supported).
2779                  */
2780                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2781                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2782 
2783                 /* TXCOE doesn't work in thresh DMA mode */
2784                 if (priv->plat->force_thresh_dma_mode)
2785                         priv->plat->tx_coe = 0;
2786                 else
2787                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
2788 
2789                 if (priv->dma_cap.rx_coe_type2)
2790                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2791                 else if (priv->dma_cap.rx_coe_type1)
2792                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2793 
2794         } else
2795                 pr_info(" No HW DMA feature register supported");
2796 
2797         /* To use alternate (extended) or normal descriptor structures */
2798         stmmac_selec_desc_mode(priv);
2799 
2800         if (priv->plat->rx_coe) {
2801                 priv->hw->rx_csum = priv->plat->rx_coe;
2802                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2803                         priv->plat->rx_coe);
2804         }
2805         if (priv->plat->tx_coe)
2806                 pr_info(" TX Checksum insertion supported\n");
2807 
2808         if (priv->plat->pmt) {
2809                 pr_info(" Wake-Up On Lan supported\n");
2810                 device_set_wakeup_capable(priv->device, 1);
2811         }
2812 
2813         return 0;
2814 }
2815 
2816 /**
2817  * stmmac_dvr_probe
2818  * @device: device pointer
2819  * @plat_dat: platform data pointer
2820  * @res: stmmac resource pointer
2821  * Description: this is the main probe function used to
2822  * call the alloc_etherdev, allocate the priv structure.
2823  * Return:
2824  * returns 0 on success, otherwise errno.
2825  */
2826 int stmmac_dvr_probe(struct device *device,
2827                      struct plat_stmmacenet_data *plat_dat,
2828                      struct stmmac_resources *res)
2829 {
2830         int ret = 0;
2831         struct net_device *ndev = NULL;
2832         struct stmmac_priv *priv;
2833 
2834         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2835         if (!ndev)
2836                 return -ENOMEM;
2837 
2838         SET_NETDEV_DEV(ndev, device);
2839 
2840         priv = netdev_priv(ndev);
2841         priv->device = device;
2842         priv->dev = ndev;
2843 
2844         stmmac_set_ethtool_ops(ndev);
2845         priv->pause = pause;
2846         priv->plat = plat_dat;
2847         priv->ioaddr = res->addr;
2848         priv->dev->base_addr = (unsigned long)res->addr;
2849 
2850         priv->dev->irq = res->irq;
2851         priv->wol_irq = res->wol_irq;
2852         priv->lpi_irq = res->lpi_irq;
2853 
2854         if (res->mac)
2855                 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
2856 
2857         dev_set_drvdata(device, priv->dev);
2858 
2859         /* Verify driver arguments */
2860         stmmac_verify_args();
2861 
2862         /* Override with kernel parameters if supplied XXX CRS XXX
2863          * this needs to have multiple instances
2864          */
2865         if ((phyaddr >= 0) && (phyaddr <= 31))
2866                 priv->plat->phy_addr = phyaddr;
2867 
2868         priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
2869         if (IS_ERR(priv->stmmac_clk)) {
2870                 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
2871                          __func__);
2872                 /* If failed to obtain stmmac_clk and specific clk_csr value
2873                  * is NOT passed from the platform, probe fail.
2874                  */
2875                 if (!priv->plat->clk_csr) {
2876                         ret = PTR_ERR(priv->stmmac_clk);
2877                         goto error_clk_get;
2878                 } else {
2879                         priv->stmmac_clk = NULL;
2880                 }
2881         }
2882         clk_prepare_enable(priv->stmmac_clk);
2883 
2884         priv->pclk = devm_clk_get(priv->device, "pclk");
2885         if (IS_ERR(priv->pclk)) {
2886                 if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) {
2887                         ret = -EPROBE_DEFER;
2888                         goto error_pclk_get;
2889                 }
2890                 priv->pclk = NULL;
2891         }
2892         clk_prepare_enable(priv->pclk);
2893 
2894         priv->stmmac_rst = devm_reset_control_get(priv->device,
2895                                                   STMMAC_RESOURCE_NAME);
2896         if (IS_ERR(priv->stmmac_rst)) {
2897                 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
2898                         ret = -EPROBE_DEFER;
2899                         goto error_hw_init;
2900                 }
2901                 dev_info(priv->device, "no reset control found\n");
2902                 priv->stmmac_rst = NULL;
2903         }
2904         if (priv->stmmac_rst)
2905                 reset_control_deassert(priv->stmmac_rst);
2906 
2907         /* Init MAC and get the capabilities */
2908         ret = stmmac_hw_init(priv);
2909         if (ret)
2910                 goto error_hw_init;
2911 
2912         ndev->netdev_ops = &stmmac_netdev_ops;
2913 
2914         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2915                             NETIF_F_RXCSUM;
2916         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2917         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2918 #ifdef STMMAC_VLAN_TAG_USED
2919         /* Both mac100 and gmac support receive VLAN tag detection */
2920         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2921 #endif
2922         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2923 
2924         if (flow_ctrl)
2925                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
2926 
2927         /* Rx Watchdog is available in the COREs newer than the 3.40.
2928          * In some case, for example on bugged HW this feature
2929          * has to be disable and this can be done by passing the
2930          * riwt_off field from the platform.
2931          */
2932         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2933                 priv->use_riwt = 1;
2934                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2935         }
2936 
2937         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2938 
2939         spin_lock_init(&priv->lock);
2940         spin_lock_init(&priv->tx_lock);
2941 
2942         ret = register_netdev(ndev);
2943         if (ret) {
2944                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2945                 goto error_netdev_register;
2946         }
2947 
2948         /* If a specific clk_csr value is passed from the platform
2949          * this means that the CSR Clock Range selection cannot be
2950          * changed at run-time and it is fixed. Viceversa the driver'll try to
2951          * set the MDC clock dynamically according to the csr actual
2952          * clock input.
2953          */
2954         if (!priv->plat->clk_csr)
2955                 stmmac_clk_csr_set(priv);
2956         else
2957                 priv->clk_csr = priv->plat->clk_csr;
2958 
2959         stmmac_check_pcs_mode(priv);
2960 
2961         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2962             priv->pcs != STMMAC_PCS_RTBI) {
2963                 /* MDIO bus Registration */
2964                 ret = stmmac_mdio_register(ndev);
2965                 if (ret < 0) {
2966                         pr_debug("%s: MDIO bus (id: %d) registration failed",
2967                                  __func__, priv->plat->bus_id);
2968                         goto error_mdio_register;
2969                 }
2970         }
2971 
2972         return 0;
2973 
2974 error_mdio_register:
2975         unregister_netdev(ndev);
2976 error_netdev_register:
2977         netif_napi_del(&priv->napi);
2978 error_hw_init:
2979         clk_disable_unprepare(priv->pclk);
2980 error_pclk_get:
2981         clk_disable_unprepare(priv->stmmac_clk);
2982 error_clk_get:
2983         free_netdev(ndev);
2984 
2985         return ret;
2986 }
2987 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
2988 
2989 /**
2990  * stmmac_dvr_remove
2991  * @ndev: net device pointer
2992  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2993  * changes the link status, releases the DMA descriptor rings.
2994  */
2995 int stmmac_dvr_remove(struct net_device *ndev)
2996 {
2997         struct stmmac_priv *priv = netdev_priv(ndev);
2998 
2999         pr_info("%s:\n\tremoving driver", __func__);
3000 
3001         priv->hw->dma->stop_rx(priv->ioaddr);
3002         priv->hw->dma->stop_tx(priv->ioaddr);
3003 
3004         stmmac_set_mac(priv->ioaddr, false);
3005         netif_carrier_off(ndev);
3006         unregister_netdev(ndev);
3007         if (priv->stmmac_rst)
3008                 reset_control_assert(priv->stmmac_rst);
3009         clk_disable_unprepare(priv->pclk);
3010         clk_disable_unprepare(priv->stmmac_clk);
3011         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
3012             priv->pcs != STMMAC_PCS_RTBI)
3013                 stmmac_mdio_unregister(ndev);
3014         free_netdev(ndev);
3015 
3016         return 0;
3017 }
3018 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
3019 
3020 /**
3021  * stmmac_suspend - suspend callback
3022  * @ndev: net device pointer
3023  * Description: this is the function to suspend the device and it is called
3024  * by the platform driver to stop the network queue, release the resources,
3025  * program the PMT register (for WoL), clean and release driver resources.
3026  */
3027 int stmmac_suspend(struct net_device *ndev)
3028 {
3029         struct stmmac_priv *priv = netdev_priv(ndev);
3030         unsigned long flags;
3031 
3032         if (!ndev || !netif_running(ndev))
3033                 return 0;
3034 
3035         if (priv->phydev)
3036                 phy_stop(priv->phydev);
3037 
3038         spin_lock_irqsave(&priv->lock, flags);
3039 
3040         netif_device_detach(ndev);
3041         netif_stop_queue(ndev);
3042 
3043         napi_disable(&priv->napi);
3044 
3045         /* Stop TX/RX DMA */
3046         priv->hw->dma->stop_tx(priv->ioaddr);
3047         priv->hw->dma->stop_rx(priv->ioaddr);
3048 
3049         /* Enable Power down mode by programming the PMT regs */
3050         if (device_may_wakeup(priv->device)) {
3051                 priv->hw->mac->pmt(priv->hw, priv->wolopts);
3052                 priv->irq_wake = 1;
3053         } else {
3054                 stmmac_set_mac(priv->ioaddr, false);
3055                 pinctrl_pm_select_sleep_state(priv->device);
3056                 /* Disable clock in case of PWM is off */
3057                 clk_disable(priv->pclk);
3058                 clk_disable(priv->stmmac_clk);
3059         }
3060         spin_unlock_irqrestore(&priv->lock, flags);
3061 
3062         priv->oldlink = 0;
3063         priv->speed = 0;
3064         priv->oldduplex = -1;
3065         return 0;
3066 }
3067 EXPORT_SYMBOL_GPL(stmmac_suspend);
3068 
3069 /**
3070  * stmmac_resume - resume callback
3071  * @ndev: net device pointer
3072  * Description: when resume this function is invoked to setup the DMA and CORE
3073  * in a usable state.
3074  */
3075 int stmmac_resume(struct net_device *ndev)
3076 {
3077         struct stmmac_priv *priv = netdev_priv(ndev);
3078         unsigned long flags;
3079 
3080         if (!netif_running(ndev))
3081                 return 0;
3082 
3083         spin_lock_irqsave(&priv->lock, flags);
3084 
3085         /* Power Down bit, into the PM register, is cleared
3086          * automatically as soon as a magic packet or a Wake-up frame
3087          * is received. Anyway, it's better to manually clear
3088          * this bit because it can generate problems while resuming
3089          * from another devices (e.g. serial console).
3090          */
3091         if (device_may_wakeup(priv->device)) {
3092                 priv->hw->mac->pmt(priv->hw, 0);
3093                 priv->irq_wake = 0;
3094         } else {
3095                 pinctrl_pm_select_default_state(priv->device);
3096                 /* enable the clk prevously disabled */
3097                 clk_enable(priv->stmmac_clk);
3098                 clk_enable(priv->pclk);
3099                 /* reset the phy so that it's ready */
3100                 if (priv->mii)
3101                         stmmac_mdio_reset(priv->mii);
3102         }
3103 
3104         netif_device_attach(ndev);
3105 
3106         priv->cur_rx = 0;
3107         priv->dirty_rx = 0;
3108         priv->dirty_tx = 0;
3109         priv->cur_tx = 0;
3110         stmmac_clear_descriptors(priv);
3111 
3112         stmmac_hw_setup(ndev, false);
3113         stmmac_init_tx_coalesce(priv);
3114         stmmac_set_rx_mode(ndev);
3115 
3116         napi_enable(&priv->napi);
3117 
3118         netif_start_queue(ndev);
3119 
3120         spin_unlock_irqrestore(&priv->lock, flags);
3121 
3122         if (priv->phydev)
3123                 phy_start(priv->phydev);
3124 
3125         return 0;
3126 }
3127 EXPORT_SYMBOL_GPL(stmmac_resume);
3128 
3129 #ifndef MODULE
3130 static int __init stmmac_cmdline_opt(char *str)
3131 {
3132         char *opt;
3133 
3134         if (!str || !*str)
3135                 return -EINVAL;
3136         while ((opt = strsep(&str, ",")) != NULL) {
3137                 if (!strncmp(opt, "debug:", 6)) {
3138                         if (kstrtoint(opt + 6, 0, &debug))
3139                                 goto err;
3140                 } else if (!strncmp(opt, "phyaddr:", 8)) {
3141                         if (kstrtoint(opt + 8, 0, &phyaddr))
3142                                 goto err;
3143                 } else if (!strncmp(opt, "dma_txsize:", 11)) {
3144                         if (kstrtoint(opt + 11, 0, &dma_txsize))
3145                                 goto err;
3146                 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
3147                         if (kstrtoint(opt + 11, 0, &dma_rxsize))
3148                                 goto err;
3149                 } else if (!strncmp(opt, "buf_sz:", 7)) {
3150                         if (kstrtoint(opt + 7, 0, &buf_sz))
3151                                 goto err;
3152                 } else if (!strncmp(opt, "tc:", 3)) {
3153                         if (kstrtoint(opt + 3, 0, &tc))
3154                                 goto err;
3155                 } else if (!strncmp(opt, "watchdog:", 9)) {
3156                         if (kstrtoint(opt + 9, 0, &watchdog))
3157                                 goto err;
3158                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
3159                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
3160                                 goto err;
3161                 } else if (!strncmp(opt, "pause:", 6)) {
3162                         if (kstrtoint(opt + 6, 0, &pause))
3163                                 goto err;
3164                 } else if (!strncmp(opt, "eee_timer:", 10)) {
3165                         if (kstrtoint(opt + 10, 0, &eee_timer))
3166                                 goto err;
3167                 } else if (!strncmp(opt, "chain_mode:", 11)) {
3168                         if (kstrtoint(opt + 11, 0, &chain_mode))
3169                                 goto err;
3170                 }
3171         }
3172         return 0;
3173 
3174 err:
3175         pr_err("%s: ERROR broken module parameter conversion", __func__);
3176         return -EINVAL;
3177 }
3178 
3179 __setup("stmmaceth=", stmmac_cmdline_opt);
3180 #endif /* MODULE */
3181 
3182 static int __init stmmac_init(void)
3183 {
3184 #ifdef CONFIG_DEBUG_FS
3185         /* Create debugfs main directory if it doesn't exist yet */
3186         if (!stmmac_fs_dir) {
3187                 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
3188 
3189                 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
3190                         pr_err("ERROR %s, debugfs create directory failed\n",
3191                                STMMAC_RESOURCE_NAME);
3192 
3193                         return -ENOMEM;
3194                 }
3195         }
3196 #endif
3197 
3198         return 0;
3199 }
3200 
3201 static void __exit stmmac_exit(void)
3202 {
3203 #ifdef CONFIG_DEBUG_FS
3204         debugfs_remove_recursive(stmmac_fs_dir);
3205 #endif
3206 }
3207 
3208 module_init(stmmac_init)
3209 module_exit(stmmac_exit)
3210 
3211 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3212 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3213 MODULE_LICENSE("GPL");
3214 

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