Version:  2.0.40 2.2.26 2.4.37 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19

Linux/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

  1 /*******************************************************************************
  2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
  3   ST Ethernet IPs are built around a Synopsys IP Core.
  4 
  5         Copyright(C) 2007-2011 STMicroelectronics Ltd
  6 
  7   This program is free software; you can redistribute it and/or modify it
  8   under the terms and conditions of the GNU General Public License,
  9   version 2, as published by the Free Software Foundation.
 10 
 11   This program is distributed in the hope it will be useful, but WITHOUT
 12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 14   more details.
 15 
 16   You should have received a copy of the GNU General Public License along with
 17   this program; if not, write to the Free Software Foundation, Inc.,
 18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 19 
 20   The full GNU General Public License is included in this distribution in
 21   the file called "COPYING".
 22 
 23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
 24 
 25   Documentation available at:
 26         http://www.stlinux.com
 27   Support available at:
 28         https://bugzilla.stlinux.com/
 29 *******************************************************************************/
 30 
 31 #include <linux/clk.h>
 32 #include <linux/kernel.h>
 33 #include <linux/interrupt.h>
 34 #include <linux/ip.h>
 35 #include <linux/tcp.h>
 36 #include <linux/skbuff.h>
 37 #include <linux/ethtool.h>
 38 #include <linux/if_ether.h>
 39 #include <linux/crc32.h>
 40 #include <linux/mii.h>
 41 #include <linux/if.h>
 42 #include <linux/if_vlan.h>
 43 #include <linux/dma-mapping.h>
 44 #include <linux/slab.h>
 45 #include <linux/prefetch.h>
 46 #include <linux/pinctrl/consumer.h>
 47 #ifdef CONFIG_DEBUG_FS
 48 #include <linux/debugfs.h>
 49 #include <linux/seq_file.h>
 50 #endif /* CONFIG_DEBUG_FS */
 51 #include <linux/net_tstamp.h>
 52 #include "stmmac_ptp.h"
 53 #include "stmmac.h"
 54 #include <linux/reset.h>
 55 
 56 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
 57 
 58 /* Module parameters */
 59 #define TX_TIMEO        5000
 60 static int watchdog = TX_TIMEO;
 61 module_param(watchdog, int, S_IRUGO | S_IWUSR);
 62 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
 63 
 64 static int debug = -1;
 65 module_param(debug, int, S_IRUGO | S_IWUSR);
 66 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
 67 
 68 static int phyaddr = -1;
 69 module_param(phyaddr, int, S_IRUGO);
 70 MODULE_PARM_DESC(phyaddr, "Physical device address");
 71 
 72 #define DMA_TX_SIZE 256
 73 static int dma_txsize = DMA_TX_SIZE;
 74 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
 75 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
 76 
 77 #define DMA_RX_SIZE 256
 78 static int dma_rxsize = DMA_RX_SIZE;
 79 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
 80 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
 81 
 82 static int flow_ctrl = FLOW_OFF;
 83 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
 84 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
 85 
 86 static int pause = PAUSE_TIME;
 87 module_param(pause, int, S_IRUGO | S_IWUSR);
 88 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
 89 
 90 #define TC_DEFAULT 64
 91 static int tc = TC_DEFAULT;
 92 module_param(tc, int, S_IRUGO | S_IWUSR);
 93 MODULE_PARM_DESC(tc, "DMA threshold control value");
 94 
 95 #define DEFAULT_BUFSIZE 1536
 96 static int buf_sz = DEFAULT_BUFSIZE;
 97 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
 98 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
 99 
100 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
101                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
102                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
103 
104 #define STMMAC_DEFAULT_LPI_TIMER        1000
105 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
106 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
107 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
108 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
109 
110 /* By default the driver will use the ring mode to manage tx and rx descriptors
111  * but passing this value so user can force to use the chain instead of the ring
112  */
113 static unsigned int chain_mode;
114 module_param(chain_mode, int, S_IRUGO);
115 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
116 
117 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
118 
119 #ifdef CONFIG_DEBUG_FS
120 static int stmmac_init_fs(struct net_device *dev);
121 static void stmmac_exit_fs(void);
122 #endif
123 
124 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
125 
126 /**
127  * stmmac_verify_args - verify the driver parameters.
128  * Description: it checks the driver parameters and set a default in case of
129  * errors.
130  */
131 static void stmmac_verify_args(void)
132 {
133         if (unlikely(watchdog < 0))
134                 watchdog = TX_TIMEO;
135         if (unlikely(dma_rxsize < 0))
136                 dma_rxsize = DMA_RX_SIZE;
137         if (unlikely(dma_txsize < 0))
138                 dma_txsize = DMA_TX_SIZE;
139         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
140                 buf_sz = DEFAULT_BUFSIZE;
141         if (unlikely(flow_ctrl > 1))
142                 flow_ctrl = FLOW_AUTO;
143         else if (likely(flow_ctrl < 0))
144                 flow_ctrl = FLOW_OFF;
145         if (unlikely((pause < 0) || (pause > 0xffff)))
146                 pause = PAUSE_TIME;
147         if (eee_timer < 0)
148                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
149 }
150 
151 /**
152  * stmmac_clk_csr_set - dynamically set the MDC clock
153  * @priv: driver private structure
154  * Description: this is to dynamically set the MDC clock according to the csr
155  * clock input.
156  * Note:
157  *      If a specific clk_csr value is passed from the platform
158  *      this means that the CSR Clock Range selection cannot be
159  *      changed at run-time and it is fixed (as reported in the driver
160  *      documentation). Viceversa the driver will try to set the MDC
161  *      clock dynamically according to the actual clock input.
162  */
163 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
164 {
165         u32 clk_rate;
166 
167         clk_rate = clk_get_rate(priv->stmmac_clk);
168 
169         /* Platform provided default clk_csr would be assumed valid
170          * for all other cases except for the below mentioned ones.
171          * For values higher than the IEEE 802.3 specified frequency
172          * we can not estimate the proper divider as it is not known
173          * the frequency of clk_csr_i. So we do not change the default
174          * divider.
175          */
176         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
177                 if (clk_rate < CSR_F_35M)
178                         priv->clk_csr = STMMAC_CSR_20_35M;
179                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
180                         priv->clk_csr = STMMAC_CSR_35_60M;
181                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
182                         priv->clk_csr = STMMAC_CSR_60_100M;
183                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
184                         priv->clk_csr = STMMAC_CSR_100_150M;
185                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
186                         priv->clk_csr = STMMAC_CSR_150_250M;
187                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
188                         priv->clk_csr = STMMAC_CSR_250_300M;
189         }
190 }
191 
192 static void print_pkt(unsigned char *buf, int len)
193 {
194         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
195         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
196 }
197 
198 /* minimum number of free TX descriptors required to wake up TX process */
199 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
200 
201 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
202 {
203         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
204 }
205 
206 /**
207  * stmmac_hw_fix_mac_speed - callback for speed selection
208  * @priv: driver private structure
209  * Description: on some platforms (e.g. ST), some HW system configuraton
210  * registers have to be set according to the link speed negotiated.
211  */
212 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
213 {
214         struct phy_device *phydev = priv->phydev;
215 
216         if (likely(priv->plat->fix_mac_speed))
217                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
218 }
219 
220 /**
221  * stmmac_enable_eee_mode - check and enter in LPI mode
222  * @priv: driver private structure
223  * Description: this function is to verify and enter in LPI mode in case of
224  * EEE.
225  */
226 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
227 {
228         /* Check and enter in LPI mode */
229         if ((priv->dirty_tx == priv->cur_tx) &&
230             (priv->tx_path_in_lpi_mode == false))
231                 priv->hw->mac->set_eee_mode(priv->hw);
232 }
233 
234 /**
235  * stmmac_disable_eee_mode - disable and exit from LPI mode
236  * @priv: driver private structure
237  * Description: this function is to exit and disable EEE in case of
238  * LPI state is true. This is called by the xmit.
239  */
240 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
241 {
242         priv->hw->mac->reset_eee_mode(priv->hw);
243         del_timer_sync(&priv->eee_ctrl_timer);
244         priv->tx_path_in_lpi_mode = false;
245 }
246 
247 /**
248  * stmmac_eee_ctrl_timer - EEE TX SW timer.
249  * @arg : data hook
250  * Description:
251  *  if there is no data transfer and if we are not in LPI state,
252  *  then MAC Transmitter can be moved to LPI state.
253  */
254 static void stmmac_eee_ctrl_timer(unsigned long arg)
255 {
256         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
257 
258         stmmac_enable_eee_mode(priv);
259         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
260 }
261 
262 /**
263  * stmmac_eee_init - init EEE
264  * @priv: driver private structure
265  * Description:
266  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
267  *  can also manage EEE, this function enable the LPI state and start related
268  *  timer.
269  */
270 bool stmmac_eee_init(struct stmmac_priv *priv)
271 {
272         char *phy_bus_name = priv->plat->phy_bus_name;
273         unsigned long flags;
274         bool ret = false;
275 
276         /* Using PCS we cannot dial with the phy registers at this stage
277          * so we do not support extra feature like EEE.
278          */
279         if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
280             (priv->pcs == STMMAC_PCS_RTBI))
281                 goto out;
282 
283         /* Never init EEE in case of a switch is attached */
284         if (phy_bus_name && (!strcmp(phy_bus_name, "fixed")))
285                 goto out;
286 
287         /* MAC core supports the EEE feature. */
288         if (priv->dma_cap.eee) {
289                 int tx_lpi_timer = priv->tx_lpi_timer;
290 
291                 /* Check if the PHY supports EEE */
292                 if (phy_init_eee(priv->phydev, 1)) {
293                         /* To manage at run-time if the EEE cannot be supported
294                          * anymore (for example because the lp caps have been
295                          * changed).
296                          * In that case the driver disable own timers.
297                          */
298                         spin_lock_irqsave(&priv->lock, flags);
299                         if (priv->eee_active) {
300                                 pr_debug("stmmac: disable EEE\n");
301                                 del_timer_sync(&priv->eee_ctrl_timer);
302                                 priv->hw->mac->set_eee_timer(priv->hw, 0,
303                                                              tx_lpi_timer);
304                         }
305                         priv->eee_active = 0;
306                         spin_unlock_irqrestore(&priv->lock, flags);
307                         goto out;
308                 }
309                 /* Activate the EEE and start timers */
310                 spin_lock_irqsave(&priv->lock, flags);
311                 if (!priv->eee_active) {
312                         priv->eee_active = 1;
313                         init_timer(&priv->eee_ctrl_timer);
314                         priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
315                         priv->eee_ctrl_timer.data = (unsigned long)priv;
316                         priv->eee_ctrl_timer.expires = STMMAC_LPI_T(eee_timer);
317                         add_timer(&priv->eee_ctrl_timer);
318 
319                         priv->hw->mac->set_eee_timer(priv->hw,
320                                                      STMMAC_DEFAULT_LIT_LS,
321                                                      tx_lpi_timer);
322                 }
323                 /* Set HW EEE according to the speed */
324                 priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link);
325 
326                 ret = true;
327                 spin_unlock_irqrestore(&priv->lock, flags);
328 
329                 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
330         }
331 out:
332         return ret;
333 }
334 
335 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
336  * @priv: driver private structure
337  * @entry : descriptor index to be used.
338  * @skb : the socket buffer
339  * Description :
340  * This function will read timestamp from the descriptor & pass it to stack.
341  * and also perform some sanity checks.
342  */
343 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
344                                    unsigned int entry, struct sk_buff *skb)
345 {
346         struct skb_shared_hwtstamps shhwtstamp;
347         u64 ns;
348         void *desc = NULL;
349 
350         if (!priv->hwts_tx_en)
351                 return;
352 
353         /* exit if skb doesn't support hw tstamp */
354         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
355                 return;
356 
357         if (priv->adv_ts)
358                 desc = (priv->dma_etx + entry);
359         else
360                 desc = (priv->dma_tx + entry);
361 
362         /* check tx tstamp status */
363         if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
364                 return;
365 
366         /* get the valid tstamp */
367         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
368 
369         memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
370         shhwtstamp.hwtstamp = ns_to_ktime(ns);
371         /* pass tstamp to stack */
372         skb_tstamp_tx(skb, &shhwtstamp);
373 
374         return;
375 }
376 
377 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
378  * @priv: driver private structure
379  * @entry : descriptor index to be used.
380  * @skb : the socket buffer
381  * Description :
382  * This function will read received packet's timestamp from the descriptor
383  * and pass it to stack. It also perform some sanity checks.
384  */
385 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
386                                    unsigned int entry, struct sk_buff *skb)
387 {
388         struct skb_shared_hwtstamps *shhwtstamp = NULL;
389         u64 ns;
390         void *desc = NULL;
391 
392         if (!priv->hwts_rx_en)
393                 return;
394 
395         if (priv->adv_ts)
396                 desc = (priv->dma_erx + entry);
397         else
398                 desc = (priv->dma_rx + entry);
399 
400         /* exit if rx tstamp is not valid */
401         if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
402                 return;
403 
404         /* get valid tstamp */
405         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
406         shhwtstamp = skb_hwtstamps(skb);
407         memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
408         shhwtstamp->hwtstamp = ns_to_ktime(ns);
409 }
410 
411 /**
412  *  stmmac_hwtstamp_ioctl - control hardware timestamping.
413  *  @dev: device pointer.
414  *  @ifr: An IOCTL specefic structure, that can contain a pointer to
415  *  a proprietary structure used to pass information to the driver.
416  *  Description:
417  *  This function configures the MAC to enable/disable both outgoing(TX)
418  *  and incoming(RX) packets time stamping based on user input.
419  *  Return Value:
420  *  0 on success and an appropriate -ve integer on failure.
421  */
422 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
423 {
424         struct stmmac_priv *priv = netdev_priv(dev);
425         struct hwtstamp_config config;
426         struct timespec now;
427         u64 temp = 0;
428         u32 ptp_v2 = 0;
429         u32 tstamp_all = 0;
430         u32 ptp_over_ipv4_udp = 0;
431         u32 ptp_over_ipv6_udp = 0;
432         u32 ptp_over_ethernet = 0;
433         u32 snap_type_sel = 0;
434         u32 ts_master_en = 0;
435         u32 ts_event_en = 0;
436         u32 value = 0;
437 
438         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
439                 netdev_alert(priv->dev, "No support for HW time stamping\n");
440                 priv->hwts_tx_en = 0;
441                 priv->hwts_rx_en = 0;
442 
443                 return -EOPNOTSUPP;
444         }
445 
446         if (copy_from_user(&config, ifr->ifr_data,
447                            sizeof(struct hwtstamp_config)))
448                 return -EFAULT;
449 
450         pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
451                  __func__, config.flags, config.tx_type, config.rx_filter);
452 
453         /* reserved for future extensions */
454         if (config.flags)
455                 return -EINVAL;
456 
457         if (config.tx_type != HWTSTAMP_TX_OFF &&
458             config.tx_type != HWTSTAMP_TX_ON)
459                 return -ERANGE;
460 
461         if (priv->adv_ts) {
462                 switch (config.rx_filter) {
463                 case HWTSTAMP_FILTER_NONE:
464                         /* time stamp no incoming packet at all */
465                         config.rx_filter = HWTSTAMP_FILTER_NONE;
466                         break;
467 
468                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
469                         /* PTP v1, UDP, any kind of event packet */
470                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
471                         /* take time stamp for all event messages */
472                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
473 
474                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
475                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
476                         break;
477 
478                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
479                         /* PTP v1, UDP, Sync packet */
480                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
481                         /* take time stamp for SYNC messages only */
482                         ts_event_en = PTP_TCR_TSEVNTENA;
483 
484                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
485                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
486                         break;
487 
488                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
489                         /* PTP v1, UDP, Delay_req packet */
490                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
491                         /* take time stamp for Delay_Req messages only */
492                         ts_master_en = PTP_TCR_TSMSTRENA;
493                         ts_event_en = PTP_TCR_TSEVNTENA;
494 
495                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
496                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
497                         break;
498 
499                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
500                         /* PTP v2, UDP, any kind of event packet */
501                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
502                         ptp_v2 = PTP_TCR_TSVER2ENA;
503                         /* take time stamp for all event messages */
504                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
505 
506                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
507                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
508                         break;
509 
510                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
511                         /* PTP v2, UDP, Sync packet */
512                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
513                         ptp_v2 = PTP_TCR_TSVER2ENA;
514                         /* take time stamp for SYNC messages only */
515                         ts_event_en = PTP_TCR_TSEVNTENA;
516 
517                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
518                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
519                         break;
520 
521                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
522                         /* PTP v2, UDP, Delay_req packet */
523                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
524                         ptp_v2 = PTP_TCR_TSVER2ENA;
525                         /* take time stamp for Delay_Req messages only */
526                         ts_master_en = PTP_TCR_TSMSTRENA;
527                         ts_event_en = PTP_TCR_TSEVNTENA;
528 
529                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
530                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
531                         break;
532 
533                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
534                         /* PTP v2/802.AS1 any layer, any kind of event packet */
535                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
536                         ptp_v2 = PTP_TCR_TSVER2ENA;
537                         /* take time stamp for all event messages */
538                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
539 
540                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
541                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
542                         ptp_over_ethernet = PTP_TCR_TSIPENA;
543                         break;
544 
545                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
546                         /* PTP v2/802.AS1, any layer, Sync packet */
547                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
548                         ptp_v2 = PTP_TCR_TSVER2ENA;
549                         /* take time stamp for SYNC messages only */
550                         ts_event_en = PTP_TCR_TSEVNTENA;
551 
552                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
553                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
554                         ptp_over_ethernet = PTP_TCR_TSIPENA;
555                         break;
556 
557                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
558                         /* PTP v2/802.AS1, any layer, Delay_req packet */
559                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
560                         ptp_v2 = PTP_TCR_TSVER2ENA;
561                         /* take time stamp for Delay_Req messages only */
562                         ts_master_en = PTP_TCR_TSMSTRENA;
563                         ts_event_en = PTP_TCR_TSEVNTENA;
564 
565                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
566                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
567                         ptp_over_ethernet = PTP_TCR_TSIPENA;
568                         break;
569 
570                 case HWTSTAMP_FILTER_ALL:
571                         /* time stamp any incoming packet */
572                         config.rx_filter = HWTSTAMP_FILTER_ALL;
573                         tstamp_all = PTP_TCR_TSENALL;
574                         break;
575 
576                 default:
577                         return -ERANGE;
578                 }
579         } else {
580                 switch (config.rx_filter) {
581                 case HWTSTAMP_FILTER_NONE:
582                         config.rx_filter = HWTSTAMP_FILTER_NONE;
583                         break;
584                 default:
585                         /* PTP v1, UDP, any kind of event packet */
586                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
587                         break;
588                 }
589         }
590         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
591         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
592 
593         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
594                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
595         else {
596                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
597                          tstamp_all | ptp_v2 | ptp_over_ethernet |
598                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
599                          ts_master_en | snap_type_sel);
600 
601                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
602 
603                 /* program Sub Second Increment reg */
604                 priv->hw->ptp->config_sub_second_increment(priv->ioaddr);
605 
606                 /* calculate default added value:
607                  * formula is :
608                  * addend = (2^32)/freq_div_ratio;
609                  * where, freq_div_ratio = clk_ptp_ref_i/50MHz
610                  * hence, addend = ((2^32) * 50MHz)/clk_ptp_ref_i;
611                  * NOTE: clk_ptp_ref_i should be >= 50MHz to
612                  *       achive 20ns accuracy.
613                  *
614                  * 2^x * y == (y << x), hence
615                  * 2^32 * 50000000 ==> (50000000 << 32)
616                  */
617                 temp = (u64) (50000000ULL << 32);
618                 priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
619                 priv->hw->ptp->config_addend(priv->ioaddr,
620                                              priv->default_addend);
621 
622                 /* initialize system time */
623                 getnstimeofday(&now);
624                 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec,
625                                             now.tv_nsec);
626         }
627 
628         return copy_to_user(ifr->ifr_data, &config,
629                             sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
630 }
631 
632 /**
633  * stmmac_init_ptp - init PTP
634  * @priv: driver private structure
635  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
636  * This is done by looking at the HW cap. register.
637  * This function also registers the ptp driver.
638  */
639 static int stmmac_init_ptp(struct stmmac_priv *priv)
640 {
641         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
642                 return -EOPNOTSUPP;
643 
644         /* Fall-back to main clock in case of no PTP ref is passed */
645         priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref");
646         if (IS_ERR(priv->clk_ptp_ref)) {
647                 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk);
648                 priv->clk_ptp_ref = NULL;
649         } else {
650                 clk_prepare_enable(priv->clk_ptp_ref);
651                 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref);
652         }
653 
654         priv->adv_ts = 0;
655         if (priv->dma_cap.atime_stamp && priv->extend_desc)
656                 priv->adv_ts = 1;
657 
658         if (netif_msg_hw(priv) && priv->dma_cap.time_stamp)
659                 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
660 
661         if (netif_msg_hw(priv) && priv->adv_ts)
662                 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
663 
664         priv->hw->ptp = &stmmac_ptp;
665         priv->hwts_tx_en = 0;
666         priv->hwts_rx_en = 0;
667 
668         return stmmac_ptp_register(priv);
669 }
670 
671 static void stmmac_release_ptp(struct stmmac_priv *priv)
672 {
673         if (priv->clk_ptp_ref)
674                 clk_disable_unprepare(priv->clk_ptp_ref);
675         stmmac_ptp_unregister(priv);
676 }
677 
678 /**
679  * stmmac_adjust_link - adjusts the link parameters
680  * @dev: net device structure
681  * Description: this is the helper called by the physical abstraction layer
682  * drivers to communicate the phy link status. According the speed and duplex
683  * this driver can invoke registered glue-logic as well.
684  * It also invoke the eee initialization because it could happen when switch
685  * on different networks (that are eee capable).
686  */
687 static void stmmac_adjust_link(struct net_device *dev)
688 {
689         struct stmmac_priv *priv = netdev_priv(dev);
690         struct phy_device *phydev = priv->phydev;
691         unsigned long flags;
692         int new_state = 0;
693         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
694 
695         if (phydev == NULL)
696                 return;
697 
698         spin_lock_irqsave(&priv->lock, flags);
699 
700         if (phydev->link) {
701                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
702 
703                 /* Now we make sure that we can be in full duplex mode.
704                  * If not, we operate in half-duplex mode. */
705                 if (phydev->duplex != priv->oldduplex) {
706                         new_state = 1;
707                         if (!(phydev->duplex))
708                                 ctrl &= ~priv->hw->link.duplex;
709                         else
710                                 ctrl |= priv->hw->link.duplex;
711                         priv->oldduplex = phydev->duplex;
712                 }
713                 /* Flow Control operation */
714                 if (phydev->pause)
715                         priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex,
716                                                  fc, pause_time);
717 
718                 if (phydev->speed != priv->speed) {
719                         new_state = 1;
720                         switch (phydev->speed) {
721                         case 1000:
722                                 if (likely(priv->plat->has_gmac))
723                                         ctrl &= ~priv->hw->link.port;
724                                 stmmac_hw_fix_mac_speed(priv);
725                                 break;
726                         case 100:
727                         case 10:
728                                 if (priv->plat->has_gmac) {
729                                         ctrl |= priv->hw->link.port;
730                                         if (phydev->speed == SPEED_100) {
731                                                 ctrl |= priv->hw->link.speed;
732                                         } else {
733                                                 ctrl &= ~(priv->hw->link.speed);
734                                         }
735                                 } else {
736                                         ctrl &= ~priv->hw->link.port;
737                                 }
738                                 stmmac_hw_fix_mac_speed(priv);
739                                 break;
740                         default:
741                                 if (netif_msg_link(priv))
742                                         pr_warn("%s: Speed (%d) not 10/100\n",
743                                                 dev->name, phydev->speed);
744                                 break;
745                         }
746 
747                         priv->speed = phydev->speed;
748                 }
749 
750                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
751 
752                 if (!priv->oldlink) {
753                         new_state = 1;
754                         priv->oldlink = 1;
755                 }
756         } else if (priv->oldlink) {
757                 new_state = 1;
758                 priv->oldlink = 0;
759                 priv->speed = 0;
760                 priv->oldduplex = -1;
761         }
762 
763         if (new_state && netif_msg_link(priv))
764                 phy_print_status(phydev);
765 
766         spin_unlock_irqrestore(&priv->lock, flags);
767 
768         /* At this stage, it could be needed to setup the EEE or adjust some
769          * MAC related HW registers.
770          */
771         priv->eee_enabled = stmmac_eee_init(priv);
772 }
773 
774 /**
775  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
776  * @priv: driver private structure
777  * Description: this is to verify if the HW supports the PCS.
778  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
779  * configured for the TBI, RTBI, or SGMII PHY interface.
780  */
781 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
782 {
783         int interface = priv->plat->interface;
784 
785         if (priv->dma_cap.pcs) {
786                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
787                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
788                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
789                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
790                         pr_debug("STMMAC: PCS RGMII support enable\n");
791                         priv->pcs = STMMAC_PCS_RGMII;
792                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
793                         pr_debug("STMMAC: PCS SGMII support enable\n");
794                         priv->pcs = STMMAC_PCS_SGMII;
795                 }
796         }
797 }
798 
799 /**
800  * stmmac_init_phy - PHY initialization
801  * @dev: net device structure
802  * Description: it initializes the driver's PHY state, and attaches the PHY
803  * to the mac driver.
804  *  Return value:
805  *  0 on success
806  */
807 static int stmmac_init_phy(struct net_device *dev)
808 {
809         struct stmmac_priv *priv = netdev_priv(dev);
810         struct phy_device *phydev;
811         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
812         char bus_id[MII_BUS_ID_SIZE];
813         int interface = priv->plat->interface;
814         int max_speed = priv->plat->max_speed;
815         priv->oldlink = 0;
816         priv->speed = 0;
817         priv->oldduplex = -1;
818 
819         if (priv->plat->phy_bus_name)
820                 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
821                          priv->plat->phy_bus_name, priv->plat->bus_id);
822         else
823                 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
824                          priv->plat->bus_id);
825 
826         snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
827                  priv->plat->phy_addr);
828         pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id_fmt);
829 
830         phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
831 
832         if (IS_ERR(phydev)) {
833                 pr_err("%s: Could not attach to PHY\n", dev->name);
834                 return PTR_ERR(phydev);
835         }
836 
837         /* Stop Advertising 1000BASE Capability if interface is not GMII */
838         if ((interface == PHY_INTERFACE_MODE_MII) ||
839             (interface == PHY_INTERFACE_MODE_RMII) ||
840                 (max_speed < 1000 && max_speed > 0))
841                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
842                                          SUPPORTED_1000baseT_Full);
843 
844         /*
845          * Broken HW is sometimes missing the pull-up resistor on the
846          * MDIO line, which results in reads to non-existent devices returning
847          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
848          * device as well.
849          * Note: phydev->phy_id is the result of reading the UID PHY registers.
850          */
851         if (phydev->phy_id == 0) {
852                 phy_disconnect(phydev);
853                 return -ENODEV;
854         }
855         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
856                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
857 
858         priv->phydev = phydev;
859 
860         return 0;
861 }
862 
863 /**
864  * stmmac_display_ring - display ring
865  * @head: pointer to the head of the ring passed.
866  * @size: size of the ring.
867  * @extend_desc: to verify if extended descriptors are used.
868  * Description: display the control/status and buffer descriptors.
869  */
870 static void stmmac_display_ring(void *head, int size, int extend_desc)
871 {
872         int i;
873         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
874         struct dma_desc *p = (struct dma_desc *)head;
875 
876         for (i = 0; i < size; i++) {
877                 u64 x;
878                 if (extend_desc) {
879                         x = *(u64 *) ep;
880                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
881                                 i, (unsigned int)virt_to_phys(ep),
882                                 (unsigned int)x, (unsigned int)(x >> 32),
883                                 ep->basic.des2, ep->basic.des3);
884                         ep++;
885                 } else {
886                         x = *(u64 *) p;
887                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
888                                 i, (unsigned int)virt_to_phys(p),
889                                 (unsigned int)x, (unsigned int)(x >> 32),
890                                 p->des2, p->des3);
891                         p++;
892                 }
893                 pr_info("\n");
894         }
895 }
896 
897 static void stmmac_display_rings(struct stmmac_priv *priv)
898 {
899         unsigned int txsize = priv->dma_tx_size;
900         unsigned int rxsize = priv->dma_rx_size;
901 
902         if (priv->extend_desc) {
903                 pr_info("Extended RX descriptor ring:\n");
904                 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
905                 pr_info("Extended TX descriptor ring:\n");
906                 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
907         } else {
908                 pr_info("RX descriptor ring:\n");
909                 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
910                 pr_info("TX descriptor ring:\n");
911                 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
912         }
913 }
914 
915 static int stmmac_set_bfsize(int mtu, int bufsize)
916 {
917         int ret = bufsize;
918 
919         if (mtu >= BUF_SIZE_4KiB)
920                 ret = BUF_SIZE_8KiB;
921         else if (mtu >= BUF_SIZE_2KiB)
922                 ret = BUF_SIZE_4KiB;
923         else if (mtu > DEFAULT_BUFSIZE)
924                 ret = BUF_SIZE_2KiB;
925         else
926                 ret = DEFAULT_BUFSIZE;
927 
928         return ret;
929 }
930 
931 /**
932  * stmmac_clear_descriptors - clear descriptors
933  * @priv: driver private structure
934  * Description: this function is called to clear the tx and rx descriptors
935  * in case of both basic and extended descriptors are used.
936  */
937 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
938 {
939         int i;
940         unsigned int txsize = priv->dma_tx_size;
941         unsigned int rxsize = priv->dma_rx_size;
942 
943         /* Clear the Rx/Tx descriptors */
944         for (i = 0; i < rxsize; i++)
945                 if (priv->extend_desc)
946                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
947                                                      priv->use_riwt, priv->mode,
948                                                      (i == rxsize - 1));
949                 else
950                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
951                                                      priv->use_riwt, priv->mode,
952                                                      (i == rxsize - 1));
953         for (i = 0; i < txsize; i++)
954                 if (priv->extend_desc)
955                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
956                                                      priv->mode,
957                                                      (i == txsize - 1));
958                 else
959                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
960                                                      priv->mode,
961                                                      (i == txsize - 1));
962 }
963 
964 /**
965  * stmmac_init_rx_buffers - init the RX descriptor buffer.
966  * @priv: driver private structure
967  * @p: descriptor pointer
968  * @i: descriptor index
969  * @flags: gfp flag.
970  * Description: this function is called to allocate a receive buffer, perform
971  * the DMA mapping and init the descriptor.
972  */
973 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
974                                   int i, gfp_t flags)
975 {
976         struct sk_buff *skb;
977 
978         skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN,
979                                  flags);
980         if (!skb) {
981                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
982                 return -ENOMEM;
983         }
984         skb_reserve(skb, NET_IP_ALIGN);
985         priv->rx_skbuff[i] = skb;
986         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
987                                                 priv->dma_buf_sz,
988                                                 DMA_FROM_DEVICE);
989         if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
990                 pr_err("%s: DMA mapping error\n", __func__);
991                 dev_kfree_skb_any(skb);
992                 return -EINVAL;
993         }
994 
995         p->des2 = priv->rx_skbuff_dma[i];
996 
997         if ((priv->hw->mode->init_desc3) &&
998             (priv->dma_buf_sz == BUF_SIZE_16KiB))
999                 priv->hw->mode->init_desc3(p);
1000 
1001         return 0;
1002 }
1003 
1004 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
1005 {
1006         if (priv->rx_skbuff[i]) {
1007                 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1008                                  priv->dma_buf_sz, DMA_FROM_DEVICE);
1009                 dev_kfree_skb_any(priv->rx_skbuff[i]);
1010         }
1011         priv->rx_skbuff[i] = NULL;
1012 }
1013 
1014 /**
1015  * init_dma_desc_rings - init the RX/TX descriptor rings
1016  * @dev: net device structure
1017  * @flags: gfp flag.
1018  * Description: this function initializes the DMA RX/TX descriptors
1019  * and allocates the socket buffers. It suppors the chained and ring
1020  * modes.
1021  */
1022 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1023 {
1024         int i;
1025         struct stmmac_priv *priv = netdev_priv(dev);
1026         unsigned int txsize = priv->dma_tx_size;
1027         unsigned int rxsize = priv->dma_rx_size;
1028         unsigned int bfsize = 0;
1029         int ret = -ENOMEM;
1030 
1031         if (priv->hw->mode->set_16kib_bfsize)
1032                 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1033 
1034         if (bfsize < BUF_SIZE_16KiB)
1035                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1036 
1037         priv->dma_buf_sz = bfsize;
1038 
1039         if (netif_msg_probe(priv))
1040                 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__,
1041                          txsize, rxsize, bfsize);
1042 
1043         if (netif_msg_probe(priv)) {
1044                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1045                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1046 
1047                 /* RX INITIALIZATION */
1048                 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1049         }
1050         for (i = 0; i < rxsize; i++) {
1051                 struct dma_desc *p;
1052                 if (priv->extend_desc)
1053                         p = &((priv->dma_erx + i)->basic);
1054                 else
1055                         p = priv->dma_rx + i;
1056 
1057                 ret = stmmac_init_rx_buffers(priv, p, i, flags);
1058                 if (ret)
1059                         goto err_init_rx_buffers;
1060 
1061                 if (netif_msg_probe(priv))
1062                         pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1063                                  priv->rx_skbuff[i]->data,
1064                                  (unsigned int)priv->rx_skbuff_dma[i]);
1065         }
1066         priv->cur_rx = 0;
1067         priv->dirty_rx = (unsigned int)(i - rxsize);
1068         buf_sz = bfsize;
1069 
1070         /* Setup the chained descriptor addresses */
1071         if (priv->mode == STMMAC_CHAIN_MODE) {
1072                 if (priv->extend_desc) {
1073                         priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1074                                              rxsize, 1);
1075                         priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1076                                              txsize, 1);
1077                 } else {
1078                         priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1079                                              rxsize, 0);
1080                         priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1081                                              txsize, 0);
1082                 }
1083         }
1084 
1085         /* TX INITIALIZATION */
1086         for (i = 0; i < txsize; i++) {
1087                 struct dma_desc *p;
1088                 if (priv->extend_desc)
1089                         p = &((priv->dma_etx + i)->basic);
1090                 else
1091                         p = priv->dma_tx + i;
1092                 p->des2 = 0;
1093                 priv->tx_skbuff_dma[i].buf = 0;
1094                 priv->tx_skbuff_dma[i].map_as_page = false;
1095                 priv->tx_skbuff[i] = NULL;
1096         }
1097 
1098         priv->dirty_tx = 0;
1099         priv->cur_tx = 0;
1100 
1101         stmmac_clear_descriptors(priv);
1102 
1103         if (netif_msg_hw(priv))
1104                 stmmac_display_rings(priv);
1105 
1106         return 0;
1107 err_init_rx_buffers:
1108         while (--i >= 0)
1109                 stmmac_free_rx_buffers(priv, i);
1110         return ret;
1111 }
1112 
1113 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1114 {
1115         int i;
1116 
1117         for (i = 0; i < priv->dma_rx_size; i++)
1118                 stmmac_free_rx_buffers(priv, i);
1119 }
1120 
1121 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1122 {
1123         int i;
1124 
1125         for (i = 0; i < priv->dma_tx_size; i++) {
1126                 struct dma_desc *p;
1127 
1128                 if (priv->extend_desc)
1129                         p = &((priv->dma_etx + i)->basic);
1130                 else
1131                         p = priv->dma_tx + i;
1132 
1133                 if (priv->tx_skbuff_dma[i].buf) {
1134                         if (priv->tx_skbuff_dma[i].map_as_page)
1135                                 dma_unmap_page(priv->device,
1136                                                priv->tx_skbuff_dma[i].buf,
1137                                                priv->hw->desc->get_tx_len(p),
1138                                                DMA_TO_DEVICE);
1139                         else
1140                                 dma_unmap_single(priv->device,
1141                                                  priv->tx_skbuff_dma[i].buf,
1142                                                  priv->hw->desc->get_tx_len(p),
1143                                                  DMA_TO_DEVICE);
1144                 }
1145 
1146                 if (priv->tx_skbuff[i] != NULL) {
1147                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1148                         priv->tx_skbuff[i] = NULL;
1149                         priv->tx_skbuff_dma[i].buf = 0;
1150                         priv->tx_skbuff_dma[i].map_as_page = false;
1151                 }
1152         }
1153 }
1154 
1155 /**
1156  * alloc_dma_desc_resources - alloc TX/RX resources.
1157  * @priv: private structure
1158  * Description: according to which descriptor can be used (extend or basic)
1159  * this function allocates the resources for TX and RX paths. In case of
1160  * reception, for example, it pre-allocated the RX socket buffer in order to
1161  * allow zero-copy mechanism.
1162  */
1163 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1164 {
1165         unsigned int txsize = priv->dma_tx_size;
1166         unsigned int rxsize = priv->dma_rx_size;
1167         int ret = -ENOMEM;
1168 
1169         priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
1170                                             GFP_KERNEL);
1171         if (!priv->rx_skbuff_dma)
1172                 return -ENOMEM;
1173 
1174         priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
1175                                         GFP_KERNEL);
1176         if (!priv->rx_skbuff)
1177                 goto err_rx_skbuff;
1178 
1179         priv->tx_skbuff_dma = kmalloc_array(txsize,
1180                                             sizeof(*priv->tx_skbuff_dma),
1181                                             GFP_KERNEL);
1182         if (!priv->tx_skbuff_dma)
1183                 goto err_tx_skbuff_dma;
1184 
1185         priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
1186                                         GFP_KERNEL);
1187         if (!priv->tx_skbuff)
1188                 goto err_tx_skbuff;
1189 
1190         if (priv->extend_desc) {
1191                 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
1192                                                    sizeof(struct
1193                                                           dma_extended_desc),
1194                                                    &priv->dma_rx_phy,
1195                                                    GFP_KERNEL);
1196                 if (!priv->dma_erx)
1197                         goto err_dma;
1198 
1199                 priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
1200                                                    sizeof(struct
1201                                                           dma_extended_desc),
1202                                                    &priv->dma_tx_phy,
1203                                                    GFP_KERNEL);
1204                 if (!priv->dma_etx) {
1205                         dma_free_coherent(priv->device, priv->dma_rx_size *
1206                                         sizeof(struct dma_extended_desc),
1207                                         priv->dma_erx, priv->dma_rx_phy);
1208                         goto err_dma;
1209                 }
1210         } else {
1211                 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
1212                                                   sizeof(struct dma_desc),
1213                                                   &priv->dma_rx_phy,
1214                                                   GFP_KERNEL);
1215                 if (!priv->dma_rx)
1216                         goto err_dma;
1217 
1218                 priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
1219                                                   sizeof(struct dma_desc),
1220                                                   &priv->dma_tx_phy,
1221                                                   GFP_KERNEL);
1222                 if (!priv->dma_tx) {
1223                         dma_free_coherent(priv->device, priv->dma_rx_size *
1224                                         sizeof(struct dma_desc),
1225                                         priv->dma_rx, priv->dma_rx_phy);
1226                         goto err_dma;
1227                 }
1228         }
1229 
1230         return 0;
1231 
1232 err_dma:
1233         kfree(priv->tx_skbuff);
1234 err_tx_skbuff:
1235         kfree(priv->tx_skbuff_dma);
1236 err_tx_skbuff_dma:
1237         kfree(priv->rx_skbuff);
1238 err_rx_skbuff:
1239         kfree(priv->rx_skbuff_dma);
1240         return ret;
1241 }
1242 
1243 static void free_dma_desc_resources(struct stmmac_priv *priv)
1244 {
1245         /* Release the DMA TX/RX socket buffers */
1246         dma_free_rx_skbufs(priv);
1247         dma_free_tx_skbufs(priv);
1248 
1249         /* Free DMA regions of consistent memory previously allocated */
1250         if (!priv->extend_desc) {
1251                 dma_free_coherent(priv->device,
1252                                   priv->dma_tx_size * sizeof(struct dma_desc),
1253                                   priv->dma_tx, priv->dma_tx_phy);
1254                 dma_free_coherent(priv->device,
1255                                   priv->dma_rx_size * sizeof(struct dma_desc),
1256                                   priv->dma_rx, priv->dma_rx_phy);
1257         } else {
1258                 dma_free_coherent(priv->device, priv->dma_tx_size *
1259                                   sizeof(struct dma_extended_desc),
1260                                   priv->dma_etx, priv->dma_tx_phy);
1261                 dma_free_coherent(priv->device, priv->dma_rx_size *
1262                                   sizeof(struct dma_extended_desc),
1263                                   priv->dma_erx, priv->dma_rx_phy);
1264         }
1265         kfree(priv->rx_skbuff_dma);
1266         kfree(priv->rx_skbuff);
1267         kfree(priv->tx_skbuff_dma);
1268         kfree(priv->tx_skbuff);
1269 }
1270 
1271 /**
1272  *  stmmac_dma_operation_mode - HW DMA operation mode
1273  *  @priv: driver private structure
1274  *  Description: it is used for configuring the DMA operation mode register in
1275  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1276  */
1277 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1278 {
1279         if (priv->plat->force_thresh_dma_mode)
1280                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc);
1281         else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1282                 /*
1283                  * In case of GMAC, SF mode can be enabled
1284                  * to perform the TX COE in HW. This depends on:
1285                  * 1) TX COE if actually supported
1286                  * 2) There is no bugged Jumbo frame support
1287                  *    that needs to not insert csum in the TDES.
1288                  */
1289                 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE);
1290                 tc = SF_DMA_MODE;
1291         } else
1292                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1293 }
1294 
1295 /**
1296  * stmmac_tx_clean - to manage the transmission completion
1297  * @priv: driver private structure
1298  * Description: it reclaims the transmit resources after transmission completes.
1299  */
1300 static void stmmac_tx_clean(struct stmmac_priv *priv)
1301 {
1302         unsigned int txsize = priv->dma_tx_size;
1303 
1304         spin_lock(&priv->tx_lock);
1305 
1306         priv->xstats.tx_clean++;
1307 
1308         while (priv->dirty_tx != priv->cur_tx) {
1309                 int last;
1310                 unsigned int entry = priv->dirty_tx % txsize;
1311                 struct sk_buff *skb = priv->tx_skbuff[entry];
1312                 struct dma_desc *p;
1313 
1314                 if (priv->extend_desc)
1315                         p = (struct dma_desc *)(priv->dma_etx + entry);
1316                 else
1317                         p = priv->dma_tx + entry;
1318 
1319                 /* Check if the descriptor is owned by the DMA. */
1320                 if (priv->hw->desc->get_tx_owner(p))
1321                         break;
1322 
1323                 /* Verify tx error by looking at the last segment. */
1324                 last = priv->hw->desc->get_tx_ls(p);
1325                 if (likely(last)) {
1326                         int tx_error =
1327                             priv->hw->desc->tx_status(&priv->dev->stats,
1328                                                       &priv->xstats, p,
1329                                                       priv->ioaddr);
1330                         if (likely(tx_error == 0)) {
1331                                 priv->dev->stats.tx_packets++;
1332                                 priv->xstats.tx_pkt_n++;
1333                         } else
1334                                 priv->dev->stats.tx_errors++;
1335 
1336                         stmmac_get_tx_hwtstamp(priv, entry, skb);
1337                 }
1338                 if (netif_msg_tx_done(priv))
1339                         pr_debug("%s: curr %d, dirty %d\n", __func__,
1340                                  priv->cur_tx, priv->dirty_tx);
1341 
1342                 if (likely(priv->tx_skbuff_dma[entry].buf)) {
1343                         if (priv->tx_skbuff_dma[entry].map_as_page)
1344                                 dma_unmap_page(priv->device,
1345                                                priv->tx_skbuff_dma[entry].buf,
1346                                                priv->hw->desc->get_tx_len(p),
1347                                                DMA_TO_DEVICE);
1348                         else
1349                                 dma_unmap_single(priv->device,
1350                                                  priv->tx_skbuff_dma[entry].buf,
1351                                                  priv->hw->desc->get_tx_len(p),
1352                                                  DMA_TO_DEVICE);
1353                         priv->tx_skbuff_dma[entry].buf = 0;
1354                         priv->tx_skbuff_dma[entry].map_as_page = false;
1355                 }
1356                 priv->hw->mode->clean_desc3(priv, p);
1357 
1358                 if (likely(skb != NULL)) {
1359                         dev_consume_skb_any(skb);
1360                         priv->tx_skbuff[entry] = NULL;
1361                 }
1362 
1363                 priv->hw->desc->release_tx_desc(p, priv->mode);
1364 
1365                 priv->dirty_tx++;
1366         }
1367         if (unlikely(netif_queue_stopped(priv->dev) &&
1368                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
1369                 netif_tx_lock(priv->dev);
1370                 if (netif_queue_stopped(priv->dev) &&
1371                     stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
1372                         if (netif_msg_tx_done(priv))
1373                                 pr_debug("%s: restart transmit\n", __func__);
1374                         netif_wake_queue(priv->dev);
1375                 }
1376                 netif_tx_unlock(priv->dev);
1377         }
1378 
1379         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1380                 stmmac_enable_eee_mode(priv);
1381                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1382         }
1383         spin_unlock(&priv->tx_lock);
1384 }
1385 
1386 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1387 {
1388         priv->hw->dma->enable_dma_irq(priv->ioaddr);
1389 }
1390 
1391 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1392 {
1393         priv->hw->dma->disable_dma_irq(priv->ioaddr);
1394 }
1395 
1396 /**
1397  * stmmac_tx_err - to manage the tx error
1398  * @priv: driver private structure
1399  * Description: it cleans the descriptors and restarts the transmission
1400  * in case of transmission errors.
1401  */
1402 static void stmmac_tx_err(struct stmmac_priv *priv)
1403 {
1404         int i;
1405         int txsize = priv->dma_tx_size;
1406         netif_stop_queue(priv->dev);
1407 
1408         priv->hw->dma->stop_tx(priv->ioaddr);
1409         dma_free_tx_skbufs(priv);
1410         for (i = 0; i < txsize; i++)
1411                 if (priv->extend_desc)
1412                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1413                                                      priv->mode,
1414                                                      (i == txsize - 1));
1415                 else
1416                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1417                                                      priv->mode,
1418                                                      (i == txsize - 1));
1419         priv->dirty_tx = 0;
1420         priv->cur_tx = 0;
1421         priv->hw->dma->start_tx(priv->ioaddr);
1422 
1423         priv->dev->stats.tx_errors++;
1424         netif_wake_queue(priv->dev);
1425 }
1426 
1427 /**
1428  * stmmac_dma_interrupt - DMA ISR
1429  * @priv: driver private structure
1430  * Description: this is the DMA ISR. It is called by the main ISR.
1431  * It calls the dwmac dma routine and schedule poll method in case of some
1432  * work can be done.
1433  */
1434 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1435 {
1436         int status;
1437 
1438         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1439         if (likely((status & handle_rx)) || (status & handle_tx)) {
1440                 if (likely(napi_schedule_prep(&priv->napi))) {
1441                         stmmac_disable_dma_irq(priv);
1442                         __napi_schedule(&priv->napi);
1443                 }
1444         }
1445         if (unlikely(status & tx_hard_error_bump_tc)) {
1446                 /* Try to bump up the dma threshold on this failure */
1447                 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
1448                         tc += 64;
1449                         priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1450                         priv->xstats.threshold = tc;
1451                 }
1452         } else if (unlikely(status == tx_hard_error))
1453                 stmmac_tx_err(priv);
1454 }
1455 
1456 /**
1457  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1458  * @priv: driver private structure
1459  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1460  */
1461 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1462 {
1463         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1464             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1465 
1466         dwmac_mmc_intr_all_mask(priv->ioaddr);
1467 
1468         if (priv->dma_cap.rmon) {
1469                 dwmac_mmc_ctrl(priv->ioaddr, mode);
1470                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1471         } else
1472                 pr_info(" No MAC Management Counters available\n");
1473 }
1474 
1475 /**
1476  * stmmac_get_synopsys_id - return the SYINID.
1477  * @priv: driver private structure
1478  * Description: this simple function is to decode and return the SYINID
1479  * starting from the HW core register.
1480  */
1481 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1482 {
1483         u32 hwid = priv->hw->synopsys_uid;
1484 
1485         /* Check Synopsys Id (not available on old chips) */
1486         if (likely(hwid)) {
1487                 u32 uid = ((hwid & 0x0000ff00) >> 8);
1488                 u32 synid = (hwid & 0x000000ff);
1489 
1490                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1491                         uid, synid);
1492 
1493                 return synid;
1494         }
1495         return 0;
1496 }
1497 
1498 /**
1499  * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1500  * @priv: driver private structure
1501  * Description: select the Enhanced/Alternate or Normal descriptors.
1502  * In case of Enhanced/Alternate, it checks if the extended descriptors are
1503  * supported by the HW capability register.
1504  */
1505 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1506 {
1507         if (priv->plat->enh_desc) {
1508                 pr_info(" Enhanced/Alternate descriptors\n");
1509 
1510                 /* GMAC older than 3.50 has no extended descriptors */
1511                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1512                         pr_info("\tEnabled extended descriptors\n");
1513                         priv->extend_desc = 1;
1514                 } else
1515                         pr_warn("Extended descriptors not supported\n");
1516 
1517                 priv->hw->desc = &enh_desc_ops;
1518         } else {
1519                 pr_info(" Normal descriptors\n");
1520                 priv->hw->desc = &ndesc_ops;
1521         }
1522 }
1523 
1524 /**
1525  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1526  * @priv: driver private structure
1527  * Description:
1528  *  new GMAC chip generations have a new register to indicate the
1529  *  presence of the optional feature/functions.
1530  *  This can be also used to override the value passed through the
1531  *  platform and necessary for old MAC10/100 and GMAC chips.
1532  */
1533 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1534 {
1535         u32 hw_cap = 0;
1536 
1537         if (priv->hw->dma->get_hw_feature) {
1538                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1539 
1540                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1541                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1542                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1543                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1544                 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1545                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1546                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1547                 priv->dma_cap.pmt_remote_wake_up =
1548                     (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1549                 priv->dma_cap.pmt_magic_frame =
1550                     (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1551                 /* MMC */
1552                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1553                 /* IEEE 1588-2002 */
1554                 priv->dma_cap.time_stamp =
1555                     (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1556                 /* IEEE 1588-2008 */
1557                 priv->dma_cap.atime_stamp =
1558                     (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1559                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1560                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1561                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1562                 /* TX and RX csum */
1563                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1564                 priv->dma_cap.rx_coe_type1 =
1565                     (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1566                 priv->dma_cap.rx_coe_type2 =
1567                     (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1568                 priv->dma_cap.rxfifo_over_2048 =
1569                     (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1570                 /* TX and RX number of channels */
1571                 priv->dma_cap.number_rx_channel =
1572                     (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1573                 priv->dma_cap.number_tx_channel =
1574                     (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1575                 /* Alternate (enhanced) DESC mode */
1576                 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1577         }
1578 
1579         return hw_cap;
1580 }
1581 
1582 /**
1583  * stmmac_check_ether_addr - check if the MAC addr is valid
1584  * @priv: driver private structure
1585  * Description:
1586  * it is to verify if the MAC address is valid, in case of failures it
1587  * generates a random MAC address
1588  */
1589 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1590 {
1591         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1592                 priv->hw->mac->get_umac_addr(priv->hw,
1593                                              priv->dev->dev_addr, 0);
1594                 if (!is_valid_ether_addr(priv->dev->dev_addr))
1595                         eth_hw_addr_random(priv->dev);
1596                 pr_info("%s: device MAC address %pM\n", priv->dev->name,
1597                         priv->dev->dev_addr);
1598         }
1599 }
1600 
1601 /**
1602  * stmmac_init_dma_engine - DMA init.
1603  * @priv: driver private structure
1604  * Description:
1605  * It inits the DMA invoking the specific MAC/GMAC callback.
1606  * Some DMA parameters can be passed from the platform;
1607  * in case of these are not passed a default is kept for the MAC or GMAC.
1608  */
1609 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1610 {
1611         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1612         int mixed_burst = 0;
1613         int atds = 0;
1614 
1615         if (priv->plat->dma_cfg) {
1616                 pbl = priv->plat->dma_cfg->pbl;
1617                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1618                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1619                 burst_len = priv->plat->dma_cfg->burst_len;
1620         }
1621 
1622         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1623                 atds = 1;
1624 
1625         return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1626                                    burst_len, priv->dma_tx_phy,
1627                                    priv->dma_rx_phy, atds);
1628 }
1629 
1630 /**
1631  * stmmac_tx_timer - mitigation sw timer for tx.
1632  * @data: data pointer
1633  * Description:
1634  * This is the timer handler to directly invoke the stmmac_tx_clean.
1635  */
1636 static void stmmac_tx_timer(unsigned long data)
1637 {
1638         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1639 
1640         stmmac_tx_clean(priv);
1641 }
1642 
1643 /**
1644  * stmmac_init_tx_coalesce - init tx mitigation options.
1645  * @priv: driver private structure
1646  * Description:
1647  * This inits the transmit coalesce parameters: i.e. timer rate,
1648  * timer handler and default threshold used for enabling the
1649  * interrupt on completion bit.
1650  */
1651 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1652 {
1653         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1654         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1655         init_timer(&priv->txtimer);
1656         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1657         priv->txtimer.data = (unsigned long)priv;
1658         priv->txtimer.function = stmmac_tx_timer;
1659         add_timer(&priv->txtimer);
1660 }
1661 
1662 /**
1663  * stmmac_hw_setup - setup mac in a usable state.
1664  *  @dev : pointer to the device structure.
1665  *  Description:
1666  *  this is the main function to setup the HW in a usable state because the
1667  *  dma engine is reset, the core registers are configured (e.g. AXI,
1668  *  Checksum features, timers). The DMA is ready to start receiving and
1669  *  transmitting.
1670  *  Return value:
1671  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1672  *  file on failure.
1673  */
1674 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
1675 {
1676         struct stmmac_priv *priv = netdev_priv(dev);
1677         int ret;
1678 
1679         /* DMA initialization and SW reset */
1680         ret = stmmac_init_dma_engine(priv);
1681         if (ret < 0) {
1682                 pr_err("%s: DMA engine initialization failed\n", __func__);
1683                 return ret;
1684         }
1685 
1686         /* Copy the MAC addr into the HW  */
1687         priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1688 
1689         /* If required, perform hw setup of the bus. */
1690         if (priv->plat->bus_setup)
1691                 priv->plat->bus_setup(priv->ioaddr);
1692 
1693         /* Initialize the MAC Core */
1694         priv->hw->mac->core_init(priv->hw, dev->mtu);
1695 
1696         ret = priv->hw->mac->rx_ipc(priv->hw);
1697         if (!ret) {
1698                 pr_warn(" RX IPC Checksum Offload disabled\n");
1699                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1700                 priv->hw->rx_csum = 0;
1701         }
1702 
1703         /* Enable the MAC Rx/Tx */
1704         stmmac_set_mac(priv->ioaddr, true);
1705 
1706         /* Set the HW DMA mode and the COE */
1707         stmmac_dma_operation_mode(priv);
1708 
1709         stmmac_mmc_setup(priv);
1710 
1711         if (init_ptp) {
1712                 ret = stmmac_init_ptp(priv);
1713                 if (ret && ret != -EOPNOTSUPP)
1714                         pr_warn("%s: failed PTP initialisation\n", __func__);
1715         }
1716 
1717 #ifdef CONFIG_DEBUG_FS
1718         ret = stmmac_init_fs(dev);
1719         if (ret < 0)
1720                 pr_warn("%s: failed debugFS registration\n", __func__);
1721 #endif
1722         /* Start the ball rolling... */
1723         pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
1724         priv->hw->dma->start_tx(priv->ioaddr);
1725         priv->hw->dma->start_rx(priv->ioaddr);
1726 
1727         /* Dump DMA/MAC registers */
1728         if (netif_msg_hw(priv)) {
1729                 priv->hw->mac->dump_regs(priv->hw);
1730                 priv->hw->dma->dump_regs(priv->ioaddr);
1731         }
1732         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1733 
1734         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1735                 priv->rx_riwt = MAX_DMA_RIWT;
1736                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1737         }
1738 
1739         if (priv->pcs && priv->hw->mac->ctrl_ane)
1740                 priv->hw->mac->ctrl_ane(priv->hw, 0);
1741 
1742         return 0;
1743 }
1744 
1745 /**
1746  *  stmmac_open - open entry point of the driver
1747  *  @dev : pointer to the device structure.
1748  *  Description:
1749  *  This function is the open entry point of the driver.
1750  *  Return value:
1751  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1752  *  file on failure.
1753  */
1754 static int stmmac_open(struct net_device *dev)
1755 {
1756         struct stmmac_priv *priv = netdev_priv(dev);
1757         int ret;
1758 
1759         stmmac_check_ether_addr(priv);
1760 
1761         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1762             priv->pcs != STMMAC_PCS_RTBI) {
1763                 ret = stmmac_init_phy(dev);
1764                 if (ret) {
1765                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1766                                __func__, ret);
1767                         return ret;
1768                 }
1769         }
1770 
1771         /* Extra statistics */
1772         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1773         priv->xstats.threshold = tc;
1774 
1775         /* Create and initialize the TX/RX descriptors chains. */
1776         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1777         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1778         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1779 
1780         ret = alloc_dma_desc_resources(priv);
1781         if (ret < 0) {
1782                 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1783                 goto dma_desc_error;
1784         }
1785 
1786         ret = init_dma_desc_rings(dev, GFP_KERNEL);
1787         if (ret < 0) {
1788                 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1789                 goto init_error;
1790         }
1791 
1792         ret = stmmac_hw_setup(dev, true);
1793         if (ret < 0) {
1794                 pr_err("%s: Hw setup failed\n", __func__);
1795                 goto init_error;
1796         }
1797 
1798         stmmac_init_tx_coalesce(priv);
1799 
1800         if (priv->phydev)
1801                 phy_start(priv->phydev);
1802 
1803         /* Request the IRQ lines */
1804         ret = request_irq(dev->irq, stmmac_interrupt,
1805                           IRQF_SHARED, dev->name, dev);
1806         if (unlikely(ret < 0)) {
1807                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1808                        __func__, dev->irq, ret);
1809                 goto init_error;
1810         }
1811 
1812         /* Request the Wake IRQ in case of another line is used for WoL */
1813         if (priv->wol_irq != dev->irq) {
1814                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1815                                   IRQF_SHARED, dev->name, dev);
1816                 if (unlikely(ret < 0)) {
1817                         pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1818                                __func__, priv->wol_irq, ret);
1819                         goto wolirq_error;
1820                 }
1821         }
1822 
1823         /* Request the IRQ lines */
1824         if (priv->lpi_irq > 0) {
1825                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1826                                   dev->name, dev);
1827                 if (unlikely(ret < 0)) {
1828                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1829                                __func__, priv->lpi_irq, ret);
1830                         goto lpiirq_error;
1831                 }
1832         }
1833 
1834         napi_enable(&priv->napi);
1835         netif_start_queue(dev);
1836 
1837         return 0;
1838 
1839 lpiirq_error:
1840         if (priv->wol_irq != dev->irq)
1841                 free_irq(priv->wol_irq, dev);
1842 wolirq_error:
1843         free_irq(dev->irq, dev);
1844 
1845 init_error:
1846         free_dma_desc_resources(priv);
1847 dma_desc_error:
1848         if (priv->phydev)
1849                 phy_disconnect(priv->phydev);
1850 
1851         return ret;
1852 }
1853 
1854 /**
1855  *  stmmac_release - close entry point of the driver
1856  *  @dev : device pointer.
1857  *  Description:
1858  *  This is the stop entry point of the driver.
1859  */
1860 static int stmmac_release(struct net_device *dev)
1861 {
1862         struct stmmac_priv *priv = netdev_priv(dev);
1863 
1864         if (priv->eee_enabled)
1865                 del_timer_sync(&priv->eee_ctrl_timer);
1866 
1867         /* Stop and disconnect the PHY */
1868         if (priv->phydev) {
1869                 phy_stop(priv->phydev);
1870                 phy_disconnect(priv->phydev);
1871                 priv->phydev = NULL;
1872         }
1873 
1874         netif_stop_queue(dev);
1875 
1876         napi_disable(&priv->napi);
1877 
1878         del_timer_sync(&priv->txtimer);
1879 
1880         /* Free the IRQ lines */
1881         free_irq(dev->irq, dev);
1882         if (priv->wol_irq != dev->irq)
1883                 free_irq(priv->wol_irq, dev);
1884         if (priv->lpi_irq > 0)
1885                 free_irq(priv->lpi_irq, dev);
1886 
1887         /* Stop TX/RX DMA and clear the descriptors */
1888         priv->hw->dma->stop_tx(priv->ioaddr);
1889         priv->hw->dma->stop_rx(priv->ioaddr);
1890 
1891         /* Release and free the Rx/Tx resources */
1892         free_dma_desc_resources(priv);
1893 
1894         /* Disable the MAC Rx/Tx */
1895         stmmac_set_mac(priv->ioaddr, false);
1896 
1897         netif_carrier_off(dev);
1898 
1899 #ifdef CONFIG_DEBUG_FS
1900         stmmac_exit_fs();
1901 #endif
1902 
1903         stmmac_release_ptp(priv);
1904 
1905         return 0;
1906 }
1907 
1908 /**
1909  *  stmmac_xmit - Tx entry point of the driver
1910  *  @skb : the socket buffer
1911  *  @dev : device pointer
1912  *  Description : this is the tx entry point of the driver.
1913  *  It programs the chain or the ring and supports oversized frames
1914  *  and SG feature.
1915  */
1916 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1917 {
1918         struct stmmac_priv *priv = netdev_priv(dev);
1919         unsigned int txsize = priv->dma_tx_size;
1920         unsigned int entry;
1921         int i, csum_insertion = 0, is_jumbo = 0;
1922         int nfrags = skb_shinfo(skb)->nr_frags;
1923         struct dma_desc *desc, *first;
1924         unsigned int nopaged_len = skb_headlen(skb);
1925         unsigned int enh_desc = priv->plat->enh_desc;
1926 
1927         spin_lock(&priv->tx_lock);
1928 
1929         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1930                 spin_unlock(&priv->tx_lock);
1931                 if (!netif_queue_stopped(dev)) {
1932                         netif_stop_queue(dev);
1933                         /* This is a hard error, log it. */
1934                         pr_err("%s: Tx Ring full when queue awake\n", __func__);
1935                 }
1936                 return NETDEV_TX_BUSY;
1937         }
1938 
1939         if (priv->tx_path_in_lpi_mode)
1940                 stmmac_disable_eee_mode(priv);
1941 
1942         entry = priv->cur_tx % txsize;
1943 
1944         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1945 
1946         if (priv->extend_desc)
1947                 desc = (struct dma_desc *)(priv->dma_etx + entry);
1948         else
1949                 desc = priv->dma_tx + entry;
1950 
1951         first = desc;
1952 
1953         /* To program the descriptors according to the size of the frame */
1954         if (enh_desc)
1955                 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
1956 
1957         if (likely(!is_jumbo)) {
1958                 desc->des2 = dma_map_single(priv->device, skb->data,
1959                                             nopaged_len, DMA_TO_DEVICE);
1960                 if (dma_mapping_error(priv->device, desc->des2))
1961                         goto dma_map_err;
1962                 priv->tx_skbuff_dma[entry].buf = desc->des2;
1963                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1964                                                 csum_insertion, priv->mode);
1965         } else {
1966                 desc = first;
1967                 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
1968                 if (unlikely(entry < 0))
1969                         goto dma_map_err;
1970         }
1971 
1972         for (i = 0; i < nfrags; i++) {
1973                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1974                 int len = skb_frag_size(frag);
1975 
1976                 priv->tx_skbuff[entry] = NULL;
1977                 entry = (++priv->cur_tx) % txsize;
1978                 if (priv->extend_desc)
1979                         desc = (struct dma_desc *)(priv->dma_etx + entry);
1980                 else
1981                         desc = priv->dma_tx + entry;
1982 
1983                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1984                                               DMA_TO_DEVICE);
1985                 if (dma_mapping_error(priv->device, desc->des2))
1986                         goto dma_map_err; /* should reuse desc w/o issues */
1987 
1988                 priv->tx_skbuff_dma[entry].buf = desc->des2;
1989                 priv->tx_skbuff_dma[entry].map_as_page = true;
1990                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
1991                                                 priv->mode);
1992                 wmb();
1993                 priv->hw->desc->set_tx_owner(desc);
1994                 wmb();
1995         }
1996 
1997         priv->tx_skbuff[entry] = skb;
1998 
1999         /* Finalize the latest segment. */
2000         priv->hw->desc->close_tx_desc(desc);
2001 
2002         wmb();
2003         /* According to the coalesce parameter the IC bit for the latest
2004          * segment could be reset and the timer re-started to invoke the
2005          * stmmac_tx function. This approach takes care about the fragments.
2006          */
2007         priv->tx_count_frames += nfrags + 1;
2008         if (priv->tx_coal_frames > priv->tx_count_frames) {
2009                 priv->hw->desc->clear_tx_ic(desc);
2010                 priv->xstats.tx_reset_ic_bit++;
2011                 mod_timer(&priv->txtimer,
2012                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
2013         } else
2014                 priv->tx_count_frames = 0;
2015 
2016         /* To avoid raise condition */
2017         priv->hw->desc->set_tx_owner(first);
2018         wmb();
2019 
2020         priv->cur_tx++;
2021 
2022         if (netif_msg_pktdata(priv)) {
2023                 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
2024                         __func__, (priv->cur_tx % txsize),
2025                         (priv->dirty_tx % txsize), entry, first, nfrags);
2026 
2027                 if (priv->extend_desc)
2028                         stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
2029                 else
2030                         stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
2031 
2032                 pr_debug(">>> frame to be transmitted: ");
2033                 print_pkt(skb->data, skb->len);
2034         }
2035         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2036                 if (netif_msg_hw(priv))
2037                         pr_debug("%s: stop transmitted packets\n", __func__);
2038                 netif_stop_queue(dev);
2039         }
2040 
2041         dev->stats.tx_bytes += skb->len;
2042 
2043         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2044                      priv->hwts_tx_en)) {
2045                 /* declare that device is doing timestamping */
2046                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2047                 priv->hw->desc->enable_tx_timestamp(first);
2048         }
2049 
2050         if (!priv->hwts_tx_en)
2051                 skb_tx_timestamp(skb);
2052 
2053         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
2054 
2055         spin_unlock(&priv->tx_lock);
2056         return NETDEV_TX_OK;
2057 
2058 dma_map_err:
2059         spin_unlock(&priv->tx_lock);
2060         dev_err(priv->device, "Tx dma map failed\n");
2061         dev_kfree_skb(skb);
2062         priv->dev->stats.tx_dropped++;
2063         return NETDEV_TX_OK;
2064 }
2065 
2066 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
2067 {
2068         struct ethhdr *ehdr;
2069         u16 vlanid;
2070 
2071         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
2072             NETIF_F_HW_VLAN_CTAG_RX &&
2073             !__vlan_get_tag(skb, &vlanid)) {
2074                 /* pop the vlan tag */
2075                 ehdr = (struct ethhdr *)skb->data;
2076                 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
2077                 skb_pull(skb, VLAN_HLEN);
2078                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
2079         }
2080 }
2081 
2082 
2083 /**
2084  * stmmac_rx_refill - refill used skb preallocated buffers
2085  * @priv: driver private structure
2086  * Description : this is to reallocate the skb for the reception process
2087  * that is based on zero-copy.
2088  */
2089 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2090 {
2091         unsigned int rxsize = priv->dma_rx_size;
2092         int bfsize = priv->dma_buf_sz;
2093 
2094         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
2095                 unsigned int entry = priv->dirty_rx % rxsize;
2096                 struct dma_desc *p;
2097 
2098                 if (priv->extend_desc)
2099                         p = (struct dma_desc *)(priv->dma_erx + entry);
2100                 else
2101                         p = priv->dma_rx + entry;
2102 
2103                 if (likely(priv->rx_skbuff[entry] == NULL)) {
2104                         struct sk_buff *skb;
2105 
2106                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2107 
2108                         if (unlikely(skb == NULL))
2109                                 break;
2110 
2111                         priv->rx_skbuff[entry] = skb;
2112                         priv->rx_skbuff_dma[entry] =
2113                             dma_map_single(priv->device, skb->data, bfsize,
2114                                            DMA_FROM_DEVICE);
2115                         if (dma_mapping_error(priv->device,
2116                                               priv->rx_skbuff_dma[entry])) {
2117                                 dev_err(priv->device, "Rx dma map failed\n");
2118                                 dev_kfree_skb(skb);
2119                                 break;
2120                         }
2121                         p->des2 = priv->rx_skbuff_dma[entry];
2122 
2123                         priv->hw->mode->refill_desc3(priv, p);
2124 
2125                         if (netif_msg_rx_status(priv))
2126                                 pr_debug("\trefill entry #%d\n", entry);
2127                 }
2128                 wmb();
2129                 priv->hw->desc->set_rx_owner(p);
2130                 wmb();
2131         }
2132 }
2133 
2134 /**
2135  * stmmac_rx - manage the receive process
2136  * @priv: driver private structure
2137  * @limit: napi bugget.
2138  * Description :  this the function called by the napi poll method.
2139  * It gets all the frames inside the ring.
2140  */
2141 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2142 {
2143         unsigned int rxsize = priv->dma_rx_size;
2144         unsigned int entry = priv->cur_rx % rxsize;
2145         unsigned int next_entry;
2146         unsigned int count = 0;
2147         int coe = priv->hw->rx_csum;
2148 
2149         if (netif_msg_rx_status(priv)) {
2150                 pr_debug("%s: descriptor ring:\n", __func__);
2151                 if (priv->extend_desc)
2152                         stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
2153                 else
2154                         stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
2155         }
2156         while (count < limit) {
2157                 int status;
2158                 struct dma_desc *p;
2159 
2160                 if (priv->extend_desc)
2161                         p = (struct dma_desc *)(priv->dma_erx + entry);
2162                 else
2163                         p = priv->dma_rx + entry;
2164 
2165                 if (priv->hw->desc->get_rx_owner(p))
2166                         break;
2167 
2168                 count++;
2169 
2170                 next_entry = (++priv->cur_rx) % rxsize;
2171                 if (priv->extend_desc)
2172                         prefetch(priv->dma_erx + next_entry);
2173                 else
2174                         prefetch(priv->dma_rx + next_entry);
2175 
2176                 /* read the status of the incoming frame */
2177                 status = priv->hw->desc->rx_status(&priv->dev->stats,
2178                                                    &priv->xstats, p);
2179                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2180                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
2181                                                            &priv->xstats,
2182                                                            priv->dma_erx +
2183                                                            entry);
2184                 if (unlikely(status == discard_frame)) {
2185                         priv->dev->stats.rx_errors++;
2186                         if (priv->hwts_rx_en && !priv->extend_desc) {
2187                                 /* DESC2 & DESC3 will be overwitten by device
2188                                  * with timestamp value, hence reinitialize
2189                                  * them in stmmac_rx_refill() function so that
2190                                  * device can reuse it.
2191                                  */
2192                                 priv->rx_skbuff[entry] = NULL;
2193                                 dma_unmap_single(priv->device,
2194                                                  priv->rx_skbuff_dma[entry],
2195                                                  priv->dma_buf_sz,
2196                                                  DMA_FROM_DEVICE);
2197                         }
2198                 } else {
2199                         struct sk_buff *skb;
2200                         int frame_len;
2201 
2202                         frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2203 
2204                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2205                          * Type frames (LLC/LLC-SNAP)
2206                          */
2207                         if (unlikely(status != llc_snap))
2208                                 frame_len -= ETH_FCS_LEN;
2209 
2210                         if (netif_msg_rx_status(priv)) {
2211                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2212                                          p, entry, p->des2);
2213                                 if (frame_len > ETH_FRAME_LEN)
2214                                         pr_debug("\tframe size %d, COE: %d\n",
2215                                                  frame_len, status);
2216                         }
2217                         skb = priv->rx_skbuff[entry];
2218                         if (unlikely(!skb)) {
2219                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
2220                                        priv->dev->name);
2221                                 priv->dev->stats.rx_dropped++;
2222                                 break;
2223                         }
2224                         prefetch(skb->data - NET_IP_ALIGN);
2225                         priv->rx_skbuff[entry] = NULL;
2226 
2227                         stmmac_get_rx_hwtstamp(priv, entry, skb);
2228 
2229                         skb_put(skb, frame_len);
2230                         dma_unmap_single(priv->device,
2231                                          priv->rx_skbuff_dma[entry],
2232                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
2233 
2234                         if (netif_msg_pktdata(priv)) {
2235                                 pr_debug("frame received (%dbytes)", frame_len);
2236                                 print_pkt(skb->data, frame_len);
2237                         }
2238 
2239                         stmmac_rx_vlan(priv->dev, skb);
2240 
2241                         skb->protocol = eth_type_trans(skb, priv->dev);
2242 
2243                         if (unlikely(!coe))
2244                                 skb_checksum_none_assert(skb);
2245                         else
2246                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2247 
2248                         napi_gro_receive(&priv->napi, skb);
2249 
2250                         priv->dev->stats.rx_packets++;
2251                         priv->dev->stats.rx_bytes += frame_len;
2252                 }
2253                 entry = next_entry;
2254         }
2255 
2256         stmmac_rx_refill(priv);
2257 
2258         priv->xstats.rx_pkt_n += count;
2259 
2260         return count;
2261 }
2262 
2263 /**
2264  *  stmmac_poll - stmmac poll method (NAPI)
2265  *  @napi : pointer to the napi structure.
2266  *  @budget : maximum number of packets that the current CPU can receive from
2267  *            all interfaces.
2268  *  Description :
2269  *  To look at the incoming frames and clear the tx resources.
2270  */
2271 static int stmmac_poll(struct napi_struct *napi, int budget)
2272 {
2273         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2274         int work_done = 0;
2275 
2276         priv->xstats.napi_poll++;
2277         stmmac_tx_clean(priv);
2278 
2279         work_done = stmmac_rx(priv, budget);
2280         if (work_done < budget) {
2281                 napi_complete(napi);
2282                 stmmac_enable_dma_irq(priv);
2283         }
2284         return work_done;
2285 }
2286 
2287 /**
2288  *  stmmac_tx_timeout
2289  *  @dev : Pointer to net device structure
2290  *  Description: this function is called when a packet transmission fails to
2291  *   complete within a reasonable time. The driver will mark the error in the
2292  *   netdev structure and arrange for the device to be reset to a sane state
2293  *   in order to transmit a new packet.
2294  */
2295 static void stmmac_tx_timeout(struct net_device *dev)
2296 {
2297         struct stmmac_priv *priv = netdev_priv(dev);
2298 
2299         /* Clear Tx resources and restart transmitting again */
2300         stmmac_tx_err(priv);
2301 }
2302 
2303 /**
2304  *  stmmac_set_rx_mode - entry point for multicast addressing
2305  *  @dev : pointer to the device structure
2306  *  Description:
2307  *  This function is a driver entry point which gets called by the kernel
2308  *  whenever multicast addresses must be enabled/disabled.
2309  *  Return value:
2310  *  void.
2311  */
2312 static void stmmac_set_rx_mode(struct net_device *dev)
2313 {
2314         struct stmmac_priv *priv = netdev_priv(dev);
2315 
2316         priv->hw->mac->set_filter(priv->hw, dev);
2317 }
2318 
2319 /**
2320  *  stmmac_change_mtu - entry point to change MTU size for the device.
2321  *  @dev : device pointer.
2322  *  @new_mtu : the new MTU size for the device.
2323  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
2324  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
2325  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
2326  *  Return value:
2327  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2328  *  file on failure.
2329  */
2330 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2331 {
2332         struct stmmac_priv *priv = netdev_priv(dev);
2333         int max_mtu;
2334 
2335         if (netif_running(dev)) {
2336                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2337                 return -EBUSY;
2338         }
2339 
2340         if (priv->plat->enh_desc)
2341                 max_mtu = JUMBO_LEN;
2342         else
2343                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2344 
2345         if (priv->plat->maxmtu < max_mtu)
2346                 max_mtu = priv->plat->maxmtu;
2347 
2348         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2349                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2350                 return -EINVAL;
2351         }
2352 
2353         dev->mtu = new_mtu;
2354         netdev_update_features(dev);
2355 
2356         return 0;
2357 }
2358 
2359 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2360                                              netdev_features_t features)
2361 {
2362         struct stmmac_priv *priv = netdev_priv(dev);
2363 
2364         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2365                 features &= ~NETIF_F_RXCSUM;
2366 
2367         if (!priv->plat->tx_coe)
2368                 features &= ~NETIF_F_ALL_CSUM;
2369 
2370         /* Some GMAC devices have a bugged Jumbo frame support that
2371          * needs to have the Tx COE disabled for oversized frames
2372          * (due to limited buffer sizes). In this case we disable
2373          * the TX csum insertionin the TDES and not use SF.
2374          */
2375         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2376                 features &= ~NETIF_F_ALL_CSUM;
2377 
2378         return features;
2379 }
2380 
2381 static int stmmac_set_features(struct net_device *netdev,
2382                                netdev_features_t features)
2383 {
2384         struct stmmac_priv *priv = netdev_priv(netdev);
2385 
2386         /* Keep the COE Type in case of csum is supporting */
2387         if (features & NETIF_F_RXCSUM)
2388                 priv->hw->rx_csum = priv->plat->rx_coe;
2389         else
2390                 priv->hw->rx_csum = 0;
2391         /* No check needed because rx_coe has been set before and it will be
2392          * fixed in case of issue.
2393          */
2394         priv->hw->mac->rx_ipc(priv->hw);
2395 
2396         return 0;
2397 }
2398 
2399 /**
2400  *  stmmac_interrupt - main ISR
2401  *  @irq: interrupt number.
2402  *  @dev_id: to pass the net device pointer.
2403  *  Description: this is the main driver interrupt service routine.
2404  *  It can call:
2405  *  o DMA service routine (to manage incoming frame reception and transmission
2406  *    status)
2407  *  o Core interrupts to manage: remote wake-up, management counter, LPI
2408  *    interrupts.
2409  */
2410 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2411 {
2412         struct net_device *dev = (struct net_device *)dev_id;
2413         struct stmmac_priv *priv = netdev_priv(dev);
2414 
2415         if (priv->irq_wake)
2416                 pm_wakeup_event(priv->device, 0);
2417 
2418         if (unlikely(!dev)) {
2419                 pr_err("%s: invalid dev pointer\n", __func__);
2420                 return IRQ_NONE;
2421         }
2422 
2423         /* To handle GMAC own interrupts */
2424         if (priv->plat->has_gmac) {
2425                 int status = priv->hw->mac->host_irq_status(priv->hw,
2426                                                             &priv->xstats);
2427                 if (unlikely(status)) {
2428                         /* For LPI we need to save the tx status */
2429                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2430                                 priv->tx_path_in_lpi_mode = true;
2431                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2432                                 priv->tx_path_in_lpi_mode = false;
2433                 }
2434         }
2435 
2436         /* To handle DMA interrupts */
2437         stmmac_dma_interrupt(priv);
2438 
2439         return IRQ_HANDLED;
2440 }
2441 
2442 #ifdef CONFIG_NET_POLL_CONTROLLER
2443 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2444  * to allow network I/O with interrupts disabled.
2445  */
2446 static void stmmac_poll_controller(struct net_device *dev)
2447 {
2448         disable_irq(dev->irq);
2449         stmmac_interrupt(dev->irq, dev);
2450         enable_irq(dev->irq);
2451 }
2452 #endif
2453 
2454 /**
2455  *  stmmac_ioctl - Entry point for the Ioctl
2456  *  @dev: Device pointer.
2457  *  @rq: An IOCTL specefic structure, that can contain a pointer to
2458  *  a proprietary structure used to pass information to the driver.
2459  *  @cmd: IOCTL command
2460  *  Description:
2461  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2462  */
2463 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2464 {
2465         struct stmmac_priv *priv = netdev_priv(dev);
2466         int ret = -EOPNOTSUPP;
2467 
2468         if (!netif_running(dev))
2469                 return -EINVAL;
2470 
2471         switch (cmd) {
2472         case SIOCGMIIPHY:
2473         case SIOCGMIIREG:
2474         case SIOCSMIIREG:
2475                 if (!priv->phydev)
2476                         return -EINVAL;
2477                 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2478                 break;
2479         case SIOCSHWTSTAMP:
2480                 ret = stmmac_hwtstamp_ioctl(dev, rq);
2481                 break;
2482         default:
2483                 break;
2484         }
2485 
2486         return ret;
2487 }
2488 
2489 #ifdef CONFIG_DEBUG_FS
2490 static struct dentry *stmmac_fs_dir;
2491 static struct dentry *stmmac_rings_status;
2492 static struct dentry *stmmac_dma_cap;
2493 
2494 static void sysfs_display_ring(void *head, int size, int extend_desc,
2495                                struct seq_file *seq)
2496 {
2497         int i;
2498         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2499         struct dma_desc *p = (struct dma_desc *)head;
2500 
2501         for (i = 0; i < size; i++) {
2502                 u64 x;
2503                 if (extend_desc) {
2504                         x = *(u64 *) ep;
2505                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2506                                    i, (unsigned int)virt_to_phys(ep),
2507                                    (unsigned int)x, (unsigned int)(x >> 32),
2508                                    ep->basic.des2, ep->basic.des3);
2509                         ep++;
2510                 } else {
2511                         x = *(u64 *) p;
2512                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2513                                    i, (unsigned int)virt_to_phys(ep),
2514                                    (unsigned int)x, (unsigned int)(x >> 32),
2515                                    p->des2, p->des3);
2516                         p++;
2517                 }
2518                 seq_printf(seq, "\n");
2519         }
2520 }
2521 
2522 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2523 {
2524         struct net_device *dev = seq->private;
2525         struct stmmac_priv *priv = netdev_priv(dev);
2526         unsigned int txsize = priv->dma_tx_size;
2527         unsigned int rxsize = priv->dma_rx_size;
2528 
2529         if (priv->extend_desc) {
2530                 seq_printf(seq, "Extended RX descriptor ring:\n");
2531                 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq);
2532                 seq_printf(seq, "Extended TX descriptor ring:\n");
2533                 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq);
2534         } else {
2535                 seq_printf(seq, "RX descriptor ring:\n");
2536                 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
2537                 seq_printf(seq, "TX descriptor ring:\n");
2538                 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
2539         }
2540 
2541         return 0;
2542 }
2543 
2544 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2545 {
2546         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2547 }
2548 
2549 static const struct file_operations stmmac_rings_status_fops = {
2550         .owner = THIS_MODULE,
2551         .open = stmmac_sysfs_ring_open,
2552         .read = seq_read,
2553         .llseek = seq_lseek,
2554         .release = single_release,
2555 };
2556 
2557 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2558 {
2559         struct net_device *dev = seq->private;
2560         struct stmmac_priv *priv = netdev_priv(dev);
2561 
2562         if (!priv->hw_cap_support) {
2563                 seq_printf(seq, "DMA HW features not supported\n");
2564                 return 0;
2565         }
2566 
2567         seq_printf(seq, "==============================\n");
2568         seq_printf(seq, "\tDMA HW features\n");
2569         seq_printf(seq, "==============================\n");
2570 
2571         seq_printf(seq, "\t10/100 Mbps %s\n",
2572                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2573         seq_printf(seq, "\t1000 Mbps %s\n",
2574                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
2575         seq_printf(seq, "\tHalf duple %s\n",
2576                    (priv->dma_cap.half_duplex) ? "Y" : "N");
2577         seq_printf(seq, "\tHash Filter: %s\n",
2578                    (priv->dma_cap.hash_filter) ? "Y" : "N");
2579         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2580                    (priv->dma_cap.multi_addr) ? "Y" : "N");
2581         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2582                    (priv->dma_cap.pcs) ? "Y" : "N");
2583         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2584                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
2585         seq_printf(seq, "\tPMT Remote wake up: %s\n",
2586                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2587         seq_printf(seq, "\tPMT Magic Frame: %s\n",
2588                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2589         seq_printf(seq, "\tRMON module: %s\n",
2590                    (priv->dma_cap.rmon) ? "Y" : "N");
2591         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2592                    (priv->dma_cap.time_stamp) ? "Y" : "N");
2593         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2594                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
2595         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2596                    (priv->dma_cap.eee) ? "Y" : "N");
2597         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2598         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2599                    (priv->dma_cap.tx_coe) ? "Y" : "N");
2600         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2601                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2602         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2603                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2604         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2605                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2606         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2607                    priv->dma_cap.number_rx_channel);
2608         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2609                    priv->dma_cap.number_tx_channel);
2610         seq_printf(seq, "\tEnhanced descriptors: %s\n",
2611                    (priv->dma_cap.enh_desc) ? "Y" : "N");
2612 
2613         return 0;
2614 }
2615 
2616 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2617 {
2618         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2619 }
2620 
2621 static const struct file_operations stmmac_dma_cap_fops = {
2622         .owner = THIS_MODULE,
2623         .open = stmmac_sysfs_dma_cap_open,
2624         .read = seq_read,
2625         .llseek = seq_lseek,
2626         .release = single_release,
2627 };
2628 
2629 static int stmmac_init_fs(struct net_device *dev)
2630 {
2631         /* Create debugfs entries */
2632         stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
2633 
2634         if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
2635                 pr_err("ERROR %s, debugfs create directory failed\n",
2636                        STMMAC_RESOURCE_NAME);
2637 
2638                 return -ENOMEM;
2639         }
2640 
2641         /* Entry to report DMA RX/TX rings */
2642         stmmac_rings_status = debugfs_create_file("descriptors_status",
2643                                                   S_IRUGO, stmmac_fs_dir, dev,
2644                                                   &stmmac_rings_status_fops);
2645 
2646         if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
2647                 pr_info("ERROR creating stmmac ring debugfs file\n");
2648                 debugfs_remove(stmmac_fs_dir);
2649 
2650                 return -ENOMEM;
2651         }
2652 
2653         /* Entry to report the DMA HW features */
2654         stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
2655                                              dev, &stmmac_dma_cap_fops);
2656 
2657         if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
2658                 pr_info("ERROR creating stmmac MMC debugfs file\n");
2659                 debugfs_remove(stmmac_rings_status);
2660                 debugfs_remove(stmmac_fs_dir);
2661 
2662                 return -ENOMEM;
2663         }
2664 
2665         return 0;
2666 }
2667 
2668 static void stmmac_exit_fs(void)
2669 {
2670         debugfs_remove(stmmac_rings_status);
2671         debugfs_remove(stmmac_dma_cap);
2672         debugfs_remove(stmmac_fs_dir);
2673 }
2674 #endif /* CONFIG_DEBUG_FS */
2675 
2676 static const struct net_device_ops stmmac_netdev_ops = {
2677         .ndo_open = stmmac_open,
2678         .ndo_start_xmit = stmmac_xmit,
2679         .ndo_stop = stmmac_release,
2680         .ndo_change_mtu = stmmac_change_mtu,
2681         .ndo_fix_features = stmmac_fix_features,
2682         .ndo_set_features = stmmac_set_features,
2683         .ndo_set_rx_mode = stmmac_set_rx_mode,
2684         .ndo_tx_timeout = stmmac_tx_timeout,
2685         .ndo_do_ioctl = stmmac_ioctl,
2686 #ifdef CONFIG_NET_POLL_CONTROLLER
2687         .ndo_poll_controller = stmmac_poll_controller,
2688 #endif
2689         .ndo_set_mac_address = eth_mac_addr,
2690 };
2691 
2692 /**
2693  *  stmmac_hw_init - Init the MAC device
2694  *  @priv: driver private structure
2695  *  Description: this function is to configure the MAC device according to
2696  *  some platform parameters or the HW capability register. It prepares the
2697  *  driver to use either ring or chain modes and to setup either enhanced or
2698  *  normal descriptors.
2699  */
2700 static int stmmac_hw_init(struct stmmac_priv *priv)
2701 {
2702         struct mac_device_info *mac;
2703 
2704         /* Identify the MAC HW device */
2705         if (priv->plat->has_gmac) {
2706                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2707                 mac = dwmac1000_setup(priv->ioaddr,
2708                                       priv->plat->multicast_filter_bins,
2709                                       priv->plat->unicast_filter_entries);
2710         } else {
2711                 mac = dwmac100_setup(priv->ioaddr);
2712         }
2713         if (!mac)
2714                 return -ENOMEM;
2715 
2716         priv->hw = mac;
2717 
2718         /* Get and dump the chip ID */
2719         priv->synopsys_id = stmmac_get_synopsys_id(priv);
2720 
2721         /* To use the chained or ring mode */
2722         if (chain_mode) {
2723                 priv->hw->mode = &chain_mode_ops;
2724                 pr_info(" Chain mode enabled\n");
2725                 priv->mode = STMMAC_CHAIN_MODE;
2726         } else {
2727                 priv->hw->mode = &ring_mode_ops;
2728                 pr_info(" Ring mode enabled\n");
2729                 priv->mode = STMMAC_RING_MODE;
2730         }
2731 
2732         /* Get the HW capability (new GMAC newer than 3.50a) */
2733         priv->hw_cap_support = stmmac_get_hw_features(priv);
2734         if (priv->hw_cap_support) {
2735                 pr_info(" DMA HW capability register supported");
2736 
2737                 /* We can override some gmac/dma configuration fields: e.g.
2738                  * enh_desc, tx_coe (e.g. that are passed through the
2739                  * platform) with the values from the HW capability
2740                  * register (if supported).
2741                  */
2742                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2743                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2744 
2745                 priv->plat->tx_coe = priv->dma_cap.tx_coe;
2746 
2747                 if (priv->dma_cap.rx_coe_type2)
2748                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2749                 else if (priv->dma_cap.rx_coe_type1)
2750                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2751 
2752         } else
2753                 pr_info(" No HW DMA feature register supported");
2754 
2755         /* To use alternate (extended) or normal descriptor structures */
2756         stmmac_selec_desc_mode(priv);
2757 
2758         if (priv->plat->rx_coe) {
2759                 priv->hw->rx_csum = priv->plat->rx_coe;
2760                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2761                         priv->plat->rx_coe);
2762         }
2763         if (priv->plat->tx_coe)
2764                 pr_info(" TX Checksum insertion supported\n");
2765 
2766         if (priv->plat->pmt) {
2767                 pr_info(" Wake-Up On Lan supported\n");
2768                 device_set_wakeup_capable(priv->device, 1);
2769         }
2770 
2771         return 0;
2772 }
2773 
2774 /**
2775  * stmmac_dvr_probe
2776  * @device: device pointer
2777  * @plat_dat: platform data pointer
2778  * @addr: iobase memory address
2779  * Description: this is the main probe function used to
2780  * call the alloc_etherdev, allocate the priv structure.
2781  * Return:
2782  * on success the new private structure is returned, otherwise the error
2783  * pointer.
2784  */
2785 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
2786                                      struct plat_stmmacenet_data *plat_dat,
2787                                      void __iomem *addr)
2788 {
2789         int ret = 0;
2790         struct net_device *ndev = NULL;
2791         struct stmmac_priv *priv;
2792 
2793         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2794         if (!ndev)
2795                 return ERR_PTR(-ENOMEM);
2796 
2797         SET_NETDEV_DEV(ndev, device);
2798 
2799         priv = netdev_priv(ndev);
2800         priv->device = device;
2801         priv->dev = ndev;
2802 
2803         stmmac_set_ethtool_ops(ndev);
2804         priv->pause = pause;
2805         priv->plat = plat_dat;
2806         priv->ioaddr = addr;
2807         priv->dev->base_addr = (unsigned long)addr;
2808 
2809         /* Verify driver arguments */
2810         stmmac_verify_args();
2811 
2812         /* Override with kernel parameters if supplied XXX CRS XXX
2813          * this needs to have multiple instances
2814          */
2815         if ((phyaddr >= 0) && (phyaddr <= 31))
2816                 priv->plat->phy_addr = phyaddr;
2817 
2818         priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
2819         if (IS_ERR(priv->stmmac_clk)) {
2820                 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
2821                          __func__);
2822                 /* If failed to obtain stmmac_clk and specific clk_csr value
2823                  * is NOT passed from the platform, probe fail.
2824                  */
2825                 if (!priv->plat->clk_csr) {
2826                         ret = PTR_ERR(priv->stmmac_clk);
2827                         goto error_clk_get;
2828                 } else {
2829                         priv->stmmac_clk = NULL;
2830                 }
2831         }
2832         clk_prepare_enable(priv->stmmac_clk);
2833 
2834         priv->stmmac_rst = devm_reset_control_get(priv->device,
2835                                                   STMMAC_RESOURCE_NAME);
2836         if (IS_ERR(priv->stmmac_rst)) {
2837                 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
2838                         ret = -EPROBE_DEFER;
2839                         goto error_hw_init;
2840                 }
2841                 dev_info(priv->device, "no reset control found\n");
2842                 priv->stmmac_rst = NULL;
2843         }
2844         if (priv->stmmac_rst)
2845                 reset_control_deassert(priv->stmmac_rst);
2846 
2847         /* Init MAC and get the capabilities */
2848         ret = stmmac_hw_init(priv);
2849         if (ret)
2850                 goto error_hw_init;
2851 
2852         ndev->netdev_ops = &stmmac_netdev_ops;
2853 
2854         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2855                             NETIF_F_RXCSUM;
2856         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2857         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2858 #ifdef STMMAC_VLAN_TAG_USED
2859         /* Both mac100 and gmac support receive VLAN tag detection */
2860         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2861 #endif
2862         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2863 
2864         if (flow_ctrl)
2865                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
2866 
2867         /* Rx Watchdog is available in the COREs newer than the 3.40.
2868          * In some case, for example on bugged HW this feature
2869          * has to be disable and this can be done by passing the
2870          * riwt_off field from the platform.
2871          */
2872         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2873                 priv->use_riwt = 1;
2874                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2875         }
2876 
2877         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2878 
2879         spin_lock_init(&priv->lock);
2880         spin_lock_init(&priv->tx_lock);
2881 
2882         ret = register_netdev(ndev);
2883         if (ret) {
2884                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2885                 goto error_netdev_register;
2886         }
2887 
2888         /* If a specific clk_csr value is passed from the platform
2889          * this means that the CSR Clock Range selection cannot be
2890          * changed at run-time and it is fixed. Viceversa the driver'll try to
2891          * set the MDC clock dynamically according to the csr actual
2892          * clock input.
2893          */
2894         if (!priv->plat->clk_csr)
2895                 stmmac_clk_csr_set(priv);
2896         else
2897                 priv->clk_csr = priv->plat->clk_csr;
2898 
2899         stmmac_check_pcs_mode(priv);
2900 
2901         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2902             priv->pcs != STMMAC_PCS_RTBI) {
2903                 /* MDIO bus Registration */
2904                 ret = stmmac_mdio_register(ndev);
2905                 if (ret < 0) {
2906                         pr_debug("%s: MDIO bus (id: %d) registration failed",
2907                                  __func__, priv->plat->bus_id);
2908                         goto error_mdio_register;
2909                 }
2910         }
2911 
2912         return priv;
2913 
2914 error_mdio_register:
2915         unregister_netdev(ndev);
2916 error_netdev_register:
2917         netif_napi_del(&priv->napi);
2918 error_hw_init:
2919         clk_disable_unprepare(priv->stmmac_clk);
2920 error_clk_get:
2921         free_netdev(ndev);
2922 
2923         return ERR_PTR(ret);
2924 }
2925 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
2926 
2927 /**
2928  * stmmac_dvr_remove
2929  * @ndev: net device pointer
2930  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2931  * changes the link status, releases the DMA descriptor rings.
2932  */
2933 int stmmac_dvr_remove(struct net_device *ndev)
2934 {
2935         struct stmmac_priv *priv = netdev_priv(ndev);
2936 
2937         pr_info("%s:\n\tremoving driver", __func__);
2938 
2939         priv->hw->dma->stop_rx(priv->ioaddr);
2940         priv->hw->dma->stop_tx(priv->ioaddr);
2941 
2942         stmmac_set_mac(priv->ioaddr, false);
2943         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2944             priv->pcs != STMMAC_PCS_RTBI)
2945                 stmmac_mdio_unregister(ndev);
2946         netif_carrier_off(ndev);
2947         unregister_netdev(ndev);
2948         if (priv->stmmac_rst)
2949                 reset_control_assert(priv->stmmac_rst);
2950         clk_disable_unprepare(priv->stmmac_clk);
2951         free_netdev(ndev);
2952 
2953         return 0;
2954 }
2955 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
2956 
2957 /**
2958  * stmmac_suspend - suspend callback
2959  * @ndev: net device pointer
2960  * Description: this is the function to suspend the device and it is called
2961  * by the platform driver to stop the network queue, release the resources,
2962  * program the PMT register (for WoL), clean and release driver resources.
2963  */
2964 int stmmac_suspend(struct net_device *ndev)
2965 {
2966         struct stmmac_priv *priv = netdev_priv(ndev);
2967         unsigned long flags;
2968 
2969         if (!ndev || !netif_running(ndev))
2970                 return 0;
2971 
2972         if (priv->phydev)
2973                 phy_stop(priv->phydev);
2974 
2975         spin_lock_irqsave(&priv->lock, flags);
2976 
2977         netif_device_detach(ndev);
2978         netif_stop_queue(ndev);
2979 
2980         napi_disable(&priv->napi);
2981 
2982         /* Stop TX/RX DMA */
2983         priv->hw->dma->stop_tx(priv->ioaddr);
2984         priv->hw->dma->stop_rx(priv->ioaddr);
2985 
2986         stmmac_clear_descriptors(priv);
2987 
2988         /* Enable Power down mode by programming the PMT regs */
2989         if (device_may_wakeup(priv->device)) {
2990                 priv->hw->mac->pmt(priv->hw, priv->wolopts);
2991                 priv->irq_wake = 1;
2992         } else {
2993                 stmmac_set_mac(priv->ioaddr, false);
2994                 pinctrl_pm_select_sleep_state(priv->device);
2995                 /* Disable clock in case of PWM is off */
2996                 clk_disable(priv->stmmac_clk);
2997         }
2998         spin_unlock_irqrestore(&priv->lock, flags);
2999 
3000         priv->oldlink = 0;
3001         priv->speed = 0;
3002         priv->oldduplex = -1;
3003         return 0;
3004 }
3005 EXPORT_SYMBOL_GPL(stmmac_suspend);
3006 
3007 /**
3008  * stmmac_resume - resume callback
3009  * @ndev: net device pointer
3010  * Description: when resume this function is invoked to setup the DMA and CORE
3011  * in a usable state.
3012  */
3013 int stmmac_resume(struct net_device *ndev)
3014 {
3015         struct stmmac_priv *priv = netdev_priv(ndev);
3016         unsigned long flags;
3017 
3018         if (!netif_running(ndev))
3019                 return 0;
3020 
3021         spin_lock_irqsave(&priv->lock, flags);
3022 
3023         /* Power Down bit, into the PM register, is cleared
3024          * automatically as soon as a magic packet or a Wake-up frame
3025          * is received. Anyway, it's better to manually clear
3026          * this bit because it can generate problems while resuming
3027          * from another devices (e.g. serial console).
3028          */
3029         if (device_may_wakeup(priv->device)) {
3030                 priv->hw->mac->pmt(priv->hw, 0);
3031                 priv->irq_wake = 0;
3032         } else {
3033                 pinctrl_pm_select_default_state(priv->device);
3034                 /* enable the clk prevously disabled */
3035                 clk_enable(priv->stmmac_clk);
3036                 /* reset the phy so that it's ready */
3037                 if (priv->mii)
3038                         stmmac_mdio_reset(priv->mii);
3039         }
3040 
3041         netif_device_attach(ndev);
3042 
3043         init_dma_desc_rings(ndev, GFP_ATOMIC);
3044         stmmac_hw_setup(ndev, false);
3045         stmmac_init_tx_coalesce(priv);
3046 
3047         napi_enable(&priv->napi);
3048 
3049         netif_start_queue(ndev);
3050 
3051         spin_unlock_irqrestore(&priv->lock, flags);
3052 
3053         if (priv->phydev)
3054                 phy_start(priv->phydev);
3055 
3056         return 0;
3057 }
3058 EXPORT_SYMBOL_GPL(stmmac_resume);
3059 
3060 #ifndef MODULE
3061 static int __init stmmac_cmdline_opt(char *str)
3062 {
3063         char *opt;
3064 
3065         if (!str || !*str)
3066                 return -EINVAL;
3067         while ((opt = strsep(&str, ",")) != NULL) {
3068                 if (!strncmp(opt, "debug:", 6)) {
3069                         if (kstrtoint(opt + 6, 0, &debug))
3070                                 goto err;
3071                 } else if (!strncmp(opt, "phyaddr:", 8)) {
3072                         if (kstrtoint(opt + 8, 0, &phyaddr))
3073                                 goto err;
3074                 } else if (!strncmp(opt, "dma_txsize:", 11)) {
3075                         if (kstrtoint(opt + 11, 0, &dma_txsize))
3076                                 goto err;
3077                 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
3078                         if (kstrtoint(opt + 11, 0, &dma_rxsize))
3079                                 goto err;
3080                 } else if (!strncmp(opt, "buf_sz:", 7)) {
3081                         if (kstrtoint(opt + 7, 0, &buf_sz))
3082                                 goto err;
3083                 } else if (!strncmp(opt, "tc:", 3)) {
3084                         if (kstrtoint(opt + 3, 0, &tc))
3085                                 goto err;
3086                 } else if (!strncmp(opt, "watchdog:", 9)) {
3087                         if (kstrtoint(opt + 9, 0, &watchdog))
3088                                 goto err;
3089                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
3090                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
3091                                 goto err;
3092                 } else if (!strncmp(opt, "pause:", 6)) {
3093                         if (kstrtoint(opt + 6, 0, &pause))
3094                                 goto err;
3095                 } else if (!strncmp(opt, "eee_timer:", 10)) {
3096                         if (kstrtoint(opt + 10, 0, &eee_timer))
3097                                 goto err;
3098                 } else if (!strncmp(opt, "chain_mode:", 11)) {
3099                         if (kstrtoint(opt + 11, 0, &chain_mode))
3100                                 goto err;
3101                 }
3102         }
3103         return 0;
3104 
3105 err:
3106         pr_err("%s: ERROR broken module parameter conversion", __func__);
3107         return -EINVAL;
3108 }
3109 
3110 __setup("stmmaceth=", stmmac_cmdline_opt);
3111 #endif /* MODULE */
3112 
3113 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3114 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3115 MODULE_LICENSE("GPL");
3116 

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