Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5

Linux/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

  1 /*******************************************************************************
  2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
  3   ST Ethernet IPs are built around a Synopsys IP Core.
  4 
  5         Copyright(C) 2007-2011 STMicroelectronics Ltd
  6 
  7   This program is free software; you can redistribute it and/or modify it
  8   under the terms and conditions of the GNU General Public License,
  9   version 2, as published by the Free Software Foundation.
 10 
 11   This program is distributed in the hope it will be useful, but WITHOUT
 12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 14   more details.
 15 
 16   You should have received a copy of the GNU General Public License along with
 17   this program; if not, write to the Free Software Foundation, Inc.,
 18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 19 
 20   The full GNU General Public License is included in this distribution in
 21   the file called "COPYING".
 22 
 23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
 24 
 25   Documentation available at:
 26         http://www.stlinux.com
 27   Support available at:
 28         https://bugzilla.stlinux.com/
 29 *******************************************************************************/
 30 
 31 #include <linux/clk.h>
 32 #include <linux/kernel.h>
 33 #include <linux/interrupt.h>
 34 #include <linux/ip.h>
 35 #include <linux/tcp.h>
 36 #include <linux/skbuff.h>
 37 #include <linux/ethtool.h>
 38 #include <linux/if_ether.h>
 39 #include <linux/crc32.h>
 40 #include <linux/mii.h>
 41 #include <linux/if.h>
 42 #include <linux/if_vlan.h>
 43 #include <linux/dma-mapping.h>
 44 #include <linux/slab.h>
 45 #include <linux/prefetch.h>
 46 #include <linux/pinctrl/consumer.h>
 47 #ifdef CONFIG_DEBUG_FS
 48 #include <linux/debugfs.h>
 49 #include <linux/seq_file.h>
 50 #endif /* CONFIG_DEBUG_FS */
 51 #include <linux/net_tstamp.h>
 52 #include "stmmac_ptp.h"
 53 #include "stmmac.h"
 54 #include <linux/reset.h>
 55 #include <linux/of_mdio.h>
 56 #include "dwmac1000.h"
 57 
 58 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
 59 
 60 /* Module parameters */
 61 #define TX_TIMEO        5000
 62 static int watchdog = TX_TIMEO;
 63 module_param(watchdog, int, S_IRUGO | S_IWUSR);
 64 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
 65 
 66 static int debug = -1;
 67 module_param(debug, int, S_IRUGO | S_IWUSR);
 68 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
 69 
 70 static int phyaddr = -1;
 71 module_param(phyaddr, int, S_IRUGO);
 72 MODULE_PARM_DESC(phyaddr, "Physical device address");
 73 
 74 #define DMA_TX_SIZE 256
 75 static int dma_txsize = DMA_TX_SIZE;
 76 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
 77 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
 78 
 79 #define DMA_RX_SIZE 256
 80 static int dma_rxsize = DMA_RX_SIZE;
 81 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
 82 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
 83 
 84 static int flow_ctrl = FLOW_OFF;
 85 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
 86 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
 87 
 88 static int pause = PAUSE_TIME;
 89 module_param(pause, int, S_IRUGO | S_IWUSR);
 90 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
 91 
 92 #define TC_DEFAULT 64
 93 static int tc = TC_DEFAULT;
 94 module_param(tc, int, S_IRUGO | S_IWUSR);
 95 MODULE_PARM_DESC(tc, "DMA threshold control value");
 96 
 97 #define DEFAULT_BUFSIZE 1536
 98 static int buf_sz = DEFAULT_BUFSIZE;
 99 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
100 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
101 
102 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
103                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
104                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
105 
106 #define STMMAC_DEFAULT_LPI_TIMER        1000
107 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
108 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
109 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
110 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
111 
112 /* By default the driver will use the ring mode to manage tx and rx descriptors
113  * but passing this value so user can force to use the chain instead of the ring
114  */
115 static unsigned int chain_mode;
116 module_param(chain_mode, int, S_IRUGO);
117 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
118 
119 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
120 
121 #ifdef CONFIG_DEBUG_FS
122 static int stmmac_init_fs(struct net_device *dev);
123 static void stmmac_exit_fs(struct net_device *dev);
124 #endif
125 
126 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
127 
128 /**
129  * stmmac_verify_args - verify the driver parameters.
130  * Description: it checks the driver parameters and set a default in case of
131  * errors.
132  */
133 static void stmmac_verify_args(void)
134 {
135         if (unlikely(watchdog < 0))
136                 watchdog = TX_TIMEO;
137         if (unlikely(dma_rxsize < 0))
138                 dma_rxsize = DMA_RX_SIZE;
139         if (unlikely(dma_txsize < 0))
140                 dma_txsize = DMA_TX_SIZE;
141         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
142                 buf_sz = DEFAULT_BUFSIZE;
143         if (unlikely(flow_ctrl > 1))
144                 flow_ctrl = FLOW_AUTO;
145         else if (likely(flow_ctrl < 0))
146                 flow_ctrl = FLOW_OFF;
147         if (unlikely((pause < 0) || (pause > 0xffff)))
148                 pause = PAUSE_TIME;
149         if (eee_timer < 0)
150                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
151 }
152 
153 /**
154  * stmmac_clk_csr_set - dynamically set the MDC clock
155  * @priv: driver private structure
156  * Description: this is to dynamically set the MDC clock according to the csr
157  * clock input.
158  * Note:
159  *      If a specific clk_csr value is passed from the platform
160  *      this means that the CSR Clock Range selection cannot be
161  *      changed at run-time and it is fixed (as reported in the driver
162  *      documentation). Viceversa the driver will try to set the MDC
163  *      clock dynamically according to the actual clock input.
164  */
165 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
166 {
167         u32 clk_rate;
168 
169         clk_rate = clk_get_rate(priv->stmmac_clk);
170 
171         /* Platform provided default clk_csr would be assumed valid
172          * for all other cases except for the below mentioned ones.
173          * For values higher than the IEEE 802.3 specified frequency
174          * we can not estimate the proper divider as it is not known
175          * the frequency of clk_csr_i. So we do not change the default
176          * divider.
177          */
178         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
179                 if (clk_rate < CSR_F_35M)
180                         priv->clk_csr = STMMAC_CSR_20_35M;
181                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
182                         priv->clk_csr = STMMAC_CSR_35_60M;
183                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
184                         priv->clk_csr = STMMAC_CSR_60_100M;
185                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
186                         priv->clk_csr = STMMAC_CSR_100_150M;
187                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
188                         priv->clk_csr = STMMAC_CSR_150_250M;
189                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
190                         priv->clk_csr = STMMAC_CSR_250_300M;
191         }
192 }
193 
194 static void print_pkt(unsigned char *buf, int len)
195 {
196         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
197         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
198 }
199 
200 /* minimum number of free TX descriptors required to wake up TX process */
201 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
202 
203 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
204 {
205         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
206 }
207 
208 /**
209  * stmmac_hw_fix_mac_speed - callback for speed selection
210  * @priv: driver private structure
211  * Description: on some platforms (e.g. ST), some HW system configuraton
212  * registers have to be set according to the link speed negotiated.
213  */
214 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
215 {
216         struct phy_device *phydev = priv->phydev;
217 
218         if (likely(priv->plat->fix_mac_speed))
219                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
220 }
221 
222 /**
223  * stmmac_enable_eee_mode - check and enter in LPI mode
224  * @priv: driver private structure
225  * Description: this function is to verify and enter in LPI mode in case of
226  * EEE.
227  */
228 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
229 {
230         /* Check and enter in LPI mode */
231         if ((priv->dirty_tx == priv->cur_tx) &&
232             (priv->tx_path_in_lpi_mode == false))
233                 priv->hw->mac->set_eee_mode(priv->hw);
234 }
235 
236 /**
237  * stmmac_disable_eee_mode - disable and exit from LPI mode
238  * @priv: driver private structure
239  * Description: this function is to exit and disable EEE in case of
240  * LPI state is true. This is called by the xmit.
241  */
242 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
243 {
244         priv->hw->mac->reset_eee_mode(priv->hw);
245         del_timer_sync(&priv->eee_ctrl_timer);
246         priv->tx_path_in_lpi_mode = false;
247 }
248 
249 /**
250  * stmmac_eee_ctrl_timer - EEE TX SW timer.
251  * @arg : data hook
252  * Description:
253  *  if there is no data transfer and if we are not in LPI state,
254  *  then MAC Transmitter can be moved to LPI state.
255  */
256 static void stmmac_eee_ctrl_timer(unsigned long arg)
257 {
258         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
259 
260         stmmac_enable_eee_mode(priv);
261         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
262 }
263 
264 /**
265  * stmmac_eee_init - init EEE
266  * @priv: driver private structure
267  * Description:
268  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
269  *  can also manage EEE, this function enable the LPI state and start related
270  *  timer.
271  */
272 bool stmmac_eee_init(struct stmmac_priv *priv)
273 {
274         char *phy_bus_name = priv->plat->phy_bus_name;
275         unsigned long flags;
276         bool ret = false;
277 
278         /* Using PCS we cannot dial with the phy registers at this stage
279          * so we do not support extra feature like EEE.
280          */
281         if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
282             (priv->pcs == STMMAC_PCS_RTBI))
283                 goto out;
284 
285         /* Never init EEE in case of a switch is attached */
286         if (phy_bus_name && (!strcmp(phy_bus_name, "fixed")))
287                 goto out;
288 
289         /* MAC core supports the EEE feature. */
290         if (priv->dma_cap.eee) {
291                 int tx_lpi_timer = priv->tx_lpi_timer;
292 
293                 /* Check if the PHY supports EEE */
294                 if (phy_init_eee(priv->phydev, 1)) {
295                         /* To manage at run-time if the EEE cannot be supported
296                          * anymore (for example because the lp caps have been
297                          * changed).
298                          * In that case the driver disable own timers.
299                          */
300                         spin_lock_irqsave(&priv->lock, flags);
301                         if (priv->eee_active) {
302                                 pr_debug("stmmac: disable EEE\n");
303                                 del_timer_sync(&priv->eee_ctrl_timer);
304                                 priv->hw->mac->set_eee_timer(priv->hw, 0,
305                                                              tx_lpi_timer);
306                         }
307                         priv->eee_active = 0;
308                         spin_unlock_irqrestore(&priv->lock, flags);
309                         goto out;
310                 }
311                 /* Activate the EEE and start timers */
312                 spin_lock_irqsave(&priv->lock, flags);
313                 if (!priv->eee_active) {
314                         priv->eee_active = 1;
315                         setup_timer(&priv->eee_ctrl_timer,
316                                     stmmac_eee_ctrl_timer,
317                                     (unsigned long)priv);
318                         mod_timer(&priv->eee_ctrl_timer,
319                                   STMMAC_LPI_T(eee_timer));
320 
321                         priv->hw->mac->set_eee_timer(priv->hw,
322                                                      STMMAC_DEFAULT_LIT_LS,
323                                                      tx_lpi_timer);
324                 }
325                 /* Set HW EEE according to the speed */
326                 priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link);
327 
328                 ret = true;
329                 spin_unlock_irqrestore(&priv->lock, flags);
330 
331                 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
332         }
333 out:
334         return ret;
335 }
336 
337 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
338  * @priv: driver private structure
339  * @entry : descriptor index to be used.
340  * @skb : the socket buffer
341  * Description :
342  * This function will read timestamp from the descriptor & pass it to stack.
343  * and also perform some sanity checks.
344  */
345 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
346                                    unsigned int entry, struct sk_buff *skb)
347 {
348         struct skb_shared_hwtstamps shhwtstamp;
349         u64 ns;
350         void *desc = NULL;
351 
352         if (!priv->hwts_tx_en)
353                 return;
354 
355         /* exit if skb doesn't support hw tstamp */
356         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
357                 return;
358 
359         if (priv->adv_ts)
360                 desc = (priv->dma_etx + entry);
361         else
362                 desc = (priv->dma_tx + entry);
363 
364         /* check tx tstamp status */
365         if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
366                 return;
367 
368         /* get the valid tstamp */
369         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
370 
371         memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
372         shhwtstamp.hwtstamp = ns_to_ktime(ns);
373         /* pass tstamp to stack */
374         skb_tstamp_tx(skb, &shhwtstamp);
375 
376         return;
377 }
378 
379 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
380  * @priv: driver private structure
381  * @entry : descriptor index to be used.
382  * @skb : the socket buffer
383  * Description :
384  * This function will read received packet's timestamp from the descriptor
385  * and pass it to stack. It also perform some sanity checks.
386  */
387 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
388                                    unsigned int entry, struct sk_buff *skb)
389 {
390         struct skb_shared_hwtstamps *shhwtstamp = NULL;
391         u64 ns;
392         void *desc = NULL;
393 
394         if (!priv->hwts_rx_en)
395                 return;
396 
397         if (priv->adv_ts)
398                 desc = (priv->dma_erx + entry);
399         else
400                 desc = (priv->dma_rx + entry);
401 
402         /* exit if rx tstamp is not valid */
403         if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
404                 return;
405 
406         /* get valid tstamp */
407         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
408         shhwtstamp = skb_hwtstamps(skb);
409         memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
410         shhwtstamp->hwtstamp = ns_to_ktime(ns);
411 }
412 
413 /**
414  *  stmmac_hwtstamp_ioctl - control hardware timestamping.
415  *  @dev: device pointer.
416  *  @ifr: An IOCTL specefic structure, that can contain a pointer to
417  *  a proprietary structure used to pass information to the driver.
418  *  Description:
419  *  This function configures the MAC to enable/disable both outgoing(TX)
420  *  and incoming(RX) packets time stamping based on user input.
421  *  Return Value:
422  *  0 on success and an appropriate -ve integer on failure.
423  */
424 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
425 {
426         struct stmmac_priv *priv = netdev_priv(dev);
427         struct hwtstamp_config config;
428         struct timespec64 now;
429         u64 temp = 0;
430         u32 ptp_v2 = 0;
431         u32 tstamp_all = 0;
432         u32 ptp_over_ipv4_udp = 0;
433         u32 ptp_over_ipv6_udp = 0;
434         u32 ptp_over_ethernet = 0;
435         u32 snap_type_sel = 0;
436         u32 ts_master_en = 0;
437         u32 ts_event_en = 0;
438         u32 value = 0;
439         u32 sec_inc;
440 
441         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
442                 netdev_alert(priv->dev, "No support for HW time stamping\n");
443                 priv->hwts_tx_en = 0;
444                 priv->hwts_rx_en = 0;
445 
446                 return -EOPNOTSUPP;
447         }
448 
449         if (copy_from_user(&config, ifr->ifr_data,
450                            sizeof(struct hwtstamp_config)))
451                 return -EFAULT;
452 
453         pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
454                  __func__, config.flags, config.tx_type, config.rx_filter);
455 
456         /* reserved for future extensions */
457         if (config.flags)
458                 return -EINVAL;
459 
460         if (config.tx_type != HWTSTAMP_TX_OFF &&
461             config.tx_type != HWTSTAMP_TX_ON)
462                 return -ERANGE;
463 
464         if (priv->adv_ts) {
465                 switch (config.rx_filter) {
466                 case HWTSTAMP_FILTER_NONE:
467                         /* time stamp no incoming packet at all */
468                         config.rx_filter = HWTSTAMP_FILTER_NONE;
469                         break;
470 
471                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
472                         /* PTP v1, UDP, any kind of event packet */
473                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
474                         /* take time stamp for all event messages */
475                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
476 
477                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
478                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
479                         break;
480 
481                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
482                         /* PTP v1, UDP, Sync packet */
483                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
484                         /* take time stamp for SYNC messages only */
485                         ts_event_en = PTP_TCR_TSEVNTENA;
486 
487                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
488                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
489                         break;
490 
491                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
492                         /* PTP v1, UDP, Delay_req packet */
493                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
494                         /* take time stamp for Delay_Req messages only */
495                         ts_master_en = PTP_TCR_TSMSTRENA;
496                         ts_event_en = PTP_TCR_TSEVNTENA;
497 
498                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
499                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
500                         break;
501 
502                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
503                         /* PTP v2, UDP, any kind of event packet */
504                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
505                         ptp_v2 = PTP_TCR_TSVER2ENA;
506                         /* take time stamp for all event messages */
507                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
508 
509                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
510                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
511                         break;
512 
513                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
514                         /* PTP v2, UDP, Sync packet */
515                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
516                         ptp_v2 = PTP_TCR_TSVER2ENA;
517                         /* take time stamp for SYNC messages only */
518                         ts_event_en = PTP_TCR_TSEVNTENA;
519 
520                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
521                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
522                         break;
523 
524                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
525                         /* PTP v2, UDP, Delay_req packet */
526                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
527                         ptp_v2 = PTP_TCR_TSVER2ENA;
528                         /* take time stamp for Delay_Req messages only */
529                         ts_master_en = PTP_TCR_TSMSTRENA;
530                         ts_event_en = PTP_TCR_TSEVNTENA;
531 
532                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
533                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
534                         break;
535 
536                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
537                         /* PTP v2/802.AS1 any layer, any kind of event packet */
538                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
539                         ptp_v2 = PTP_TCR_TSVER2ENA;
540                         /* take time stamp for all event messages */
541                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
542 
543                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
544                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
545                         ptp_over_ethernet = PTP_TCR_TSIPENA;
546                         break;
547 
548                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
549                         /* PTP v2/802.AS1, any layer, Sync packet */
550                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
551                         ptp_v2 = PTP_TCR_TSVER2ENA;
552                         /* take time stamp for SYNC messages only */
553                         ts_event_en = PTP_TCR_TSEVNTENA;
554 
555                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
556                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
557                         ptp_over_ethernet = PTP_TCR_TSIPENA;
558                         break;
559 
560                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
561                         /* PTP v2/802.AS1, any layer, Delay_req packet */
562                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
563                         ptp_v2 = PTP_TCR_TSVER2ENA;
564                         /* take time stamp for Delay_Req messages only */
565                         ts_master_en = PTP_TCR_TSMSTRENA;
566                         ts_event_en = PTP_TCR_TSEVNTENA;
567 
568                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
569                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
570                         ptp_over_ethernet = PTP_TCR_TSIPENA;
571                         break;
572 
573                 case HWTSTAMP_FILTER_ALL:
574                         /* time stamp any incoming packet */
575                         config.rx_filter = HWTSTAMP_FILTER_ALL;
576                         tstamp_all = PTP_TCR_TSENALL;
577                         break;
578 
579                 default:
580                         return -ERANGE;
581                 }
582         } else {
583                 switch (config.rx_filter) {
584                 case HWTSTAMP_FILTER_NONE:
585                         config.rx_filter = HWTSTAMP_FILTER_NONE;
586                         break;
587                 default:
588                         /* PTP v1, UDP, any kind of event packet */
589                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
590                         break;
591                 }
592         }
593         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
594         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
595 
596         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
597                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
598         else {
599                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
600                          tstamp_all | ptp_v2 | ptp_over_ethernet |
601                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
602                          ts_master_en | snap_type_sel);
603                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
604 
605                 /* program Sub Second Increment reg */
606                 sec_inc = priv->hw->ptp->config_sub_second_increment(
607                         priv->ioaddr, priv->clk_ptp_rate);
608                 temp = div_u64(1000000000ULL, sec_inc);
609 
610                 /* calculate default added value:
611                  * formula is :
612                  * addend = (2^32)/freq_div_ratio;
613                  * where, freq_div_ratio = 1e9ns/sec_inc
614                  */
615                 temp = (u64)(temp << 32);
616                 priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
617                 priv->hw->ptp->config_addend(priv->ioaddr,
618                                              priv->default_addend);
619 
620                 /* initialize system time */
621                 ktime_get_real_ts64(&now);
622 
623                 /* lower 32 bits of tv_sec are safe until y2106 */
624                 priv->hw->ptp->init_systime(priv->ioaddr, (u32)now.tv_sec,
625                                             now.tv_nsec);
626         }
627 
628         return copy_to_user(ifr->ifr_data, &config,
629                             sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
630 }
631 
632 /**
633  * stmmac_init_ptp - init PTP
634  * @priv: driver private structure
635  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
636  * This is done by looking at the HW cap. register.
637  * This function also registers the ptp driver.
638  */
639 static int stmmac_init_ptp(struct stmmac_priv *priv)
640 {
641         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
642                 return -EOPNOTSUPP;
643 
644         /* Fall-back to main clock in case of no PTP ref is passed */
645         priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref");
646         if (IS_ERR(priv->clk_ptp_ref)) {
647                 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk);
648                 priv->clk_ptp_ref = NULL;
649         } else {
650                 clk_prepare_enable(priv->clk_ptp_ref);
651                 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref);
652         }
653 
654         priv->adv_ts = 0;
655         if (priv->dma_cap.atime_stamp && priv->extend_desc)
656                 priv->adv_ts = 1;
657 
658         if (netif_msg_hw(priv) && priv->dma_cap.time_stamp)
659                 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
660 
661         if (netif_msg_hw(priv) && priv->adv_ts)
662                 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
663 
664         priv->hw->ptp = &stmmac_ptp;
665         priv->hwts_tx_en = 0;
666         priv->hwts_rx_en = 0;
667 
668         return stmmac_ptp_register(priv);
669 }
670 
671 static void stmmac_release_ptp(struct stmmac_priv *priv)
672 {
673         if (priv->clk_ptp_ref)
674                 clk_disable_unprepare(priv->clk_ptp_ref);
675         stmmac_ptp_unregister(priv);
676 }
677 
678 /**
679  * stmmac_adjust_link - adjusts the link parameters
680  * @dev: net device structure
681  * Description: this is the helper called by the physical abstraction layer
682  * drivers to communicate the phy link status. According the speed and duplex
683  * this driver can invoke registered glue-logic as well.
684  * It also invoke the eee initialization because it could happen when switch
685  * on different networks (that are eee capable).
686  */
687 static void stmmac_adjust_link(struct net_device *dev)
688 {
689         struct stmmac_priv *priv = netdev_priv(dev);
690         struct phy_device *phydev = priv->phydev;
691         unsigned long flags;
692         int new_state = 0;
693         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
694 
695         if (phydev == NULL)
696                 return;
697 
698         spin_lock_irqsave(&priv->lock, flags);
699 
700         if (phydev->link) {
701                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
702 
703                 /* Now we make sure that we can be in full duplex mode.
704                  * If not, we operate in half-duplex mode. */
705                 if (phydev->duplex != priv->oldduplex) {
706                         new_state = 1;
707                         if (!(phydev->duplex))
708                                 ctrl &= ~priv->hw->link.duplex;
709                         else
710                                 ctrl |= priv->hw->link.duplex;
711                         priv->oldduplex = phydev->duplex;
712                 }
713                 /* Flow Control operation */
714                 if (phydev->pause)
715                         priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex,
716                                                  fc, pause_time);
717 
718                 if (phydev->speed != priv->speed) {
719                         new_state = 1;
720                         switch (phydev->speed) {
721                         case 1000:
722                                 if (likely(priv->plat->has_gmac))
723                                         ctrl &= ~priv->hw->link.port;
724                                 stmmac_hw_fix_mac_speed(priv);
725                                 break;
726                         case 100:
727                         case 10:
728                                 if (priv->plat->has_gmac) {
729                                         ctrl |= priv->hw->link.port;
730                                         if (phydev->speed == SPEED_100) {
731                                                 ctrl |= priv->hw->link.speed;
732                                         } else {
733                                                 ctrl &= ~(priv->hw->link.speed);
734                                         }
735                                 } else {
736                                         ctrl &= ~priv->hw->link.port;
737                                 }
738                                 stmmac_hw_fix_mac_speed(priv);
739                                 break;
740                         default:
741                                 if (netif_msg_link(priv))
742                                         pr_warn("%s: Speed (%d) not 10/100\n",
743                                                 dev->name, phydev->speed);
744                                 break;
745                         }
746 
747                         priv->speed = phydev->speed;
748                 }
749 
750                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
751 
752                 if (!priv->oldlink) {
753                         new_state = 1;
754                         priv->oldlink = 1;
755                 }
756         } else if (priv->oldlink) {
757                 new_state = 1;
758                 priv->oldlink = 0;
759                 priv->speed = 0;
760                 priv->oldduplex = -1;
761         }
762 
763         if (new_state && netif_msg_link(priv))
764                 phy_print_status(phydev);
765 
766         spin_unlock_irqrestore(&priv->lock, flags);
767 
768         /* At this stage, it could be needed to setup the EEE or adjust some
769          * MAC related HW registers.
770          */
771         priv->eee_enabled = stmmac_eee_init(priv);
772 }
773 
774 /**
775  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
776  * @priv: driver private structure
777  * Description: this is to verify if the HW supports the PCS.
778  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
779  * configured for the TBI, RTBI, or SGMII PHY interface.
780  */
781 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
782 {
783         int interface = priv->plat->interface;
784 
785         if (priv->dma_cap.pcs) {
786                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
787                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
788                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
789                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
790                         pr_debug("STMMAC: PCS RGMII support enable\n");
791                         priv->pcs = STMMAC_PCS_RGMII;
792                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
793                         pr_debug("STMMAC: PCS SGMII support enable\n");
794                         priv->pcs = STMMAC_PCS_SGMII;
795                 }
796         }
797 }
798 
799 /**
800  * stmmac_init_phy - PHY initialization
801  * @dev: net device structure
802  * Description: it initializes the driver's PHY state, and attaches the PHY
803  * to the mac driver.
804  *  Return value:
805  *  0 on success
806  */
807 static int stmmac_init_phy(struct net_device *dev)
808 {
809         struct stmmac_priv *priv = netdev_priv(dev);
810         struct phy_device *phydev;
811         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
812         char bus_id[MII_BUS_ID_SIZE];
813         int interface = priv->plat->interface;
814         int max_speed = priv->plat->max_speed;
815         priv->oldlink = 0;
816         priv->speed = 0;
817         priv->oldduplex = -1;
818 
819         if (priv->plat->phy_node) {
820                 phydev = of_phy_connect(dev, priv->plat->phy_node,
821                                         &stmmac_adjust_link, 0, interface);
822         } else {
823                 if (priv->plat->phy_bus_name)
824                         snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
825                                  priv->plat->phy_bus_name, priv->plat->bus_id);
826                 else
827                         snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
828                                  priv->plat->bus_id);
829 
830                 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
831                          priv->plat->phy_addr);
832                 pr_debug("stmmac_init_phy:  trying to attach to %s\n",
833                          phy_id_fmt);
834 
835                 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
836                                      interface);
837         }
838 
839         if (IS_ERR_OR_NULL(phydev)) {
840                 pr_err("%s: Could not attach to PHY\n", dev->name);
841                 if (!phydev)
842                         return -ENODEV;
843 
844                 return PTR_ERR(phydev);
845         }
846 
847         /* Stop Advertising 1000BASE Capability if interface is not GMII */
848         if ((interface == PHY_INTERFACE_MODE_MII) ||
849             (interface == PHY_INTERFACE_MODE_RMII) ||
850                 (max_speed < 1000 && max_speed > 0))
851                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
852                                          SUPPORTED_1000baseT_Full);
853 
854         /*
855          * Broken HW is sometimes missing the pull-up resistor on the
856          * MDIO line, which results in reads to non-existent devices returning
857          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
858          * device as well.
859          * Note: phydev->phy_id is the result of reading the UID PHY registers.
860          */
861         if (!priv->plat->phy_node && phydev->phy_id == 0) {
862                 phy_disconnect(phydev);
863                 return -ENODEV;
864         }
865         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
866                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
867 
868         priv->phydev = phydev;
869 
870         return 0;
871 }
872 
873 /**
874  * stmmac_display_ring - display ring
875  * @head: pointer to the head of the ring passed.
876  * @size: size of the ring.
877  * @extend_desc: to verify if extended descriptors are used.
878  * Description: display the control/status and buffer descriptors.
879  */
880 static void stmmac_display_ring(void *head, int size, int extend_desc)
881 {
882         int i;
883         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
884         struct dma_desc *p = (struct dma_desc *)head;
885 
886         for (i = 0; i < size; i++) {
887                 u64 x;
888                 if (extend_desc) {
889                         x = *(u64 *) ep;
890                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
891                                 i, (unsigned int)virt_to_phys(ep),
892                                 (unsigned int)x, (unsigned int)(x >> 32),
893                                 ep->basic.des2, ep->basic.des3);
894                         ep++;
895                 } else {
896                         x = *(u64 *) p;
897                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
898                                 i, (unsigned int)virt_to_phys(p),
899                                 (unsigned int)x, (unsigned int)(x >> 32),
900                                 p->des2, p->des3);
901                         p++;
902                 }
903                 pr_info("\n");
904         }
905 }
906 
907 static void stmmac_display_rings(struct stmmac_priv *priv)
908 {
909         unsigned int txsize = priv->dma_tx_size;
910         unsigned int rxsize = priv->dma_rx_size;
911 
912         if (priv->extend_desc) {
913                 pr_info("Extended RX descriptor ring:\n");
914                 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
915                 pr_info("Extended TX descriptor ring:\n");
916                 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
917         } else {
918                 pr_info("RX descriptor ring:\n");
919                 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
920                 pr_info("TX descriptor ring:\n");
921                 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
922         }
923 }
924 
925 static int stmmac_set_bfsize(int mtu, int bufsize)
926 {
927         int ret = bufsize;
928 
929         if (mtu >= BUF_SIZE_4KiB)
930                 ret = BUF_SIZE_8KiB;
931         else if (mtu >= BUF_SIZE_2KiB)
932                 ret = BUF_SIZE_4KiB;
933         else if (mtu > DEFAULT_BUFSIZE)
934                 ret = BUF_SIZE_2KiB;
935         else
936                 ret = DEFAULT_BUFSIZE;
937 
938         return ret;
939 }
940 
941 /**
942  * stmmac_clear_descriptors - clear descriptors
943  * @priv: driver private structure
944  * Description: this function is called to clear the tx and rx descriptors
945  * in case of both basic and extended descriptors are used.
946  */
947 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
948 {
949         int i;
950         unsigned int txsize = priv->dma_tx_size;
951         unsigned int rxsize = priv->dma_rx_size;
952 
953         /* Clear the Rx/Tx descriptors */
954         for (i = 0; i < rxsize; i++)
955                 if (priv->extend_desc)
956                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
957                                                      priv->use_riwt, priv->mode,
958                                                      (i == rxsize - 1));
959                 else
960                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
961                                                      priv->use_riwt, priv->mode,
962                                                      (i == rxsize - 1));
963         for (i = 0; i < txsize; i++)
964                 if (priv->extend_desc)
965                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
966                                                      priv->mode,
967                                                      (i == txsize - 1));
968                 else
969                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
970                                                      priv->mode,
971                                                      (i == txsize - 1));
972 }
973 
974 /**
975  * stmmac_init_rx_buffers - init the RX descriptor buffer.
976  * @priv: driver private structure
977  * @p: descriptor pointer
978  * @i: descriptor index
979  * @flags: gfp flag.
980  * Description: this function is called to allocate a receive buffer, perform
981  * the DMA mapping and init the descriptor.
982  */
983 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
984                                   int i, gfp_t flags)
985 {
986         struct sk_buff *skb;
987 
988         skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
989         if (!skb) {
990                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
991                 return -ENOMEM;
992         }
993         priv->rx_skbuff[i] = skb;
994         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
995                                                 priv->dma_buf_sz,
996                                                 DMA_FROM_DEVICE);
997         if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
998                 pr_err("%s: DMA mapping error\n", __func__);
999                 dev_kfree_skb_any(skb);
1000                 return -EINVAL;
1001         }
1002 
1003         p->des2 = priv->rx_skbuff_dma[i];
1004 
1005         if ((priv->hw->mode->init_desc3) &&
1006             (priv->dma_buf_sz == BUF_SIZE_16KiB))
1007                 priv->hw->mode->init_desc3(p);
1008 
1009         return 0;
1010 }
1011 
1012 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
1013 {
1014         if (priv->rx_skbuff[i]) {
1015                 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1016                                  priv->dma_buf_sz, DMA_FROM_DEVICE);
1017                 dev_kfree_skb_any(priv->rx_skbuff[i]);
1018         }
1019         priv->rx_skbuff[i] = NULL;
1020 }
1021 
1022 /**
1023  * init_dma_desc_rings - init the RX/TX descriptor rings
1024  * @dev: net device structure
1025  * @flags: gfp flag.
1026  * Description: this function initializes the DMA RX/TX descriptors
1027  * and allocates the socket buffers. It suppors the chained and ring
1028  * modes.
1029  */
1030 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1031 {
1032         int i;
1033         struct stmmac_priv *priv = netdev_priv(dev);
1034         unsigned int txsize = priv->dma_tx_size;
1035         unsigned int rxsize = priv->dma_rx_size;
1036         unsigned int bfsize = 0;
1037         int ret = -ENOMEM;
1038 
1039         if (priv->hw->mode->set_16kib_bfsize)
1040                 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1041 
1042         if (bfsize < BUF_SIZE_16KiB)
1043                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1044 
1045         priv->dma_buf_sz = bfsize;
1046 
1047         if (netif_msg_probe(priv))
1048                 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__,
1049                          txsize, rxsize, bfsize);
1050 
1051         if (netif_msg_probe(priv)) {
1052                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1053                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1054 
1055                 /* RX INITIALIZATION */
1056                 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1057         }
1058         for (i = 0; i < rxsize; i++) {
1059                 struct dma_desc *p;
1060                 if (priv->extend_desc)
1061                         p = &((priv->dma_erx + i)->basic);
1062                 else
1063                         p = priv->dma_rx + i;
1064 
1065                 ret = stmmac_init_rx_buffers(priv, p, i, flags);
1066                 if (ret)
1067                         goto err_init_rx_buffers;
1068 
1069                 if (netif_msg_probe(priv))
1070                         pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1071                                  priv->rx_skbuff[i]->data,
1072                                  (unsigned int)priv->rx_skbuff_dma[i]);
1073         }
1074         priv->cur_rx = 0;
1075         priv->dirty_rx = (unsigned int)(i - rxsize);
1076         buf_sz = bfsize;
1077 
1078         /* Setup the chained descriptor addresses */
1079         if (priv->mode == STMMAC_CHAIN_MODE) {
1080                 if (priv->extend_desc) {
1081                         priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1082                                              rxsize, 1);
1083                         priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1084                                              txsize, 1);
1085                 } else {
1086                         priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1087                                              rxsize, 0);
1088                         priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1089                                              txsize, 0);
1090                 }
1091         }
1092 
1093         /* TX INITIALIZATION */
1094         for (i = 0; i < txsize; i++) {
1095                 struct dma_desc *p;
1096                 if (priv->extend_desc)
1097                         p = &((priv->dma_etx + i)->basic);
1098                 else
1099                         p = priv->dma_tx + i;
1100                 p->des2 = 0;
1101                 priv->tx_skbuff_dma[i].buf = 0;
1102                 priv->tx_skbuff_dma[i].map_as_page = false;
1103                 priv->tx_skbuff[i] = NULL;
1104         }
1105 
1106         priv->dirty_tx = 0;
1107         priv->cur_tx = 0;
1108         netdev_reset_queue(priv->dev);
1109 
1110         stmmac_clear_descriptors(priv);
1111 
1112         if (netif_msg_hw(priv))
1113                 stmmac_display_rings(priv);
1114 
1115         return 0;
1116 err_init_rx_buffers:
1117         while (--i >= 0)
1118                 stmmac_free_rx_buffers(priv, i);
1119         return ret;
1120 }
1121 
1122 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1123 {
1124         int i;
1125 
1126         for (i = 0; i < priv->dma_rx_size; i++)
1127                 stmmac_free_rx_buffers(priv, i);
1128 }
1129 
1130 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1131 {
1132         int i;
1133 
1134         for (i = 0; i < priv->dma_tx_size; i++) {
1135                 struct dma_desc *p;
1136 
1137                 if (priv->extend_desc)
1138                         p = &((priv->dma_etx + i)->basic);
1139                 else
1140                         p = priv->dma_tx + i;
1141 
1142                 if (priv->tx_skbuff_dma[i].buf) {
1143                         if (priv->tx_skbuff_dma[i].map_as_page)
1144                                 dma_unmap_page(priv->device,
1145                                                priv->tx_skbuff_dma[i].buf,
1146                                                priv->hw->desc->get_tx_len(p),
1147                                                DMA_TO_DEVICE);
1148                         else
1149                                 dma_unmap_single(priv->device,
1150                                                  priv->tx_skbuff_dma[i].buf,
1151                                                  priv->hw->desc->get_tx_len(p),
1152                                                  DMA_TO_DEVICE);
1153                 }
1154 
1155                 if (priv->tx_skbuff[i] != NULL) {
1156                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1157                         priv->tx_skbuff[i] = NULL;
1158                         priv->tx_skbuff_dma[i].buf = 0;
1159                         priv->tx_skbuff_dma[i].map_as_page = false;
1160                 }
1161         }
1162 }
1163 
1164 /**
1165  * alloc_dma_desc_resources - alloc TX/RX resources.
1166  * @priv: private structure
1167  * Description: according to which descriptor can be used (extend or basic)
1168  * this function allocates the resources for TX and RX paths. In case of
1169  * reception, for example, it pre-allocated the RX socket buffer in order to
1170  * allow zero-copy mechanism.
1171  */
1172 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1173 {
1174         unsigned int txsize = priv->dma_tx_size;
1175         unsigned int rxsize = priv->dma_rx_size;
1176         int ret = -ENOMEM;
1177 
1178         priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
1179                                             GFP_KERNEL);
1180         if (!priv->rx_skbuff_dma)
1181                 return -ENOMEM;
1182 
1183         priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
1184                                         GFP_KERNEL);
1185         if (!priv->rx_skbuff)
1186                 goto err_rx_skbuff;
1187 
1188         priv->tx_skbuff_dma = kmalloc_array(txsize,
1189                                             sizeof(*priv->tx_skbuff_dma),
1190                                             GFP_KERNEL);
1191         if (!priv->tx_skbuff_dma)
1192                 goto err_tx_skbuff_dma;
1193 
1194         priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
1195                                         GFP_KERNEL);
1196         if (!priv->tx_skbuff)
1197                 goto err_tx_skbuff;
1198 
1199         if (priv->extend_desc) {
1200                 priv->dma_erx = dma_zalloc_coherent(priv->device, rxsize *
1201                                                     sizeof(struct
1202                                                            dma_extended_desc),
1203                                                     &priv->dma_rx_phy,
1204                                                     GFP_KERNEL);
1205                 if (!priv->dma_erx)
1206                         goto err_dma;
1207 
1208                 priv->dma_etx = dma_zalloc_coherent(priv->device, txsize *
1209                                                     sizeof(struct
1210                                                            dma_extended_desc),
1211                                                     &priv->dma_tx_phy,
1212                                                     GFP_KERNEL);
1213                 if (!priv->dma_etx) {
1214                         dma_free_coherent(priv->device, priv->dma_rx_size *
1215                                           sizeof(struct dma_extended_desc),
1216                                           priv->dma_erx, priv->dma_rx_phy);
1217                         goto err_dma;
1218                 }
1219         } else {
1220                 priv->dma_rx = dma_zalloc_coherent(priv->device, rxsize *
1221                                                    sizeof(struct dma_desc),
1222                                                    &priv->dma_rx_phy,
1223                                                    GFP_KERNEL);
1224                 if (!priv->dma_rx)
1225                         goto err_dma;
1226 
1227                 priv->dma_tx = dma_zalloc_coherent(priv->device, txsize *
1228                                                    sizeof(struct dma_desc),
1229                                                    &priv->dma_tx_phy,
1230                                                    GFP_KERNEL);
1231                 if (!priv->dma_tx) {
1232                         dma_free_coherent(priv->device, priv->dma_rx_size *
1233                                           sizeof(struct dma_desc),
1234                                           priv->dma_rx, priv->dma_rx_phy);
1235                         goto err_dma;
1236                 }
1237         }
1238 
1239         return 0;
1240 
1241 err_dma:
1242         kfree(priv->tx_skbuff);
1243 err_tx_skbuff:
1244         kfree(priv->tx_skbuff_dma);
1245 err_tx_skbuff_dma:
1246         kfree(priv->rx_skbuff);
1247 err_rx_skbuff:
1248         kfree(priv->rx_skbuff_dma);
1249         return ret;
1250 }
1251 
1252 static void free_dma_desc_resources(struct stmmac_priv *priv)
1253 {
1254         /* Release the DMA TX/RX socket buffers */
1255         dma_free_rx_skbufs(priv);
1256         dma_free_tx_skbufs(priv);
1257 
1258         /* Free DMA regions of consistent memory previously allocated */
1259         if (!priv->extend_desc) {
1260                 dma_free_coherent(priv->device,
1261                                   priv->dma_tx_size * sizeof(struct dma_desc),
1262                                   priv->dma_tx, priv->dma_tx_phy);
1263                 dma_free_coherent(priv->device,
1264                                   priv->dma_rx_size * sizeof(struct dma_desc),
1265                                   priv->dma_rx, priv->dma_rx_phy);
1266         } else {
1267                 dma_free_coherent(priv->device, priv->dma_tx_size *
1268                                   sizeof(struct dma_extended_desc),
1269                                   priv->dma_etx, priv->dma_tx_phy);
1270                 dma_free_coherent(priv->device, priv->dma_rx_size *
1271                                   sizeof(struct dma_extended_desc),
1272                                   priv->dma_erx, priv->dma_rx_phy);
1273         }
1274         kfree(priv->rx_skbuff_dma);
1275         kfree(priv->rx_skbuff);
1276         kfree(priv->tx_skbuff_dma);
1277         kfree(priv->tx_skbuff);
1278 }
1279 
1280 /**
1281  *  stmmac_dma_operation_mode - HW DMA operation mode
1282  *  @priv: driver private structure
1283  *  Description: it is used for configuring the DMA operation mode register in
1284  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1285  */
1286 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1287 {
1288         int rxfifosz = priv->plat->rx_fifo_size;
1289 
1290         if (priv->plat->force_thresh_dma_mode)
1291                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz);
1292         else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1293                 /*
1294                  * In case of GMAC, SF mode can be enabled
1295                  * to perform the TX COE in HW. This depends on:
1296                  * 1) TX COE if actually supported
1297                  * 2) There is no bugged Jumbo frame support
1298                  *    that needs to not insert csum in the TDES.
1299                  */
1300                 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE,
1301                                         rxfifosz);
1302                 priv->xstats.threshold = SF_DMA_MODE;
1303         } else
1304                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE,
1305                                         rxfifosz);
1306 }
1307 
1308 /**
1309  * stmmac_tx_clean - to manage the transmission completion
1310  * @priv: driver private structure
1311  * Description: it reclaims the transmit resources after transmission completes.
1312  */
1313 static void stmmac_tx_clean(struct stmmac_priv *priv)
1314 {
1315         unsigned int txsize = priv->dma_tx_size;
1316         unsigned int bytes_compl = 0, pkts_compl = 0;
1317 
1318         spin_lock(&priv->tx_lock);
1319 
1320         priv->xstats.tx_clean++;
1321 
1322         while (priv->dirty_tx != priv->cur_tx) {
1323                 int last;
1324                 unsigned int entry = priv->dirty_tx % txsize;
1325                 struct sk_buff *skb = priv->tx_skbuff[entry];
1326                 struct dma_desc *p;
1327 
1328                 if (priv->extend_desc)
1329                         p = (struct dma_desc *)(priv->dma_etx + entry);
1330                 else
1331                         p = priv->dma_tx + entry;
1332 
1333                 /* Check if the descriptor is owned by the DMA. */
1334                 if (priv->hw->desc->get_tx_owner(p))
1335                         break;
1336 
1337                 /* Verify tx error by looking at the last segment. */
1338                 last = priv->hw->desc->get_tx_ls(p);
1339                 if (likely(last)) {
1340                         int tx_error =
1341                             priv->hw->desc->tx_status(&priv->dev->stats,
1342                                                       &priv->xstats, p,
1343                                                       priv->ioaddr);
1344                         if (likely(tx_error == 0)) {
1345                                 priv->dev->stats.tx_packets++;
1346                                 priv->xstats.tx_pkt_n++;
1347                         } else
1348                                 priv->dev->stats.tx_errors++;
1349 
1350                         stmmac_get_tx_hwtstamp(priv, entry, skb);
1351                 }
1352                 if (netif_msg_tx_done(priv))
1353                         pr_debug("%s: curr %d, dirty %d\n", __func__,
1354                                  priv->cur_tx, priv->dirty_tx);
1355 
1356                 if (likely(priv->tx_skbuff_dma[entry].buf)) {
1357                         if (priv->tx_skbuff_dma[entry].map_as_page)
1358                                 dma_unmap_page(priv->device,
1359                                                priv->tx_skbuff_dma[entry].buf,
1360                                                priv->hw->desc->get_tx_len(p),
1361                                                DMA_TO_DEVICE);
1362                         else
1363                                 dma_unmap_single(priv->device,
1364                                                  priv->tx_skbuff_dma[entry].buf,
1365                                                  priv->hw->desc->get_tx_len(p),
1366                                                  DMA_TO_DEVICE);
1367                         priv->tx_skbuff_dma[entry].buf = 0;
1368                         priv->tx_skbuff_dma[entry].map_as_page = false;
1369                 }
1370                 priv->hw->mode->clean_desc3(priv, p);
1371 
1372                 if (likely(skb != NULL)) {
1373                         pkts_compl++;
1374                         bytes_compl += skb->len;
1375                         dev_consume_skb_any(skb);
1376                         priv->tx_skbuff[entry] = NULL;
1377                 }
1378 
1379                 priv->hw->desc->release_tx_desc(p, priv->mode);
1380 
1381                 priv->dirty_tx++;
1382         }
1383 
1384         netdev_completed_queue(priv->dev, pkts_compl, bytes_compl);
1385 
1386         if (unlikely(netif_queue_stopped(priv->dev) &&
1387                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
1388                 netif_tx_lock(priv->dev);
1389                 if (netif_queue_stopped(priv->dev) &&
1390                     stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
1391                         if (netif_msg_tx_done(priv))
1392                                 pr_debug("%s: restart transmit\n", __func__);
1393                         netif_wake_queue(priv->dev);
1394                 }
1395                 netif_tx_unlock(priv->dev);
1396         }
1397 
1398         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1399                 stmmac_enable_eee_mode(priv);
1400                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1401         }
1402         spin_unlock(&priv->tx_lock);
1403 }
1404 
1405 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1406 {
1407         priv->hw->dma->enable_dma_irq(priv->ioaddr);
1408 }
1409 
1410 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1411 {
1412         priv->hw->dma->disable_dma_irq(priv->ioaddr);
1413 }
1414 
1415 /**
1416  * stmmac_tx_err - to manage the tx error
1417  * @priv: driver private structure
1418  * Description: it cleans the descriptors and restarts the transmission
1419  * in case of transmission errors.
1420  */
1421 static void stmmac_tx_err(struct stmmac_priv *priv)
1422 {
1423         int i;
1424         int txsize = priv->dma_tx_size;
1425         netif_stop_queue(priv->dev);
1426 
1427         priv->hw->dma->stop_tx(priv->ioaddr);
1428         dma_free_tx_skbufs(priv);
1429         for (i = 0; i < txsize; i++)
1430                 if (priv->extend_desc)
1431                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1432                                                      priv->mode,
1433                                                      (i == txsize - 1));
1434                 else
1435                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1436                                                      priv->mode,
1437                                                      (i == txsize - 1));
1438         priv->dirty_tx = 0;
1439         priv->cur_tx = 0;
1440         netdev_reset_queue(priv->dev);
1441         priv->hw->dma->start_tx(priv->ioaddr);
1442 
1443         priv->dev->stats.tx_errors++;
1444         netif_wake_queue(priv->dev);
1445 }
1446 
1447 /**
1448  * stmmac_dma_interrupt - DMA ISR
1449  * @priv: driver private structure
1450  * Description: this is the DMA ISR. It is called by the main ISR.
1451  * It calls the dwmac dma routine and schedule poll method in case of some
1452  * work can be done.
1453  */
1454 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1455 {
1456         int status;
1457         int rxfifosz = priv->plat->rx_fifo_size;
1458 
1459         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1460         if (likely((status & handle_rx)) || (status & handle_tx)) {
1461                 if (likely(napi_schedule_prep(&priv->napi))) {
1462                         stmmac_disable_dma_irq(priv);
1463                         __napi_schedule(&priv->napi);
1464                 }
1465         }
1466         if (unlikely(status & tx_hard_error_bump_tc)) {
1467                 /* Try to bump up the dma threshold on this failure */
1468                 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
1469                     (tc <= 256)) {
1470                         tc += 64;
1471                         if (priv->plat->force_thresh_dma_mode)
1472                                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc,
1473                                                         rxfifosz);
1474                         else
1475                                 priv->hw->dma->dma_mode(priv->ioaddr, tc,
1476                                                         SF_DMA_MODE, rxfifosz);
1477                         priv->xstats.threshold = tc;
1478                 }
1479         } else if (unlikely(status == tx_hard_error))
1480                 stmmac_tx_err(priv);
1481 }
1482 
1483 /**
1484  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1485  * @priv: driver private structure
1486  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1487  */
1488 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1489 {
1490         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1491             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1492 
1493         dwmac_mmc_intr_all_mask(priv->ioaddr);
1494 
1495         if (priv->dma_cap.rmon) {
1496                 dwmac_mmc_ctrl(priv->ioaddr, mode);
1497                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1498         } else
1499                 pr_info(" No MAC Management Counters available\n");
1500 }
1501 
1502 /**
1503  * stmmac_get_synopsys_id - return the SYINID.
1504  * @priv: driver private structure
1505  * Description: this simple function is to decode and return the SYINID
1506  * starting from the HW core register.
1507  */
1508 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1509 {
1510         u32 hwid = priv->hw->synopsys_uid;
1511 
1512         /* Check Synopsys Id (not available on old chips) */
1513         if (likely(hwid)) {
1514                 u32 uid = ((hwid & 0x0000ff00) >> 8);
1515                 u32 synid = (hwid & 0x000000ff);
1516 
1517                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1518                         uid, synid);
1519 
1520                 return synid;
1521         }
1522         return 0;
1523 }
1524 
1525 /**
1526  * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1527  * @priv: driver private structure
1528  * Description: select the Enhanced/Alternate or Normal descriptors.
1529  * In case of Enhanced/Alternate, it checks if the extended descriptors are
1530  * supported by the HW capability register.
1531  */
1532 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1533 {
1534         if (priv->plat->enh_desc) {
1535                 pr_info(" Enhanced/Alternate descriptors\n");
1536 
1537                 /* GMAC older than 3.50 has no extended descriptors */
1538                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1539                         pr_info("\tEnabled extended descriptors\n");
1540                         priv->extend_desc = 1;
1541                 } else
1542                         pr_warn("Extended descriptors not supported\n");
1543 
1544                 priv->hw->desc = &enh_desc_ops;
1545         } else {
1546                 pr_info(" Normal descriptors\n");
1547                 priv->hw->desc = &ndesc_ops;
1548         }
1549 }
1550 
1551 /**
1552  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1553  * @priv: driver private structure
1554  * Description:
1555  *  new GMAC chip generations have a new register to indicate the
1556  *  presence of the optional feature/functions.
1557  *  This can be also used to override the value passed through the
1558  *  platform and necessary for old MAC10/100 and GMAC chips.
1559  */
1560 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1561 {
1562         u32 hw_cap = 0;
1563 
1564         if (priv->hw->dma->get_hw_feature) {
1565                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1566 
1567                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1568                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1569                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1570                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1571                 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1572                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1573                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1574                 priv->dma_cap.pmt_remote_wake_up =
1575                     (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1576                 priv->dma_cap.pmt_magic_frame =
1577                     (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1578                 /* MMC */
1579                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1580                 /* IEEE 1588-2002 */
1581                 priv->dma_cap.time_stamp =
1582                     (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1583                 /* IEEE 1588-2008 */
1584                 priv->dma_cap.atime_stamp =
1585                     (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1586                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1587                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1588                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1589                 /* TX and RX csum */
1590                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1591                 priv->dma_cap.rx_coe_type1 =
1592                     (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1593                 priv->dma_cap.rx_coe_type2 =
1594                     (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1595                 priv->dma_cap.rxfifo_over_2048 =
1596                     (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1597                 /* TX and RX number of channels */
1598                 priv->dma_cap.number_rx_channel =
1599                     (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1600                 priv->dma_cap.number_tx_channel =
1601                     (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1602                 /* Alternate (enhanced) DESC mode */
1603                 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1604         }
1605 
1606         return hw_cap;
1607 }
1608 
1609 /**
1610  * stmmac_check_ether_addr - check if the MAC addr is valid
1611  * @priv: driver private structure
1612  * Description:
1613  * it is to verify if the MAC address is valid, in case of failures it
1614  * generates a random MAC address
1615  */
1616 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1617 {
1618         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1619                 priv->hw->mac->get_umac_addr(priv->hw,
1620                                              priv->dev->dev_addr, 0);
1621                 if (!is_valid_ether_addr(priv->dev->dev_addr))
1622                         eth_hw_addr_random(priv->dev);
1623                 pr_info("%s: device MAC address %pM\n", priv->dev->name,
1624                         priv->dev->dev_addr);
1625         }
1626 }
1627 
1628 /**
1629  * stmmac_init_dma_engine - DMA init.
1630  * @priv: driver private structure
1631  * Description:
1632  * It inits the DMA invoking the specific MAC/GMAC callback.
1633  * Some DMA parameters can be passed from the platform;
1634  * in case of these are not passed a default is kept for the MAC or GMAC.
1635  */
1636 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1637 {
1638         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1639         int mixed_burst = 0;
1640         int atds = 0;
1641 
1642         if (priv->plat->dma_cfg) {
1643                 pbl = priv->plat->dma_cfg->pbl;
1644                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1645                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1646                 burst_len = priv->plat->dma_cfg->burst_len;
1647         }
1648 
1649         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1650                 atds = 1;
1651 
1652         return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1653                                    burst_len, priv->dma_tx_phy,
1654                                    priv->dma_rx_phy, atds);
1655 }
1656 
1657 /**
1658  * stmmac_tx_timer - mitigation sw timer for tx.
1659  * @data: data pointer
1660  * Description:
1661  * This is the timer handler to directly invoke the stmmac_tx_clean.
1662  */
1663 static void stmmac_tx_timer(unsigned long data)
1664 {
1665         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1666 
1667         stmmac_tx_clean(priv);
1668 }
1669 
1670 /**
1671  * stmmac_init_tx_coalesce - init tx mitigation options.
1672  * @priv: driver private structure
1673  * Description:
1674  * This inits the transmit coalesce parameters: i.e. timer rate,
1675  * timer handler and default threshold used for enabling the
1676  * interrupt on completion bit.
1677  */
1678 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1679 {
1680         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1681         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1682         init_timer(&priv->txtimer);
1683         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1684         priv->txtimer.data = (unsigned long)priv;
1685         priv->txtimer.function = stmmac_tx_timer;
1686         add_timer(&priv->txtimer);
1687 }
1688 
1689 /**
1690  * stmmac_hw_setup - setup mac in a usable state.
1691  *  @dev : pointer to the device structure.
1692  *  Description:
1693  *  this is the main function to setup the HW in a usable state because the
1694  *  dma engine is reset, the core registers are configured (e.g. AXI,
1695  *  Checksum features, timers). The DMA is ready to start receiving and
1696  *  transmitting.
1697  *  Return value:
1698  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1699  *  file on failure.
1700  */
1701 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
1702 {
1703         struct stmmac_priv *priv = netdev_priv(dev);
1704         int ret;
1705 
1706         /* DMA initialization and SW reset */
1707         ret = stmmac_init_dma_engine(priv);
1708         if (ret < 0) {
1709                 pr_err("%s: DMA engine initialization failed\n", __func__);
1710                 return ret;
1711         }
1712 
1713         /* Copy the MAC addr into the HW  */
1714         priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1715 
1716         /* If required, perform hw setup of the bus. */
1717         if (priv->plat->bus_setup)
1718                 priv->plat->bus_setup(priv->ioaddr);
1719 
1720         /* Initialize the MAC Core */
1721         priv->hw->mac->core_init(priv->hw, dev->mtu);
1722 
1723         ret = priv->hw->mac->rx_ipc(priv->hw);
1724         if (!ret) {
1725                 pr_warn(" RX IPC Checksum Offload disabled\n");
1726                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1727                 priv->hw->rx_csum = 0;
1728         }
1729 
1730         /* Enable the MAC Rx/Tx */
1731         stmmac_set_mac(priv->ioaddr, true);
1732 
1733         /* Set the HW DMA mode and the COE */
1734         stmmac_dma_operation_mode(priv);
1735 
1736         stmmac_mmc_setup(priv);
1737 
1738         if (init_ptp) {
1739                 ret = stmmac_init_ptp(priv);
1740                 if (ret && ret != -EOPNOTSUPP)
1741                         pr_warn("%s: failed PTP initialisation\n", __func__);
1742         }
1743 
1744 #ifdef CONFIG_DEBUG_FS
1745         ret = stmmac_init_fs(dev);
1746         if (ret < 0)
1747                 pr_warn("%s: failed debugFS registration\n", __func__);
1748 #endif
1749         /* Start the ball rolling... */
1750         pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
1751         priv->hw->dma->start_tx(priv->ioaddr);
1752         priv->hw->dma->start_rx(priv->ioaddr);
1753 
1754         /* Dump DMA/MAC registers */
1755         if (netif_msg_hw(priv)) {
1756                 priv->hw->mac->dump_regs(priv->hw);
1757                 priv->hw->dma->dump_regs(priv->ioaddr);
1758         }
1759         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1760 
1761         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1762                 priv->rx_riwt = MAX_DMA_RIWT;
1763                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1764         }
1765 
1766         if (priv->pcs && priv->hw->mac->ctrl_ane)
1767                 priv->hw->mac->ctrl_ane(priv->hw, 0);
1768 
1769         return 0;
1770 }
1771 
1772 /**
1773  *  stmmac_open - open entry point of the driver
1774  *  @dev : pointer to the device structure.
1775  *  Description:
1776  *  This function is the open entry point of the driver.
1777  *  Return value:
1778  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1779  *  file on failure.
1780  */
1781 static int stmmac_open(struct net_device *dev)
1782 {
1783         struct stmmac_priv *priv = netdev_priv(dev);
1784         int ret;
1785 
1786         stmmac_check_ether_addr(priv);
1787 
1788         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1789             priv->pcs != STMMAC_PCS_RTBI) {
1790                 ret = stmmac_init_phy(dev);
1791                 if (ret) {
1792                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1793                                __func__, ret);
1794                         return ret;
1795                 }
1796         }
1797 
1798         /* Extra statistics */
1799         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1800         priv->xstats.threshold = tc;
1801 
1802         /* Create and initialize the TX/RX descriptors chains. */
1803         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1804         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1805         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1806 
1807         ret = alloc_dma_desc_resources(priv);
1808         if (ret < 0) {
1809                 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1810                 goto dma_desc_error;
1811         }
1812 
1813         ret = init_dma_desc_rings(dev, GFP_KERNEL);
1814         if (ret < 0) {
1815                 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1816                 goto init_error;
1817         }
1818 
1819         ret = stmmac_hw_setup(dev, true);
1820         if (ret < 0) {
1821                 pr_err("%s: Hw setup failed\n", __func__);
1822                 goto init_error;
1823         }
1824 
1825         stmmac_init_tx_coalesce(priv);
1826 
1827         if (priv->phydev)
1828                 phy_start(priv->phydev);
1829 
1830         /* Request the IRQ lines */
1831         ret = request_irq(dev->irq, stmmac_interrupt,
1832                           IRQF_SHARED, dev->name, dev);
1833         if (unlikely(ret < 0)) {
1834                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1835                        __func__, dev->irq, ret);
1836                 goto init_error;
1837         }
1838 
1839         /* Request the Wake IRQ in case of another line is used for WoL */
1840         if (priv->wol_irq != dev->irq) {
1841                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1842                                   IRQF_SHARED, dev->name, dev);
1843                 if (unlikely(ret < 0)) {
1844                         pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1845                                __func__, priv->wol_irq, ret);
1846                         goto wolirq_error;
1847                 }
1848         }
1849 
1850         /* Request the IRQ lines */
1851         if (priv->lpi_irq > 0) {
1852                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1853                                   dev->name, dev);
1854                 if (unlikely(ret < 0)) {
1855                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1856                                __func__, priv->lpi_irq, ret);
1857                         goto lpiirq_error;
1858                 }
1859         }
1860 
1861         napi_enable(&priv->napi);
1862         netif_start_queue(dev);
1863 
1864         return 0;
1865 
1866 lpiirq_error:
1867         if (priv->wol_irq != dev->irq)
1868                 free_irq(priv->wol_irq, dev);
1869 wolirq_error:
1870         free_irq(dev->irq, dev);
1871 
1872 init_error:
1873         free_dma_desc_resources(priv);
1874 dma_desc_error:
1875         if (priv->phydev)
1876                 phy_disconnect(priv->phydev);
1877 
1878         return ret;
1879 }
1880 
1881 /**
1882  *  stmmac_release - close entry point of the driver
1883  *  @dev : device pointer.
1884  *  Description:
1885  *  This is the stop entry point of the driver.
1886  */
1887 static int stmmac_release(struct net_device *dev)
1888 {
1889         struct stmmac_priv *priv = netdev_priv(dev);
1890 
1891         if (priv->eee_enabled)
1892                 del_timer_sync(&priv->eee_ctrl_timer);
1893 
1894         /* Stop and disconnect the PHY */
1895         if (priv->phydev) {
1896                 phy_stop(priv->phydev);
1897                 phy_disconnect(priv->phydev);
1898                 priv->phydev = NULL;
1899         }
1900 
1901         netif_stop_queue(dev);
1902 
1903         napi_disable(&priv->napi);
1904 
1905         del_timer_sync(&priv->txtimer);
1906 
1907         /* Free the IRQ lines */
1908         free_irq(dev->irq, dev);
1909         if (priv->wol_irq != dev->irq)
1910                 free_irq(priv->wol_irq, dev);
1911         if (priv->lpi_irq > 0)
1912                 free_irq(priv->lpi_irq, dev);
1913 
1914         /* Stop TX/RX DMA and clear the descriptors */
1915         priv->hw->dma->stop_tx(priv->ioaddr);
1916         priv->hw->dma->stop_rx(priv->ioaddr);
1917 
1918         /* Release and free the Rx/Tx resources */
1919         free_dma_desc_resources(priv);
1920 
1921         /* Disable the MAC Rx/Tx */
1922         stmmac_set_mac(priv->ioaddr, false);
1923 
1924         netif_carrier_off(dev);
1925 
1926 #ifdef CONFIG_DEBUG_FS
1927         stmmac_exit_fs(dev);
1928 #endif
1929 
1930         stmmac_release_ptp(priv);
1931 
1932         return 0;
1933 }
1934 
1935 /**
1936  *  stmmac_xmit - Tx entry point of the driver
1937  *  @skb : the socket buffer
1938  *  @dev : device pointer
1939  *  Description : this is the tx entry point of the driver.
1940  *  It programs the chain or the ring and supports oversized frames
1941  *  and SG feature.
1942  */
1943 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1944 {
1945         struct stmmac_priv *priv = netdev_priv(dev);
1946         unsigned int txsize = priv->dma_tx_size;
1947         int entry;
1948         int i, csum_insertion = 0, is_jumbo = 0;
1949         int nfrags = skb_shinfo(skb)->nr_frags;
1950         struct dma_desc *desc, *first;
1951         unsigned int nopaged_len = skb_headlen(skb);
1952         unsigned int enh_desc = priv->plat->enh_desc;
1953 
1954         spin_lock(&priv->tx_lock);
1955 
1956         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1957                 spin_unlock(&priv->tx_lock);
1958                 if (!netif_queue_stopped(dev)) {
1959                         netif_stop_queue(dev);
1960                         /* This is a hard error, log it. */
1961                         pr_err("%s: Tx Ring full when queue awake\n", __func__);
1962                 }
1963                 return NETDEV_TX_BUSY;
1964         }
1965 
1966         if (priv->tx_path_in_lpi_mode)
1967                 stmmac_disable_eee_mode(priv);
1968 
1969         entry = priv->cur_tx % txsize;
1970 
1971         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1972 
1973         if (priv->extend_desc)
1974                 desc = (struct dma_desc *)(priv->dma_etx + entry);
1975         else
1976                 desc = priv->dma_tx + entry;
1977 
1978         first = desc;
1979 
1980         /* To program the descriptors according to the size of the frame */
1981         if (enh_desc)
1982                 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
1983 
1984         if (likely(!is_jumbo)) {
1985                 desc->des2 = dma_map_single(priv->device, skb->data,
1986                                             nopaged_len, DMA_TO_DEVICE);
1987                 if (dma_mapping_error(priv->device, desc->des2))
1988                         goto dma_map_err;
1989                 priv->tx_skbuff_dma[entry].buf = desc->des2;
1990                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1991                                                 csum_insertion, priv->mode);
1992         } else {
1993                 desc = first;
1994                 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
1995                 if (unlikely(entry < 0))
1996                         goto dma_map_err;
1997         }
1998 
1999         for (i = 0; i < nfrags; i++) {
2000                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2001                 int len = skb_frag_size(frag);
2002 
2003                 priv->tx_skbuff[entry] = NULL;
2004                 entry = (++priv->cur_tx) % txsize;
2005                 if (priv->extend_desc)
2006                         desc = (struct dma_desc *)(priv->dma_etx + entry);
2007                 else
2008                         desc = priv->dma_tx + entry;
2009 
2010                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
2011                                               DMA_TO_DEVICE);
2012                 if (dma_mapping_error(priv->device, desc->des2))
2013                         goto dma_map_err; /* should reuse desc w/o issues */
2014 
2015                 priv->tx_skbuff_dma[entry].buf = desc->des2;
2016                 priv->tx_skbuff_dma[entry].map_as_page = true;
2017                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
2018                                                 priv->mode);
2019                 wmb();
2020                 priv->hw->desc->set_tx_owner(desc);
2021                 wmb();
2022         }
2023 
2024         priv->tx_skbuff[entry] = skb;
2025 
2026         /* Finalize the latest segment. */
2027         priv->hw->desc->close_tx_desc(desc);
2028 
2029         wmb();
2030         /* According to the coalesce parameter the IC bit for the latest
2031          * segment could be reset and the timer re-started to invoke the
2032          * stmmac_tx function. This approach takes care about the fragments.
2033          */
2034         priv->tx_count_frames += nfrags + 1;
2035         if (priv->tx_coal_frames > priv->tx_count_frames) {
2036                 priv->hw->desc->clear_tx_ic(desc);
2037                 priv->xstats.tx_reset_ic_bit++;
2038                 mod_timer(&priv->txtimer,
2039                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
2040         } else
2041                 priv->tx_count_frames = 0;
2042 
2043         /* To avoid raise condition */
2044         priv->hw->desc->set_tx_owner(first);
2045         wmb();
2046 
2047         priv->cur_tx++;
2048 
2049         if (netif_msg_pktdata(priv)) {
2050                 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
2051                         __func__, (priv->cur_tx % txsize),
2052                         (priv->dirty_tx % txsize), entry, first, nfrags);
2053 
2054                 if (priv->extend_desc)
2055                         stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
2056                 else
2057                         stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
2058 
2059                 pr_debug(">>> frame to be transmitted: ");
2060                 print_pkt(skb->data, skb->len);
2061         }
2062         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2063                 if (netif_msg_hw(priv))
2064                         pr_debug("%s: stop transmitted packets\n", __func__);
2065                 netif_stop_queue(dev);
2066         }
2067 
2068         dev->stats.tx_bytes += skb->len;
2069 
2070         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2071                      priv->hwts_tx_en)) {
2072                 /* declare that device is doing timestamping */
2073                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2074                 priv->hw->desc->enable_tx_timestamp(first);
2075         }
2076 
2077         if (!priv->hwts_tx_en)
2078                 skb_tx_timestamp(skb);
2079 
2080         netdev_sent_queue(dev, skb->len);
2081         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
2082 
2083         spin_unlock(&priv->tx_lock);
2084         return NETDEV_TX_OK;
2085 
2086 dma_map_err:
2087         spin_unlock(&priv->tx_lock);
2088         dev_err(priv->device, "Tx dma map failed\n");
2089         dev_kfree_skb(skb);
2090         priv->dev->stats.tx_dropped++;
2091         return NETDEV_TX_OK;
2092 }
2093 
2094 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
2095 {
2096         struct ethhdr *ehdr;
2097         u16 vlanid;
2098 
2099         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
2100             NETIF_F_HW_VLAN_CTAG_RX &&
2101             !__vlan_get_tag(skb, &vlanid)) {
2102                 /* pop the vlan tag */
2103                 ehdr = (struct ethhdr *)skb->data;
2104                 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
2105                 skb_pull(skb, VLAN_HLEN);
2106                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
2107         }
2108 }
2109 
2110 
2111 /**
2112  * stmmac_rx_refill - refill used skb preallocated buffers
2113  * @priv: driver private structure
2114  * Description : this is to reallocate the skb for the reception process
2115  * that is based on zero-copy.
2116  */
2117 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2118 {
2119         unsigned int rxsize = priv->dma_rx_size;
2120         int bfsize = priv->dma_buf_sz;
2121 
2122         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
2123                 unsigned int entry = priv->dirty_rx % rxsize;
2124                 struct dma_desc *p;
2125 
2126                 if (priv->extend_desc)
2127                         p = (struct dma_desc *)(priv->dma_erx + entry);
2128                 else
2129                         p = priv->dma_rx + entry;
2130 
2131                 if (likely(priv->rx_skbuff[entry] == NULL)) {
2132                         struct sk_buff *skb;
2133 
2134                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2135 
2136                         if (unlikely(skb == NULL))
2137                                 break;
2138 
2139                         priv->rx_skbuff[entry] = skb;
2140                         priv->rx_skbuff_dma[entry] =
2141                             dma_map_single(priv->device, skb->data, bfsize,
2142                                            DMA_FROM_DEVICE);
2143                         if (dma_mapping_error(priv->device,
2144                                               priv->rx_skbuff_dma[entry])) {
2145                                 dev_err(priv->device, "Rx dma map failed\n");
2146                                 dev_kfree_skb(skb);
2147                                 break;
2148                         }
2149                         p->des2 = priv->rx_skbuff_dma[entry];
2150 
2151                         priv->hw->mode->refill_desc3(priv, p);
2152 
2153                         if (netif_msg_rx_status(priv))
2154                                 pr_debug("\trefill entry #%d\n", entry);
2155                 }
2156                 wmb();
2157                 priv->hw->desc->set_rx_owner(p);
2158                 wmb();
2159         }
2160 }
2161 
2162 /**
2163  * stmmac_rx - manage the receive process
2164  * @priv: driver private structure
2165  * @limit: napi bugget.
2166  * Description :  this the function called by the napi poll method.
2167  * It gets all the frames inside the ring.
2168  */
2169 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2170 {
2171         unsigned int rxsize = priv->dma_rx_size;
2172         unsigned int entry = priv->cur_rx % rxsize;
2173         unsigned int next_entry;
2174         unsigned int count = 0;
2175         int coe = priv->hw->rx_csum;
2176 
2177         if (netif_msg_rx_status(priv)) {
2178                 pr_debug("%s: descriptor ring:\n", __func__);
2179                 if (priv->extend_desc)
2180                         stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
2181                 else
2182                         stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
2183         }
2184         while (count < limit) {
2185                 int status;
2186                 struct dma_desc *p;
2187 
2188                 if (priv->extend_desc)
2189                         p = (struct dma_desc *)(priv->dma_erx + entry);
2190                 else
2191                         p = priv->dma_rx + entry;
2192 
2193                 if (priv->hw->desc->get_rx_owner(p))
2194                         break;
2195 
2196                 count++;
2197 
2198                 next_entry = (++priv->cur_rx) % rxsize;
2199                 if (priv->extend_desc)
2200                         prefetch(priv->dma_erx + next_entry);
2201                 else
2202                         prefetch(priv->dma_rx + next_entry);
2203 
2204                 /* read the status of the incoming frame */
2205                 status = priv->hw->desc->rx_status(&priv->dev->stats,
2206                                                    &priv->xstats, p);
2207                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2208                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
2209                                                            &priv->xstats,
2210                                                            priv->dma_erx +
2211                                                            entry);
2212                 if (unlikely(status == discard_frame)) {
2213                         priv->dev->stats.rx_errors++;
2214                         if (priv->hwts_rx_en && !priv->extend_desc) {
2215                                 /* DESC2 & DESC3 will be overwitten by device
2216                                  * with timestamp value, hence reinitialize
2217                                  * them in stmmac_rx_refill() function so that
2218                                  * device can reuse it.
2219                                  */
2220                                 priv->rx_skbuff[entry] = NULL;
2221                                 dma_unmap_single(priv->device,
2222                                                  priv->rx_skbuff_dma[entry],
2223                                                  priv->dma_buf_sz,
2224                                                  DMA_FROM_DEVICE);
2225                         }
2226                 } else {
2227                         struct sk_buff *skb;
2228                         int frame_len;
2229 
2230                         frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2231 
2232                         /*  check if frame_len fits the preallocated memory */
2233                         if (frame_len > priv->dma_buf_sz) {
2234                                 priv->dev->stats.rx_length_errors++;
2235                                 break;
2236                         }
2237 
2238                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2239                          * Type frames (LLC/LLC-SNAP)
2240                          */
2241                         if (unlikely(status != llc_snap))
2242                                 frame_len -= ETH_FCS_LEN;
2243 
2244                         if (netif_msg_rx_status(priv)) {
2245                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2246                                          p, entry, p->des2);
2247                                 if (frame_len > ETH_FRAME_LEN)
2248                                         pr_debug("\tframe size %d, COE: %d\n",
2249                                                  frame_len, status);
2250                         }
2251                         skb = priv->rx_skbuff[entry];
2252                         if (unlikely(!skb)) {
2253                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
2254                                        priv->dev->name);
2255                                 priv->dev->stats.rx_dropped++;
2256                                 break;
2257                         }
2258                         prefetch(skb->data - NET_IP_ALIGN);
2259                         priv->rx_skbuff[entry] = NULL;
2260 
2261                         stmmac_get_rx_hwtstamp(priv, entry, skb);
2262 
2263                         skb_put(skb, frame_len);
2264                         dma_unmap_single(priv->device,
2265                                          priv->rx_skbuff_dma[entry],
2266                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
2267 
2268                         if (netif_msg_pktdata(priv)) {
2269                                 pr_debug("frame received (%dbytes)", frame_len);
2270                                 print_pkt(skb->data, frame_len);
2271                         }
2272 
2273                         stmmac_rx_vlan(priv->dev, skb);
2274 
2275                         skb->protocol = eth_type_trans(skb, priv->dev);
2276 
2277                         if (unlikely(!coe))
2278                                 skb_checksum_none_assert(skb);
2279                         else
2280                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2281 
2282                         napi_gro_receive(&priv->napi, skb);
2283 
2284                         priv->dev->stats.rx_packets++;
2285                         priv->dev->stats.rx_bytes += frame_len;
2286                 }
2287                 entry = next_entry;
2288         }
2289 
2290         stmmac_rx_refill(priv);
2291 
2292         priv->xstats.rx_pkt_n += count;
2293 
2294         return count;
2295 }
2296 
2297 /**
2298  *  stmmac_poll - stmmac poll method (NAPI)
2299  *  @napi : pointer to the napi structure.
2300  *  @budget : maximum number of packets that the current CPU can receive from
2301  *            all interfaces.
2302  *  Description :
2303  *  To look at the incoming frames and clear the tx resources.
2304  */
2305 static int stmmac_poll(struct napi_struct *napi, int budget)
2306 {
2307         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2308         int work_done = 0;
2309 
2310         priv->xstats.napi_poll++;
2311         stmmac_tx_clean(priv);
2312 
2313         work_done = stmmac_rx(priv, budget);
2314         if (work_done < budget) {
2315                 napi_complete(napi);
2316                 stmmac_enable_dma_irq(priv);
2317         }
2318         return work_done;
2319 }
2320 
2321 /**
2322  *  stmmac_tx_timeout
2323  *  @dev : Pointer to net device structure
2324  *  Description: this function is called when a packet transmission fails to
2325  *   complete within a reasonable time. The driver will mark the error in the
2326  *   netdev structure and arrange for the device to be reset to a sane state
2327  *   in order to transmit a new packet.
2328  */
2329 static void stmmac_tx_timeout(struct net_device *dev)
2330 {
2331         struct stmmac_priv *priv = netdev_priv(dev);
2332 
2333         /* Clear Tx resources and restart transmitting again */
2334         stmmac_tx_err(priv);
2335 }
2336 
2337 /**
2338  *  stmmac_set_rx_mode - entry point for multicast addressing
2339  *  @dev : pointer to the device structure
2340  *  Description:
2341  *  This function is a driver entry point which gets called by the kernel
2342  *  whenever multicast addresses must be enabled/disabled.
2343  *  Return value:
2344  *  void.
2345  */
2346 static void stmmac_set_rx_mode(struct net_device *dev)
2347 {
2348         struct stmmac_priv *priv = netdev_priv(dev);
2349 
2350         priv->hw->mac->set_filter(priv->hw, dev);
2351 }
2352 
2353 /**
2354  *  stmmac_change_mtu - entry point to change MTU size for the device.
2355  *  @dev : device pointer.
2356  *  @new_mtu : the new MTU size for the device.
2357  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
2358  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
2359  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
2360  *  Return value:
2361  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2362  *  file on failure.
2363  */
2364 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2365 {
2366         struct stmmac_priv *priv = netdev_priv(dev);
2367         int max_mtu;
2368 
2369         if (netif_running(dev)) {
2370                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2371                 return -EBUSY;
2372         }
2373 
2374         if (priv->plat->enh_desc)
2375                 max_mtu = JUMBO_LEN;
2376         else
2377                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2378 
2379         if (priv->plat->maxmtu < max_mtu)
2380                 max_mtu = priv->plat->maxmtu;
2381 
2382         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2383                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2384                 return -EINVAL;
2385         }
2386 
2387         dev->mtu = new_mtu;
2388         netdev_update_features(dev);
2389 
2390         return 0;
2391 }
2392 
2393 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2394                                              netdev_features_t features)
2395 {
2396         struct stmmac_priv *priv = netdev_priv(dev);
2397 
2398         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2399                 features &= ~NETIF_F_RXCSUM;
2400 
2401         if (!priv->plat->tx_coe)
2402                 features &= ~NETIF_F_CSUM_MASK;
2403 
2404         /* Some GMAC devices have a bugged Jumbo frame support that
2405          * needs to have the Tx COE disabled for oversized frames
2406          * (due to limited buffer sizes). In this case we disable
2407          * the TX csum insertionin the TDES and not use SF.
2408          */
2409         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2410                 features &= ~NETIF_F_CSUM_MASK;
2411 
2412         return features;
2413 }
2414 
2415 static int stmmac_set_features(struct net_device *netdev,
2416                                netdev_features_t features)
2417 {
2418         struct stmmac_priv *priv = netdev_priv(netdev);
2419 
2420         /* Keep the COE Type in case of csum is supporting */
2421         if (features & NETIF_F_RXCSUM)
2422                 priv->hw->rx_csum = priv->plat->rx_coe;
2423         else
2424                 priv->hw->rx_csum = 0;
2425         /* No check needed because rx_coe has been set before and it will be
2426          * fixed in case of issue.
2427          */
2428         priv->hw->mac->rx_ipc(priv->hw);
2429 
2430         return 0;
2431 }
2432 
2433 /**
2434  *  stmmac_interrupt - main ISR
2435  *  @irq: interrupt number.
2436  *  @dev_id: to pass the net device pointer.
2437  *  Description: this is the main driver interrupt service routine.
2438  *  It can call:
2439  *  o DMA service routine (to manage incoming frame reception and transmission
2440  *    status)
2441  *  o Core interrupts to manage: remote wake-up, management counter, LPI
2442  *    interrupts.
2443  */
2444 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2445 {
2446         struct net_device *dev = (struct net_device *)dev_id;
2447         struct stmmac_priv *priv = netdev_priv(dev);
2448 
2449         if (priv->irq_wake)
2450                 pm_wakeup_event(priv->device, 0);
2451 
2452         if (unlikely(!dev)) {
2453                 pr_err("%s: invalid dev pointer\n", __func__);
2454                 return IRQ_NONE;
2455         }
2456 
2457         /* To handle GMAC own interrupts */
2458         if (priv->plat->has_gmac) {
2459                 int status = priv->hw->mac->host_irq_status(priv->hw,
2460                                                             &priv->xstats);
2461                 if (unlikely(status)) {
2462                         /* For LPI we need to save the tx status */
2463                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2464                                 priv->tx_path_in_lpi_mode = true;
2465                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2466                                 priv->tx_path_in_lpi_mode = false;
2467                 }
2468         }
2469 
2470         /* To handle DMA interrupts */
2471         stmmac_dma_interrupt(priv);
2472 
2473         return IRQ_HANDLED;
2474 }
2475 
2476 #ifdef CONFIG_NET_POLL_CONTROLLER
2477 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2478  * to allow network I/O with interrupts disabled.
2479  */
2480 static void stmmac_poll_controller(struct net_device *dev)
2481 {
2482         disable_irq(dev->irq);
2483         stmmac_interrupt(dev->irq, dev);
2484         enable_irq(dev->irq);
2485 }
2486 #endif
2487 
2488 /**
2489  *  stmmac_ioctl - Entry point for the Ioctl
2490  *  @dev: Device pointer.
2491  *  @rq: An IOCTL specefic structure, that can contain a pointer to
2492  *  a proprietary structure used to pass information to the driver.
2493  *  @cmd: IOCTL command
2494  *  Description:
2495  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2496  */
2497 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2498 {
2499         struct stmmac_priv *priv = netdev_priv(dev);
2500         int ret = -EOPNOTSUPP;
2501 
2502         if (!netif_running(dev))
2503                 return -EINVAL;
2504 
2505         switch (cmd) {
2506         case SIOCGMIIPHY:
2507         case SIOCGMIIREG:
2508         case SIOCSMIIREG:
2509                 if (!priv->phydev)
2510                         return -EINVAL;
2511                 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2512                 break;
2513         case SIOCSHWTSTAMP:
2514                 ret = stmmac_hwtstamp_ioctl(dev, rq);
2515                 break;
2516         default:
2517                 break;
2518         }
2519 
2520         return ret;
2521 }
2522 
2523 #ifdef CONFIG_DEBUG_FS
2524 static struct dentry *stmmac_fs_dir;
2525 
2526 static void sysfs_display_ring(void *head, int size, int extend_desc,
2527                                struct seq_file *seq)
2528 {
2529         int i;
2530         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2531         struct dma_desc *p = (struct dma_desc *)head;
2532 
2533         for (i = 0; i < size; i++) {
2534                 u64 x;
2535                 if (extend_desc) {
2536                         x = *(u64 *) ep;
2537                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2538                                    i, (unsigned int)virt_to_phys(ep),
2539                                    (unsigned int)x, (unsigned int)(x >> 32),
2540                                    ep->basic.des2, ep->basic.des3);
2541                         ep++;
2542                 } else {
2543                         x = *(u64 *) p;
2544                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2545                                    i, (unsigned int)virt_to_phys(ep),
2546                                    (unsigned int)x, (unsigned int)(x >> 32),
2547                                    p->des2, p->des3);
2548                         p++;
2549                 }
2550                 seq_printf(seq, "\n");
2551         }
2552 }
2553 
2554 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2555 {
2556         struct net_device *dev = seq->private;
2557         struct stmmac_priv *priv = netdev_priv(dev);
2558         unsigned int txsize = priv->dma_tx_size;
2559         unsigned int rxsize = priv->dma_rx_size;
2560 
2561         if (priv->extend_desc) {
2562                 seq_printf(seq, "Extended RX descriptor ring:\n");
2563                 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq);
2564                 seq_printf(seq, "Extended TX descriptor ring:\n");
2565                 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq);
2566         } else {
2567                 seq_printf(seq, "RX descriptor ring:\n");
2568                 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
2569                 seq_printf(seq, "TX descriptor ring:\n");
2570                 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
2571         }
2572 
2573         return 0;
2574 }
2575 
2576 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2577 {
2578         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2579 }
2580 
2581 static const struct file_operations stmmac_rings_status_fops = {
2582         .owner = THIS_MODULE,
2583         .open = stmmac_sysfs_ring_open,
2584         .read = seq_read,
2585         .llseek = seq_lseek,
2586         .release = single_release,
2587 };
2588 
2589 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2590 {
2591         struct net_device *dev = seq->private;
2592         struct stmmac_priv *priv = netdev_priv(dev);
2593 
2594         if (!priv->hw_cap_support) {
2595                 seq_printf(seq, "DMA HW features not supported\n");
2596                 return 0;
2597         }
2598 
2599         seq_printf(seq, "==============================\n");
2600         seq_printf(seq, "\tDMA HW features\n");
2601         seq_printf(seq, "==============================\n");
2602 
2603         seq_printf(seq, "\t10/100 Mbps %s\n",
2604                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2605         seq_printf(seq, "\t1000 Mbps %s\n",
2606                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
2607         seq_printf(seq, "\tHalf duple %s\n",
2608                    (priv->dma_cap.half_duplex) ? "Y" : "N");
2609         seq_printf(seq, "\tHash Filter: %s\n",
2610                    (priv->dma_cap.hash_filter) ? "Y" : "N");
2611         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2612                    (priv->dma_cap.multi_addr) ? "Y" : "N");
2613         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2614                    (priv->dma_cap.pcs) ? "Y" : "N");
2615         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2616                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
2617         seq_printf(seq, "\tPMT Remote wake up: %s\n",
2618                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2619         seq_printf(seq, "\tPMT Magic Frame: %s\n",
2620                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2621         seq_printf(seq, "\tRMON module: %s\n",
2622                    (priv->dma_cap.rmon) ? "Y" : "N");
2623         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2624                    (priv->dma_cap.time_stamp) ? "Y" : "N");
2625         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2626                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
2627         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2628                    (priv->dma_cap.eee) ? "Y" : "N");
2629         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2630         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2631                    (priv->dma_cap.tx_coe) ? "Y" : "N");
2632         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2633                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2634         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2635                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2636         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2637                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2638         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2639                    priv->dma_cap.number_rx_channel);
2640         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2641                    priv->dma_cap.number_tx_channel);
2642         seq_printf(seq, "\tEnhanced descriptors: %s\n",
2643                    (priv->dma_cap.enh_desc) ? "Y" : "N");
2644 
2645         return 0;
2646 }
2647 
2648 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2649 {
2650         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2651 }
2652 
2653 static const struct file_operations stmmac_dma_cap_fops = {
2654         .owner = THIS_MODULE,
2655         .open = stmmac_sysfs_dma_cap_open,
2656         .read = seq_read,
2657         .llseek = seq_lseek,
2658         .release = single_release,
2659 };
2660 
2661 static int stmmac_init_fs(struct net_device *dev)
2662 {
2663         struct stmmac_priv *priv = netdev_priv(dev);
2664 
2665         /* Create per netdev entries */
2666         priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
2667 
2668         if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
2669                 pr_err("ERROR %s/%s, debugfs create directory failed\n",
2670                        STMMAC_RESOURCE_NAME, dev->name);
2671 
2672                 return -ENOMEM;
2673         }
2674 
2675         /* Entry to report DMA RX/TX rings */
2676         priv->dbgfs_rings_status =
2677                 debugfs_create_file("descriptors_status", S_IRUGO,
2678                                     priv->dbgfs_dir, dev,
2679                                     &stmmac_rings_status_fops);
2680 
2681         if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
2682                 pr_info("ERROR creating stmmac ring debugfs file\n");
2683                 debugfs_remove_recursive(priv->dbgfs_dir);
2684 
2685                 return -ENOMEM;
2686         }
2687 
2688         /* Entry to report the DMA HW features */
2689         priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO,
2690                                             priv->dbgfs_dir,
2691                                             dev, &stmmac_dma_cap_fops);
2692 
2693         if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
2694                 pr_info("ERROR creating stmmac MMC debugfs file\n");
2695                 debugfs_remove_recursive(priv->dbgfs_dir);
2696 
2697                 return -ENOMEM;
2698         }
2699 
2700         return 0;
2701 }
2702 
2703 static void stmmac_exit_fs(struct net_device *dev)
2704 {
2705         struct stmmac_priv *priv = netdev_priv(dev);
2706 
2707         debugfs_remove_recursive(priv->dbgfs_dir);
2708 }
2709 #endif /* CONFIG_DEBUG_FS */
2710 
2711 static const struct net_device_ops stmmac_netdev_ops = {
2712         .ndo_open = stmmac_open,
2713         .ndo_start_xmit = stmmac_xmit,
2714         .ndo_stop = stmmac_release,
2715         .ndo_change_mtu = stmmac_change_mtu,
2716         .ndo_fix_features = stmmac_fix_features,
2717         .ndo_set_features = stmmac_set_features,
2718         .ndo_set_rx_mode = stmmac_set_rx_mode,
2719         .ndo_tx_timeout = stmmac_tx_timeout,
2720         .ndo_do_ioctl = stmmac_ioctl,
2721 #ifdef CONFIG_NET_POLL_CONTROLLER
2722         .ndo_poll_controller = stmmac_poll_controller,
2723 #endif
2724         .ndo_set_mac_address = eth_mac_addr,
2725 };
2726 
2727 /**
2728  *  stmmac_hw_init - Init the MAC device
2729  *  @priv: driver private structure
2730  *  Description: this function is to configure the MAC device according to
2731  *  some platform parameters or the HW capability register. It prepares the
2732  *  driver to use either ring or chain modes and to setup either enhanced or
2733  *  normal descriptors.
2734  */
2735 static int stmmac_hw_init(struct stmmac_priv *priv)
2736 {
2737         struct mac_device_info *mac;
2738 
2739         /* Identify the MAC HW device */
2740         if (priv->plat->has_gmac) {
2741                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2742                 mac = dwmac1000_setup(priv->ioaddr,
2743                                       priv->plat->multicast_filter_bins,
2744                                       priv->plat->unicast_filter_entries);
2745         } else {
2746                 mac = dwmac100_setup(priv->ioaddr);
2747         }
2748         if (!mac)
2749                 return -ENOMEM;
2750 
2751         priv->hw = mac;
2752 
2753         /* Get and dump the chip ID */
2754         priv->synopsys_id = stmmac_get_synopsys_id(priv);
2755 
2756         /* To use the chained or ring mode */
2757         if (chain_mode) {
2758                 priv->hw->mode = &chain_mode_ops;
2759                 pr_info(" Chain mode enabled\n");
2760                 priv->mode = STMMAC_CHAIN_MODE;
2761         } else {
2762                 priv->hw->mode = &ring_mode_ops;
2763                 pr_info(" Ring mode enabled\n");
2764                 priv->mode = STMMAC_RING_MODE;
2765         }
2766 
2767         /* Get the HW capability (new GMAC newer than 3.50a) */
2768         priv->hw_cap_support = stmmac_get_hw_features(priv);
2769         if (priv->hw_cap_support) {
2770                 pr_info(" DMA HW capability register supported");
2771 
2772                 /* We can override some gmac/dma configuration fields: e.g.
2773                  * enh_desc, tx_coe (e.g. that are passed through the
2774                  * platform) with the values from the HW capability
2775                  * register (if supported).
2776                  */
2777                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2778                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2779 
2780                 /* TXCOE doesn't work in thresh DMA mode */
2781                 if (priv->plat->force_thresh_dma_mode)
2782                         priv->plat->tx_coe = 0;
2783                 else
2784                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
2785 
2786                 if (priv->dma_cap.rx_coe_type2)
2787                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2788                 else if (priv->dma_cap.rx_coe_type1)
2789                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2790 
2791         } else
2792                 pr_info(" No HW DMA feature register supported");
2793 
2794         /* To use alternate (extended) or normal descriptor structures */
2795         stmmac_selec_desc_mode(priv);
2796 
2797         if (priv->plat->rx_coe) {
2798                 priv->hw->rx_csum = priv->plat->rx_coe;
2799                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2800                         priv->plat->rx_coe);
2801         }
2802         if (priv->plat->tx_coe)
2803                 pr_info(" TX Checksum insertion supported\n");
2804 
2805         if (priv->plat->pmt) {
2806                 pr_info(" Wake-Up On Lan supported\n");
2807                 device_set_wakeup_capable(priv->device, 1);
2808         }
2809 
2810         return 0;
2811 }
2812 
2813 /**
2814  * stmmac_dvr_probe
2815  * @device: device pointer
2816  * @plat_dat: platform data pointer
2817  * @res: stmmac resource pointer
2818  * Description: this is the main probe function used to
2819  * call the alloc_etherdev, allocate the priv structure.
2820  * Return:
2821  * returns 0 on success, otherwise errno.
2822  */
2823 int stmmac_dvr_probe(struct device *device,
2824                      struct plat_stmmacenet_data *plat_dat,
2825                      struct stmmac_resources *res)
2826 {
2827         int ret = 0;
2828         struct net_device *ndev = NULL;
2829         struct stmmac_priv *priv;
2830 
2831         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2832         if (!ndev)
2833                 return -ENOMEM;
2834 
2835         SET_NETDEV_DEV(ndev, device);
2836 
2837         priv = netdev_priv(ndev);
2838         priv->device = device;
2839         priv->dev = ndev;
2840 
2841         stmmac_set_ethtool_ops(ndev);
2842         priv->pause = pause;
2843         priv->plat = plat_dat;
2844         priv->ioaddr = res->addr;
2845         priv->dev->base_addr = (unsigned long)res->addr;
2846 
2847         priv->dev->irq = res->irq;
2848         priv->wol_irq = res->wol_irq;
2849         priv->lpi_irq = res->lpi_irq;
2850 
2851         if (res->mac)
2852                 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
2853 
2854         dev_set_drvdata(device, priv->dev);
2855 
2856         /* Verify driver arguments */
2857         stmmac_verify_args();
2858 
2859         /* Override with kernel parameters if supplied XXX CRS XXX
2860          * this needs to have multiple instances
2861          */
2862         if ((phyaddr >= 0) && (phyaddr <= 31))
2863                 priv->plat->phy_addr = phyaddr;
2864 
2865         priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
2866         if (IS_ERR(priv->stmmac_clk)) {
2867                 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
2868                          __func__);
2869                 /* If failed to obtain stmmac_clk and specific clk_csr value
2870                  * is NOT passed from the platform, probe fail.
2871                  */
2872                 if (!priv->plat->clk_csr) {
2873                         ret = PTR_ERR(priv->stmmac_clk);
2874                         goto error_clk_get;
2875                 } else {
2876                         priv->stmmac_clk = NULL;
2877                 }
2878         }
2879         clk_prepare_enable(priv->stmmac_clk);
2880 
2881         priv->pclk = devm_clk_get(priv->device, "pclk");
2882         if (IS_ERR(priv->pclk)) {
2883                 if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) {
2884                         ret = -EPROBE_DEFER;
2885                         goto error_pclk_get;
2886                 }
2887                 priv->pclk = NULL;
2888         }
2889         clk_prepare_enable(priv->pclk);
2890 
2891         priv->stmmac_rst = devm_reset_control_get(priv->device,
2892                                                   STMMAC_RESOURCE_NAME);
2893         if (IS_ERR(priv->stmmac_rst)) {
2894                 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
2895                         ret = -EPROBE_DEFER;
2896                         goto error_hw_init;
2897                 }
2898                 dev_info(priv->device, "no reset control found\n");
2899                 priv->stmmac_rst = NULL;
2900         }
2901         if (priv->stmmac_rst)
2902                 reset_control_deassert(priv->stmmac_rst);
2903 
2904         /* Init MAC and get the capabilities */
2905         ret = stmmac_hw_init(priv);
2906         if (ret)
2907                 goto error_hw_init;
2908 
2909         ndev->netdev_ops = &stmmac_netdev_ops;
2910 
2911         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2912                             NETIF_F_RXCSUM;
2913         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2914         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2915 #ifdef STMMAC_VLAN_TAG_USED
2916         /* Both mac100 and gmac support receive VLAN tag detection */
2917         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2918 #endif
2919         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2920 
2921         if (flow_ctrl)
2922                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
2923 
2924         /* Rx Watchdog is available in the COREs newer than the 3.40.
2925          * In some case, for example on bugged HW this feature
2926          * has to be disable and this can be done by passing the
2927          * riwt_off field from the platform.
2928          */
2929         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2930                 priv->use_riwt = 1;
2931                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2932         }
2933 
2934         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2935 
2936         spin_lock_init(&priv->lock);
2937         spin_lock_init(&priv->tx_lock);
2938 
2939         ret = register_netdev(ndev);
2940         if (ret) {
2941                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2942                 goto error_netdev_register;
2943         }
2944 
2945         /* If a specific clk_csr value is passed from the platform
2946          * this means that the CSR Clock Range selection cannot be
2947          * changed at run-time and it is fixed. Viceversa the driver'll try to
2948          * set the MDC clock dynamically according to the csr actual
2949          * clock input.
2950          */
2951         if (!priv->plat->clk_csr)
2952                 stmmac_clk_csr_set(priv);
2953         else
2954                 priv->clk_csr = priv->plat->clk_csr;
2955 
2956         stmmac_check_pcs_mode(priv);
2957 
2958         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2959             priv->pcs != STMMAC_PCS_RTBI) {
2960                 /* MDIO bus Registration */
2961                 ret = stmmac_mdio_register(ndev);
2962                 if (ret < 0) {
2963                         pr_debug("%s: MDIO bus (id: %d) registration failed",
2964                                  __func__, priv->plat->bus_id);
2965                         goto error_mdio_register;
2966                 }
2967         }
2968 
2969         return 0;
2970 
2971 error_mdio_register:
2972         unregister_netdev(ndev);
2973 error_netdev_register:
2974         netif_napi_del(&priv->napi);
2975 error_hw_init:
2976         clk_disable_unprepare(priv->pclk);
2977 error_pclk_get:
2978         clk_disable_unprepare(priv->stmmac_clk);
2979 error_clk_get:
2980         free_netdev(ndev);
2981 
2982         return ret;
2983 }
2984 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
2985 
2986 /**
2987  * stmmac_dvr_remove
2988  * @ndev: net device pointer
2989  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2990  * changes the link status, releases the DMA descriptor rings.
2991  */
2992 int stmmac_dvr_remove(struct net_device *ndev)
2993 {
2994         struct stmmac_priv *priv = netdev_priv(ndev);
2995 
2996         pr_info("%s:\n\tremoving driver", __func__);
2997 
2998         priv->hw->dma->stop_rx(priv->ioaddr);
2999         priv->hw->dma->stop_tx(priv->ioaddr);
3000 
3001         stmmac_set_mac(priv->ioaddr, false);
3002         netif_carrier_off(ndev);
3003         unregister_netdev(ndev);
3004         if (priv->stmmac_rst)
3005                 reset_control_assert(priv->stmmac_rst);
3006         clk_disable_unprepare(priv->pclk);
3007         clk_disable_unprepare(priv->stmmac_clk);
3008         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
3009             priv->pcs != STMMAC_PCS_RTBI)
3010                 stmmac_mdio_unregister(ndev);
3011         free_netdev(ndev);
3012 
3013         return 0;
3014 }
3015 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
3016 
3017 /**
3018  * stmmac_suspend - suspend callback
3019  * @ndev: net device pointer
3020  * Description: this is the function to suspend the device and it is called
3021  * by the platform driver to stop the network queue, release the resources,
3022  * program the PMT register (for WoL), clean and release driver resources.
3023  */
3024 int stmmac_suspend(struct net_device *ndev)
3025 {
3026         struct stmmac_priv *priv = netdev_priv(ndev);
3027         unsigned long flags;
3028 
3029         if (!ndev || !netif_running(ndev))
3030                 return 0;
3031 
3032         if (priv->phydev)
3033                 phy_stop(priv->phydev);
3034 
3035         spin_lock_irqsave(&priv->lock, flags);
3036 
3037         netif_device_detach(ndev);
3038         netif_stop_queue(ndev);
3039 
3040         napi_disable(&priv->napi);
3041 
3042         /* Stop TX/RX DMA */
3043         priv->hw->dma->stop_tx(priv->ioaddr);
3044         priv->hw->dma->stop_rx(priv->ioaddr);
3045 
3046         /* Enable Power down mode by programming the PMT regs */
3047         if (device_may_wakeup(priv->device)) {
3048                 priv->hw->mac->pmt(priv->hw, priv->wolopts);
3049                 priv->irq_wake = 1;
3050         } else {
3051                 stmmac_set_mac(priv->ioaddr, false);
3052                 pinctrl_pm_select_sleep_state(priv->device);
3053                 /* Disable clock in case of PWM is off */
3054                 clk_disable(priv->pclk);
3055                 clk_disable(priv->stmmac_clk);
3056         }
3057         spin_unlock_irqrestore(&priv->lock, flags);
3058 
3059         priv->oldlink = 0;
3060         priv->speed = 0;
3061         priv->oldduplex = -1;
3062         return 0;
3063 }
3064 EXPORT_SYMBOL_GPL(stmmac_suspend);
3065 
3066 /**
3067  * stmmac_resume - resume callback
3068  * @ndev: net device pointer
3069  * Description: when resume this function is invoked to setup the DMA and CORE
3070  * in a usable state.
3071  */
3072 int stmmac_resume(struct net_device *ndev)
3073 {
3074         struct stmmac_priv *priv = netdev_priv(ndev);
3075         unsigned long flags;
3076 
3077         if (!netif_running(ndev))
3078                 return 0;
3079 
3080         spin_lock_irqsave(&priv->lock, flags);
3081 
3082         /* Power Down bit, into the PM register, is cleared
3083          * automatically as soon as a magic packet or a Wake-up frame
3084          * is received. Anyway, it's better to manually clear
3085          * this bit because it can generate problems while resuming
3086          * from another devices (e.g. serial console).
3087          */
3088         if (device_may_wakeup(priv->device)) {
3089                 priv->hw->mac->pmt(priv->hw, 0);
3090                 priv->irq_wake = 0;
3091         } else {
3092                 pinctrl_pm_select_default_state(priv->device);
3093                 /* enable the clk prevously disabled */
3094                 clk_enable(priv->stmmac_clk);
3095                 clk_enable(priv->pclk);
3096                 /* reset the phy so that it's ready */
3097                 if (priv->mii)
3098                         stmmac_mdio_reset(priv->mii);
3099         }
3100 
3101         netif_device_attach(ndev);
3102 
3103         priv->cur_rx = 0;
3104         priv->dirty_rx = 0;
3105         priv->dirty_tx = 0;
3106         priv->cur_tx = 0;
3107         stmmac_clear_descriptors(priv);
3108 
3109         stmmac_hw_setup(ndev, false);
3110         stmmac_init_tx_coalesce(priv);
3111         stmmac_set_rx_mode(ndev);
3112 
3113         napi_enable(&priv->napi);
3114 
3115         netif_start_queue(ndev);
3116 
3117         spin_unlock_irqrestore(&priv->lock, flags);
3118 
3119         if (priv->phydev)
3120                 phy_start(priv->phydev);
3121 
3122         return 0;
3123 }
3124 EXPORT_SYMBOL_GPL(stmmac_resume);
3125 
3126 #ifndef MODULE
3127 static int __init stmmac_cmdline_opt(char *str)
3128 {
3129         char *opt;
3130 
3131         if (!str || !*str)
3132                 return -EINVAL;
3133         while ((opt = strsep(&str, ",")) != NULL) {
3134                 if (!strncmp(opt, "debug:", 6)) {
3135                         if (kstrtoint(opt + 6, 0, &debug))
3136                                 goto err;
3137                 } else if (!strncmp(opt, "phyaddr:", 8)) {
3138                         if (kstrtoint(opt + 8, 0, &phyaddr))
3139                                 goto err;
3140                 } else if (!strncmp(opt, "dma_txsize:", 11)) {
3141                         if (kstrtoint(opt + 11, 0, &dma_txsize))
3142                                 goto err;
3143                 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
3144                         if (kstrtoint(opt + 11, 0, &dma_rxsize))
3145                                 goto err;
3146                 } else if (!strncmp(opt, "buf_sz:", 7)) {
3147                         if (kstrtoint(opt + 7, 0, &buf_sz))
3148                                 goto err;
3149                 } else if (!strncmp(opt, "tc:", 3)) {
3150                         if (kstrtoint(opt + 3, 0, &tc))
3151                                 goto err;
3152                 } else if (!strncmp(opt, "watchdog:", 9)) {
3153                         if (kstrtoint(opt + 9, 0, &watchdog))
3154                                 goto err;
3155                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
3156                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
3157                                 goto err;
3158                 } else if (!strncmp(opt, "pause:", 6)) {
3159                         if (kstrtoint(opt + 6, 0, &pause))
3160                                 goto err;
3161                 } else if (!strncmp(opt, "eee_timer:", 10)) {
3162                         if (kstrtoint(opt + 10, 0, &eee_timer))
3163                                 goto err;
3164                 } else if (!strncmp(opt, "chain_mode:", 11)) {
3165                         if (kstrtoint(opt + 11, 0, &chain_mode))
3166                                 goto err;
3167                 }
3168         }
3169         return 0;
3170 
3171 err:
3172         pr_err("%s: ERROR broken module parameter conversion", __func__);
3173         return -EINVAL;
3174 }
3175 
3176 __setup("stmmaceth=", stmmac_cmdline_opt);
3177 #endif /* MODULE */
3178 
3179 static int __init stmmac_init(void)
3180 {
3181 #ifdef CONFIG_DEBUG_FS
3182         /* Create debugfs main directory if it doesn't exist yet */
3183         if (!stmmac_fs_dir) {
3184                 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
3185 
3186                 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
3187                         pr_err("ERROR %s, debugfs create directory failed\n",
3188                                STMMAC_RESOURCE_NAME);
3189 
3190                         return -ENOMEM;
3191                 }
3192         }
3193 #endif
3194 
3195         return 0;
3196 }
3197 
3198 static void __exit stmmac_exit(void)
3199 {
3200 #ifdef CONFIG_DEBUG_FS
3201         debugfs_remove_recursive(stmmac_fs_dir);
3202 #endif
3203 }
3204 
3205 module_init(stmmac_init)
3206 module_exit(stmmac_exit)
3207 
3208 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3209 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3210 MODULE_LICENSE("GPL");
3211 

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