Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

  1 /*******************************************************************************
  2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
  3   ST Ethernet IPs are built around a Synopsys IP Core.
  4 
  5         Copyright(C) 2007-2011 STMicroelectronics Ltd
  6 
  7   This program is free software; you can redistribute it and/or modify it
  8   under the terms and conditions of the GNU General Public License,
  9   version 2, as published by the Free Software Foundation.
 10 
 11   This program is distributed in the hope it will be useful, but WITHOUT
 12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 14   more details.
 15 
 16   You should have received a copy of the GNU General Public License along with
 17   this program; if not, write to the Free Software Foundation, Inc.,
 18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 19 
 20   The full GNU General Public License is included in this distribution in
 21   the file called "COPYING".
 22 
 23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
 24 
 25   Documentation available at:
 26         http://www.stlinux.com
 27   Support available at:
 28         https://bugzilla.stlinux.com/
 29 *******************************************************************************/
 30 
 31 #include <linux/clk.h>
 32 #include <linux/kernel.h>
 33 #include <linux/interrupt.h>
 34 #include <linux/ip.h>
 35 #include <linux/tcp.h>
 36 #include <linux/skbuff.h>
 37 #include <linux/ethtool.h>
 38 #include <linux/if_ether.h>
 39 #include <linux/crc32.h>
 40 #include <linux/mii.h>
 41 #include <linux/if.h>
 42 #include <linux/if_vlan.h>
 43 #include <linux/dma-mapping.h>
 44 #include <linux/slab.h>
 45 #include <linux/prefetch.h>
 46 #include <linux/pinctrl/consumer.h>
 47 #ifdef CONFIG_STMMAC_DEBUG_FS
 48 #include <linux/debugfs.h>
 49 #include <linux/seq_file.h>
 50 #endif /* CONFIG_STMMAC_DEBUG_FS */
 51 #include <linux/net_tstamp.h>
 52 #include "stmmac_ptp.h"
 53 #include "stmmac.h"
 54 #include <linux/reset.h>
 55 
 56 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
 57 
 58 /* Module parameters */
 59 #define TX_TIMEO        5000
 60 static int watchdog = TX_TIMEO;
 61 module_param(watchdog, int, S_IRUGO | S_IWUSR);
 62 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
 63 
 64 static int debug = -1;
 65 module_param(debug, int, S_IRUGO | S_IWUSR);
 66 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
 67 
 68 static int phyaddr = -1;
 69 module_param(phyaddr, int, S_IRUGO);
 70 MODULE_PARM_DESC(phyaddr, "Physical device address");
 71 
 72 #define DMA_TX_SIZE 256
 73 static int dma_txsize = DMA_TX_SIZE;
 74 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
 75 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
 76 
 77 #define DMA_RX_SIZE 256
 78 static int dma_rxsize = DMA_RX_SIZE;
 79 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
 80 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
 81 
 82 static int flow_ctrl = FLOW_OFF;
 83 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
 84 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
 85 
 86 static int pause = PAUSE_TIME;
 87 module_param(pause, int, S_IRUGO | S_IWUSR);
 88 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
 89 
 90 #define TC_DEFAULT 64
 91 static int tc = TC_DEFAULT;
 92 module_param(tc, int, S_IRUGO | S_IWUSR);
 93 MODULE_PARM_DESC(tc, "DMA threshold control value");
 94 
 95 #define DEFAULT_BUFSIZE 1536
 96 static int buf_sz = DEFAULT_BUFSIZE;
 97 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
 98 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
 99 
100 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
101                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
102                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
103 
104 #define STMMAC_DEFAULT_LPI_TIMER        1000
105 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
106 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
107 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
108 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
109 
110 /* By default the driver will use the ring mode to manage tx and rx descriptors
111  * but passing this value so user can force to use the chain instead of the ring
112  */
113 static unsigned int chain_mode;
114 module_param(chain_mode, int, S_IRUGO);
115 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
116 
117 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
118 
119 #ifdef CONFIG_STMMAC_DEBUG_FS
120 static int stmmac_init_fs(struct net_device *dev);
121 static void stmmac_exit_fs(void);
122 #endif
123 
124 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
125 
126 /**
127  * stmmac_verify_args - verify the driver parameters.
128  * Description: it verifies if some wrong parameter is passed to the driver.
129  * Note that wrong parameters are replaced with the default values.
130  */
131 static void stmmac_verify_args(void)
132 {
133         if (unlikely(watchdog < 0))
134                 watchdog = TX_TIMEO;
135         if (unlikely(dma_rxsize < 0))
136                 dma_rxsize = DMA_RX_SIZE;
137         if (unlikely(dma_txsize < 0))
138                 dma_txsize = DMA_TX_SIZE;
139         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
140                 buf_sz = DEFAULT_BUFSIZE;
141         if (unlikely(flow_ctrl > 1))
142                 flow_ctrl = FLOW_AUTO;
143         else if (likely(flow_ctrl < 0))
144                 flow_ctrl = FLOW_OFF;
145         if (unlikely((pause < 0) || (pause > 0xffff)))
146                 pause = PAUSE_TIME;
147         if (eee_timer < 0)
148                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
149 }
150 
151 /**
152  * stmmac_clk_csr_set - dynamically set the MDC clock
153  * @priv: driver private structure
154  * Description: this is to dynamically set the MDC clock according to the csr
155  * clock input.
156  * Note:
157  *      If a specific clk_csr value is passed from the platform
158  *      this means that the CSR Clock Range selection cannot be
159  *      changed at run-time and it is fixed (as reported in the driver
160  *      documentation). Viceversa the driver will try to set the MDC
161  *      clock dynamically according to the actual clock input.
162  */
163 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
164 {
165         u32 clk_rate;
166 
167         clk_rate = clk_get_rate(priv->stmmac_clk);
168 
169         /* Platform provided default clk_csr would be assumed valid
170          * for all other cases except for the below mentioned ones.
171          * For values higher than the IEEE 802.3 specified frequency
172          * we can not estimate the proper divider as it is not known
173          * the frequency of clk_csr_i. So we do not change the default
174          * divider.
175          */
176         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
177                 if (clk_rate < CSR_F_35M)
178                         priv->clk_csr = STMMAC_CSR_20_35M;
179                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
180                         priv->clk_csr = STMMAC_CSR_35_60M;
181                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
182                         priv->clk_csr = STMMAC_CSR_60_100M;
183                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
184                         priv->clk_csr = STMMAC_CSR_100_150M;
185                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
186                         priv->clk_csr = STMMAC_CSR_150_250M;
187                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
188                         priv->clk_csr = STMMAC_CSR_250_300M;
189         }
190 }
191 
192 static void print_pkt(unsigned char *buf, int len)
193 {
194         int j;
195         pr_debug("len = %d byte, buf addr: 0x%p", len, buf);
196         for (j = 0; j < len; j++) {
197                 if ((j % 16) == 0)
198                         pr_debug("\n %03x:", j);
199                 pr_debug(" %02x", buf[j]);
200         }
201         pr_debug("\n");
202 }
203 
204 /* minimum number of free TX descriptors required to wake up TX process */
205 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
206 
207 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
208 {
209         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
210 }
211 
212 /**
213  * stmmac_hw_fix_mac_speed: callback for speed selection
214  * @priv: driver private structure
215  * Description: on some platforms (e.g. ST), some HW system configuraton
216  * registers have to be set according to the link speed negotiated.
217  */
218 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
219 {
220         struct phy_device *phydev = priv->phydev;
221 
222         if (likely(priv->plat->fix_mac_speed))
223                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
224 }
225 
226 /**
227  * stmmac_enable_eee_mode: Check and enter in LPI mode
228  * @priv: driver private structure
229  * Description: this function is to verify and enter in LPI mode for EEE.
230  */
231 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
232 {
233         /* Check and enter in LPI mode */
234         if ((priv->dirty_tx == priv->cur_tx) &&
235             (priv->tx_path_in_lpi_mode == false))
236                 priv->hw->mac->set_eee_mode(priv->hw);
237 }
238 
239 /**
240  * stmmac_disable_eee_mode: disable/exit from EEE
241  * @priv: driver private structure
242  * Description: this function is to exit and disable EEE in case of
243  * LPI state is true. This is called by the xmit.
244  */
245 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
246 {
247         priv->hw->mac->reset_eee_mode(priv->hw);
248         del_timer_sync(&priv->eee_ctrl_timer);
249         priv->tx_path_in_lpi_mode = false;
250 }
251 
252 /**
253  * stmmac_eee_ctrl_timer: EEE TX SW timer.
254  * @arg : data hook
255  * Description:
256  *  if there is no data transfer and if we are not in LPI state,
257  *  then MAC Transmitter can be moved to LPI state.
258  */
259 static void stmmac_eee_ctrl_timer(unsigned long arg)
260 {
261         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
262 
263         stmmac_enable_eee_mode(priv);
264         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
265 }
266 
267 /**
268  * stmmac_eee_init: init EEE
269  * @priv: driver private structure
270  * Description:
271  *  If the EEE support has been enabled while configuring the driver,
272  *  if the GMAC actually supports the EEE (from the HW cap reg) and the
273  *  phy can also manage EEE, so enable the LPI state and start the timer
274  *  to verify if the tx path can enter in LPI state.
275  */
276 bool stmmac_eee_init(struct stmmac_priv *priv)
277 {
278         char *phy_bus_name = priv->plat->phy_bus_name;
279         unsigned long flags;
280         bool ret = false;
281 
282         /* Using PCS we cannot dial with the phy registers at this stage
283          * so we do not support extra feature like EEE.
284          */
285         if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
286             (priv->pcs == STMMAC_PCS_RTBI))
287                 goto out;
288 
289         /* Never init EEE in case of a switch is attached */
290         if (phy_bus_name && (!strcmp(phy_bus_name, "fixed")))
291                 goto out;
292 
293         /* MAC core supports the EEE feature. */
294         if (priv->dma_cap.eee) {
295                 int tx_lpi_timer = priv->tx_lpi_timer;
296 
297                 /* Check if the PHY supports EEE */
298                 if (phy_init_eee(priv->phydev, 1)) {
299                         /* To manage at run-time if the EEE cannot be supported
300                          * anymore (for example because the lp caps have been
301                          * changed).
302                          * In that case the driver disable own timers.
303                          */
304                         spin_lock_irqsave(&priv->lock, flags);
305                         if (priv->eee_active) {
306                                 pr_debug("stmmac: disable EEE\n");
307                                 del_timer_sync(&priv->eee_ctrl_timer);
308                                 priv->hw->mac->set_eee_timer(priv->hw, 0,
309                                                              tx_lpi_timer);
310                         }
311                         priv->eee_active = 0;
312                         spin_unlock_irqrestore(&priv->lock, flags);
313                         goto out;
314                 }
315                 /* Activate the EEE and start timers */
316                 spin_lock_irqsave(&priv->lock, flags);
317                 if (!priv->eee_active) {
318                         priv->eee_active = 1;
319                         init_timer(&priv->eee_ctrl_timer);
320                         priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
321                         priv->eee_ctrl_timer.data = (unsigned long)priv;
322                         priv->eee_ctrl_timer.expires = STMMAC_LPI_T(eee_timer);
323                         add_timer(&priv->eee_ctrl_timer);
324 
325                         priv->hw->mac->set_eee_timer(priv->hw,
326                                                      STMMAC_DEFAULT_LIT_LS,
327                                                      tx_lpi_timer);
328                 }
329                 /* Set HW EEE according to the speed */
330                 priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link);
331 
332                 ret = true;
333                 spin_unlock_irqrestore(&priv->lock, flags);
334 
335                 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
336         }
337 out:
338         return ret;
339 }
340 
341 /* stmmac_get_tx_hwtstamp: get HW TX timestamps
342  * @priv: driver private structure
343  * @entry : descriptor index to be used.
344  * @skb : the socket buffer
345  * Description :
346  * This function will read timestamp from the descriptor & pass it to stack.
347  * and also perform some sanity checks.
348  */
349 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
350                                    unsigned int entry, struct sk_buff *skb)
351 {
352         struct skb_shared_hwtstamps shhwtstamp;
353         u64 ns;
354         void *desc = NULL;
355 
356         if (!priv->hwts_tx_en)
357                 return;
358 
359         /* exit if skb doesn't support hw tstamp */
360         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
361                 return;
362 
363         if (priv->adv_ts)
364                 desc = (priv->dma_etx + entry);
365         else
366                 desc = (priv->dma_tx + entry);
367 
368         /* check tx tstamp status */
369         if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
370                 return;
371 
372         /* get the valid tstamp */
373         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
374 
375         memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
376         shhwtstamp.hwtstamp = ns_to_ktime(ns);
377         /* pass tstamp to stack */
378         skb_tstamp_tx(skb, &shhwtstamp);
379 
380         return;
381 }
382 
383 /* stmmac_get_rx_hwtstamp: get HW RX timestamps
384  * @priv: driver private structure
385  * @entry : descriptor index to be used.
386  * @skb : the socket buffer
387  * Description :
388  * This function will read received packet's timestamp from the descriptor
389  * and pass it to stack. It also perform some sanity checks.
390  */
391 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
392                                    unsigned int entry, struct sk_buff *skb)
393 {
394         struct skb_shared_hwtstamps *shhwtstamp = NULL;
395         u64 ns;
396         void *desc = NULL;
397 
398         if (!priv->hwts_rx_en)
399                 return;
400 
401         if (priv->adv_ts)
402                 desc = (priv->dma_erx + entry);
403         else
404                 desc = (priv->dma_rx + entry);
405 
406         /* exit if rx tstamp is not valid */
407         if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
408                 return;
409 
410         /* get valid tstamp */
411         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
412         shhwtstamp = skb_hwtstamps(skb);
413         memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
414         shhwtstamp->hwtstamp = ns_to_ktime(ns);
415 }
416 
417 /**
418  *  stmmac_hwtstamp_ioctl - control hardware timestamping.
419  *  @dev: device pointer.
420  *  @ifr: An IOCTL specefic structure, that can contain a pointer to
421  *  a proprietary structure used to pass information to the driver.
422  *  Description:
423  *  This function configures the MAC to enable/disable both outgoing(TX)
424  *  and incoming(RX) packets time stamping based on user input.
425  *  Return Value:
426  *  0 on success and an appropriate -ve integer on failure.
427  */
428 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
429 {
430         struct stmmac_priv *priv = netdev_priv(dev);
431         struct hwtstamp_config config;
432         struct timespec now;
433         u64 temp = 0;
434         u32 ptp_v2 = 0;
435         u32 tstamp_all = 0;
436         u32 ptp_over_ipv4_udp = 0;
437         u32 ptp_over_ipv6_udp = 0;
438         u32 ptp_over_ethernet = 0;
439         u32 snap_type_sel = 0;
440         u32 ts_master_en = 0;
441         u32 ts_event_en = 0;
442         u32 value = 0;
443 
444         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
445                 netdev_alert(priv->dev, "No support for HW time stamping\n");
446                 priv->hwts_tx_en = 0;
447                 priv->hwts_rx_en = 0;
448 
449                 return -EOPNOTSUPP;
450         }
451 
452         if (copy_from_user(&config, ifr->ifr_data,
453                            sizeof(struct hwtstamp_config)))
454                 return -EFAULT;
455 
456         pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
457                  __func__, config.flags, config.tx_type, config.rx_filter);
458 
459         /* reserved for future extensions */
460         if (config.flags)
461                 return -EINVAL;
462 
463         if (config.tx_type != HWTSTAMP_TX_OFF &&
464             config.tx_type != HWTSTAMP_TX_ON)
465                 return -ERANGE;
466 
467         if (priv->adv_ts) {
468                 switch (config.rx_filter) {
469                 case HWTSTAMP_FILTER_NONE:
470                         /* time stamp no incoming packet at all */
471                         config.rx_filter = HWTSTAMP_FILTER_NONE;
472                         break;
473 
474                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
475                         /* PTP v1, UDP, any kind of event packet */
476                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
477                         /* take time stamp for all event messages */
478                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
479 
480                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
481                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
482                         break;
483 
484                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
485                         /* PTP v1, UDP, Sync packet */
486                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
487                         /* take time stamp for SYNC messages only */
488                         ts_event_en = PTP_TCR_TSEVNTENA;
489 
490                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
491                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
492                         break;
493 
494                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
495                         /* PTP v1, UDP, Delay_req packet */
496                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
497                         /* take time stamp for Delay_Req messages only */
498                         ts_master_en = PTP_TCR_TSMSTRENA;
499                         ts_event_en = PTP_TCR_TSEVNTENA;
500 
501                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
502                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
503                         break;
504 
505                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
506                         /* PTP v2, UDP, any kind of event packet */
507                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
508                         ptp_v2 = PTP_TCR_TSVER2ENA;
509                         /* take time stamp for all event messages */
510                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
511 
512                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
513                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
514                         break;
515 
516                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
517                         /* PTP v2, UDP, Sync packet */
518                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
519                         ptp_v2 = PTP_TCR_TSVER2ENA;
520                         /* take time stamp for SYNC messages only */
521                         ts_event_en = PTP_TCR_TSEVNTENA;
522 
523                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
524                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
525                         break;
526 
527                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
528                         /* PTP v2, UDP, Delay_req packet */
529                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
530                         ptp_v2 = PTP_TCR_TSVER2ENA;
531                         /* take time stamp for Delay_Req messages only */
532                         ts_master_en = PTP_TCR_TSMSTRENA;
533                         ts_event_en = PTP_TCR_TSEVNTENA;
534 
535                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
536                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
537                         break;
538 
539                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
540                         /* PTP v2/802.AS1 any layer, any kind of event packet */
541                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
542                         ptp_v2 = PTP_TCR_TSVER2ENA;
543                         /* take time stamp for all event messages */
544                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
545 
546                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
547                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
548                         ptp_over_ethernet = PTP_TCR_TSIPENA;
549                         break;
550 
551                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
552                         /* PTP v2/802.AS1, any layer, Sync packet */
553                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
554                         ptp_v2 = PTP_TCR_TSVER2ENA;
555                         /* take time stamp for SYNC messages only */
556                         ts_event_en = PTP_TCR_TSEVNTENA;
557 
558                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
559                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
560                         ptp_over_ethernet = PTP_TCR_TSIPENA;
561                         break;
562 
563                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
564                         /* PTP v2/802.AS1, any layer, Delay_req packet */
565                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
566                         ptp_v2 = PTP_TCR_TSVER2ENA;
567                         /* take time stamp for Delay_Req messages only */
568                         ts_master_en = PTP_TCR_TSMSTRENA;
569                         ts_event_en = PTP_TCR_TSEVNTENA;
570 
571                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
572                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
573                         ptp_over_ethernet = PTP_TCR_TSIPENA;
574                         break;
575 
576                 case HWTSTAMP_FILTER_ALL:
577                         /* time stamp any incoming packet */
578                         config.rx_filter = HWTSTAMP_FILTER_ALL;
579                         tstamp_all = PTP_TCR_TSENALL;
580                         break;
581 
582                 default:
583                         return -ERANGE;
584                 }
585         } else {
586                 switch (config.rx_filter) {
587                 case HWTSTAMP_FILTER_NONE:
588                         config.rx_filter = HWTSTAMP_FILTER_NONE;
589                         break;
590                 default:
591                         /* PTP v1, UDP, any kind of event packet */
592                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
593                         break;
594                 }
595         }
596         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
597         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
598 
599         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
600                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
601         else {
602                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
603                          tstamp_all | ptp_v2 | ptp_over_ethernet |
604                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
605                          ts_master_en | snap_type_sel);
606 
607                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
608 
609                 /* program Sub Second Increment reg */
610                 priv->hw->ptp->config_sub_second_increment(priv->ioaddr);
611 
612                 /* calculate default added value:
613                  * formula is :
614                  * addend = (2^32)/freq_div_ratio;
615                  * where, freq_div_ratio = clk_ptp_ref_i/50MHz
616                  * hence, addend = ((2^32) * 50MHz)/clk_ptp_ref_i;
617                  * NOTE: clk_ptp_ref_i should be >= 50MHz to
618                  *       achive 20ns accuracy.
619                  *
620                  * 2^x * y == (y << x), hence
621                  * 2^32 * 50000000 ==> (50000000 << 32)
622                  */
623                 temp = (u64) (50000000ULL << 32);
624                 priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
625                 priv->hw->ptp->config_addend(priv->ioaddr,
626                                              priv->default_addend);
627 
628                 /* initialize system time */
629                 getnstimeofday(&now);
630                 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec,
631                                             now.tv_nsec);
632         }
633 
634         return copy_to_user(ifr->ifr_data, &config,
635                             sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
636 }
637 
638 /**
639  * stmmac_init_ptp: init PTP
640  * @priv: driver private structure
641  * Description: this is to verify if the HW supports the PTPv1 or v2.
642  * This is done by looking at the HW cap. register.
643  * Also it registers the ptp driver.
644  */
645 static int stmmac_init_ptp(struct stmmac_priv *priv)
646 {
647         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
648                 return -EOPNOTSUPP;
649 
650         /* Fall-back to main clock in case of no PTP ref is passed */
651         priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref");
652         if (IS_ERR(priv->clk_ptp_ref)) {
653                 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk);
654                 priv->clk_ptp_ref = NULL;
655         } else {
656                 clk_prepare_enable(priv->clk_ptp_ref);
657                 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref);
658         }
659 
660         priv->adv_ts = 0;
661         if (priv->dma_cap.atime_stamp && priv->extend_desc)
662                 priv->adv_ts = 1;
663 
664         if (netif_msg_hw(priv) && priv->dma_cap.time_stamp)
665                 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
666 
667         if (netif_msg_hw(priv) && priv->adv_ts)
668                 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
669 
670         priv->hw->ptp = &stmmac_ptp;
671         priv->hwts_tx_en = 0;
672         priv->hwts_rx_en = 0;
673 
674         return stmmac_ptp_register(priv);
675 }
676 
677 static void stmmac_release_ptp(struct stmmac_priv *priv)
678 {
679         if (priv->clk_ptp_ref)
680                 clk_disable_unprepare(priv->clk_ptp_ref);
681         stmmac_ptp_unregister(priv);
682 }
683 
684 /**
685  * stmmac_adjust_link
686  * @dev: net device structure
687  * Description: it adjusts the link parameters.
688  */
689 static void stmmac_adjust_link(struct net_device *dev)
690 {
691         struct stmmac_priv *priv = netdev_priv(dev);
692         struct phy_device *phydev = priv->phydev;
693         unsigned long flags;
694         int new_state = 0;
695         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
696 
697         if (phydev == NULL)
698                 return;
699 
700         spin_lock_irqsave(&priv->lock, flags);
701 
702         if (phydev->link) {
703                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
704 
705                 /* Now we make sure that we can be in full duplex mode.
706                  * If not, we operate in half-duplex mode. */
707                 if (phydev->duplex != priv->oldduplex) {
708                         new_state = 1;
709                         if (!(phydev->duplex))
710                                 ctrl &= ~priv->hw->link.duplex;
711                         else
712                                 ctrl |= priv->hw->link.duplex;
713                         priv->oldduplex = phydev->duplex;
714                 }
715                 /* Flow Control operation */
716                 if (phydev->pause)
717                         priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex,
718                                                  fc, pause_time);
719 
720                 if (phydev->speed != priv->speed) {
721                         new_state = 1;
722                         switch (phydev->speed) {
723                         case 1000:
724                                 if (likely(priv->plat->has_gmac))
725                                         ctrl &= ~priv->hw->link.port;
726                                 stmmac_hw_fix_mac_speed(priv);
727                                 break;
728                         case 100:
729                         case 10:
730                                 if (priv->plat->has_gmac) {
731                                         ctrl |= priv->hw->link.port;
732                                         if (phydev->speed == SPEED_100) {
733                                                 ctrl |= priv->hw->link.speed;
734                                         } else {
735                                                 ctrl &= ~(priv->hw->link.speed);
736                                         }
737                                 } else {
738                                         ctrl &= ~priv->hw->link.port;
739                                 }
740                                 stmmac_hw_fix_mac_speed(priv);
741                                 break;
742                         default:
743                                 if (netif_msg_link(priv))
744                                         pr_warn("%s: Speed (%d) not 10/100\n",
745                                                 dev->name, phydev->speed);
746                                 break;
747                         }
748 
749                         priv->speed = phydev->speed;
750                 }
751 
752                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
753 
754                 if (!priv->oldlink) {
755                         new_state = 1;
756                         priv->oldlink = 1;
757                 }
758         } else if (priv->oldlink) {
759                 new_state = 1;
760                 priv->oldlink = 0;
761                 priv->speed = 0;
762                 priv->oldduplex = -1;
763         }
764 
765         if (new_state && netif_msg_link(priv))
766                 phy_print_status(phydev);
767 
768         spin_unlock_irqrestore(&priv->lock, flags);
769 
770         /* At this stage, it could be needed to setup the EEE or adjust some
771          * MAC related HW registers.
772          */
773         priv->eee_enabled = stmmac_eee_init(priv);
774 }
775 
776 /**
777  * stmmac_check_pcs_mode: verify if RGMII/SGMII is supported
778  * @priv: driver private structure
779  * Description: this is to verify if the HW supports the PCS.
780  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
781  * configured for the TBI, RTBI, or SGMII PHY interface.
782  */
783 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
784 {
785         int interface = priv->plat->interface;
786 
787         if (priv->dma_cap.pcs) {
788                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
789                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
790                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
791                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
792                         pr_debug("STMMAC: PCS RGMII support enable\n");
793                         priv->pcs = STMMAC_PCS_RGMII;
794                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
795                         pr_debug("STMMAC: PCS SGMII support enable\n");
796                         priv->pcs = STMMAC_PCS_SGMII;
797                 }
798         }
799 }
800 
801 /**
802  * stmmac_init_phy - PHY initialization
803  * @dev: net device structure
804  * Description: it initializes the driver's PHY state, and attaches the PHY
805  * to the mac driver.
806  *  Return value:
807  *  0 on success
808  */
809 static int stmmac_init_phy(struct net_device *dev)
810 {
811         struct stmmac_priv *priv = netdev_priv(dev);
812         struct phy_device *phydev;
813         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
814         char bus_id[MII_BUS_ID_SIZE];
815         int interface = priv->plat->interface;
816         int max_speed = priv->plat->max_speed;
817         priv->oldlink = 0;
818         priv->speed = 0;
819         priv->oldduplex = -1;
820 
821         if (priv->plat->phy_bus_name)
822                 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
823                          priv->plat->phy_bus_name, priv->plat->bus_id);
824         else
825                 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
826                          priv->plat->bus_id);
827 
828         snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
829                  priv->plat->phy_addr);
830         pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id_fmt);
831 
832         phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
833 
834         if (IS_ERR(phydev)) {
835                 pr_err("%s: Could not attach to PHY\n", dev->name);
836                 return PTR_ERR(phydev);
837         }
838 
839         /* Stop Advertising 1000BASE Capability if interface is not GMII */
840         if ((interface == PHY_INTERFACE_MODE_MII) ||
841             (interface == PHY_INTERFACE_MODE_RMII) ||
842                 (max_speed < 1000 && max_speed > 0))
843                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
844                                          SUPPORTED_1000baseT_Full);
845 
846         /*
847          * Broken HW is sometimes missing the pull-up resistor on the
848          * MDIO line, which results in reads to non-existent devices returning
849          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
850          * device as well.
851          * Note: phydev->phy_id is the result of reading the UID PHY registers.
852          */
853         if (phydev->phy_id == 0) {
854                 phy_disconnect(phydev);
855                 return -ENODEV;
856         }
857         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
858                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
859 
860         priv->phydev = phydev;
861 
862         return 0;
863 }
864 
865 /**
866  * stmmac_display_ring: display ring
867  * @head: pointer to the head of the ring passed.
868  * @size: size of the ring.
869  * @extend_desc: to verify if extended descriptors are used.
870  * Description: display the control/status and buffer descriptors.
871  */
872 static void stmmac_display_ring(void *head, int size, int extend_desc)
873 {
874         int i;
875         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
876         struct dma_desc *p = (struct dma_desc *)head;
877 
878         for (i = 0; i < size; i++) {
879                 u64 x;
880                 if (extend_desc) {
881                         x = *(u64 *) ep;
882                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
883                                 i, (unsigned int)virt_to_phys(ep),
884                                 (unsigned int)x, (unsigned int)(x >> 32),
885                                 ep->basic.des2, ep->basic.des3);
886                         ep++;
887                 } else {
888                         x = *(u64 *) p;
889                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
890                                 i, (unsigned int)virt_to_phys(p),
891                                 (unsigned int)x, (unsigned int)(x >> 32),
892                                 p->des2, p->des3);
893                         p++;
894                 }
895                 pr_info("\n");
896         }
897 }
898 
899 static void stmmac_display_rings(struct stmmac_priv *priv)
900 {
901         unsigned int txsize = priv->dma_tx_size;
902         unsigned int rxsize = priv->dma_rx_size;
903 
904         if (priv->extend_desc) {
905                 pr_info("Extended RX descriptor ring:\n");
906                 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
907                 pr_info("Extended TX descriptor ring:\n");
908                 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
909         } else {
910                 pr_info("RX descriptor ring:\n");
911                 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
912                 pr_info("TX descriptor ring:\n");
913                 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
914         }
915 }
916 
917 static int stmmac_set_bfsize(int mtu, int bufsize)
918 {
919         int ret = bufsize;
920 
921         if (mtu >= BUF_SIZE_4KiB)
922                 ret = BUF_SIZE_8KiB;
923         else if (mtu >= BUF_SIZE_2KiB)
924                 ret = BUF_SIZE_4KiB;
925         else if (mtu > DEFAULT_BUFSIZE)
926                 ret = BUF_SIZE_2KiB;
927         else
928                 ret = DEFAULT_BUFSIZE;
929 
930         return ret;
931 }
932 
933 /**
934  * stmmac_clear_descriptors: clear descriptors
935  * @priv: driver private structure
936  * Description: this function is called to clear the tx and rx descriptors
937  * in case of both basic and extended descriptors are used.
938  */
939 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
940 {
941         int i;
942         unsigned int txsize = priv->dma_tx_size;
943         unsigned int rxsize = priv->dma_rx_size;
944 
945         /* Clear the Rx/Tx descriptors */
946         for (i = 0; i < rxsize; i++)
947                 if (priv->extend_desc)
948                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
949                                                      priv->use_riwt, priv->mode,
950                                                      (i == rxsize - 1));
951                 else
952                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
953                                                      priv->use_riwt, priv->mode,
954                                                      (i == rxsize - 1));
955         for (i = 0; i < txsize; i++)
956                 if (priv->extend_desc)
957                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
958                                                      priv->mode,
959                                                      (i == txsize - 1));
960                 else
961                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
962                                                      priv->mode,
963                                                      (i == txsize - 1));
964 }
965 
966 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
967                                   int i, gfp_t flags)
968 {
969         struct sk_buff *skb;
970 
971         skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN,
972                                  flags);
973         if (!skb) {
974                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
975                 return -ENOMEM;
976         }
977         skb_reserve(skb, NET_IP_ALIGN);
978         priv->rx_skbuff[i] = skb;
979         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
980                                                 priv->dma_buf_sz,
981                                                 DMA_FROM_DEVICE);
982         if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
983                 pr_err("%s: DMA mapping error\n", __func__);
984                 dev_kfree_skb_any(skb);
985                 return -EINVAL;
986         }
987 
988         p->des2 = priv->rx_skbuff_dma[i];
989 
990         if ((priv->hw->mode->init_desc3) &&
991             (priv->dma_buf_sz == BUF_SIZE_16KiB))
992                 priv->hw->mode->init_desc3(p);
993 
994         return 0;
995 }
996 
997 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
998 {
999         if (priv->rx_skbuff[i]) {
1000                 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1001                                  priv->dma_buf_sz, DMA_FROM_DEVICE);
1002                 dev_kfree_skb_any(priv->rx_skbuff[i]);
1003         }
1004         priv->rx_skbuff[i] = NULL;
1005 }
1006 
1007 /**
1008  * init_dma_desc_rings - init the RX/TX descriptor rings
1009  * @dev: net device structure
1010  * Description:  this function initializes the DMA RX/TX descriptors
1011  * and allocates the socket buffers. It suppors the chained and ring
1012  * modes.
1013  */
1014 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1015 {
1016         int i;
1017         struct stmmac_priv *priv = netdev_priv(dev);
1018         unsigned int txsize = priv->dma_tx_size;
1019         unsigned int rxsize = priv->dma_rx_size;
1020         unsigned int bfsize = 0;
1021         int ret = -ENOMEM;
1022 
1023         if (priv->hw->mode->set_16kib_bfsize)
1024                 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1025 
1026         if (bfsize < BUF_SIZE_16KiB)
1027                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1028 
1029         priv->dma_buf_sz = bfsize;
1030 
1031         if (netif_msg_probe(priv))
1032                 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__,
1033                          txsize, rxsize, bfsize);
1034 
1035         if (netif_msg_probe(priv)) {
1036                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1037                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1038 
1039                 /* RX INITIALIZATION */
1040                 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1041         }
1042         for (i = 0; i < rxsize; i++) {
1043                 struct dma_desc *p;
1044                 if (priv->extend_desc)
1045                         p = &((priv->dma_erx + i)->basic);
1046                 else
1047                         p = priv->dma_rx + i;
1048 
1049                 ret = stmmac_init_rx_buffers(priv, p, i, flags);
1050                 if (ret)
1051                         goto err_init_rx_buffers;
1052 
1053                 if (netif_msg_probe(priv))
1054                         pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1055                                  priv->rx_skbuff[i]->data,
1056                                  (unsigned int)priv->rx_skbuff_dma[i]);
1057         }
1058         priv->cur_rx = 0;
1059         priv->dirty_rx = (unsigned int)(i - rxsize);
1060         buf_sz = bfsize;
1061 
1062         /* Setup the chained descriptor addresses */
1063         if (priv->mode == STMMAC_CHAIN_MODE) {
1064                 if (priv->extend_desc) {
1065                         priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1066                                              rxsize, 1);
1067                         priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1068                                              txsize, 1);
1069                 } else {
1070                         priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1071                                              rxsize, 0);
1072                         priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1073                                              txsize, 0);
1074                 }
1075         }
1076 
1077         /* TX INITIALIZATION */
1078         for (i = 0; i < txsize; i++) {
1079                 struct dma_desc *p;
1080                 if (priv->extend_desc)
1081                         p = &((priv->dma_etx + i)->basic);
1082                 else
1083                         p = priv->dma_tx + i;
1084                 p->des2 = 0;
1085                 priv->tx_skbuff_dma[i].buf = 0;
1086                 priv->tx_skbuff_dma[i].map_as_page = false;
1087                 priv->tx_skbuff[i] = NULL;
1088         }
1089 
1090         priv->dirty_tx = 0;
1091         priv->cur_tx = 0;
1092 
1093         stmmac_clear_descriptors(priv);
1094 
1095         if (netif_msg_hw(priv))
1096                 stmmac_display_rings(priv);
1097 
1098         return 0;
1099 err_init_rx_buffers:
1100         while (--i >= 0)
1101                 stmmac_free_rx_buffers(priv, i);
1102         return ret;
1103 }
1104 
1105 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1106 {
1107         int i;
1108 
1109         for (i = 0; i < priv->dma_rx_size; i++)
1110                 stmmac_free_rx_buffers(priv, i);
1111 }
1112 
1113 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1114 {
1115         int i;
1116 
1117         for (i = 0; i < priv->dma_tx_size; i++) {
1118                 struct dma_desc *p;
1119 
1120                 if (priv->extend_desc)
1121                         p = &((priv->dma_etx + i)->basic);
1122                 else
1123                         p = priv->dma_tx + i;
1124 
1125                 if (priv->tx_skbuff_dma[i].buf) {
1126                         if (priv->tx_skbuff_dma[i].map_as_page)
1127                                 dma_unmap_page(priv->device,
1128                                                priv->tx_skbuff_dma[i].buf,
1129                                                priv->hw->desc->get_tx_len(p),
1130                                                DMA_TO_DEVICE);
1131                         else
1132                                 dma_unmap_single(priv->device,
1133                                                  priv->tx_skbuff_dma[i].buf,
1134                                                  priv->hw->desc->get_tx_len(p),
1135                                                  DMA_TO_DEVICE);
1136                 }
1137 
1138                 if (priv->tx_skbuff[i] != NULL) {
1139                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1140                         priv->tx_skbuff[i] = NULL;
1141                         priv->tx_skbuff_dma[i].buf = 0;
1142                         priv->tx_skbuff_dma[i].map_as_page = false;
1143                 }
1144         }
1145 }
1146 
1147 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1148 {
1149         unsigned int txsize = priv->dma_tx_size;
1150         unsigned int rxsize = priv->dma_rx_size;
1151         int ret = -ENOMEM;
1152 
1153         priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
1154                                             GFP_KERNEL);
1155         if (!priv->rx_skbuff_dma)
1156                 return -ENOMEM;
1157 
1158         priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
1159                                         GFP_KERNEL);
1160         if (!priv->rx_skbuff)
1161                 goto err_rx_skbuff;
1162 
1163         priv->tx_skbuff_dma = kmalloc_array(txsize,
1164                                             sizeof(*priv->tx_skbuff_dma),
1165                                             GFP_KERNEL);
1166         if (!priv->tx_skbuff_dma)
1167                 goto err_tx_skbuff_dma;
1168 
1169         priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
1170                                         GFP_KERNEL);
1171         if (!priv->tx_skbuff)
1172                 goto err_tx_skbuff;
1173 
1174         if (priv->extend_desc) {
1175                 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
1176                                                    sizeof(struct
1177                                                           dma_extended_desc),
1178                                                    &priv->dma_rx_phy,
1179                                                    GFP_KERNEL);
1180                 if (!priv->dma_erx)
1181                         goto err_dma;
1182 
1183                 priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
1184                                                    sizeof(struct
1185                                                           dma_extended_desc),
1186                                                    &priv->dma_tx_phy,
1187                                                    GFP_KERNEL);
1188                 if (!priv->dma_etx) {
1189                         dma_free_coherent(priv->device, priv->dma_rx_size *
1190                                         sizeof(struct dma_extended_desc),
1191                                         priv->dma_erx, priv->dma_rx_phy);
1192                         goto err_dma;
1193                 }
1194         } else {
1195                 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
1196                                                   sizeof(struct dma_desc),
1197                                                   &priv->dma_rx_phy,
1198                                                   GFP_KERNEL);
1199                 if (!priv->dma_rx)
1200                         goto err_dma;
1201 
1202                 priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
1203                                                   sizeof(struct dma_desc),
1204                                                   &priv->dma_tx_phy,
1205                                                   GFP_KERNEL);
1206                 if (!priv->dma_tx) {
1207                         dma_free_coherent(priv->device, priv->dma_rx_size *
1208                                         sizeof(struct dma_desc),
1209                                         priv->dma_rx, priv->dma_rx_phy);
1210                         goto err_dma;
1211                 }
1212         }
1213 
1214         return 0;
1215 
1216 err_dma:
1217         kfree(priv->tx_skbuff);
1218 err_tx_skbuff:
1219         kfree(priv->tx_skbuff_dma);
1220 err_tx_skbuff_dma:
1221         kfree(priv->rx_skbuff);
1222 err_rx_skbuff:
1223         kfree(priv->rx_skbuff_dma);
1224         return ret;
1225 }
1226 
1227 static void free_dma_desc_resources(struct stmmac_priv *priv)
1228 {
1229         /* Release the DMA TX/RX socket buffers */
1230         dma_free_rx_skbufs(priv);
1231         dma_free_tx_skbufs(priv);
1232 
1233         /* Free DMA regions of consistent memory previously allocated */
1234         if (!priv->extend_desc) {
1235                 dma_free_coherent(priv->device,
1236                                   priv->dma_tx_size * sizeof(struct dma_desc),
1237                                   priv->dma_tx, priv->dma_tx_phy);
1238                 dma_free_coherent(priv->device,
1239                                   priv->dma_rx_size * sizeof(struct dma_desc),
1240                                   priv->dma_rx, priv->dma_rx_phy);
1241         } else {
1242                 dma_free_coherent(priv->device, priv->dma_tx_size *
1243                                   sizeof(struct dma_extended_desc),
1244                                   priv->dma_etx, priv->dma_tx_phy);
1245                 dma_free_coherent(priv->device, priv->dma_rx_size *
1246                                   sizeof(struct dma_extended_desc),
1247                                   priv->dma_erx, priv->dma_rx_phy);
1248         }
1249         kfree(priv->rx_skbuff_dma);
1250         kfree(priv->rx_skbuff);
1251         kfree(priv->tx_skbuff_dma);
1252         kfree(priv->tx_skbuff);
1253 }
1254 
1255 /**
1256  *  stmmac_dma_operation_mode - HW DMA operation mode
1257  *  @priv: driver private structure
1258  *  Description: it sets the DMA operation mode: tx/rx DMA thresholds
1259  *  or Store-And-Forward capability.
1260  */
1261 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1262 {
1263         if (priv->plat->force_thresh_dma_mode)
1264                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc);
1265         else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1266                 /*
1267                  * In case of GMAC, SF mode can be enabled
1268                  * to perform the TX COE in HW. This depends on:
1269                  * 1) TX COE if actually supported
1270                  * 2) There is no bugged Jumbo frame support
1271                  *    that needs to not insert csum in the TDES.
1272                  */
1273                 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE);
1274                 tc = SF_DMA_MODE;
1275         } else
1276                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1277 }
1278 
1279 /**
1280  * stmmac_tx_clean:
1281  * @priv: driver private structure
1282  * Description: it reclaims resources after transmission completes.
1283  */
1284 static void stmmac_tx_clean(struct stmmac_priv *priv)
1285 {
1286         unsigned int txsize = priv->dma_tx_size;
1287 
1288         spin_lock(&priv->tx_lock);
1289 
1290         priv->xstats.tx_clean++;
1291 
1292         while (priv->dirty_tx != priv->cur_tx) {
1293                 int last;
1294                 unsigned int entry = priv->dirty_tx % txsize;
1295                 struct sk_buff *skb = priv->tx_skbuff[entry];
1296                 struct dma_desc *p;
1297 
1298                 if (priv->extend_desc)
1299                         p = (struct dma_desc *)(priv->dma_etx + entry);
1300                 else
1301                         p = priv->dma_tx + entry;
1302 
1303                 /* Check if the descriptor is owned by the DMA. */
1304                 if (priv->hw->desc->get_tx_owner(p))
1305                         break;
1306 
1307                 /* Verify tx error by looking at the last segment. */
1308                 last = priv->hw->desc->get_tx_ls(p);
1309                 if (likely(last)) {
1310                         int tx_error =
1311                             priv->hw->desc->tx_status(&priv->dev->stats,
1312                                                       &priv->xstats, p,
1313                                                       priv->ioaddr);
1314                         if (likely(tx_error == 0)) {
1315                                 priv->dev->stats.tx_packets++;
1316                                 priv->xstats.tx_pkt_n++;
1317                         } else
1318                                 priv->dev->stats.tx_errors++;
1319 
1320                         stmmac_get_tx_hwtstamp(priv, entry, skb);
1321                 }
1322                 if (netif_msg_tx_done(priv))
1323                         pr_debug("%s: curr %d, dirty %d\n", __func__,
1324                                  priv->cur_tx, priv->dirty_tx);
1325 
1326                 if (likely(priv->tx_skbuff_dma[entry].buf)) {
1327                         if (priv->tx_skbuff_dma[entry].map_as_page)
1328                                 dma_unmap_page(priv->device,
1329                                                priv->tx_skbuff_dma[entry].buf,
1330                                                priv->hw->desc->get_tx_len(p),
1331                                                DMA_TO_DEVICE);
1332                         else
1333                                 dma_unmap_single(priv->device,
1334                                                  priv->tx_skbuff_dma[entry].buf,
1335                                                  priv->hw->desc->get_tx_len(p),
1336                                                  DMA_TO_DEVICE);
1337                         priv->tx_skbuff_dma[entry].buf = 0;
1338                         priv->tx_skbuff_dma[entry].map_as_page = false;
1339                 }
1340                 priv->hw->mode->clean_desc3(priv, p);
1341 
1342                 if (likely(skb != NULL)) {
1343                         dev_consume_skb_any(skb);
1344                         priv->tx_skbuff[entry] = NULL;
1345                 }
1346 
1347                 priv->hw->desc->release_tx_desc(p, priv->mode);
1348 
1349                 priv->dirty_tx++;
1350         }
1351         if (unlikely(netif_queue_stopped(priv->dev) &&
1352                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
1353                 netif_tx_lock(priv->dev);
1354                 if (netif_queue_stopped(priv->dev) &&
1355                     stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
1356                         if (netif_msg_tx_done(priv))
1357                                 pr_debug("%s: restart transmit\n", __func__);
1358                         netif_wake_queue(priv->dev);
1359                 }
1360                 netif_tx_unlock(priv->dev);
1361         }
1362 
1363         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1364                 stmmac_enable_eee_mode(priv);
1365                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1366         }
1367         spin_unlock(&priv->tx_lock);
1368 }
1369 
1370 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1371 {
1372         priv->hw->dma->enable_dma_irq(priv->ioaddr);
1373 }
1374 
1375 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1376 {
1377         priv->hw->dma->disable_dma_irq(priv->ioaddr);
1378 }
1379 
1380 /**
1381  * stmmac_tx_err: irq tx error mng function
1382  * @priv: driver private structure
1383  * Description: it cleans the descriptors and restarts the transmission
1384  * in case of errors.
1385  */
1386 static void stmmac_tx_err(struct stmmac_priv *priv)
1387 {
1388         int i;
1389         int txsize = priv->dma_tx_size;
1390         netif_stop_queue(priv->dev);
1391 
1392         priv->hw->dma->stop_tx(priv->ioaddr);
1393         dma_free_tx_skbufs(priv);
1394         for (i = 0; i < txsize; i++)
1395                 if (priv->extend_desc)
1396                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1397                                                      priv->mode,
1398                                                      (i == txsize - 1));
1399                 else
1400                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1401                                                      priv->mode,
1402                                                      (i == txsize - 1));
1403         priv->dirty_tx = 0;
1404         priv->cur_tx = 0;
1405         priv->hw->dma->start_tx(priv->ioaddr);
1406 
1407         priv->dev->stats.tx_errors++;
1408         netif_wake_queue(priv->dev);
1409 }
1410 
1411 /**
1412  * stmmac_dma_interrupt: DMA ISR
1413  * @priv: driver private structure
1414  * Description: this is the DMA ISR. It is called by the main ISR.
1415  * It calls the dwmac dma routine to understand which type of interrupt
1416  * happened. In case of there is a Normal interrupt and either TX or RX
1417  * interrupt happened so the NAPI is scheduled.
1418  */
1419 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1420 {
1421         int status;
1422 
1423         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1424         if (likely((status & handle_rx)) || (status & handle_tx)) {
1425                 if (likely(napi_schedule_prep(&priv->napi))) {
1426                         stmmac_disable_dma_irq(priv);
1427                         __napi_schedule(&priv->napi);
1428                 }
1429         }
1430         if (unlikely(status & tx_hard_error_bump_tc)) {
1431                 /* Try to bump up the dma threshold on this failure */
1432                 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
1433                         tc += 64;
1434                         priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1435                         priv->xstats.threshold = tc;
1436                 }
1437         } else if (unlikely(status == tx_hard_error))
1438                 stmmac_tx_err(priv);
1439 }
1440 
1441 /**
1442  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1443  * @priv: driver private structure
1444  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1445  */
1446 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1447 {
1448         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1449             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1450 
1451         dwmac_mmc_intr_all_mask(priv->ioaddr);
1452 
1453         if (priv->dma_cap.rmon) {
1454                 dwmac_mmc_ctrl(priv->ioaddr, mode);
1455                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1456         } else
1457                 pr_info(" No MAC Management Counters available\n");
1458 }
1459 
1460 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1461 {
1462         u32 hwid = priv->hw->synopsys_uid;
1463 
1464         /* Check Synopsys Id (not available on old chips) */
1465         if (likely(hwid)) {
1466                 u32 uid = ((hwid & 0x0000ff00) >> 8);
1467                 u32 synid = (hwid & 0x000000ff);
1468 
1469                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1470                         uid, synid);
1471 
1472                 return synid;
1473         }
1474         return 0;
1475 }
1476 
1477 /**
1478  * stmmac_selec_desc_mode: to select among: normal/alternate/extend descriptors
1479  * @priv: driver private structure
1480  * Description: select the Enhanced/Alternate or Normal descriptors.
1481  * In case of Enhanced/Alternate, it looks at the extended descriptors are
1482  * supported by the HW cap. register.
1483  */
1484 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1485 {
1486         if (priv->plat->enh_desc) {
1487                 pr_info(" Enhanced/Alternate descriptors\n");
1488 
1489                 /* GMAC older than 3.50 has no extended descriptors */
1490                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1491                         pr_info("\tEnabled extended descriptors\n");
1492                         priv->extend_desc = 1;
1493                 } else
1494                         pr_warn("Extended descriptors not supported\n");
1495 
1496                 priv->hw->desc = &enh_desc_ops;
1497         } else {
1498                 pr_info(" Normal descriptors\n");
1499                 priv->hw->desc = &ndesc_ops;
1500         }
1501 }
1502 
1503 /**
1504  * stmmac_get_hw_features: get MAC capabilities from the HW cap. register.
1505  * @priv: driver private structure
1506  * Description:
1507  *  new GMAC chip generations have a new register to indicate the
1508  *  presence of the optional feature/functions.
1509  *  This can be also used to override the value passed through the
1510  *  platform and necessary for old MAC10/100 and GMAC chips.
1511  */
1512 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1513 {
1514         u32 hw_cap = 0;
1515 
1516         if (priv->hw->dma->get_hw_feature) {
1517                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1518 
1519                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1520                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1521                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1522                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1523                 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1524                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1525                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1526                 priv->dma_cap.pmt_remote_wake_up =
1527                     (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1528                 priv->dma_cap.pmt_magic_frame =
1529                     (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1530                 /* MMC */
1531                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1532                 /* IEEE 1588-2002 */
1533                 priv->dma_cap.time_stamp =
1534                     (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1535                 /* IEEE 1588-2008 */
1536                 priv->dma_cap.atime_stamp =
1537                     (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1538                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1539                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1540                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1541                 /* TX and RX csum */
1542                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1543                 priv->dma_cap.rx_coe_type1 =
1544                     (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1545                 priv->dma_cap.rx_coe_type2 =
1546                     (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1547                 priv->dma_cap.rxfifo_over_2048 =
1548                     (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1549                 /* TX and RX number of channels */
1550                 priv->dma_cap.number_rx_channel =
1551                     (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1552                 priv->dma_cap.number_tx_channel =
1553                     (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1554                 /* Alternate (enhanced) DESC mode */
1555                 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1556         }
1557 
1558         return hw_cap;
1559 }
1560 
1561 /**
1562  * stmmac_check_ether_addr: check if the MAC addr is valid
1563  * @priv: driver private structure
1564  * Description:
1565  * it is to verify if the MAC address is valid, in case of failures it
1566  * generates a random MAC address
1567  */
1568 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1569 {
1570         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1571                 priv->hw->mac->get_umac_addr(priv->hw,
1572                                              priv->dev->dev_addr, 0);
1573                 if (!is_valid_ether_addr(priv->dev->dev_addr))
1574                         eth_hw_addr_random(priv->dev);
1575                 pr_info("%s: device MAC address %pM\n", priv->dev->name,
1576                         priv->dev->dev_addr);
1577         }
1578 }
1579 
1580 /**
1581  * stmmac_init_dma_engine: DMA init.
1582  * @priv: driver private structure
1583  * Description:
1584  * It inits the DMA invoking the specific MAC/GMAC callback.
1585  * Some DMA parameters can be passed from the platform;
1586  * in case of these are not passed a default is kept for the MAC or GMAC.
1587  */
1588 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1589 {
1590         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1591         int mixed_burst = 0;
1592         int atds = 0;
1593 
1594         if (priv->plat->dma_cfg) {
1595                 pbl = priv->plat->dma_cfg->pbl;
1596                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1597                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1598                 burst_len = priv->plat->dma_cfg->burst_len;
1599         }
1600 
1601         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1602                 atds = 1;
1603 
1604         return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1605                                    burst_len, priv->dma_tx_phy,
1606                                    priv->dma_rx_phy, atds);
1607 }
1608 
1609 /**
1610  * stmmac_tx_timer: mitigation sw timer for tx.
1611  * @data: data pointer
1612  * Description:
1613  * This is the timer handler to directly invoke the stmmac_tx_clean.
1614  */
1615 static void stmmac_tx_timer(unsigned long data)
1616 {
1617         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1618 
1619         stmmac_tx_clean(priv);
1620 }
1621 
1622 /**
1623  * stmmac_init_tx_coalesce: init tx mitigation options.
1624  * @priv: driver private structure
1625  * Description:
1626  * This inits the transmit coalesce parameters: i.e. timer rate,
1627  * timer handler and default threshold used for enabling the
1628  * interrupt on completion bit.
1629  */
1630 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1631 {
1632         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1633         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1634         init_timer(&priv->txtimer);
1635         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1636         priv->txtimer.data = (unsigned long)priv;
1637         priv->txtimer.function = stmmac_tx_timer;
1638         add_timer(&priv->txtimer);
1639 }
1640 
1641 /**
1642  * stmmac_hw_setup: setup mac in a usable state.
1643  *  @dev : pointer to the device structure.
1644  *  Description:
1645  *  This function sets up the ip in a usable state.
1646  *  Return value:
1647  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1648  *  file on failure.
1649  */
1650 static int stmmac_hw_setup(struct net_device *dev)
1651 {
1652         struct stmmac_priv *priv = netdev_priv(dev);
1653         int ret;
1654 
1655         /* DMA initialization and SW reset */
1656         ret = stmmac_init_dma_engine(priv);
1657         if (ret < 0) {
1658                 pr_err("%s: DMA engine initialization failed\n", __func__);
1659                 return ret;
1660         }
1661 
1662         /* Copy the MAC addr into the HW  */
1663         priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1664 
1665         /* If required, perform hw setup of the bus. */
1666         if (priv->plat->bus_setup)
1667                 priv->plat->bus_setup(priv->ioaddr);
1668 
1669         /* Initialize the MAC Core */
1670         priv->hw->mac->core_init(priv->hw, dev->mtu);
1671 
1672         ret = priv->hw->mac->rx_ipc(priv->hw);
1673         if (!ret) {
1674                 pr_warn(" RX IPC Checksum Offload disabled\n");
1675                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1676                 priv->hw->rx_csum = 0;
1677         }
1678 
1679         /* Enable the MAC Rx/Tx */
1680         stmmac_set_mac(priv->ioaddr, true);
1681 
1682         /* Set the HW DMA mode and the COE */
1683         stmmac_dma_operation_mode(priv);
1684 
1685         stmmac_mmc_setup(priv);
1686 
1687         ret = stmmac_init_ptp(priv);
1688         if (ret && ret != -EOPNOTSUPP)
1689                 pr_warn("%s: failed PTP initialisation\n", __func__);
1690 
1691 #ifdef CONFIG_STMMAC_DEBUG_FS
1692         ret = stmmac_init_fs(dev);
1693         if (ret < 0)
1694                 pr_warn("%s: failed debugFS registration\n", __func__);
1695 #endif
1696         /* Start the ball rolling... */
1697         pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
1698         priv->hw->dma->start_tx(priv->ioaddr);
1699         priv->hw->dma->start_rx(priv->ioaddr);
1700 
1701         /* Dump DMA/MAC registers */
1702         if (netif_msg_hw(priv)) {
1703                 priv->hw->mac->dump_regs(priv->hw);
1704                 priv->hw->dma->dump_regs(priv->ioaddr);
1705         }
1706         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1707 
1708         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1709                 priv->rx_riwt = MAX_DMA_RIWT;
1710                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1711         }
1712 
1713         if (priv->pcs && priv->hw->mac->ctrl_ane)
1714                 priv->hw->mac->ctrl_ane(priv->hw, 0);
1715 
1716         return 0;
1717 }
1718 
1719 /**
1720  *  stmmac_open - open entry point of the driver
1721  *  @dev : pointer to the device structure.
1722  *  Description:
1723  *  This function is the open entry point of the driver.
1724  *  Return value:
1725  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1726  *  file on failure.
1727  */
1728 static int stmmac_open(struct net_device *dev)
1729 {
1730         struct stmmac_priv *priv = netdev_priv(dev);
1731         int ret;
1732 
1733         stmmac_check_ether_addr(priv);
1734 
1735         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1736             priv->pcs != STMMAC_PCS_RTBI) {
1737                 ret = stmmac_init_phy(dev);
1738                 if (ret) {
1739                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1740                                __func__, ret);
1741                         return ret;
1742                 }
1743         }
1744 
1745         /* Extra statistics */
1746         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1747         priv->xstats.threshold = tc;
1748 
1749         /* Create and initialize the TX/RX descriptors chains. */
1750         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1751         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1752         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1753 
1754         ret = alloc_dma_desc_resources(priv);
1755         if (ret < 0) {
1756                 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1757                 goto dma_desc_error;
1758         }
1759 
1760         ret = init_dma_desc_rings(dev, GFP_KERNEL);
1761         if (ret < 0) {
1762                 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1763                 goto init_error;
1764         }
1765 
1766         ret = stmmac_hw_setup(dev);
1767         if (ret < 0) {
1768                 pr_err("%s: Hw setup failed\n", __func__);
1769                 goto init_error;
1770         }
1771 
1772         stmmac_init_tx_coalesce(priv);
1773 
1774         if (priv->phydev)
1775                 phy_start(priv->phydev);
1776 
1777         /* Request the IRQ lines */
1778         ret = request_irq(dev->irq, stmmac_interrupt,
1779                           IRQF_SHARED, dev->name, dev);
1780         if (unlikely(ret < 0)) {
1781                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1782                        __func__, dev->irq, ret);
1783                 goto init_error;
1784         }
1785 
1786         /* Request the Wake IRQ in case of another line is used for WoL */
1787         if (priv->wol_irq != dev->irq) {
1788                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1789                                   IRQF_SHARED, dev->name, dev);
1790                 if (unlikely(ret < 0)) {
1791                         pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1792                                __func__, priv->wol_irq, ret);
1793                         goto wolirq_error;
1794                 }
1795         }
1796 
1797         /* Request the IRQ lines */
1798         if (priv->lpi_irq > 0) {
1799                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1800                                   dev->name, dev);
1801                 if (unlikely(ret < 0)) {
1802                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1803                                __func__, priv->lpi_irq, ret);
1804                         goto lpiirq_error;
1805                 }
1806         }
1807 
1808         napi_enable(&priv->napi);
1809         netif_start_queue(dev);
1810 
1811         return 0;
1812 
1813 lpiirq_error:
1814         if (priv->wol_irq != dev->irq)
1815                 free_irq(priv->wol_irq, dev);
1816 wolirq_error:
1817         free_irq(dev->irq, dev);
1818 
1819 init_error:
1820         free_dma_desc_resources(priv);
1821 dma_desc_error:
1822         if (priv->phydev)
1823                 phy_disconnect(priv->phydev);
1824 
1825         return ret;
1826 }
1827 
1828 /**
1829  *  stmmac_release - close entry point of the driver
1830  *  @dev : device pointer.
1831  *  Description:
1832  *  This is the stop entry point of the driver.
1833  */
1834 static int stmmac_release(struct net_device *dev)
1835 {
1836         struct stmmac_priv *priv = netdev_priv(dev);
1837 
1838         if (priv->eee_enabled)
1839                 del_timer_sync(&priv->eee_ctrl_timer);
1840 
1841         /* Stop and disconnect the PHY */
1842         if (priv->phydev) {
1843                 phy_stop(priv->phydev);
1844                 phy_disconnect(priv->phydev);
1845                 priv->phydev = NULL;
1846         }
1847 
1848         netif_stop_queue(dev);
1849 
1850         napi_disable(&priv->napi);
1851 
1852         del_timer_sync(&priv->txtimer);
1853 
1854         /* Free the IRQ lines */
1855         free_irq(dev->irq, dev);
1856         if (priv->wol_irq != dev->irq)
1857                 free_irq(priv->wol_irq, dev);
1858         if (priv->lpi_irq > 0)
1859                 free_irq(priv->lpi_irq, dev);
1860 
1861         /* Stop TX/RX DMA and clear the descriptors */
1862         priv->hw->dma->stop_tx(priv->ioaddr);
1863         priv->hw->dma->stop_rx(priv->ioaddr);
1864 
1865         /* Release and free the Rx/Tx resources */
1866         free_dma_desc_resources(priv);
1867 
1868         /* Disable the MAC Rx/Tx */
1869         stmmac_set_mac(priv->ioaddr, false);
1870 
1871         netif_carrier_off(dev);
1872 
1873 #ifdef CONFIG_STMMAC_DEBUG_FS
1874         stmmac_exit_fs();
1875 #endif
1876 
1877         stmmac_release_ptp(priv);
1878 
1879         return 0;
1880 }
1881 
1882 /**
1883  *  stmmac_xmit: Tx entry point of the driver
1884  *  @skb : the socket buffer
1885  *  @dev : device pointer
1886  *  Description : this is the tx entry point of the driver.
1887  *  It programs the chain or the ring and supports oversized frames
1888  *  and SG feature.
1889  */
1890 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1891 {
1892         struct stmmac_priv *priv = netdev_priv(dev);
1893         unsigned int txsize = priv->dma_tx_size;
1894         unsigned int entry;
1895         int i, csum_insertion = 0, is_jumbo = 0;
1896         int nfrags = skb_shinfo(skb)->nr_frags;
1897         struct dma_desc *desc, *first;
1898         unsigned int nopaged_len = skb_headlen(skb);
1899         unsigned int enh_desc = priv->plat->enh_desc;
1900 
1901         spin_lock(&priv->tx_lock);
1902 
1903         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1904                 spin_unlock(&priv->tx_lock);
1905                 if (!netif_queue_stopped(dev)) {
1906                         netif_stop_queue(dev);
1907                         /* This is a hard error, log it. */
1908                         pr_err("%s: Tx Ring full when queue awake\n", __func__);
1909                 }
1910                 return NETDEV_TX_BUSY;
1911         }
1912 
1913         if (priv->tx_path_in_lpi_mode)
1914                 stmmac_disable_eee_mode(priv);
1915 
1916         entry = priv->cur_tx % txsize;
1917 
1918         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1919 
1920         if (priv->extend_desc)
1921                 desc = (struct dma_desc *)(priv->dma_etx + entry);
1922         else
1923                 desc = priv->dma_tx + entry;
1924 
1925         first = desc;
1926 
1927         /* To program the descriptors according to the size of the frame */
1928         if (enh_desc)
1929                 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
1930 
1931         if (likely(!is_jumbo)) {
1932                 desc->des2 = dma_map_single(priv->device, skb->data,
1933                                             nopaged_len, DMA_TO_DEVICE);
1934                 if (dma_mapping_error(priv->device, desc->des2))
1935                         goto dma_map_err;
1936                 priv->tx_skbuff_dma[entry].buf = desc->des2;
1937                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1938                                                 csum_insertion, priv->mode);
1939         } else {
1940                 desc = first;
1941                 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
1942                 if (unlikely(entry < 0))
1943                         goto dma_map_err;
1944         }
1945 
1946         for (i = 0; i < nfrags; i++) {
1947                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1948                 int len = skb_frag_size(frag);
1949 
1950                 priv->tx_skbuff[entry] = NULL;
1951                 entry = (++priv->cur_tx) % txsize;
1952                 if (priv->extend_desc)
1953                         desc = (struct dma_desc *)(priv->dma_etx + entry);
1954                 else
1955                         desc = priv->dma_tx + entry;
1956 
1957                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1958                                               DMA_TO_DEVICE);
1959                 if (dma_mapping_error(priv->device, desc->des2))
1960                         goto dma_map_err; /* should reuse desc w/o issues */
1961 
1962                 priv->tx_skbuff_dma[entry].buf = desc->des2;
1963                 priv->tx_skbuff_dma[entry].map_as_page = true;
1964                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
1965                                                 priv->mode);
1966                 wmb();
1967                 priv->hw->desc->set_tx_owner(desc);
1968                 wmb();
1969         }
1970 
1971         priv->tx_skbuff[entry] = skb;
1972 
1973         /* Finalize the latest segment. */
1974         priv->hw->desc->close_tx_desc(desc);
1975 
1976         wmb();
1977         /* According to the coalesce parameter the IC bit for the latest
1978          * segment could be reset and the timer re-started to invoke the
1979          * stmmac_tx function. This approach takes care about the fragments.
1980          */
1981         priv->tx_count_frames += nfrags + 1;
1982         if (priv->tx_coal_frames > priv->tx_count_frames) {
1983                 priv->hw->desc->clear_tx_ic(desc);
1984                 priv->xstats.tx_reset_ic_bit++;
1985                 mod_timer(&priv->txtimer,
1986                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
1987         } else
1988                 priv->tx_count_frames = 0;
1989 
1990         /* To avoid raise condition */
1991         priv->hw->desc->set_tx_owner(first);
1992         wmb();
1993 
1994         priv->cur_tx++;
1995 
1996         if (netif_msg_pktdata(priv)) {
1997                 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
1998                         __func__, (priv->cur_tx % txsize),
1999                         (priv->dirty_tx % txsize), entry, first, nfrags);
2000 
2001                 if (priv->extend_desc)
2002                         stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
2003                 else
2004                         stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
2005 
2006                 pr_debug(">>> frame to be transmitted: ");
2007                 print_pkt(skb->data, skb->len);
2008         }
2009         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2010                 if (netif_msg_hw(priv))
2011                         pr_debug("%s: stop transmitted packets\n", __func__);
2012                 netif_stop_queue(dev);
2013         }
2014 
2015         dev->stats.tx_bytes += skb->len;
2016 
2017         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2018                      priv->hwts_tx_en)) {
2019                 /* declare that device is doing timestamping */
2020                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2021                 priv->hw->desc->enable_tx_timestamp(first);
2022         }
2023 
2024         if (!priv->hwts_tx_en)
2025                 skb_tx_timestamp(skb);
2026 
2027         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
2028 
2029         spin_unlock(&priv->tx_lock);
2030         return NETDEV_TX_OK;
2031 
2032 dma_map_err:
2033         spin_unlock(&priv->tx_lock);
2034         dev_err(priv->device, "Tx dma map failed\n");
2035         dev_kfree_skb(skb);
2036         priv->dev->stats.tx_dropped++;
2037         return NETDEV_TX_OK;
2038 }
2039 
2040 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
2041 {
2042         struct ethhdr *ehdr;
2043         u16 vlanid;
2044 
2045         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
2046             NETIF_F_HW_VLAN_CTAG_RX &&
2047             !__vlan_get_tag(skb, &vlanid)) {
2048                 /* pop the vlan tag */
2049                 ehdr = (struct ethhdr *)skb->data;
2050                 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
2051                 skb_pull(skb, VLAN_HLEN);
2052                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
2053         }
2054 }
2055 
2056 
2057 /**
2058  * stmmac_rx_refill: refill used skb preallocated buffers
2059  * @priv: driver private structure
2060  * Description : this is to reallocate the skb for the reception process
2061  * that is based on zero-copy.
2062  */
2063 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2064 {
2065         unsigned int rxsize = priv->dma_rx_size;
2066         int bfsize = priv->dma_buf_sz;
2067 
2068         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
2069                 unsigned int entry = priv->dirty_rx % rxsize;
2070                 struct dma_desc *p;
2071 
2072                 if (priv->extend_desc)
2073                         p = (struct dma_desc *)(priv->dma_erx + entry);
2074                 else
2075                         p = priv->dma_rx + entry;
2076 
2077                 if (likely(priv->rx_skbuff[entry] == NULL)) {
2078                         struct sk_buff *skb;
2079 
2080                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2081 
2082                         if (unlikely(skb == NULL))
2083                                 break;
2084 
2085                         priv->rx_skbuff[entry] = skb;
2086                         priv->rx_skbuff_dma[entry] =
2087                             dma_map_single(priv->device, skb->data, bfsize,
2088                                            DMA_FROM_DEVICE);
2089                         if (dma_mapping_error(priv->device,
2090                                               priv->rx_skbuff_dma[entry])) {
2091                                 dev_err(priv->device, "Rx dma map failed\n");
2092                                 dev_kfree_skb(skb);
2093                                 break;
2094                         }
2095                         p->des2 = priv->rx_skbuff_dma[entry];
2096 
2097                         priv->hw->mode->refill_desc3(priv, p);
2098 
2099                         if (netif_msg_rx_status(priv))
2100                                 pr_debug("\trefill entry #%d\n", entry);
2101                 }
2102                 wmb();
2103                 priv->hw->desc->set_rx_owner(p);
2104                 wmb();
2105         }
2106 }
2107 
2108 /**
2109  * stmmac_rx_refill: refill used skb preallocated buffers
2110  * @priv: driver private structure
2111  * @limit: napi bugget.
2112  * Description :  this the function called by the napi poll method.
2113  * It gets all the frames inside the ring.
2114  */
2115 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2116 {
2117         unsigned int rxsize = priv->dma_rx_size;
2118         unsigned int entry = priv->cur_rx % rxsize;
2119         unsigned int next_entry;
2120         unsigned int count = 0;
2121         int coe = priv->hw->rx_csum;
2122 
2123         if (netif_msg_rx_status(priv)) {
2124                 pr_debug("%s: descriptor ring:\n", __func__);
2125                 if (priv->extend_desc)
2126                         stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
2127                 else
2128                         stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
2129         }
2130         while (count < limit) {
2131                 int status;
2132                 struct dma_desc *p;
2133 
2134                 if (priv->extend_desc)
2135                         p = (struct dma_desc *)(priv->dma_erx + entry);
2136                 else
2137                         p = priv->dma_rx + entry;
2138 
2139                 if (priv->hw->desc->get_rx_owner(p))
2140                         break;
2141 
2142                 count++;
2143 
2144                 next_entry = (++priv->cur_rx) % rxsize;
2145                 if (priv->extend_desc)
2146                         prefetch(priv->dma_erx + next_entry);
2147                 else
2148                         prefetch(priv->dma_rx + next_entry);
2149 
2150                 /* read the status of the incoming frame */
2151                 status = priv->hw->desc->rx_status(&priv->dev->stats,
2152                                                    &priv->xstats, p);
2153                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2154                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
2155                                                            &priv->xstats,
2156                                                            priv->dma_erx +
2157                                                            entry);
2158                 if (unlikely(status == discard_frame)) {
2159                         priv->dev->stats.rx_errors++;
2160                         if (priv->hwts_rx_en && !priv->extend_desc) {
2161                                 /* DESC2 & DESC3 will be overwitten by device
2162                                  * with timestamp value, hence reinitialize
2163                                  * them in stmmac_rx_refill() function so that
2164                                  * device can reuse it.
2165                                  */
2166                                 priv->rx_skbuff[entry] = NULL;
2167                                 dma_unmap_single(priv->device,
2168                                                  priv->rx_skbuff_dma[entry],
2169                                                  priv->dma_buf_sz,
2170                                                  DMA_FROM_DEVICE);
2171                         }
2172                 } else {
2173                         struct sk_buff *skb;
2174                         int frame_len;
2175 
2176                         frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2177 
2178                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2179                          * Type frames (LLC/LLC-SNAP)
2180                          */
2181                         if (unlikely(status != llc_snap))
2182                                 frame_len -= ETH_FCS_LEN;
2183 
2184                         if (netif_msg_rx_status(priv)) {
2185                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2186                                          p, entry, p->des2);
2187                                 if (frame_len > ETH_FRAME_LEN)
2188                                         pr_debug("\tframe size %d, COE: %d\n",
2189                                                  frame_len, status);
2190                         }
2191                         skb = priv->rx_skbuff[entry];
2192                         if (unlikely(!skb)) {
2193                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
2194                                        priv->dev->name);
2195                                 priv->dev->stats.rx_dropped++;
2196                                 break;
2197                         }
2198                         prefetch(skb->data - NET_IP_ALIGN);
2199                         priv->rx_skbuff[entry] = NULL;
2200 
2201                         stmmac_get_rx_hwtstamp(priv, entry, skb);
2202 
2203                         skb_put(skb, frame_len);
2204                         dma_unmap_single(priv->device,
2205                                          priv->rx_skbuff_dma[entry],
2206                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
2207 
2208                         if (netif_msg_pktdata(priv)) {
2209                                 pr_debug("frame received (%dbytes)", frame_len);
2210                                 print_pkt(skb->data, frame_len);
2211                         }
2212 
2213                         stmmac_rx_vlan(priv->dev, skb);
2214 
2215                         skb->protocol = eth_type_trans(skb, priv->dev);
2216 
2217                         if (unlikely(!coe))
2218                                 skb_checksum_none_assert(skb);
2219                         else
2220                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2221 
2222                         napi_gro_receive(&priv->napi, skb);
2223 
2224                         priv->dev->stats.rx_packets++;
2225                         priv->dev->stats.rx_bytes += frame_len;
2226                 }
2227                 entry = next_entry;
2228         }
2229 
2230         stmmac_rx_refill(priv);
2231 
2232         priv->xstats.rx_pkt_n += count;
2233 
2234         return count;
2235 }
2236 
2237 /**
2238  *  stmmac_poll - stmmac poll method (NAPI)
2239  *  @napi : pointer to the napi structure.
2240  *  @budget : maximum number of packets that the current CPU can receive from
2241  *            all interfaces.
2242  *  Description :
2243  *  To look at the incoming frames and clear the tx resources.
2244  */
2245 static int stmmac_poll(struct napi_struct *napi, int budget)
2246 {
2247         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2248         int work_done = 0;
2249 
2250         priv->xstats.napi_poll++;
2251         stmmac_tx_clean(priv);
2252 
2253         work_done = stmmac_rx(priv, budget);
2254         if (work_done < budget) {
2255                 napi_complete(napi);
2256                 stmmac_enable_dma_irq(priv);
2257         }
2258         return work_done;
2259 }
2260 
2261 /**
2262  *  stmmac_tx_timeout
2263  *  @dev : Pointer to net device structure
2264  *  Description: this function is called when a packet transmission fails to
2265  *   complete within a reasonable time. The driver will mark the error in the
2266  *   netdev structure and arrange for the device to be reset to a sane state
2267  *   in order to transmit a new packet.
2268  */
2269 static void stmmac_tx_timeout(struct net_device *dev)
2270 {
2271         struct stmmac_priv *priv = netdev_priv(dev);
2272 
2273         /* Clear Tx resources and restart transmitting again */
2274         stmmac_tx_err(priv);
2275 }
2276 
2277 /**
2278  *  stmmac_set_rx_mode - entry point for multicast addressing
2279  *  @dev : pointer to the device structure
2280  *  Description:
2281  *  This function is a driver entry point which gets called by the kernel
2282  *  whenever multicast addresses must be enabled/disabled.
2283  *  Return value:
2284  *  void.
2285  */
2286 static void stmmac_set_rx_mode(struct net_device *dev)
2287 {
2288         struct stmmac_priv *priv = netdev_priv(dev);
2289 
2290         priv->hw->mac->set_filter(priv->hw, dev);
2291 }
2292 
2293 /**
2294  *  stmmac_change_mtu - entry point to change MTU size for the device.
2295  *  @dev : device pointer.
2296  *  @new_mtu : the new MTU size for the device.
2297  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
2298  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
2299  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
2300  *  Return value:
2301  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2302  *  file on failure.
2303  */
2304 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2305 {
2306         struct stmmac_priv *priv = netdev_priv(dev);
2307         int max_mtu;
2308 
2309         if (netif_running(dev)) {
2310                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2311                 return -EBUSY;
2312         }
2313 
2314         if (priv->plat->enh_desc)
2315                 max_mtu = JUMBO_LEN;
2316         else
2317                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2318 
2319         if (priv->plat->maxmtu < max_mtu)
2320                 max_mtu = priv->plat->maxmtu;
2321 
2322         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2323                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2324                 return -EINVAL;
2325         }
2326 
2327         dev->mtu = new_mtu;
2328         netdev_update_features(dev);
2329 
2330         return 0;
2331 }
2332 
2333 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2334                                              netdev_features_t features)
2335 {
2336         struct stmmac_priv *priv = netdev_priv(dev);
2337 
2338         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2339                 features &= ~NETIF_F_RXCSUM;
2340 
2341         if (!priv->plat->tx_coe)
2342                 features &= ~NETIF_F_ALL_CSUM;
2343 
2344         /* Some GMAC devices have a bugged Jumbo frame support that
2345          * needs to have the Tx COE disabled for oversized frames
2346          * (due to limited buffer sizes). In this case we disable
2347          * the TX csum insertionin the TDES and not use SF.
2348          */
2349         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2350                 features &= ~NETIF_F_ALL_CSUM;
2351 
2352         return features;
2353 }
2354 
2355 static int stmmac_set_features(struct net_device *netdev,
2356                                netdev_features_t features)
2357 {
2358         struct stmmac_priv *priv = netdev_priv(netdev);
2359 
2360         /* Keep the COE Type in case of csum is supporting */
2361         if (features & NETIF_F_RXCSUM)
2362                 priv->hw->rx_csum = priv->plat->rx_coe;
2363         else
2364                 priv->hw->rx_csum = 0;
2365         /* No check needed because rx_coe has been set before and it will be
2366          * fixed in case of issue.
2367          */
2368         priv->hw->mac->rx_ipc(priv->hw);
2369 
2370         return 0;
2371 }
2372 
2373 /**
2374  *  stmmac_interrupt - main ISR
2375  *  @irq: interrupt number.
2376  *  @dev_id: to pass the net device pointer.
2377  *  Description: this is the main driver interrupt service routine.
2378  *  It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI
2379  *  interrupts.
2380  */
2381 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2382 {
2383         struct net_device *dev = (struct net_device *)dev_id;
2384         struct stmmac_priv *priv = netdev_priv(dev);
2385 
2386         if (priv->irq_wake)
2387                 pm_wakeup_event(priv->device, 0);
2388 
2389         if (unlikely(!dev)) {
2390                 pr_err("%s: invalid dev pointer\n", __func__);
2391                 return IRQ_NONE;
2392         }
2393 
2394         /* To handle GMAC own interrupts */
2395         if (priv->plat->has_gmac) {
2396                 int status = priv->hw->mac->host_irq_status(priv->hw,
2397                                                             &priv->xstats);
2398                 if (unlikely(status)) {
2399                         /* For LPI we need to save the tx status */
2400                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2401                                 priv->tx_path_in_lpi_mode = true;
2402                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2403                                 priv->tx_path_in_lpi_mode = false;
2404                 }
2405         }
2406 
2407         /* To handle DMA interrupts */
2408         stmmac_dma_interrupt(priv);
2409 
2410         return IRQ_HANDLED;
2411 }
2412 
2413 #ifdef CONFIG_NET_POLL_CONTROLLER
2414 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2415  * to allow network I/O with interrupts disabled.
2416  */
2417 static void stmmac_poll_controller(struct net_device *dev)
2418 {
2419         disable_irq(dev->irq);
2420         stmmac_interrupt(dev->irq, dev);
2421         enable_irq(dev->irq);
2422 }
2423 #endif
2424 
2425 /**
2426  *  stmmac_ioctl - Entry point for the Ioctl
2427  *  @dev: Device pointer.
2428  *  @rq: An IOCTL specefic structure, that can contain a pointer to
2429  *  a proprietary structure used to pass information to the driver.
2430  *  @cmd: IOCTL command
2431  *  Description:
2432  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2433  */
2434 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2435 {
2436         struct stmmac_priv *priv = netdev_priv(dev);
2437         int ret = -EOPNOTSUPP;
2438 
2439         if (!netif_running(dev))
2440                 return -EINVAL;
2441 
2442         switch (cmd) {
2443         case SIOCGMIIPHY:
2444         case SIOCGMIIREG:
2445         case SIOCSMIIREG:
2446                 if (!priv->phydev)
2447                         return -EINVAL;
2448                 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2449                 break;
2450         case SIOCSHWTSTAMP:
2451                 ret = stmmac_hwtstamp_ioctl(dev, rq);
2452                 break;
2453         default:
2454                 break;
2455         }
2456 
2457         return ret;
2458 }
2459 
2460 #ifdef CONFIG_STMMAC_DEBUG_FS
2461 static struct dentry *stmmac_fs_dir;
2462 static struct dentry *stmmac_rings_status;
2463 static struct dentry *stmmac_dma_cap;
2464 
2465 static void sysfs_display_ring(void *head, int size, int extend_desc,
2466                                struct seq_file *seq)
2467 {
2468         int i;
2469         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2470         struct dma_desc *p = (struct dma_desc *)head;
2471 
2472         for (i = 0; i < size; i++) {
2473                 u64 x;
2474                 if (extend_desc) {
2475                         x = *(u64 *) ep;
2476                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2477                                    i, (unsigned int)virt_to_phys(ep),
2478                                    (unsigned int)x, (unsigned int)(x >> 32),
2479                                    ep->basic.des2, ep->basic.des3);
2480                         ep++;
2481                 } else {
2482                         x = *(u64 *) p;
2483                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2484                                    i, (unsigned int)virt_to_phys(ep),
2485                                    (unsigned int)x, (unsigned int)(x >> 32),
2486                                    p->des2, p->des3);
2487                         p++;
2488                 }
2489                 seq_printf(seq, "\n");
2490         }
2491 }
2492 
2493 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2494 {
2495         struct net_device *dev = seq->private;
2496         struct stmmac_priv *priv = netdev_priv(dev);
2497         unsigned int txsize = priv->dma_tx_size;
2498         unsigned int rxsize = priv->dma_rx_size;
2499 
2500         if (priv->extend_desc) {
2501                 seq_printf(seq, "Extended RX descriptor ring:\n");
2502                 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq);
2503                 seq_printf(seq, "Extended TX descriptor ring:\n");
2504                 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq);
2505         } else {
2506                 seq_printf(seq, "RX descriptor ring:\n");
2507                 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
2508                 seq_printf(seq, "TX descriptor ring:\n");
2509                 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
2510         }
2511 
2512         return 0;
2513 }
2514 
2515 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2516 {
2517         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2518 }
2519 
2520 static const struct file_operations stmmac_rings_status_fops = {
2521         .owner = THIS_MODULE,
2522         .open = stmmac_sysfs_ring_open,
2523         .read = seq_read,
2524         .llseek = seq_lseek,
2525         .release = single_release,
2526 };
2527 
2528 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2529 {
2530         struct net_device *dev = seq->private;
2531         struct stmmac_priv *priv = netdev_priv(dev);
2532 
2533         if (!priv->hw_cap_support) {
2534                 seq_printf(seq, "DMA HW features not supported\n");
2535                 return 0;
2536         }
2537 
2538         seq_printf(seq, "==============================\n");
2539         seq_printf(seq, "\tDMA HW features\n");
2540         seq_printf(seq, "==============================\n");
2541 
2542         seq_printf(seq, "\t10/100 Mbps %s\n",
2543                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2544         seq_printf(seq, "\t1000 Mbps %s\n",
2545                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
2546         seq_printf(seq, "\tHalf duple %s\n",
2547                    (priv->dma_cap.half_duplex) ? "Y" : "N");
2548         seq_printf(seq, "\tHash Filter: %s\n",
2549                    (priv->dma_cap.hash_filter) ? "Y" : "N");
2550         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2551                    (priv->dma_cap.multi_addr) ? "Y" : "N");
2552         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2553                    (priv->dma_cap.pcs) ? "Y" : "N");
2554         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2555                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
2556         seq_printf(seq, "\tPMT Remote wake up: %s\n",
2557                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2558         seq_printf(seq, "\tPMT Magic Frame: %s\n",
2559                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2560         seq_printf(seq, "\tRMON module: %s\n",
2561                    (priv->dma_cap.rmon) ? "Y" : "N");
2562         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2563                    (priv->dma_cap.time_stamp) ? "Y" : "N");
2564         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2565                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
2566         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2567                    (priv->dma_cap.eee) ? "Y" : "N");
2568         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2569         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2570                    (priv->dma_cap.tx_coe) ? "Y" : "N");
2571         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2572                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2573         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2574                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2575         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2576                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2577         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2578                    priv->dma_cap.number_rx_channel);
2579         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2580                    priv->dma_cap.number_tx_channel);
2581         seq_printf(seq, "\tEnhanced descriptors: %s\n",
2582                    (priv->dma_cap.enh_desc) ? "Y" : "N");
2583 
2584         return 0;
2585 }
2586 
2587 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2588 {
2589         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2590 }
2591 
2592 static const struct file_operations stmmac_dma_cap_fops = {
2593         .owner = THIS_MODULE,
2594         .open = stmmac_sysfs_dma_cap_open,
2595         .read = seq_read,
2596         .llseek = seq_lseek,
2597         .release = single_release,
2598 };
2599 
2600 static int stmmac_init_fs(struct net_device *dev)
2601 {
2602         /* Create debugfs entries */
2603         stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
2604 
2605         if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
2606                 pr_err("ERROR %s, debugfs create directory failed\n",
2607                        STMMAC_RESOURCE_NAME);
2608 
2609                 return -ENOMEM;
2610         }
2611 
2612         /* Entry to report DMA RX/TX rings */
2613         stmmac_rings_status = debugfs_create_file("descriptors_status",
2614                                                   S_IRUGO, stmmac_fs_dir, dev,
2615                                                   &stmmac_rings_status_fops);
2616 
2617         if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
2618                 pr_info("ERROR creating stmmac ring debugfs file\n");
2619                 debugfs_remove(stmmac_fs_dir);
2620 
2621                 return -ENOMEM;
2622         }
2623 
2624         /* Entry to report the DMA HW features */
2625         stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
2626                                              dev, &stmmac_dma_cap_fops);
2627 
2628         if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
2629                 pr_info("ERROR creating stmmac MMC debugfs file\n");
2630                 debugfs_remove(stmmac_rings_status);
2631                 debugfs_remove(stmmac_fs_dir);
2632 
2633                 return -ENOMEM;
2634         }
2635 
2636         return 0;
2637 }
2638 
2639 static void stmmac_exit_fs(void)
2640 {
2641         debugfs_remove(stmmac_rings_status);
2642         debugfs_remove(stmmac_dma_cap);
2643         debugfs_remove(stmmac_fs_dir);
2644 }
2645 #endif /* CONFIG_STMMAC_DEBUG_FS */
2646 
2647 static const struct net_device_ops stmmac_netdev_ops = {
2648         .ndo_open = stmmac_open,
2649         .ndo_start_xmit = stmmac_xmit,
2650         .ndo_stop = stmmac_release,
2651         .ndo_change_mtu = stmmac_change_mtu,
2652         .ndo_fix_features = stmmac_fix_features,
2653         .ndo_set_features = stmmac_set_features,
2654         .ndo_set_rx_mode = stmmac_set_rx_mode,
2655         .ndo_tx_timeout = stmmac_tx_timeout,
2656         .ndo_do_ioctl = stmmac_ioctl,
2657 #ifdef CONFIG_NET_POLL_CONTROLLER
2658         .ndo_poll_controller = stmmac_poll_controller,
2659 #endif
2660         .ndo_set_mac_address = eth_mac_addr,
2661 };
2662 
2663 /**
2664  *  stmmac_hw_init - Init the MAC device
2665  *  @priv: driver private structure
2666  *  Description: this function detects which MAC device
2667  *  (GMAC/MAC10-100) has to attached, checks the HW capability
2668  *  (if supported) and sets the driver's features (for example
2669  *  to use the ring or chaine mode or support the normal/enh
2670  *  descriptor structure).
2671  */
2672 static int stmmac_hw_init(struct stmmac_priv *priv)
2673 {
2674         struct mac_device_info *mac;
2675 
2676         /* Identify the MAC HW device */
2677         if (priv->plat->has_gmac) {
2678                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2679                 mac = dwmac1000_setup(priv->ioaddr,
2680                                       priv->plat->multicast_filter_bins,
2681                                       priv->plat->unicast_filter_entries);
2682         } else {
2683                 mac = dwmac100_setup(priv->ioaddr);
2684         }
2685         if (!mac)
2686                 return -ENOMEM;
2687 
2688         priv->hw = mac;
2689 
2690         /* Get and dump the chip ID */
2691         priv->synopsys_id = stmmac_get_synopsys_id(priv);
2692 
2693         /* To use the chained or ring mode */
2694         if (chain_mode) {
2695                 priv->hw->mode = &chain_mode_ops;
2696                 pr_info(" Chain mode enabled\n");
2697                 priv->mode = STMMAC_CHAIN_MODE;
2698         } else {
2699                 priv->hw->mode = &ring_mode_ops;
2700                 pr_info(" Ring mode enabled\n");
2701                 priv->mode = STMMAC_RING_MODE;
2702         }
2703 
2704         /* Get the HW capability (new GMAC newer than 3.50a) */
2705         priv->hw_cap_support = stmmac_get_hw_features(priv);
2706         if (priv->hw_cap_support) {
2707                 pr_info(" DMA HW capability register supported");
2708 
2709                 /* We can override some gmac/dma configuration fields: e.g.
2710                  * enh_desc, tx_coe (e.g. that are passed through the
2711                  * platform) with the values from the HW capability
2712                  * register (if supported).
2713                  */
2714                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2715                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2716 
2717                 priv->plat->tx_coe = priv->dma_cap.tx_coe;
2718 
2719                 if (priv->dma_cap.rx_coe_type2)
2720                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2721                 else if (priv->dma_cap.rx_coe_type1)
2722                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2723 
2724         } else
2725                 pr_info(" No HW DMA feature register supported");
2726 
2727         /* To use alternate (extended) or normal descriptor structures */
2728         stmmac_selec_desc_mode(priv);
2729 
2730         if (priv->plat->rx_coe) {
2731                 priv->hw->rx_csum = priv->plat->rx_coe;
2732                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2733                         priv->plat->rx_coe);
2734         }
2735         if (priv->plat->tx_coe)
2736                 pr_info(" TX Checksum insertion supported\n");
2737 
2738         if (priv->plat->pmt) {
2739                 pr_info(" Wake-Up On Lan supported\n");
2740                 device_set_wakeup_capable(priv->device, 1);
2741         }
2742 
2743         return 0;
2744 }
2745 
2746 /**
2747  * stmmac_dvr_probe
2748  * @device: device pointer
2749  * @plat_dat: platform data pointer
2750  * @addr: iobase memory address
2751  * Description: this is the main probe function used to
2752  * call the alloc_etherdev, allocate the priv structure.
2753  */
2754 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
2755                                      struct plat_stmmacenet_data *plat_dat,
2756                                      void __iomem *addr)
2757 {
2758         int ret = 0;
2759         struct net_device *ndev = NULL;
2760         struct stmmac_priv *priv;
2761 
2762         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2763         if (!ndev)
2764                 return NULL;
2765 
2766         SET_NETDEV_DEV(ndev, device);
2767 
2768         priv = netdev_priv(ndev);
2769         priv->device = device;
2770         priv->dev = ndev;
2771 
2772         stmmac_set_ethtool_ops(ndev);
2773         priv->pause = pause;
2774         priv->plat = plat_dat;
2775         priv->ioaddr = addr;
2776         priv->dev->base_addr = (unsigned long)addr;
2777 
2778         /* Verify driver arguments */
2779         stmmac_verify_args();
2780 
2781         /* Override with kernel parameters if supplied XXX CRS XXX
2782          * this needs to have multiple instances
2783          */
2784         if ((phyaddr >= 0) && (phyaddr <= 31))
2785                 priv->plat->phy_addr = phyaddr;
2786 
2787         priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
2788         if (IS_ERR(priv->stmmac_clk)) {
2789                 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
2790                          __func__);
2791                 /* If failed to obtain stmmac_clk and specific clk_csr value
2792                  * is NOT passed from the platform, probe fail.
2793                  */
2794                 if (!priv->plat->clk_csr) {
2795                         ret = PTR_ERR(priv->stmmac_clk);
2796                         goto error_clk_get;
2797                 } else {
2798                         priv->stmmac_clk = NULL;
2799                 }
2800         }
2801         clk_prepare_enable(priv->stmmac_clk);
2802 
2803         priv->stmmac_rst = devm_reset_control_get(priv->device,
2804                                                   STMMAC_RESOURCE_NAME);
2805         if (IS_ERR(priv->stmmac_rst)) {
2806                 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
2807                         ret = -EPROBE_DEFER;
2808                         goto error_hw_init;
2809                 }
2810                 dev_info(priv->device, "no reset control found\n");
2811                 priv->stmmac_rst = NULL;
2812         }
2813         if (priv->stmmac_rst)
2814                 reset_control_deassert(priv->stmmac_rst);
2815 
2816         /* Init MAC and get the capabilities */
2817         ret = stmmac_hw_init(priv);
2818         if (ret)
2819                 goto error_hw_init;
2820 
2821         ndev->netdev_ops = &stmmac_netdev_ops;
2822 
2823         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2824                             NETIF_F_RXCSUM;
2825         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2826         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2827 #ifdef STMMAC_VLAN_TAG_USED
2828         /* Both mac100 and gmac support receive VLAN tag detection */
2829         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2830 #endif
2831         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2832 
2833         if (flow_ctrl)
2834                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
2835 
2836         /* Rx Watchdog is available in the COREs newer than the 3.40.
2837          * In some case, for example on bugged HW this feature
2838          * has to be disable and this can be done by passing the
2839          * riwt_off field from the platform.
2840          */
2841         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2842                 priv->use_riwt = 1;
2843                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2844         }
2845 
2846         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2847 
2848         spin_lock_init(&priv->lock);
2849         spin_lock_init(&priv->tx_lock);
2850 
2851         ret = register_netdev(ndev);
2852         if (ret) {
2853                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2854                 goto error_netdev_register;
2855         }
2856 
2857         /* If a specific clk_csr value is passed from the platform
2858          * this means that the CSR Clock Range selection cannot be
2859          * changed at run-time and it is fixed. Viceversa the driver'll try to
2860          * set the MDC clock dynamically according to the csr actual
2861          * clock input.
2862          */
2863         if (!priv->plat->clk_csr)
2864                 stmmac_clk_csr_set(priv);
2865         else
2866                 priv->clk_csr = priv->plat->clk_csr;
2867 
2868         stmmac_check_pcs_mode(priv);
2869 
2870         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2871             priv->pcs != STMMAC_PCS_RTBI) {
2872                 /* MDIO bus Registration */
2873                 ret = stmmac_mdio_register(ndev);
2874                 if (ret < 0) {
2875                         pr_debug("%s: MDIO bus (id: %d) registration failed",
2876                                  __func__, priv->plat->bus_id);
2877                         goto error_mdio_register;
2878                 }
2879         }
2880 
2881         return priv;
2882 
2883 error_mdio_register:
2884         unregister_netdev(ndev);
2885 error_netdev_register:
2886         netif_napi_del(&priv->napi);
2887 error_hw_init:
2888         clk_disable_unprepare(priv->stmmac_clk);
2889 error_clk_get:
2890         free_netdev(ndev);
2891 
2892         return ERR_PTR(ret);
2893 }
2894 
2895 /**
2896  * stmmac_dvr_remove
2897  * @ndev: net device pointer
2898  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2899  * changes the link status, releases the DMA descriptor rings.
2900  */
2901 int stmmac_dvr_remove(struct net_device *ndev)
2902 {
2903         struct stmmac_priv *priv = netdev_priv(ndev);
2904 
2905         pr_info("%s:\n\tremoving driver", __func__);
2906 
2907         priv->hw->dma->stop_rx(priv->ioaddr);
2908         priv->hw->dma->stop_tx(priv->ioaddr);
2909 
2910         stmmac_set_mac(priv->ioaddr, false);
2911         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2912             priv->pcs != STMMAC_PCS_RTBI)
2913                 stmmac_mdio_unregister(ndev);
2914         netif_carrier_off(ndev);
2915         unregister_netdev(ndev);
2916         if (priv->stmmac_rst)
2917                 reset_control_assert(priv->stmmac_rst);
2918         clk_disable_unprepare(priv->stmmac_clk);
2919         free_netdev(ndev);
2920 
2921         return 0;
2922 }
2923 
2924 #ifdef CONFIG_PM
2925 int stmmac_suspend(struct net_device *ndev)
2926 {
2927         struct stmmac_priv *priv = netdev_priv(ndev);
2928         unsigned long flags;
2929 
2930         if (!ndev || !netif_running(ndev))
2931                 return 0;
2932 
2933         if (priv->phydev)
2934                 phy_stop(priv->phydev);
2935 
2936         spin_lock_irqsave(&priv->lock, flags);
2937 
2938         netif_device_detach(ndev);
2939         netif_stop_queue(ndev);
2940 
2941         napi_disable(&priv->napi);
2942 
2943         /* Stop TX/RX DMA */
2944         priv->hw->dma->stop_tx(priv->ioaddr);
2945         priv->hw->dma->stop_rx(priv->ioaddr);
2946 
2947         stmmac_clear_descriptors(priv);
2948 
2949         /* Enable Power down mode by programming the PMT regs */
2950         if (device_may_wakeup(priv->device)) {
2951                 priv->hw->mac->pmt(priv->hw, priv->wolopts);
2952                 priv->irq_wake = 1;
2953         } else {
2954                 stmmac_set_mac(priv->ioaddr, false);
2955                 pinctrl_pm_select_sleep_state(priv->device);
2956                 /* Disable clock in case of PWM is off */
2957                 clk_disable(priv->stmmac_clk);
2958         }
2959         spin_unlock_irqrestore(&priv->lock, flags);
2960 
2961         priv->oldlink = 0;
2962         priv->speed = 0;
2963         priv->oldduplex = -1;
2964         return 0;
2965 }
2966 
2967 int stmmac_resume(struct net_device *ndev)
2968 {
2969         struct stmmac_priv *priv = netdev_priv(ndev);
2970         unsigned long flags;
2971 
2972         if (!netif_running(ndev))
2973                 return 0;
2974 
2975         spin_lock_irqsave(&priv->lock, flags);
2976 
2977         /* Power Down bit, into the PM register, is cleared
2978          * automatically as soon as a magic packet or a Wake-up frame
2979          * is received. Anyway, it's better to manually clear
2980          * this bit because it can generate problems while resuming
2981          * from another devices (e.g. serial console).
2982          */
2983         if (device_may_wakeup(priv->device)) {
2984                 priv->hw->mac->pmt(priv->hw, 0);
2985                 priv->irq_wake = 0;
2986         } else {
2987                 pinctrl_pm_select_default_state(priv->device);
2988                 /* enable the clk prevously disabled */
2989                 clk_enable(priv->stmmac_clk);
2990                 /* reset the phy so that it's ready */
2991                 if (priv->mii)
2992                         stmmac_mdio_reset(priv->mii);
2993         }
2994 
2995         netif_device_attach(ndev);
2996 
2997         init_dma_desc_rings(ndev, GFP_ATOMIC);
2998         stmmac_hw_setup(ndev);
2999         stmmac_init_tx_coalesce(priv);
3000 
3001         napi_enable(&priv->napi);
3002 
3003         netif_start_queue(ndev);
3004 
3005         spin_unlock_irqrestore(&priv->lock, flags);
3006 
3007         if (priv->phydev)
3008                 phy_start(priv->phydev);
3009 
3010         return 0;
3011 }
3012 #endif /* CONFIG_PM */
3013 
3014 /* Driver can be configured w/ and w/ both PCI and Platf drivers
3015  * depending on the configuration selected.
3016  */
3017 static int __init stmmac_init(void)
3018 {
3019         int ret;
3020 
3021         ret = stmmac_register_platform();
3022         if (ret)
3023                 goto err;
3024         ret = stmmac_register_pci();
3025         if (ret)
3026                 goto err_pci;
3027         return 0;
3028 err_pci:
3029         stmmac_unregister_platform();
3030 err:
3031         pr_err("stmmac: driver registration failed\n");
3032         return ret;
3033 }
3034 
3035 static void __exit stmmac_exit(void)
3036 {
3037         stmmac_unregister_platform();
3038         stmmac_unregister_pci();
3039 }
3040 
3041 module_init(stmmac_init);
3042 module_exit(stmmac_exit);
3043 
3044 #ifndef MODULE
3045 static int __init stmmac_cmdline_opt(char *str)
3046 {
3047         char *opt;
3048 
3049         if (!str || !*str)
3050                 return -EINVAL;
3051         while ((opt = strsep(&str, ",")) != NULL) {
3052                 if (!strncmp(opt, "debug:", 6)) {
3053                         if (kstrtoint(opt + 6, 0, &debug))
3054                                 goto err;
3055                 } else if (!strncmp(opt, "phyaddr:", 8)) {
3056                         if (kstrtoint(opt + 8, 0, &phyaddr))
3057                                 goto err;
3058                 } else if (!strncmp(opt, "dma_txsize:", 11)) {
3059                         if (kstrtoint(opt + 11, 0, &dma_txsize))
3060                                 goto err;
3061                 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
3062                         if (kstrtoint(opt + 11, 0, &dma_rxsize))
3063                                 goto err;
3064                 } else if (!strncmp(opt, "buf_sz:", 7)) {
3065                         if (kstrtoint(opt + 7, 0, &buf_sz))
3066                                 goto err;
3067                 } else if (!strncmp(opt, "tc:", 3)) {
3068                         if (kstrtoint(opt + 3, 0, &tc))
3069                                 goto err;
3070                 } else if (!strncmp(opt, "watchdog:", 9)) {
3071                         if (kstrtoint(opt + 9, 0, &watchdog))
3072                                 goto err;
3073                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
3074                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
3075                                 goto err;
3076                 } else if (!strncmp(opt, "pause:", 6)) {
3077                         if (kstrtoint(opt + 6, 0, &pause))
3078                                 goto err;
3079                 } else if (!strncmp(opt, "eee_timer:", 10)) {
3080                         if (kstrtoint(opt + 10, 0, &eee_timer))
3081                                 goto err;
3082                 } else if (!strncmp(opt, "chain_mode:", 11)) {
3083                         if (kstrtoint(opt + 11, 0, &chain_mode))
3084                                 goto err;
3085                 }
3086         }
3087         return 0;
3088 
3089 err:
3090         pr_err("%s: ERROR broken module parameter conversion", __func__);
3091         return -EINVAL;
3092 }
3093 
3094 __setup("stmmaceth=", stmmac_cmdline_opt);
3095 #endif /* MODULE */
3096 
3097 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3098 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3099 MODULE_LICENSE("GPL");
3100 

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