Version:  2.0.40 2.2.26 2.4.37 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9

Linux/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

  1 /*******************************************************************************
  2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
  3   ST Ethernet IPs are built around a Synopsys IP Core.
  4 
  5         Copyright(C) 2007-2011 STMicroelectronics Ltd
  6 
  7   This program is free software; you can redistribute it and/or modify it
  8   under the terms and conditions of the GNU General Public License,
  9   version 2, as published by the Free Software Foundation.
 10 
 11   This program is distributed in the hope it will be useful, but WITHOUT
 12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 14   more details.
 15 
 16   You should have received a copy of the GNU General Public License along with
 17   this program; if not, write to the Free Software Foundation, Inc.,
 18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 19 
 20   The full GNU General Public License is included in this distribution in
 21   the file called "COPYING".
 22 
 23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
 24 
 25   Documentation available at:
 26         http://www.stlinux.com
 27   Support available at:
 28         https://bugzilla.stlinux.com/
 29 *******************************************************************************/
 30 
 31 #include <linux/clk.h>
 32 #include <linux/kernel.h>
 33 #include <linux/interrupt.h>
 34 #include <linux/ip.h>
 35 #include <linux/tcp.h>
 36 #include <linux/skbuff.h>
 37 #include <linux/ethtool.h>
 38 #include <linux/if_ether.h>
 39 #include <linux/crc32.h>
 40 #include <linux/mii.h>
 41 #include <linux/if.h>
 42 #include <linux/if_vlan.h>
 43 #include <linux/dma-mapping.h>
 44 #include <linux/slab.h>
 45 #include <linux/prefetch.h>
 46 #include <linux/pinctrl/consumer.h>
 47 #ifdef CONFIG_DEBUG_FS
 48 #include <linux/debugfs.h>
 49 #include <linux/seq_file.h>
 50 #endif /* CONFIG_DEBUG_FS */
 51 #include <linux/net_tstamp.h>
 52 #include "stmmac_ptp.h"
 53 #include "stmmac.h"
 54 #include <linux/reset.h>
 55 #include <linux/of_mdio.h>
 56 #include "dwmac1000.h"
 57 
 58 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
 59 #define TSO_MAX_BUFF_SIZE       (SZ_16K - 1)
 60 
 61 /* Module parameters */
 62 #define TX_TIMEO        5000
 63 static int watchdog = TX_TIMEO;
 64 module_param(watchdog, int, S_IRUGO | S_IWUSR);
 65 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
 66 
 67 static int debug = -1;
 68 module_param(debug, int, S_IRUGO | S_IWUSR);
 69 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
 70 
 71 static int phyaddr = -1;
 72 module_param(phyaddr, int, S_IRUGO);
 73 MODULE_PARM_DESC(phyaddr, "Physical device address");
 74 
 75 #define STMMAC_TX_THRESH        (DMA_TX_SIZE / 4)
 76 #define STMMAC_RX_THRESH        (DMA_RX_SIZE / 4)
 77 
 78 static int flow_ctrl = FLOW_OFF;
 79 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
 80 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
 81 
 82 static int pause = PAUSE_TIME;
 83 module_param(pause, int, S_IRUGO | S_IWUSR);
 84 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
 85 
 86 #define TC_DEFAULT 64
 87 static int tc = TC_DEFAULT;
 88 module_param(tc, int, S_IRUGO | S_IWUSR);
 89 MODULE_PARM_DESC(tc, "DMA threshold control value");
 90 
 91 #define DEFAULT_BUFSIZE 1536
 92 static int buf_sz = DEFAULT_BUFSIZE;
 93 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
 94 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
 95 
 96 #define STMMAC_RX_COPYBREAK     256
 97 
 98 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 99                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
100                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
101 
102 #define STMMAC_DEFAULT_LPI_TIMER        1000
103 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
104 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
105 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
106 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
107 
108 /* By default the driver will use the ring mode to manage tx and rx descriptors
109  * but passing this value so user can force to use the chain instead of the ring
110  */
111 static unsigned int chain_mode;
112 module_param(chain_mode, int, S_IRUGO);
113 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
114 
115 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
116 
117 #ifdef CONFIG_DEBUG_FS
118 static int stmmac_init_fs(struct net_device *dev);
119 static void stmmac_exit_fs(struct net_device *dev);
120 #endif
121 
122 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
123 
124 /**
125  * stmmac_verify_args - verify the driver parameters.
126  * Description: it checks the driver parameters and set a default in case of
127  * errors.
128  */
129 static void stmmac_verify_args(void)
130 {
131         if (unlikely(watchdog < 0))
132                 watchdog = TX_TIMEO;
133         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
134                 buf_sz = DEFAULT_BUFSIZE;
135         if (unlikely(flow_ctrl > 1))
136                 flow_ctrl = FLOW_AUTO;
137         else if (likely(flow_ctrl < 0))
138                 flow_ctrl = FLOW_OFF;
139         if (unlikely((pause < 0) || (pause > 0xffff)))
140                 pause = PAUSE_TIME;
141         if (eee_timer < 0)
142                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
143 }
144 
145 /**
146  * stmmac_clk_csr_set - dynamically set the MDC clock
147  * @priv: driver private structure
148  * Description: this is to dynamically set the MDC clock according to the csr
149  * clock input.
150  * Note:
151  *      If a specific clk_csr value is passed from the platform
152  *      this means that the CSR Clock Range selection cannot be
153  *      changed at run-time and it is fixed (as reported in the driver
154  *      documentation). Viceversa the driver will try to set the MDC
155  *      clock dynamically according to the actual clock input.
156  */
157 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
158 {
159         u32 clk_rate;
160 
161         clk_rate = clk_get_rate(priv->stmmac_clk);
162 
163         /* Platform provided default clk_csr would be assumed valid
164          * for all other cases except for the below mentioned ones.
165          * For values higher than the IEEE 802.3 specified frequency
166          * we can not estimate the proper divider as it is not known
167          * the frequency of clk_csr_i. So we do not change the default
168          * divider.
169          */
170         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
171                 if (clk_rate < CSR_F_35M)
172                         priv->clk_csr = STMMAC_CSR_20_35M;
173                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
174                         priv->clk_csr = STMMAC_CSR_35_60M;
175                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
176                         priv->clk_csr = STMMAC_CSR_60_100M;
177                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
178                         priv->clk_csr = STMMAC_CSR_100_150M;
179                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
180                         priv->clk_csr = STMMAC_CSR_150_250M;
181                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
182                         priv->clk_csr = STMMAC_CSR_250_300M;
183         }
184 }
185 
186 static void print_pkt(unsigned char *buf, int len)
187 {
188         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
189         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
190 }
191 
192 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
193 {
194         unsigned avail;
195 
196         if (priv->dirty_tx > priv->cur_tx)
197                 avail = priv->dirty_tx - priv->cur_tx - 1;
198         else
199                 avail = DMA_TX_SIZE - priv->cur_tx + priv->dirty_tx - 1;
200 
201         return avail;
202 }
203 
204 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv)
205 {
206         unsigned dirty;
207 
208         if (priv->dirty_rx <= priv->cur_rx)
209                 dirty = priv->cur_rx - priv->dirty_rx;
210         else
211                 dirty = DMA_RX_SIZE - priv->dirty_rx + priv->cur_rx;
212 
213         return dirty;
214 }
215 
216 /**
217  * stmmac_hw_fix_mac_speed - callback for speed selection
218  * @priv: driver private structure
219  * Description: on some platforms (e.g. ST), some HW system configuraton
220  * registers have to be set according to the link speed negotiated.
221  */
222 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
223 {
224         struct phy_device *phydev = priv->phydev;
225 
226         if (likely(priv->plat->fix_mac_speed))
227                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
228 }
229 
230 /**
231  * stmmac_enable_eee_mode - check and enter in LPI mode
232  * @priv: driver private structure
233  * Description: this function is to verify and enter in LPI mode in case of
234  * EEE.
235  */
236 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
237 {
238         /* Check and enter in LPI mode */
239         if ((priv->dirty_tx == priv->cur_tx) &&
240             (priv->tx_path_in_lpi_mode == false))
241                 priv->hw->mac->set_eee_mode(priv->hw);
242 }
243 
244 /**
245  * stmmac_disable_eee_mode - disable and exit from LPI mode
246  * @priv: driver private structure
247  * Description: this function is to exit and disable EEE in case of
248  * LPI state is true. This is called by the xmit.
249  */
250 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
251 {
252         priv->hw->mac->reset_eee_mode(priv->hw);
253         del_timer_sync(&priv->eee_ctrl_timer);
254         priv->tx_path_in_lpi_mode = false;
255 }
256 
257 /**
258  * stmmac_eee_ctrl_timer - EEE TX SW timer.
259  * @arg : data hook
260  * Description:
261  *  if there is no data transfer and if we are not in LPI state,
262  *  then MAC Transmitter can be moved to LPI state.
263  */
264 static void stmmac_eee_ctrl_timer(unsigned long arg)
265 {
266         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
267 
268         stmmac_enable_eee_mode(priv);
269         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
270 }
271 
272 /**
273  * stmmac_eee_init - init EEE
274  * @priv: driver private structure
275  * Description:
276  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
277  *  can also manage EEE, this function enable the LPI state and start related
278  *  timer.
279  */
280 bool stmmac_eee_init(struct stmmac_priv *priv)
281 {
282         unsigned long flags;
283         bool ret = false;
284 
285         /* Using PCS we cannot dial with the phy registers at this stage
286          * so we do not support extra feature like EEE.
287          */
288         if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
289             (priv->hw->pcs == STMMAC_PCS_TBI) ||
290             (priv->hw->pcs == STMMAC_PCS_RTBI))
291                 goto out;
292 
293         /* MAC core supports the EEE feature. */
294         if (priv->dma_cap.eee) {
295                 int tx_lpi_timer = priv->tx_lpi_timer;
296 
297                 /* Check if the PHY supports EEE */
298                 if (phy_init_eee(priv->phydev, 1)) {
299                         /* To manage at run-time if the EEE cannot be supported
300                          * anymore (for example because the lp caps have been
301                          * changed).
302                          * In that case the driver disable own timers.
303                          */
304                         spin_lock_irqsave(&priv->lock, flags);
305                         if (priv->eee_active) {
306                                 pr_debug("stmmac: disable EEE\n");
307                                 del_timer_sync(&priv->eee_ctrl_timer);
308                                 priv->hw->mac->set_eee_timer(priv->hw, 0,
309                                                              tx_lpi_timer);
310                         }
311                         priv->eee_active = 0;
312                         spin_unlock_irqrestore(&priv->lock, flags);
313                         goto out;
314                 }
315                 /* Activate the EEE and start timers */
316                 spin_lock_irqsave(&priv->lock, flags);
317                 if (!priv->eee_active) {
318                         priv->eee_active = 1;
319                         setup_timer(&priv->eee_ctrl_timer,
320                                     stmmac_eee_ctrl_timer,
321                                     (unsigned long)priv);
322                         mod_timer(&priv->eee_ctrl_timer,
323                                   STMMAC_LPI_T(eee_timer));
324 
325                         priv->hw->mac->set_eee_timer(priv->hw,
326                                                      STMMAC_DEFAULT_LIT_LS,
327                                                      tx_lpi_timer);
328                 }
329                 /* Set HW EEE according to the speed */
330                 priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link);
331 
332                 ret = true;
333                 spin_unlock_irqrestore(&priv->lock, flags);
334 
335                 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
336         }
337 out:
338         return ret;
339 }
340 
341 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
342  * @priv: driver private structure
343  * @p : descriptor pointer
344  * @skb : the socket buffer
345  * Description :
346  * This function will read timestamp from the descriptor & pass it to stack.
347  * and also perform some sanity checks.
348  */
349 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
350                                    struct dma_desc *p, struct sk_buff *skb)
351 {
352         struct skb_shared_hwtstamps shhwtstamp;
353         u64 ns;
354 
355         if (!priv->hwts_tx_en)
356                 return;
357 
358         /* exit if skb doesn't support hw tstamp */
359         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
360                 return;
361 
362         /* check tx tstamp status */
363         if (!priv->hw->desc->get_tx_timestamp_status(p)) {
364                 /* get the valid tstamp */
365                 ns = priv->hw->desc->get_timestamp(p, priv->adv_ts);
366 
367                 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
368                 shhwtstamp.hwtstamp = ns_to_ktime(ns);
369 
370                 netdev_info(priv->dev, "get valid TX hw timestamp %llu\n", ns);
371                 /* pass tstamp to stack */
372                 skb_tstamp_tx(skb, &shhwtstamp);
373         }
374 
375         return;
376 }
377 
378 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
379  * @priv: driver private structure
380  * @p : descriptor pointer
381  * @np : next descriptor pointer
382  * @skb : the socket buffer
383  * Description :
384  * This function will read received packet's timestamp from the descriptor
385  * and pass it to stack. It also perform some sanity checks.
386  */
387 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
388                                    struct dma_desc *np, struct sk_buff *skb)
389 {
390         struct skb_shared_hwtstamps *shhwtstamp = NULL;
391         u64 ns;
392 
393         if (!priv->hwts_rx_en)
394                 return;
395 
396         /* Check if timestamp is available */
397         if (!priv->hw->desc->get_rx_timestamp_status(p, priv->adv_ts)) {
398                 /* For GMAC4, the valid timestamp is from CTX next desc. */
399                 if (priv->plat->has_gmac4)
400                         ns = priv->hw->desc->get_timestamp(np, priv->adv_ts);
401                 else
402                         ns = priv->hw->desc->get_timestamp(p, priv->adv_ts);
403 
404                 netdev_info(priv->dev, "get valid RX hw timestamp %llu\n", ns);
405                 shhwtstamp = skb_hwtstamps(skb);
406                 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
407                 shhwtstamp->hwtstamp = ns_to_ktime(ns);
408         } else  {
409                 netdev_err(priv->dev, "cannot get RX hw timestamp\n");
410         }
411 }
412 
413 /**
414  *  stmmac_hwtstamp_ioctl - control hardware timestamping.
415  *  @dev: device pointer.
416  *  @ifr: An IOCTL specefic structure, that can contain a pointer to
417  *  a proprietary structure used to pass information to the driver.
418  *  Description:
419  *  This function configures the MAC to enable/disable both outgoing(TX)
420  *  and incoming(RX) packets time stamping based on user input.
421  *  Return Value:
422  *  0 on success and an appropriate -ve integer on failure.
423  */
424 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
425 {
426         struct stmmac_priv *priv = netdev_priv(dev);
427         struct hwtstamp_config config;
428         struct timespec64 now;
429         u64 temp = 0;
430         u32 ptp_v2 = 0;
431         u32 tstamp_all = 0;
432         u32 ptp_over_ipv4_udp = 0;
433         u32 ptp_over_ipv6_udp = 0;
434         u32 ptp_over_ethernet = 0;
435         u32 snap_type_sel = 0;
436         u32 ts_master_en = 0;
437         u32 ts_event_en = 0;
438         u32 value = 0;
439         u32 sec_inc;
440 
441         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
442                 netdev_alert(priv->dev, "No support for HW time stamping\n");
443                 priv->hwts_tx_en = 0;
444                 priv->hwts_rx_en = 0;
445 
446                 return -EOPNOTSUPP;
447         }
448 
449         if (copy_from_user(&config, ifr->ifr_data,
450                            sizeof(struct hwtstamp_config)))
451                 return -EFAULT;
452 
453         pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
454                  __func__, config.flags, config.tx_type, config.rx_filter);
455 
456         /* reserved for future extensions */
457         if (config.flags)
458                 return -EINVAL;
459 
460         if (config.tx_type != HWTSTAMP_TX_OFF &&
461             config.tx_type != HWTSTAMP_TX_ON)
462                 return -ERANGE;
463 
464         if (priv->adv_ts) {
465                 switch (config.rx_filter) {
466                 case HWTSTAMP_FILTER_NONE:
467                         /* time stamp no incoming packet at all */
468                         config.rx_filter = HWTSTAMP_FILTER_NONE;
469                         break;
470 
471                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
472                         /* PTP v1, UDP, any kind of event packet */
473                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
474                         /* take time stamp for all event messages */
475                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
476 
477                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
478                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
479                         break;
480 
481                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
482                         /* PTP v1, UDP, Sync packet */
483                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
484                         /* take time stamp for SYNC messages only */
485                         ts_event_en = PTP_TCR_TSEVNTENA;
486 
487                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
488                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
489                         break;
490 
491                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
492                         /* PTP v1, UDP, Delay_req packet */
493                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
494                         /* take time stamp for Delay_Req messages only */
495                         ts_master_en = PTP_TCR_TSMSTRENA;
496                         ts_event_en = PTP_TCR_TSEVNTENA;
497 
498                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
499                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
500                         break;
501 
502                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
503                         /* PTP v2, UDP, any kind of event packet */
504                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
505                         ptp_v2 = PTP_TCR_TSVER2ENA;
506                         /* take time stamp for all event messages */
507                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
508 
509                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
510                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
511                         break;
512 
513                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
514                         /* PTP v2, UDP, Sync packet */
515                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
516                         ptp_v2 = PTP_TCR_TSVER2ENA;
517                         /* take time stamp for SYNC messages only */
518                         ts_event_en = PTP_TCR_TSEVNTENA;
519 
520                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
521                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
522                         break;
523 
524                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
525                         /* PTP v2, UDP, Delay_req packet */
526                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
527                         ptp_v2 = PTP_TCR_TSVER2ENA;
528                         /* take time stamp for Delay_Req messages only */
529                         ts_master_en = PTP_TCR_TSMSTRENA;
530                         ts_event_en = PTP_TCR_TSEVNTENA;
531 
532                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
533                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
534                         break;
535 
536                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
537                         /* PTP v2/802.AS1 any layer, any kind of event packet */
538                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
539                         ptp_v2 = PTP_TCR_TSVER2ENA;
540                         /* take time stamp for all event messages */
541                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
542 
543                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
544                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
545                         ptp_over_ethernet = PTP_TCR_TSIPENA;
546                         break;
547 
548                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
549                         /* PTP v2/802.AS1, any layer, Sync packet */
550                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
551                         ptp_v2 = PTP_TCR_TSVER2ENA;
552                         /* take time stamp for SYNC messages only */
553                         ts_event_en = PTP_TCR_TSEVNTENA;
554 
555                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
556                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
557                         ptp_over_ethernet = PTP_TCR_TSIPENA;
558                         break;
559 
560                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
561                         /* PTP v2/802.AS1, any layer, Delay_req packet */
562                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
563                         ptp_v2 = PTP_TCR_TSVER2ENA;
564                         /* take time stamp for Delay_Req messages only */
565                         ts_master_en = PTP_TCR_TSMSTRENA;
566                         ts_event_en = PTP_TCR_TSEVNTENA;
567 
568                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
569                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
570                         ptp_over_ethernet = PTP_TCR_TSIPENA;
571                         break;
572 
573                 case HWTSTAMP_FILTER_ALL:
574                         /* time stamp any incoming packet */
575                         config.rx_filter = HWTSTAMP_FILTER_ALL;
576                         tstamp_all = PTP_TCR_TSENALL;
577                         break;
578 
579                 default:
580                         return -ERANGE;
581                 }
582         } else {
583                 switch (config.rx_filter) {
584                 case HWTSTAMP_FILTER_NONE:
585                         config.rx_filter = HWTSTAMP_FILTER_NONE;
586                         break;
587                 default:
588                         /* PTP v1, UDP, any kind of event packet */
589                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
590                         break;
591                 }
592         }
593         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
594         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
595 
596         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
597                 priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, 0);
598         else {
599                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
600                          tstamp_all | ptp_v2 | ptp_over_ethernet |
601                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
602                          ts_master_en | snap_type_sel);
603                 priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, value);
604 
605                 /* program Sub Second Increment reg */
606                 sec_inc = priv->hw->ptp->config_sub_second_increment(
607                         priv->ptpaddr, priv->clk_ptp_rate,
608                         priv->plat->has_gmac4);
609                 temp = div_u64(1000000000ULL, sec_inc);
610 
611                 /* calculate default added value:
612                  * formula is :
613                  * addend = (2^32)/freq_div_ratio;
614                  * where, freq_div_ratio = 1e9ns/sec_inc
615                  */
616                 temp = (u64)(temp << 32);
617                 priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
618                 priv->hw->ptp->config_addend(priv->ptpaddr,
619                                              priv->default_addend);
620 
621                 /* initialize system time */
622                 ktime_get_real_ts64(&now);
623 
624                 /* lower 32 bits of tv_sec are safe until y2106 */
625                 priv->hw->ptp->init_systime(priv->ptpaddr, (u32)now.tv_sec,
626                                             now.tv_nsec);
627         }
628 
629         return copy_to_user(ifr->ifr_data, &config,
630                             sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
631 }
632 
633 /**
634  * stmmac_init_ptp - init PTP
635  * @priv: driver private structure
636  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
637  * This is done by looking at the HW cap. register.
638  * This function also registers the ptp driver.
639  */
640 static int stmmac_init_ptp(struct stmmac_priv *priv)
641 {
642         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
643                 return -EOPNOTSUPP;
644 
645         /* Fall-back to main clock in case of no PTP ref is passed */
646         priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref");
647         if (IS_ERR(priv->clk_ptp_ref)) {
648                 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk);
649                 priv->clk_ptp_ref = NULL;
650                 netdev_dbg(priv->dev, "PTP uses main clock\n");
651         } else {
652                 clk_prepare_enable(priv->clk_ptp_ref);
653                 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref);
654                 netdev_dbg(priv->dev, "PTP rate %d\n", priv->clk_ptp_rate);
655         }
656 
657         priv->adv_ts = 0;
658         /* Check if adv_ts can be enabled for dwmac 4.x core */
659         if (priv->plat->has_gmac4 && priv->dma_cap.atime_stamp)
660                 priv->adv_ts = 1;
661         /* Dwmac 3.x core with extend_desc can support adv_ts */
662         else if (priv->extend_desc && priv->dma_cap.atime_stamp)
663                 priv->adv_ts = 1;
664 
665         if (priv->dma_cap.time_stamp)
666                 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
667 
668         if (priv->adv_ts)
669                 netdev_info(priv->dev,
670                             "IEEE 1588-2008 Advanced Timestamp supported\n");
671 
672         priv->hw->ptp = &stmmac_ptp;
673         priv->hwts_tx_en = 0;
674         priv->hwts_rx_en = 0;
675 
676         stmmac_ptp_register(priv);
677 
678         return 0;
679 }
680 
681 static void stmmac_release_ptp(struct stmmac_priv *priv)
682 {
683         if (priv->clk_ptp_ref)
684                 clk_disable_unprepare(priv->clk_ptp_ref);
685         stmmac_ptp_unregister(priv);
686 }
687 
688 /**
689  * stmmac_adjust_link - adjusts the link parameters
690  * @dev: net device structure
691  * Description: this is the helper called by the physical abstraction layer
692  * drivers to communicate the phy link status. According the speed and duplex
693  * this driver can invoke registered glue-logic as well.
694  * It also invoke the eee initialization because it could happen when switch
695  * on different networks (that are eee capable).
696  */
697 static void stmmac_adjust_link(struct net_device *dev)
698 {
699         struct stmmac_priv *priv = netdev_priv(dev);
700         struct phy_device *phydev = priv->phydev;
701         unsigned long flags;
702         int new_state = 0;
703         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
704 
705         if (phydev == NULL)
706                 return;
707 
708         spin_lock_irqsave(&priv->lock, flags);
709 
710         if (phydev->link) {
711                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
712 
713                 /* Now we make sure that we can be in full duplex mode.
714                  * If not, we operate in half-duplex mode. */
715                 if (phydev->duplex != priv->oldduplex) {
716                         new_state = 1;
717                         if (!(phydev->duplex))
718                                 ctrl &= ~priv->hw->link.duplex;
719                         else
720                                 ctrl |= priv->hw->link.duplex;
721                         priv->oldduplex = phydev->duplex;
722                 }
723                 /* Flow Control operation */
724                 if (phydev->pause)
725                         priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex,
726                                                  fc, pause_time);
727 
728                 if (phydev->speed != priv->speed) {
729                         new_state = 1;
730                         switch (phydev->speed) {
731                         case 1000:
732                                 if (likely((priv->plat->has_gmac) ||
733                                            (priv->plat->has_gmac4)))
734                                         ctrl &= ~priv->hw->link.port;
735                                 stmmac_hw_fix_mac_speed(priv);
736                                 break;
737                         case 100:
738                         case 10:
739                                 if (likely((priv->plat->has_gmac) ||
740                                            (priv->plat->has_gmac4))) {
741                                         ctrl |= priv->hw->link.port;
742                                         if (phydev->speed == SPEED_100) {
743                                                 ctrl |= priv->hw->link.speed;
744                                         } else {
745                                                 ctrl &= ~(priv->hw->link.speed);
746                                         }
747                                 } else {
748                                         ctrl &= ~priv->hw->link.port;
749                                 }
750                                 stmmac_hw_fix_mac_speed(priv);
751                                 break;
752                         default:
753                                 if (netif_msg_link(priv))
754                                         pr_warn("%s: Speed (%d) not 10/100\n",
755                                                 dev->name, phydev->speed);
756                                 break;
757                         }
758 
759                         priv->speed = phydev->speed;
760                 }
761 
762                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
763 
764                 if (!priv->oldlink) {
765                         new_state = 1;
766                         priv->oldlink = 1;
767                 }
768         } else if (priv->oldlink) {
769                 new_state = 1;
770                 priv->oldlink = 0;
771                 priv->speed = 0;
772                 priv->oldduplex = -1;
773         }
774 
775         if (new_state && netif_msg_link(priv))
776                 phy_print_status(phydev);
777 
778         spin_unlock_irqrestore(&priv->lock, flags);
779 
780         if (phydev->is_pseudo_fixed_link)
781                 /* Stop PHY layer to call the hook to adjust the link in case
782                  * of a switch is attached to the stmmac driver.
783                  */
784                 phydev->irq = PHY_IGNORE_INTERRUPT;
785         else
786                 /* At this stage, init the EEE if supported.
787                  * Never called in case of fixed_link.
788                  */
789                 priv->eee_enabled = stmmac_eee_init(priv);
790 }
791 
792 /**
793  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
794  * @priv: driver private structure
795  * Description: this is to verify if the HW supports the PCS.
796  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
797  * configured for the TBI, RTBI, or SGMII PHY interface.
798  */
799 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
800 {
801         int interface = priv->plat->interface;
802 
803         if (priv->dma_cap.pcs) {
804                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
805                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
806                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
807                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
808                         pr_debug("STMMAC: PCS RGMII support enable\n");
809                         priv->hw->pcs = STMMAC_PCS_RGMII;
810                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
811                         pr_debug("STMMAC: PCS SGMII support enable\n");
812                         priv->hw->pcs = STMMAC_PCS_SGMII;
813                 }
814         }
815 }
816 
817 /**
818  * stmmac_init_phy - PHY initialization
819  * @dev: net device structure
820  * Description: it initializes the driver's PHY state, and attaches the PHY
821  * to the mac driver.
822  *  Return value:
823  *  0 on success
824  */
825 static int stmmac_init_phy(struct net_device *dev)
826 {
827         struct stmmac_priv *priv = netdev_priv(dev);
828         struct phy_device *phydev;
829         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
830         char bus_id[MII_BUS_ID_SIZE];
831         int interface = priv->plat->interface;
832         int max_speed = priv->plat->max_speed;
833         priv->oldlink = 0;
834         priv->speed = 0;
835         priv->oldduplex = -1;
836 
837         if (priv->plat->phy_node) {
838                 phydev = of_phy_connect(dev, priv->plat->phy_node,
839                                         &stmmac_adjust_link, 0, interface);
840         } else {
841                 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
842                          priv->plat->bus_id);
843 
844                 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
845                          priv->plat->phy_addr);
846                 pr_debug("stmmac_init_phy:  trying to attach to %s\n",
847                          phy_id_fmt);
848 
849                 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
850                                      interface);
851         }
852 
853         if (IS_ERR_OR_NULL(phydev)) {
854                 pr_err("%s: Could not attach to PHY\n", dev->name);
855                 if (!phydev)
856                         return -ENODEV;
857 
858                 return PTR_ERR(phydev);
859         }
860 
861         /* Stop Advertising 1000BASE Capability if interface is not GMII */
862         if ((interface == PHY_INTERFACE_MODE_MII) ||
863             (interface == PHY_INTERFACE_MODE_RMII) ||
864                 (max_speed < 1000 && max_speed > 0))
865                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
866                                          SUPPORTED_1000baseT_Full);
867 
868         /*
869          * Broken HW is sometimes missing the pull-up resistor on the
870          * MDIO line, which results in reads to non-existent devices returning
871          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
872          * device as well.
873          * Note: phydev->phy_id is the result of reading the UID PHY registers.
874          */
875         if (!priv->plat->phy_node && phydev->phy_id == 0) {
876                 phy_disconnect(phydev);
877                 return -ENODEV;
878         }
879 
880         /* stmmac_adjust_link will change this to PHY_IGNORE_INTERRUPT to avoid
881          * subsequent PHY polling, make sure we force a link transition if
882          * we have a UP/DOWN/UP transition
883          */
884         if (phydev->is_pseudo_fixed_link)
885                 phydev->irq = PHY_POLL;
886 
887         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
888                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
889 
890         priv->phydev = phydev;
891 
892         return 0;
893 }
894 
895 static void stmmac_display_rings(struct stmmac_priv *priv)
896 {
897         void *head_rx, *head_tx;
898 
899         if (priv->extend_desc) {
900                 head_rx = (void *)priv->dma_erx;
901                 head_tx = (void *)priv->dma_etx;
902         } else {
903                 head_rx = (void *)priv->dma_rx;
904                 head_tx = (void *)priv->dma_tx;
905         }
906 
907         /* Display Rx ring */
908         priv->hw->desc->display_ring(head_rx, DMA_RX_SIZE, true);
909         /* Display Tx ring */
910         priv->hw->desc->display_ring(head_tx, DMA_TX_SIZE, false);
911 }
912 
913 static int stmmac_set_bfsize(int mtu, int bufsize)
914 {
915         int ret = bufsize;
916 
917         if (mtu >= BUF_SIZE_4KiB)
918                 ret = BUF_SIZE_8KiB;
919         else if (mtu >= BUF_SIZE_2KiB)
920                 ret = BUF_SIZE_4KiB;
921         else if (mtu > DEFAULT_BUFSIZE)
922                 ret = BUF_SIZE_2KiB;
923         else
924                 ret = DEFAULT_BUFSIZE;
925 
926         return ret;
927 }
928 
929 /**
930  * stmmac_clear_descriptors - clear descriptors
931  * @priv: driver private structure
932  * Description: this function is called to clear the tx and rx descriptors
933  * in case of both basic and extended descriptors are used.
934  */
935 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
936 {
937         int i;
938 
939         /* Clear the Rx/Tx descriptors */
940         for (i = 0; i < DMA_RX_SIZE; i++)
941                 if (priv->extend_desc)
942                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
943                                                      priv->use_riwt, priv->mode,
944                                                      (i == DMA_RX_SIZE - 1));
945                 else
946                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
947                                                      priv->use_riwt, priv->mode,
948                                                      (i == DMA_RX_SIZE - 1));
949         for (i = 0; i < DMA_TX_SIZE; i++)
950                 if (priv->extend_desc)
951                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
952                                                      priv->mode,
953                                                      (i == DMA_TX_SIZE - 1));
954                 else
955                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
956                                                      priv->mode,
957                                                      (i == DMA_TX_SIZE - 1));
958 }
959 
960 /**
961  * stmmac_init_rx_buffers - init the RX descriptor buffer.
962  * @priv: driver private structure
963  * @p: descriptor pointer
964  * @i: descriptor index
965  * @flags: gfp flag.
966  * Description: this function is called to allocate a receive buffer, perform
967  * the DMA mapping and init the descriptor.
968  */
969 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
970                                   int i, gfp_t flags)
971 {
972         struct sk_buff *skb;
973 
974         skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
975         if (!skb) {
976                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
977                 return -ENOMEM;
978         }
979         priv->rx_skbuff[i] = skb;
980         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
981                                                 priv->dma_buf_sz,
982                                                 DMA_FROM_DEVICE);
983         if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
984                 pr_err("%s: DMA mapping error\n", __func__);
985                 dev_kfree_skb_any(skb);
986                 return -EINVAL;
987         }
988 
989         if (priv->synopsys_id >= DWMAC_CORE_4_00)
990                 p->des0 = priv->rx_skbuff_dma[i];
991         else
992                 p->des2 = priv->rx_skbuff_dma[i];
993 
994         if ((priv->hw->mode->init_desc3) &&
995             (priv->dma_buf_sz == BUF_SIZE_16KiB))
996                 priv->hw->mode->init_desc3(p);
997 
998         return 0;
999 }
1000 
1001 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
1002 {
1003         if (priv->rx_skbuff[i]) {
1004                 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1005                                  priv->dma_buf_sz, DMA_FROM_DEVICE);
1006                 dev_kfree_skb_any(priv->rx_skbuff[i]);
1007         }
1008         priv->rx_skbuff[i] = NULL;
1009 }
1010 
1011 /**
1012  * init_dma_desc_rings - init the RX/TX descriptor rings
1013  * @dev: net device structure
1014  * @flags: gfp flag.
1015  * Description: this function initializes the DMA RX/TX descriptors
1016  * and allocates the socket buffers. It suppors the chained and ring
1017  * modes.
1018  */
1019 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1020 {
1021         int i;
1022         struct stmmac_priv *priv = netdev_priv(dev);
1023         unsigned int bfsize = 0;
1024         int ret = -ENOMEM;
1025 
1026         if (priv->hw->mode->set_16kib_bfsize)
1027                 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1028 
1029         if (bfsize < BUF_SIZE_16KiB)
1030                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1031 
1032         priv->dma_buf_sz = bfsize;
1033 
1034         if (netif_msg_probe(priv)) {
1035                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1036                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1037 
1038                 /* RX INITIALIZATION */
1039                 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1040         }
1041         for (i = 0; i < DMA_RX_SIZE; i++) {
1042                 struct dma_desc *p;
1043                 if (priv->extend_desc)
1044                         p = &((priv->dma_erx + i)->basic);
1045                 else
1046                         p = priv->dma_rx + i;
1047 
1048                 ret = stmmac_init_rx_buffers(priv, p, i, flags);
1049                 if (ret)
1050                         goto err_init_rx_buffers;
1051 
1052                 if (netif_msg_probe(priv))
1053                         pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1054                                  priv->rx_skbuff[i]->data,
1055                                  (unsigned int)priv->rx_skbuff_dma[i]);
1056         }
1057         priv->cur_rx = 0;
1058         priv->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1059         buf_sz = bfsize;
1060 
1061         /* Setup the chained descriptor addresses */
1062         if (priv->mode == STMMAC_CHAIN_MODE) {
1063                 if (priv->extend_desc) {
1064                         priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1065                                              DMA_RX_SIZE, 1);
1066                         priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1067                                              DMA_TX_SIZE, 1);
1068                 } else {
1069                         priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1070                                              DMA_RX_SIZE, 0);
1071                         priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1072                                              DMA_TX_SIZE, 0);
1073                 }
1074         }
1075 
1076         /* TX INITIALIZATION */
1077         for (i = 0; i < DMA_TX_SIZE; i++) {
1078                 struct dma_desc *p;
1079                 if (priv->extend_desc)
1080                         p = &((priv->dma_etx + i)->basic);
1081                 else
1082                         p = priv->dma_tx + i;
1083 
1084                 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1085                         p->des0 = 0;
1086                         p->des1 = 0;
1087                         p->des2 = 0;
1088                         p->des3 = 0;
1089                 } else {
1090                         p->des2 = 0;
1091                 }
1092 
1093                 priv->tx_skbuff_dma[i].buf = 0;
1094                 priv->tx_skbuff_dma[i].map_as_page = false;
1095                 priv->tx_skbuff_dma[i].len = 0;
1096                 priv->tx_skbuff_dma[i].last_segment = false;
1097                 priv->tx_skbuff[i] = NULL;
1098         }
1099 
1100         priv->dirty_tx = 0;
1101         priv->cur_tx = 0;
1102         netdev_reset_queue(priv->dev);
1103 
1104         stmmac_clear_descriptors(priv);
1105 
1106         if (netif_msg_hw(priv))
1107                 stmmac_display_rings(priv);
1108 
1109         return 0;
1110 err_init_rx_buffers:
1111         while (--i >= 0)
1112                 stmmac_free_rx_buffers(priv, i);
1113         return ret;
1114 }
1115 
1116 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1117 {
1118         int i;
1119 
1120         for (i = 0; i < DMA_RX_SIZE; i++)
1121                 stmmac_free_rx_buffers(priv, i);
1122 }
1123 
1124 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1125 {
1126         int i;
1127 
1128         for (i = 0; i < DMA_TX_SIZE; i++) {
1129                 struct dma_desc *p;
1130 
1131                 if (priv->extend_desc)
1132                         p = &((priv->dma_etx + i)->basic);
1133                 else
1134                         p = priv->dma_tx + i;
1135 
1136                 if (priv->tx_skbuff_dma[i].buf) {
1137                         if (priv->tx_skbuff_dma[i].map_as_page)
1138                                 dma_unmap_page(priv->device,
1139                                                priv->tx_skbuff_dma[i].buf,
1140                                                priv->tx_skbuff_dma[i].len,
1141                                                DMA_TO_DEVICE);
1142                         else
1143                                 dma_unmap_single(priv->device,
1144                                                  priv->tx_skbuff_dma[i].buf,
1145                                                  priv->tx_skbuff_dma[i].len,
1146                                                  DMA_TO_DEVICE);
1147                 }
1148 
1149                 if (priv->tx_skbuff[i] != NULL) {
1150                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1151                         priv->tx_skbuff[i] = NULL;
1152                         priv->tx_skbuff_dma[i].buf = 0;
1153                         priv->tx_skbuff_dma[i].map_as_page = false;
1154                 }
1155         }
1156 }
1157 
1158 /**
1159  * alloc_dma_desc_resources - alloc TX/RX resources.
1160  * @priv: private structure
1161  * Description: according to which descriptor can be used (extend or basic)
1162  * this function allocates the resources for TX and RX paths. In case of
1163  * reception, for example, it pre-allocated the RX socket buffer in order to
1164  * allow zero-copy mechanism.
1165  */
1166 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1167 {
1168         int ret = -ENOMEM;
1169 
1170         priv->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE, sizeof(dma_addr_t),
1171                                             GFP_KERNEL);
1172         if (!priv->rx_skbuff_dma)
1173                 return -ENOMEM;
1174 
1175         priv->rx_skbuff = kmalloc_array(DMA_RX_SIZE, sizeof(struct sk_buff *),
1176                                         GFP_KERNEL);
1177         if (!priv->rx_skbuff)
1178                 goto err_rx_skbuff;
1179 
1180         priv->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE,
1181                                             sizeof(*priv->tx_skbuff_dma),
1182                                             GFP_KERNEL);
1183         if (!priv->tx_skbuff_dma)
1184                 goto err_tx_skbuff_dma;
1185 
1186         priv->tx_skbuff = kmalloc_array(DMA_TX_SIZE, sizeof(struct sk_buff *),
1187                                         GFP_KERNEL);
1188         if (!priv->tx_skbuff)
1189                 goto err_tx_skbuff;
1190 
1191         if (priv->extend_desc) {
1192                 priv->dma_erx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE *
1193                                                     sizeof(struct
1194                                                            dma_extended_desc),
1195                                                     &priv->dma_rx_phy,
1196                                                     GFP_KERNEL);
1197                 if (!priv->dma_erx)
1198                         goto err_dma;
1199 
1200                 priv->dma_etx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE *
1201                                                     sizeof(struct
1202                                                            dma_extended_desc),
1203                                                     &priv->dma_tx_phy,
1204                                                     GFP_KERNEL);
1205                 if (!priv->dma_etx) {
1206                         dma_free_coherent(priv->device, DMA_RX_SIZE *
1207                                           sizeof(struct dma_extended_desc),
1208                                           priv->dma_erx, priv->dma_rx_phy);
1209                         goto err_dma;
1210                 }
1211         } else {
1212                 priv->dma_rx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE *
1213                                                    sizeof(struct dma_desc),
1214                                                    &priv->dma_rx_phy,
1215                                                    GFP_KERNEL);
1216                 if (!priv->dma_rx)
1217                         goto err_dma;
1218 
1219                 priv->dma_tx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE *
1220                                                    sizeof(struct dma_desc),
1221                                                    &priv->dma_tx_phy,
1222                                                    GFP_KERNEL);
1223                 if (!priv->dma_tx) {
1224                         dma_free_coherent(priv->device, DMA_RX_SIZE *
1225                                           sizeof(struct dma_desc),
1226                                           priv->dma_rx, priv->dma_rx_phy);
1227                         goto err_dma;
1228                 }
1229         }
1230 
1231         return 0;
1232 
1233 err_dma:
1234         kfree(priv->tx_skbuff);
1235 err_tx_skbuff:
1236         kfree(priv->tx_skbuff_dma);
1237 err_tx_skbuff_dma:
1238         kfree(priv->rx_skbuff);
1239 err_rx_skbuff:
1240         kfree(priv->rx_skbuff_dma);
1241         return ret;
1242 }
1243 
1244 static void free_dma_desc_resources(struct stmmac_priv *priv)
1245 {
1246         /* Release the DMA TX/RX socket buffers */
1247         dma_free_rx_skbufs(priv);
1248         dma_free_tx_skbufs(priv);
1249 
1250         /* Free DMA regions of consistent memory previously allocated */
1251         if (!priv->extend_desc) {
1252                 dma_free_coherent(priv->device,
1253                                   DMA_TX_SIZE * sizeof(struct dma_desc),
1254                                   priv->dma_tx, priv->dma_tx_phy);
1255                 dma_free_coherent(priv->device,
1256                                   DMA_RX_SIZE * sizeof(struct dma_desc),
1257                                   priv->dma_rx, priv->dma_rx_phy);
1258         } else {
1259                 dma_free_coherent(priv->device, DMA_TX_SIZE *
1260                                   sizeof(struct dma_extended_desc),
1261                                   priv->dma_etx, priv->dma_tx_phy);
1262                 dma_free_coherent(priv->device, DMA_RX_SIZE *
1263                                   sizeof(struct dma_extended_desc),
1264                                   priv->dma_erx, priv->dma_rx_phy);
1265         }
1266         kfree(priv->rx_skbuff_dma);
1267         kfree(priv->rx_skbuff);
1268         kfree(priv->tx_skbuff_dma);
1269         kfree(priv->tx_skbuff);
1270 }
1271 
1272 /**
1273  *  stmmac_dma_operation_mode - HW DMA operation mode
1274  *  @priv: driver private structure
1275  *  Description: it is used for configuring the DMA operation mode register in
1276  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1277  */
1278 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1279 {
1280         int rxfifosz = priv->plat->rx_fifo_size;
1281 
1282         if (priv->plat->force_thresh_dma_mode)
1283                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz);
1284         else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1285                 /*
1286                  * In case of GMAC, SF mode can be enabled
1287                  * to perform the TX COE in HW. This depends on:
1288                  * 1) TX COE if actually supported
1289                  * 2) There is no bugged Jumbo frame support
1290                  *    that needs to not insert csum in the TDES.
1291                  */
1292                 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE,
1293                                         rxfifosz);
1294                 priv->xstats.threshold = SF_DMA_MODE;
1295         } else
1296                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE,
1297                                         rxfifosz);
1298 }
1299 
1300 /**
1301  * stmmac_tx_clean - to manage the transmission completion
1302  * @priv: driver private structure
1303  * Description: it reclaims the transmit resources after transmission completes.
1304  */
1305 static void stmmac_tx_clean(struct stmmac_priv *priv)
1306 {
1307         unsigned int bytes_compl = 0, pkts_compl = 0;
1308         unsigned int entry = priv->dirty_tx;
1309 
1310         spin_lock(&priv->tx_lock);
1311 
1312         priv->xstats.tx_clean++;
1313 
1314         while (entry != priv->cur_tx) {
1315                 struct sk_buff *skb = priv->tx_skbuff[entry];
1316                 struct dma_desc *p;
1317                 int status;
1318 
1319                 if (priv->extend_desc)
1320                         p = (struct dma_desc *)(priv->dma_etx + entry);
1321                 else
1322                         p = priv->dma_tx + entry;
1323 
1324                 status = priv->hw->desc->tx_status(&priv->dev->stats,
1325                                                       &priv->xstats, p,
1326                                                       priv->ioaddr);
1327                 /* Check if the descriptor is owned by the DMA */
1328                 if (unlikely(status & tx_dma_own))
1329                         break;
1330 
1331                 /* Just consider the last segment and ...*/
1332                 if (likely(!(status & tx_not_ls))) {
1333                         /* ... verify the status error condition */
1334                         if (unlikely(status & tx_err)) {
1335                                 priv->dev->stats.tx_errors++;
1336                         } else {
1337                                 priv->dev->stats.tx_packets++;
1338                                 priv->xstats.tx_pkt_n++;
1339                         }
1340                         stmmac_get_tx_hwtstamp(priv, p, skb);
1341                 }
1342 
1343                 if (likely(priv->tx_skbuff_dma[entry].buf)) {
1344                         if (priv->tx_skbuff_dma[entry].map_as_page)
1345                                 dma_unmap_page(priv->device,
1346                                                priv->tx_skbuff_dma[entry].buf,
1347                                                priv->tx_skbuff_dma[entry].len,
1348                                                DMA_TO_DEVICE);
1349                         else
1350                                 dma_unmap_single(priv->device,
1351                                                  priv->tx_skbuff_dma[entry].buf,
1352                                                  priv->tx_skbuff_dma[entry].len,
1353                                                  DMA_TO_DEVICE);
1354                         priv->tx_skbuff_dma[entry].buf = 0;
1355                         priv->tx_skbuff_dma[entry].len = 0;
1356                         priv->tx_skbuff_dma[entry].map_as_page = false;
1357                 }
1358 
1359                 if (priv->hw->mode->clean_desc3)
1360                         priv->hw->mode->clean_desc3(priv, p);
1361 
1362                 priv->tx_skbuff_dma[entry].last_segment = false;
1363                 priv->tx_skbuff_dma[entry].is_jumbo = false;
1364 
1365                 if (likely(skb != NULL)) {
1366                         pkts_compl++;
1367                         bytes_compl += skb->len;
1368                         dev_consume_skb_any(skb);
1369                         priv->tx_skbuff[entry] = NULL;
1370                 }
1371 
1372                 priv->hw->desc->release_tx_desc(p, priv->mode);
1373 
1374                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1375         }
1376         priv->dirty_tx = entry;
1377 
1378         netdev_completed_queue(priv->dev, pkts_compl, bytes_compl);
1379 
1380         if (unlikely(netif_queue_stopped(priv->dev) &&
1381                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH)) {
1382                 netif_tx_lock(priv->dev);
1383                 if (netif_queue_stopped(priv->dev) &&
1384                     stmmac_tx_avail(priv) > STMMAC_TX_THRESH) {
1385                         if (netif_msg_tx_done(priv))
1386                                 pr_debug("%s: restart transmit\n", __func__);
1387                         netif_wake_queue(priv->dev);
1388                 }
1389                 netif_tx_unlock(priv->dev);
1390         }
1391 
1392         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1393                 stmmac_enable_eee_mode(priv);
1394                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1395         }
1396         spin_unlock(&priv->tx_lock);
1397 }
1398 
1399 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1400 {
1401         priv->hw->dma->enable_dma_irq(priv->ioaddr);
1402 }
1403 
1404 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1405 {
1406         priv->hw->dma->disable_dma_irq(priv->ioaddr);
1407 }
1408 
1409 /**
1410  * stmmac_tx_err - to manage the tx error
1411  * @priv: driver private structure
1412  * Description: it cleans the descriptors and restarts the transmission
1413  * in case of transmission errors.
1414  */
1415 static void stmmac_tx_err(struct stmmac_priv *priv)
1416 {
1417         int i;
1418         netif_stop_queue(priv->dev);
1419 
1420         priv->hw->dma->stop_tx(priv->ioaddr);
1421         dma_free_tx_skbufs(priv);
1422         for (i = 0; i < DMA_TX_SIZE; i++)
1423                 if (priv->extend_desc)
1424                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1425                                                      priv->mode,
1426                                                      (i == DMA_TX_SIZE - 1));
1427                 else
1428                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1429                                                      priv->mode,
1430                                                      (i == DMA_TX_SIZE - 1));
1431         priv->dirty_tx = 0;
1432         priv->cur_tx = 0;
1433         netdev_reset_queue(priv->dev);
1434         priv->hw->dma->start_tx(priv->ioaddr);
1435 
1436         priv->dev->stats.tx_errors++;
1437         netif_wake_queue(priv->dev);
1438 }
1439 
1440 /**
1441  * stmmac_dma_interrupt - DMA ISR
1442  * @priv: driver private structure
1443  * Description: this is the DMA ISR. It is called by the main ISR.
1444  * It calls the dwmac dma routine and schedule poll method in case of some
1445  * work can be done.
1446  */
1447 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1448 {
1449         int status;
1450         int rxfifosz = priv->plat->rx_fifo_size;
1451 
1452         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1453         if (likely((status & handle_rx)) || (status & handle_tx)) {
1454                 if (likely(napi_schedule_prep(&priv->napi))) {
1455                         stmmac_disable_dma_irq(priv);
1456                         __napi_schedule(&priv->napi);
1457                 }
1458         }
1459         if (unlikely(status & tx_hard_error_bump_tc)) {
1460                 /* Try to bump up the dma threshold on this failure */
1461                 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
1462                     (tc <= 256)) {
1463                         tc += 64;
1464                         if (priv->plat->force_thresh_dma_mode)
1465                                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc,
1466                                                         rxfifosz);
1467                         else
1468                                 priv->hw->dma->dma_mode(priv->ioaddr, tc,
1469                                                         SF_DMA_MODE, rxfifosz);
1470                         priv->xstats.threshold = tc;
1471                 }
1472         } else if (unlikely(status == tx_hard_error))
1473                 stmmac_tx_err(priv);
1474 }
1475 
1476 /**
1477  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1478  * @priv: driver private structure
1479  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1480  */
1481 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1482 {
1483         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1484                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1485 
1486         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1487                 priv->ptpaddr = priv->ioaddr + PTP_GMAC4_OFFSET;
1488                 priv->mmcaddr = priv->ioaddr + MMC_GMAC4_OFFSET;
1489         } else {
1490                 priv->ptpaddr = priv->ioaddr + PTP_GMAC3_X_OFFSET;
1491                 priv->mmcaddr = priv->ioaddr + MMC_GMAC3_X_OFFSET;
1492         }
1493 
1494         dwmac_mmc_intr_all_mask(priv->mmcaddr);
1495 
1496         if (priv->dma_cap.rmon) {
1497                 dwmac_mmc_ctrl(priv->mmcaddr, mode);
1498                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1499         } else
1500                 pr_info(" No MAC Management Counters available\n");
1501 }
1502 
1503 /**
1504  * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1505  * @priv: driver private structure
1506  * Description: select the Enhanced/Alternate or Normal descriptors.
1507  * In case of Enhanced/Alternate, it checks if the extended descriptors are
1508  * supported by the HW capability register.
1509  */
1510 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1511 {
1512         if (priv->plat->enh_desc) {
1513                 pr_info(" Enhanced/Alternate descriptors\n");
1514 
1515                 /* GMAC older than 3.50 has no extended descriptors */
1516                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1517                         pr_info("\tEnabled extended descriptors\n");
1518                         priv->extend_desc = 1;
1519                 } else
1520                         pr_warn("Extended descriptors not supported\n");
1521 
1522                 priv->hw->desc = &enh_desc_ops;
1523         } else {
1524                 pr_info(" Normal descriptors\n");
1525                 priv->hw->desc = &ndesc_ops;
1526         }
1527 }
1528 
1529 /**
1530  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1531  * @priv: driver private structure
1532  * Description:
1533  *  new GMAC chip generations have a new register to indicate the
1534  *  presence of the optional feature/functions.
1535  *  This can be also used to override the value passed through the
1536  *  platform and necessary for old MAC10/100 and GMAC chips.
1537  */
1538 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1539 {
1540         u32 ret = 0;
1541 
1542         if (priv->hw->dma->get_hw_feature) {
1543                 priv->hw->dma->get_hw_feature(priv->ioaddr,
1544                                               &priv->dma_cap);
1545                 ret = 1;
1546         }
1547 
1548         return ret;
1549 }
1550 
1551 /**
1552  * stmmac_check_ether_addr - check if the MAC addr is valid
1553  * @priv: driver private structure
1554  * Description:
1555  * it is to verify if the MAC address is valid, in case of failures it
1556  * generates a random MAC address
1557  */
1558 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1559 {
1560         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1561                 priv->hw->mac->get_umac_addr(priv->hw,
1562                                              priv->dev->dev_addr, 0);
1563                 if (!is_valid_ether_addr(priv->dev->dev_addr))
1564                         eth_hw_addr_random(priv->dev);
1565                 pr_info("%s: device MAC address %pM\n", priv->dev->name,
1566                         priv->dev->dev_addr);
1567         }
1568 }
1569 
1570 /**
1571  * stmmac_init_dma_engine - DMA init.
1572  * @priv: driver private structure
1573  * Description:
1574  * It inits the DMA invoking the specific MAC/GMAC callback.
1575  * Some DMA parameters can be passed from the platform;
1576  * in case of these are not passed a default is kept for the MAC or GMAC.
1577  */
1578 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1579 {
1580         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, aal = 0;
1581         int mixed_burst = 0;
1582         int atds = 0;
1583         int ret = 0;
1584 
1585         if (priv->plat->dma_cfg) {
1586                 pbl = priv->plat->dma_cfg->pbl;
1587                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1588                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1589                 aal = priv->plat->dma_cfg->aal;
1590         }
1591 
1592         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1593                 atds = 1;
1594 
1595         ret = priv->hw->dma->reset(priv->ioaddr);
1596         if (ret) {
1597                 dev_err(priv->device, "Failed to reset the dma\n");
1598                 return ret;
1599         }
1600 
1601         priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1602                             aal, priv->dma_tx_phy, priv->dma_rx_phy, atds);
1603 
1604         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1605                 priv->rx_tail_addr = priv->dma_rx_phy +
1606                             (DMA_RX_SIZE * sizeof(struct dma_desc));
1607                 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr, priv->rx_tail_addr,
1608                                                STMMAC_CHAN0);
1609 
1610                 priv->tx_tail_addr = priv->dma_tx_phy +
1611                             (DMA_TX_SIZE * sizeof(struct dma_desc));
1612                 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr,
1613                                                STMMAC_CHAN0);
1614         }
1615 
1616         if (priv->plat->axi && priv->hw->dma->axi)
1617                 priv->hw->dma->axi(priv->ioaddr, priv->plat->axi);
1618 
1619         return ret;
1620 }
1621 
1622 /**
1623  * stmmac_tx_timer - mitigation sw timer for tx.
1624  * @data: data pointer
1625  * Description:
1626  * This is the timer handler to directly invoke the stmmac_tx_clean.
1627  */
1628 static void stmmac_tx_timer(unsigned long data)
1629 {
1630         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1631 
1632         stmmac_tx_clean(priv);
1633 }
1634 
1635 /**
1636  * stmmac_init_tx_coalesce - init tx mitigation options.
1637  * @priv: driver private structure
1638  * Description:
1639  * This inits the transmit coalesce parameters: i.e. timer rate,
1640  * timer handler and default threshold used for enabling the
1641  * interrupt on completion bit.
1642  */
1643 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1644 {
1645         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1646         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1647         init_timer(&priv->txtimer);
1648         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1649         priv->txtimer.data = (unsigned long)priv;
1650         priv->txtimer.function = stmmac_tx_timer;
1651         add_timer(&priv->txtimer);
1652 }
1653 
1654 /**
1655  * stmmac_hw_setup - setup mac in a usable state.
1656  *  @dev : pointer to the device structure.
1657  *  Description:
1658  *  this is the main function to setup the HW in a usable state because the
1659  *  dma engine is reset, the core registers are configured (e.g. AXI,
1660  *  Checksum features, timers). The DMA is ready to start receiving and
1661  *  transmitting.
1662  *  Return value:
1663  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1664  *  file on failure.
1665  */
1666 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
1667 {
1668         struct stmmac_priv *priv = netdev_priv(dev);
1669         int ret;
1670 
1671         /* DMA initialization and SW reset */
1672         ret = stmmac_init_dma_engine(priv);
1673         if (ret < 0) {
1674                 pr_err("%s: DMA engine initialization failed\n", __func__);
1675                 return ret;
1676         }
1677 
1678         /* Copy the MAC addr into the HW  */
1679         priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1680 
1681         /* If required, perform hw setup of the bus. */
1682         if (priv->plat->bus_setup)
1683                 priv->plat->bus_setup(priv->ioaddr);
1684 
1685         /* PS and related bits will be programmed according to the speed */
1686         if (priv->hw->pcs) {
1687                 int speed = priv->plat->mac_port_sel_speed;
1688 
1689                 if ((speed == SPEED_10) || (speed == SPEED_100) ||
1690                     (speed == SPEED_1000)) {
1691                         priv->hw->ps = speed;
1692                 } else {
1693                         dev_warn(priv->device, "invalid port speed\n");
1694                         priv->hw->ps = 0;
1695                 }
1696         }
1697 
1698         /* Initialize the MAC Core */
1699         priv->hw->mac->core_init(priv->hw, dev->mtu);
1700 
1701         ret = priv->hw->mac->rx_ipc(priv->hw);
1702         if (!ret) {
1703                 pr_warn(" RX IPC Checksum Offload disabled\n");
1704                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1705                 priv->hw->rx_csum = 0;
1706         }
1707 
1708         /* Enable the MAC Rx/Tx */
1709         if (priv->synopsys_id >= DWMAC_CORE_4_00)
1710                 stmmac_dwmac4_set_mac(priv->ioaddr, true);
1711         else
1712                 stmmac_set_mac(priv->ioaddr, true);
1713 
1714         /* Set the HW DMA mode and the COE */
1715         stmmac_dma_operation_mode(priv);
1716 
1717         stmmac_mmc_setup(priv);
1718 
1719         if (init_ptp) {
1720                 ret = stmmac_init_ptp(priv);
1721                 if (ret)
1722                         netdev_warn(priv->dev, "fail to init PTP.\n");
1723         }
1724 
1725 #ifdef CONFIG_DEBUG_FS
1726         ret = stmmac_init_fs(dev);
1727         if (ret < 0)
1728                 pr_warn("%s: failed debugFS registration\n", __func__);
1729 #endif
1730         /* Start the ball rolling... */
1731         pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
1732         priv->hw->dma->start_tx(priv->ioaddr);
1733         priv->hw->dma->start_rx(priv->ioaddr);
1734 
1735         /* Dump DMA/MAC registers */
1736         if (netif_msg_hw(priv)) {
1737                 priv->hw->mac->dump_regs(priv->hw);
1738                 priv->hw->dma->dump_regs(priv->ioaddr);
1739         }
1740         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1741 
1742         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1743                 priv->rx_riwt = MAX_DMA_RIWT;
1744                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1745         }
1746 
1747         if (priv->hw->pcs && priv->hw->mac->pcs_ctrl_ane)
1748                 priv->hw->mac->pcs_ctrl_ane(priv->hw, 1, priv->hw->ps, 0);
1749 
1750         /*  set TX ring length */
1751         if (priv->hw->dma->set_tx_ring_len)
1752                 priv->hw->dma->set_tx_ring_len(priv->ioaddr,
1753                                                (DMA_TX_SIZE - 1));
1754         /*  set RX ring length */
1755         if (priv->hw->dma->set_rx_ring_len)
1756                 priv->hw->dma->set_rx_ring_len(priv->ioaddr,
1757                                                (DMA_RX_SIZE - 1));
1758         /* Enable TSO */
1759         if (priv->tso)
1760                 priv->hw->dma->enable_tso(priv->ioaddr, 1, STMMAC_CHAN0);
1761 
1762         return 0;
1763 }
1764 
1765 /**
1766  *  stmmac_open - open entry point of the driver
1767  *  @dev : pointer to the device structure.
1768  *  Description:
1769  *  This function is the open entry point of the driver.
1770  *  Return value:
1771  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1772  *  file on failure.
1773  */
1774 static int stmmac_open(struct net_device *dev)
1775 {
1776         struct stmmac_priv *priv = netdev_priv(dev);
1777         int ret;
1778 
1779         stmmac_check_ether_addr(priv);
1780 
1781         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
1782             priv->hw->pcs != STMMAC_PCS_TBI &&
1783             priv->hw->pcs != STMMAC_PCS_RTBI) {
1784                 ret = stmmac_init_phy(dev);
1785                 if (ret) {
1786                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1787                                __func__, ret);
1788                         return ret;
1789                 }
1790         }
1791 
1792         /* Extra statistics */
1793         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1794         priv->xstats.threshold = tc;
1795 
1796         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1797         priv->rx_copybreak = STMMAC_RX_COPYBREAK;
1798 
1799         ret = alloc_dma_desc_resources(priv);
1800         if (ret < 0) {
1801                 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1802                 goto dma_desc_error;
1803         }
1804 
1805         ret = init_dma_desc_rings(dev, GFP_KERNEL);
1806         if (ret < 0) {
1807                 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1808                 goto init_error;
1809         }
1810 
1811         ret = stmmac_hw_setup(dev, true);
1812         if (ret < 0) {
1813                 pr_err("%s: Hw setup failed\n", __func__);
1814                 goto init_error;
1815         }
1816 
1817         stmmac_init_tx_coalesce(priv);
1818 
1819         if (priv->phydev)
1820                 phy_start(priv->phydev);
1821 
1822         /* Request the IRQ lines */
1823         ret = request_irq(dev->irq, stmmac_interrupt,
1824                           IRQF_SHARED, dev->name, dev);
1825         if (unlikely(ret < 0)) {
1826                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1827                        __func__, dev->irq, ret);
1828                 goto init_error;
1829         }
1830 
1831         /* Request the Wake IRQ in case of another line is used for WoL */
1832         if (priv->wol_irq != dev->irq) {
1833                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1834                                   IRQF_SHARED, dev->name, dev);
1835                 if (unlikely(ret < 0)) {
1836                         pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1837                                __func__, priv->wol_irq, ret);
1838                         goto wolirq_error;
1839                 }
1840         }
1841 
1842         /* Request the IRQ lines */
1843         if (priv->lpi_irq > 0) {
1844                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1845                                   dev->name, dev);
1846                 if (unlikely(ret < 0)) {
1847                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1848                                __func__, priv->lpi_irq, ret);
1849                         goto lpiirq_error;
1850                 }
1851         }
1852 
1853         napi_enable(&priv->napi);
1854         netif_start_queue(dev);
1855 
1856         return 0;
1857 
1858 lpiirq_error:
1859         if (priv->wol_irq != dev->irq)
1860                 free_irq(priv->wol_irq, dev);
1861 wolirq_error:
1862         free_irq(dev->irq, dev);
1863 
1864 init_error:
1865         free_dma_desc_resources(priv);
1866 dma_desc_error:
1867         if (priv->phydev)
1868                 phy_disconnect(priv->phydev);
1869 
1870         return ret;
1871 }
1872 
1873 /**
1874  *  stmmac_release - close entry point of the driver
1875  *  @dev : device pointer.
1876  *  Description:
1877  *  This is the stop entry point of the driver.
1878  */
1879 static int stmmac_release(struct net_device *dev)
1880 {
1881         struct stmmac_priv *priv = netdev_priv(dev);
1882 
1883         if (priv->eee_enabled)
1884                 del_timer_sync(&priv->eee_ctrl_timer);
1885 
1886         /* Stop and disconnect the PHY */
1887         if (priv->phydev) {
1888                 phy_stop(priv->phydev);
1889                 phy_disconnect(priv->phydev);
1890                 priv->phydev = NULL;
1891         }
1892 
1893         netif_stop_queue(dev);
1894 
1895         napi_disable(&priv->napi);
1896 
1897         del_timer_sync(&priv->txtimer);
1898 
1899         /* Free the IRQ lines */
1900         free_irq(dev->irq, dev);
1901         if (priv->wol_irq != dev->irq)
1902                 free_irq(priv->wol_irq, dev);
1903         if (priv->lpi_irq > 0)
1904                 free_irq(priv->lpi_irq, dev);
1905 
1906         /* Stop TX/RX DMA and clear the descriptors */
1907         priv->hw->dma->stop_tx(priv->ioaddr);
1908         priv->hw->dma->stop_rx(priv->ioaddr);
1909 
1910         /* Release and free the Rx/Tx resources */
1911         free_dma_desc_resources(priv);
1912 
1913         /* Disable the MAC Rx/Tx */
1914         stmmac_set_mac(priv->ioaddr, false);
1915 
1916         netif_carrier_off(dev);
1917 
1918 #ifdef CONFIG_DEBUG_FS
1919         stmmac_exit_fs(dev);
1920 #endif
1921 
1922         stmmac_release_ptp(priv);
1923 
1924         return 0;
1925 }
1926 
1927 /**
1928  *  stmmac_tso_allocator - close entry point of the driver
1929  *  @priv: driver private structure
1930  *  @des: buffer start address
1931  *  @total_len: total length to fill in descriptors
1932  *  @last_segmant: condition for the last descriptor
1933  *  Description:
1934  *  This function fills descriptor and request new descriptors according to
1935  *  buffer length to fill
1936  */
1937 static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des,
1938                                  int total_len, bool last_segment)
1939 {
1940         struct dma_desc *desc;
1941         int tmp_len;
1942         u32 buff_size;
1943 
1944         tmp_len = total_len;
1945 
1946         while (tmp_len > 0) {
1947                 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
1948                 desc = priv->dma_tx + priv->cur_tx;
1949 
1950                 desc->des0 = des + (total_len - tmp_len);
1951                 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
1952                             TSO_MAX_BUFF_SIZE : tmp_len;
1953 
1954                 priv->hw->desc->prepare_tso_tx_desc(desc, 0, buff_size,
1955                         0, 1,
1956                         (last_segment) && (buff_size < TSO_MAX_BUFF_SIZE),
1957                         0, 0);
1958 
1959                 tmp_len -= TSO_MAX_BUFF_SIZE;
1960         }
1961 }
1962 
1963 /**
1964  *  stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
1965  *  @skb : the socket buffer
1966  *  @dev : device pointer
1967  *  Description: this is the transmit function that is called on TSO frames
1968  *  (support available on GMAC4 and newer chips).
1969  *  Diagram below show the ring programming in case of TSO frames:
1970  *
1971  *  First Descriptor
1972  *   --------
1973  *   | DES0 |---> buffer1 = L2/L3/L4 header
1974  *   | DES1 |---> TCP Payload (can continue on next descr...)
1975  *   | DES2 |---> buffer 1 and 2 len
1976  *   | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
1977  *   --------
1978  *      |
1979  *     ...
1980  *      |
1981  *   --------
1982  *   | DES0 | --| Split TCP Payload on Buffers 1 and 2
1983  *   | DES1 | --|
1984  *   | DES2 | --> buffer 1 and 2 len
1985  *   | DES3 |
1986  *   --------
1987  *
1988  * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
1989  */
1990 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
1991 {
1992         u32 pay_len, mss;
1993         int tmp_pay_len = 0;
1994         struct stmmac_priv *priv = netdev_priv(dev);
1995         int nfrags = skb_shinfo(skb)->nr_frags;
1996         unsigned int first_entry, des;
1997         struct dma_desc *desc, *first, *mss_desc = NULL;
1998         u8 proto_hdr_len;
1999         int i;
2000 
2001         spin_lock(&priv->tx_lock);
2002 
2003         /* Compute header lengths */
2004         proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2005 
2006         /* Desc availability based on threshold should be enough safe */
2007         if (unlikely(stmmac_tx_avail(priv) <
2008                 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2009                 if (!netif_queue_stopped(dev)) {
2010                         netif_stop_queue(dev);
2011                         /* This is a hard error, log it. */
2012                         pr_err("%s: Tx Ring full when queue awake\n", __func__);
2013                 }
2014                 spin_unlock(&priv->tx_lock);
2015                 return NETDEV_TX_BUSY;
2016         }
2017 
2018         pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2019 
2020         mss = skb_shinfo(skb)->gso_size;
2021 
2022         /* set new MSS value if needed */
2023         if (mss != priv->mss) {
2024                 mss_desc = priv->dma_tx + priv->cur_tx;
2025                 priv->hw->desc->set_mss(mss_desc, mss);
2026                 priv->mss = mss;
2027                 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
2028         }
2029 
2030         if (netif_msg_tx_queued(priv)) {
2031                 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2032                         __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
2033                 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2034                         skb->data_len);
2035         }
2036 
2037         first_entry = priv->cur_tx;
2038 
2039         desc = priv->dma_tx + first_entry;
2040         first = desc;
2041 
2042         /* first descriptor: fill Headers on Buf1 */
2043         des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2044                              DMA_TO_DEVICE);
2045         if (dma_mapping_error(priv->device, des))
2046                 goto dma_map_err;
2047 
2048         priv->tx_skbuff_dma[first_entry].buf = des;
2049         priv->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2050         priv->tx_skbuff[first_entry] = skb;
2051 
2052         first->des0 = des;
2053 
2054         /* Fill start of payload in buff2 of first descriptor */
2055         if (pay_len)
2056                 first->des1 =  des + proto_hdr_len;
2057 
2058         /* If needed take extra descriptors to fill the remaining payload */
2059         tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
2060 
2061         stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0));
2062 
2063         /* Prepare fragments */
2064         for (i = 0; i < nfrags; i++) {
2065                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2066 
2067                 des = skb_frag_dma_map(priv->device, frag, 0,
2068                                        skb_frag_size(frag),
2069                                        DMA_TO_DEVICE);
2070 
2071                 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
2072                                      (i == nfrags - 1));
2073 
2074                 priv->tx_skbuff_dma[priv->cur_tx].buf = des;
2075                 priv->tx_skbuff_dma[priv->cur_tx].len = skb_frag_size(frag);
2076                 priv->tx_skbuff[priv->cur_tx] = NULL;
2077                 priv->tx_skbuff_dma[priv->cur_tx].map_as_page = true;
2078         }
2079 
2080         priv->tx_skbuff_dma[priv->cur_tx].last_segment = true;
2081 
2082         priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
2083 
2084         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2085                 if (netif_msg_hw(priv))
2086                         pr_debug("%s: stop transmitted packets\n", __func__);
2087                 netif_stop_queue(dev);
2088         }
2089 
2090         dev->stats.tx_bytes += skb->len;
2091         priv->xstats.tx_tso_frames++;
2092         priv->xstats.tx_tso_nfrags += nfrags;
2093 
2094         /* Manage tx mitigation */
2095         priv->tx_count_frames += nfrags + 1;
2096         if (likely(priv->tx_coal_frames > priv->tx_count_frames)) {
2097                 mod_timer(&priv->txtimer,
2098                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
2099         } else {
2100                 priv->tx_count_frames = 0;
2101                 priv->hw->desc->set_tx_ic(desc);
2102                 priv->xstats.tx_set_ic_bit++;
2103         }
2104 
2105         if (!priv->hwts_tx_en)
2106                 skb_tx_timestamp(skb);
2107 
2108         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2109                      priv->hwts_tx_en)) {
2110                 /* declare that device is doing timestamping */
2111                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2112                 priv->hw->desc->enable_tx_timestamp(first);
2113         }
2114 
2115         /* Complete the first descriptor before granting the DMA */
2116         priv->hw->desc->prepare_tso_tx_desc(first, 1,
2117                         proto_hdr_len,
2118                         pay_len,
2119                         1, priv->tx_skbuff_dma[first_entry].last_segment,
2120                         tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
2121 
2122         /* If context desc is used to change MSS */
2123         if (mss_desc)
2124                 priv->hw->desc->set_tx_owner(mss_desc);
2125 
2126         /* The own bit must be the latest setting done when prepare the
2127          * descriptor and then barrier is needed to make sure that
2128          * all is coherent before granting the DMA engine.
2129          */
2130         smp_wmb();
2131 
2132         if (netif_msg_pktdata(priv)) {
2133                 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
2134                         __func__, priv->cur_tx, priv->dirty_tx, first_entry,
2135                         priv->cur_tx, first, nfrags);
2136 
2137                 priv->hw->desc->display_ring((void *)priv->dma_tx, DMA_TX_SIZE,
2138                                              0);
2139 
2140                 pr_info(">>> frame to be transmitted: ");
2141                 print_pkt(skb->data, skb_headlen(skb));
2142         }
2143 
2144         netdev_sent_queue(dev, skb->len);
2145 
2146         priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr,
2147                                        STMMAC_CHAN0);
2148 
2149         spin_unlock(&priv->tx_lock);
2150         return NETDEV_TX_OK;
2151 
2152 dma_map_err:
2153         spin_unlock(&priv->tx_lock);
2154         dev_err(priv->device, "Tx dma map failed\n");
2155         dev_kfree_skb(skb);
2156         priv->dev->stats.tx_dropped++;
2157         return NETDEV_TX_OK;
2158 }
2159 
2160 /**
2161  *  stmmac_xmit - Tx entry point of the driver
2162  *  @skb : the socket buffer
2163  *  @dev : device pointer
2164  *  Description : this is the tx entry point of the driver.
2165  *  It programs the chain or the ring and supports oversized frames
2166  *  and SG feature.
2167  */
2168 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
2169 {
2170         struct stmmac_priv *priv = netdev_priv(dev);
2171         unsigned int nopaged_len = skb_headlen(skb);
2172         int i, csum_insertion = 0, is_jumbo = 0;
2173         int nfrags = skb_shinfo(skb)->nr_frags;
2174         unsigned int entry, first_entry;
2175         struct dma_desc *desc, *first;
2176         unsigned int enh_desc;
2177         unsigned int des;
2178 
2179         /* Manage oversized TCP frames for GMAC4 device */
2180         if (skb_is_gso(skb) && priv->tso) {
2181                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2182                         return stmmac_tso_xmit(skb, dev);
2183         }
2184 
2185         spin_lock(&priv->tx_lock);
2186 
2187         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
2188                 spin_unlock(&priv->tx_lock);
2189                 if (!netif_queue_stopped(dev)) {
2190                         netif_stop_queue(dev);
2191                         /* This is a hard error, log it. */
2192                         pr_err("%s: Tx Ring full when queue awake\n", __func__);
2193                 }
2194                 return NETDEV_TX_BUSY;
2195         }
2196 
2197         if (priv->tx_path_in_lpi_mode)
2198                 stmmac_disable_eee_mode(priv);
2199 
2200         entry = priv->cur_tx;
2201         first_entry = entry;
2202 
2203         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
2204 
2205         if (likely(priv->extend_desc))
2206                 desc = (struct dma_desc *)(priv->dma_etx + entry);
2207         else
2208                 desc = priv->dma_tx + entry;
2209 
2210         first = desc;
2211 
2212         priv->tx_skbuff[first_entry] = skb;
2213 
2214         enh_desc = priv->plat->enh_desc;
2215         /* To program the descriptors according to the size of the frame */
2216         if (enh_desc)
2217                 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
2218 
2219         if (unlikely(is_jumbo) && likely(priv->synopsys_id <
2220                                          DWMAC_CORE_4_00)) {
2221                 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
2222                 if (unlikely(entry < 0))
2223                         goto dma_map_err;
2224         }
2225 
2226         for (i = 0; i < nfrags; i++) {
2227                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2228                 int len = skb_frag_size(frag);
2229                 bool last_segment = (i == (nfrags - 1));
2230 
2231                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
2232 
2233                 if (likely(priv->extend_desc))
2234                         desc = (struct dma_desc *)(priv->dma_etx + entry);
2235                 else
2236                         desc = priv->dma_tx + entry;
2237 
2238                 des = skb_frag_dma_map(priv->device, frag, 0, len,
2239                                        DMA_TO_DEVICE);
2240                 if (dma_mapping_error(priv->device, des))
2241                         goto dma_map_err; /* should reuse desc w/o issues */
2242 
2243                 priv->tx_skbuff[entry] = NULL;
2244 
2245                 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) {
2246                         desc->des0 = des;
2247                         priv->tx_skbuff_dma[entry].buf = desc->des0;
2248                 } else {
2249                         desc->des2 = des;
2250                         priv->tx_skbuff_dma[entry].buf = desc->des2;
2251                 }
2252 
2253                 priv->tx_skbuff_dma[entry].map_as_page = true;
2254                 priv->tx_skbuff_dma[entry].len = len;
2255                 priv->tx_skbuff_dma[entry].last_segment = last_segment;
2256 
2257                 /* Prepare the descriptor and set the own bit too */
2258                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
2259                                                 priv->mode, 1, last_segment);
2260         }
2261 
2262         entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
2263 
2264         priv->cur_tx = entry;
2265 
2266         if (netif_msg_pktdata(priv)) {
2267                 void *tx_head;
2268 
2269                 pr_debug("%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
2270                          __func__, priv->cur_tx, priv->dirty_tx, first_entry,
2271                          entry, first, nfrags);
2272 
2273                 if (priv->extend_desc)
2274                         tx_head = (void *)priv->dma_etx;
2275                 else
2276                         tx_head = (void *)priv->dma_tx;
2277 
2278                 priv->hw->desc->display_ring(tx_head, DMA_TX_SIZE, false);
2279 
2280                 pr_debug(">>> frame to be transmitted: ");
2281                 print_pkt(skb->data, skb->len);
2282         }
2283 
2284         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2285                 if (netif_msg_hw(priv))
2286                         pr_debug("%s: stop transmitted packets\n", __func__);
2287                 netif_stop_queue(dev);
2288         }
2289 
2290         dev->stats.tx_bytes += skb->len;
2291 
2292         /* According to the coalesce parameter the IC bit for the latest
2293          * segment is reset and the timer re-started to clean the tx status.
2294          * This approach takes care about the fragments: desc is the first
2295          * element in case of no SG.
2296          */
2297         priv->tx_count_frames += nfrags + 1;
2298         if (likely(priv->tx_coal_frames > priv->tx_count_frames)) {
2299                 mod_timer(&priv->txtimer,
2300                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
2301         } else {
2302                 priv->tx_count_frames = 0;
2303                 priv->hw->desc->set_tx_ic(desc);
2304                 priv->xstats.tx_set_ic_bit++;
2305         }
2306 
2307         if (!priv->hwts_tx_en)
2308                 skb_tx_timestamp(skb);
2309 
2310         /* Ready to fill the first descriptor and set the OWN bit w/o any
2311          * problems because all the descriptors are actually ready to be
2312          * passed to the DMA engine.
2313          */
2314         if (likely(!is_jumbo)) {
2315                 bool last_segment = (nfrags == 0);
2316 
2317                 des = dma_map_single(priv->device, skb->data,
2318                                      nopaged_len, DMA_TO_DEVICE);
2319                 if (dma_mapping_error(priv->device, des))
2320                         goto dma_map_err;
2321 
2322                 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) {
2323                         first->des0 = des;
2324                         priv->tx_skbuff_dma[first_entry].buf = first->des0;
2325                 } else {
2326                         first->des2 = des;
2327                         priv->tx_skbuff_dma[first_entry].buf = first->des2;
2328                 }
2329 
2330                 priv->tx_skbuff_dma[first_entry].len = nopaged_len;
2331                 priv->tx_skbuff_dma[first_entry].last_segment = last_segment;
2332 
2333                 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2334                              priv->hwts_tx_en)) {
2335                         /* declare that device is doing timestamping */
2336                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2337                         priv->hw->desc->enable_tx_timestamp(first);
2338                 }
2339 
2340                 /* Prepare the first descriptor setting the OWN bit too */
2341                 priv->hw->desc->prepare_tx_desc(first, 1, nopaged_len,
2342                                                 csum_insertion, priv->mode, 1,
2343                                                 last_segment);
2344 
2345                 /* The own bit must be the latest setting done when prepare the
2346                  * descriptor and then barrier is needed to make sure that
2347                  * all is coherent before granting the DMA engine.
2348                  */
2349                 smp_wmb();
2350         }
2351 
2352         netdev_sent_queue(dev, skb->len);
2353 
2354         if (priv->synopsys_id < DWMAC_CORE_4_00)
2355                 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
2356         else
2357                 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr,
2358                                                STMMAC_CHAN0);
2359 
2360         spin_unlock(&priv->tx_lock);
2361         return NETDEV_TX_OK;
2362 
2363 dma_map_err:
2364         spin_unlock(&priv->tx_lock);
2365         dev_err(priv->device, "Tx dma map failed\n");
2366         dev_kfree_skb(skb);
2367         priv->dev->stats.tx_dropped++;
2368         return NETDEV_TX_OK;
2369 }
2370 
2371 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
2372 {
2373         struct ethhdr *ehdr;
2374         u16 vlanid;
2375 
2376         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
2377             NETIF_F_HW_VLAN_CTAG_RX &&
2378             !__vlan_get_tag(skb, &vlanid)) {
2379                 /* pop the vlan tag */
2380                 ehdr = (struct ethhdr *)skb->data;
2381                 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
2382                 skb_pull(skb, VLAN_HLEN);
2383                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
2384         }
2385 }
2386 
2387 
2388 static inline int stmmac_rx_threshold_count(struct stmmac_priv *priv)
2389 {
2390         if (priv->rx_zeroc_thresh < STMMAC_RX_THRESH)
2391                 return 0;
2392 
2393         return 1;
2394 }
2395 
2396 /**
2397  * stmmac_rx_refill - refill used skb preallocated buffers
2398  * @priv: driver private structure
2399  * Description : this is to reallocate the skb for the reception process
2400  * that is based on zero-copy.
2401  */
2402 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2403 {
2404         int bfsize = priv->dma_buf_sz;
2405         unsigned int entry = priv->dirty_rx;
2406         int dirty = stmmac_rx_dirty(priv);
2407 
2408         while (dirty-- > 0) {
2409                 struct dma_desc *p;
2410 
2411                 if (priv->extend_desc)
2412                         p = (struct dma_desc *)(priv->dma_erx + entry);
2413                 else
2414                         p = priv->dma_rx + entry;
2415 
2416                 if (likely(priv->rx_skbuff[entry] == NULL)) {
2417                         struct sk_buff *skb;
2418 
2419                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2420                         if (unlikely(!skb)) {
2421                                 /* so for a while no zero-copy! */
2422                                 priv->rx_zeroc_thresh = STMMAC_RX_THRESH;
2423                                 if (unlikely(net_ratelimit()))
2424                                         dev_err(priv->device,
2425                                                 "fail to alloc skb entry %d\n",
2426                                                 entry);
2427                                 break;
2428                         }
2429 
2430                         priv->rx_skbuff[entry] = skb;
2431                         priv->rx_skbuff_dma[entry] =
2432                             dma_map_single(priv->device, skb->data, bfsize,
2433                                            DMA_FROM_DEVICE);
2434                         if (dma_mapping_error(priv->device,
2435                                               priv->rx_skbuff_dma[entry])) {
2436                                 dev_err(priv->device, "Rx dma map failed\n");
2437                                 dev_kfree_skb(skb);
2438                                 break;
2439                         }
2440 
2441                         if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) {
2442                                 p->des0 = priv->rx_skbuff_dma[entry];
2443                                 p->des1 = 0;
2444                         } else {
2445                                 p->des2 = priv->rx_skbuff_dma[entry];
2446                         }
2447                         if (priv->hw->mode->refill_desc3)
2448                                 priv->hw->mode->refill_desc3(priv, p);
2449 
2450                         if (priv->rx_zeroc_thresh > 0)
2451                                 priv->rx_zeroc_thresh--;
2452 
2453                         if (netif_msg_rx_status(priv))
2454                                 pr_debug("\trefill entry #%d\n", entry);
2455                 }
2456                 wmb();
2457 
2458                 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2459                         priv->hw->desc->init_rx_desc(p, priv->use_riwt, 0, 0);
2460                 else
2461                         priv->hw->desc->set_rx_owner(p);
2462 
2463                 wmb();
2464 
2465                 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
2466         }
2467         priv->dirty_rx = entry;
2468 }
2469 
2470 /**
2471  * stmmac_rx - manage the receive process
2472  * @priv: driver private structure
2473  * @limit: napi bugget.
2474  * Description :  this the function called by the napi poll method.
2475  * It gets all the frames inside the ring.
2476  */
2477 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2478 {
2479         unsigned int entry = priv->cur_rx;
2480         unsigned int next_entry;
2481         unsigned int count = 0;
2482         int coe = priv->hw->rx_csum;
2483 
2484         if (netif_msg_rx_status(priv)) {
2485                 void *rx_head;
2486 
2487                 pr_info(">>>>>> %s: descriptor ring:\n", __func__);
2488                 if (priv->extend_desc)
2489                         rx_head = (void *)priv->dma_erx;
2490                 else
2491                         rx_head = (void *)priv->dma_rx;
2492 
2493                 priv->hw->desc->display_ring(rx_head, DMA_RX_SIZE, true);
2494         }
2495         while (count < limit) {
2496                 int status;
2497                 struct dma_desc *p;
2498                 struct dma_desc *np;
2499 
2500                 if (priv->extend_desc)
2501                         p = (struct dma_desc *)(priv->dma_erx + entry);
2502                 else
2503                         p = priv->dma_rx + entry;
2504 
2505                 /* read the status of the incoming frame */
2506                 status = priv->hw->desc->rx_status(&priv->dev->stats,
2507                                                    &priv->xstats, p);
2508                 /* check if managed by the DMA otherwise go ahead */
2509                 if (unlikely(status & dma_own))
2510                         break;
2511 
2512                 count++;
2513 
2514                 priv->cur_rx = STMMAC_GET_ENTRY(priv->cur_rx, DMA_RX_SIZE);
2515                 next_entry = priv->cur_rx;
2516 
2517                 if (priv->extend_desc)
2518                         np = (struct dma_desc *)(priv->dma_erx + next_entry);
2519                 else
2520                         np = priv->dma_rx + next_entry;
2521 
2522                 prefetch(np);
2523 
2524                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2525                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
2526                                                            &priv->xstats,
2527                                                            priv->dma_erx +
2528                                                            entry);
2529                 if (unlikely(status == discard_frame)) {
2530                         priv->dev->stats.rx_errors++;
2531                         if (priv->hwts_rx_en && !priv->extend_desc) {
2532                                 /* DESC2 & DESC3 will be overwitten by device
2533                                  * with timestamp value, hence reinitialize
2534                                  * them in stmmac_rx_refill() function so that
2535                                  * device can reuse it.
2536                                  */
2537                                 priv->rx_skbuff[entry] = NULL;
2538                                 dma_unmap_single(priv->device,
2539                                                  priv->rx_skbuff_dma[entry],
2540                                                  priv->dma_buf_sz,
2541                                                  DMA_FROM_DEVICE);
2542                         }
2543                 } else {
2544                         struct sk_buff *skb;
2545                         int frame_len;
2546                         unsigned int des;
2547 
2548                         if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2549                                 des = p->des0;
2550                         else
2551                                 des = p->des2;
2552 
2553                         frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2554 
2555                         /*  If frame length is greather than skb buffer size
2556                          *  (preallocated during init) then the packet is
2557                          *  ignored
2558                          */
2559                         if (frame_len > priv->dma_buf_sz) {
2560                                 pr_err("%s: len %d larger than size (%d)\n",
2561                                        priv->dev->name, frame_len,
2562                                        priv->dma_buf_sz);
2563                                 priv->dev->stats.rx_length_errors++;
2564                                 break;
2565                         }
2566 
2567                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2568                          * Type frames (LLC/LLC-SNAP)
2569                          */
2570                         if (unlikely(status != llc_snap))
2571                                 frame_len -= ETH_FCS_LEN;
2572 
2573                         if (netif_msg_rx_status(priv)) {
2574                                 pr_info("\tdesc: %p [entry %d] buff=0x%x\n",
2575                                         p, entry, des);
2576                                 if (frame_len > ETH_FRAME_LEN)
2577                                         pr_debug("\tframe size %d, COE: %d\n",
2578                                                  frame_len, status);
2579                         }
2580 
2581                         /* The zero-copy is always used for all the sizes
2582                          * in case of GMAC4 because it needs
2583                          * to refill the used descriptors, always.
2584                          */
2585                         if (unlikely(!priv->plat->has_gmac4 &&
2586                                      ((frame_len < priv->rx_copybreak) ||
2587                                      stmmac_rx_threshold_count(priv)))) {
2588                                 skb = netdev_alloc_skb_ip_align(priv->dev,
2589                                                                 frame_len);
2590                                 if (unlikely(!skb)) {
2591                                         if (net_ratelimit())
2592                                                 dev_warn(priv->device,
2593                                                          "packet dropped\n");
2594                                         priv->dev->stats.rx_dropped++;
2595                                         break;
2596                                 }
2597 
2598                                 dma_sync_single_for_cpu(priv->device,
2599                                                         priv->rx_skbuff_dma
2600                                                         [entry], frame_len,
2601                                                         DMA_FROM_DEVICE);
2602                                 skb_copy_to_linear_data(skb,
2603                                                         priv->
2604                                                         rx_skbuff[entry]->data,
2605                                                         frame_len);
2606 
2607                                 skb_put(skb, frame_len);
2608                                 dma_sync_single_for_device(priv->device,
2609                                                            priv->rx_skbuff_dma
2610                                                            [entry], frame_len,
2611                                                            DMA_FROM_DEVICE);
2612                         } else {
2613                                 skb = priv->rx_skbuff[entry];
2614                                 if (unlikely(!skb)) {
2615                                         pr_err("%s: Inconsistent Rx chain\n",
2616                                                priv->dev->name);
2617                                         priv->dev->stats.rx_dropped++;
2618                                         break;
2619                                 }
2620                                 prefetch(skb->data - NET_IP_ALIGN);
2621                                 priv->rx_skbuff[entry] = NULL;
2622                                 priv->rx_zeroc_thresh++;
2623 
2624                                 skb_put(skb, frame_len);
2625                                 dma_unmap_single(priv->device,
2626                                                  priv->rx_skbuff_dma[entry],
2627                                                  priv->dma_buf_sz,
2628                                                  DMA_FROM_DEVICE);
2629                         }
2630 
2631                         if (netif_msg_pktdata(priv)) {
2632                                 pr_debug("frame received (%dbytes)", frame_len);
2633                                 print_pkt(skb->data, frame_len);
2634                         }
2635 
2636                         stmmac_get_rx_hwtstamp(priv, p, np, skb);
2637 
2638                         stmmac_rx_vlan(priv->dev, skb);
2639 
2640                         skb->protocol = eth_type_trans(skb, priv->dev);
2641 
2642                         if (unlikely(!coe))
2643                                 skb_checksum_none_assert(skb);
2644                         else
2645                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2646 
2647                         napi_gro_receive(&priv->napi, skb);
2648 
2649                         priv->dev->stats.rx_packets++;
2650                         priv->dev->stats.rx_bytes += frame_len;
2651                 }
2652                 entry = next_entry;
2653         }
2654 
2655         stmmac_rx_refill(priv);
2656 
2657         priv->xstats.rx_pkt_n += count;
2658 
2659         return count;
2660 }
2661 
2662 /**
2663  *  stmmac_poll - stmmac poll method (NAPI)
2664  *  @napi : pointer to the napi structure.
2665  *  @budget : maximum number of packets that the current CPU can receive from
2666  *            all interfaces.
2667  *  Description :
2668  *  To look at the incoming frames and clear the tx resources.
2669  */
2670 static int stmmac_poll(struct napi_struct *napi, int budget)
2671 {
2672         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2673         int work_done = 0;
2674 
2675         priv->xstats.napi_poll++;
2676         stmmac_tx_clean(priv);
2677 
2678         work_done = stmmac_rx(priv, budget);
2679         if (work_done < budget) {
2680                 napi_complete(napi);
2681                 stmmac_enable_dma_irq(priv);
2682         }
2683         return work_done;
2684 }
2685 
2686 /**
2687  *  stmmac_tx_timeout
2688  *  @dev : Pointer to net device structure
2689  *  Description: this function is called when a packet transmission fails to
2690  *   complete within a reasonable time. The driver will mark the error in the
2691  *   netdev structure and arrange for the device to be reset to a sane state
2692  *   in order to transmit a new packet.
2693  */
2694 static void stmmac_tx_timeout(struct net_device *dev)
2695 {
2696         struct stmmac_priv *priv = netdev_priv(dev);
2697 
2698         /* Clear Tx resources and restart transmitting again */
2699         stmmac_tx_err(priv);
2700 }
2701 
2702 /**
2703  *  stmmac_set_rx_mode - entry point for multicast addressing
2704  *  @dev : pointer to the device structure
2705  *  Description:
2706  *  This function is a driver entry point which gets called by the kernel
2707  *  whenever multicast addresses must be enabled/disabled.
2708  *  Return value:
2709  *  void.
2710  */
2711 static void stmmac_set_rx_mode(struct net_device *dev)
2712 {
2713         struct stmmac_priv *priv = netdev_priv(dev);
2714 
2715         priv->hw->mac->set_filter(priv->hw, dev);
2716 }
2717 
2718 /**
2719  *  stmmac_change_mtu - entry point to change MTU size for the device.
2720  *  @dev : device pointer.
2721  *  @new_mtu : the new MTU size for the device.
2722  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
2723  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
2724  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
2725  *  Return value:
2726  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2727  *  file on failure.
2728  */
2729 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2730 {
2731         struct stmmac_priv *priv = netdev_priv(dev);
2732         int max_mtu;
2733 
2734         if (netif_running(dev)) {
2735                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2736                 return -EBUSY;
2737         }
2738 
2739         if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
2740                 max_mtu = JUMBO_LEN;
2741         else
2742                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2743 
2744         if (priv->plat->maxmtu < max_mtu)
2745                 max_mtu = priv->plat->maxmtu;
2746 
2747         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2748                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2749                 return -EINVAL;
2750         }
2751 
2752         dev->mtu = new_mtu;
2753 
2754         netdev_update_features(dev);
2755 
2756         return 0;
2757 }
2758 
2759 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2760                                              netdev_features_t features)
2761 {
2762         struct stmmac_priv *priv = netdev_priv(dev);
2763 
2764         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2765                 features &= ~NETIF_F_RXCSUM;
2766 
2767         if (!priv->plat->tx_coe)
2768                 features &= ~NETIF_F_CSUM_MASK;
2769 
2770         /* Some GMAC devices have a bugged Jumbo frame support that
2771          * needs to have the Tx COE disabled for oversized frames
2772          * (due to limited buffer sizes). In this case we disable
2773          * the TX csum insertionin the TDES and not use SF.
2774          */
2775         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2776                 features &= ~NETIF_F_CSUM_MASK;
2777 
2778         /* Disable tso if asked by ethtool */
2779         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
2780                 if (features & NETIF_F_TSO)
2781                         priv->tso = true;
2782                 else
2783                         priv->tso = false;
2784         }
2785 
2786         return features;
2787 }
2788 
2789 static int stmmac_set_features(struct net_device *netdev,
2790                                netdev_features_t features)
2791 {
2792         struct stmmac_priv *priv = netdev_priv(netdev);
2793 
2794         /* Keep the COE Type in case of csum is supporting */
2795         if (features & NETIF_F_RXCSUM)
2796                 priv->hw->rx_csum = priv->plat->rx_coe;
2797         else
2798                 priv->hw->rx_csum = 0;
2799         /* No check needed because rx_coe has been set before and it will be
2800          * fixed in case of issue.
2801          */
2802         priv->hw->mac->rx_ipc(priv->hw);
2803 
2804         return 0;
2805 }
2806 
2807 /**
2808  *  stmmac_interrupt - main ISR
2809  *  @irq: interrupt number.
2810  *  @dev_id: to pass the net device pointer.
2811  *  Description: this is the main driver interrupt service routine.
2812  *  It can call:
2813  *  o DMA service routine (to manage incoming frame reception and transmission
2814  *    status)
2815  *  o Core interrupts to manage: remote wake-up, management counter, LPI
2816  *    interrupts.
2817  */
2818 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2819 {
2820         struct net_device *dev = (struct net_device *)dev_id;
2821         struct stmmac_priv *priv = netdev_priv(dev);
2822 
2823         if (priv->irq_wake)
2824                 pm_wakeup_event(priv->device, 0);
2825 
2826         if (unlikely(!dev)) {
2827                 pr_err("%s: invalid dev pointer\n", __func__);
2828                 return IRQ_NONE;
2829         }
2830 
2831         /* To handle GMAC own interrupts */
2832         if ((priv->plat->has_gmac) || (priv->plat->has_gmac4)) {
2833                 int status = priv->hw->mac->host_irq_status(priv->hw,
2834                                                             &priv->xstats);
2835                 if (unlikely(status)) {
2836                         /* For LPI we need to save the tx status */
2837                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2838                                 priv->tx_path_in_lpi_mode = true;
2839                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2840                                 priv->tx_path_in_lpi_mode = false;
2841                         if (status & CORE_IRQ_MTL_RX_OVERFLOW && priv->hw->dma->set_rx_tail_ptr)
2842                                 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr,
2843                                                         priv->rx_tail_addr,
2844                                                         STMMAC_CHAN0);
2845                 }
2846 
2847                 /* PCS link status */
2848                 if (priv->hw->pcs) {
2849                         if (priv->xstats.pcs_link)
2850                                 netif_carrier_on(dev);
2851                         else
2852                                 netif_carrier_off(dev);
2853                 }
2854         }
2855 
2856         /* To handle DMA interrupts */
2857         stmmac_dma_interrupt(priv);
2858 
2859         return IRQ_HANDLED;
2860 }
2861 
2862 #ifdef CONFIG_NET_POLL_CONTROLLER
2863 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2864  * to allow network I/O with interrupts disabled.
2865  */
2866 static void stmmac_poll_controller(struct net_device *dev)
2867 {
2868         disable_irq(dev->irq);
2869         stmmac_interrupt(dev->irq, dev);
2870         enable_irq(dev->irq);
2871 }
2872 #endif
2873 
2874 /**
2875  *  stmmac_ioctl - Entry point for the Ioctl
2876  *  @dev: Device pointer.
2877  *  @rq: An IOCTL specefic structure, that can contain a pointer to
2878  *  a proprietary structure used to pass information to the driver.
2879  *  @cmd: IOCTL command
2880  *  Description:
2881  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2882  */
2883 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2884 {
2885         struct stmmac_priv *priv = netdev_priv(dev);
2886         int ret = -EOPNOTSUPP;
2887 
2888         if (!netif_running(dev))
2889                 return -EINVAL;
2890 
2891         switch (cmd) {
2892         case SIOCGMIIPHY:
2893         case SIOCGMIIREG:
2894         case SIOCSMIIREG:
2895                 if (!priv->phydev)
2896                         return -EINVAL;
2897                 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2898                 break;
2899         case SIOCSHWTSTAMP:
2900                 ret = stmmac_hwtstamp_ioctl(dev, rq);
2901                 break;
2902         default:
2903                 break;
2904         }
2905 
2906         return ret;
2907 }
2908 
2909 #ifdef CONFIG_DEBUG_FS
2910 static struct dentry *stmmac_fs_dir;
2911 
2912 static void sysfs_display_ring(void *head, int size, int extend_desc,
2913                                struct seq_file *seq)
2914 {
2915         int i;
2916         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2917         struct dma_desc *p = (struct dma_desc *)head;
2918 
2919         for (i = 0; i < size; i++) {
2920                 u64 x;
2921                 if (extend_desc) {
2922                         x = *(u64 *) ep;
2923                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2924                                    i, (unsigned int)virt_to_phys(ep),
2925                                    ep->basic.des0, ep->basic.des1,
2926                                    ep->basic.des2, ep->basic.des3);
2927                         ep++;
2928                 } else {
2929                         x = *(u64 *) p;
2930                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2931                                    i, (unsigned int)virt_to_phys(ep),
2932                                    p->des0, p->des1, p->des2, p->des3);
2933                         p++;
2934                 }
2935                 seq_printf(seq, "\n");
2936         }
2937 }
2938 
2939 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2940 {
2941         struct net_device *dev = seq->private;
2942         struct stmmac_priv *priv = netdev_priv(dev);
2943 
2944         if (priv->extend_desc) {
2945                 seq_printf(seq, "Extended RX descriptor ring:\n");
2946                 sysfs_display_ring((void *)priv->dma_erx, DMA_RX_SIZE, 1, seq);
2947                 seq_printf(seq, "Extended TX descriptor ring:\n");
2948                 sysfs_display_ring((void *)priv->dma_etx, DMA_TX_SIZE, 1, seq);
2949         } else {
2950                 seq_printf(seq, "RX descriptor ring:\n");
2951                 sysfs_display_ring((void *)priv->dma_rx, DMA_RX_SIZE, 0, seq);
2952                 seq_printf(seq, "TX descriptor ring:\n");
2953                 sysfs_display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 0, seq);
2954         }
2955 
2956         return 0;
2957 }
2958 
2959 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2960 {
2961         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2962 }
2963 
2964 static const struct file_operations stmmac_rings_status_fops = {
2965         .owner = THIS_MODULE,
2966         .open = stmmac_sysfs_ring_open,
2967         .read = seq_read,
2968         .llseek = seq_lseek,
2969         .release = single_release,
2970 };
2971 
2972 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2973 {
2974         struct net_device *dev = seq->private;
2975         struct stmmac_priv *priv = netdev_priv(dev);
2976 
2977         if (!priv->hw_cap_support) {
2978                 seq_printf(seq, "DMA HW features not supported\n");
2979                 return 0;
2980         }
2981 
2982         seq_printf(seq, "==============================\n");
2983         seq_printf(seq, "\tDMA HW features\n");
2984         seq_printf(seq, "==============================\n");
2985 
2986         seq_printf(seq, "\t10/100 Mbps %s\n",
2987                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2988         seq_printf(seq, "\t1000 Mbps %s\n",
2989                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
2990         seq_printf(seq, "\tHalf duple %s\n",
2991                    (priv->dma_cap.half_duplex) ? "Y" : "N");
2992         seq_printf(seq, "\tHash Filter: %s\n",
2993                    (priv->dma_cap.hash_filter) ? "Y" : "N");
2994         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2995                    (priv->dma_cap.multi_addr) ? "Y" : "N");
2996         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2997                    (priv->dma_cap.pcs) ? "Y" : "N");
2998         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2999                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
3000         seq_printf(seq, "\tPMT Remote wake up: %s\n",
3001                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
3002         seq_printf(seq, "\tPMT Magic Frame: %s\n",
3003                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
3004         seq_printf(seq, "\tRMON module: %s\n",
3005                    (priv->dma_cap.rmon) ? "Y" : "N");
3006         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
3007                    (priv->dma_cap.time_stamp) ? "Y" : "N");
3008         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
3009                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
3010         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
3011                    (priv->dma_cap.eee) ? "Y" : "N");
3012         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
3013         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
3014                    (priv->dma_cap.tx_coe) ? "Y" : "N");
3015         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3016                 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
3017                            (priv->dma_cap.rx_coe) ? "Y" : "N");
3018         } else {
3019                 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
3020                            (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
3021                 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
3022                            (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
3023         }
3024         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
3025                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
3026         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
3027                    priv->dma_cap.number_rx_channel);
3028         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
3029                    priv->dma_cap.number_tx_channel);
3030         seq_printf(seq, "\tEnhanced descriptors: %s\n",
3031                    (priv->dma_cap.enh_desc) ? "Y" : "N");
3032 
3033         return 0;
3034 }
3035 
3036 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
3037 {
3038         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
3039 }
3040 
3041 static const struct file_operations stmmac_dma_cap_fops = {
3042         .owner = THIS_MODULE,
3043         .open = stmmac_sysfs_dma_cap_open,
3044         .read = seq_read,
3045         .llseek = seq_lseek,
3046         .release = single_release,
3047 };
3048 
3049 static int stmmac_init_fs(struct net_device *dev)
3050 {
3051         struct stmmac_priv *priv = netdev_priv(dev);
3052 
3053         /* Create per netdev entries */
3054         priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
3055 
3056         if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
3057                 pr_err("ERROR %s/%s, debugfs create directory failed\n",
3058                        STMMAC_RESOURCE_NAME, dev->name);
3059 
3060                 return -ENOMEM;
3061         }
3062 
3063         /* Entry to report DMA RX/TX rings */
3064         priv->dbgfs_rings_status =
3065                 debugfs_create_file("descriptors_status", S_IRUGO,
3066                                     priv->dbgfs_dir, dev,
3067                                     &stmmac_rings_status_fops);
3068 
3069         if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
3070                 pr_info("ERROR creating stmmac ring debugfs file\n");
3071                 debugfs_remove_recursive(priv->dbgfs_dir);
3072 
3073                 return -ENOMEM;
3074         }
3075 
3076         /* Entry to report the DMA HW features */
3077         priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO,
3078                                             priv->dbgfs_dir,
3079                                             dev, &stmmac_dma_cap_fops);
3080 
3081         if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
3082                 pr_info("ERROR creating stmmac MMC debugfs file\n");
3083                 debugfs_remove_recursive(priv->dbgfs_dir);
3084 
3085                 return -ENOMEM;
3086         }
3087 
3088         return 0;
3089 }
3090 
3091 static void stmmac_exit_fs(struct net_device *dev)
3092 {
3093         struct stmmac_priv *priv = netdev_priv(dev);
3094 
3095         debugfs_remove_recursive(priv->dbgfs_dir);
3096 }
3097 #endif /* CONFIG_DEBUG_FS */
3098 
3099 static const struct net_device_ops stmmac_netdev_ops = {
3100         .ndo_open = stmmac_open,
3101         .ndo_start_xmit = stmmac_xmit,
3102         .ndo_stop = stmmac_release,
3103         .ndo_change_mtu = stmmac_change_mtu,
3104         .ndo_fix_features = stmmac_fix_features,
3105         .ndo_set_features = stmmac_set_features,
3106         .ndo_set_rx_mode = stmmac_set_rx_mode,
3107         .ndo_tx_timeout = stmmac_tx_timeout,
3108         .ndo_do_ioctl = stmmac_ioctl,
3109 #ifdef CONFIG_NET_POLL_CONTROLLER
3110         .ndo_poll_controller = stmmac_poll_controller,
3111 #endif
3112         .ndo_set_mac_address = eth_mac_addr,
3113 };
3114 
3115 /**
3116  *  stmmac_hw_init - Init the MAC device
3117  *  @priv: driver private structure
3118  *  Description: this function is to configure the MAC device according to
3119  *  some platform parameters or the HW capability register. It prepares the
3120  *  driver to use either ring or chain modes and to setup either enhanced or
3121  *  normal descriptors.
3122  */
3123 static int stmmac_hw_init(struct stmmac_priv *priv)
3124 {
3125         struct mac_device_info *mac;
3126 
3127         /* Identify the MAC HW device */
3128         if (priv->plat->has_gmac) {
3129                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
3130                 mac = dwmac1000_setup(priv->ioaddr,
3131                                       priv->plat->multicast_filter_bins,
3132                                       priv->plat->unicast_filter_entries,
3133                                       &priv->synopsys_id);
3134         } else if (priv->plat->has_gmac4) {
3135                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
3136                 mac = dwmac4_setup(priv->ioaddr,
3137                                    priv->plat->multicast_filter_bins,
3138                                    priv->plat->unicast_filter_entries,
3139                                    &priv->synopsys_id);
3140         } else {
3141                 mac = dwmac100_setup(priv->ioaddr, &priv->synopsys_id);
3142         }
3143         if (!mac)
3144                 return -ENOMEM;
3145 
3146         priv->hw = mac;
3147 
3148         /* To use the chained or ring mode */
3149         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3150                 priv->hw->mode = &dwmac4_ring_mode_ops;
3151         } else {
3152                 if (chain_mode) {
3153                         priv->hw->mode = &chain_mode_ops;
3154                         pr_info(" Chain mode enabled\n");
3155                         priv->mode = STMMAC_CHAIN_MODE;
3156                 } else {
3157                         priv->hw->mode = &ring_mode_ops;
3158                         pr_info(" Ring mode enabled\n");
3159                         priv->mode = STMMAC_RING_MODE;
3160                 }
3161         }
3162 
3163         /* Get the HW capability (new GMAC newer than 3.50a) */
3164         priv->hw_cap_support = stmmac_get_hw_features(priv);
3165         if (priv->hw_cap_support) {
3166                 pr_info(" DMA HW capability register supported");
3167 
3168                 /* We can override some gmac/dma configuration fields: e.g.
3169                  * enh_desc, tx_coe (e.g. that are passed through the
3170                  * platform) with the values from the HW capability
3171                  * register (if supported).
3172                  */
3173                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
3174                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
3175                 priv->hw->pmt = priv->plat->pmt;
3176 
3177                 /* TXCOE doesn't work in thresh DMA mode */
3178                 if (priv->plat->force_thresh_dma_mode)
3179                         priv->plat->tx_coe = 0;
3180                 else
3181                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
3182 
3183                 /* In case of GMAC4 rx_coe is from HW cap register. */
3184                 priv->plat->rx_coe = priv->dma_cap.rx_coe;
3185 
3186                 if (priv->dma_cap.rx_coe_type2)
3187                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
3188                 else if (priv->dma_cap.rx_coe_type1)
3189                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
3190 
3191         } else
3192                 pr_info(" No HW DMA feature register supported");
3193 
3194         /* To use alternate (extended), normal or GMAC4 descriptor structures */
3195         if (priv->synopsys_id >= DWMAC_CORE_4_00)
3196                 priv->hw->desc = &dwmac4_desc_ops;
3197         else
3198                 stmmac_selec_desc_mode(priv);
3199 
3200         if (priv->plat->rx_coe) {
3201                 priv->hw->rx_csum = priv->plat->rx_coe;
3202                 pr_info(" RX Checksum Offload Engine supported\n");
3203                 if (priv->synopsys_id < DWMAC_CORE_4_00)
3204                         pr_info("\tCOE Type %d\n", priv->hw->rx_csum);
3205         }
3206         if (priv->plat->tx_coe)
3207                 pr_info(" TX Checksum insertion supported\n");
3208 
3209         if (priv->plat->pmt) {
3210                 pr_info(" Wake-Up On Lan supported\n");
3211                 device_set_wakeup_capable(priv->device, 1);
3212         }
3213 
3214         if (priv->dma_cap.tsoen)
3215                 pr_info(" TSO supported\n");
3216 
3217         return 0;
3218 }
3219 
3220 /**
3221  * stmmac_dvr_probe
3222  * @device: device pointer
3223  * @plat_dat: platform data pointer
3224  * @res: stmmac resource pointer
3225  * Description: this is the main probe function used to
3226  * call the alloc_etherdev, allocate the priv structure.
3227  * Return:
3228  * returns 0 on success, otherwise errno.
3229  */
3230 int stmmac_dvr_probe(struct device *device,
3231                      struct plat_stmmacenet_data *plat_dat,
3232                      struct stmmac_resources *res)
3233 {
3234         int ret = 0;
3235         struct net_device *ndev = NULL;
3236         struct stmmac_priv *priv;
3237 
3238         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
3239         if (!ndev)
3240                 return -ENOMEM;
3241 
3242         SET_NETDEV_DEV(ndev, device);
3243 
3244         priv = netdev_priv(ndev);
3245         priv->device = device;
3246         priv->dev = ndev;
3247 
3248         stmmac_set_ethtool_ops(ndev);
3249         priv->pause = pause;
3250         priv->plat = plat_dat;
3251         priv->ioaddr = res->addr;
3252         priv->dev->base_addr = (unsigned long)res->addr;
3253 
3254         priv->dev->irq = res->irq;
3255         priv->wol_irq = res->wol_irq;
3256         priv->lpi_irq = res->lpi_irq;
3257 
3258         if (res->mac)
3259                 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
3260 
3261         dev_set_drvdata(device, priv->dev);
3262 
3263         /* Verify driver arguments */
3264         stmmac_verify_args();
3265 
3266         /* Override with kernel parameters if supplied XXX CRS XXX
3267          * this needs to have multiple instances
3268          */
3269         if ((phyaddr >= 0) && (phyaddr <= 31))
3270                 priv->plat->phy_addr = phyaddr;
3271 
3272         priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
3273         if (IS_ERR(priv->stmmac_clk)) {
3274                 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
3275                          __func__);
3276                 /* If failed to obtain stmmac_clk and specific clk_csr value
3277                  * is NOT passed from the platform, probe fail.
3278                  */
3279                 if (!priv->plat->clk_csr) {
3280                         ret = PTR_ERR(priv->stmmac_clk);
3281                         goto error_clk_get;
3282                 } else {
3283                         priv->stmmac_clk = NULL;
3284                 }
3285         }
3286         clk_prepare_enable(priv->stmmac_clk);
3287 
3288         priv->pclk = devm_clk_get(priv->device, "pclk");
3289         if (IS_ERR(priv->pclk)) {
3290                 if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) {
3291                         ret = -EPROBE_DEFER;
3292                         goto error_pclk_get;
3293                 }
3294                 priv->pclk = NULL;
3295         }
3296         clk_prepare_enable(priv->pclk);
3297 
3298         priv->stmmac_rst = devm_reset_control_get(priv->device,
3299                                                   STMMAC_RESOURCE_NAME);
3300         if (IS_ERR(priv->stmmac_rst)) {
3301                 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
3302                         ret = -EPROBE_DEFER;
3303                         goto error_hw_init;
3304                 }
3305                 dev_info(priv->device, "no reset control found\n");
3306                 priv->stmmac_rst = NULL;
3307         }
3308         if (priv->stmmac_rst)
3309                 reset_control_deassert(priv->stmmac_rst);
3310 
3311         /* Init MAC and get the capabilities */
3312         ret = stmmac_hw_init(priv);
3313         if (ret)
3314                 goto error_hw_init;
3315 
3316         ndev->netdev_ops = &stmmac_netdev_ops;
3317 
3318         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3319                             NETIF_F_RXCSUM;
3320 
3321         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3322                 ndev->hw_features |= NETIF_F_TSO;
3323                 priv->tso = true;
3324                 pr_info(" TSO feature enabled\n");
3325         }
3326         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
3327         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
3328 #ifdef STMMAC_VLAN_TAG_USED
3329         /* Both mac100 and gmac support receive VLAN tag detection */
3330         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3331 #endif
3332         priv->msg_enable = netif_msg_init(debug, default_msg_level);
3333 
3334         if (flow_ctrl)
3335                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
3336 
3337         /* Rx Watchdog is available in the COREs newer than the 3.40.
3338          * In some case, for example on bugged HW this feature
3339          * has to be disable and this can be done by passing the
3340          * riwt_off field from the platform.
3341          */
3342         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
3343                 priv->use_riwt = 1;
3344                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
3345         }
3346 
3347         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
3348 
3349         spin_lock_init(&priv->lock);
3350         spin_lock_init(&priv->tx_lock);
3351 
3352         ret = register_netdev(ndev);
3353         if (ret) {
3354                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
3355                 goto error_netdev_register;
3356         }
3357 
3358         /* If a specific clk_csr value is passed from the platform
3359          * this means that the CSR Clock Range selection cannot be
3360          * changed at run-time and it is fixed. Viceversa the driver'll try to
3361          * set the MDC clock dynamically according to the csr actual
3362          * clock input.
3363          */
3364         if (!priv->plat->clk_csr)
3365                 stmmac_clk_csr_set(priv);
3366         else
3367                 priv->clk_csr = priv->plat->clk_csr;
3368 
3369         stmmac_check_pcs_mode(priv);
3370 
3371         if (priv->hw->pcs != STMMAC_PCS_RGMII  &&
3372             priv->hw->pcs != STMMAC_PCS_TBI &&
3373             priv->hw->pcs != STMMAC_PCS_RTBI) {
3374                 /* MDIO bus Registration */
3375                 ret = stmmac_mdio_register(ndev);
3376                 if (ret < 0) {
3377                         pr_debug("%s: MDIO bus (id: %d) registration failed",
3378                                  __func__, priv->plat->bus_id);
3379                         goto error_mdio_register;
3380                 }
3381         }
3382 
3383         return 0;
3384 
3385 error_mdio_register:
3386         unregister_netdev(ndev);
3387 error_netdev_register:
3388         netif_napi_del(&priv->napi);
3389 error_hw_init:
3390         clk_disable_unprepare(priv->pclk);
3391 error_pclk_get:
3392         clk_disable_unprepare(priv->stmmac_clk);
3393 error_clk_get:
3394         free_netdev(ndev);
3395 
3396         return ret;
3397 }
3398 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
3399 
3400 /**
3401  * stmmac_dvr_remove
3402  * @dev: device pointer
3403  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
3404  * changes the link status, releases the DMA descriptor rings.
3405  */
3406 int stmmac_dvr_remove(struct device *dev)
3407 {
3408         struct net_device *ndev = dev_get_drvdata(dev);
3409         struct stmmac_priv *priv = netdev_priv(ndev);
3410 
3411         pr_info("%s:\n\tremoving driver", __func__);
3412 
3413         priv->hw->dma->stop_rx(priv->ioaddr);
3414         priv->hw->dma->stop_tx(priv->ioaddr);
3415 
3416         stmmac_set_mac(priv->ioaddr, false);
3417         netif_carrier_off(ndev);
3418         unregister_netdev(ndev);
3419         if (priv->stmmac_rst)
3420                 reset_control_assert(priv->stmmac_rst);
3421         clk_disable_unprepare(priv->pclk);
3422         clk_disable_unprepare(priv->stmmac_clk);
3423         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
3424             priv->hw->pcs != STMMAC_PCS_TBI &&
3425             priv->hw->pcs != STMMAC_PCS_RTBI)
3426                 stmmac_mdio_unregister(ndev);
3427         free_netdev(ndev);
3428 
3429         return 0;
3430 }
3431 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
3432 
3433 /**
3434  * stmmac_suspend - suspend callback
3435  * @dev: device pointer
3436  * Description: this is the function to suspend the device and it is called
3437  * by the platform driver to stop the network queue, release the resources,
3438  * program the PMT register (for WoL), clean and release driver resources.
3439  */
3440 int stmmac_suspend(struct device *dev)
3441 {
3442         struct net_device *ndev = dev_get_drvdata(dev);
3443         struct stmmac_priv *priv = netdev_priv(ndev);
3444         unsigned long flags;
3445 
3446         if (!ndev || !netif_running(ndev))
3447                 return 0;
3448 
3449         if (priv->phydev)
3450                 phy_stop(priv->phydev);
3451 
3452         spin_lock_irqsave(&priv->lock, flags);
3453 
3454         netif_device_detach(ndev);
3455         netif_stop_queue(ndev);
3456 
3457         napi_disable(&priv->napi);
3458 
3459         /* Stop TX/RX DMA */
3460         priv->hw->dma->stop_tx(priv->ioaddr);
3461         priv->hw->dma->stop_rx(priv->ioaddr);
3462 
3463         /* Enable Power down mode by programming the PMT regs */
3464         if (device_may_wakeup(priv->device)) {
3465                 priv->hw->mac->pmt(priv->hw, priv->wolopts);
3466                 priv->irq_wake = 1;
3467         } else {
3468                 stmmac_set_mac(priv->ioaddr, false);
3469                 pinctrl_pm_select_sleep_state(priv->device);
3470                 /* Disable clock in case of PWM is off */
3471                 clk_disable(priv->pclk);
3472                 clk_disable(priv->stmmac_clk);
3473         }
3474         spin_unlock_irqrestore(&priv->lock, flags);
3475 
3476         priv->oldlink = 0;
3477         priv->speed = 0;
3478         priv->oldduplex = -1;
3479         return 0;
3480 }
3481 EXPORT_SYMBOL_GPL(stmmac_suspend);
3482 
3483 /**
3484  * stmmac_resume - resume callback
3485  * @dev: device pointer
3486  * Description: when resume this function is invoked to setup the DMA and CORE
3487  * in a usable state.
3488  */
3489 int stmmac_resume(struct device *dev)
3490 {
3491         struct net_device *ndev = dev_get_drvdata(dev);
3492         struct stmmac_priv *priv = netdev_priv(ndev);
3493         unsigned long flags;
3494 
3495         if (!netif_running(ndev))
3496                 return 0;
3497 
3498         /* Power Down bit, into the PM register, is cleared
3499          * automatically as soon as a magic packet or a Wake-up frame
3500          * is received. Anyway, it's better to manually clear
3501          * this bit because it can generate problems while resuming
3502          * from another devices (e.g. serial console).
3503          */
3504         if (device_may_wakeup(priv->device)) {
3505                 spin_lock_irqsave(&priv->lock, flags);
3506                 priv->hw->mac->pmt(priv->hw, 0);
3507                 spin_unlock_irqrestore(&priv->lock, flags);
3508                 priv->irq_wake = 0;
3509         } else {
3510                 pinctrl_pm_select_default_state(priv->device);
3511                 /* enable the clk prevously disabled */
3512                 clk_enable(priv->stmmac_clk);
3513                 clk_enable(priv->pclk);
3514                 /* reset the phy so that it's ready */
3515                 if (priv->mii)
3516                         stmmac_mdio_reset(priv->mii);
3517         }
3518 
3519         netif_device_attach(ndev);
3520 
3521         spin_lock_irqsave(&priv->lock, flags);
3522 
3523         priv->cur_rx = 0;
3524         priv->dirty_rx = 0;
3525         priv->dirty_tx = 0;
3526         priv->cur_tx = 0;
3527         /* reset private mss value to force mss context settings at
3528          * next tso xmit (only used for gmac4).
3529          */
3530         priv->mss = 0;
3531 
3532         stmmac_clear_descriptors(priv);
3533 
3534         stmmac_hw_setup(ndev, false);
3535         stmmac_init_tx_coalesce(priv);
3536         stmmac_set_rx_mode(ndev);
3537 
3538         napi_enable(&priv->napi);
3539 
3540         netif_start_queue(ndev);
3541 
3542         spin_unlock_irqrestore(&priv->lock, flags);
3543 
3544         if (priv->phydev)
3545                 phy_start(priv->phydev);
3546 
3547         return 0;
3548 }
3549 EXPORT_SYMBOL_GPL(stmmac_resume);
3550 
3551 #ifndef MODULE
3552 static int __init stmmac_cmdline_opt(char *str)
3553 {
3554         char *opt;
3555 
3556         if (!str || !*str)
3557                 return -EINVAL;
3558         while ((opt = strsep(&str, ",")) != NULL) {
3559                 if (!strncmp(opt, "debug:", 6)) {
3560                         if (kstrtoint(opt + 6, 0, &debug))
3561                                 goto err;
3562                 } else if (!strncmp(opt, "phyaddr:", 8)) {
3563                         if (kstrtoint(opt + 8, 0, &phyaddr))
3564                                 goto err;
3565                 } else if (!strncmp(opt, "buf_sz:", 7)) {
3566                         if (kstrtoint(opt + 7, 0, &buf_sz))
3567                                 goto err;
3568                 } else if (!strncmp(opt, "tc:", 3)) {
3569                         if (kstrtoint(opt + 3, 0, &tc))
3570                                 goto err;
3571                 } else if (!strncmp(opt, "watchdog:", 9)) {
3572                         if (kstrtoint(opt + 9, 0, &watchdog))
3573                                 goto err;
3574                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
3575                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
3576                                 goto err;
3577                 } else if (!strncmp(opt, "pause:", 6)) {
3578                         if (kstrtoint(opt + 6, 0, &pause))
3579                                 goto err;
3580                 } else if (!strncmp(opt, "eee_timer:", 10)) {
3581                         if (kstrtoint(opt + 10, 0, &eee_timer))
3582                                 goto err;
3583                 } else if (!strncmp(opt, "chain_mode:", 11)) {
3584                         if (kstrtoint(opt + 11, 0, &chain_mode))
3585                                 goto err;
3586                 }
3587         }
3588         return 0;
3589 
3590 err:
3591         pr_err("%s: ERROR broken module parameter conversion", __func__);
3592         return -EINVAL;
3593 }
3594 
3595 __setup("stmmaceth=", stmmac_cmdline_opt);
3596 #endif /* MODULE */
3597 
3598 static int __init stmmac_init(void)
3599 {
3600 #ifdef CONFIG_DEBUG_FS
3601         /* Create debugfs main directory if it doesn't exist yet */
3602         if (!stmmac_fs_dir) {
3603                 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
3604 
3605                 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
3606                         pr_err("ERROR %s, debugfs create directory failed\n",
3607                                STMMAC_RESOURCE_NAME);
3608 
3609                         return -ENOMEM;
3610                 }
3611         }
3612 #endif
3613 
3614         return 0;
3615 }
3616 
3617 static void __exit stmmac_exit(void)
3618 {
3619 #ifdef CONFIG_DEBUG_FS
3620         debugfs_remove_recursive(stmmac_fs_dir);
3621 #endif
3622 }
3623 
3624 module_init(stmmac_init)
3625 module_exit(stmmac_exit)
3626 
3627 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3628 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3629 MODULE_LICENSE("GPL");
3630 

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