Version:  2.0.40 2.2.26 2.4.37 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15

Linux/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

  1 /*******************************************************************************
  2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
  3   ST Ethernet IPs are built around a Synopsys IP Core.
  4 
  5         Copyright(C) 2007-2011 STMicroelectronics Ltd
  6 
  7   This program is free software; you can redistribute it and/or modify it
  8   under the terms and conditions of the GNU General Public License,
  9   version 2, as published by the Free Software Foundation.
 10 
 11   This program is distributed in the hope it will be useful, but WITHOUT
 12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 14   more details.
 15 
 16   You should have received a copy of the GNU General Public License along with
 17   this program; if not, write to the Free Software Foundation, Inc.,
 18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 19 
 20   The full GNU General Public License is included in this distribution in
 21   the file called "COPYING".
 22 
 23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
 24 
 25   Documentation available at:
 26         http://www.stlinux.com
 27   Support available at:
 28         https://bugzilla.stlinux.com/
 29 *******************************************************************************/
 30 
 31 #include <linux/clk.h>
 32 #include <linux/kernel.h>
 33 #include <linux/interrupt.h>
 34 #include <linux/ip.h>
 35 #include <linux/tcp.h>
 36 #include <linux/skbuff.h>
 37 #include <linux/ethtool.h>
 38 #include <linux/if_ether.h>
 39 #include <linux/crc32.h>
 40 #include <linux/mii.h>
 41 #include <linux/if.h>
 42 #include <linux/if_vlan.h>
 43 #include <linux/dma-mapping.h>
 44 #include <linux/slab.h>
 45 #include <linux/prefetch.h>
 46 #include <linux/pinctrl/consumer.h>
 47 #ifdef CONFIG_STMMAC_DEBUG_FS
 48 #include <linux/debugfs.h>
 49 #include <linux/seq_file.h>
 50 #endif /* CONFIG_STMMAC_DEBUG_FS */
 51 #include <linux/net_tstamp.h>
 52 #include "stmmac_ptp.h"
 53 #include "stmmac.h"
 54 #include <linux/reset.h>
 55 
 56 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
 57 
 58 /* Module parameters */
 59 #define TX_TIMEO        5000
 60 static int watchdog = TX_TIMEO;
 61 module_param(watchdog, int, S_IRUGO | S_IWUSR);
 62 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
 63 
 64 static int debug = -1;
 65 module_param(debug, int, S_IRUGO | S_IWUSR);
 66 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
 67 
 68 static int phyaddr = -1;
 69 module_param(phyaddr, int, S_IRUGO);
 70 MODULE_PARM_DESC(phyaddr, "Physical device address");
 71 
 72 #define DMA_TX_SIZE 256
 73 static int dma_txsize = DMA_TX_SIZE;
 74 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
 75 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
 76 
 77 #define DMA_RX_SIZE 256
 78 static int dma_rxsize = DMA_RX_SIZE;
 79 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
 80 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
 81 
 82 static int flow_ctrl = FLOW_OFF;
 83 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
 84 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
 85 
 86 static int pause = PAUSE_TIME;
 87 module_param(pause, int, S_IRUGO | S_IWUSR);
 88 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
 89 
 90 #define TC_DEFAULT 64
 91 static int tc = TC_DEFAULT;
 92 module_param(tc, int, S_IRUGO | S_IWUSR);
 93 MODULE_PARM_DESC(tc, "DMA threshold control value");
 94 
 95 #define DEFAULT_BUFSIZE 1536
 96 static int buf_sz = DEFAULT_BUFSIZE;
 97 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
 98 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
 99 
100 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
101                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
102                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
103 
104 #define STMMAC_DEFAULT_LPI_TIMER        1000
105 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
106 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
107 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
108 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
109 
110 /* By default the driver will use the ring mode to manage tx and rx descriptors
111  * but passing this value so user can force to use the chain instead of the ring
112  */
113 static unsigned int chain_mode;
114 module_param(chain_mode, int, S_IRUGO);
115 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
116 
117 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
118 
119 #ifdef CONFIG_STMMAC_DEBUG_FS
120 static int stmmac_init_fs(struct net_device *dev);
121 static void stmmac_exit_fs(void);
122 #endif
123 
124 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
125 
126 /**
127  * stmmac_verify_args - verify the driver parameters.
128  * Description: it verifies if some wrong parameter is passed to the driver.
129  * Note that wrong parameters are replaced with the default values.
130  */
131 static void stmmac_verify_args(void)
132 {
133         if (unlikely(watchdog < 0))
134                 watchdog = TX_TIMEO;
135         if (unlikely(dma_rxsize < 0))
136                 dma_rxsize = DMA_RX_SIZE;
137         if (unlikely(dma_txsize < 0))
138                 dma_txsize = DMA_TX_SIZE;
139         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
140                 buf_sz = DEFAULT_BUFSIZE;
141         if (unlikely(flow_ctrl > 1))
142                 flow_ctrl = FLOW_AUTO;
143         else if (likely(flow_ctrl < 0))
144                 flow_ctrl = FLOW_OFF;
145         if (unlikely((pause < 0) || (pause > 0xffff)))
146                 pause = PAUSE_TIME;
147         if (eee_timer < 0)
148                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
149 }
150 
151 /**
152  * stmmac_clk_csr_set - dynamically set the MDC clock
153  * @priv: driver private structure
154  * Description: this is to dynamically set the MDC clock according to the csr
155  * clock input.
156  * Note:
157  *      If a specific clk_csr value is passed from the platform
158  *      this means that the CSR Clock Range selection cannot be
159  *      changed at run-time and it is fixed (as reported in the driver
160  *      documentation). Viceversa the driver will try to set the MDC
161  *      clock dynamically according to the actual clock input.
162  */
163 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
164 {
165         u32 clk_rate;
166 
167         clk_rate = clk_get_rate(priv->stmmac_clk);
168 
169         /* Platform provided default clk_csr would be assumed valid
170          * for all other cases except for the below mentioned ones.
171          * For values higher than the IEEE 802.3 specified frequency
172          * we can not estimate the proper divider as it is not known
173          * the frequency of clk_csr_i. So we do not change the default
174          * divider.
175          */
176         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
177                 if (clk_rate < CSR_F_35M)
178                         priv->clk_csr = STMMAC_CSR_20_35M;
179                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
180                         priv->clk_csr = STMMAC_CSR_35_60M;
181                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
182                         priv->clk_csr = STMMAC_CSR_60_100M;
183                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
184                         priv->clk_csr = STMMAC_CSR_100_150M;
185                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
186                         priv->clk_csr = STMMAC_CSR_150_250M;
187                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
188                         priv->clk_csr = STMMAC_CSR_250_300M;
189         }
190 }
191 
192 static void print_pkt(unsigned char *buf, int len)
193 {
194         int j;
195         pr_debug("len = %d byte, buf addr: 0x%p", len, buf);
196         for (j = 0; j < len; j++) {
197                 if ((j % 16) == 0)
198                         pr_debug("\n %03x:", j);
199                 pr_debug(" %02x", buf[j]);
200         }
201         pr_debug("\n");
202 }
203 
204 /* minimum number of free TX descriptors required to wake up TX process */
205 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
206 
207 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
208 {
209         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
210 }
211 
212 /**
213  * stmmac_hw_fix_mac_speed: callback for speed selection
214  * @priv: driver private structure
215  * Description: on some platforms (e.g. ST), some HW system configuraton
216  * registers have to be set according to the link speed negotiated.
217  */
218 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
219 {
220         struct phy_device *phydev = priv->phydev;
221 
222         if (likely(priv->plat->fix_mac_speed))
223                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
224 }
225 
226 /**
227  * stmmac_enable_eee_mode: Check and enter in LPI mode
228  * @priv: driver private structure
229  * Description: this function is to verify and enter in LPI mode for EEE.
230  */
231 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
232 {
233         /* Check and enter in LPI mode */
234         if ((priv->dirty_tx == priv->cur_tx) &&
235             (priv->tx_path_in_lpi_mode == false))
236                 priv->hw->mac->set_eee_mode(priv->ioaddr);
237 }
238 
239 /**
240  * stmmac_disable_eee_mode: disable/exit from EEE
241  * @priv: driver private structure
242  * Description: this function is to exit and disable EEE in case of
243  * LPI state is true. This is called by the xmit.
244  */
245 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
246 {
247         priv->hw->mac->reset_eee_mode(priv->ioaddr);
248         del_timer_sync(&priv->eee_ctrl_timer);
249         priv->tx_path_in_lpi_mode = false;
250 }
251 
252 /**
253  * stmmac_eee_ctrl_timer: EEE TX SW timer.
254  * @arg : data hook
255  * Description:
256  *  if there is no data transfer and if we are not in LPI state,
257  *  then MAC Transmitter can be moved to LPI state.
258  */
259 static void stmmac_eee_ctrl_timer(unsigned long arg)
260 {
261         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
262 
263         stmmac_enable_eee_mode(priv);
264         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
265 }
266 
267 /**
268  * stmmac_eee_init: init EEE
269  * @priv: driver private structure
270  * Description:
271  *  If the EEE support has been enabled while configuring the driver,
272  *  if the GMAC actually supports the EEE (from the HW cap reg) and the
273  *  phy can also manage EEE, so enable the LPI state and start the timer
274  *  to verify if the tx path can enter in LPI state.
275  */
276 bool stmmac_eee_init(struct stmmac_priv *priv)
277 {
278         bool ret = false;
279 
280         /* Using PCS we cannot dial with the phy registers at this stage
281          * so we do not support extra feature like EEE.
282          */
283         if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
284             (priv->pcs == STMMAC_PCS_RTBI))
285                 goto out;
286 
287         /* MAC core supports the EEE feature. */
288         if (priv->dma_cap.eee) {
289                 int tx_lpi_timer = priv->tx_lpi_timer;
290 
291                 /* Check if the PHY supports EEE */
292                 if (phy_init_eee(priv->phydev, 1)) {
293                         /* To manage at run-time if the EEE cannot be supported
294                          * anymore (for example because the lp caps have been
295                          * changed).
296                          * In that case the driver disable own timers.
297                          */
298                         if (priv->eee_active) {
299                                 pr_debug("stmmac: disable EEE\n");
300                                 del_timer_sync(&priv->eee_ctrl_timer);
301                                 priv->hw->mac->set_eee_timer(priv->ioaddr, 0,
302                                                              tx_lpi_timer);
303                         }
304                         priv->eee_active = 0;
305                         goto out;
306                 }
307                 /* Activate the EEE and start timers */
308                 if (!priv->eee_active) {
309                         priv->eee_active = 1;
310                         init_timer(&priv->eee_ctrl_timer);
311                         priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
312                         priv->eee_ctrl_timer.data = (unsigned long)priv;
313                         priv->eee_ctrl_timer.expires = STMMAC_LPI_T(eee_timer);
314                         add_timer(&priv->eee_ctrl_timer);
315 
316                         priv->hw->mac->set_eee_timer(priv->ioaddr,
317                                                      STMMAC_DEFAULT_LIT_LS,
318                                                      tx_lpi_timer);
319                 } else
320                         /* Set HW EEE according to the speed */
321                         priv->hw->mac->set_eee_pls(priv->ioaddr,
322                                                    priv->phydev->link);
323 
324                 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
325 
326                 ret = true;
327         }
328 out:
329         return ret;
330 }
331 
332 /* stmmac_get_tx_hwtstamp: get HW TX timestamps
333  * @priv: driver private structure
334  * @entry : descriptor index to be used.
335  * @skb : the socket buffer
336  * Description :
337  * This function will read timestamp from the descriptor & pass it to stack.
338  * and also perform some sanity checks.
339  */
340 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
341                                    unsigned int entry, struct sk_buff *skb)
342 {
343         struct skb_shared_hwtstamps shhwtstamp;
344         u64 ns;
345         void *desc = NULL;
346 
347         if (!priv->hwts_tx_en)
348                 return;
349 
350         /* exit if skb doesn't support hw tstamp */
351         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
352                 return;
353 
354         if (priv->adv_ts)
355                 desc = (priv->dma_etx + entry);
356         else
357                 desc = (priv->dma_tx + entry);
358 
359         /* check tx tstamp status */
360         if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
361                 return;
362 
363         /* get the valid tstamp */
364         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
365 
366         memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
367         shhwtstamp.hwtstamp = ns_to_ktime(ns);
368         /* pass tstamp to stack */
369         skb_tstamp_tx(skb, &shhwtstamp);
370 
371         return;
372 }
373 
374 /* stmmac_get_rx_hwtstamp: get HW RX timestamps
375  * @priv: driver private structure
376  * @entry : descriptor index to be used.
377  * @skb : the socket buffer
378  * Description :
379  * This function will read received packet's timestamp from the descriptor
380  * and pass it to stack. It also perform some sanity checks.
381  */
382 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
383                                    unsigned int entry, struct sk_buff *skb)
384 {
385         struct skb_shared_hwtstamps *shhwtstamp = NULL;
386         u64 ns;
387         void *desc = NULL;
388 
389         if (!priv->hwts_rx_en)
390                 return;
391 
392         if (priv->adv_ts)
393                 desc = (priv->dma_erx + entry);
394         else
395                 desc = (priv->dma_rx + entry);
396 
397         /* exit if rx tstamp is not valid */
398         if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
399                 return;
400 
401         /* get valid tstamp */
402         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
403         shhwtstamp = skb_hwtstamps(skb);
404         memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
405         shhwtstamp->hwtstamp = ns_to_ktime(ns);
406 }
407 
408 /**
409  *  stmmac_hwtstamp_ioctl - control hardware timestamping.
410  *  @dev: device pointer.
411  *  @ifr: An IOCTL specefic structure, that can contain a pointer to
412  *  a proprietary structure used to pass information to the driver.
413  *  Description:
414  *  This function configures the MAC to enable/disable both outgoing(TX)
415  *  and incoming(RX) packets time stamping based on user input.
416  *  Return Value:
417  *  0 on success and an appropriate -ve integer on failure.
418  */
419 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
420 {
421         struct stmmac_priv *priv = netdev_priv(dev);
422         struct hwtstamp_config config;
423         struct timespec now;
424         u64 temp = 0;
425         u32 ptp_v2 = 0;
426         u32 tstamp_all = 0;
427         u32 ptp_over_ipv4_udp = 0;
428         u32 ptp_over_ipv6_udp = 0;
429         u32 ptp_over_ethernet = 0;
430         u32 snap_type_sel = 0;
431         u32 ts_master_en = 0;
432         u32 ts_event_en = 0;
433         u32 value = 0;
434 
435         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
436                 netdev_alert(priv->dev, "No support for HW time stamping\n");
437                 priv->hwts_tx_en = 0;
438                 priv->hwts_rx_en = 0;
439 
440                 return -EOPNOTSUPP;
441         }
442 
443         if (copy_from_user(&config, ifr->ifr_data,
444                            sizeof(struct hwtstamp_config)))
445                 return -EFAULT;
446 
447         pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
448                  __func__, config.flags, config.tx_type, config.rx_filter);
449 
450         /* reserved for future extensions */
451         if (config.flags)
452                 return -EINVAL;
453 
454         if (config.tx_type != HWTSTAMP_TX_OFF &&
455             config.tx_type != HWTSTAMP_TX_ON)
456                 return -ERANGE;
457 
458         if (priv->adv_ts) {
459                 switch (config.rx_filter) {
460                 case HWTSTAMP_FILTER_NONE:
461                         /* time stamp no incoming packet at all */
462                         config.rx_filter = HWTSTAMP_FILTER_NONE;
463                         break;
464 
465                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
466                         /* PTP v1, UDP, any kind of event packet */
467                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
468                         /* take time stamp for all event messages */
469                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
470 
471                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
472                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
473                         break;
474 
475                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
476                         /* PTP v1, UDP, Sync packet */
477                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
478                         /* take time stamp for SYNC messages only */
479                         ts_event_en = PTP_TCR_TSEVNTENA;
480 
481                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
482                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
483                         break;
484 
485                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
486                         /* PTP v1, UDP, Delay_req packet */
487                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
488                         /* take time stamp for Delay_Req messages only */
489                         ts_master_en = PTP_TCR_TSMSTRENA;
490                         ts_event_en = PTP_TCR_TSEVNTENA;
491 
492                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
493                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
494                         break;
495 
496                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
497                         /* PTP v2, UDP, any kind of event packet */
498                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
499                         ptp_v2 = PTP_TCR_TSVER2ENA;
500                         /* take time stamp for all event messages */
501                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
502 
503                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
504                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
505                         break;
506 
507                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
508                         /* PTP v2, UDP, Sync packet */
509                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
510                         ptp_v2 = PTP_TCR_TSVER2ENA;
511                         /* take time stamp for SYNC messages only */
512                         ts_event_en = PTP_TCR_TSEVNTENA;
513 
514                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
515                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
516                         break;
517 
518                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
519                         /* PTP v2, UDP, Delay_req packet */
520                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
521                         ptp_v2 = PTP_TCR_TSVER2ENA;
522                         /* take time stamp for Delay_Req messages only */
523                         ts_master_en = PTP_TCR_TSMSTRENA;
524                         ts_event_en = PTP_TCR_TSEVNTENA;
525 
526                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
527                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
528                         break;
529 
530                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
531                         /* PTP v2/802.AS1 any layer, any kind of event packet */
532                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
533                         ptp_v2 = PTP_TCR_TSVER2ENA;
534                         /* take time stamp for all event messages */
535                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
536 
537                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
538                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
539                         ptp_over_ethernet = PTP_TCR_TSIPENA;
540                         break;
541 
542                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
543                         /* PTP v2/802.AS1, any layer, Sync packet */
544                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
545                         ptp_v2 = PTP_TCR_TSVER2ENA;
546                         /* take time stamp for SYNC messages only */
547                         ts_event_en = PTP_TCR_TSEVNTENA;
548 
549                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
550                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
551                         ptp_over_ethernet = PTP_TCR_TSIPENA;
552                         break;
553 
554                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
555                         /* PTP v2/802.AS1, any layer, Delay_req packet */
556                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
557                         ptp_v2 = PTP_TCR_TSVER2ENA;
558                         /* take time stamp for Delay_Req messages only */
559                         ts_master_en = PTP_TCR_TSMSTRENA;
560                         ts_event_en = PTP_TCR_TSEVNTENA;
561 
562                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
563                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
564                         ptp_over_ethernet = PTP_TCR_TSIPENA;
565                         break;
566 
567                 case HWTSTAMP_FILTER_ALL:
568                         /* time stamp any incoming packet */
569                         config.rx_filter = HWTSTAMP_FILTER_ALL;
570                         tstamp_all = PTP_TCR_TSENALL;
571                         break;
572 
573                 default:
574                         return -ERANGE;
575                 }
576         } else {
577                 switch (config.rx_filter) {
578                 case HWTSTAMP_FILTER_NONE:
579                         config.rx_filter = HWTSTAMP_FILTER_NONE;
580                         break;
581                 default:
582                         /* PTP v1, UDP, any kind of event packet */
583                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
584                         break;
585                 }
586         }
587         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
588         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
589 
590         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
591                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
592         else {
593                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
594                          tstamp_all | ptp_v2 | ptp_over_ethernet |
595                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
596                          ts_master_en | snap_type_sel);
597 
598                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
599 
600                 /* program Sub Second Increment reg */
601                 priv->hw->ptp->config_sub_second_increment(priv->ioaddr);
602 
603                 /* calculate default added value:
604                  * formula is :
605                  * addend = (2^32)/freq_div_ratio;
606                  * where, freq_div_ratio = STMMAC_SYSCLOCK/50MHz
607                  * hence, addend = ((2^32) * 50MHz)/STMMAC_SYSCLOCK;
608                  * NOTE: STMMAC_SYSCLOCK should be >= 50MHz to
609                  *       achive 20ns accuracy.
610                  *
611                  * 2^x * y == (y << x), hence
612                  * 2^32 * 50000000 ==> (50000000 << 32)
613                  */
614                 temp = (u64) (50000000ULL << 32);
615                 priv->default_addend = div_u64(temp, STMMAC_SYSCLOCK);
616                 priv->hw->ptp->config_addend(priv->ioaddr,
617                                              priv->default_addend);
618 
619                 /* initialize system time */
620                 getnstimeofday(&now);
621                 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec,
622                                             now.tv_nsec);
623         }
624 
625         return copy_to_user(ifr->ifr_data, &config,
626                             sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
627 }
628 
629 /**
630  * stmmac_init_ptp: init PTP
631  * @priv: driver private structure
632  * Description: this is to verify if the HW supports the PTPv1 or v2.
633  * This is done by looking at the HW cap. register.
634  * Also it registers the ptp driver.
635  */
636 static int stmmac_init_ptp(struct stmmac_priv *priv)
637 {
638         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
639                 return -EOPNOTSUPP;
640 
641         priv->adv_ts = 0;
642         if (priv->dma_cap.atime_stamp && priv->extend_desc)
643                 priv->adv_ts = 1;
644 
645         if (netif_msg_hw(priv) && priv->dma_cap.time_stamp)
646                 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
647 
648         if (netif_msg_hw(priv) && priv->adv_ts)
649                 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
650 
651         priv->hw->ptp = &stmmac_ptp;
652         priv->hwts_tx_en = 0;
653         priv->hwts_rx_en = 0;
654 
655         return stmmac_ptp_register(priv);
656 }
657 
658 static void stmmac_release_ptp(struct stmmac_priv *priv)
659 {
660         stmmac_ptp_unregister(priv);
661 }
662 
663 /**
664  * stmmac_adjust_link
665  * @dev: net device structure
666  * Description: it adjusts the link parameters.
667  */
668 static void stmmac_adjust_link(struct net_device *dev)
669 {
670         struct stmmac_priv *priv = netdev_priv(dev);
671         struct phy_device *phydev = priv->phydev;
672         unsigned long flags;
673         int new_state = 0;
674         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
675 
676         if (phydev == NULL)
677                 return;
678 
679         spin_lock_irqsave(&priv->lock, flags);
680 
681         if (phydev->link) {
682                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
683 
684                 /* Now we make sure that we can be in full duplex mode.
685                  * If not, we operate in half-duplex mode. */
686                 if (phydev->duplex != priv->oldduplex) {
687                         new_state = 1;
688                         if (!(phydev->duplex))
689                                 ctrl &= ~priv->hw->link.duplex;
690                         else
691                                 ctrl |= priv->hw->link.duplex;
692                         priv->oldduplex = phydev->duplex;
693                 }
694                 /* Flow Control operation */
695                 if (phydev->pause)
696                         priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
697                                                  fc, pause_time);
698 
699                 if (phydev->speed != priv->speed) {
700                         new_state = 1;
701                         switch (phydev->speed) {
702                         case 1000:
703                                 if (likely(priv->plat->has_gmac))
704                                         ctrl &= ~priv->hw->link.port;
705                                 stmmac_hw_fix_mac_speed(priv);
706                                 break;
707                         case 100:
708                         case 10:
709                                 if (priv->plat->has_gmac) {
710                                         ctrl |= priv->hw->link.port;
711                                         if (phydev->speed == SPEED_100) {
712                                                 ctrl |= priv->hw->link.speed;
713                                         } else {
714                                                 ctrl &= ~(priv->hw->link.speed);
715                                         }
716                                 } else {
717                                         ctrl &= ~priv->hw->link.port;
718                                 }
719                                 stmmac_hw_fix_mac_speed(priv);
720                                 break;
721                         default:
722                                 if (netif_msg_link(priv))
723                                         pr_warn("%s: Speed (%d) not 10/100\n",
724                                                 dev->name, phydev->speed);
725                                 break;
726                         }
727 
728                         priv->speed = phydev->speed;
729                 }
730 
731                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
732 
733                 if (!priv->oldlink) {
734                         new_state = 1;
735                         priv->oldlink = 1;
736                 }
737         } else if (priv->oldlink) {
738                 new_state = 1;
739                 priv->oldlink = 0;
740                 priv->speed = 0;
741                 priv->oldduplex = -1;
742         }
743 
744         if (new_state && netif_msg_link(priv))
745                 phy_print_status(phydev);
746 
747         /* At this stage, it could be needed to setup the EEE or adjust some
748          * MAC related HW registers.
749          */
750         priv->eee_enabled = stmmac_eee_init(priv);
751 
752         spin_unlock_irqrestore(&priv->lock, flags);
753 }
754 
755 /**
756  * stmmac_check_pcs_mode: verify if RGMII/SGMII is supported
757  * @priv: driver private structure
758  * Description: this is to verify if the HW supports the PCS.
759  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
760  * configured for the TBI, RTBI, or SGMII PHY interface.
761  */
762 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
763 {
764         int interface = priv->plat->interface;
765 
766         if (priv->dma_cap.pcs) {
767                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
768                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
769                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
770                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
771                         pr_debug("STMMAC: PCS RGMII support enable\n");
772                         priv->pcs = STMMAC_PCS_RGMII;
773                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
774                         pr_debug("STMMAC: PCS SGMII support enable\n");
775                         priv->pcs = STMMAC_PCS_SGMII;
776                 }
777         }
778 }
779 
780 /**
781  * stmmac_init_phy - PHY initialization
782  * @dev: net device structure
783  * Description: it initializes the driver's PHY state, and attaches the PHY
784  * to the mac driver.
785  *  Return value:
786  *  0 on success
787  */
788 static int stmmac_init_phy(struct net_device *dev)
789 {
790         struct stmmac_priv *priv = netdev_priv(dev);
791         struct phy_device *phydev;
792         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
793         char bus_id[MII_BUS_ID_SIZE];
794         int interface = priv->plat->interface;
795         int max_speed = priv->plat->max_speed;
796         priv->oldlink = 0;
797         priv->speed = 0;
798         priv->oldduplex = -1;
799 
800         if (priv->plat->phy_bus_name)
801                 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
802                          priv->plat->phy_bus_name, priv->plat->bus_id);
803         else
804                 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
805                          priv->plat->bus_id);
806 
807         snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
808                  priv->plat->phy_addr);
809         pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id_fmt);
810 
811         phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
812 
813         if (IS_ERR(phydev)) {
814                 pr_err("%s: Could not attach to PHY\n", dev->name);
815                 return PTR_ERR(phydev);
816         }
817 
818         /* Stop Advertising 1000BASE Capability if interface is not GMII */
819         if ((interface == PHY_INTERFACE_MODE_MII) ||
820             (interface == PHY_INTERFACE_MODE_RMII) ||
821                 (max_speed < 1000 &&  max_speed > 0))
822                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
823                                          SUPPORTED_1000baseT_Full);
824 
825         /*
826          * Broken HW is sometimes missing the pull-up resistor on the
827          * MDIO line, which results in reads to non-existent devices returning
828          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
829          * device as well.
830          * Note: phydev->phy_id is the result of reading the UID PHY registers.
831          */
832         if (phydev->phy_id == 0) {
833                 phy_disconnect(phydev);
834                 return -ENODEV;
835         }
836         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
837                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
838 
839         priv->phydev = phydev;
840 
841         return 0;
842 }
843 
844 /**
845  * stmmac_display_ring: display ring
846  * @head: pointer to the head of the ring passed.
847  * @size: size of the ring.
848  * @extend_desc: to verify if extended descriptors are used.
849  * Description: display the control/status and buffer descriptors.
850  */
851 static void stmmac_display_ring(void *head, int size, int extend_desc)
852 {
853         int i;
854         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
855         struct dma_desc *p = (struct dma_desc *)head;
856 
857         for (i = 0; i < size; i++) {
858                 u64 x;
859                 if (extend_desc) {
860                         x = *(u64 *) ep;
861                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
862                                 i, (unsigned int)virt_to_phys(ep),
863                                 (unsigned int)x, (unsigned int)(x >> 32),
864                                 ep->basic.des2, ep->basic.des3);
865                         ep++;
866                 } else {
867                         x = *(u64 *) p;
868                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
869                                 i, (unsigned int)virt_to_phys(p),
870                                 (unsigned int)x, (unsigned int)(x >> 32),
871                                 p->des2, p->des3);
872                         p++;
873                 }
874                 pr_info("\n");
875         }
876 }
877 
878 static void stmmac_display_rings(struct stmmac_priv *priv)
879 {
880         unsigned int txsize = priv->dma_tx_size;
881         unsigned int rxsize = priv->dma_rx_size;
882 
883         if (priv->extend_desc) {
884                 pr_info("Extended RX descriptor ring:\n");
885                 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
886                 pr_info("Extended TX descriptor ring:\n");
887                 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
888         } else {
889                 pr_info("RX descriptor ring:\n");
890                 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
891                 pr_info("TX descriptor ring:\n");
892                 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
893         }
894 }
895 
896 static int stmmac_set_bfsize(int mtu, int bufsize)
897 {
898         int ret = bufsize;
899 
900         if (mtu >= BUF_SIZE_4KiB)
901                 ret = BUF_SIZE_8KiB;
902         else if (mtu >= BUF_SIZE_2KiB)
903                 ret = BUF_SIZE_4KiB;
904         else if (mtu > DEFAULT_BUFSIZE)
905                 ret = BUF_SIZE_2KiB;
906         else
907                 ret = DEFAULT_BUFSIZE;
908 
909         return ret;
910 }
911 
912 /**
913  * stmmac_clear_descriptors: clear descriptors
914  * @priv: driver private structure
915  * Description: this function is called to clear the tx and rx descriptors
916  * in case of both basic and extended descriptors are used.
917  */
918 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
919 {
920         int i;
921         unsigned int txsize = priv->dma_tx_size;
922         unsigned int rxsize = priv->dma_rx_size;
923 
924         /* Clear the Rx/Tx descriptors */
925         for (i = 0; i < rxsize; i++)
926                 if (priv->extend_desc)
927                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
928                                                      priv->use_riwt, priv->mode,
929                                                      (i == rxsize - 1));
930                 else
931                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
932                                                      priv->use_riwt, priv->mode,
933                                                      (i == rxsize - 1));
934         for (i = 0; i < txsize; i++)
935                 if (priv->extend_desc)
936                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
937                                                      priv->mode,
938                                                      (i == txsize - 1));
939                 else
940                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
941                                                      priv->mode,
942                                                      (i == txsize - 1));
943 }
944 
945 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
946                                   int i)
947 {
948         struct sk_buff *skb;
949 
950         skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN,
951                                  GFP_KERNEL);
952         if (!skb) {
953                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
954                 return -ENOMEM;
955         }
956         skb_reserve(skb, NET_IP_ALIGN);
957         priv->rx_skbuff[i] = skb;
958         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
959                                                 priv->dma_buf_sz,
960                                                 DMA_FROM_DEVICE);
961         if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
962                 pr_err("%s: DMA mapping error\n", __func__);
963                 dev_kfree_skb_any(skb);
964                 return -EINVAL;
965         }
966 
967         p->des2 = priv->rx_skbuff_dma[i];
968 
969         if ((priv->hw->mode->init_desc3) &&
970             (priv->dma_buf_sz == BUF_SIZE_16KiB))
971                 priv->hw->mode->init_desc3(p);
972 
973         return 0;
974 }
975 
976 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
977 {
978         if (priv->rx_skbuff[i]) {
979                 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
980                                  priv->dma_buf_sz, DMA_FROM_DEVICE);
981                 dev_kfree_skb_any(priv->rx_skbuff[i]);
982         }
983         priv->rx_skbuff[i] = NULL;
984 }
985 
986 /**
987  * init_dma_desc_rings - init the RX/TX descriptor rings
988  * @dev: net device structure
989  * Description:  this function initializes the DMA RX/TX descriptors
990  * and allocates the socket buffers. It suppors the chained and ring
991  * modes.
992  */
993 static int init_dma_desc_rings(struct net_device *dev)
994 {
995         int i;
996         struct stmmac_priv *priv = netdev_priv(dev);
997         unsigned int txsize = priv->dma_tx_size;
998         unsigned int rxsize = priv->dma_rx_size;
999         unsigned int bfsize = 0;
1000         int ret = -ENOMEM;
1001 
1002         if (priv->hw->mode->set_16kib_bfsize)
1003                 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1004 
1005         if (bfsize < BUF_SIZE_16KiB)
1006                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1007 
1008         priv->dma_buf_sz = bfsize;
1009 
1010         if (netif_msg_probe(priv))
1011                 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__,
1012                          txsize, rxsize, bfsize);
1013 
1014         if (netif_msg_probe(priv)) {
1015                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1016                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1017 
1018                 /* RX INITIALIZATION */
1019                 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1020         }
1021         for (i = 0; i < rxsize; i++) {
1022                 struct dma_desc *p;
1023                 if (priv->extend_desc)
1024                         p = &((priv->dma_erx + i)->basic);
1025                 else
1026                         p = priv->dma_rx + i;
1027 
1028                 ret = stmmac_init_rx_buffers(priv, p, i);
1029                 if (ret)
1030                         goto err_init_rx_buffers;
1031 
1032                 if (netif_msg_probe(priv))
1033                         pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1034                                  priv->rx_skbuff[i]->data,
1035                                  (unsigned int)priv->rx_skbuff_dma[i]);
1036         }
1037         priv->cur_rx = 0;
1038         priv->dirty_rx = (unsigned int)(i - rxsize);
1039         buf_sz = bfsize;
1040 
1041         /* Setup the chained descriptor addresses */
1042         if (priv->mode == STMMAC_CHAIN_MODE) {
1043                 if (priv->extend_desc) {
1044                         priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1045                                              rxsize, 1);
1046                         priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1047                                              txsize, 1);
1048                 } else {
1049                         priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1050                                              rxsize, 0);
1051                         priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1052                                              txsize, 0);
1053                 }
1054         }
1055 
1056         /* TX INITIALIZATION */
1057         for (i = 0; i < txsize; i++) {
1058                 struct dma_desc *p;
1059                 if (priv->extend_desc)
1060                         p = &((priv->dma_etx + i)->basic);
1061                 else
1062                         p = priv->dma_tx + i;
1063                 p->des2 = 0;
1064                 priv->tx_skbuff_dma[i] = 0;
1065                 priv->tx_skbuff[i] = NULL;
1066         }
1067 
1068         priv->dirty_tx = 0;
1069         priv->cur_tx = 0;
1070 
1071         stmmac_clear_descriptors(priv);
1072 
1073         if (netif_msg_hw(priv))
1074                 stmmac_display_rings(priv);
1075 
1076         return 0;
1077 err_init_rx_buffers:
1078         while (--i >= 0)
1079                 stmmac_free_rx_buffers(priv, i);
1080         return ret;
1081 }
1082 
1083 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1084 {
1085         int i;
1086 
1087         for (i = 0; i < priv->dma_rx_size; i++)
1088                 stmmac_free_rx_buffers(priv, i);
1089 }
1090 
1091 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1092 {
1093         int i;
1094 
1095         for (i = 0; i < priv->dma_tx_size; i++) {
1096                 struct dma_desc *p;
1097 
1098                 if (priv->extend_desc)
1099                         p = &((priv->dma_etx + i)->basic);
1100                 else
1101                         p = priv->dma_tx + i;
1102 
1103                 if (priv->tx_skbuff_dma[i]) {
1104                         dma_unmap_single(priv->device,
1105                                          priv->tx_skbuff_dma[i],
1106                                          priv->hw->desc->get_tx_len(p),
1107                                          DMA_TO_DEVICE);
1108                         priv->tx_skbuff_dma[i] = 0;
1109                 }
1110 
1111                 if (priv->tx_skbuff[i] != NULL) {
1112                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1113                         priv->tx_skbuff[i] = NULL;
1114                 }
1115         }
1116 }
1117 
1118 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1119 {
1120         unsigned int txsize = priv->dma_tx_size;
1121         unsigned int rxsize = priv->dma_rx_size;
1122         int ret = -ENOMEM;
1123 
1124         priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
1125                                             GFP_KERNEL);
1126         if (!priv->rx_skbuff_dma)
1127                 return -ENOMEM;
1128 
1129         priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
1130                                         GFP_KERNEL);
1131         if (!priv->rx_skbuff)
1132                 goto err_rx_skbuff;
1133 
1134         priv->tx_skbuff_dma = kmalloc_array(txsize, sizeof(dma_addr_t),
1135                                             GFP_KERNEL);
1136         if (!priv->tx_skbuff_dma)
1137                 goto err_tx_skbuff_dma;
1138 
1139         priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
1140                                         GFP_KERNEL);
1141         if (!priv->tx_skbuff)
1142                 goto err_tx_skbuff;
1143 
1144         if (priv->extend_desc) {
1145                 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
1146                                                    sizeof(struct
1147                                                           dma_extended_desc),
1148                                                    &priv->dma_rx_phy,
1149                                                    GFP_KERNEL);
1150                 if (!priv->dma_erx)
1151                         goto err_dma;
1152 
1153                 priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
1154                                                    sizeof(struct
1155                                                           dma_extended_desc),
1156                                                    &priv->dma_tx_phy,
1157                                                    GFP_KERNEL);
1158                 if (!priv->dma_etx) {
1159                         dma_free_coherent(priv->device, priv->dma_rx_size *
1160                                         sizeof(struct dma_extended_desc),
1161                                         priv->dma_erx, priv->dma_rx_phy);
1162                         goto err_dma;
1163                 }
1164         } else {
1165                 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
1166                                                   sizeof(struct dma_desc),
1167                                                   &priv->dma_rx_phy,
1168                                                   GFP_KERNEL);
1169                 if (!priv->dma_rx)
1170                         goto err_dma;
1171 
1172                 priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
1173                                                   sizeof(struct dma_desc),
1174                                                   &priv->dma_tx_phy,
1175                                                   GFP_KERNEL);
1176                 if (!priv->dma_tx) {
1177                         dma_free_coherent(priv->device, priv->dma_rx_size *
1178                                         sizeof(struct dma_desc),
1179                                         priv->dma_rx, priv->dma_rx_phy);
1180                         goto err_dma;
1181                 }
1182         }
1183 
1184         return 0;
1185 
1186 err_dma:
1187         kfree(priv->tx_skbuff);
1188 err_tx_skbuff:
1189         kfree(priv->tx_skbuff_dma);
1190 err_tx_skbuff_dma:
1191         kfree(priv->rx_skbuff);
1192 err_rx_skbuff:
1193         kfree(priv->rx_skbuff_dma);
1194         return ret;
1195 }
1196 
1197 static void free_dma_desc_resources(struct stmmac_priv *priv)
1198 {
1199         /* Release the DMA TX/RX socket buffers */
1200         dma_free_rx_skbufs(priv);
1201         dma_free_tx_skbufs(priv);
1202 
1203         /* Free DMA regions of consistent memory previously allocated */
1204         if (!priv->extend_desc) {
1205                 dma_free_coherent(priv->device,
1206                                   priv->dma_tx_size * sizeof(struct dma_desc),
1207                                   priv->dma_tx, priv->dma_tx_phy);
1208                 dma_free_coherent(priv->device,
1209                                   priv->dma_rx_size * sizeof(struct dma_desc),
1210                                   priv->dma_rx, priv->dma_rx_phy);
1211         } else {
1212                 dma_free_coherent(priv->device, priv->dma_tx_size *
1213                                   sizeof(struct dma_extended_desc),
1214                                   priv->dma_etx, priv->dma_tx_phy);
1215                 dma_free_coherent(priv->device, priv->dma_rx_size *
1216                                   sizeof(struct dma_extended_desc),
1217                                   priv->dma_erx, priv->dma_rx_phy);
1218         }
1219         kfree(priv->rx_skbuff_dma);
1220         kfree(priv->rx_skbuff);
1221         kfree(priv->tx_skbuff_dma);
1222         kfree(priv->tx_skbuff);
1223 }
1224 
1225 /**
1226  *  stmmac_dma_operation_mode - HW DMA operation mode
1227  *  @priv: driver private structure
1228  *  Description: it sets the DMA operation mode: tx/rx DMA thresholds
1229  *  or Store-And-Forward capability.
1230  */
1231 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1232 {
1233         if (priv->plat->force_thresh_dma_mode)
1234                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc);
1235         else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1236                 /*
1237                  * In case of GMAC, SF mode can be enabled
1238                  * to perform the TX COE in HW. This depends on:
1239                  * 1) TX COE if actually supported
1240                  * 2) There is no bugged Jumbo frame support
1241                  *    that needs to not insert csum in the TDES.
1242                  */
1243                 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE);
1244                 tc = SF_DMA_MODE;
1245         } else
1246                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1247 }
1248 
1249 /**
1250  * stmmac_tx_clean:
1251  * @priv: driver private structure
1252  * Description: it reclaims resources after transmission completes.
1253  */
1254 static void stmmac_tx_clean(struct stmmac_priv *priv)
1255 {
1256         unsigned int txsize = priv->dma_tx_size;
1257 
1258         spin_lock(&priv->tx_lock);
1259 
1260         priv->xstats.tx_clean++;
1261 
1262         while (priv->dirty_tx != priv->cur_tx) {
1263                 int last;
1264                 unsigned int entry = priv->dirty_tx % txsize;
1265                 struct sk_buff *skb = priv->tx_skbuff[entry];
1266                 struct dma_desc *p;
1267 
1268                 if (priv->extend_desc)
1269                         p = (struct dma_desc *)(priv->dma_etx + entry);
1270                 else
1271                         p = priv->dma_tx + entry;
1272 
1273                 /* Check if the descriptor is owned by the DMA. */
1274                 if (priv->hw->desc->get_tx_owner(p))
1275                         break;
1276 
1277                 /* Verify tx error by looking at the last segment. */
1278                 last = priv->hw->desc->get_tx_ls(p);
1279                 if (likely(last)) {
1280                         int tx_error =
1281                             priv->hw->desc->tx_status(&priv->dev->stats,
1282                                                       &priv->xstats, p,
1283                                                       priv->ioaddr);
1284                         if (likely(tx_error == 0)) {
1285                                 priv->dev->stats.tx_packets++;
1286                                 priv->xstats.tx_pkt_n++;
1287                         } else
1288                                 priv->dev->stats.tx_errors++;
1289 
1290                         stmmac_get_tx_hwtstamp(priv, entry, skb);
1291                 }
1292                 if (netif_msg_tx_done(priv))
1293                         pr_debug("%s: curr %d, dirty %d\n", __func__,
1294                                  priv->cur_tx, priv->dirty_tx);
1295 
1296                 if (likely(priv->tx_skbuff_dma[entry])) {
1297                         dma_unmap_single(priv->device,
1298                                          priv->tx_skbuff_dma[entry],
1299                                          priv->hw->desc->get_tx_len(p),
1300                                          DMA_TO_DEVICE);
1301                         priv->tx_skbuff_dma[entry] = 0;
1302                 }
1303                 priv->hw->mode->clean_desc3(priv, p);
1304 
1305                 if (likely(skb != NULL)) {
1306                         dev_consume_skb_any(skb);
1307                         priv->tx_skbuff[entry] = NULL;
1308                 }
1309 
1310                 priv->hw->desc->release_tx_desc(p, priv->mode);
1311 
1312                 priv->dirty_tx++;
1313         }
1314         if (unlikely(netif_queue_stopped(priv->dev) &&
1315                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
1316                 netif_tx_lock(priv->dev);
1317                 if (netif_queue_stopped(priv->dev) &&
1318                     stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
1319                         if (netif_msg_tx_done(priv))
1320                                 pr_debug("%s: restart transmit\n", __func__);
1321                         netif_wake_queue(priv->dev);
1322                 }
1323                 netif_tx_unlock(priv->dev);
1324         }
1325 
1326         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1327                 stmmac_enable_eee_mode(priv);
1328                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1329         }
1330         spin_unlock(&priv->tx_lock);
1331 }
1332 
1333 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1334 {
1335         priv->hw->dma->enable_dma_irq(priv->ioaddr);
1336 }
1337 
1338 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1339 {
1340         priv->hw->dma->disable_dma_irq(priv->ioaddr);
1341 }
1342 
1343 /**
1344  * stmmac_tx_err: irq tx error mng function
1345  * @priv: driver private structure
1346  * Description: it cleans the descriptors and restarts the transmission
1347  * in case of errors.
1348  */
1349 static void stmmac_tx_err(struct stmmac_priv *priv)
1350 {
1351         int i;
1352         int txsize = priv->dma_tx_size;
1353         netif_stop_queue(priv->dev);
1354 
1355         priv->hw->dma->stop_tx(priv->ioaddr);
1356         dma_free_tx_skbufs(priv);
1357         for (i = 0; i < txsize; i++)
1358                 if (priv->extend_desc)
1359                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1360                                                      priv->mode,
1361                                                      (i == txsize - 1));
1362                 else
1363                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1364                                                      priv->mode,
1365                                                      (i == txsize - 1));
1366         priv->dirty_tx = 0;
1367         priv->cur_tx = 0;
1368         priv->hw->dma->start_tx(priv->ioaddr);
1369 
1370         priv->dev->stats.tx_errors++;
1371         netif_wake_queue(priv->dev);
1372 }
1373 
1374 /**
1375  * stmmac_dma_interrupt: DMA ISR
1376  * @priv: driver private structure
1377  * Description: this is the DMA ISR. It is called by the main ISR.
1378  * It calls the dwmac dma routine to understand which type of interrupt
1379  * happened. In case of there is a Normal interrupt and either TX or RX
1380  * interrupt happened so the NAPI is scheduled.
1381  */
1382 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1383 {
1384         int status;
1385 
1386         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1387         if (likely((status & handle_rx)) || (status & handle_tx)) {
1388                 if (likely(napi_schedule_prep(&priv->napi))) {
1389                         stmmac_disable_dma_irq(priv);
1390                         __napi_schedule(&priv->napi);
1391                 }
1392         }
1393         if (unlikely(status & tx_hard_error_bump_tc)) {
1394                 /* Try to bump up the dma threshold on this failure */
1395                 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
1396                         tc += 64;
1397                         priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1398                         priv->xstats.threshold = tc;
1399                 }
1400         } else if (unlikely(status == tx_hard_error))
1401                 stmmac_tx_err(priv);
1402 }
1403 
1404 /**
1405  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1406  * @priv: driver private structure
1407  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1408  */
1409 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1410 {
1411         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1412             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1413 
1414         dwmac_mmc_intr_all_mask(priv->ioaddr);
1415 
1416         if (priv->dma_cap.rmon) {
1417                 dwmac_mmc_ctrl(priv->ioaddr, mode);
1418                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1419         } else
1420                 pr_info(" No MAC Management Counters available\n");
1421 }
1422 
1423 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1424 {
1425         u32 hwid = priv->hw->synopsys_uid;
1426 
1427         /* Check Synopsys Id (not available on old chips) */
1428         if (likely(hwid)) {
1429                 u32 uid = ((hwid & 0x0000ff00) >> 8);
1430                 u32 synid = (hwid & 0x000000ff);
1431 
1432                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1433                         uid, synid);
1434 
1435                 return synid;
1436         }
1437         return 0;
1438 }
1439 
1440 /**
1441  * stmmac_selec_desc_mode: to select among: normal/alternate/extend descriptors
1442  * @priv: driver private structure
1443  * Description: select the Enhanced/Alternate or Normal descriptors.
1444  * In case of Enhanced/Alternate, it looks at the extended descriptors are
1445  * supported by the HW cap. register.
1446  */
1447 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1448 {
1449         if (priv->plat->enh_desc) {
1450                 pr_info(" Enhanced/Alternate descriptors\n");
1451 
1452                 /* GMAC older than 3.50 has no extended descriptors */
1453                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1454                         pr_info("\tEnabled extended descriptors\n");
1455                         priv->extend_desc = 1;
1456                 } else
1457                         pr_warn("Extended descriptors not supported\n");
1458 
1459                 priv->hw->desc = &enh_desc_ops;
1460         } else {
1461                 pr_info(" Normal descriptors\n");
1462                 priv->hw->desc = &ndesc_ops;
1463         }
1464 }
1465 
1466 /**
1467  * stmmac_get_hw_features: get MAC capabilities from the HW cap. register.
1468  * @priv: driver private structure
1469  * Description:
1470  *  new GMAC chip generations have a new register to indicate the
1471  *  presence of the optional feature/functions.
1472  *  This can be also used to override the value passed through the
1473  *  platform and necessary for old MAC10/100 and GMAC chips.
1474  */
1475 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1476 {
1477         u32 hw_cap = 0;
1478 
1479         if (priv->hw->dma->get_hw_feature) {
1480                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1481 
1482                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1483                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1484                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1485                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1486                 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1487                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1488                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1489                 priv->dma_cap.pmt_remote_wake_up =
1490                     (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1491                 priv->dma_cap.pmt_magic_frame =
1492                     (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1493                 /* MMC */
1494                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1495                 /* IEEE 1588-2002 */
1496                 priv->dma_cap.time_stamp =
1497                     (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1498                 /* IEEE 1588-2008 */
1499                 priv->dma_cap.atime_stamp =
1500                     (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1501                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1502                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1503                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1504                 /* TX and RX csum */
1505                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1506                 priv->dma_cap.rx_coe_type1 =
1507                     (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1508                 priv->dma_cap.rx_coe_type2 =
1509                     (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1510                 priv->dma_cap.rxfifo_over_2048 =
1511                     (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1512                 /* TX and RX number of channels */
1513                 priv->dma_cap.number_rx_channel =
1514                     (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1515                 priv->dma_cap.number_tx_channel =
1516                     (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1517                 /* Alternate (enhanced) DESC mode */
1518                 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1519         }
1520 
1521         return hw_cap;
1522 }
1523 
1524 /**
1525  * stmmac_check_ether_addr: check if the MAC addr is valid
1526  * @priv: driver private structure
1527  * Description:
1528  * it is to verify if the MAC address is valid, in case of failures it
1529  * generates a random MAC address
1530  */
1531 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1532 {
1533         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1534                 priv->hw->mac->get_umac_addr((void __iomem *)
1535                                              priv->dev->base_addr,
1536                                              priv->dev->dev_addr, 0);
1537                 if (!is_valid_ether_addr(priv->dev->dev_addr))
1538                         eth_hw_addr_random(priv->dev);
1539                 pr_info("%s: device MAC address %pM\n", priv->dev->name,
1540                         priv->dev->dev_addr);
1541         }
1542 }
1543 
1544 /**
1545  * stmmac_init_dma_engine: DMA init.
1546  * @priv: driver private structure
1547  * Description:
1548  * It inits the DMA invoking the specific MAC/GMAC callback.
1549  * Some DMA parameters can be passed from the platform;
1550  * in case of these are not passed a default is kept for the MAC or GMAC.
1551  */
1552 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1553 {
1554         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1555         int mixed_burst = 0;
1556         int atds = 0;
1557 
1558         if (priv->plat->dma_cfg) {
1559                 pbl = priv->plat->dma_cfg->pbl;
1560                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1561                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1562                 burst_len = priv->plat->dma_cfg->burst_len;
1563         }
1564 
1565         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1566                 atds = 1;
1567 
1568         return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1569                                    burst_len, priv->dma_tx_phy,
1570                                    priv->dma_rx_phy, atds);
1571 }
1572 
1573 /**
1574  * stmmac_tx_timer: mitigation sw timer for tx.
1575  * @data: data pointer
1576  * Description:
1577  * This is the timer handler to directly invoke the stmmac_tx_clean.
1578  */
1579 static void stmmac_tx_timer(unsigned long data)
1580 {
1581         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1582 
1583         stmmac_tx_clean(priv);
1584 }
1585 
1586 /**
1587  * stmmac_init_tx_coalesce: init tx mitigation options.
1588  * @priv: driver private structure
1589  * Description:
1590  * This inits the transmit coalesce parameters: i.e. timer rate,
1591  * timer handler and default threshold used for enabling the
1592  * interrupt on completion bit.
1593  */
1594 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1595 {
1596         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1597         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1598         init_timer(&priv->txtimer);
1599         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1600         priv->txtimer.data = (unsigned long)priv;
1601         priv->txtimer.function = stmmac_tx_timer;
1602         add_timer(&priv->txtimer);
1603 }
1604 
1605 /**
1606  * stmmac_hw_setup: setup mac in a usable state.
1607  *  @dev : pointer to the device structure.
1608  *  Description:
1609  *  This function sets up the ip in a usable state.
1610  *  Return value:
1611  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1612  *  file on failure.
1613  */
1614 static int stmmac_hw_setup(struct net_device *dev)
1615 {
1616         struct stmmac_priv *priv = netdev_priv(dev);
1617         int ret;
1618 
1619         ret = init_dma_desc_rings(dev);
1620         if (ret < 0) {
1621                 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1622                 return ret;
1623         }
1624         /* DMA initialization and SW reset */
1625         ret = stmmac_init_dma_engine(priv);
1626         if (ret < 0) {
1627                 pr_err("%s: DMA engine initialization failed\n", __func__);
1628                 return ret;
1629         }
1630 
1631         /* Copy the MAC addr into the HW  */
1632         priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
1633 
1634         /* If required, perform hw setup of the bus. */
1635         if (priv->plat->bus_setup)
1636                 priv->plat->bus_setup(priv->ioaddr);
1637 
1638         /* Initialize the MAC Core */
1639         priv->hw->mac->core_init(priv->ioaddr, dev->mtu);
1640 
1641         /* Enable the MAC Rx/Tx */
1642         stmmac_set_mac(priv->ioaddr, true);
1643 
1644         /* Set the HW DMA mode and the COE */
1645         stmmac_dma_operation_mode(priv);
1646 
1647         stmmac_mmc_setup(priv);
1648 
1649         ret = stmmac_init_ptp(priv);
1650         if (ret && ret != -EOPNOTSUPP)
1651                 pr_warn("%s: failed PTP initialisation\n", __func__);
1652 
1653 #ifdef CONFIG_STMMAC_DEBUG_FS
1654         ret = stmmac_init_fs(dev);
1655         if (ret < 0)
1656                 pr_warn("%s: failed debugFS registration\n", __func__);
1657 #endif
1658         /* Start the ball rolling... */
1659         pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
1660         priv->hw->dma->start_tx(priv->ioaddr);
1661         priv->hw->dma->start_rx(priv->ioaddr);
1662 
1663         /* Dump DMA/MAC registers */
1664         if (netif_msg_hw(priv)) {
1665                 priv->hw->mac->dump_regs(priv->ioaddr);
1666                 priv->hw->dma->dump_regs(priv->ioaddr);
1667         }
1668         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1669 
1670         priv->eee_enabled = stmmac_eee_init(priv);
1671 
1672         stmmac_init_tx_coalesce(priv);
1673 
1674         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1675                 priv->rx_riwt = MAX_DMA_RIWT;
1676                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1677         }
1678 
1679         if (priv->pcs && priv->hw->mac->ctrl_ane)
1680                 priv->hw->mac->ctrl_ane(priv->ioaddr, 0);
1681 
1682         return 0;
1683 }
1684 
1685 /**
1686  *  stmmac_open - open entry point of the driver
1687  *  @dev : pointer to the device structure.
1688  *  Description:
1689  *  This function is the open entry point of the driver.
1690  *  Return value:
1691  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1692  *  file on failure.
1693  */
1694 static int stmmac_open(struct net_device *dev)
1695 {
1696         struct stmmac_priv *priv = netdev_priv(dev);
1697         int ret;
1698 
1699         stmmac_check_ether_addr(priv);
1700 
1701         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1702             priv->pcs != STMMAC_PCS_RTBI) {
1703                 ret = stmmac_init_phy(dev);
1704                 if (ret) {
1705                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1706                                __func__, ret);
1707                         return ret;
1708                 }
1709         }
1710 
1711         /* Extra statistics */
1712         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1713         priv->xstats.threshold = tc;
1714 
1715         /* Create and initialize the TX/RX descriptors chains. */
1716         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1717         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1718         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1719 
1720         ret = alloc_dma_desc_resources(priv);
1721         if (ret < 0) {
1722                 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1723                 goto dma_desc_error;
1724         }
1725 
1726         ret = stmmac_hw_setup(dev);
1727         if (ret < 0) {
1728                 pr_err("%s: Hw setup failed\n", __func__);
1729                 goto init_error;
1730         }
1731 
1732         if (priv->phydev)
1733                 phy_start(priv->phydev);
1734 
1735         /* Request the IRQ lines */
1736         ret = request_irq(dev->irq, stmmac_interrupt,
1737                           IRQF_SHARED, dev->name, dev);
1738         if (unlikely(ret < 0)) {
1739                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1740                        __func__, dev->irq, ret);
1741                 goto init_error;
1742         }
1743 
1744         /* Request the Wake IRQ in case of another line is used for WoL */
1745         if (priv->wol_irq != dev->irq) {
1746                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1747                                   IRQF_SHARED, dev->name, dev);
1748                 if (unlikely(ret < 0)) {
1749                         pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1750                                __func__, priv->wol_irq, ret);
1751                         goto wolirq_error;
1752                 }
1753         }
1754 
1755         /* Request the IRQ lines */
1756         if (priv->lpi_irq != -ENXIO) {
1757                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1758                                   dev->name, dev);
1759                 if (unlikely(ret < 0)) {
1760                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1761                                __func__, priv->lpi_irq, ret);
1762                         goto lpiirq_error;
1763                 }
1764         }
1765 
1766         napi_enable(&priv->napi);
1767         netif_start_queue(dev);
1768 
1769         return 0;
1770 
1771 lpiirq_error:
1772         if (priv->wol_irq != dev->irq)
1773                 free_irq(priv->wol_irq, dev);
1774 wolirq_error:
1775         free_irq(dev->irq, dev);
1776 
1777 init_error:
1778         free_dma_desc_resources(priv);
1779 dma_desc_error:
1780         if (priv->phydev)
1781                 phy_disconnect(priv->phydev);
1782 
1783         return ret;
1784 }
1785 
1786 /**
1787  *  stmmac_release - close entry point of the driver
1788  *  @dev : device pointer.
1789  *  Description:
1790  *  This is the stop entry point of the driver.
1791  */
1792 static int stmmac_release(struct net_device *dev)
1793 {
1794         struct stmmac_priv *priv = netdev_priv(dev);
1795 
1796         if (priv->eee_enabled)
1797                 del_timer_sync(&priv->eee_ctrl_timer);
1798 
1799         /* Stop and disconnect the PHY */
1800         if (priv->phydev) {
1801                 phy_stop(priv->phydev);
1802                 phy_disconnect(priv->phydev);
1803                 priv->phydev = NULL;
1804         }
1805 
1806         netif_stop_queue(dev);
1807 
1808         napi_disable(&priv->napi);
1809 
1810         del_timer_sync(&priv->txtimer);
1811 
1812         /* Free the IRQ lines */
1813         free_irq(dev->irq, dev);
1814         if (priv->wol_irq != dev->irq)
1815                 free_irq(priv->wol_irq, dev);
1816         if (priv->lpi_irq != -ENXIO)
1817                 free_irq(priv->lpi_irq, dev);
1818 
1819         /* Stop TX/RX DMA and clear the descriptors */
1820         priv->hw->dma->stop_tx(priv->ioaddr);
1821         priv->hw->dma->stop_rx(priv->ioaddr);
1822 
1823         /* Release and free the Rx/Tx resources */
1824         free_dma_desc_resources(priv);
1825 
1826         /* Disable the MAC Rx/Tx */
1827         stmmac_set_mac(priv->ioaddr, false);
1828 
1829         netif_carrier_off(dev);
1830 
1831 #ifdef CONFIG_STMMAC_DEBUG_FS
1832         stmmac_exit_fs();
1833 #endif
1834 
1835         stmmac_release_ptp(priv);
1836 
1837         return 0;
1838 }
1839 
1840 /**
1841  *  stmmac_xmit: Tx entry point of the driver
1842  *  @skb : the socket buffer
1843  *  @dev : device pointer
1844  *  Description : this is the tx entry point of the driver.
1845  *  It programs the chain or the ring and supports oversized frames
1846  *  and SG feature.
1847  */
1848 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1849 {
1850         struct stmmac_priv *priv = netdev_priv(dev);
1851         unsigned int txsize = priv->dma_tx_size;
1852         unsigned int entry;
1853         int i, csum_insertion = 0, is_jumbo = 0;
1854         int nfrags = skb_shinfo(skb)->nr_frags;
1855         struct dma_desc *desc, *first;
1856         unsigned int nopaged_len = skb_headlen(skb);
1857         unsigned int enh_desc = priv->plat->enh_desc;
1858 
1859         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1860                 if (!netif_queue_stopped(dev)) {
1861                         netif_stop_queue(dev);
1862                         /* This is a hard error, log it. */
1863                         pr_err("%s: Tx Ring full when queue awake\n", __func__);
1864                 }
1865                 return NETDEV_TX_BUSY;
1866         }
1867 
1868         spin_lock(&priv->tx_lock);
1869 
1870         if (priv->tx_path_in_lpi_mode)
1871                 stmmac_disable_eee_mode(priv);
1872 
1873         entry = priv->cur_tx % txsize;
1874 
1875         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1876 
1877         if (priv->extend_desc)
1878                 desc = (struct dma_desc *)(priv->dma_etx + entry);
1879         else
1880                 desc = priv->dma_tx + entry;
1881 
1882         first = desc;
1883 
1884         /* To program the descriptors according to the size of the frame */
1885         if (enh_desc)
1886                 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
1887 
1888         if (likely(!is_jumbo)) {
1889                 desc->des2 = dma_map_single(priv->device, skb->data,
1890                                             nopaged_len, DMA_TO_DEVICE);
1891                 priv->tx_skbuff_dma[entry] = desc->des2;
1892                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1893                                                 csum_insertion, priv->mode);
1894         } else {
1895                 desc = first;
1896                 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
1897         }
1898 
1899         for (i = 0; i < nfrags; i++) {
1900                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1901                 int len = skb_frag_size(frag);
1902 
1903                 priv->tx_skbuff[entry] = NULL;
1904                 entry = (++priv->cur_tx) % txsize;
1905                 if (priv->extend_desc)
1906                         desc = (struct dma_desc *)(priv->dma_etx + entry);
1907                 else
1908                         desc = priv->dma_tx + entry;
1909 
1910                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1911                                               DMA_TO_DEVICE);
1912                 priv->tx_skbuff_dma[entry] = desc->des2;
1913                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
1914                                                 priv->mode);
1915                 wmb();
1916                 priv->hw->desc->set_tx_owner(desc);
1917                 wmb();
1918         }
1919 
1920         priv->tx_skbuff[entry] = skb;
1921 
1922         /* Finalize the latest segment. */
1923         priv->hw->desc->close_tx_desc(desc);
1924 
1925         wmb();
1926         /* According to the coalesce parameter the IC bit for the latest
1927          * segment could be reset and the timer re-started to invoke the
1928          * stmmac_tx function. This approach takes care about the fragments.
1929          */
1930         priv->tx_count_frames += nfrags + 1;
1931         if (priv->tx_coal_frames > priv->tx_count_frames) {
1932                 priv->hw->desc->clear_tx_ic(desc);
1933                 priv->xstats.tx_reset_ic_bit++;
1934                 mod_timer(&priv->txtimer,
1935                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
1936         } else
1937                 priv->tx_count_frames = 0;
1938 
1939         /* To avoid raise condition */
1940         priv->hw->desc->set_tx_owner(first);
1941         wmb();
1942 
1943         priv->cur_tx++;
1944 
1945         if (netif_msg_pktdata(priv)) {
1946                 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
1947                         __func__, (priv->cur_tx % txsize),
1948                         (priv->dirty_tx % txsize), entry, first, nfrags);
1949 
1950                 if (priv->extend_desc)
1951                         stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
1952                 else
1953                         stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
1954 
1955                 pr_debug(">>> frame to be transmitted: ");
1956                 print_pkt(skb->data, skb->len);
1957         }
1958         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1959                 if (netif_msg_hw(priv))
1960                         pr_debug("%s: stop transmitted packets\n", __func__);
1961                 netif_stop_queue(dev);
1962         }
1963 
1964         dev->stats.tx_bytes += skb->len;
1965 
1966         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1967                      priv->hwts_tx_en)) {
1968                 /* declare that device is doing timestamping */
1969                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1970                 priv->hw->desc->enable_tx_timestamp(first);
1971         }
1972 
1973         if (!priv->hwts_tx_en)
1974                 skb_tx_timestamp(skb);
1975 
1976         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1977 
1978         spin_unlock(&priv->tx_lock);
1979 
1980         return NETDEV_TX_OK;
1981 }
1982 
1983 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
1984 {
1985         struct ethhdr *ehdr;
1986         u16 vlanid;
1987 
1988         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
1989             NETIF_F_HW_VLAN_CTAG_RX &&
1990             !__vlan_get_tag(skb, &vlanid)) {
1991                 /* pop the vlan tag */
1992                 ehdr = (struct ethhdr *)skb->data;
1993                 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
1994                 skb_pull(skb, VLAN_HLEN);
1995                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
1996         }
1997 }
1998 
1999 
2000 /**
2001  * stmmac_rx_refill: refill used skb preallocated buffers
2002  * @priv: driver private structure
2003  * Description : this is to reallocate the skb for the reception process
2004  * that is based on zero-copy.
2005  */
2006 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2007 {
2008         unsigned int rxsize = priv->dma_rx_size;
2009         int bfsize = priv->dma_buf_sz;
2010 
2011         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
2012                 unsigned int entry = priv->dirty_rx % rxsize;
2013                 struct dma_desc *p;
2014 
2015                 if (priv->extend_desc)
2016                         p = (struct dma_desc *)(priv->dma_erx + entry);
2017                 else
2018                         p = priv->dma_rx + entry;
2019 
2020                 if (likely(priv->rx_skbuff[entry] == NULL)) {
2021                         struct sk_buff *skb;
2022 
2023                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2024 
2025                         if (unlikely(skb == NULL))
2026                                 break;
2027 
2028                         priv->rx_skbuff[entry] = skb;
2029                         priv->rx_skbuff_dma[entry] =
2030                             dma_map_single(priv->device, skb->data, bfsize,
2031                                            DMA_FROM_DEVICE);
2032 
2033                         p->des2 = priv->rx_skbuff_dma[entry];
2034 
2035                         priv->hw->mode->refill_desc3(priv, p);
2036 
2037                         if (netif_msg_rx_status(priv))
2038                                 pr_debug("\trefill entry #%d\n", entry);
2039                 }
2040                 wmb();
2041                 priv->hw->desc->set_rx_owner(p);
2042                 wmb();
2043         }
2044 }
2045 
2046 /**
2047  * stmmac_rx_refill: refill used skb preallocated buffers
2048  * @priv: driver private structure
2049  * @limit: napi bugget.
2050  * Description :  this the function called by the napi poll method.
2051  * It gets all the frames inside the ring.
2052  */
2053 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2054 {
2055         unsigned int rxsize = priv->dma_rx_size;
2056         unsigned int entry = priv->cur_rx % rxsize;
2057         unsigned int next_entry;
2058         unsigned int count = 0;
2059         int coe = priv->plat->rx_coe;
2060 
2061         if (netif_msg_rx_status(priv)) {
2062                 pr_debug("%s: descriptor ring:\n", __func__);
2063                 if (priv->extend_desc)
2064                         stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
2065                 else
2066                         stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
2067         }
2068         while (count < limit) {
2069                 int status;
2070                 struct dma_desc *p;
2071 
2072                 if (priv->extend_desc)
2073                         p = (struct dma_desc *)(priv->dma_erx + entry);
2074                 else
2075                         p = priv->dma_rx + entry;
2076 
2077                 if (priv->hw->desc->get_rx_owner(p))
2078                         break;
2079 
2080                 count++;
2081 
2082                 next_entry = (++priv->cur_rx) % rxsize;
2083                 if (priv->extend_desc)
2084                         prefetch(priv->dma_erx + next_entry);
2085                 else
2086                         prefetch(priv->dma_rx + next_entry);
2087 
2088                 /* read the status of the incoming frame */
2089                 status = priv->hw->desc->rx_status(&priv->dev->stats,
2090                                                    &priv->xstats, p);
2091                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2092                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
2093                                                            &priv->xstats,
2094                                                            priv->dma_erx +
2095                                                            entry);
2096                 if (unlikely(status == discard_frame)) {
2097                         priv->dev->stats.rx_errors++;
2098                         if (priv->hwts_rx_en && !priv->extend_desc) {
2099                                 /* DESC2 & DESC3 will be overwitten by device
2100                                  * with timestamp value, hence reinitialize
2101                                  * them in stmmac_rx_refill() function so that
2102                                  * device can reuse it.
2103                                  */
2104                                 priv->rx_skbuff[entry] = NULL;
2105                                 dma_unmap_single(priv->device,
2106                                                  priv->rx_skbuff_dma[entry],
2107                                                  priv->dma_buf_sz,
2108                                                  DMA_FROM_DEVICE);
2109                         }
2110                 } else {
2111                         struct sk_buff *skb;
2112                         int frame_len;
2113 
2114                         frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2115 
2116                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2117                          * Type frames (LLC/LLC-SNAP)
2118                          */
2119                         if (unlikely(status != llc_snap))
2120                                 frame_len -= ETH_FCS_LEN;
2121 
2122                         if (netif_msg_rx_status(priv)) {
2123                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2124                                          p, entry, p->des2);
2125                                 if (frame_len > ETH_FRAME_LEN)
2126                                         pr_debug("\tframe size %d, COE: %d\n",
2127                                                  frame_len, status);
2128                         }
2129                         skb = priv->rx_skbuff[entry];
2130                         if (unlikely(!skb)) {
2131                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
2132                                        priv->dev->name);
2133                                 priv->dev->stats.rx_dropped++;
2134                                 break;
2135                         }
2136                         prefetch(skb->data - NET_IP_ALIGN);
2137                         priv->rx_skbuff[entry] = NULL;
2138 
2139                         stmmac_get_rx_hwtstamp(priv, entry, skb);
2140 
2141                         skb_put(skb, frame_len);
2142                         dma_unmap_single(priv->device,
2143                                          priv->rx_skbuff_dma[entry],
2144                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
2145 
2146                         if (netif_msg_pktdata(priv)) {
2147                                 pr_debug("frame received (%dbytes)", frame_len);
2148                                 print_pkt(skb->data, frame_len);
2149                         }
2150 
2151                         stmmac_rx_vlan(priv->dev, skb);
2152 
2153                         skb->protocol = eth_type_trans(skb, priv->dev);
2154 
2155                         if (unlikely(!coe))
2156                                 skb_checksum_none_assert(skb);
2157                         else
2158                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2159 
2160                         napi_gro_receive(&priv->napi, skb);
2161 
2162                         priv->dev->stats.rx_packets++;
2163                         priv->dev->stats.rx_bytes += frame_len;
2164                 }
2165                 entry = next_entry;
2166         }
2167 
2168         stmmac_rx_refill(priv);
2169 
2170         priv->xstats.rx_pkt_n += count;
2171 
2172         return count;
2173 }
2174 
2175 /**
2176  *  stmmac_poll - stmmac poll method (NAPI)
2177  *  @napi : pointer to the napi structure.
2178  *  @budget : maximum number of packets that the current CPU can receive from
2179  *            all interfaces.
2180  *  Description :
2181  *  To look at the incoming frames and clear the tx resources.
2182  */
2183 static int stmmac_poll(struct napi_struct *napi, int budget)
2184 {
2185         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2186         int work_done = 0;
2187 
2188         priv->xstats.napi_poll++;
2189         stmmac_tx_clean(priv);
2190 
2191         work_done = stmmac_rx(priv, budget);
2192         if (work_done < budget) {
2193                 napi_complete(napi);
2194                 stmmac_enable_dma_irq(priv);
2195         }
2196         return work_done;
2197 }
2198 
2199 /**
2200  *  stmmac_tx_timeout
2201  *  @dev : Pointer to net device structure
2202  *  Description: this function is called when a packet transmission fails to
2203  *   complete within a reasonable time. The driver will mark the error in the
2204  *   netdev structure and arrange for the device to be reset to a sane state
2205  *   in order to transmit a new packet.
2206  */
2207 static void stmmac_tx_timeout(struct net_device *dev)
2208 {
2209         struct stmmac_priv *priv = netdev_priv(dev);
2210 
2211         /* Clear Tx resources and restart transmitting again */
2212         stmmac_tx_err(priv);
2213 }
2214 
2215 /* Configuration changes (passed on by ifconfig) */
2216 static int stmmac_config(struct net_device *dev, struct ifmap *map)
2217 {
2218         if (dev->flags & IFF_UP)        /* can't act on a running interface */
2219                 return -EBUSY;
2220 
2221         /* Don't allow changing the I/O address */
2222         if (map->base_addr != dev->base_addr) {
2223                 pr_warn("%s: can't change I/O address\n", dev->name);
2224                 return -EOPNOTSUPP;
2225         }
2226 
2227         /* Don't allow changing the IRQ */
2228         if (map->irq != dev->irq) {
2229                 pr_warn("%s: not change IRQ number %d\n", dev->name, dev->irq);
2230                 return -EOPNOTSUPP;
2231         }
2232 
2233         return 0;
2234 }
2235 
2236 /**
2237  *  stmmac_set_rx_mode - entry point for multicast addressing
2238  *  @dev : pointer to the device structure
2239  *  Description:
2240  *  This function is a driver entry point which gets called by the kernel
2241  *  whenever multicast addresses must be enabled/disabled.
2242  *  Return value:
2243  *  void.
2244  */
2245 static void stmmac_set_rx_mode(struct net_device *dev)
2246 {
2247         struct stmmac_priv *priv = netdev_priv(dev);
2248 
2249         spin_lock(&priv->lock);
2250         priv->hw->mac->set_filter(dev, priv->synopsys_id);
2251         spin_unlock(&priv->lock);
2252 }
2253 
2254 /**
2255  *  stmmac_change_mtu - entry point to change MTU size for the device.
2256  *  @dev : device pointer.
2257  *  @new_mtu : the new MTU size for the device.
2258  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
2259  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
2260  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
2261  *  Return value:
2262  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2263  *  file on failure.
2264  */
2265 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2266 {
2267         struct stmmac_priv *priv = netdev_priv(dev);
2268         int max_mtu;
2269 
2270         if (netif_running(dev)) {
2271                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2272                 return -EBUSY;
2273         }
2274 
2275         if (priv->plat->enh_desc)
2276                 max_mtu = JUMBO_LEN;
2277         else
2278                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2279 
2280         if (priv->plat->maxmtu < max_mtu)
2281                 max_mtu = priv->plat->maxmtu;
2282 
2283         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2284                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2285                 return -EINVAL;
2286         }
2287 
2288         dev->mtu = new_mtu;
2289         netdev_update_features(dev);
2290 
2291         return 0;
2292 }
2293 
2294 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2295                                              netdev_features_t features)
2296 {
2297         struct stmmac_priv *priv = netdev_priv(dev);
2298 
2299         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2300                 features &= ~NETIF_F_RXCSUM;
2301         else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1)
2302                 features &= ~NETIF_F_IPV6_CSUM;
2303         if (!priv->plat->tx_coe)
2304                 features &= ~NETIF_F_ALL_CSUM;
2305 
2306         /* Some GMAC devices have a bugged Jumbo frame support that
2307          * needs to have the Tx COE disabled for oversized frames
2308          * (due to limited buffer sizes). In this case we disable
2309          * the TX csum insertionin the TDES and not use SF.
2310          */
2311         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2312                 features &= ~NETIF_F_ALL_CSUM;
2313 
2314         return features;
2315 }
2316 
2317 /**
2318  *  stmmac_interrupt - main ISR
2319  *  @irq: interrupt number.
2320  *  @dev_id: to pass the net device pointer.
2321  *  Description: this is the main driver interrupt service routine.
2322  *  It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI
2323  *  interrupts.
2324  */
2325 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2326 {
2327         struct net_device *dev = (struct net_device *)dev_id;
2328         struct stmmac_priv *priv = netdev_priv(dev);
2329 
2330         if (priv->irq_wake)
2331                 pm_wakeup_event(priv->device, 0);
2332 
2333         if (unlikely(!dev)) {
2334                 pr_err("%s: invalid dev pointer\n", __func__);
2335                 return IRQ_NONE;
2336         }
2337 
2338         /* To handle GMAC own interrupts */
2339         if (priv->plat->has_gmac) {
2340                 int status = priv->hw->mac->host_irq_status((void __iomem *)
2341                                                             dev->base_addr,
2342                                                             &priv->xstats);
2343                 if (unlikely(status)) {
2344                         /* For LPI we need to save the tx status */
2345                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2346                                 priv->tx_path_in_lpi_mode = true;
2347                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2348                                 priv->tx_path_in_lpi_mode = false;
2349                 }
2350         }
2351 
2352         /* To handle DMA interrupts */
2353         stmmac_dma_interrupt(priv);
2354 
2355         return IRQ_HANDLED;
2356 }
2357 
2358 #ifdef CONFIG_NET_POLL_CONTROLLER
2359 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2360  * to allow network I/O with interrupts disabled.
2361  */
2362 static void stmmac_poll_controller(struct net_device *dev)
2363 {
2364         disable_irq(dev->irq);
2365         stmmac_interrupt(dev->irq, dev);
2366         enable_irq(dev->irq);
2367 }
2368 #endif
2369 
2370 /**
2371  *  stmmac_ioctl - Entry point for the Ioctl
2372  *  @dev: Device pointer.
2373  *  @rq: An IOCTL specefic structure, that can contain a pointer to
2374  *  a proprietary structure used to pass information to the driver.
2375  *  @cmd: IOCTL command
2376  *  Description:
2377  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2378  */
2379 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2380 {
2381         struct stmmac_priv *priv = netdev_priv(dev);
2382         int ret = -EOPNOTSUPP;
2383 
2384         if (!netif_running(dev))
2385                 return -EINVAL;
2386 
2387         switch (cmd) {
2388         case SIOCGMIIPHY:
2389         case SIOCGMIIREG:
2390         case SIOCSMIIREG:
2391                 if (!priv->phydev)
2392                         return -EINVAL;
2393                 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2394                 break;
2395         case SIOCSHWTSTAMP:
2396                 ret = stmmac_hwtstamp_ioctl(dev, rq);
2397                 break;
2398         default:
2399                 break;
2400         }
2401 
2402         return ret;
2403 }
2404 
2405 #ifdef CONFIG_STMMAC_DEBUG_FS
2406 static struct dentry *stmmac_fs_dir;
2407 static struct dentry *stmmac_rings_status;
2408 static struct dentry *stmmac_dma_cap;
2409 
2410 static void sysfs_display_ring(void *head, int size, int extend_desc,
2411                                struct seq_file *seq)
2412 {
2413         int i;
2414         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2415         struct dma_desc *p = (struct dma_desc *)head;
2416 
2417         for (i = 0; i < size; i++) {
2418                 u64 x;
2419                 if (extend_desc) {
2420                         x = *(u64 *) ep;
2421                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2422                                    i, (unsigned int)virt_to_phys(ep),
2423                                    (unsigned int)x, (unsigned int)(x >> 32),
2424                                    ep->basic.des2, ep->basic.des3);
2425                         ep++;
2426                 } else {
2427                         x = *(u64 *) p;
2428                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2429                                    i, (unsigned int)virt_to_phys(ep),
2430                                    (unsigned int)x, (unsigned int)(x >> 32),
2431                                    p->des2, p->des3);
2432                         p++;
2433                 }
2434                 seq_printf(seq, "\n");
2435         }
2436 }
2437 
2438 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2439 {
2440         struct net_device *dev = seq->private;
2441         struct stmmac_priv *priv = netdev_priv(dev);
2442         unsigned int txsize = priv->dma_tx_size;
2443         unsigned int rxsize = priv->dma_rx_size;
2444 
2445         if (priv->extend_desc) {
2446                 seq_printf(seq, "Extended RX descriptor ring:\n");
2447                 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq);
2448                 seq_printf(seq, "Extended TX descriptor ring:\n");
2449                 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq);
2450         } else {
2451                 seq_printf(seq, "RX descriptor ring:\n");
2452                 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
2453                 seq_printf(seq, "TX descriptor ring:\n");
2454                 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
2455         }
2456 
2457         return 0;
2458 }
2459 
2460 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2461 {
2462         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2463 }
2464 
2465 static const struct file_operations stmmac_rings_status_fops = {
2466         .owner = THIS_MODULE,
2467         .open = stmmac_sysfs_ring_open,
2468         .read = seq_read,
2469         .llseek = seq_lseek,
2470         .release = single_release,
2471 };
2472 
2473 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2474 {
2475         struct net_device *dev = seq->private;
2476         struct stmmac_priv *priv = netdev_priv(dev);
2477 
2478         if (!priv->hw_cap_support) {
2479                 seq_printf(seq, "DMA HW features not supported\n");
2480                 return 0;
2481         }
2482 
2483         seq_printf(seq, "==============================\n");
2484         seq_printf(seq, "\tDMA HW features\n");
2485         seq_printf(seq, "==============================\n");
2486 
2487         seq_printf(seq, "\t10/100 Mbps %s\n",
2488                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2489         seq_printf(seq, "\t1000 Mbps %s\n",
2490                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
2491         seq_printf(seq, "\tHalf duple %s\n",
2492                    (priv->dma_cap.half_duplex) ? "Y" : "N");
2493         seq_printf(seq, "\tHash Filter: %s\n",
2494                    (priv->dma_cap.hash_filter) ? "Y" : "N");
2495         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2496                    (priv->dma_cap.multi_addr) ? "Y" : "N");
2497         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2498                    (priv->dma_cap.pcs) ? "Y" : "N");
2499         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2500                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
2501         seq_printf(seq, "\tPMT Remote wake up: %s\n",
2502                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2503         seq_printf(seq, "\tPMT Magic Frame: %s\n",
2504                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2505         seq_printf(seq, "\tRMON module: %s\n",
2506                    (priv->dma_cap.rmon) ? "Y" : "N");
2507         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2508                    (priv->dma_cap.time_stamp) ? "Y" : "N");
2509         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2510                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
2511         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2512                    (priv->dma_cap.eee) ? "Y" : "N");
2513         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2514         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2515                    (priv->dma_cap.tx_coe) ? "Y" : "N");
2516         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2517                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2518         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2519                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2520         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2521                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2522         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2523                    priv->dma_cap.number_rx_channel);
2524         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2525                    priv->dma_cap.number_tx_channel);
2526         seq_printf(seq, "\tEnhanced descriptors: %s\n",
2527                    (priv->dma_cap.enh_desc) ? "Y" : "N");
2528 
2529         return 0;
2530 }
2531 
2532 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2533 {
2534         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2535 }
2536 
2537 static const struct file_operations stmmac_dma_cap_fops = {
2538         .owner = THIS_MODULE,
2539         .open = stmmac_sysfs_dma_cap_open,
2540         .read = seq_read,
2541         .llseek = seq_lseek,
2542         .release = single_release,
2543 };
2544 
2545 static int stmmac_init_fs(struct net_device *dev)
2546 {
2547         /* Create debugfs entries */
2548         stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
2549 
2550         if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
2551                 pr_err("ERROR %s, debugfs create directory failed\n",
2552                        STMMAC_RESOURCE_NAME);
2553 
2554                 return -ENOMEM;
2555         }
2556 
2557         /* Entry to report DMA RX/TX rings */
2558         stmmac_rings_status = debugfs_create_file("descriptors_status",
2559                                                   S_IRUGO, stmmac_fs_dir, dev,
2560                                                   &stmmac_rings_status_fops);
2561 
2562         if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
2563                 pr_info("ERROR creating stmmac ring debugfs file\n");
2564                 debugfs_remove(stmmac_fs_dir);
2565 
2566                 return -ENOMEM;
2567         }
2568 
2569         /* Entry to report the DMA HW features */
2570         stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
2571                                              dev, &stmmac_dma_cap_fops);
2572 
2573         if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
2574                 pr_info("ERROR creating stmmac MMC debugfs file\n");
2575                 debugfs_remove(stmmac_rings_status);
2576                 debugfs_remove(stmmac_fs_dir);
2577 
2578                 return -ENOMEM;
2579         }
2580 
2581         return 0;
2582 }
2583 
2584 static void stmmac_exit_fs(void)
2585 {
2586         debugfs_remove(stmmac_rings_status);
2587         debugfs_remove(stmmac_dma_cap);
2588         debugfs_remove(stmmac_fs_dir);
2589 }
2590 #endif /* CONFIG_STMMAC_DEBUG_FS */
2591 
2592 static const struct net_device_ops stmmac_netdev_ops = {
2593         .ndo_open = stmmac_open,
2594         .ndo_start_xmit = stmmac_xmit,
2595         .ndo_stop = stmmac_release,
2596         .ndo_change_mtu = stmmac_change_mtu,
2597         .ndo_fix_features = stmmac_fix_features,
2598         .ndo_set_rx_mode = stmmac_set_rx_mode,
2599         .ndo_tx_timeout = stmmac_tx_timeout,
2600         .ndo_do_ioctl = stmmac_ioctl,
2601         .ndo_set_config = stmmac_config,
2602 #ifdef CONFIG_NET_POLL_CONTROLLER
2603         .ndo_poll_controller = stmmac_poll_controller,
2604 #endif
2605         .ndo_set_mac_address = eth_mac_addr,
2606 };
2607 
2608 /**
2609  *  stmmac_hw_init - Init the MAC device
2610  *  @priv: driver private structure
2611  *  Description: this function detects which MAC device
2612  *  (GMAC/MAC10-100) has to attached, checks the HW capability
2613  *  (if supported) and sets the driver's features (for example
2614  *  to use the ring or chaine mode or support the normal/enh
2615  *  descriptor structure).
2616  */
2617 static int stmmac_hw_init(struct stmmac_priv *priv)
2618 {
2619         int ret;
2620         struct mac_device_info *mac;
2621 
2622         /* Identify the MAC HW device */
2623         if (priv->plat->has_gmac) {
2624                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2625                 mac = dwmac1000_setup(priv->ioaddr);
2626         } else {
2627                 mac = dwmac100_setup(priv->ioaddr);
2628         }
2629         if (!mac)
2630                 return -ENOMEM;
2631 
2632         priv->hw = mac;
2633 
2634         /* Get and dump the chip ID */
2635         priv->synopsys_id = stmmac_get_synopsys_id(priv);
2636 
2637         /* To use the chained or ring mode */
2638         if (chain_mode) {
2639                 priv->hw->mode = &chain_mode_ops;
2640                 pr_info(" Chain mode enabled\n");
2641                 priv->mode = STMMAC_CHAIN_MODE;
2642         } else {
2643                 priv->hw->mode = &ring_mode_ops;
2644                 pr_info(" Ring mode enabled\n");
2645                 priv->mode = STMMAC_RING_MODE;
2646         }
2647 
2648         /* Get the HW capability (new GMAC newer than 3.50a) */
2649         priv->hw_cap_support = stmmac_get_hw_features(priv);
2650         if (priv->hw_cap_support) {
2651                 pr_info(" DMA HW capability register supported");
2652 
2653                 /* We can override some gmac/dma configuration fields: e.g.
2654                  * enh_desc, tx_coe (e.g. that are passed through the
2655                  * platform) with the values from the HW capability
2656                  * register (if supported).
2657                  */
2658                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2659                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2660 
2661                 priv->plat->tx_coe = priv->dma_cap.tx_coe;
2662 
2663                 if (priv->dma_cap.rx_coe_type2)
2664                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2665                 else if (priv->dma_cap.rx_coe_type1)
2666                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2667 
2668         } else
2669                 pr_info(" No HW DMA feature register supported");
2670 
2671         /* To use alternate (extended) or normal descriptor structures */
2672         stmmac_selec_desc_mode(priv);
2673 
2674         ret = priv->hw->mac->rx_ipc(priv->ioaddr);
2675         if (!ret) {
2676                 pr_warn(" RX IPC Checksum Offload not configured.\n");
2677                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2678         }
2679 
2680         if (priv->plat->rx_coe)
2681                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2682                         priv->plat->rx_coe);
2683         if (priv->plat->tx_coe)
2684                 pr_info(" TX Checksum insertion supported\n");
2685 
2686         if (priv->plat->pmt) {
2687                 pr_info(" Wake-Up On Lan supported\n");
2688                 device_set_wakeup_capable(priv->device, 1);
2689         }
2690 
2691         return 0;
2692 }
2693 
2694 /**
2695  * stmmac_dvr_probe
2696  * @device: device pointer
2697  * @plat_dat: platform data pointer
2698  * @addr: iobase memory address
2699  * Description: this is the main probe function used to
2700  * call the alloc_etherdev, allocate the priv structure.
2701  */
2702 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
2703                                      struct plat_stmmacenet_data *plat_dat,
2704                                      void __iomem *addr)
2705 {
2706         int ret = 0;
2707         struct net_device *ndev = NULL;
2708         struct stmmac_priv *priv;
2709 
2710         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2711         if (!ndev)
2712                 return NULL;
2713 
2714         SET_NETDEV_DEV(ndev, device);
2715 
2716         priv = netdev_priv(ndev);
2717         priv->device = device;
2718         priv->dev = ndev;
2719 
2720         ether_setup(ndev);
2721 
2722         stmmac_set_ethtool_ops(ndev);
2723         priv->pause = pause;
2724         priv->plat = plat_dat;
2725         priv->ioaddr = addr;
2726         priv->dev->base_addr = (unsigned long)addr;
2727 
2728         /* Verify driver arguments */
2729         stmmac_verify_args();
2730 
2731         /* Override with kernel parameters if supplied XXX CRS XXX
2732          * this needs to have multiple instances
2733          */
2734         if ((phyaddr >= 0) && (phyaddr <= 31))
2735                 priv->plat->phy_addr = phyaddr;
2736 
2737         priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
2738         if (IS_ERR(priv->stmmac_clk)) {
2739                 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
2740                          __func__);
2741                 ret = PTR_ERR(priv->stmmac_clk);
2742                 goto error_clk_get;
2743         }
2744         clk_prepare_enable(priv->stmmac_clk);
2745 
2746         priv->stmmac_rst = devm_reset_control_get(priv->device,
2747                                                   STMMAC_RESOURCE_NAME);
2748         if (IS_ERR(priv->stmmac_rst)) {
2749                 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
2750                         ret = -EPROBE_DEFER;
2751                         goto error_hw_init;
2752                 }
2753                 dev_info(priv->device, "no reset control found\n");
2754                 priv->stmmac_rst = NULL;
2755         }
2756         if (priv->stmmac_rst)
2757                 reset_control_deassert(priv->stmmac_rst);
2758 
2759         /* Init MAC and get the capabilities */
2760         ret = stmmac_hw_init(priv);
2761         if (ret)
2762                 goto error_hw_init;
2763 
2764         ndev->netdev_ops = &stmmac_netdev_ops;
2765 
2766         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2767                             NETIF_F_RXCSUM;
2768         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2769         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2770 #ifdef STMMAC_VLAN_TAG_USED
2771         /* Both mac100 and gmac support receive VLAN tag detection */
2772         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2773 #endif
2774         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2775 
2776         if (flow_ctrl)
2777                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
2778 
2779         /* Rx Watchdog is available in the COREs newer than the 3.40.
2780          * In some case, for example on bugged HW this feature
2781          * has to be disable and this can be done by passing the
2782          * riwt_off field from the platform.
2783          */
2784         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2785                 priv->use_riwt = 1;
2786                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2787         }
2788 
2789         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2790 
2791         spin_lock_init(&priv->lock);
2792         spin_lock_init(&priv->tx_lock);
2793 
2794         ret = register_netdev(ndev);
2795         if (ret) {
2796                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2797                 goto error_netdev_register;
2798         }
2799 
2800         /* If a specific clk_csr value is passed from the platform
2801          * this means that the CSR Clock Range selection cannot be
2802          * changed at run-time and it is fixed. Viceversa the driver'll try to
2803          * set the MDC clock dynamically according to the csr actual
2804          * clock input.
2805          */
2806         if (!priv->plat->clk_csr)
2807                 stmmac_clk_csr_set(priv);
2808         else
2809                 priv->clk_csr = priv->plat->clk_csr;
2810 
2811         stmmac_check_pcs_mode(priv);
2812 
2813         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2814             priv->pcs != STMMAC_PCS_RTBI) {
2815                 /* MDIO bus Registration */
2816                 ret = stmmac_mdio_register(ndev);
2817                 if (ret < 0) {
2818                         pr_debug("%s: MDIO bus (id: %d) registration failed",
2819                                  __func__, priv->plat->bus_id);
2820                         goto error_mdio_register;
2821                 }
2822         }
2823 
2824         return priv;
2825 
2826 error_mdio_register:
2827         unregister_netdev(ndev);
2828 error_netdev_register:
2829         netif_napi_del(&priv->napi);
2830 error_hw_init:
2831         clk_disable_unprepare(priv->stmmac_clk);
2832 error_clk_get:
2833         free_netdev(ndev);
2834 
2835         return ERR_PTR(ret);
2836 }
2837 
2838 /**
2839  * stmmac_dvr_remove
2840  * @ndev: net device pointer
2841  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2842  * changes the link status, releases the DMA descriptor rings.
2843  */
2844 int stmmac_dvr_remove(struct net_device *ndev)
2845 {
2846         struct stmmac_priv *priv = netdev_priv(ndev);
2847 
2848         pr_info("%s:\n\tremoving driver", __func__);
2849 
2850         priv->hw->dma->stop_rx(priv->ioaddr);
2851         priv->hw->dma->stop_tx(priv->ioaddr);
2852 
2853         stmmac_set_mac(priv->ioaddr, false);
2854         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2855             priv->pcs != STMMAC_PCS_RTBI)
2856                 stmmac_mdio_unregister(ndev);
2857         netif_carrier_off(ndev);
2858         unregister_netdev(ndev);
2859         if (priv->stmmac_rst)
2860                 reset_control_assert(priv->stmmac_rst);
2861         clk_disable_unprepare(priv->stmmac_clk);
2862         free_netdev(ndev);
2863 
2864         return 0;
2865 }
2866 
2867 #ifdef CONFIG_PM
2868 int stmmac_suspend(struct net_device *ndev)
2869 {
2870         struct stmmac_priv *priv = netdev_priv(ndev);
2871         unsigned long flags;
2872 
2873         if (!ndev || !netif_running(ndev))
2874                 return 0;
2875 
2876         if (priv->phydev)
2877                 phy_stop(priv->phydev);
2878 
2879         spin_lock_irqsave(&priv->lock, flags);
2880 
2881         netif_device_detach(ndev);
2882         netif_stop_queue(ndev);
2883 
2884         napi_disable(&priv->napi);
2885 
2886         /* Stop TX/RX DMA */
2887         priv->hw->dma->stop_tx(priv->ioaddr);
2888         priv->hw->dma->stop_rx(priv->ioaddr);
2889 
2890         stmmac_clear_descriptors(priv);
2891 
2892         /* Enable Power down mode by programming the PMT regs */
2893         if (device_may_wakeup(priv->device)) {
2894                 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
2895                 priv->irq_wake = 1;
2896         } else {
2897                 stmmac_set_mac(priv->ioaddr, false);
2898                 pinctrl_pm_select_sleep_state(priv->device);
2899                 /* Disable clock in case of PWM is off */
2900                 clk_disable_unprepare(priv->stmmac_clk);
2901         }
2902         spin_unlock_irqrestore(&priv->lock, flags);
2903         return 0;
2904 }
2905 
2906 int stmmac_resume(struct net_device *ndev)
2907 {
2908         struct stmmac_priv *priv = netdev_priv(ndev);
2909         unsigned long flags;
2910 
2911         if (!netif_running(ndev))
2912                 return 0;
2913 
2914         spin_lock_irqsave(&priv->lock, flags);
2915 
2916         /* Power Down bit, into the PM register, is cleared
2917          * automatically as soon as a magic packet or a Wake-up frame
2918          * is received. Anyway, it's better to manually clear
2919          * this bit because it can generate problems while resuming
2920          * from another devices (e.g. serial console).
2921          */
2922         if (device_may_wakeup(priv->device)) {
2923                 priv->hw->mac->pmt(priv->ioaddr, 0);
2924                 priv->irq_wake = 0;
2925         } else {
2926                 pinctrl_pm_select_default_state(priv->device);
2927                 /* enable the clk prevously disabled */
2928                 clk_prepare_enable(priv->stmmac_clk);
2929                 /* reset the phy so that it's ready */
2930                 if (priv->mii)
2931                         stmmac_mdio_reset(priv->mii);
2932         }
2933 
2934         netif_device_attach(ndev);
2935 
2936         stmmac_hw_setup(ndev);
2937 
2938         napi_enable(&priv->napi);
2939 
2940         netif_start_queue(ndev);
2941 
2942         spin_unlock_irqrestore(&priv->lock, flags);
2943 
2944         if (priv->phydev)
2945                 phy_start(priv->phydev);
2946 
2947         return 0;
2948 }
2949 #endif /* CONFIG_PM */
2950 
2951 /* Driver can be configured w/ and w/ both PCI and Platf drivers
2952  * depending on the configuration selected.
2953  */
2954 static int __init stmmac_init(void)
2955 {
2956         int ret;
2957 
2958         ret = stmmac_register_platform();
2959         if (ret)
2960                 goto err;
2961         ret = stmmac_register_pci();
2962         if (ret)
2963                 goto err_pci;
2964         return 0;
2965 err_pci:
2966         stmmac_unregister_platform();
2967 err:
2968         pr_err("stmmac: driver registration failed\n");
2969         return ret;
2970 }
2971 
2972 static void __exit stmmac_exit(void)
2973 {
2974         stmmac_unregister_platform();
2975         stmmac_unregister_pci();
2976 }
2977 
2978 module_init(stmmac_init);
2979 module_exit(stmmac_exit);
2980 
2981 #ifndef MODULE
2982 static int __init stmmac_cmdline_opt(char *str)
2983 {
2984         char *opt;
2985 
2986         if (!str || !*str)
2987                 return -EINVAL;
2988         while ((opt = strsep(&str, ",")) != NULL) {
2989                 if (!strncmp(opt, "debug:", 6)) {
2990                         if (kstrtoint(opt + 6, 0, &debug))
2991                                 goto err;
2992                 } else if (!strncmp(opt, "phyaddr:", 8)) {
2993                         if (kstrtoint(opt + 8, 0, &phyaddr))
2994                                 goto err;
2995                 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2996                         if (kstrtoint(opt + 11, 0, &dma_txsize))
2997                                 goto err;
2998                 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2999                         if (kstrtoint(opt + 11, 0, &dma_rxsize))
3000                                 goto err;
3001                 } else if (!strncmp(opt, "buf_sz:", 7)) {
3002                         if (kstrtoint(opt + 7, 0, &buf_sz))
3003                                 goto err;
3004                 } else if (!strncmp(opt, "tc:", 3)) {
3005                         if (kstrtoint(opt + 3, 0, &tc))
3006                                 goto err;
3007                 } else if (!strncmp(opt, "watchdog:", 9)) {
3008                         if (kstrtoint(opt + 9, 0, &watchdog))
3009                                 goto err;
3010                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
3011                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
3012                                 goto err;
3013                 } else if (!strncmp(opt, "pause:", 6)) {
3014                         if (kstrtoint(opt + 6, 0, &pause))
3015                                 goto err;
3016                 } else if (!strncmp(opt, "eee_timer:", 10)) {
3017                         if (kstrtoint(opt + 10, 0, &eee_timer))
3018                                 goto err;
3019                 } else if (!strncmp(opt, "chain_mode:", 11)) {
3020                         if (kstrtoint(opt + 11, 0, &chain_mode))
3021                                 goto err;
3022                 }
3023         }
3024         return 0;
3025 
3026 err:
3027         pr_err("%s: ERROR broken module parameter conversion", __func__);
3028         return -EINVAL;
3029 }
3030 
3031 __setup("stmmaceth=", stmmac_cmdline_opt);
3032 #endif /* MODULE */
3033 
3034 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3035 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3036 MODULE_LICENSE("GPL");
3037 

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