Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5

Linux/drivers/net/ethernet/renesas/sh_eth.c

  1 /*  SuperH Ethernet device driver
  2  *
  3  *  Copyright (C) 2014  Renesas Electronics Corporation
  4  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
  5  *  Copyright (C) 2008-2014 Renesas Solutions Corp.
  6  *  Copyright (C) 2013-2014 Cogent Embedded, Inc.
  7  *  Copyright (C) 2014 Codethink Limited
  8  *
  9  *  This program is free software; you can redistribute it and/or modify it
 10  *  under the terms and conditions of the GNU General Public License,
 11  *  version 2, as published by the Free Software Foundation.
 12  *
 13  *  This program is distributed in the hope it will be useful, but WITHOUT
 14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 15  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 16  *  more details.
 17  *
 18  *  The full GNU General Public License is included in this distribution in
 19  *  the file called "COPYING".
 20  */
 21 
 22 #include <linux/module.h>
 23 #include <linux/kernel.h>
 24 #include <linux/spinlock.h>
 25 #include <linux/interrupt.h>
 26 #include <linux/dma-mapping.h>
 27 #include <linux/etherdevice.h>
 28 #include <linux/delay.h>
 29 #include <linux/platform_device.h>
 30 #include <linux/mdio-bitbang.h>
 31 #include <linux/netdevice.h>
 32 #include <linux/of.h>
 33 #include <linux/of_device.h>
 34 #include <linux/of_irq.h>
 35 #include <linux/of_net.h>
 36 #include <linux/phy.h>
 37 #include <linux/cache.h>
 38 #include <linux/io.h>
 39 #include <linux/pm_runtime.h>
 40 #include <linux/slab.h>
 41 #include <linux/ethtool.h>
 42 #include <linux/if_vlan.h>
 43 #include <linux/clk.h>
 44 #include <linux/sh_eth.h>
 45 #include <linux/of_mdio.h>
 46 
 47 #include "sh_eth.h"
 48 
 49 #define SH_ETH_DEF_MSG_ENABLE \
 50                 (NETIF_MSG_LINK | \
 51                 NETIF_MSG_TIMER | \
 52                 NETIF_MSG_RX_ERR| \
 53                 NETIF_MSG_TX_ERR)
 54 
 55 #define SH_ETH_OFFSET_INVALID   ((u16)~0)
 56 
 57 #define SH_ETH_OFFSET_DEFAULTS                  \
 58         [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
 59 
 60 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
 61         SH_ETH_OFFSET_DEFAULTS,
 62 
 63         [EDSR]          = 0x0000,
 64         [EDMR]          = 0x0400,
 65         [EDTRR]         = 0x0408,
 66         [EDRRR]         = 0x0410,
 67         [EESR]          = 0x0428,
 68         [EESIPR]        = 0x0430,
 69         [TDLAR]         = 0x0010,
 70         [TDFAR]         = 0x0014,
 71         [TDFXR]         = 0x0018,
 72         [TDFFR]         = 0x001c,
 73         [RDLAR]         = 0x0030,
 74         [RDFAR]         = 0x0034,
 75         [RDFXR]         = 0x0038,
 76         [RDFFR]         = 0x003c,
 77         [TRSCER]        = 0x0438,
 78         [RMFCR]         = 0x0440,
 79         [TFTR]          = 0x0448,
 80         [FDR]           = 0x0450,
 81         [RMCR]          = 0x0458,
 82         [RPADIR]        = 0x0460,
 83         [FCFTR]         = 0x0468,
 84         [CSMR]          = 0x04E4,
 85 
 86         [ECMR]          = 0x0500,
 87         [ECSR]          = 0x0510,
 88         [ECSIPR]        = 0x0518,
 89         [PIR]           = 0x0520,
 90         [PSR]           = 0x0528,
 91         [PIPR]          = 0x052c,
 92         [RFLR]          = 0x0508,
 93         [APR]           = 0x0554,
 94         [MPR]           = 0x0558,
 95         [PFTCR]         = 0x055c,
 96         [PFRCR]         = 0x0560,
 97         [TPAUSER]       = 0x0564,
 98         [GECMR]         = 0x05b0,
 99         [BCULR]         = 0x05b4,
100         [MAHR]          = 0x05c0,
101         [MALR]          = 0x05c8,
102         [TROCR]         = 0x0700,
103         [CDCR]          = 0x0708,
104         [LCCR]          = 0x0710,
105         [CEFCR]         = 0x0740,
106         [FRECR]         = 0x0748,
107         [TSFRCR]        = 0x0750,
108         [TLFRCR]        = 0x0758,
109         [RFCR]          = 0x0760,
110         [CERCR]         = 0x0768,
111         [CEECR]         = 0x0770,
112         [MAFCR]         = 0x0778,
113         [RMII_MII]      = 0x0790,
114 
115         [ARSTR]         = 0x0000,
116         [TSU_CTRST]     = 0x0004,
117         [TSU_FWEN0]     = 0x0010,
118         [TSU_FWEN1]     = 0x0014,
119         [TSU_FCM]       = 0x0018,
120         [TSU_BSYSL0]    = 0x0020,
121         [TSU_BSYSL1]    = 0x0024,
122         [TSU_PRISL0]    = 0x0028,
123         [TSU_PRISL1]    = 0x002c,
124         [TSU_FWSL0]     = 0x0030,
125         [TSU_FWSL1]     = 0x0034,
126         [TSU_FWSLC]     = 0x0038,
127         [TSU_QTAG0]     = 0x0040,
128         [TSU_QTAG1]     = 0x0044,
129         [TSU_FWSR]      = 0x0050,
130         [TSU_FWINMK]    = 0x0054,
131         [TSU_ADQT0]     = 0x0048,
132         [TSU_ADQT1]     = 0x004c,
133         [TSU_VTAG0]     = 0x0058,
134         [TSU_VTAG1]     = 0x005c,
135         [TSU_ADSBSY]    = 0x0060,
136         [TSU_TEN]       = 0x0064,
137         [TSU_POST1]     = 0x0070,
138         [TSU_POST2]     = 0x0074,
139         [TSU_POST3]     = 0x0078,
140         [TSU_POST4]     = 0x007c,
141         [TSU_ADRH0]     = 0x0100,
142 
143         [TXNLCR0]       = 0x0080,
144         [TXALCR0]       = 0x0084,
145         [RXNLCR0]       = 0x0088,
146         [RXALCR0]       = 0x008c,
147         [FWNLCR0]       = 0x0090,
148         [FWALCR0]       = 0x0094,
149         [TXNLCR1]       = 0x00a0,
150         [TXALCR1]       = 0x00a0,
151         [RXNLCR1]       = 0x00a8,
152         [RXALCR1]       = 0x00ac,
153         [FWNLCR1]       = 0x00b0,
154         [FWALCR1]       = 0x00b4,
155 };
156 
157 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
158         SH_ETH_OFFSET_DEFAULTS,
159 
160         [EDSR]          = 0x0000,
161         [EDMR]          = 0x0400,
162         [EDTRR]         = 0x0408,
163         [EDRRR]         = 0x0410,
164         [EESR]          = 0x0428,
165         [EESIPR]        = 0x0430,
166         [TDLAR]         = 0x0010,
167         [TDFAR]         = 0x0014,
168         [TDFXR]         = 0x0018,
169         [TDFFR]         = 0x001c,
170         [RDLAR]         = 0x0030,
171         [RDFAR]         = 0x0034,
172         [RDFXR]         = 0x0038,
173         [RDFFR]         = 0x003c,
174         [TRSCER]        = 0x0438,
175         [RMFCR]         = 0x0440,
176         [TFTR]          = 0x0448,
177         [FDR]           = 0x0450,
178         [RMCR]          = 0x0458,
179         [RPADIR]        = 0x0460,
180         [FCFTR]         = 0x0468,
181         [CSMR]          = 0x04E4,
182 
183         [ECMR]          = 0x0500,
184         [RFLR]          = 0x0508,
185         [ECSR]          = 0x0510,
186         [ECSIPR]        = 0x0518,
187         [PIR]           = 0x0520,
188         [APR]           = 0x0554,
189         [MPR]           = 0x0558,
190         [PFTCR]         = 0x055c,
191         [PFRCR]         = 0x0560,
192         [TPAUSER]       = 0x0564,
193         [MAHR]          = 0x05c0,
194         [MALR]          = 0x05c8,
195         [CEFCR]         = 0x0740,
196         [FRECR]         = 0x0748,
197         [TSFRCR]        = 0x0750,
198         [TLFRCR]        = 0x0758,
199         [RFCR]          = 0x0760,
200         [MAFCR]         = 0x0778,
201 
202         [ARSTR]         = 0x0000,
203         [TSU_CTRST]     = 0x0004,
204         [TSU_VTAG0]     = 0x0058,
205         [TSU_ADSBSY]    = 0x0060,
206         [TSU_TEN]       = 0x0064,
207         [TSU_ADRH0]     = 0x0100,
208 
209         [TXNLCR0]       = 0x0080,
210         [TXALCR0]       = 0x0084,
211         [RXNLCR0]       = 0x0088,
212         [RXALCR0]       = 0x008C,
213 };
214 
215 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
216         SH_ETH_OFFSET_DEFAULTS,
217 
218         [ECMR]          = 0x0300,
219         [RFLR]          = 0x0308,
220         [ECSR]          = 0x0310,
221         [ECSIPR]        = 0x0318,
222         [PIR]           = 0x0320,
223         [PSR]           = 0x0328,
224         [RDMLR]         = 0x0340,
225         [IPGR]          = 0x0350,
226         [APR]           = 0x0354,
227         [MPR]           = 0x0358,
228         [RFCF]          = 0x0360,
229         [TPAUSER]       = 0x0364,
230         [TPAUSECR]      = 0x0368,
231         [MAHR]          = 0x03c0,
232         [MALR]          = 0x03c8,
233         [TROCR]         = 0x03d0,
234         [CDCR]          = 0x03d4,
235         [LCCR]          = 0x03d8,
236         [CNDCR]         = 0x03dc,
237         [CEFCR]         = 0x03e4,
238         [FRECR]         = 0x03e8,
239         [TSFRCR]        = 0x03ec,
240         [TLFRCR]        = 0x03f0,
241         [RFCR]          = 0x03f4,
242         [MAFCR]         = 0x03f8,
243 
244         [EDMR]          = 0x0200,
245         [EDTRR]         = 0x0208,
246         [EDRRR]         = 0x0210,
247         [TDLAR]         = 0x0218,
248         [RDLAR]         = 0x0220,
249         [EESR]          = 0x0228,
250         [EESIPR]        = 0x0230,
251         [TRSCER]        = 0x0238,
252         [RMFCR]         = 0x0240,
253         [TFTR]          = 0x0248,
254         [FDR]           = 0x0250,
255         [RMCR]          = 0x0258,
256         [TFUCR]         = 0x0264,
257         [RFOCR]         = 0x0268,
258         [RMIIMODE]      = 0x026c,
259         [FCFTR]         = 0x0270,
260         [TRIMD]         = 0x027c,
261 };
262 
263 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
264         SH_ETH_OFFSET_DEFAULTS,
265 
266         [ECMR]          = 0x0100,
267         [RFLR]          = 0x0108,
268         [ECSR]          = 0x0110,
269         [ECSIPR]        = 0x0118,
270         [PIR]           = 0x0120,
271         [PSR]           = 0x0128,
272         [RDMLR]         = 0x0140,
273         [IPGR]          = 0x0150,
274         [APR]           = 0x0154,
275         [MPR]           = 0x0158,
276         [TPAUSER]       = 0x0164,
277         [RFCF]          = 0x0160,
278         [TPAUSECR]      = 0x0168,
279         [BCFRR]         = 0x016c,
280         [MAHR]          = 0x01c0,
281         [MALR]          = 0x01c8,
282         [TROCR]         = 0x01d0,
283         [CDCR]          = 0x01d4,
284         [LCCR]          = 0x01d8,
285         [CNDCR]         = 0x01dc,
286         [CEFCR]         = 0x01e4,
287         [FRECR]         = 0x01e8,
288         [TSFRCR]        = 0x01ec,
289         [TLFRCR]        = 0x01f0,
290         [RFCR]          = 0x01f4,
291         [MAFCR]         = 0x01f8,
292         [RTRATE]        = 0x01fc,
293 
294         [EDMR]          = 0x0000,
295         [EDTRR]         = 0x0008,
296         [EDRRR]         = 0x0010,
297         [TDLAR]         = 0x0018,
298         [RDLAR]         = 0x0020,
299         [EESR]          = 0x0028,
300         [EESIPR]        = 0x0030,
301         [TRSCER]        = 0x0038,
302         [RMFCR]         = 0x0040,
303         [TFTR]          = 0x0048,
304         [FDR]           = 0x0050,
305         [RMCR]          = 0x0058,
306         [TFUCR]         = 0x0064,
307         [RFOCR]         = 0x0068,
308         [FCFTR]         = 0x0070,
309         [RPADIR]        = 0x0078,
310         [TRIMD]         = 0x007c,
311         [RBWAR]         = 0x00c8,
312         [RDFAR]         = 0x00cc,
313         [TBRAR]         = 0x00d4,
314         [TDFAR]         = 0x00d8,
315 };
316 
317 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
318         SH_ETH_OFFSET_DEFAULTS,
319 
320         [EDMR]          = 0x0000,
321         [EDTRR]         = 0x0004,
322         [EDRRR]         = 0x0008,
323         [TDLAR]         = 0x000c,
324         [RDLAR]         = 0x0010,
325         [EESR]          = 0x0014,
326         [EESIPR]        = 0x0018,
327         [TRSCER]        = 0x001c,
328         [RMFCR]         = 0x0020,
329         [TFTR]          = 0x0024,
330         [FDR]           = 0x0028,
331         [RMCR]          = 0x002c,
332         [EDOCR]         = 0x0030,
333         [FCFTR]         = 0x0034,
334         [RPADIR]        = 0x0038,
335         [TRIMD]         = 0x003c,
336         [RBWAR]         = 0x0040,
337         [RDFAR]         = 0x0044,
338         [TBRAR]         = 0x004c,
339         [TDFAR]         = 0x0050,
340 
341         [ECMR]          = 0x0160,
342         [ECSR]          = 0x0164,
343         [ECSIPR]        = 0x0168,
344         [PIR]           = 0x016c,
345         [MAHR]          = 0x0170,
346         [MALR]          = 0x0174,
347         [RFLR]          = 0x0178,
348         [PSR]           = 0x017c,
349         [TROCR]         = 0x0180,
350         [CDCR]          = 0x0184,
351         [LCCR]          = 0x0188,
352         [CNDCR]         = 0x018c,
353         [CEFCR]         = 0x0194,
354         [FRECR]         = 0x0198,
355         [TSFRCR]        = 0x019c,
356         [TLFRCR]        = 0x01a0,
357         [RFCR]          = 0x01a4,
358         [MAFCR]         = 0x01a8,
359         [IPGR]          = 0x01b4,
360         [APR]           = 0x01b8,
361         [MPR]           = 0x01bc,
362         [TPAUSER]       = 0x01c4,
363         [BCFR]          = 0x01cc,
364 
365         [ARSTR]         = 0x0000,
366         [TSU_CTRST]     = 0x0004,
367         [TSU_FWEN0]     = 0x0010,
368         [TSU_FWEN1]     = 0x0014,
369         [TSU_FCM]       = 0x0018,
370         [TSU_BSYSL0]    = 0x0020,
371         [TSU_BSYSL1]    = 0x0024,
372         [TSU_PRISL0]    = 0x0028,
373         [TSU_PRISL1]    = 0x002c,
374         [TSU_FWSL0]     = 0x0030,
375         [TSU_FWSL1]     = 0x0034,
376         [TSU_FWSLC]     = 0x0038,
377         [TSU_QTAGM0]    = 0x0040,
378         [TSU_QTAGM1]    = 0x0044,
379         [TSU_ADQT0]     = 0x0048,
380         [TSU_ADQT1]     = 0x004c,
381         [TSU_FWSR]      = 0x0050,
382         [TSU_FWINMK]    = 0x0054,
383         [TSU_ADSBSY]    = 0x0060,
384         [TSU_TEN]       = 0x0064,
385         [TSU_POST1]     = 0x0070,
386         [TSU_POST2]     = 0x0074,
387         [TSU_POST3]     = 0x0078,
388         [TSU_POST4]     = 0x007c,
389 
390         [TXNLCR0]       = 0x0080,
391         [TXALCR0]       = 0x0084,
392         [RXNLCR0]       = 0x0088,
393         [RXALCR0]       = 0x008c,
394         [FWNLCR0]       = 0x0090,
395         [FWALCR0]       = 0x0094,
396         [TXNLCR1]       = 0x00a0,
397         [TXALCR1]       = 0x00a0,
398         [RXNLCR1]       = 0x00a8,
399         [RXALCR1]       = 0x00ac,
400         [FWNLCR1]       = 0x00b0,
401         [FWALCR1]       = 0x00b4,
402 
403         [TSU_ADRH0]     = 0x0100,
404 };
405 
406 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
407 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
408 
409 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
410 {
411         struct sh_eth_private *mdp = netdev_priv(ndev);
412         u16 offset = mdp->reg_offset[enum_index];
413 
414         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
415                 return;
416 
417         iowrite32(data, mdp->addr + offset);
418 }
419 
420 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
421 {
422         struct sh_eth_private *mdp = netdev_priv(ndev);
423         u16 offset = mdp->reg_offset[enum_index];
424 
425         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
426                 return ~0U;
427 
428         return ioread32(mdp->addr + offset);
429 }
430 
431 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
432 {
433         return mdp->reg_offset == sh_eth_offset_gigabit;
434 }
435 
436 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
437 {
438         return mdp->reg_offset == sh_eth_offset_fast_rz;
439 }
440 
441 static void sh_eth_select_mii(struct net_device *ndev)
442 {
443         u32 value = 0x0;
444         struct sh_eth_private *mdp = netdev_priv(ndev);
445 
446         switch (mdp->phy_interface) {
447         case PHY_INTERFACE_MODE_GMII:
448                 value = 0x2;
449                 break;
450         case PHY_INTERFACE_MODE_MII:
451                 value = 0x1;
452                 break;
453         case PHY_INTERFACE_MODE_RMII:
454                 value = 0x0;
455                 break;
456         default:
457                 netdev_warn(ndev,
458                             "PHY interface mode was not setup. Set to MII.\n");
459                 value = 0x1;
460                 break;
461         }
462 
463         sh_eth_write(ndev, value, RMII_MII);
464 }
465 
466 static void sh_eth_set_duplex(struct net_device *ndev)
467 {
468         struct sh_eth_private *mdp = netdev_priv(ndev);
469 
470         if (mdp->duplex) /* Full */
471                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
472         else            /* Half */
473                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
474 }
475 
476 static void sh_eth_chip_reset(struct net_device *ndev)
477 {
478         struct sh_eth_private *mdp = netdev_priv(ndev);
479 
480         /* reset device */
481         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
482         mdelay(1);
483 }
484 
485 static void sh_eth_set_rate_gether(struct net_device *ndev)
486 {
487         struct sh_eth_private *mdp = netdev_priv(ndev);
488 
489         switch (mdp->speed) {
490         case 10: /* 10BASE */
491                 sh_eth_write(ndev, GECMR_10, GECMR);
492                 break;
493         case 100:/* 100BASE */
494                 sh_eth_write(ndev, GECMR_100, GECMR);
495                 break;
496         case 1000: /* 1000BASE */
497                 sh_eth_write(ndev, GECMR_1000, GECMR);
498                 break;
499         default:
500                 break;
501         }
502 }
503 
504 #ifdef CONFIG_OF
505 /* R7S72100 */
506 static struct sh_eth_cpu_data r7s72100_data = {
507         .chip_reset     = sh_eth_chip_reset,
508         .set_duplex     = sh_eth_set_duplex,
509 
510         .register_type  = SH_ETH_REG_FAST_RZ,
511 
512         .ecsr_value     = ECSR_ICD,
513         .ecsipr_value   = ECSIPR_ICDIP,
514         .eesipr_value   = 0xff7f009f,
515 
516         .tx_check       = EESR_TC1 | EESR_FTC,
517         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
518                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
519                           EESR_TDE | EESR_ECI,
520         .fdr_value      = 0x0000070f,
521 
522         .no_psr         = 1,
523         .apr            = 1,
524         .mpr            = 1,
525         .tpauser        = 1,
526         .hw_swap        = 1,
527         .rpadir         = 1,
528         .rpadir_value   = 2 << 16,
529         .no_trimd       = 1,
530         .no_ade         = 1,
531         .hw_crc         = 1,
532         .tsu            = 1,
533         .shift_rd0      = 1,
534 };
535 
536 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
537 {
538         struct sh_eth_private *mdp = netdev_priv(ndev);
539 
540         /* reset device */
541         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
542         mdelay(1);
543 
544         sh_eth_select_mii(ndev);
545 }
546 
547 /* R8A7740 */
548 static struct sh_eth_cpu_data r8a7740_data = {
549         .chip_reset     = sh_eth_chip_reset_r8a7740,
550         .set_duplex     = sh_eth_set_duplex,
551         .set_rate       = sh_eth_set_rate_gether,
552 
553         .register_type  = SH_ETH_REG_GIGABIT,
554 
555         .ecsr_value     = ECSR_ICD | ECSR_MPD,
556         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
557         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
558 
559         .tx_check       = EESR_TC1 | EESR_FTC,
560         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
561                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
562                           EESR_TDE | EESR_ECI,
563         .fdr_value      = 0x0000070f,
564 
565         .apr            = 1,
566         .mpr            = 1,
567         .tpauser        = 1,
568         .bculr          = 1,
569         .hw_swap        = 1,
570         .rpadir         = 1,
571         .rpadir_value   = 2 << 16,
572         .no_trimd       = 1,
573         .no_ade         = 1,
574         .tsu            = 1,
575         .select_mii     = 1,
576         .shift_rd0      = 1,
577 };
578 
579 /* There is CPU dependent code */
580 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
581 {
582         struct sh_eth_private *mdp = netdev_priv(ndev);
583 
584         switch (mdp->speed) {
585         case 10: /* 10BASE */
586                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
587                 break;
588         case 100:/* 100BASE */
589                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
590                 break;
591         default:
592                 break;
593         }
594 }
595 
596 /* R8A7778/9 */
597 static struct sh_eth_cpu_data r8a777x_data = {
598         .set_duplex     = sh_eth_set_duplex,
599         .set_rate       = sh_eth_set_rate_r8a777x,
600 
601         .register_type  = SH_ETH_REG_FAST_RCAR,
602 
603         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
604         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
605         .eesipr_value   = 0x01ff009f,
606 
607         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
608         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
609                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
610                           EESR_ECI,
611         .fdr_value      = 0x00000f0f,
612 
613         .apr            = 1,
614         .mpr            = 1,
615         .tpauser        = 1,
616         .hw_swap        = 1,
617 };
618 
619 /* R8A7790/1 */
620 static struct sh_eth_cpu_data r8a779x_data = {
621         .set_duplex     = sh_eth_set_duplex,
622         .set_rate       = sh_eth_set_rate_r8a777x,
623 
624         .register_type  = SH_ETH_REG_FAST_RCAR,
625 
626         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
627         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
628         .eesipr_value   = 0x01ff009f,
629 
630         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
631         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
632                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
633                           EESR_ECI,
634         .fdr_value      = 0x00000f0f,
635 
636         .trscer_err_mask = DESC_I_RINT8,
637 
638         .apr            = 1,
639         .mpr            = 1,
640         .tpauser        = 1,
641         .hw_swap        = 1,
642         .rmiimode       = 1,
643 };
644 #endif /* CONFIG_OF */
645 
646 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
647 {
648         struct sh_eth_private *mdp = netdev_priv(ndev);
649 
650         switch (mdp->speed) {
651         case 10: /* 10BASE */
652                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
653                 break;
654         case 100:/* 100BASE */
655                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
656                 break;
657         default:
658                 break;
659         }
660 }
661 
662 /* SH7724 */
663 static struct sh_eth_cpu_data sh7724_data = {
664         .set_duplex     = sh_eth_set_duplex,
665         .set_rate       = sh_eth_set_rate_sh7724,
666 
667         .register_type  = SH_ETH_REG_FAST_SH4,
668 
669         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
670         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
671         .eesipr_value   = 0x01ff009f,
672 
673         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
674         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
675                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
676                           EESR_ECI,
677 
678         .apr            = 1,
679         .mpr            = 1,
680         .tpauser        = 1,
681         .hw_swap        = 1,
682         .rpadir         = 1,
683         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
684 };
685 
686 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
687 {
688         struct sh_eth_private *mdp = netdev_priv(ndev);
689 
690         switch (mdp->speed) {
691         case 10: /* 10BASE */
692                 sh_eth_write(ndev, 0, RTRATE);
693                 break;
694         case 100:/* 100BASE */
695                 sh_eth_write(ndev, 1, RTRATE);
696                 break;
697         default:
698                 break;
699         }
700 }
701 
702 /* SH7757 */
703 static struct sh_eth_cpu_data sh7757_data = {
704         .set_duplex     = sh_eth_set_duplex,
705         .set_rate       = sh_eth_set_rate_sh7757,
706 
707         .register_type  = SH_ETH_REG_FAST_SH4,
708 
709         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
710 
711         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
712         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
713                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
714                           EESR_ECI,
715 
716         .irq_flags      = IRQF_SHARED,
717         .apr            = 1,
718         .mpr            = 1,
719         .tpauser        = 1,
720         .hw_swap        = 1,
721         .no_ade         = 1,
722         .rpadir         = 1,
723         .rpadir_value   = 2 << 16,
724         .rtrate         = 1,
725 };
726 
727 #define SH_GIGA_ETH_BASE        0xfee00000UL
728 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
729 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
730 static void sh_eth_chip_reset_giga(struct net_device *ndev)
731 {
732         int i;
733         u32 mahr[2], malr[2];
734 
735         /* save MAHR and MALR */
736         for (i = 0; i < 2; i++) {
737                 malr[i] = ioread32((void *)GIGA_MALR(i));
738                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
739         }
740 
741         /* reset device */
742         iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
743         mdelay(1);
744 
745         /* restore MAHR and MALR */
746         for (i = 0; i < 2; i++) {
747                 iowrite32(malr[i], (void *)GIGA_MALR(i));
748                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
749         }
750 }
751 
752 static void sh_eth_set_rate_giga(struct net_device *ndev)
753 {
754         struct sh_eth_private *mdp = netdev_priv(ndev);
755 
756         switch (mdp->speed) {
757         case 10: /* 10BASE */
758                 sh_eth_write(ndev, 0x00000000, GECMR);
759                 break;
760         case 100:/* 100BASE */
761                 sh_eth_write(ndev, 0x00000010, GECMR);
762                 break;
763         case 1000: /* 1000BASE */
764                 sh_eth_write(ndev, 0x00000020, GECMR);
765                 break;
766         default:
767                 break;
768         }
769 }
770 
771 /* SH7757(GETHERC) */
772 static struct sh_eth_cpu_data sh7757_data_giga = {
773         .chip_reset     = sh_eth_chip_reset_giga,
774         .set_duplex     = sh_eth_set_duplex,
775         .set_rate       = sh_eth_set_rate_giga,
776 
777         .register_type  = SH_ETH_REG_GIGABIT,
778 
779         .ecsr_value     = ECSR_ICD | ECSR_MPD,
780         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
781         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
782 
783         .tx_check       = EESR_TC1 | EESR_FTC,
784         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
785                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
786                           EESR_TDE | EESR_ECI,
787         .fdr_value      = 0x0000072f,
788 
789         .irq_flags      = IRQF_SHARED,
790         .apr            = 1,
791         .mpr            = 1,
792         .tpauser        = 1,
793         .bculr          = 1,
794         .hw_swap        = 1,
795         .rpadir         = 1,
796         .rpadir_value   = 2 << 16,
797         .no_trimd       = 1,
798         .no_ade         = 1,
799         .tsu            = 1,
800 };
801 
802 /* SH7734 */
803 static struct sh_eth_cpu_data sh7734_data = {
804         .chip_reset     = sh_eth_chip_reset,
805         .set_duplex     = sh_eth_set_duplex,
806         .set_rate       = sh_eth_set_rate_gether,
807 
808         .register_type  = SH_ETH_REG_GIGABIT,
809 
810         .ecsr_value     = ECSR_ICD | ECSR_MPD,
811         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
812         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
813 
814         .tx_check       = EESR_TC1 | EESR_FTC,
815         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
816                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
817                           EESR_TDE | EESR_ECI,
818 
819         .apr            = 1,
820         .mpr            = 1,
821         .tpauser        = 1,
822         .bculr          = 1,
823         .hw_swap        = 1,
824         .no_trimd       = 1,
825         .no_ade         = 1,
826         .tsu            = 1,
827         .hw_crc         = 1,
828         .select_mii     = 1,
829 };
830 
831 /* SH7763 */
832 static struct sh_eth_cpu_data sh7763_data = {
833         .chip_reset     = sh_eth_chip_reset,
834         .set_duplex     = sh_eth_set_duplex,
835         .set_rate       = sh_eth_set_rate_gether,
836 
837         .register_type  = SH_ETH_REG_GIGABIT,
838 
839         .ecsr_value     = ECSR_ICD | ECSR_MPD,
840         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
841         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
842 
843         .tx_check       = EESR_TC1 | EESR_FTC,
844         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
845                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
846                           EESR_ECI,
847 
848         .apr            = 1,
849         .mpr            = 1,
850         .tpauser        = 1,
851         .bculr          = 1,
852         .hw_swap        = 1,
853         .no_trimd       = 1,
854         .no_ade         = 1,
855         .tsu            = 1,
856         .irq_flags      = IRQF_SHARED,
857 };
858 
859 static struct sh_eth_cpu_data sh7619_data = {
860         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
861 
862         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
863 
864         .apr            = 1,
865         .mpr            = 1,
866         .tpauser        = 1,
867         .hw_swap        = 1,
868 };
869 
870 static struct sh_eth_cpu_data sh771x_data = {
871         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
872 
873         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
874         .tsu            = 1,
875 };
876 
877 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
878 {
879         if (!cd->ecsr_value)
880                 cd->ecsr_value = DEFAULT_ECSR_INIT;
881 
882         if (!cd->ecsipr_value)
883                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
884 
885         if (!cd->fcftr_value)
886                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
887                                   DEFAULT_FIFO_F_D_RFD;
888 
889         if (!cd->fdr_value)
890                 cd->fdr_value = DEFAULT_FDR_INIT;
891 
892         if (!cd->tx_check)
893                 cd->tx_check = DEFAULT_TX_CHECK;
894 
895         if (!cd->eesr_err_check)
896                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
897 
898         if (!cd->trscer_err_mask)
899                 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
900 }
901 
902 static int sh_eth_check_reset(struct net_device *ndev)
903 {
904         int ret = 0;
905         int cnt = 100;
906 
907         while (cnt > 0) {
908                 if (!(sh_eth_read(ndev, EDMR) & 0x3))
909                         break;
910                 mdelay(1);
911                 cnt--;
912         }
913         if (cnt <= 0) {
914                 netdev_err(ndev, "Device reset failed\n");
915                 ret = -ETIMEDOUT;
916         }
917         return ret;
918 }
919 
920 static int sh_eth_reset(struct net_device *ndev)
921 {
922         struct sh_eth_private *mdp = netdev_priv(ndev);
923         int ret = 0;
924 
925         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
926                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
927                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
928                              EDMR);
929 
930                 ret = sh_eth_check_reset(ndev);
931                 if (ret)
932                         return ret;
933 
934                 /* Table Init */
935                 sh_eth_write(ndev, 0x0, TDLAR);
936                 sh_eth_write(ndev, 0x0, TDFAR);
937                 sh_eth_write(ndev, 0x0, TDFXR);
938                 sh_eth_write(ndev, 0x0, TDFFR);
939                 sh_eth_write(ndev, 0x0, RDLAR);
940                 sh_eth_write(ndev, 0x0, RDFAR);
941                 sh_eth_write(ndev, 0x0, RDFXR);
942                 sh_eth_write(ndev, 0x0, RDFFR);
943 
944                 /* Reset HW CRC register */
945                 if (mdp->cd->hw_crc)
946                         sh_eth_write(ndev, 0x0, CSMR);
947 
948                 /* Select MII mode */
949                 if (mdp->cd->select_mii)
950                         sh_eth_select_mii(ndev);
951         } else {
952                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
953                              EDMR);
954                 mdelay(3);
955                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
956                              EDMR);
957         }
958 
959         return ret;
960 }
961 
962 static void sh_eth_set_receive_align(struct sk_buff *skb)
963 {
964         uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
965 
966         if (reserve)
967                 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
968 }
969 
970 /* Program the hardware MAC address from dev->dev_addr. */
971 static void update_mac_address(struct net_device *ndev)
972 {
973         sh_eth_write(ndev,
974                      (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
975                      (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
976         sh_eth_write(ndev,
977                      (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
978 }
979 
980 /* Get MAC address from SuperH MAC address register
981  *
982  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
983  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
984  * When you want use this device, you must set MAC address in bootloader.
985  *
986  */
987 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
988 {
989         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
990                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
991         } else {
992                 u32 mahr = sh_eth_read(ndev, MAHR);
993                 u32 malr = sh_eth_read(ndev, MALR);
994 
995                 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
996                 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
997                 ndev->dev_addr[2] = (mahr >>  8) & 0xFF;
998                 ndev->dev_addr[3] = (mahr >>  0) & 0xFF;
999                 ndev->dev_addr[4] = (malr >>  8) & 0xFF;
1000                 ndev->dev_addr[5] = (malr >>  0) & 0xFF;
1001         }
1002 }
1003 
1004 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
1005 {
1006         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
1007                 return EDTRR_TRNS_GETHER;
1008         else
1009                 return EDTRR_TRNS_ETHER;
1010 }
1011 
1012 struct bb_info {
1013         void (*set_gate)(void *addr);
1014         struct mdiobb_ctrl ctrl;
1015         void *addr;
1016 };
1017 
1018 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1019 {
1020         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1021         u32 pir;
1022 
1023         if (bitbang->set_gate)
1024                 bitbang->set_gate(bitbang->addr);
1025 
1026         pir = ioread32(bitbang->addr);
1027         if (set)
1028                 pir |=  mask;
1029         else
1030                 pir &= ~mask;
1031         iowrite32(pir, bitbang->addr);
1032 }
1033 
1034 /* Data I/O pin control */
1035 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1036 {
1037         sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1038 }
1039 
1040 /* Set bit data*/
1041 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1042 {
1043         sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1044 }
1045 
1046 /* Get bit data*/
1047 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1048 {
1049         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1050 
1051         if (bitbang->set_gate)
1052                 bitbang->set_gate(bitbang->addr);
1053 
1054         return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1055 }
1056 
1057 /* MDC pin control */
1058 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1059 {
1060         sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1061 }
1062 
1063 /* mdio bus control struct */
1064 static struct mdiobb_ops bb_ops = {
1065         .owner = THIS_MODULE,
1066         .set_mdc = sh_mdc_ctrl,
1067         .set_mdio_dir = sh_mmd_ctrl,
1068         .set_mdio_data = sh_set_mdio,
1069         .get_mdio_data = sh_get_mdio,
1070 };
1071 
1072 /* free skb and descriptor buffer */
1073 static void sh_eth_ring_free(struct net_device *ndev)
1074 {
1075         struct sh_eth_private *mdp = netdev_priv(ndev);
1076         int ringsize, i;
1077 
1078         /* Free Rx skb ringbuffer */
1079         if (mdp->rx_skbuff) {
1080                 for (i = 0; i < mdp->num_rx_ring; i++)
1081                         dev_kfree_skb(mdp->rx_skbuff[i]);
1082         }
1083         kfree(mdp->rx_skbuff);
1084         mdp->rx_skbuff = NULL;
1085 
1086         /* Free Tx skb ringbuffer */
1087         if (mdp->tx_skbuff) {
1088                 for (i = 0; i < mdp->num_tx_ring; i++)
1089                         dev_kfree_skb(mdp->tx_skbuff[i]);
1090         }
1091         kfree(mdp->tx_skbuff);
1092         mdp->tx_skbuff = NULL;
1093 
1094         if (mdp->rx_ring) {
1095                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1096                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1097                                   mdp->rx_desc_dma);
1098                 mdp->rx_ring = NULL;
1099         }
1100 
1101         if (mdp->tx_ring) {
1102                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1103                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1104                                   mdp->tx_desc_dma);
1105                 mdp->tx_ring = NULL;
1106         }
1107 }
1108 
1109 /* format skb and descriptor buffer */
1110 static void sh_eth_ring_format(struct net_device *ndev)
1111 {
1112         struct sh_eth_private *mdp = netdev_priv(ndev);
1113         int i;
1114         struct sk_buff *skb;
1115         struct sh_eth_rxdesc *rxdesc = NULL;
1116         struct sh_eth_txdesc *txdesc = NULL;
1117         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1118         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1119         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1120         dma_addr_t dma_addr;
1121         u32 buf_len;
1122 
1123         mdp->cur_rx = 0;
1124         mdp->cur_tx = 0;
1125         mdp->dirty_rx = 0;
1126         mdp->dirty_tx = 0;
1127 
1128         memset(mdp->rx_ring, 0, rx_ringsize);
1129 
1130         /* build Rx ring buffer */
1131         for (i = 0; i < mdp->num_rx_ring; i++) {
1132                 /* skb */
1133                 mdp->rx_skbuff[i] = NULL;
1134                 skb = netdev_alloc_skb(ndev, skbuff_size);
1135                 if (skb == NULL)
1136                         break;
1137                 sh_eth_set_receive_align(skb);
1138 
1139                 /* RX descriptor */
1140                 rxdesc = &mdp->rx_ring[i];
1141                 /* The size of the buffer is a multiple of 32 bytes. */
1142                 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1143                 rxdesc->len = cpu_to_le32(buf_len << 16);
1144                 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
1145                                           DMA_FROM_DEVICE);
1146                 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1147                         kfree_skb(skb);
1148                         break;
1149                 }
1150                 mdp->rx_skbuff[i] = skb;
1151                 rxdesc->addr = cpu_to_le32(dma_addr);
1152                 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1153 
1154                 /* Rx descriptor address set */
1155                 if (i == 0) {
1156                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1157                         if (sh_eth_is_gether(mdp) ||
1158                             sh_eth_is_rz_fast_ether(mdp))
1159                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1160                 }
1161         }
1162 
1163         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1164 
1165         /* Mark the last entry as wrapping the ring. */
1166         rxdesc->status |= cpu_to_le32(RD_RDLE);
1167 
1168         memset(mdp->tx_ring, 0, tx_ringsize);
1169 
1170         /* build Tx ring buffer */
1171         for (i = 0; i < mdp->num_tx_ring; i++) {
1172                 mdp->tx_skbuff[i] = NULL;
1173                 txdesc = &mdp->tx_ring[i];
1174                 txdesc->status = cpu_to_le32(TD_TFP);
1175                 txdesc->len = cpu_to_le32(0);
1176                 if (i == 0) {
1177                         /* Tx descriptor address set */
1178                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1179                         if (sh_eth_is_gether(mdp) ||
1180                             sh_eth_is_rz_fast_ether(mdp))
1181                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1182                 }
1183         }
1184 
1185         txdesc->status |= cpu_to_le32(TD_TDLE);
1186 }
1187 
1188 /* Get skb and descriptor buffer */
1189 static int sh_eth_ring_init(struct net_device *ndev)
1190 {
1191         struct sh_eth_private *mdp = netdev_priv(ndev);
1192         int rx_ringsize, tx_ringsize;
1193 
1194         /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1195          * card needs room to do 8 byte alignment, +2 so we can reserve
1196          * the first 2 bytes, and +16 gets room for the status word from the
1197          * card.
1198          */
1199         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1200                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1201         if (mdp->cd->rpadir)
1202                 mdp->rx_buf_sz += NET_IP_ALIGN;
1203 
1204         /* Allocate RX and TX skb rings */
1205         mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1206                                  GFP_KERNEL);
1207         if (!mdp->rx_skbuff)
1208                 return -ENOMEM;
1209 
1210         mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1211                                  GFP_KERNEL);
1212         if (!mdp->tx_skbuff)
1213                 goto ring_free;
1214 
1215         /* Allocate all Rx descriptors. */
1216         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1217         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1218                                           GFP_KERNEL);
1219         if (!mdp->rx_ring)
1220                 goto ring_free;
1221 
1222         mdp->dirty_rx = 0;
1223 
1224         /* Allocate all Tx descriptors. */
1225         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1226         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1227                                           GFP_KERNEL);
1228         if (!mdp->tx_ring)
1229                 goto ring_free;
1230         return 0;
1231 
1232 ring_free:
1233         /* Free Rx and Tx skb ring buffer and DMA buffer */
1234         sh_eth_ring_free(ndev);
1235 
1236         return -ENOMEM;
1237 }
1238 
1239 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1240 {
1241         int ret = 0;
1242         struct sh_eth_private *mdp = netdev_priv(ndev);
1243 
1244         /* Soft Reset */
1245         ret = sh_eth_reset(ndev);
1246         if (ret)
1247                 return ret;
1248 
1249         if (mdp->cd->rmiimode)
1250                 sh_eth_write(ndev, 0x1, RMIIMODE);
1251 
1252         /* Descriptor format */
1253         sh_eth_ring_format(ndev);
1254         if (mdp->cd->rpadir)
1255                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1256 
1257         /* all sh_eth int mask */
1258         sh_eth_write(ndev, 0, EESIPR);
1259 
1260 #if defined(__LITTLE_ENDIAN)
1261         if (mdp->cd->hw_swap)
1262                 sh_eth_write(ndev, EDMR_EL, EDMR);
1263         else
1264 #endif
1265                 sh_eth_write(ndev, 0, EDMR);
1266 
1267         /* FIFO size set */
1268         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1269         sh_eth_write(ndev, 0, TFTR);
1270 
1271         /* Frame recv control (enable multiple-packets per rx irq) */
1272         sh_eth_write(ndev, RMCR_RNC, RMCR);
1273 
1274         sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1275 
1276         if (mdp->cd->bculr)
1277                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1278 
1279         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1280 
1281         if (!mdp->cd->no_trimd)
1282                 sh_eth_write(ndev, 0, TRIMD);
1283 
1284         /* Recv frame limit set register */
1285         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1286                      RFLR);
1287 
1288         sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1289         if (start) {
1290                 mdp->irq_enabled = true;
1291                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1292         }
1293 
1294         /* PAUSE Prohibition */
1295         sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1296                      ECMR_TE | ECMR_RE, ECMR);
1297 
1298         if (mdp->cd->set_rate)
1299                 mdp->cd->set_rate(ndev);
1300 
1301         /* E-MAC Status Register clear */
1302         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1303 
1304         /* E-MAC Interrupt Enable register */
1305         if (start)
1306                 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1307 
1308         /* Set MAC address */
1309         update_mac_address(ndev);
1310 
1311         /* mask reset */
1312         if (mdp->cd->apr)
1313                 sh_eth_write(ndev, APR_AP, APR);
1314         if (mdp->cd->mpr)
1315                 sh_eth_write(ndev, MPR_MP, MPR);
1316         if (mdp->cd->tpauser)
1317                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1318 
1319         if (start) {
1320                 /* Setting the Rx mode will start the Rx process. */
1321                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1322 
1323                 netif_start_queue(ndev);
1324         }
1325 
1326         return ret;
1327 }
1328 
1329 static void sh_eth_dev_exit(struct net_device *ndev)
1330 {
1331         struct sh_eth_private *mdp = netdev_priv(ndev);
1332         int i;
1333 
1334         /* Deactivate all TX descriptors, so DMA should stop at next
1335          * packet boundary if it's currently running
1336          */
1337         for (i = 0; i < mdp->num_tx_ring; i++)
1338                 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1339 
1340         /* Disable TX FIFO egress to MAC */
1341         sh_eth_rcv_snd_disable(ndev);
1342 
1343         /* Stop RX DMA at next packet boundary */
1344         sh_eth_write(ndev, 0, EDRRR);
1345 
1346         /* Aside from TX DMA, we can't tell when the hardware is
1347          * really stopped, so we need to reset to make sure.
1348          * Before doing that, wait for long enough to *probably*
1349          * finish transmitting the last packet and poll stats.
1350          */
1351         msleep(2); /* max frame time at 10 Mbps < 1250 us */
1352         sh_eth_get_stats(ndev);
1353         sh_eth_reset(ndev);
1354 
1355         /* Set MAC address again */
1356         update_mac_address(ndev);
1357 }
1358 
1359 /* free Tx skb function */
1360 static int sh_eth_txfree(struct net_device *ndev)
1361 {
1362         struct sh_eth_private *mdp = netdev_priv(ndev);
1363         struct sh_eth_txdesc *txdesc;
1364         int free_num = 0;
1365         int entry = 0;
1366 
1367         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1368                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1369                 txdesc = &mdp->tx_ring[entry];
1370                 if (txdesc->status & cpu_to_le32(TD_TACT))
1371                         break;
1372                 /* TACT bit must be checked before all the following reads */
1373                 dma_rmb();
1374                 netif_info(mdp, tx_done, ndev,
1375                            "tx entry %d status 0x%08x\n",
1376                            entry, le32_to_cpu(txdesc->status));
1377                 /* Free the original skb. */
1378                 if (mdp->tx_skbuff[entry]) {
1379                         dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
1380                                          le32_to_cpu(txdesc->len) >> 16,
1381                                          DMA_TO_DEVICE);
1382                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1383                         mdp->tx_skbuff[entry] = NULL;
1384                         free_num++;
1385                 }
1386                 txdesc->status = cpu_to_le32(TD_TFP);
1387                 if (entry >= mdp->num_tx_ring - 1)
1388                         txdesc->status |= cpu_to_le32(TD_TDLE);
1389 
1390                 ndev->stats.tx_packets++;
1391                 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1392         }
1393         return free_num;
1394 }
1395 
1396 /* Packet receive function */
1397 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1398 {
1399         struct sh_eth_private *mdp = netdev_priv(ndev);
1400         struct sh_eth_rxdesc *rxdesc;
1401 
1402         int entry = mdp->cur_rx % mdp->num_rx_ring;
1403         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1404         int limit;
1405         struct sk_buff *skb;
1406         u16 pkt_len = 0;
1407         u32 desc_status;
1408         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1409         dma_addr_t dma_addr;
1410         u32 buf_len;
1411 
1412         boguscnt = min(boguscnt, *quota);
1413         limit = boguscnt;
1414         rxdesc = &mdp->rx_ring[entry];
1415         while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1416                 /* RACT bit must be checked before all the following reads */
1417                 dma_rmb();
1418                 desc_status = le32_to_cpu(rxdesc->status);
1419                 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1420 
1421                 if (--boguscnt < 0)
1422                         break;
1423 
1424                 netif_info(mdp, rx_status, ndev,
1425                            "rx entry %d status 0x%08x len %d\n",
1426                            entry, desc_status, pkt_len);
1427 
1428                 if (!(desc_status & RDFEND))
1429                         ndev->stats.rx_length_errors++;
1430 
1431                 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1432                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1433                  * bit 0. However, in case of the R8A7740 and R7S72100
1434                  * the RFS bits are from bit 25 to bit 16. So, the
1435                  * driver needs right shifting by 16.
1436                  */
1437                 if (mdp->cd->shift_rd0)
1438                         desc_status >>= 16;
1439 
1440                 skb = mdp->rx_skbuff[entry];
1441                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1442                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1443                         ndev->stats.rx_errors++;
1444                         if (desc_status & RD_RFS1)
1445                                 ndev->stats.rx_crc_errors++;
1446                         if (desc_status & RD_RFS2)
1447                                 ndev->stats.rx_frame_errors++;
1448                         if (desc_status & RD_RFS3)
1449                                 ndev->stats.rx_length_errors++;
1450                         if (desc_status & RD_RFS4)
1451                                 ndev->stats.rx_length_errors++;
1452                         if (desc_status & RD_RFS6)
1453                                 ndev->stats.rx_missed_errors++;
1454                         if (desc_status & RD_RFS10)
1455                                 ndev->stats.rx_over_errors++;
1456                 } else  if (skb) {
1457                         dma_addr = le32_to_cpu(rxdesc->addr);