Version:  2.0.40 2.2.26 2.4.37 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7

Linux/drivers/net/ethernet/renesas/sh_eth.c

  1 /*  SuperH Ethernet device driver
  2  *
  3  *  Copyright (C) 2014  Renesas Electronics Corporation
  4  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
  5  *  Copyright (C) 2008-2014 Renesas Solutions Corp.
  6  *  Copyright (C) 2013-2016 Cogent Embedded, Inc.
  7  *  Copyright (C) 2014 Codethink Limited
  8  *
  9  *  This program is free software; you can redistribute it and/or modify it
 10  *  under the terms and conditions of the GNU General Public License,
 11  *  version 2, as published by the Free Software Foundation.
 12  *
 13  *  This program is distributed in the hope it will be useful, but WITHOUT
 14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 15  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 16  *  more details.
 17  *
 18  *  The full GNU General Public License is included in this distribution in
 19  *  the file called "COPYING".
 20  */
 21 
 22 #include <linux/module.h>
 23 #include <linux/kernel.h>
 24 #include <linux/spinlock.h>
 25 #include <linux/interrupt.h>
 26 #include <linux/dma-mapping.h>
 27 #include <linux/etherdevice.h>
 28 #include <linux/delay.h>
 29 #include <linux/platform_device.h>
 30 #include <linux/mdio-bitbang.h>
 31 #include <linux/netdevice.h>
 32 #include <linux/of.h>
 33 #include <linux/of_device.h>
 34 #include <linux/of_irq.h>
 35 #include <linux/of_net.h>
 36 #include <linux/phy.h>
 37 #include <linux/cache.h>
 38 #include <linux/io.h>
 39 #include <linux/pm_runtime.h>
 40 #include <linux/slab.h>
 41 #include <linux/ethtool.h>
 42 #include <linux/if_vlan.h>
 43 #include <linux/clk.h>
 44 #include <linux/sh_eth.h>
 45 #include <linux/of_mdio.h>
 46 
 47 #include "sh_eth.h"
 48 
 49 #define SH_ETH_DEF_MSG_ENABLE \
 50                 (NETIF_MSG_LINK | \
 51                 NETIF_MSG_TIMER | \
 52                 NETIF_MSG_RX_ERR| \
 53                 NETIF_MSG_TX_ERR)
 54 
 55 #define SH_ETH_OFFSET_INVALID   ((u16)~0)
 56 
 57 #define SH_ETH_OFFSET_DEFAULTS                  \
 58         [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
 59 
 60 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
 61         SH_ETH_OFFSET_DEFAULTS,
 62 
 63         [EDSR]          = 0x0000,
 64         [EDMR]          = 0x0400,
 65         [EDTRR]         = 0x0408,
 66         [EDRRR]         = 0x0410,
 67         [EESR]          = 0x0428,
 68         [EESIPR]        = 0x0430,
 69         [TDLAR]         = 0x0010,
 70         [TDFAR]         = 0x0014,
 71         [TDFXR]         = 0x0018,
 72         [TDFFR]         = 0x001c,
 73         [RDLAR]         = 0x0030,
 74         [RDFAR]         = 0x0034,
 75         [RDFXR]         = 0x0038,
 76         [RDFFR]         = 0x003c,
 77         [TRSCER]        = 0x0438,
 78         [RMFCR]         = 0x0440,
 79         [TFTR]          = 0x0448,
 80         [FDR]           = 0x0450,
 81         [RMCR]          = 0x0458,
 82         [RPADIR]        = 0x0460,
 83         [FCFTR]         = 0x0468,
 84         [CSMR]          = 0x04E4,
 85 
 86         [ECMR]          = 0x0500,
 87         [ECSR]          = 0x0510,
 88         [ECSIPR]        = 0x0518,
 89         [PIR]           = 0x0520,
 90         [PSR]           = 0x0528,
 91         [PIPR]          = 0x052c,
 92         [RFLR]          = 0x0508,
 93         [APR]           = 0x0554,
 94         [MPR]           = 0x0558,
 95         [PFTCR]         = 0x055c,
 96         [PFRCR]         = 0x0560,
 97         [TPAUSER]       = 0x0564,
 98         [GECMR]         = 0x05b0,
 99         [BCULR]         = 0x05b4,
100         [MAHR]          = 0x05c0,
101         [MALR]          = 0x05c8,
102         [TROCR]         = 0x0700,
103         [CDCR]          = 0x0708,
104         [LCCR]          = 0x0710,
105         [CEFCR]         = 0x0740,
106         [FRECR]         = 0x0748,
107         [TSFRCR]        = 0x0750,
108         [TLFRCR]        = 0x0758,
109         [RFCR]          = 0x0760,
110         [CERCR]         = 0x0768,
111         [CEECR]         = 0x0770,
112         [MAFCR]         = 0x0778,
113         [RMII_MII]      = 0x0790,
114 
115         [ARSTR]         = 0x0000,
116         [TSU_CTRST]     = 0x0004,
117         [TSU_FWEN0]     = 0x0010,
118         [TSU_FWEN1]     = 0x0014,
119         [TSU_FCM]       = 0x0018,
120         [TSU_BSYSL0]    = 0x0020,
121         [TSU_BSYSL1]    = 0x0024,
122         [TSU_PRISL0]    = 0x0028,
123         [TSU_PRISL1]    = 0x002c,
124         [TSU_FWSL0]     = 0x0030,
125         [TSU_FWSL1]     = 0x0034,
126         [TSU_FWSLC]     = 0x0038,
127         [TSU_QTAG0]     = 0x0040,
128         [TSU_QTAG1]     = 0x0044,
129         [TSU_FWSR]      = 0x0050,
130         [TSU_FWINMK]    = 0x0054,
131         [TSU_ADQT0]     = 0x0048,
132         [TSU_ADQT1]     = 0x004c,
133         [TSU_VTAG0]     = 0x0058,
134         [TSU_VTAG1]     = 0x005c,
135         [TSU_ADSBSY]    = 0x0060,
136         [TSU_TEN]       = 0x0064,
137         [TSU_POST1]     = 0x0070,
138         [TSU_POST2]     = 0x0074,
139         [TSU_POST3]     = 0x0078,
140         [TSU_POST4]     = 0x007c,
141         [TSU_ADRH0]     = 0x0100,
142 
143         [TXNLCR0]       = 0x0080,
144         [TXALCR0]       = 0x0084,
145         [RXNLCR0]       = 0x0088,
146         [RXALCR0]       = 0x008c,
147         [FWNLCR0]       = 0x0090,
148         [FWALCR0]       = 0x0094,
149         [TXNLCR1]       = 0x00a0,
150         [TXALCR1]       = 0x00a0,
151         [RXNLCR1]       = 0x00a8,
152         [RXALCR1]       = 0x00ac,
153         [FWNLCR1]       = 0x00b0,
154         [FWALCR1]       = 0x00b4,
155 };
156 
157 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
158         SH_ETH_OFFSET_DEFAULTS,
159 
160         [EDSR]          = 0x0000,
161         [EDMR]          = 0x0400,
162         [EDTRR]         = 0x0408,
163         [EDRRR]         = 0x0410,
164         [EESR]          = 0x0428,
165         [EESIPR]        = 0x0430,
166         [TDLAR]         = 0x0010,
167         [TDFAR]         = 0x0014,
168         [TDFXR]         = 0x0018,
169         [TDFFR]         = 0x001c,
170         [RDLAR]         = 0x0030,
171         [RDFAR]         = 0x0034,
172         [RDFXR]         = 0x0038,
173         [RDFFR]         = 0x003c,
174         [TRSCER]        = 0x0438,
175         [RMFCR]         = 0x0440,
176         [TFTR]          = 0x0448,
177         [FDR]           = 0x0450,
178         [RMCR]          = 0x0458,
179         [RPADIR]        = 0x0460,
180         [FCFTR]         = 0x0468,
181         [CSMR]          = 0x04E4,
182 
183         [ECMR]          = 0x0500,
184         [RFLR]          = 0x0508,
185         [ECSR]          = 0x0510,
186         [ECSIPR]        = 0x0518,
187         [PIR]           = 0x0520,
188         [APR]           = 0x0554,
189         [MPR]           = 0x0558,
190         [PFTCR]         = 0x055c,
191         [PFRCR]         = 0x0560,
192         [TPAUSER]       = 0x0564,
193         [MAHR]          = 0x05c0,
194         [MALR]          = 0x05c8,
195         [CEFCR]         = 0x0740,
196         [FRECR]         = 0x0748,
197         [TSFRCR]        = 0x0750,
198         [TLFRCR]        = 0x0758,
199         [RFCR]          = 0x0760,
200         [MAFCR]         = 0x0778,
201 
202         [ARSTR]         = 0x0000,
203         [TSU_CTRST]     = 0x0004,
204         [TSU_VTAG0]     = 0x0058,
205         [TSU_ADSBSY]    = 0x0060,
206         [TSU_TEN]       = 0x0064,
207         [TSU_ADRH0]     = 0x0100,
208 
209         [TXNLCR0]       = 0x0080,
210         [TXALCR0]       = 0x0084,
211         [RXNLCR0]       = 0x0088,
212         [RXALCR0]       = 0x008C,
213 };
214 
215 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
216         SH_ETH_OFFSET_DEFAULTS,
217 
218         [ECMR]          = 0x0300,
219         [RFLR]          = 0x0308,
220         [ECSR]          = 0x0310,
221         [ECSIPR]        = 0x0318,
222         [PIR]           = 0x0320,
223         [PSR]           = 0x0328,
224         [RDMLR]         = 0x0340,
225         [IPGR]          = 0x0350,
226         [APR]           = 0x0354,
227         [MPR]           = 0x0358,
228         [RFCF]          = 0x0360,
229         [TPAUSER]       = 0x0364,
230         [TPAUSECR]      = 0x0368,
231         [MAHR]          = 0x03c0,
232         [MALR]          = 0x03c8,
233         [TROCR]         = 0x03d0,
234         [CDCR]          = 0x03d4,
235         [LCCR]          = 0x03d8,
236         [CNDCR]         = 0x03dc,
237         [CEFCR]         = 0x03e4,
238         [FRECR]         = 0x03e8,
239         [TSFRCR]        = 0x03ec,
240         [TLFRCR]        = 0x03f0,
241         [RFCR]          = 0x03f4,
242         [MAFCR]         = 0x03f8,
243 
244         [EDMR]          = 0x0200,
245         [EDTRR]         = 0x0208,
246         [EDRRR]         = 0x0210,
247         [TDLAR]         = 0x0218,
248         [RDLAR]         = 0x0220,
249         [EESR]          = 0x0228,
250         [EESIPR]        = 0x0230,
251         [TRSCER]        = 0x0238,
252         [RMFCR]         = 0x0240,
253         [TFTR]          = 0x0248,
254         [FDR]           = 0x0250,
255         [RMCR]          = 0x0258,
256         [TFUCR]         = 0x0264,
257         [RFOCR]         = 0x0268,
258         [RMIIMODE]      = 0x026c,
259         [FCFTR]         = 0x0270,
260         [TRIMD]         = 0x027c,
261 };
262 
263 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
264         SH_ETH_OFFSET_DEFAULTS,
265 
266         [ECMR]          = 0x0100,
267         [RFLR]          = 0x0108,
268         [ECSR]          = 0x0110,
269         [ECSIPR]        = 0x0118,
270         [PIR]           = 0x0120,
271         [PSR]           = 0x0128,
272         [RDMLR]         = 0x0140,
273         [IPGR]          = 0x0150,
274         [APR]           = 0x0154,
275         [MPR]           = 0x0158,
276         [TPAUSER]       = 0x0164,
277         [RFCF]          = 0x0160,
278         [TPAUSECR]      = 0x0168,
279         [BCFRR]         = 0x016c,
280         [MAHR]          = 0x01c0,
281         [MALR]          = 0x01c8,
282         [TROCR]         = 0x01d0,
283         [CDCR]          = 0x01d4,
284         [LCCR]          = 0x01d8,
285         [CNDCR]         = 0x01dc,
286         [CEFCR]         = 0x01e4,
287         [FRECR]         = 0x01e8,
288         [TSFRCR]        = 0x01ec,
289         [TLFRCR]        = 0x01f0,
290         [RFCR]          = 0x01f4,
291         [MAFCR]         = 0x01f8,
292         [RTRATE]        = 0x01fc,
293 
294         [EDMR]          = 0x0000,
295         [EDTRR]         = 0x0008,
296         [EDRRR]         = 0x0010,
297         [TDLAR]         = 0x0018,
298         [RDLAR]         = 0x0020,
299         [EESR]          = 0x0028,
300         [EESIPR]        = 0x0030,
301         [TRSCER]        = 0x0038,
302         [RMFCR]         = 0x0040,
303         [TFTR]          = 0x0048,
304         [FDR]           = 0x0050,
305         [RMCR]          = 0x0058,
306         [TFUCR]         = 0x0064,
307         [RFOCR]         = 0x0068,
308         [FCFTR]         = 0x0070,
309         [RPADIR]        = 0x0078,
310         [TRIMD]         = 0x007c,
311         [RBWAR]         = 0x00c8,
312         [RDFAR]         = 0x00cc,
313         [TBRAR]         = 0x00d4,
314         [TDFAR]         = 0x00d8,
315 };
316 
317 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
318         SH_ETH_OFFSET_DEFAULTS,
319 
320         [EDMR]          = 0x0000,
321         [EDTRR]         = 0x0004,
322         [EDRRR]         = 0x0008,
323         [TDLAR]         = 0x000c,
324         [RDLAR]         = 0x0010,
325         [EESR]          = 0x0014,
326         [EESIPR]        = 0x0018,
327         [TRSCER]        = 0x001c,
328         [RMFCR]         = 0x0020,
329         [TFTR]          = 0x0024,
330         [FDR]           = 0x0028,
331         [RMCR]          = 0x002c,
332         [EDOCR]         = 0x0030,
333         [FCFTR]         = 0x0034,
334         [RPADIR]        = 0x0038,
335         [TRIMD]         = 0x003c,
336         [RBWAR]         = 0x0040,
337         [RDFAR]         = 0x0044,
338         [TBRAR]         = 0x004c,
339         [TDFAR]         = 0x0050,
340 
341         [ECMR]          = 0x0160,
342         [ECSR]          = 0x0164,
343         [ECSIPR]        = 0x0168,
344         [PIR]           = 0x016c,
345         [MAHR]          = 0x0170,
346         [MALR]          = 0x0174,
347         [RFLR]          = 0x0178,
348         [PSR]           = 0x017c,
349         [TROCR]         = 0x0180,
350         [CDCR]          = 0x0184,
351         [LCCR]          = 0x0188,
352         [CNDCR]         = 0x018c,
353         [CEFCR]         = 0x0194,
354         [FRECR]         = 0x0198,
355         [TSFRCR]        = 0x019c,
356         [TLFRCR]        = 0x01a0,
357         [RFCR]          = 0x01a4,
358         [MAFCR]         = 0x01a8,
359         [IPGR]          = 0x01b4,
360         [APR]           = 0x01b8,
361         [MPR]           = 0x01bc,
362         [TPAUSER]       = 0x01c4,
363         [BCFR]          = 0x01cc,
364 
365         [ARSTR]         = 0x0000,
366         [TSU_CTRST]     = 0x0004,
367         [TSU_FWEN0]     = 0x0010,
368         [TSU_FWEN1]     = 0x0014,
369         [TSU_FCM]       = 0x0018,
370         [TSU_BSYSL0]    = 0x0020,
371         [TSU_BSYSL1]    = 0x0024,
372         [TSU_PRISL0]    = 0x0028,
373         [TSU_PRISL1]    = 0x002c,
374         [TSU_FWSL0]     = 0x0030,
375         [TSU_FWSL1]     = 0x0034,
376         [TSU_FWSLC]     = 0x0038,
377         [TSU_QTAGM0]    = 0x0040,
378         [TSU_QTAGM1]    = 0x0044,
379         [TSU_ADQT0]     = 0x0048,
380         [TSU_ADQT1]     = 0x004c,
381         [TSU_FWSR]      = 0x0050,
382         [TSU_FWINMK]    = 0x0054,
383         [TSU_ADSBSY]    = 0x0060,
384         [TSU_TEN]       = 0x0064,
385         [TSU_POST1]     = 0x0070,
386         [TSU_POST2]     = 0x0074,
387         [TSU_POST3]     = 0x0078,
388         [TSU_POST4]     = 0x007c,
389 
390         [TXNLCR0]       = 0x0080,
391         [TXALCR0]       = 0x0084,
392         [RXNLCR0]       = 0x0088,
393         [RXALCR0]       = 0x008c,
394         [FWNLCR0]       = 0x0090,
395         [FWALCR0]       = 0x0094,
396         [TXNLCR1]       = 0x00a0,
397         [TXALCR1]       = 0x00a0,
398         [RXNLCR1]       = 0x00a8,
399         [RXALCR1]       = 0x00ac,
400         [FWNLCR1]       = 0x00b0,
401         [FWALCR1]       = 0x00b4,
402 
403         [TSU_ADRH0]     = 0x0100,
404 };
405 
406 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
407 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
408 
409 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
410 {
411         struct sh_eth_private *mdp = netdev_priv(ndev);
412         u16 offset = mdp->reg_offset[enum_index];
413 
414         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
415                 return;
416 
417         iowrite32(data, mdp->addr + offset);
418 }
419 
420 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
421 {
422         struct sh_eth_private *mdp = netdev_priv(ndev);
423         u16 offset = mdp->reg_offset[enum_index];
424 
425         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
426                 return ~0U;
427 
428         return ioread32(mdp->addr + offset);
429 }
430 
431 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
432                           u32 set)
433 {
434         sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
435                      enum_index);
436 }
437 
438 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
439 {
440         return mdp->reg_offset == sh_eth_offset_gigabit;
441 }
442 
443 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
444 {
445         return mdp->reg_offset == sh_eth_offset_fast_rz;
446 }
447 
448 static void sh_eth_select_mii(struct net_device *ndev)
449 {
450         struct sh_eth_private *mdp = netdev_priv(ndev);
451         u32 value;
452 
453         switch (mdp->phy_interface) {
454         case PHY_INTERFACE_MODE_GMII:
455                 value = 0x2;
456                 break;
457         case PHY_INTERFACE_MODE_MII:
458                 value = 0x1;
459                 break;
460         case PHY_INTERFACE_MODE_RMII:
461                 value = 0x0;
462                 break;
463         default:
464                 netdev_warn(ndev,
465                             "PHY interface mode was not setup. Set to MII.\n");
466                 value = 0x1;
467                 break;
468         }
469 
470         sh_eth_write(ndev, value, RMII_MII);
471 }
472 
473 static void sh_eth_set_duplex(struct net_device *ndev)
474 {
475         struct sh_eth_private *mdp = netdev_priv(ndev);
476 
477         sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
478 }
479 
480 static void sh_eth_chip_reset(struct net_device *ndev)
481 {
482         struct sh_eth_private *mdp = netdev_priv(ndev);
483 
484         /* reset device */
485         sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
486         mdelay(1);
487 }
488 
489 static void sh_eth_set_rate_gether(struct net_device *ndev)
490 {
491         struct sh_eth_private *mdp = netdev_priv(ndev);
492 
493         switch (mdp->speed) {
494         case 10: /* 10BASE */
495                 sh_eth_write(ndev, GECMR_10, GECMR);
496                 break;
497         case 100:/* 100BASE */
498                 sh_eth_write(ndev, GECMR_100, GECMR);
499                 break;
500         case 1000: /* 1000BASE */
501                 sh_eth_write(ndev, GECMR_1000, GECMR);
502                 break;
503         }
504 }
505 
506 #ifdef CONFIG_OF
507 /* R7S72100 */
508 static struct sh_eth_cpu_data r7s72100_data = {
509         .chip_reset     = sh_eth_chip_reset,
510         .set_duplex     = sh_eth_set_duplex,
511 
512         .register_type  = SH_ETH_REG_FAST_RZ,
513 
514         .ecsr_value     = ECSR_ICD,
515         .ecsipr_value   = ECSIPR_ICDIP,
516         .eesipr_value   = 0xff7f009f,
517 
518         .tx_check       = EESR_TC1 | EESR_FTC,
519         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
520                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
521                           EESR_TDE | EESR_ECI,
522         .fdr_value      = 0x0000070f,
523 
524         .no_psr         = 1,
525         .apr            = 1,
526         .mpr            = 1,
527         .tpauser        = 1,
528         .hw_swap        = 1,
529         .rpadir         = 1,
530         .rpadir_value   = 2 << 16,
531         .no_trimd       = 1,
532         .no_ade         = 1,
533         .hw_crc         = 1,
534         .tsu            = 1,
535         .shift_rd0      = 1,
536 };
537 
538 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
539 {
540         sh_eth_chip_reset(ndev);
541 
542         sh_eth_select_mii(ndev);
543 }
544 
545 /* R8A7740 */
546 static struct sh_eth_cpu_data r8a7740_data = {
547         .chip_reset     = sh_eth_chip_reset_r8a7740,
548         .set_duplex     = sh_eth_set_duplex,
549         .set_rate       = sh_eth_set_rate_gether,
550 
551         .register_type  = SH_ETH_REG_GIGABIT,
552 
553         .ecsr_value     = ECSR_ICD | ECSR_MPD,
554         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
555         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
556 
557         .tx_check       = EESR_TC1 | EESR_FTC,
558         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
559                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
560                           EESR_TDE | EESR_ECI,
561         .fdr_value      = 0x0000070f,
562 
563         .apr            = 1,
564         .mpr            = 1,
565         .tpauser        = 1,
566         .bculr          = 1,
567         .hw_swap        = 1,
568         .rpadir         = 1,
569         .rpadir_value   = 2 << 16,
570         .no_trimd       = 1,
571         .no_ade         = 1,
572         .tsu            = 1,
573         .select_mii     = 1,
574         .shift_rd0      = 1,
575 };
576 
577 /* There is CPU dependent code */
578 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
579 {
580         struct sh_eth_private *mdp = netdev_priv(ndev);
581 
582         switch (mdp->speed) {
583         case 10: /* 10BASE */
584                 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
585                 break;
586         case 100:/* 100BASE */
587                 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
588                 break;
589         }
590 }
591 
592 /* R8A7778/9 */
593 static struct sh_eth_cpu_data r8a777x_data = {
594         .set_duplex     = sh_eth_set_duplex,
595         .set_rate       = sh_eth_set_rate_r8a777x,
596 
597         .register_type  = SH_ETH_REG_FAST_RCAR,
598 
599         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
600         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
601         .eesipr_value   = 0x01ff009f,
602 
603         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
604         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
605                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
606                           EESR_ECI,
607         .fdr_value      = 0x00000f0f,
608 
609         .apr            = 1,
610         .mpr            = 1,
611         .tpauser        = 1,
612         .hw_swap        = 1,
613 };
614 
615 /* R8A7790/1 */
616 static struct sh_eth_cpu_data r8a779x_data = {
617         .set_duplex     = sh_eth_set_duplex,
618         .set_rate       = sh_eth_set_rate_r8a777x,
619 
620         .register_type  = SH_ETH_REG_FAST_RCAR,
621 
622         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
623         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
624         .eesipr_value   = 0x01ff009f,
625 
626         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
627         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
628                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
629                           EESR_ECI,
630         .fdr_value      = 0x00000f0f,
631 
632         .trscer_err_mask = DESC_I_RINT8,
633 
634         .apr            = 1,
635         .mpr            = 1,
636         .tpauser        = 1,
637         .hw_swap        = 1,
638         .rmiimode       = 1,
639 };
640 #endif /* CONFIG_OF */
641 
642 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
643 {
644         struct sh_eth_private *mdp = netdev_priv(ndev);
645 
646         switch (mdp->speed) {
647         case 10: /* 10BASE */
648                 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
649                 break;
650         case 100:/* 100BASE */
651                 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
652                 break;
653         }
654 }
655 
656 /* SH7724 */
657 static struct sh_eth_cpu_data sh7724_data = {
658         .set_duplex     = sh_eth_set_duplex,
659         .set_rate       = sh_eth_set_rate_sh7724,
660 
661         .register_type  = SH_ETH_REG_FAST_SH4,
662 
663         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
664         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
665         .eesipr_value   = 0x01ff009f,
666 
667         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
668         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
669                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
670                           EESR_ECI,
671 
672         .apr            = 1,
673         .mpr            = 1,
674         .tpauser        = 1,
675         .hw_swap        = 1,
676         .rpadir         = 1,
677         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
678 };
679 
680 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
681 {
682         struct sh_eth_private *mdp = netdev_priv(ndev);
683 
684         switch (mdp->speed) {
685         case 10: /* 10BASE */
686                 sh_eth_write(ndev, 0, RTRATE);
687                 break;
688         case 100:/* 100BASE */
689                 sh_eth_write(ndev, 1, RTRATE);
690                 break;
691         }
692 }
693 
694 /* SH7757 */
695 static struct sh_eth_cpu_data sh7757_data = {
696         .set_duplex     = sh_eth_set_duplex,
697         .set_rate       = sh_eth_set_rate_sh7757,
698 
699         .register_type  = SH_ETH_REG_FAST_SH4,
700 
701         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
702 
703         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
704         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
705                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
706                           EESR_ECI,
707 
708         .irq_flags      = IRQF_SHARED,
709         .apr            = 1,
710         .mpr            = 1,
711         .tpauser        = 1,
712         .hw_swap        = 1,
713         .no_ade         = 1,
714         .rpadir         = 1,
715         .rpadir_value   = 2 << 16,
716         .rtrate         = 1,
717 };
718 
719 #define SH_GIGA_ETH_BASE        0xfee00000UL
720 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
721 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
722 static void sh_eth_chip_reset_giga(struct net_device *ndev)
723 {
724         u32 mahr[2], malr[2];
725         int i;
726 
727         /* save MAHR and MALR */
728         for (i = 0; i < 2; i++) {
729                 malr[i] = ioread32((void *)GIGA_MALR(i));
730                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
731         }
732 
733         sh_eth_chip_reset(ndev);
734 
735         /* restore MAHR and MALR */
736         for (i = 0; i < 2; i++) {
737                 iowrite32(malr[i], (void *)GIGA_MALR(i));
738                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
739         }
740 }
741 
742 static void sh_eth_set_rate_giga(struct net_device *ndev)
743 {
744         struct sh_eth_private *mdp = netdev_priv(ndev);
745 
746         switch (mdp->speed) {
747         case 10: /* 10BASE */
748                 sh_eth_write(ndev, 0x00000000, GECMR);
749                 break;
750         case 100:/* 100BASE */
751                 sh_eth_write(ndev, 0x00000010, GECMR);
752                 break;
753         case 1000: /* 1000BASE */
754                 sh_eth_write(ndev, 0x00000020, GECMR);
755                 break;
756         }
757 }
758 
759 /* SH7757(GETHERC) */
760 static struct sh_eth_cpu_data sh7757_data_giga = {
761         .chip_reset     = sh_eth_chip_reset_giga,
762         .set_duplex     = sh_eth_set_duplex,
763         .set_rate       = sh_eth_set_rate_giga,
764 
765         .register_type  = SH_ETH_REG_GIGABIT,
766 
767         .ecsr_value     = ECSR_ICD | ECSR_MPD,
768         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
769         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
770 
771         .tx_check       = EESR_TC1 | EESR_FTC,
772         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
773                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
774                           EESR_TDE | EESR_ECI,
775         .fdr_value      = 0x0000072f,
776 
777         .irq_flags      = IRQF_SHARED,
778         .apr            = 1,
779         .mpr            = 1,
780         .tpauser        = 1,
781         .bculr          = 1,
782         .hw_swap        = 1,
783         .rpadir         = 1,
784         .rpadir_value   = 2 << 16,
785         .no_trimd       = 1,
786         .no_ade         = 1,
787         .tsu            = 1,
788 };
789 
790 /* SH7734 */
791 static struct sh_eth_cpu_data sh7734_data = {
792         .chip_reset     = sh_eth_chip_reset,
793         .set_duplex     = sh_eth_set_duplex,
794         .set_rate       = sh_eth_set_rate_gether,
795 
796         .register_type  = SH_ETH_REG_GIGABIT,
797 
798         .ecsr_value     = ECSR_ICD | ECSR_MPD,
799         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
800         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
801 
802         .tx_check       = EESR_TC1 | EESR_FTC,
803         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
804                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
805                           EESR_TDE | EESR_ECI,
806 
807         .apr            = 1,
808         .mpr            = 1,
809         .tpauser        = 1,
810         .bculr          = 1,
811         .hw_swap        = 1,
812         .no_trimd       = 1,
813         .no_ade         = 1,
814         .tsu            = 1,
815         .hw_crc         = 1,
816         .select_mii     = 1,
817 };
818 
819 /* SH7763 */
820 static struct sh_eth_cpu_data sh7763_data = {
821         .chip_reset     = sh_eth_chip_reset,
822         .set_duplex     = sh_eth_set_duplex,
823         .set_rate       = sh_eth_set_rate_gether,
824 
825         .register_type  = SH_ETH_REG_GIGABIT,
826 
827         .ecsr_value     = ECSR_ICD | ECSR_MPD,
828         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
829         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
830 
831         .tx_check       = EESR_TC1 | EESR_FTC,
832         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
833                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
834                           EESR_ECI,
835 
836         .apr            = 1,
837         .mpr            = 1,
838         .tpauser        = 1,
839         .bculr          = 1,
840         .hw_swap        = 1,
841         .no_trimd       = 1,
842         .no_ade         = 1,
843         .tsu            = 1,
844         .irq_flags      = IRQF_SHARED,
845 };
846 
847 static struct sh_eth_cpu_data sh7619_data = {
848         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
849 
850         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
851 
852         .apr            = 1,
853         .mpr            = 1,
854         .tpauser        = 1,
855         .hw_swap        = 1,
856 };
857 
858 static struct sh_eth_cpu_data sh771x_data = {
859         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
860 
861         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
862         .tsu            = 1,
863 };
864 
865 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
866 {
867         if (!cd->ecsr_value)
868                 cd->ecsr_value = DEFAULT_ECSR_INIT;
869 
870         if (!cd->ecsipr_value)
871                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
872 
873         if (!cd->fcftr_value)
874                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
875                                   DEFAULT_FIFO_F_D_RFD;
876 
877         if (!cd->fdr_value)
878                 cd->fdr_value = DEFAULT_FDR_INIT;
879 
880         if (!cd->tx_check)
881                 cd->tx_check = DEFAULT_TX_CHECK;
882 
883         if (!cd->eesr_err_check)
884                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
885 
886         if (!cd->trscer_err_mask)
887                 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
888 }
889 
890 static int sh_eth_check_reset(struct net_device *ndev)
891 {
892         int ret = 0;
893         int cnt = 100;
894 
895         while (cnt > 0) {
896                 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
897                         break;
898                 mdelay(1);
899                 cnt--;
900         }
901         if (cnt <= 0) {
902                 netdev_err(ndev, "Device reset failed\n");
903                 ret = -ETIMEDOUT;
904         }
905         return ret;
906 }
907 
908 static int sh_eth_reset(struct net_device *ndev)
909 {
910         struct sh_eth_private *mdp = netdev_priv(ndev);
911         int ret = 0;
912 
913         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
914                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
915                 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
916 
917                 ret = sh_eth_check_reset(ndev);
918                 if (ret)
919                         return ret;
920 
921                 /* Table Init */
922                 sh_eth_write(ndev, 0x0, TDLAR);
923                 sh_eth_write(ndev, 0x0, TDFAR);
924                 sh_eth_write(ndev, 0x0, TDFXR);
925                 sh_eth_write(ndev, 0x0, TDFFR);
926                 sh_eth_write(ndev, 0x0, RDLAR);
927                 sh_eth_write(ndev, 0x0, RDFAR);
928                 sh_eth_write(ndev, 0x0, RDFXR);
929                 sh_eth_write(ndev, 0x0, RDFFR);
930 
931                 /* Reset HW CRC register */
932                 if (mdp->cd->hw_crc)
933                         sh_eth_write(ndev, 0x0, CSMR);
934 
935                 /* Select MII mode */
936                 if (mdp->cd->select_mii)
937                         sh_eth_select_mii(ndev);
938         } else {
939                 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
940                 mdelay(3);
941                 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
942         }
943 
944         return ret;
945 }
946 
947 static void sh_eth_set_receive_align(struct sk_buff *skb)
948 {
949         uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
950 
951         if (reserve)
952                 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
953 }
954 
955 /* Program the hardware MAC address from dev->dev_addr. */
956 static void update_mac_address(struct net_device *ndev)
957 {
958         sh_eth_write(ndev,
959                      (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
960                      (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
961         sh_eth_write(ndev,
962                      (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
963 }
964 
965 /* Get MAC address from SuperH MAC address register
966  *
967  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
968  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
969  * When you want use this device, you must set MAC address in bootloader.
970  *
971  */
972 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
973 {
974         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
975                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
976         } else {
977                 u32 mahr = sh_eth_read(ndev, MAHR);
978                 u32 malr = sh_eth_read(ndev, MALR);
979 
980                 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
981                 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
982                 ndev->dev_addr[2] = (mahr >>  8) & 0xFF;
983                 ndev->dev_addr[3] = (mahr >>  0) & 0xFF;
984                 ndev->dev_addr[4] = (malr >>  8) & 0xFF;
985                 ndev->dev_addr[5] = (malr >>  0) & 0xFF;
986         }
987 }
988 
989 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
990 {
991         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
992                 return EDTRR_TRNS_GETHER;
993         else
994                 return EDTRR_TRNS_ETHER;
995 }
996 
997 struct bb_info {
998         void (*set_gate)(void *addr);
999         struct mdiobb_ctrl ctrl;
1000         void *addr;
1001 };
1002 
1003 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1004 {
1005         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1006         u32 pir;
1007 
1008         if (bitbang->set_gate)
1009                 bitbang->set_gate(bitbang->addr);
1010 
1011         pir = ioread32(bitbang->addr);
1012         if (set)
1013                 pir |=  mask;
1014         else
1015                 pir &= ~mask;
1016         iowrite32(pir, bitbang->addr);
1017 }
1018 
1019 /* Data I/O pin control */
1020 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1021 {
1022         sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1023 }
1024 
1025 /* Set bit data*/
1026 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1027 {
1028         sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1029 }
1030 
1031 /* Get bit data*/
1032 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1033 {
1034         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1035 
1036         if (bitbang->set_gate)
1037                 bitbang->set_gate(bitbang->addr);
1038 
1039         return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1040 }
1041 
1042 /* MDC pin control */
1043 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1044 {
1045         sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1046 }
1047 
1048 /* mdio bus control struct */
1049 static struct mdiobb_ops bb_ops = {
1050         .owner = THIS_MODULE,
1051         .set_mdc = sh_mdc_ctrl,
1052         .set_mdio_dir = sh_mmd_ctrl,
1053         .set_mdio_data = sh_set_mdio,
1054         .get_mdio_data = sh_get_mdio,
1055 };
1056 
1057 /* free skb and descriptor buffer */
1058 static void sh_eth_ring_free(struct net_device *ndev)
1059 {
1060         struct sh_eth_private *mdp = netdev_priv(ndev);
1061         int ringsize, i;
1062 
1063         /* Free Rx skb ringbuffer */
1064         if (mdp->rx_skbuff) {
1065                 for (i = 0; i < mdp->num_rx_ring; i++)
1066                         dev_kfree_skb(mdp->rx_skbuff[i]);
1067         }
1068         kfree(mdp->rx_skbuff);
1069         mdp->rx_skbuff = NULL;
1070 
1071         /* Free Tx skb ringbuffer */
1072         if (mdp->tx_skbuff) {
1073                 for (i = 0; i < mdp->num_tx_ring; i++)
1074                         dev_kfree_skb(mdp->tx_skbuff[i]);
1075         }
1076         kfree(mdp->tx_skbuff);
1077         mdp->tx_skbuff = NULL;
1078 
1079         if (mdp->rx_ring) {
1080                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1081                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1082                                   mdp->rx_desc_dma);
1083                 mdp->rx_ring = NULL;
1084         }
1085 
1086         if (mdp->tx_ring) {
1087                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1088                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1089                                   mdp->tx_desc_dma);
1090                 mdp->tx_ring = NULL;
1091         }
1092 }
1093 
1094 /* format skb and descriptor buffer */
1095 static void sh_eth_ring_format(struct net_device *ndev)
1096 {
1097         struct sh_eth_private *mdp = netdev_priv(ndev);
1098         int i;
1099         struct sk_buff *skb;
1100         struct sh_eth_rxdesc *rxdesc = NULL;
1101         struct sh_eth_txdesc *txdesc = NULL;
1102         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1103         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1104         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1105         dma_addr_t dma_addr;
1106         u32 buf_len;
1107 
1108         mdp->cur_rx = 0;
1109         mdp->cur_tx = 0;
1110         mdp->dirty_rx = 0;
1111         mdp->dirty_tx = 0;
1112 
1113         memset(mdp->rx_ring, 0, rx_ringsize);
1114 
1115         /* build Rx ring buffer */
1116         for (i = 0; i < mdp->num_rx_ring; i++) {
1117                 /* skb */
1118                 mdp->rx_skbuff[i] = NULL;
1119                 skb = netdev_alloc_skb(ndev, skbuff_size);
1120                 if (skb == NULL)
1121                         break;
1122                 sh_eth_set_receive_align(skb);
1123 
1124                 /* The size of the buffer is a multiple of 32 bytes. */
1125                 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1126                 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
1127                                           DMA_FROM_DEVICE);
1128                 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1129                         kfree_skb(skb);
1130                         break;
1131                 }
1132                 mdp->rx_skbuff[i] = skb;
1133 
1134                 /* RX descriptor */
1135                 rxdesc = &mdp->rx_ring[i];
1136                 rxdesc->len = cpu_to_le32(buf_len << 16);
1137                 rxdesc->addr = cpu_to_le32(dma_addr);
1138                 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1139 
1140                 /* Rx descriptor address set */
1141                 if (i == 0) {
1142                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1143                         if (sh_eth_is_gether(mdp) ||
1144                             sh_eth_is_rz_fast_ether(mdp))
1145                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1146                 }
1147         }
1148 
1149         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1150 
1151         /* Mark the last entry as wrapping the ring. */
1152         if (rxdesc)
1153                 rxdesc->status |= cpu_to_le32(RD_RDLE);
1154 
1155         memset(mdp->tx_ring, 0, tx_ringsize);
1156 
1157         /* build Tx ring buffer */
1158         for (i = 0; i < mdp->num_tx_ring; i++) {
1159                 mdp->tx_skbuff[i] = NULL;
1160                 txdesc = &mdp->tx_ring[i];
1161                 txdesc->status = cpu_to_le32(TD_TFP);
1162                 txdesc->len = cpu_to_le32(0);
1163                 if (i == 0) {
1164                         /* Tx descriptor address set */
1165                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1166                         if (sh_eth_is_gether(mdp) ||
1167                             sh_eth_is_rz_fast_ether(mdp))
1168                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1169                 }
1170         }
1171 
1172         txdesc->status |= cpu_to_le32(TD_TDLE);
1173 }
1174 
1175 /* Get skb and descriptor buffer */
1176 static int sh_eth_ring_init(struct net_device *ndev)
1177 {
1178         struct sh_eth_private *mdp = netdev_priv(ndev);
1179         int rx_ringsize, tx_ringsize;
1180 
1181         /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1182          * card needs room to do 8 byte alignment, +2 so we can reserve
1183          * the first 2 bytes, and +16 gets room for the status word from the
1184          * card.
1185          */
1186         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1187                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1188         if (mdp->cd->rpadir)
1189                 mdp->rx_buf_sz += NET_IP_ALIGN;
1190 
1191         /* Allocate RX and TX skb rings */
1192         mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1193                                  GFP_KERNEL);
1194         if (!mdp->rx_skbuff)
1195                 return -ENOMEM;
1196 
1197         mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1198                                  GFP_KERNEL);
1199         if (!mdp->tx_skbuff)
1200                 goto ring_free;
1201 
1202         /* Allocate all Rx descriptors. */
1203         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1204         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1205                                           GFP_KERNEL);
1206         if (!mdp->rx_ring)
1207                 goto ring_free;
1208 
1209         mdp->dirty_rx = 0;
1210 
1211         /* Allocate all Tx descriptors. */
1212         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1213         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1214                                           GFP_KERNEL);
1215         if (!mdp->tx_ring)
1216                 goto ring_free;
1217         return 0;
1218 
1219 ring_free:
1220         /* Free Rx and Tx skb ring buffer and DMA buffer */
1221         sh_eth_ring_free(ndev);
1222 
1223         return -ENOMEM;
1224 }
1225 
1226 static int sh_eth_dev_init(struct net_device *ndev)
1227 {
1228         struct sh_eth_private *mdp = netdev_priv(ndev);
1229         int ret;
1230 
1231         /* Soft Reset */
1232         ret = sh_eth_reset(ndev);
1233         if (ret)
1234                 return ret;
1235 
1236         if (mdp->cd->rmiimode)
1237                 sh_eth_write(ndev, 0x1, RMIIMODE);
1238 
1239         /* Descriptor format */
1240         sh_eth_ring_format(ndev);
1241         if (mdp->cd->rpadir)
1242                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1243 
1244         /* all sh_eth int mask */
1245         sh_eth_write(ndev, 0, EESIPR);
1246 
1247 #if defined(__LITTLE_ENDIAN)
1248         if (mdp->cd->hw_swap)
1249                 sh_eth_write(ndev, EDMR_EL, EDMR);
1250         else
1251 #endif
1252                 sh_eth_write(ndev, 0, EDMR);
1253 
1254         /* FIFO size set */
1255         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1256         sh_eth_write(ndev, 0, TFTR);
1257 
1258         /* Frame recv control (enable multiple-packets per rx irq) */
1259         sh_eth_write(ndev, RMCR_RNC, RMCR);
1260 
1261         sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1262 
1263         if (mdp->cd->bculr)
1264                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1265 
1266         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1267 
1268         if (!mdp->cd->no_trimd)
1269                 sh_eth_write(ndev, 0, TRIMD);
1270 
1271         /* Recv frame limit set register */
1272         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1273                      RFLR);
1274 
1275         sh_eth_modify(ndev, EESR, 0, 0);
1276         mdp->irq_enabled = true;
1277         sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1278 
1279         /* PAUSE Prohibition */
1280         sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1281                      ECMR_TE | ECMR_RE, ECMR);
1282 
1283         if (mdp->cd->set_rate)
1284                 mdp->cd->set_rate(ndev);
1285 
1286         /* E-MAC Status Register clear */
1287         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1288 
1289         /* E-MAC Interrupt Enable register */
1290         sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1291 
1292         /* Set MAC address */
1293         update_mac_address(ndev);
1294 
1295         /* mask reset */
1296         if (mdp->cd->apr)
1297                 sh_eth_write(ndev, APR_AP, APR);
1298         if (mdp->cd->mpr)
1299                 sh_eth_write(ndev, MPR_MP, MPR);
1300         if (mdp->cd->tpauser)
1301                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1302 
1303         /* Setting the Rx mode will start the Rx process. */
1304         sh_eth_write(ndev, EDRRR_R, EDRRR);
1305 
1306         return ret;
1307 }
1308 
1309 static void sh_eth_dev_exit(struct net_device *ndev)
1310 {
1311         struct sh_eth_private *mdp = netdev_priv(ndev);
1312         int i;
1313 
1314         /* Deactivate all TX descriptors, so DMA should stop at next
1315          * packet boundary if it's currently running
1316          */
1317         for (i = 0; i < mdp->num_tx_ring; i++)
1318                 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1319 
1320         /* Disable TX FIFO egress to MAC */
1321         sh_eth_rcv_snd_disable(ndev);
1322 
1323         /* Stop RX DMA at next packet boundary */
1324         sh_eth_write(ndev, 0, EDRRR);
1325 
1326         /* Aside from TX DMA, we can't tell when the hardware is
1327          * really stopped, so we need to reset to make sure.
1328          * Before doing that, wait for long enough to *probably*
1329          * finish transmitting the last packet and poll stats.
1330          */
1331         msleep(2); /* max frame time at 10 Mbps < 1250 us */
1332         sh_eth_get_stats(ndev);
1333         sh_eth_reset(ndev);
1334 
1335         /* Set MAC address again */
1336         update_mac_address(ndev);
1337 }
1338 
1339 /* free Tx skb function */
1340 static int sh_eth_txfree(struct net_device *ndev)
1341 {
1342         struct sh_eth_private *mdp = netdev_priv(ndev);
1343         struct sh_eth_txdesc *txdesc;
1344         int free_num = 0;
1345         int entry;
1346 
1347         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1348                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1349                 txdesc = &mdp->tx_ring[entry];
1350                 if (txdesc->status & cpu_to_le32(TD_TACT))
1351                         break;
1352                 /* TACT bit must be checked before all the following reads */
1353                 dma_rmb();
1354                 netif_info(mdp, tx_done, ndev,
1355                            "tx entry %d status 0x%08x\n",
1356                            entry, le32_to_cpu(txdesc->status));
1357                 /* Free the original skb. */
1358                 if (mdp->tx_skbuff[entry]) {
1359                         dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
1360                                          le32_to_cpu(txdesc->len) >> 16,
1361                                          DMA_TO_DEVICE);
1362                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1363                         mdp->tx_skbuff[entry] = NULL;
1364                         free_num++;
1365                 }
1366                 txdesc->status = cpu_to_le32(TD_TFP);
1367                 if (entry >= mdp->num_tx_ring - 1)
1368                         txdesc->status |= cpu_to_le32(TD_TDLE);
1369 
1370                 ndev->stats.tx_packets++;
1371                 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1372         }
1373         return free_num;
1374 }
1375 
1376 /* Packet receive function */
1377 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1378 {
1379         struct sh_eth_private *mdp = netdev_priv(ndev);
1380         struct sh_eth_rxdesc *rxdesc;
1381 
1382         int entry = mdp->cur_rx % mdp->num_rx_ring;
1383         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1384         int limit;
1385         struct sk_buff *skb;
1386         u32 desc_status;
1387         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1388         dma_addr_t dma_addr;
1389         u16 pkt_len;
1390         u32 buf_len;
1391 
1392         boguscnt = min(boguscnt, *quota);
1393         limit = boguscnt;
1394         rxdesc = &mdp->rx_ring[entry];
1395         while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1396                 /* RACT bit must be checked before all the following reads */
1397                 dma_rmb();
1398                 desc_status = le32_to_cpu(rxdesc->status);
1399                 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1400 
1401                 if (--boguscnt < 0)
1402                         break;
1403 
1404                 netif_info(mdp, rx_status, ndev,
1405                            "rx entry %d status 0x%08x len %d\n",
1406                            entry, desc_status, pkt_len);
1407 
1408                 if (!(desc_status & RDFEND))
1409                         ndev->stats.rx_length_errors++;
1410 
1411                 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1412                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1413                  * bit 0. However, in case of the R8A7740 and R7S72100
1414                  * the RFS bits are from bit 25 to bit 16. So, the
1415                  * driver needs right shifting by 16.
1416                  */
1417                 if (mdp->cd->shift_rd0)
1418                         desc_status >>= 16;
1419 
1420                 skb = mdp->rx_skbuff[entry];
1421                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1422                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1423                         ndev->stats.rx_errors++;
1424                         if (desc_status & RD_RFS1)
1425                                 ndev->stats.rx_crc_errors++;
1426                         if (desc_status & RD_RFS2)
1427                                 ndev->stats.rx_frame_errors++;
1428                         if (desc_status & RD_RFS3)
1429                                 ndev->stats.rx_length_errors++;
1430                         if (desc_status & RD_RFS4)
1431                                 ndev->stats.rx_length_errors++;
1432                         if (desc_status & RD_RFS6)
1433                                 ndev->stats.rx_missed_errors++;
1434                         if (desc_status & RD_RFS10)
1435                                 ndev->stats.rx_over_errors++;
1436                 } else  if (skb) {
1437                         dma_addr = le32_to_cpu(rxdesc->addr);
1438                         if (!mdp->cd->hw_swap)
1439                                 sh_eth_soft_swap(
1440                                         phys_to_virt(ALIGN(dma_addr, 4)),
1441                                         pkt_len + 2);
1442                         mdp->rx_skbuff[entry] = NULL;
1443                         if (mdp->cd->rpadir)
1444                                 skb_reserve(skb, NET_IP_ALIGN);
1445                         dma_unmap_single(&ndev->dev, dma_addr,
1446                                          ALIGN(mdp->rx_buf_sz, 32),
1447                                          DMA_FROM_DEVICE);
1448                         skb_put(skb, pkt_len);
1449                         skb->protocol = eth_type_trans(skb, ndev);
1450                         netif_receive_skb(skb);
1451                         ndev->stats.rx_packets++;
1452                         ndev->stats.rx_bytes += pkt_len;
1453                         if (desc_status & RD_RFS8)
1454                                 ndev->stats.multicast++;
1455                 }
1456                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1457                 rxdesc = &mdp->rx_ring[entry];
1458         }
1459 
1460         /* Refill the Rx ring buffers. */
1461         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1462                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1463                 rxdesc = &mdp->rx_ring[entry];
1464                 /* The size of the buffer is 32 byte boundary. */
1465                 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1466                 rxdesc->len = cpu_to_le32(buf_len << 16);
1467 
1468                 if (mdp->rx_skbuff[entry] == NULL) {
1469                         skb = netdev_alloc_skb(ndev, skbuff_size);
1470                         if (skb == NULL)
1471                                 break;  /* Better luck next round. */
1472                         sh_eth_set_receive_align(skb);
1473                         dma_addr = dma_map_single(&ndev->dev, skb->data,
1474                                                   buf_len, DMA_FROM_DEVICE);
1475                         if (dma_mapping_error(&ndev->dev, dma_addr)) {
1476                                 kfree_skb(skb);
1477                                 break;
1478                         }
1479                         mdp->rx_skbuff[entry] = skb;
1480 
1481                         skb_checksum_none_assert(skb);
1482                         rxdesc->addr = cpu_to_le32(dma_addr);
1483                 }
1484                 dma_wmb(); /* RACT bit must be set after all the above writes */
1485                 if (entry >= mdp->num_rx_ring - 1)
1486                         rxdesc->status |=
1487                                 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1488                 else
1489                         rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1490         }
1491 
1492         /* Restart Rx engine if stopped. */
1493         /* If we don't need to check status, don't. -KDU */
1494         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1495                 /* fix the values for the next receiving if RDE is set */
1496                 if (intr_status & EESR_RDE &&
1497                     mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
1498                         u32 count = (sh_eth_read(ndev, RDFAR) -
1499                                      sh_eth_read(ndev, RDLAR)) >> 4;
1500 
1501                         mdp->cur_rx = count;
1502                         mdp->dirty_rx = count;
1503                 }
1504                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1505         }
1506 
1507         *quota -= limit - boguscnt - 1;
1508 
1509         return *quota <= 0;
1510 }
1511 
1512 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1513 {
1514         /* disable tx and rx */
1515         sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1516 }
1517 
1518 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1519 {
1520         /* enable tx and rx */
1521         sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1522 }
1523 
1524 /* error control function */
1525 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1526 {
1527         struct sh_eth_private *mdp = netdev_priv(ndev);
1528         u32 felic_stat;
1529         u32 link_stat;
1530         u32 mask;
1531 
1532         if (intr_status & EESR_ECI) {
1533                 felic_stat = sh_eth_read(ndev, ECSR);
1534                 sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1535                 if (felic_stat & ECSR_ICD)
1536                         ndev->stats.tx_carrier_errors++;
1537                 if (felic_stat & ECSR_LCHNG) {
1538                         /* Link Changed */
1539                         if (mdp->cd->no_psr || mdp->no_ether_link) {
1540                                 goto ignore_link;
1541                         } else {
1542                                 link_stat = (sh_eth_read(ndev, PSR));
1543                                 if (mdp->ether_link_active_low)
1544                                         link_stat = ~link_stat;
1545                         }
1546                         if (!(link_stat & PHY_ST_LINK)) {
1547                                 sh_eth_rcv_snd_disable(ndev);
1548                         } else {
1549                                 /* Link Up */
1550                                 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, 0);
1551                                 /* clear int */
1552                                 sh_eth_modify(ndev, ECSR, 0, 0);
1553                                 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI,
1554                                               DMAC_M_ECI);
1555                                 /* enable tx and rx */
1556                                 sh_eth_rcv_snd_enable(ndev);
1557                         }
1558                 }
1559         }
1560 
1561 ignore_link:
1562         if (intr_status & EESR_TWB) {
1563                 /* Unused write back interrupt */
1564                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1565                         ndev->stats.tx_aborted_errors++;
1566                         netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1567                 }
1568         }
1569 
1570         if (intr_status & EESR_RABT) {
1571                 /* Receive Abort int */
1572                 if (intr_status & EESR_RFRMER) {
1573                         /* Receive Frame Overflow int */
1574                         ndev->stats.rx_frame_errors++;
1575                 }
1576         }
1577 
1578         if (intr_status & EESR_TDE) {
1579                 /* Transmit Descriptor Empty int */
1580                 ndev->stats.tx_fifo_errors++;
1581                 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1582         }
1583 
1584         if (intr_status & EESR_TFE) {
1585                 /* FIFO under flow */
1586                 ndev->stats.tx_fifo_errors++;
1587                 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1588         }
1589 
1590         if (intr_status & EESR_RDE) {
1591                 /* Receive Descriptor Empty int */
1592                 ndev->stats.rx_over_errors++;
1593         }
1594 
1595         if (intr_status & EESR_RFE) {
1596                 /* Receive FIFO Overflow int */
1597                 ndev->stats.rx_fifo_errors++;
1598         }
1599 
1600         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1601                 /* Address Error */
1602                 ndev->stats.tx_fifo_errors++;
1603                 netif_err(mdp, tx_err, ndev, "Address Error\n");
1604         }
1605 
1606         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1607         if (mdp->cd->no_ade)
1608                 mask &= ~EESR_ADE;
1609         if (intr_status & mask) {
1610                 /* Tx error */
1611                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1612 
1613                 /* dmesg */
1614                 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1615                            intr_status, mdp->cur_tx, mdp->dirty_tx,
1616                            (u32)ndev->state, edtrr);
1617                 /* dirty buffer free */
1618                 sh_eth_txfree(ndev);
1619 
1620                 /* SH7712 BUG */
1621                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1622                         /* tx dma start */
1623                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1624                 }
1625                 /* wakeup */
1626                 netif_wake_queue(ndev);
1627         }
1628 }
1629 
1630 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1631 {
1632         struct net_device *ndev = netdev;
1633         struct sh_eth_private *mdp = netdev_priv(ndev);
1634         struct sh_eth_cpu_data *cd = mdp->cd;
1635         irqreturn_t ret = IRQ_NONE;
1636         u32 intr_status, intr_enable;
1637 
1638         spin_lock(&mdp->lock);
1639 
1640         /* Get interrupt status */
1641         intr_status = sh_eth_read(ndev, EESR);
1642         /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1643          * enabled since it's the one that  comes thru regardless of the mask,
1644          * and we need to fully handle it in sh_eth_error() in order to quench
1645          * it as it doesn't get cleared by just writing 1 to the ECI bit...
1646          */
1647         intr_enable = sh_eth_read(ndev, EESIPR);
1648         intr_status &= intr_enable | DMAC_M_ECI;
1649         if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1650                 ret = IRQ_HANDLED;
1651         else
1652                 goto out;
1653 
1654         if (!likely(mdp->irq_enabled)) {
1655                 sh_eth_write(ndev, 0, EESIPR);
1656                 goto out;
1657         }
1658 
1659         if (intr_status & EESR_RX_CHECK) {
1660                 if (napi_schedule_prep(&mdp->napi)) {
1661                         /* Mask Rx interrupts */
1662                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1663                                      EESIPR);
1664                         __napi_schedule(&mdp->napi);
1665                 } else {
1666                         netdev_warn(ndev,
1667                                     "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1668                                     intr_status, intr_enable);
1669                 }
1670         }
1671 
1672         /* Tx Check */
1673         if (intr_status & cd->tx_check) {
1674                 /* Clear Tx interrupts */
1675                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1676 
1677                 sh_eth_txfree(ndev);
1678                 netif_wake_queue(ndev);
1679         }
1680 
1681         if (intr_status & cd->eesr_err_check) {
1682                 /* Clear error interrupts */
1683                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1684 
1685                 sh_eth_error(ndev, intr_status);
1686         }
1687 
1688 out:
1689         spin_unlock(&mdp->lock);
1690 
1691         return ret;
1692 }
1693 
1694 static int sh_eth_poll(struct napi_struct *napi, int budget)
1695 {
1696         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1697                                                   napi);
1698         struct net_device *ndev = napi->dev;
1699         int quota = budget;
1700         u32 intr_status;
1701 
1702         for (;;) {
1703                 intr_status = sh_eth_read(ndev, EESR);
1704                 if (!(intr_status & EESR_RX_CHECK))
1705                         break;
1706                 /* Clear Rx interrupts */
1707                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1708 
1709                 if (sh_eth_rx(ndev, intr_status, &quota))
1710                         goto out;
1711         }
1712 
1713         napi_complete(napi);
1714 
1715         /* Reenable Rx interrupts */
1716         if (mdp->irq_enabled)
1717                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1718 out:
1719         return budget - quota;
1720 }
1721 
1722 /* PHY state control function */
1723 static void sh_eth_adjust_link(struct net_device *ndev)
1724 {
1725         struct sh_eth_private *mdp = netdev_priv(ndev);
1726         struct phy_device *phydev = mdp->phydev;
1727         int new_state = 0;
1728 
1729         if (phydev->link) {
1730                 if (phydev->duplex != mdp->duplex) {
1731                         new_state = 1;
1732                         mdp->duplex = phydev->duplex;
1733                         if (mdp->cd->set_duplex)
1734                                 mdp->cd->set_duplex(ndev);
1735                 }
1736 
1737                 if (phydev->speed != mdp->speed) {
1738                         new_state = 1;
1739                         mdp->speed = phydev->speed;
1740                         if (mdp->cd->set_rate)
1741                                 mdp->cd->set_rate(ndev);
1742                 }
1743                 if (!mdp->link) {
1744                         sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1745                         new_state = 1;
1746                         mdp->link = phydev->link;
1747                         if (mdp->cd->no_psr || mdp->no_ether_link)
1748                                 sh_eth_rcv_snd_enable(ndev);
1749                 }
1750         } else if (mdp->link) {
1751                 new_state = 1;
1752                 mdp->link = 0;
1753                 mdp->speed = 0;
1754                 mdp->duplex = -1;
1755                 if (mdp->cd->no_psr || mdp->no_ether_link)
1756                         sh_eth_rcv_snd_disable(ndev);
1757         }
1758 
1759         if (new_state && netif_msg_link(mdp))
1760                 phy_print_status(phydev);
1761 }
1762 
1763 /* PHY init function */
1764 static int sh_eth_phy_init(struct net_device *ndev)
1765 {
1766         struct device_node *np = ndev->dev.parent->of_node;
1767         struct sh_eth_private *mdp = netdev_priv(ndev);
1768         struct phy_device *phydev;
1769 
1770         mdp->link = 0;
1771         mdp->speed = 0;
1772         mdp->duplex = -1;
1773 
1774         /* Try connect to PHY */
1775         if (np) {
1776                 struct device_node *pn;
1777 
1778                 pn = of_parse_phandle(np, "phy-handle", 0);
1779                 phydev = of_phy_connect(ndev, pn,
1780                                         sh_eth_adjust_link, 0,
1781                                         mdp->phy_interface);
1782 
1783                 if (!phydev)
1784                         phydev = ERR_PTR(-ENOENT);
1785         } else {
1786                 char phy_id[MII_BUS_ID_SIZE + 3];
1787 
1788                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1789                          mdp->mii_bus->id, mdp->phy_id);
1790 
1791                 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1792                                      mdp->phy_interface);
1793         }
1794 
1795         if (IS_ERR(phydev)) {
1796                 netdev_err(ndev, "failed to connect PHY\n");
1797                 return PTR_ERR(phydev);
1798         }
1799 
1800         phy_attached_info(phydev);
1801 
1802         mdp->phydev = phydev;
1803 
1804         return 0;
1805 }
1806 
1807 /* PHY control start function */
1808 static int sh_eth_phy_start(struct net_device *ndev)
1809 {
1810         struct sh_eth_private *mdp = netdev_priv(ndev);
1811         int ret;
1812 
1813         ret = sh_eth_phy_init(ndev);
1814         if (ret)
1815                 return ret;
1816 
1817         phy_start(mdp->phydev);
1818 
1819         return 0;
1820 }
1821 
1822 static int sh_eth_get_settings(struct net_device *ndev,
1823                                struct ethtool_cmd *ecmd)
1824 {
1825         struct sh_eth_private *mdp = netdev_priv(ndev);
1826         unsigned long flags;
1827         int ret;
1828 
1829         if (!mdp->phydev)
1830                 return -ENODEV;
1831 
1832         spin_lock_irqsave(&mdp->lock, flags);
1833         ret = phy_ethtool_gset(mdp->phydev, ecmd);
1834         spin_unlock_irqrestore(&mdp->lock, flags);
1835 
1836         return ret;
1837 }
1838 
1839 static int sh_eth_set_settings(struct net_device *ndev,
1840                                struct ethtool_cmd *ecmd)
1841 {
1842         struct sh_eth_private *mdp = netdev_priv(ndev);
1843         unsigned long flags;
1844         int ret;
1845 
1846         if (!mdp->phydev)
1847                 return -ENODEV;
1848 
1849         spin_lock_irqsave(&mdp->lock, flags);
1850 
1851         /* disable tx and rx */
1852         sh_eth_rcv_snd_disable(ndev);
1853 
1854         ret = phy_ethtool_sset(mdp->phydev, ecmd);
1855         if (ret)
1856                 goto error_exit;
1857 
1858         if (ecmd->duplex == DUPLEX_FULL)
1859                 mdp->duplex = 1;
1860         else
1861                 mdp->duplex = 0;
1862 
1863         if (mdp->cd->set_duplex)
1864                 mdp->cd->set_duplex(ndev);
1865 
1866 error_exit:
1867         mdelay(1);
1868 
1869         /* enable tx and rx */
1870         sh_eth_rcv_snd_enable(ndev);
1871 
1872         spin_unlock_irqrestore(&mdp->lock, flags);
1873 
1874         return ret;
1875 }
1876 
1877 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1878  * version must be bumped as well.  Just adding registers up to that
1879  * limit is fine, as long as the existing register indices don't
1880  * change.
1881  */
1882 #define SH_ETH_REG_DUMP_VERSION         1
1883 #define SH_ETH_REG_DUMP_MAX_REGS        256
1884 
1885 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1886 {
1887         struct sh_eth_private *mdp = netdev_priv(ndev);
1888         struct sh_eth_cpu_data *cd = mdp->cd;
1889         u32 *valid_map;
1890         size_t len;
1891 
1892         BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1893 
1894         /* Dump starts with a bitmap that tells ethtool which
1895          * registers are defined for this chip.
1896          */
1897         len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1898         if (buf) {
1899                 valid_map = buf;
1900                 buf += len;
1901         } else {
1902                 valid_map = NULL;
1903         }
1904 
1905         /* Add a register to the dump, if it has a defined offset.
1906          * This automatically skips most undefined registers, but for
1907          * some it is also necessary to check a capability flag in
1908          * struct sh_eth_cpu_data.
1909          */
1910 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1911 #define add_reg_from(reg, read_expr) do {                               \
1912                 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) {    \
1913                         if (buf) {                                      \
1914                                 mark_reg_valid(reg);                    \
1915                                 *buf++ = read_expr;                     \
1916                         }                                               \
1917                         ++len;                                          \
1918                 }                                                       \
1919         } while (0)
1920 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1921 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
1922 
1923         add_reg(EDSR);
1924         add_reg(EDMR);
1925         add_reg(EDTRR);
1926         add_reg(EDRRR);
1927         add_reg(EESR);
1928         add_reg(EESIPR);
1929         add_reg(TDLAR);
1930         add_reg(TDFAR);
1931         add_reg(TDFXR);
1932         add_reg(TDFFR);
1933         add_reg(RDLAR);
1934         add_reg(RDFAR);
1935         add_reg(RDFXR);
1936         add_reg(RDFFR);
1937         add_reg(TRSCER);
1938         add_reg(RMFCR);
1939         add_reg(TFTR);
1940         add_reg(FDR);
1941         add_reg(RMCR);
1942         add_reg(TFUCR);
1943         add_reg(RFOCR);
1944         if (cd->rmiimode)
1945                 add_reg(RMIIMODE);
1946         add_reg(FCFTR);
1947         if (cd->rpadir)
1948                 add_reg(RPADIR);
1949         if (!cd->no_trimd)
1950                 add_reg(TRIMD);
1951         add_reg(ECMR);
1952         add_reg(ECSR);
1953         add_reg(ECSIPR);
1954         add_reg(PIR);
1955         if (!cd->no_psr)
1956                 add_reg(PSR);
1957         add_reg(RDMLR);
1958         add_reg(RFLR);
1959         add_reg(IPGR);
1960         if (cd->apr)
1961                 add_reg(APR);
1962         if (cd->mpr)
1963                 add_reg(MPR);
1964         add_reg(RFCR);
1965         add_reg(RFCF);
1966         if (cd->tpauser)
1967                 add_reg(TPAUSER);
1968         add_reg(TPAUSECR);
1969         add_reg(GECMR);
1970         if (cd->bculr)
1971                 add_reg(BCULR);
1972         add_reg(MAHR);
1973         add_reg(MALR);
1974         add_reg(TROCR);
1975         add_reg(CDCR);
1976         add_reg(LCCR);
1977         add_reg(CNDCR);
1978         add_reg(CEFCR);
1979         add_reg(FRECR);
1980         add_reg(TSFRCR);
1981         add_reg(TLFRCR);
1982         add_reg(CERCR);
1983         add_reg(CEECR);
1984         add_reg(MAFCR);
1985         if (cd->rtrate)
1986                 add_reg(RTRATE);
1987         if (cd->hw_crc)
1988                 add_reg(CSMR);
1989         if (cd->select_mii)
1990                 add_reg(RMII_MII);
1991         add_reg(ARSTR);
1992         if (cd->tsu) {
1993                 add_tsu_reg(TSU_CTRST);
1994                 add_tsu_reg(TSU_FWEN0);
1995                 add_tsu_reg(TSU_FWEN1);
1996                 add_tsu_reg(TSU_FCM);
1997                 add_tsu_reg(TSU_BSYSL0);
1998                 add_tsu_reg(TSU_BSYSL1);
1999                 add_tsu_reg(TSU_PRISL0);
2000                 add_tsu_reg(TSU_PRISL1);
2001                 add_tsu_reg(TSU_FWSL0);
2002                 add_tsu_reg(TSU_FWSL1);
2003                 add_tsu_reg(TSU_FWSLC);
2004                 add_tsu_reg(TSU_QTAG0);
2005                 add_tsu_reg(TSU_QTAG1);
2006                 add_tsu_reg(TSU_QTAGM0);
2007                 add_tsu_reg(TSU_QTAGM1);
2008                 add_tsu_reg(TSU_FWSR);
2009                 add_tsu_reg(TSU_FWINMK);
2010                 add_tsu_reg(TSU_ADQT0);
2011                 add_tsu_reg(TSU_ADQT1);
2012                 add_tsu_reg(TSU_VTAG0);
2013                 add_tsu_reg(TSU_VTAG1);
2014                 add_tsu_reg(TSU_ADSBSY);
2015                 add_tsu_reg(TSU_TEN);
2016                 add_tsu_reg(TSU_POST1);
2017                 add_tsu_reg(TSU_POST2);
2018                 add_tsu_reg(TSU_POST3);
2019                 add_tsu_reg(TSU_POST4);
2020                 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2021                         /* This is the start of a table, not just a single
2022                          * register.
2023                          */
2024                         if (buf) {
2025                                 unsigned int i;
2026 
2027                                 mark_reg_valid(TSU_ADRH0);
2028                                 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2029                                         *buf++ = ioread32(
2030                                                 mdp->tsu_addr +
2031                                                 mdp->reg_offset[TSU_ADRH0] +
2032                                                 i * 4);
2033                         }
2034                         len += SH_ETH_TSU_CAM_ENTRIES * 2;
2035                 }
2036         }
2037 
2038 #undef mark_reg_valid
2039 #undef add_reg_from
2040 #undef add_reg
2041 #undef add_tsu_reg
2042 
2043         return len * 4;
2044 }
2045 
2046 static int sh_eth_get_regs_len(struct net_device *ndev)
2047 {
2048         return __sh_eth_get_regs(ndev, NULL);
2049 }
2050 
2051 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2052                             void *buf)
2053 {
2054         struct sh_eth_private *mdp = netdev_priv(ndev);
2055 
2056         regs->version = SH_ETH_REG_DUMP_VERSION;
2057 
2058         pm_runtime_get_sync(&mdp->pdev->dev);
2059         __sh_eth_get_regs(ndev, buf);
2060         pm_runtime_put_sync(&mdp->pdev->dev);
2061 }
2062 
2063 static int sh_eth_nway_reset(struct net_device *ndev)
2064 {
2065         struct sh_eth_private *mdp = netdev_priv(ndev);
2066         unsigned long flags;
2067         int ret;
2068 
2069         if (!mdp->phydev)
2070                 return -ENODEV;
2071 
2072         spin_lock_irqsave(&mdp->lock, flags);
2073         ret = phy_start_aneg(mdp->phydev);
2074         spin_unlock_irqrestore(&mdp->lock, flags);
2075 
2076         return ret;
2077 }
2078 
2079 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2080 {
2081         struct sh_eth_private *mdp = netdev_priv(ndev);
2082         return mdp->msg_enable;
2083 }
2084 
2085 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2086 {
2087         struct sh_eth_private *mdp = netdev_priv(ndev);
2088         mdp->msg_enable = value;
2089 }
2090 
2091 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2092         "rx_current", "tx_current",
2093         "rx_dirty", "tx_dirty",
2094 };
2095 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
2096 
2097 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2098 {
2099         switch (sset) {
2100         case ETH_SS_STATS:
2101                 return SH_ETH_STATS_LEN;
2102         default:
2103                 return -EOPNOTSUPP;
2104         }
2105 }
2106 
2107 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2108                                      struct ethtool_stats *stats, u64 *data)
2109 {
2110         struct sh_eth_private *mdp = netdev_priv(ndev);
2111         int i = 0;
2112 
2113         /* device-specific stats */
2114         data[i++] = mdp->cur_rx;
2115         data[i++] = mdp->cur_tx;
2116         data[i++] = mdp->dirty_rx;
2117         data[i++] = mdp->dirty_tx;
2118 }
2119 
2120 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2121 {
2122         switch (stringset) {
2123         case ETH_SS_STATS:
2124                 memcpy(data, *sh_eth_gstrings_stats,
2125                        sizeof(sh_eth_gstrings_stats));
2126                 break;
2127         }
2128 }
2129 
2130 static void sh_eth_get_ringparam(struct net_device *ndev,
2131                                  struct ethtool_ringparam *ring)
2132 {
2133         struct sh_eth_private *mdp = netdev_priv(ndev);
2134 
2135         ring->rx_max_pending = RX_RING_MAX;
2136         ring->tx_max_pending = TX_RING_MAX;
2137         ring->rx_pending = mdp->num_rx_ring;
2138         ring->tx_pending = mdp->num_tx_ring;
2139 }
2140 
2141 static int sh_eth_set_ringparam(struct net_device *ndev,
2142                                 struct ethtool_ringparam *ring)
2143 {
2144         struct sh_eth_private *mdp = netdev_priv(ndev);
2145         int ret;
2146 
2147         if (ring->tx_pending > TX_RING_MAX ||
2148             ring->rx_pending > RX_RING_MAX ||
2149             ring->tx_pending < TX_RING_MIN ||
2150             ring->rx_pending < RX_RING_MIN)
2151                 return -EINVAL;
2152         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2153                 return -EINVAL;
2154 
2155         if (netif_running(ndev)) {
2156                 netif_device_detach(ndev);
2157                 netif_tx_disable(ndev);
2158 
2159                 /* Serialise with the interrupt handler and NAPI, then
2160                  * disable interrupts.  We have to clear the
2161                  * irq_enabled flag first to ensure that interrupts
2162                  * won't be re-enabled.
2163                  */
2164                 mdp->irq_enabled = false;
2165                 synchronize_irq(ndev->irq);
2166                 napi_synchronize(&mdp->napi);
2167                 sh_eth_write(ndev, 0x0000, EESIPR);
2168 
2169                 sh_eth_dev_exit(ndev);
2170 
2171                 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2172                 sh_eth_ring_free(ndev);
2173         }
2174 
2175         /* Set new parameters */
2176         mdp->num_rx_ring = ring->rx_pending;
2177         mdp->num_tx_ring = ring->tx_pending;
2178 
2179         if (netif_running(ndev)) {
2180                 ret = sh_eth_ring_init(ndev);
2181                 if (ret < 0) {
2182                         netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2183                                    __func__);
2184                         return ret;
2185                 }
2186                 ret = sh_eth_dev_init(ndev);
2187                 if (ret < 0) {
2188                         netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2189                                    __func__);
2190                         return ret;
2191                 }
2192 
2193                 netif_device_attach(ndev);
2194         }
2195 
2196         return 0;
2197 }
2198 
2199 static const struct ethtool_ops sh_eth_ethtool_ops = {
2200         .get_settings   = sh_eth_get_settings,
2201         .set_settings   = sh_eth_set_settings,
2202         .get_regs_len   = sh_eth_get_regs_len,
2203         .get_regs       = sh_eth_get_regs,
2204         .nway_reset     = sh_eth_nway_reset,
2205         .get_msglevel   = sh_eth_get_msglevel,
2206         .set_msglevel   = sh_eth_set_msglevel,
2207         .get_link       = ethtool_op_get_link,
2208         .get_strings    = sh_eth_get_strings,
2209         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
2210         .get_sset_count     = sh_eth_get_sset_count,
2211         .get_ringparam  = sh_eth_get_ringparam,
2212         .set_ringparam  = sh_eth_set_ringparam,
2213 };
2214 
2215 /* network device open function */
2216 static int sh_eth_open(struct net_device *ndev)
2217 {
2218         struct sh_eth_private *mdp = netdev_priv(ndev);
2219         int ret;
2220 
2221         pm_runtime_get_sync(&mdp->pdev->dev);
2222 
2223         napi_enable(&mdp->napi);
2224 
2225         ret = request_irq(ndev->irq, sh_eth_interrupt,
2226                           mdp->cd->irq_flags, ndev->name, ndev);
2227         if (ret) {
2228                 netdev_err(ndev, "Can not assign IRQ number\n");
2229                 goto out_napi_off;
2230         }
2231 
2232         /* Descriptor set */
2233         ret = sh_eth_ring_init(ndev);
2234         if (ret)
2235                 goto out_free_irq;
2236 
2237         /* device init */
2238         ret = sh_eth_dev_init(ndev);
2239         if (ret)
2240                 goto out_free_irq;
2241 
2242         /* PHY control start*/
2243         ret = sh_eth_phy_start(ndev);
2244         if (ret)
2245                 goto out_free_irq;
2246 
2247         netif_start_queue(ndev);
2248 
2249         mdp->is_opened = 1;
2250 
2251         return ret;
2252 
2253 out_free_irq:
2254         free_irq(ndev->irq, ndev);
2255 out_napi_off:
2256         napi_disable(&mdp->napi);
2257         pm_runtime_put_sync(&mdp->pdev->dev);
2258         return ret;
2259 }
2260 
2261 /* Timeout function */
2262 static void sh_eth_tx_timeout(struct net_device *ndev)
2263 {
2264         struct sh_eth_private *mdp = netdev_priv(ndev);
2265         struct sh_eth_rxdesc *rxdesc;
2266         int i;
2267 
2268         netif_stop_queue(ndev);
2269 
2270         netif_err(mdp, timer, ndev,
2271                   "transmit timed out, status %8.8x, resetting...\n",
2272                   sh_eth_read(ndev, EESR));
2273 
2274         /* tx_errors count up */
2275         ndev->stats.tx_errors++;
2276 
2277         /* Free all the skbuffs in the Rx queue. */
2278         for (i = 0; i < mdp->num_rx_ring; i++) {
2279                 rxdesc = &mdp->rx_ring[i];
2280                 rxdesc->status = cpu_to_le32(0);
2281                 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2282                 dev_kfree_skb(mdp->rx_skbuff[i]);
2283                 mdp->rx_skbuff[i] = NULL;
2284         }
2285         for (i = 0; i < mdp->num_tx_ring; i++) {
2286                 dev_kfree_skb(mdp->tx_skbuff[i]);
2287                 mdp->tx_skbuff[i] = NULL;
2288         }
2289 
2290         /* device init */
2291         sh_eth_dev_init(ndev);
2292 
2293         netif_start_queue(ndev);
2294 }
2295 
2296 /* Packet transmit function */
2297 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2298 {
2299         struct sh_eth_private *mdp = netdev_priv(ndev);
2300         struct sh_eth_txdesc *txdesc;
2301         dma_addr_t dma_addr;
2302         u32 entry;
2303         unsigned long flags;
2304 
2305         spin_lock_irqsave(&mdp->lock, flags);
2306         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2307                 if (!sh_eth_txfree(ndev)) {
2308                         netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2309                         netif_stop_queue(ndev);
2310                         spin_unlock_irqrestore(&mdp->lock, flags);
2311                         return NETDEV_TX_BUSY;
2312                 }
2313         }
2314         spin_unlock_irqrestore(&mdp->lock, flags);
2315 
2316         if (skb_put_padto(skb, ETH_ZLEN))
2317                 return NETDEV_TX_OK;
2318 
2319         entry = mdp->cur_tx % mdp->num_tx_ring;
2320         mdp->tx_skbuff[entry] = skb;
2321         txdesc = &mdp->tx_ring[entry];
2322         /* soft swap. */
2323         if (!mdp->cd->hw_swap)
2324                 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2325         dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2326                                   DMA_TO_DEVICE);
2327         if (dma_mapping_error(&ndev->dev, dma_addr)) {
2328                 kfree_skb(skb);
2329                 return NETDEV_TX_OK;
2330         }
2331         txdesc->addr = cpu_to_le32(dma_addr);
2332         txdesc->len  = cpu_to_le32(skb->len << 16);
2333 
2334         dma_wmb(); /* TACT bit must be set after all the above writes */
2335         if (entry >= mdp->num_tx_ring - 1)
2336                 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2337         else
2338                 txdesc->status |= cpu_to_le32(TD_TACT);
2339 
2340         mdp->cur_tx++;
2341 
2342         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2343                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2344 
2345         return NETDEV_TX_OK;
2346 }
2347 
2348 /* The statistics registers have write-clear behaviour, which means we
2349  * will lose any increment between the read and write.  We mitigate
2350  * this by only clearing when we read a non-zero value, so we will
2351  * never falsely report a total of zero.
2352  */
2353 static void
2354 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2355 {
2356         u32 delta = sh_eth_read(ndev, reg);
2357 
2358         if (delta) {
2359                 *stat += delta;
2360                 sh_eth_write(ndev, 0, reg);
2361         }
2362 }
2363 
2364 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2365 {
2366         struct sh_eth_private *mdp = netdev_priv(ndev);
2367 
2368         if (sh_eth_is_rz_fast_ether(mdp))
2369                 return &ndev->stats;
2370 
2371         if (!mdp->is_opened)
2372                 return &ndev->stats;
2373 
2374         sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2375         sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2376         sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2377 
2378         if (sh_eth_is_gether(mdp)) {
2379                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2380                                    CERCR);
2381                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2382                                    CEECR);
2383         } else {
2384                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2385                                    CNDCR);
2386         }
2387 
2388         return &ndev->stats;
2389 }
2390 
2391 /* device close function */
2392 static int sh_eth_close(struct net_device *ndev)
2393 {
2394         struct sh_eth_private *mdp = netdev_priv(ndev);
2395 
2396         netif_stop_queue(ndev);
2397 
2398         /* Serialise with the interrupt handler and NAPI, then disable
2399          * interrupts.  We have to clear the irq_enabled flag first to
2400          * ensure that interrupts won't be re-enabled.
2401          */
2402         mdp->irq_enabled = false;
2403         synchronize_irq(ndev->irq);
2404         napi_disable(&mdp->napi);
2405         sh_eth_write(ndev, 0x0000, EESIPR);
2406 
2407         sh_eth_dev_exit(ndev);
2408 
2409         /* PHY Disconnect */
2410         if (mdp->phydev) {
2411                 phy_stop(mdp->phydev);
2412                 phy_disconnect(mdp->phydev);
2413                 mdp->phydev = NULL;
2414         }
2415 
2416         free_irq(ndev->irq, ndev);
2417 
2418         /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2419         sh_eth_ring_free(ndev);
2420 
2421         pm_runtime_put_sync(&mdp->pdev->dev);
2422 
2423         mdp->is_opened = 0;
2424 
2425         return 0;
2426 }
2427 
2428 /* ioctl to device function */
2429 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2430 {
2431         struct sh_eth_private *mdp = netdev_priv(ndev);
2432         struct phy_device *phydev = mdp->phydev;
2433 
2434         if (!netif_running(ndev))
2435                 return -EINVAL;
2436 
2437         if (!phydev)
2438                 return -ENODEV;
2439 
2440         return phy_mii_ioctl(phydev, rq, cmd);
2441 }
2442 
2443 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2444 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2445                                             int entry)
2446 {
2447         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2448 }
2449 
2450 static u32 sh_eth_tsu_get_post_mask(int entry)
2451 {
2452         return 0x0f << (28 - ((entry % 8) * 4));
2453 }
2454 
2455 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2456 {
2457         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2458 }
2459 
2460 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2461                                              int entry)
2462 {
2463         struct sh_eth_private *mdp = netdev_priv(ndev);
2464         u32 tmp;
2465         void *reg_offset;
2466 
2467         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2468         tmp = ioread32(reg_offset);
2469         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2470 }
2471 
2472 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2473                                               int entry)
2474 {
2475         struct sh_eth_private *mdp = netdev_priv(ndev);
2476         u32 post_mask, ref_mask, tmp;
2477         void *reg_offset;
2478 
2479         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2480         post_mask = sh_eth_tsu_get_post_mask(entry);
2481         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2482 
2483         tmp = ioread32(reg_offset);
2484         iowrite32(tmp & ~post_mask, reg_offset);
2485 
2486         /* If other port enables, the function returns "true" */
2487         return tmp & ref_mask;
2488 }
2489 
2490 static int sh_eth_tsu_busy(struct net_device *ndev)
2491 {
2492         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2493         struct sh_eth_private *mdp = netdev_priv(ndev);
2494 
2495         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2496                 udelay(10);
2497                 timeout--;
2498                 if (timeout <= 0) {
2499                         netdev_err(ndev, "%s: timeout\n", __func__);
2500                         return -ETIMEDOUT;
2501                 }
2502         }
2503 
2504         return 0;
2505 }
2506 
2507 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2508                                   const u8 *addr)
2509 {
2510         u32 val;
2511 
2512         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2513         iowrite32(val, reg);
2514         if (sh_eth_tsu_busy(ndev) < 0)
2515                 return -EBUSY;
2516 
2517         val = addr[4] << 8 | addr[5];
2518         iowrite32(val, reg + 4);
2519         if (sh_eth_tsu_busy(ndev) < 0)
2520                 return -EBUSY;
2521 
2522         return 0;
2523 }
2524 
2525 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2526 {
2527         u32 val;
2528 
2529         val = ioread32(reg);
2530         addr[0] = (val >> 24) & 0xff;
2531         addr[1] = (val >> 16) & 0xff;
2532         addr[2] = (val >> 8) & 0xff;
2533         addr[3] = val & 0xff;
2534         val = ioread32(reg + 4);
2535         addr[4] = (val >> 8) & 0xff;
2536         addr[5] = val & 0xff;
2537 }
2538 
2539 
2540 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2541 {
2542         struct sh_eth_private *mdp = netdev_priv(ndev);
2543         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2544         int i;
2545         u8 c_addr[ETH_ALEN];
2546 
2547         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2548                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2549                 if (ether_addr_equal(addr, c_addr))
2550                         return i;
2551         }
2552 
2553         return -ENOENT;
2554 }
2555 
2556 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2557 {
2558         u8 blank[ETH_ALEN];
2559         int entry;
2560 
2561         memset(blank, 0, sizeof(blank));
2562         entry = sh_eth_tsu_find_entry(ndev, blank);
2563         return (entry < 0) ? -ENOMEM : entry;
2564 }
2565 
2566 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2567                                               int entry)
2568 {
2569         struct sh_eth_private *mdp = netdev_priv(ndev);
2570         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2571         int ret;
2572         u8 blank[ETH_ALEN];
2573 
2574         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2575                          ~(1 << (31 - entry)), TSU_TEN);
2576 
2577         memset(blank, 0, sizeof(blank));
2578         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2579         if (ret < 0)
2580                 return ret;
2581         return 0;
2582 }
2583 
2584 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2585 {
2586         struct sh_eth_private *mdp = netdev_priv(ndev);
2587         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2588         int i, ret;
2589 
2590         if (!mdp->cd->tsu)
2591                 return 0;
2592 
2593         i = sh_eth_tsu_find_entry(ndev, addr);
2594         if (i < 0) {
2595                 /* No entry found, create one */
2596                 i = sh_eth_tsu_find_empty(ndev);
2597                 if (i < 0)
2598                         return -ENOMEM;
2599                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2600                 if (ret < 0)
2601                         return ret;
2602 
2603                 /* Enable the entry */
2604                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2605                                  (1 << (31 - i)), TSU_TEN);
2606         }
2607 
2608         /* Entry found or created, enable POST */
2609         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2610 
2611         return 0;
2612 }
2613 
2614 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2615 {
2616         struct sh_eth_private *mdp = netdev_priv(ndev);
2617         int i, ret;
2618 
2619         if (!mdp->cd->tsu)
2620                 return 0;
2621 
2622         i = sh_eth_tsu_find_entry(ndev, addr);
2623         if (i) {
2624                 /* Entry found */
2625                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2626                         goto done;
2627 
2628                 /* Disable the entry if both ports was disabled */
2629                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2630                 if (ret < 0)
2631                         return ret;
2632         }
2633 done:
2634         return 0;
2635 }
2636 
2637 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2638 {
2639         struct sh_eth_private *mdp = netdev_priv(ndev);
2640         int i, ret;
2641 
2642         if (!mdp->cd->tsu)
2643                 return 0;
2644 
2645         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2646                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2647                         continue;
2648 
2649                 /* Disable the entry if both ports was disabled */
2650                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2651                 if (ret < 0)
2652                         return ret;
2653         }
2654 
2655         return 0;
2656 }
2657 
2658 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2659 {
2660         struct sh_eth_private *mdp = netdev_priv(ndev);
2661         u8 addr[ETH_ALEN];
2662         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2663         int i;
2664 
2665         if (!mdp->cd->tsu)
2666                 return;
2667 
2668         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2669                 sh_eth_tsu_read_entry(reg_offset, addr);
2670                 if (is_multicast_ether_addr(addr))
2671                         sh_eth_tsu_del_entry(ndev, addr);
2672         }
2673 }
2674 
2675 /* Update promiscuous flag and multicast filter */
2676 static void sh_eth_set_rx_mode(struct net_device *ndev)
2677 {
2678         struct sh_eth_private *mdp = netdev_priv(ndev);
2679         u32 ecmr_bits;
2680         int mcast_all = 0;
2681         unsigned long flags;
2682 
2683         spin_lock_irqsave(&mdp->lock, flags);
2684         /* Initial condition is MCT = 1, PRM = 0.
2685          * Depending on ndev->flags, set PRM or clear MCT
2686          */
2687         ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2688         if (mdp->cd->tsu)
2689                 ecmr_bits |= ECMR_MCT;
2690 
2691         if (!(ndev->flags & IFF_MULTICAST)) {
2692                 sh_eth_tsu_purge_mcast(ndev);
2693                 mcast_all = 1;
2694         }
2695         if (ndev->flags & IFF_ALLMULTI) {
2696                 sh_eth_tsu_purge_mcast(ndev);
2697                 ecmr_bits &= ~ECMR_MCT;
2698                 mcast_all = 1;
2699         }
2700 
2701         if (ndev->flags & IFF_PROMISC) {
2702                 sh_eth_tsu_purge_all(ndev);
2703                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2704         } else if (mdp->cd->tsu) {
2705                 struct netdev_hw_addr *ha;
2706                 netdev_for_each_mc_addr(ha, ndev) {
2707                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2708                                 continue;
2709 
2710                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2711                                 if (!mcast_all) {
2712                                         sh_eth_tsu_purge_mcast(ndev);
2713                                         ecmr_bits &= ~ECMR_MCT;
2714                                         mcast_all = 1;
2715                                 }
2716                         }
2717                 }
2718         }
2719 
2720         /* update the ethernet mode */
2721         sh_eth_write(ndev, ecmr_bits, ECMR);
2722 
2723         spin_unlock_irqrestore(&mdp->lock, flags);
2724 }
2725 
2726 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2727 {
2728         if (!mdp->port)
2729                 return TSU_VTAG0;
2730         else
2731                 return TSU_VTAG1;
2732 }
2733 
2734 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2735                                   __be16 proto, u16 vid)
2736 {
2737         struct sh_eth_private *mdp = netdev_priv(ndev);
2738         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2739 
2740         if (unlikely(!mdp->cd->tsu))
2741                 return -EPERM;
2742 
2743         /* No filtering if vid = 0 */
2744         if (!vid)
2745                 return 0;
2746 
2747         mdp->vlan_num_ids++;
2748 
2749         /* The controller has one VLAN tag HW filter. So, if the filter is
2750          * already enabled, the driver disables it and the filte
2751          */
2752         if (mdp->vlan_num_ids > 1) {
2753                 /* disable VLAN filter */
2754                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2755                 return 0;
2756         }
2757 
2758         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2759                          vtag_reg_index);
2760 
2761         return 0;
2762 }
2763 
2764 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2765                                    __be16 proto, u16 vid)
2766 {
2767         struct sh_eth_private *mdp = netdev_priv(ndev);
2768         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2769 
2770         if (unlikely(!mdp->cd->tsu))
2771                 return -EPERM;
2772 
2773         /* No filtering if vid = 0 */
2774         if (!vid)
2775                 return 0;
2776 
2777         mdp->vlan_num_ids--;
2778         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2779 
2780         return 0;
2781 }
2782 
2783 /* SuperH's TSU register init function */
2784 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2785 {
2786         if (sh_eth_is_rz_fast_ether(mdp)) {
2787                 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2788                 return;
2789         }
2790 
2791         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2792         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2793         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2794         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2795         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2796         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2797         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2798         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2799         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2800         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2801         if (sh_eth_is_gether(mdp)) {
2802                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2803                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2804         } else {
2805                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2806                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2807         }
2808         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2809         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2810         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2811         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2812         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2813         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2814         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2815 }
2816 
2817 /* MDIO bus release function */
2818 static int sh_mdio_release(struct sh_eth_private *mdp)
2819 {
2820         /* unregister mdio bus */
2821         mdiobus_unregister(mdp->mii_bus);
2822 
2823         /* free bitbang info */
2824         free_mdio_bitbang(mdp->mii_bus);
2825 
2826         return 0;
2827 }
2828 
2829 /* MDIO bus init function */
2830 static int sh_mdio_init(struct sh_eth_private *mdp,
2831                         struct sh_eth_plat_data *pd)
2832 {
2833         int ret;
2834         struct bb_info *bitbang;
2835         struct platform_device *pdev = mdp->pdev;
2836         struct device *dev = &mdp->pdev->dev;
2837 
2838         /* create bit control struct for PHY */
2839         bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2840         if (!bitbang)
2841                 return -ENOMEM;
2842 
2843         /* bitbang init */
2844         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2845         bitbang->set_gate = pd->set_mdio_gate;
2846         bitbang->ctrl.ops = &bb_ops;
2847 
2848         /* MII controller setting */
2849         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2850         if (!mdp->mii_bus)
2851                 return -ENOMEM;
2852 
2853         /* Hook up MII support for ethtool */
2854         mdp->mii_bus->name = "sh_mii";
2855         mdp->mii_bus->parent = dev;
2856         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2857                  pdev->name, pdev->id);
2858 
2859         /* register MDIO bus */
2860         if (dev->of_node) {
2861                 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2862         } else {
2863                 if (pd->phy_irq > 0)
2864                         mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2865 
2866                 ret = mdiobus_register(mdp->mii_bus);
2867         }
2868 
2869         if (ret)
2870                 goto out_free_bus;
2871 
2872         return 0;
2873 
2874 out_free_bus:
2875         free_mdio_bitbang(mdp->mii_bus);
2876         return ret;
2877 }
2878 
2879 static const u16 *sh_eth_get_register_offset(int register_type)
2880 {
2881         const u16 *reg_offset = NULL;
2882 
2883         switch (register_type) {
2884         case SH_ETH_REG_GIGABIT:
2885                 reg_offset = sh_eth_offset_gigabit;
2886                 break;
2887         case SH_ETH_REG_FAST_RZ:
2888                 reg_offset = sh_eth_offset_fast_rz;
2889                 break;
2890         case SH_ETH_REG_FAST_RCAR:
2891                 reg_offset = sh_eth_offset_fast_rcar;
2892                 break;
2893         case SH_ETH_REG_FAST_SH4:
2894                 reg_offset = sh_eth_offset_fast_sh4;
2895                 break;
2896         case SH_ETH_REG_FAST_SH3_SH2:
2897                 reg_offset = sh_eth_offset_fast_sh3_sh2;
2898                 break;
2899         }
2900 
2901         return reg_offset;
2902 }
2903 
2904 static const struct net_device_ops sh_eth_netdev_ops = {
2905         .ndo_open               = sh_eth_open,
2906         .ndo_stop               = sh_eth_close,
2907         .ndo_start_xmit         = sh_eth_start_xmit,
2908         .ndo_get_stats          = sh_eth_get_stats,
2909         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
2910         .ndo_tx_timeout         = sh_eth_tx_timeout,
2911         .ndo_do_ioctl           = sh_eth_do_ioctl,
2912         .ndo_validate_addr      = eth_validate_addr,
2913         .ndo_set_mac_address    = eth_mac_addr,
2914         .ndo_change_mtu         = eth_change_mtu,
2915 };
2916 
2917 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2918         .ndo_open               = sh_eth_open,
2919         .ndo_stop               = sh_eth_close,
2920         .ndo_start_xmit         = sh_eth_start_xmit,
2921         .ndo_get_stats          = sh_eth_get_stats,
2922         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
2923         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
2924         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
2925         .ndo_tx_timeout         = sh_eth_tx_timeout,
2926         .ndo_do_ioctl           = sh_eth_do_ioctl,
2927         .ndo_validate_addr      = eth_validate_addr,
2928         .ndo_set_mac_address    = eth_mac_addr,
2929         .ndo_change_mtu         = eth_change_mtu,
2930 };
2931 
2932 #ifdef CONFIG_OF
2933 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2934 {
2935         struct device_node *np = dev->of_node;
2936         struct sh_eth_plat_data *pdata;
2937         const char *mac_addr;
2938 
2939         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2940         if (!pdata)
2941                 return NULL;
2942 
2943         pdata->phy_interface = of_get_phy_mode(np);
2944 
2945         mac_addr = of_get_mac_address(np);
2946         if (mac_addr)
2947                 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2948 
2949         pdata->no_ether_link =
2950                 of_property_read_bool(np, "renesas,no-ether-link");
2951         pdata->ether_link_active_low =
2952                 of_property_read_bool(np, "renesas,ether-link-active-low");
2953 
2954         return pdata;
2955 }
2956 
2957 static const struct of_device_id sh_eth_match_table[] = {
2958         { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2959         { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2960         { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2961         { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2962         { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
2963         { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
2964         { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
2965         { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2966         { }
2967 };
2968 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2969 #else
2970 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2971 {
2972         return NULL;
2973 }
2974 #endif
2975 
2976 static int sh_eth_drv_probe(struct platform_device *pdev)
2977 {
2978         struct resource *res;
2979         struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2980         const struct platform_device_id *id = platform_get_device_id(pdev);
2981         struct sh_eth_private *mdp;
2982         struct net_device *ndev;
2983         int ret, devno;
2984 
2985         /* get base addr */
2986         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2987 
2988         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2989         if (!ndev)
2990                 return -ENOMEM;
2991 
2992         pm_runtime_enable(&pdev->dev);
2993         pm_runtime_get_sync(&pdev->dev);
2994 
2995         devno = pdev->id;
2996         if (devno < 0)
2997                 devno = 0;
2998 
2999         ndev->dma = -1;
3000         ret = platform_get_irq(pdev, 0);
3001         if (ret < 0)
3002                 goto out_release;
3003         ndev->irq = ret;
3004 
3005         SET_NETDEV_DEV(ndev, &pdev->dev);
3006 
3007         mdp = netdev_priv(ndev);
3008         mdp->num_tx_ring = TX_RING_SIZE;
3009         mdp->num_rx_ring = RX_RING_SIZE;
3010         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3011         if (IS_ERR(mdp->addr)) {
3012                 ret = PTR_ERR(mdp->addr);
3013                 goto out_release;
3014         }
3015 
3016         ndev->base_addr = res->start;
3017 
3018         spin_lock_init(&mdp->lock);
3019         mdp->pdev = pdev;
3020 
3021         if (pdev->dev.of_node)
3022                 pd = sh_eth_parse_dt(&pdev->dev);
3023         if (!pd) {
3024                 dev_err(&pdev->dev, "no platform data\n");
3025                 ret = -EINVAL;
3026                 goto out_release;
3027         }
3028 
3029         /* get PHY ID */
3030         mdp->phy_id = pd->phy;
3031         mdp->phy_interface = pd->phy_interface;
3032         mdp->no_ether_link = pd->no_ether_link;
3033         mdp->ether_link_active_low = pd->ether_link_active_low;
3034 
3035         /* set cpu data */
3036         if (id)
3037                 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3038         else
3039                 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3040 
3041         mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3042         if (!mdp->reg_offset) {
3043                 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3044                         mdp->cd->register_type);
3045                 ret = -EINVAL;
3046                 goto out_release;
3047         }
3048         sh_eth_set_default_cpu_data(mdp->cd);
3049 
3050         /* set function */
3051         if (mdp->cd->tsu)
3052                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3053         else
3054                 ndev->netdev_ops = &sh_eth_netdev_ops;
3055         ndev->ethtool_ops = &sh_eth_ethtool_ops;
3056         ndev->watchdog_timeo = TX_TIMEOUT;
3057 
3058         /* debug message level */
3059         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3060 
3061         /* read and set MAC address */
3062         read_mac_address(ndev, pd->mac_addr);
3063         if (!is_valid_ether_addr(ndev->dev_addr)) {
3064                 dev_warn(&pdev->dev,
3065                          "no valid MAC address supplied, using a random one.\n");
3066                 eth_hw_addr_random(ndev);
3067         }
3068 
3069         /* ioremap the TSU registers */
3070         if (mdp->cd->tsu) {
3071                 struct resource *rtsu;
3072                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3073                 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3074                 if (IS_ERR(mdp->tsu_addr)) {
3075                         ret = PTR_ERR(mdp->tsu_addr);
3076                         goto out_release;
3077                 }
3078                 mdp->port = devno % 2;
3079                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3080         }
3081 
3082         /* initialize first or needed device */
3083         if (!devno || pd->needs_init) {
3084                 if (mdp->cd->chip_reset)
3085                         mdp->cd->chip_reset(ndev);
3086 
3087                 if (mdp->cd->tsu) {
3088                         /* TSU init (Init only)*/
3089                         sh_eth_tsu_init(mdp);
3090                 }
3091         }
3092 
3093         if (mdp->cd->rmiimode)
3094                 sh_eth_write(ndev, 0x1, RMIIMODE);
3095 
3096         /* MDIO bus init */
3097         ret = sh_mdio_init(mdp, pd);
3098         if (ret) {
3099                 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3100                 goto out_release;
3101         }
3102 
3103         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3104 
3105         /* network device register */
3106         ret = register_netdev(ndev);
3107         if (ret)
3108                 goto out_napi_del;
3109 
3110         /* print device information */
3111         netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3112                     (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3113 
3114         pm_runtime_put(&pdev->dev);
3115         platform_set_drvdata(pdev, ndev);
3116 
3117         return ret;
3118 
3119 out_napi_del:
3120         netif_napi_del(&mdp->napi);
3121         sh_mdio_release(mdp);
3122 
3123 out_release:
3124         /* net_dev free */
3125         if (ndev)
3126                 free_netdev(ndev);
3127 
3128         pm_runtime_put(&pdev->dev);
3129         pm_runtime_disable(&pdev->dev);
3130         return ret;
3131 }
3132 
3133 static int sh_eth_drv_remove(struct platform_device *pdev)
3134 {
3135         struct net_device *ndev = platform_get_drvdata(pdev);
3136         struct sh_eth_private *mdp = netdev_priv(ndev);
3137 
3138         unregister_netdev(ndev);
3139         netif_napi_del(&mdp->napi);
3140         sh_mdio_release(mdp);
3141         pm_runtime_disable(&pdev->dev);
3142         free_netdev(ndev);
3143 
3144         return 0;
3145 }
3146 
3147 #ifdef CONFIG_PM
3148 #ifdef CONFIG_PM_SLEEP
3149 static int sh_eth_suspend(struct device *dev)
3150 {
3151         struct net_device *ndev = dev_get_drvdata(dev);
3152         int ret = 0;
3153 
3154         if (netif_running(ndev)) {
3155                 netif_device_detach(ndev);
3156                 ret = sh_eth_close(ndev);
3157         }
3158 
3159         return ret;
3160 }
3161 
3162 static int sh_eth_resume(struct device *dev)
3163 {
3164         struct net_device *ndev = dev_get_drvdata(dev);
3165         int ret = 0;
3166 
3167         if (netif_running(ndev)) {
3168                 ret = sh_eth_open(ndev);
3169                 if (ret < 0)
3170                         return ret;
3171                 netif_device_attach(ndev);
3172         }
3173 
3174         return ret;
3175 }
3176 #endif
3177 
3178 static int sh_eth_runtime_nop(struct device *dev)
3179 {
3180         /* Runtime PM callback shared between ->runtime_suspend()
3181          * and ->runtime_resume(). Simply returns success.
3182          *
3183          * This driver re-initializes all registers after
3184          * pm_runtime_get_sync() anyway so there is no need
3185          * to save and restore registers here.
3186          */
3187         return 0;
3188 }
3189 
3190 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3191         SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3192         SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3193 };
3194 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3195 #else
3196 #define SH_ETH_PM_OPS NULL
3197 #endif
3198 
3199 static struct platform_device_id sh_eth_id_table[] = {
3200         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3201         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3202         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3203         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3204         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3205         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3206         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3207         { }
3208 };
3209 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3210 
3211 static struct platform_driver sh_eth_driver = {
3212         .probe = sh_eth_drv_probe,
3213         .remove = sh_eth_drv_remove,
3214         .id_table = sh_eth_id_table,
3215         .driver = {
3216                    .name = CARDNAME,
3217                    .pm = SH_ETH_PM_OPS,
3218                    .of_match_table = of_match_ptr(sh_eth_match_table),
3219         },
3220 };
3221 
3222 module_platform_driver(sh_eth_driver);
3223 
3224 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3225 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3226 MODULE_LICENSE("GPL v2");
3227 

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