Version:  2.0.40 2.2.26 2.4.37 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6

Linux/drivers/net/ethernet/nxp/lpc_eth.c

  1 /*
  2  * drivers/net/ethernet/nxp/lpc_eth.c
  3  *
  4  * Author: Kevin Wells <kevin.wells@nxp.com>
  5  *
  6  * Copyright (C) 2010 NXP Semiconductors
  7  * Copyright (C) 2012 Roland Stigge <stigge@antcom.de>
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License as published by
 11  * the Free Software Foundation; either version 2 of the License, or
 12  * (at your option) any later version.
 13  *
 14  * This program is distributed in the hope that it will be useful,
 15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 17  * GNU General Public License for more details.
 18  */
 19 
 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 21 
 22 #include <linux/module.h>
 23 #include <linux/kernel.h>
 24 #include <linux/sched.h>
 25 #include <linux/slab.h>
 26 #include <linux/delay.h>
 27 #include <linux/interrupt.h>
 28 #include <linux/errno.h>
 29 #include <linux/ioport.h>
 30 #include <linux/crc32.h>
 31 #include <linux/platform_device.h>
 32 #include <linux/spinlock.h>
 33 #include <linux/ethtool.h>
 34 #include <linux/mii.h>
 35 #include <linux/clk.h>
 36 #include <linux/workqueue.h>
 37 #include <linux/netdevice.h>
 38 #include <linux/etherdevice.h>
 39 #include <linux/skbuff.h>
 40 #include <linux/phy.h>
 41 #include <linux/dma-mapping.h>
 42 #include <linux/of.h>
 43 #include <linux/of_net.h>
 44 #include <linux/types.h>
 45 
 46 #include <linux/io.h>
 47 #include <mach/board.h>
 48 #include <mach/platform.h>
 49 #include <mach/hardware.h>
 50 
 51 #define MODNAME "lpc-eth"
 52 #define DRV_VERSION "1.00"
 53 
 54 #define ENET_MAXF_SIZE 1536
 55 #define ENET_RX_DESC 48
 56 #define ENET_TX_DESC 16
 57 
 58 #define NAPI_WEIGHT 16
 59 
 60 /*
 61  * Ethernet MAC controller Register offsets
 62  */
 63 #define LPC_ENET_MAC1(x)                        (x + 0x000)
 64 #define LPC_ENET_MAC2(x)                        (x + 0x004)
 65 #define LPC_ENET_IPGT(x)                        (x + 0x008)
 66 #define LPC_ENET_IPGR(x)                        (x + 0x00C)
 67 #define LPC_ENET_CLRT(x)                        (x + 0x010)
 68 #define LPC_ENET_MAXF(x)                        (x + 0x014)
 69 #define LPC_ENET_SUPP(x)                        (x + 0x018)
 70 #define LPC_ENET_TEST(x)                        (x + 0x01C)
 71 #define LPC_ENET_MCFG(x)                        (x + 0x020)
 72 #define LPC_ENET_MCMD(x)                        (x + 0x024)
 73 #define LPC_ENET_MADR(x)                        (x + 0x028)
 74 #define LPC_ENET_MWTD(x)                        (x + 0x02C)
 75 #define LPC_ENET_MRDD(x)                        (x + 0x030)
 76 #define LPC_ENET_MIND(x)                        (x + 0x034)
 77 #define LPC_ENET_SA0(x)                         (x + 0x040)
 78 #define LPC_ENET_SA1(x)                         (x + 0x044)
 79 #define LPC_ENET_SA2(x)                         (x + 0x048)
 80 #define LPC_ENET_COMMAND(x)                     (x + 0x100)
 81 #define LPC_ENET_STATUS(x)                      (x + 0x104)
 82 #define LPC_ENET_RXDESCRIPTOR(x)                (x + 0x108)
 83 #define LPC_ENET_RXSTATUS(x)                    (x + 0x10C)
 84 #define LPC_ENET_RXDESCRIPTORNUMBER(x)          (x + 0x110)
 85 #define LPC_ENET_RXPRODUCEINDEX(x)              (x + 0x114)
 86 #define LPC_ENET_RXCONSUMEINDEX(x)              (x + 0x118)
 87 #define LPC_ENET_TXDESCRIPTOR(x)                (x + 0x11C)
 88 #define LPC_ENET_TXSTATUS(x)                    (x + 0x120)
 89 #define LPC_ENET_TXDESCRIPTORNUMBER(x)          (x + 0x124)
 90 #define LPC_ENET_TXPRODUCEINDEX(x)              (x + 0x128)
 91 #define LPC_ENET_TXCONSUMEINDEX(x)              (x + 0x12C)
 92 #define LPC_ENET_TSV0(x)                        (x + 0x158)
 93 #define LPC_ENET_TSV1(x)                        (x + 0x15C)
 94 #define LPC_ENET_RSV(x)                         (x + 0x160)
 95 #define LPC_ENET_FLOWCONTROLCOUNTER(x)          (x + 0x170)
 96 #define LPC_ENET_FLOWCONTROLSTATUS(x)           (x + 0x174)
 97 #define LPC_ENET_RXFILTER_CTRL(x)               (x + 0x200)
 98 #define LPC_ENET_RXFILTERWOLSTATUS(x)           (x + 0x204)
 99 #define LPC_ENET_RXFILTERWOLCLEAR(x)            (x + 0x208)
100 #define LPC_ENET_HASHFILTERL(x)                 (x + 0x210)
101 #define LPC_ENET_HASHFILTERH(x)                 (x + 0x214)
102 #define LPC_ENET_INTSTATUS(x)                   (x + 0xFE0)
103 #define LPC_ENET_INTENABLE(x)                   (x + 0xFE4)
104 #define LPC_ENET_INTCLEAR(x)                    (x + 0xFE8)
105 #define LPC_ENET_INTSET(x)                      (x + 0xFEC)
106 #define LPC_ENET_POWERDOWN(x)                   (x + 0xFF4)
107 
108 /*
109  * mac1 register definitions
110  */
111 #define LPC_MAC1_RECV_ENABLE                    (1 << 0)
112 #define LPC_MAC1_PASS_ALL_RX_FRAMES             (1 << 1)
113 #define LPC_MAC1_RX_FLOW_CONTROL                (1 << 2)
114 #define LPC_MAC1_TX_FLOW_CONTROL                (1 << 3)
115 #define LPC_MAC1_LOOPBACK                       (1 << 4)
116 #define LPC_MAC1_RESET_TX                       (1 << 8)
117 #define LPC_MAC1_RESET_MCS_TX                   (1 << 9)
118 #define LPC_MAC1_RESET_RX                       (1 << 10)
119 #define LPC_MAC1_RESET_MCS_RX                   (1 << 11)
120 #define LPC_MAC1_SIMULATION_RESET               (1 << 14)
121 #define LPC_MAC1_SOFT_RESET                     (1 << 15)
122 
123 /*
124  * mac2 register definitions
125  */
126 #define LPC_MAC2_FULL_DUPLEX                    (1 << 0)
127 #define LPC_MAC2_FRAME_LENGTH_CHECKING          (1 << 1)
128 #define LPC_MAC2_HUGH_LENGTH_CHECKING           (1 << 2)
129 #define LPC_MAC2_DELAYED_CRC                    (1 << 3)
130 #define LPC_MAC2_CRC_ENABLE                     (1 << 4)
131 #define LPC_MAC2_PAD_CRC_ENABLE                 (1 << 5)
132 #define LPC_MAC2_VLAN_PAD_ENABLE                (1 << 6)
133 #define LPC_MAC2_AUTO_DETECT_PAD_ENABLE         (1 << 7)
134 #define LPC_MAC2_PURE_PREAMBLE_ENFORCEMENT      (1 << 8)
135 #define LPC_MAC2_LONG_PREAMBLE_ENFORCEMENT      (1 << 9)
136 #define LPC_MAC2_NO_BACKOFF                     (1 << 12)
137 #define LPC_MAC2_BACK_PRESSURE                  (1 << 13)
138 #define LPC_MAC2_EXCESS_DEFER                   (1 << 14)
139 
140 /*
141  * ipgt register definitions
142  */
143 #define LPC_IPGT_LOAD(n)                        ((n) & 0x7F)
144 
145 /*
146  * ipgr register definitions
147  */
148 #define LPC_IPGR_LOAD_PART2(n)                  ((n) & 0x7F)
149 #define LPC_IPGR_LOAD_PART1(n)                  (((n) & 0x7F) << 8)
150 
151 /*
152  * clrt register definitions
153  */
154 #define LPC_CLRT_LOAD_RETRY_MAX(n)              ((n) & 0xF)
155 #define LPC_CLRT_LOAD_COLLISION_WINDOW(n)       (((n) & 0x3F) << 8)
156 
157 /*
158  * maxf register definitions
159  */
160 #define LPC_MAXF_LOAD_MAX_FRAME_LEN(n)          ((n) & 0xFFFF)
161 
162 /*
163  * supp register definitions
164  */
165 #define LPC_SUPP_SPEED                          (1 << 8)
166 #define LPC_SUPP_RESET_RMII                     (1 << 11)
167 
168 /*
169  * test register definitions
170  */
171 #define LPC_TEST_SHORTCUT_PAUSE_QUANTA          (1 << 0)
172 #define LPC_TEST_PAUSE                          (1 << 1)
173 #define LPC_TEST_BACKPRESSURE                   (1 << 2)
174 
175 /*
176  * mcfg register definitions
177  */
178 #define LPC_MCFG_SCAN_INCREMENT                 (1 << 0)
179 #define LPC_MCFG_SUPPRESS_PREAMBLE              (1 << 1)
180 #define LPC_MCFG_CLOCK_SELECT(n)                (((n) & 0x7) << 2)
181 #define LPC_MCFG_CLOCK_HOST_DIV_4               0
182 #define LPC_MCFG_CLOCK_HOST_DIV_6               2
183 #define LPC_MCFG_CLOCK_HOST_DIV_8               3
184 #define LPC_MCFG_CLOCK_HOST_DIV_10              4
185 #define LPC_MCFG_CLOCK_HOST_DIV_14              5
186 #define LPC_MCFG_CLOCK_HOST_DIV_20              6
187 #define LPC_MCFG_CLOCK_HOST_DIV_28              7
188 #define LPC_MCFG_RESET_MII_MGMT                 (1 << 15)
189 
190 /*
191  * mcmd register definitions
192  */
193 #define LPC_MCMD_READ                           (1 << 0)
194 #define LPC_MCMD_SCAN                           (1 << 1)
195 
196 /*
197  * madr register definitions
198  */
199 #define LPC_MADR_REGISTER_ADDRESS(n)            ((n) & 0x1F)
200 #define LPC_MADR_PHY_0ADDRESS(n)                (((n) & 0x1F) << 8)
201 
202 /*
203  * mwtd register definitions
204  */
205 #define LPC_MWDT_WRITE(n)                       ((n) & 0xFFFF)
206 
207 /*
208  * mrdd register definitions
209  */
210 #define LPC_MRDD_READ_MASK                      0xFFFF
211 
212 /*
213  * mind register definitions
214  */
215 #define LPC_MIND_BUSY                           (1 << 0)
216 #define LPC_MIND_SCANNING                       (1 << 1)
217 #define LPC_MIND_NOT_VALID                      (1 << 2)
218 #define LPC_MIND_MII_LINK_FAIL                  (1 << 3)
219 
220 /*
221  * command register definitions
222  */
223 #define LPC_COMMAND_RXENABLE                    (1 << 0)
224 #define LPC_COMMAND_TXENABLE                    (1 << 1)
225 #define LPC_COMMAND_REG_RESET                   (1 << 3)
226 #define LPC_COMMAND_TXRESET                     (1 << 4)
227 #define LPC_COMMAND_RXRESET                     (1 << 5)
228 #define LPC_COMMAND_PASSRUNTFRAME               (1 << 6)
229 #define LPC_COMMAND_PASSRXFILTER                (1 << 7)
230 #define LPC_COMMAND_TXFLOWCONTROL               (1 << 8)
231 #define LPC_COMMAND_RMII                        (1 << 9)
232 #define LPC_COMMAND_FULLDUPLEX                  (1 << 10)
233 
234 /*
235  * status register definitions
236  */
237 #define LPC_STATUS_RXACTIVE                     (1 << 0)
238 #define LPC_STATUS_TXACTIVE                     (1 << 1)
239 
240 /*
241  * tsv0 register definitions
242  */
243 #define LPC_TSV0_CRC_ERROR                      (1 << 0)
244 #define LPC_TSV0_LENGTH_CHECK_ERROR             (1 << 1)
245 #define LPC_TSV0_LENGTH_OUT_OF_RANGE            (1 << 2)
246 #define LPC_TSV0_DONE                           (1 << 3)
247 #define LPC_TSV0_MULTICAST                      (1 << 4)
248 #define LPC_TSV0_BROADCAST                      (1 << 5)
249 #define LPC_TSV0_PACKET_DEFER                   (1 << 6)
250 #define LPC_TSV0_ESCESSIVE_DEFER                (1 << 7)
251 #define LPC_TSV0_ESCESSIVE_COLLISION            (1 << 8)
252 #define LPC_TSV0_LATE_COLLISION                 (1 << 9)
253 #define LPC_TSV0_GIANT                          (1 << 10)
254 #define LPC_TSV0_UNDERRUN                       (1 << 11)
255 #define LPC_TSV0_TOTAL_BYTES(n)                 (((n) >> 12) & 0xFFFF)
256 #define LPC_TSV0_CONTROL_FRAME                  (1 << 28)
257 #define LPC_TSV0_PAUSE                          (1 << 29)
258 #define LPC_TSV0_BACKPRESSURE                   (1 << 30)
259 #define LPC_TSV0_VLAN                           (1 << 31)
260 
261 /*
262  * tsv1 register definitions
263  */
264 #define LPC_TSV1_TRANSMIT_BYTE_COUNT(n)         ((n) & 0xFFFF)
265 #define LPC_TSV1_COLLISION_COUNT(n)             (((n) >> 16) & 0xF)
266 
267 /*
268  * rsv register definitions
269  */
270 #define LPC_RSV_RECEIVED_BYTE_COUNT(n)          ((n) & 0xFFFF)
271 #define LPC_RSV_RXDV_EVENT_IGNORED              (1 << 16)
272 #define LPC_RSV_RXDV_EVENT_PREVIOUSLY_SEEN      (1 << 17)
273 #define LPC_RSV_CARRIER_EVNT_PREVIOUS_SEEN      (1 << 18)
274 #define LPC_RSV_RECEIVE_CODE_VIOLATION          (1 << 19)
275 #define LPC_RSV_CRC_ERROR                       (1 << 20)
276 #define LPC_RSV_LENGTH_CHECK_ERROR              (1 << 21)
277 #define LPC_RSV_LENGTH_OUT_OF_RANGE             (1 << 22)
278 #define LPC_RSV_RECEIVE_OK                      (1 << 23)
279 #define LPC_RSV_MULTICAST                       (1 << 24)
280 #define LPC_RSV_BROADCAST                       (1 << 25)
281 #define LPC_RSV_DRIBBLE_NIBBLE                  (1 << 26)
282 #define LPC_RSV_CONTROL_FRAME                   (1 << 27)
283 #define LPC_RSV_PAUSE                           (1 << 28)
284 #define LPC_RSV_UNSUPPORTED_OPCODE              (1 << 29)
285 #define LPC_RSV_VLAN                            (1 << 30)
286 
287 /*
288  * flowcontrolcounter register definitions
289  */
290 #define LPC_FCCR_MIRRORCOUNTER(n)               ((n) & 0xFFFF)
291 #define LPC_FCCR_PAUSETIMER(n)                  (((n) >> 16) & 0xFFFF)
292 
293 /*
294  * flowcontrolstatus register definitions
295  */
296 #define LPC_FCCR_MIRRORCOUNTERCURRENT(n)        ((n) & 0xFFFF)
297 
298 /*
299  * rxfliterctrl, rxfilterwolstatus, and rxfilterwolclear shared
300  * register definitions
301  */
302 #define LPC_RXFLTRW_ACCEPTUNICAST               (1 << 0)
303 #define LPC_RXFLTRW_ACCEPTUBROADCAST            (1 << 1)
304 #define LPC_RXFLTRW_ACCEPTUMULTICAST            (1 << 2)
305 #define LPC_RXFLTRW_ACCEPTUNICASTHASH           (1 << 3)
306 #define LPC_RXFLTRW_ACCEPTUMULTICASTHASH        (1 << 4)
307 #define LPC_RXFLTRW_ACCEPTPERFECT               (1 << 5)
308 
309 /*
310  * rxfliterctrl register definitions
311  */
312 #define LPC_RXFLTRWSTS_MAGICPACKETENWOL         (1 << 12)
313 #define LPC_RXFLTRWSTS_RXFILTERENWOL            (1 << 13)
314 
315 /*
316  * rxfilterwolstatus/rxfilterwolclear register definitions
317  */
318 #define LPC_RXFLTRWSTS_RXFILTERWOL              (1 << 7)
319 #define LPC_RXFLTRWSTS_MAGICPACKETWOL           (1 << 8)
320 
321 /*
322  * intstatus, intenable, intclear, and Intset shared register
323  * definitions
324  */
325 #define LPC_MACINT_RXOVERRUNINTEN               (1 << 0)
326 #define LPC_MACINT_RXERRORONINT                 (1 << 1)
327 #define LPC_MACINT_RXFINISHEDINTEN              (1 << 2)
328 #define LPC_MACINT_RXDONEINTEN                  (1 << 3)
329 #define LPC_MACINT_TXUNDERRUNINTEN              (1 << 4)
330 #define LPC_MACINT_TXERRORINTEN                 (1 << 5)
331 #define LPC_MACINT_TXFINISHEDINTEN              (1 << 6)
332 #define LPC_MACINT_TXDONEINTEN                  (1 << 7)
333 #define LPC_MACINT_SOFTINTEN                    (1 << 12)
334 #define LPC_MACINT_WAKEUPINTEN                  (1 << 13)
335 
336 /*
337  * powerdown register definitions
338  */
339 #define LPC_POWERDOWN_MACAHB                    (1 << 31)
340 
341 static phy_interface_t lpc_phy_interface_mode(struct device *dev)
342 {
343         if (dev && dev->of_node) {
344                 const char *mode = of_get_property(dev->of_node,
345                                                    "phy-mode", NULL);
346                 if (mode && !strcmp(mode, "mii"))
347                         return PHY_INTERFACE_MODE_MII;
348         }
349         return PHY_INTERFACE_MODE_RMII;
350 }
351 
352 static bool use_iram_for_net(struct device *dev)
353 {
354         if (dev && dev->of_node)
355                 return of_property_read_bool(dev->of_node, "use-iram");
356         return false;
357 }
358 
359 /* Receive Status information word */
360 #define RXSTATUS_SIZE                   0x000007FF
361 #define RXSTATUS_CONTROL                (1 << 18)
362 #define RXSTATUS_VLAN                   (1 << 19)
363 #define RXSTATUS_FILTER                 (1 << 20)
364 #define RXSTATUS_MULTICAST              (1 << 21)
365 #define RXSTATUS_BROADCAST              (1 << 22)
366 #define RXSTATUS_CRC                    (1 << 23)
367 #define RXSTATUS_SYMBOL                 (1 << 24)
368 #define RXSTATUS_LENGTH                 (1 << 25)
369 #define RXSTATUS_RANGE                  (1 << 26)
370 #define RXSTATUS_ALIGN                  (1 << 27)
371 #define RXSTATUS_OVERRUN                (1 << 28)
372 #define RXSTATUS_NODESC                 (1 << 29)
373 #define RXSTATUS_LAST                   (1 << 30)
374 #define RXSTATUS_ERROR                  (1 << 31)
375 
376 #define RXSTATUS_STATUS_ERROR \
377         (RXSTATUS_NODESC | RXSTATUS_OVERRUN | RXSTATUS_ALIGN | \
378          RXSTATUS_RANGE | RXSTATUS_LENGTH | RXSTATUS_SYMBOL | RXSTATUS_CRC)
379 
380 /* Receive Descriptor control word */
381 #define RXDESC_CONTROL_SIZE             0x000007FF
382 #define RXDESC_CONTROL_INT              (1 << 31)
383 
384 /* Transmit Status information word */
385 #define TXSTATUS_COLLISIONS_GET(x)      (((x) >> 21) & 0xF)
386 #define TXSTATUS_DEFER                  (1 << 25)
387 #define TXSTATUS_EXCESSDEFER            (1 << 26)
388 #define TXSTATUS_EXCESSCOLL             (1 << 27)
389 #define TXSTATUS_LATECOLL               (1 << 28)
390 #define TXSTATUS_UNDERRUN               (1 << 29)
391 #define TXSTATUS_NODESC                 (1 << 30)
392 #define TXSTATUS_ERROR                  (1 << 31)
393 
394 /* Transmit Descriptor control word */
395 #define TXDESC_CONTROL_SIZE             0x000007FF
396 #define TXDESC_CONTROL_OVERRIDE         (1 << 26)
397 #define TXDESC_CONTROL_HUGE             (1 << 27)
398 #define TXDESC_CONTROL_PAD              (1 << 28)
399 #define TXDESC_CONTROL_CRC              (1 << 29)
400 #define TXDESC_CONTROL_LAST             (1 << 30)
401 #define TXDESC_CONTROL_INT              (1 << 31)
402 
403 /*
404  * Structure of a TX/RX descriptors and RX status
405  */
406 struct txrx_desc_t {
407         __le32 packet;
408         __le32 control;
409 };
410 struct rx_status_t {
411         __le32 statusinfo;
412         __le32 statushashcrc;
413 };
414 
415 /*
416  * Device driver data structure
417  */
418 struct netdata_local {
419         struct platform_device  *pdev;
420         struct net_device       *ndev;
421         spinlock_t              lock;
422         void __iomem            *net_base;
423         u32                     msg_enable;
424         unsigned int            skblen[ENET_TX_DESC];
425         unsigned int            last_tx_idx;
426         unsigned int            num_used_tx_buffs;
427         struct mii_bus          *mii_bus;
428         struct phy_device       *phy_dev;
429         struct clk              *clk;
430         dma_addr_t              dma_buff_base_p;
431         void                    *dma_buff_base_v;
432         size_t                  dma_buff_size;
433         struct txrx_desc_t      *tx_desc_v;
434         u32                     *tx_stat_v;
435         void                    *tx_buff_v;
436         struct txrx_desc_t      *rx_desc_v;
437         struct rx_status_t      *rx_stat_v;
438         void                    *rx_buff_v;
439         int                     link;
440         int                     speed;
441         int                     duplex;
442         struct napi_struct      napi;
443 };
444 
445 /*
446  * MAC support functions
447  */
448 static void __lpc_set_mac(struct netdata_local *pldat, u8 *mac)
449 {
450         u32 tmp;
451 
452         /* Set station address */
453         tmp = mac[0] | ((u32)mac[1] << 8);
454         writel(tmp, LPC_ENET_SA2(pldat->net_base));
455         tmp = mac[2] | ((u32)mac[3] << 8);
456         writel(tmp, LPC_ENET_SA1(pldat->net_base));
457         tmp = mac[4] | ((u32)mac[5] << 8);
458         writel(tmp, LPC_ENET_SA0(pldat->net_base));
459 
460         netdev_dbg(pldat->ndev, "Ethernet MAC address %pM\n", mac);
461 }
462 
463 static void __lpc_get_mac(struct netdata_local *pldat, u8 *mac)
464 {
465         u32 tmp;
466 
467         /* Get station address */
468         tmp = readl(LPC_ENET_SA2(pldat->net_base));
469         mac[0] = tmp & 0xFF;
470         mac[1] = tmp >> 8;
471         tmp = readl(LPC_ENET_SA1(pldat->net_base));
472         mac[2] = tmp & 0xFF;
473         mac[3] = tmp >> 8;
474         tmp = readl(LPC_ENET_SA0(pldat->net_base));
475         mac[4] = tmp & 0xFF;
476         mac[5] = tmp >> 8;
477 }
478 
479 static void __lpc_eth_clock_enable(struct netdata_local *pldat, bool enable)
480 {
481         if (enable)
482                 clk_prepare_enable(pldat->clk);
483         else
484                 clk_disable_unprepare(pldat->clk);
485 }
486 
487 static void __lpc_params_setup(struct netdata_local *pldat)
488 {
489         u32 tmp;
490 
491         if (pldat->duplex == DUPLEX_FULL) {
492                 tmp = readl(LPC_ENET_MAC2(pldat->net_base));
493                 tmp |= LPC_MAC2_FULL_DUPLEX;
494                 writel(tmp, LPC_ENET_MAC2(pldat->net_base));
495                 tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
496                 tmp |= LPC_COMMAND_FULLDUPLEX;
497                 writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
498                 writel(LPC_IPGT_LOAD(0x15), LPC_ENET_IPGT(pldat->net_base));
499         } else {
500                 tmp = readl(LPC_ENET_MAC2(pldat->net_base));
501                 tmp &= ~LPC_MAC2_FULL_DUPLEX;
502                 writel(tmp, LPC_ENET_MAC2(pldat->net_base));
503                 tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
504                 tmp &= ~LPC_COMMAND_FULLDUPLEX;
505                 writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
506                 writel(LPC_IPGT_LOAD(0x12), LPC_ENET_IPGT(pldat->net_base));
507         }
508 
509         if (pldat->speed == SPEED_100)
510                 writel(LPC_SUPP_SPEED, LPC_ENET_SUPP(pldat->net_base));
511         else
512                 writel(0, LPC_ENET_SUPP(pldat->net_base));
513 }
514 
515 static void __lpc_eth_reset(struct netdata_local *pldat)
516 {
517         /* Reset all MAC logic */
518         writel((LPC_MAC1_RESET_TX | LPC_MAC1_RESET_MCS_TX | LPC_MAC1_RESET_RX |
519                 LPC_MAC1_RESET_MCS_RX | LPC_MAC1_SIMULATION_RESET |
520                 LPC_MAC1_SOFT_RESET), LPC_ENET_MAC1(pldat->net_base));
521         writel((LPC_COMMAND_REG_RESET | LPC_COMMAND_TXRESET |
522                 LPC_COMMAND_RXRESET), LPC_ENET_COMMAND(pldat->net_base));
523 }
524 
525 static int __lpc_mii_mngt_reset(struct netdata_local *pldat)
526 {
527         /* Reset MII management hardware */
528         writel(LPC_MCFG_RESET_MII_MGMT, LPC_ENET_MCFG(pldat->net_base));
529 
530         /* Setup MII clock to slowest rate with a /28 divider */
531         writel(LPC_MCFG_CLOCK_SELECT(LPC_MCFG_CLOCK_HOST_DIV_28),
532                LPC_ENET_MCFG(pldat->net_base));
533 
534         return 0;
535 }
536 
537 static inline phys_addr_t __va_to_pa(void *addr, struct netdata_local *pldat)
538 {
539         phys_addr_t phaddr;
540 
541         phaddr = addr - pldat->dma_buff_base_v;
542         phaddr += pldat->dma_buff_base_p;
543 
544         return phaddr;
545 }
546 
547 static void lpc_eth_enable_int(void __iomem *regbase)
548 {
549         writel((LPC_MACINT_RXDONEINTEN | LPC_MACINT_TXDONEINTEN),
550                LPC_ENET_INTENABLE(regbase));
551 }
552 
553 static void lpc_eth_disable_int(void __iomem *regbase)
554 {
555         writel(0, LPC_ENET_INTENABLE(regbase));
556 }
557 
558 /* Setup TX/RX descriptors */
559 static void __lpc_txrx_desc_setup(struct netdata_local *pldat)
560 {
561         u32 *ptxstat;
562         void *tbuff;
563         int i;
564         struct txrx_desc_t *ptxrxdesc;
565         struct rx_status_t *prxstat;
566 
567         tbuff = PTR_ALIGN(pldat->dma_buff_base_v, 16);
568 
569         /* Setup TX descriptors, status, and buffers */
570         pldat->tx_desc_v = tbuff;
571         tbuff += sizeof(struct txrx_desc_t) * ENET_TX_DESC;
572 
573         pldat->tx_stat_v = tbuff;
574         tbuff += sizeof(u32) * ENET_TX_DESC;
575 
576         tbuff = PTR_ALIGN(tbuff, 16);
577         pldat->tx_buff_v = tbuff;
578         tbuff += ENET_MAXF_SIZE * ENET_TX_DESC;
579 
580         /* Setup RX descriptors, status, and buffers */
581         pldat->rx_desc_v = tbuff;
582         tbuff += sizeof(struct txrx_desc_t) * ENET_RX_DESC;
583 
584         tbuff = PTR_ALIGN(tbuff, 16);
585         pldat->rx_stat_v = tbuff;
586         tbuff += sizeof(struct rx_status_t) * ENET_RX_DESC;
587 
588         tbuff = PTR_ALIGN(tbuff, 16);
589         pldat->rx_buff_v = tbuff;
590         tbuff += ENET_MAXF_SIZE * ENET_RX_DESC;
591 
592         /* Map the TX descriptors to the TX buffers in hardware */
593         for (i = 0; i < ENET_TX_DESC; i++) {
594                 ptxstat = &pldat->tx_stat_v[i];
595                 ptxrxdesc = &pldat->tx_desc_v[i];
596 
597                 ptxrxdesc->packet = __va_to_pa(
598                                 pldat->tx_buff_v + i * ENET_MAXF_SIZE, pldat);
599                 ptxrxdesc->control = 0;
600                 *ptxstat = 0;
601         }
602 
603         /* Map the RX descriptors to the RX buffers in hardware */
604         for (i = 0; i < ENET_RX_DESC; i++) {
605                 prxstat = &pldat->rx_stat_v[i];
606                 ptxrxdesc = &pldat->rx_desc_v[i];
607 
608                 ptxrxdesc->packet = __va_to_pa(
609                                 pldat->rx_buff_v + i * ENET_MAXF_SIZE, pldat);
610                 ptxrxdesc->control = RXDESC_CONTROL_INT | (ENET_MAXF_SIZE - 1);
611                 prxstat->statusinfo = 0;
612                 prxstat->statushashcrc = 0;
613         }
614 
615         /* Setup base addresses in hardware to point to buffers and
616          * descriptors
617          */
618         writel((ENET_TX_DESC - 1),
619                LPC_ENET_TXDESCRIPTORNUMBER(pldat->net_base));
620         writel(__va_to_pa(pldat->tx_desc_v, pldat),
621                LPC_ENET_TXDESCRIPTOR(pldat->net_base));
622         writel(__va_to_pa(pldat->tx_stat_v, pldat),
623                LPC_ENET_TXSTATUS(pldat->net_base));
624         writel((ENET_RX_DESC - 1),
625                LPC_ENET_RXDESCRIPTORNUMBER(pldat->net_base));
626         writel(__va_to_pa(pldat->rx_desc_v, pldat),
627                LPC_ENET_RXDESCRIPTOR(pldat->net_base));
628         writel(__va_to_pa(pldat->rx_stat_v, pldat),
629                LPC_ENET_RXSTATUS(pldat->net_base));
630 }
631 
632 static void __lpc_eth_init(struct netdata_local *pldat)
633 {
634         u32 tmp;
635 
636         /* Disable controller and reset */
637         tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
638         tmp &= ~LPC_COMMAND_RXENABLE | LPC_COMMAND_TXENABLE;
639         writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
640         tmp = readl(LPC_ENET_MAC1(pldat->net_base));
641         tmp &= ~LPC_MAC1_RECV_ENABLE;
642         writel(tmp, LPC_ENET_MAC1(pldat->net_base));
643 
644         /* Initial MAC setup */
645         writel(LPC_MAC1_PASS_ALL_RX_FRAMES, LPC_ENET_MAC1(pldat->net_base));
646         writel((LPC_MAC2_PAD_CRC_ENABLE | LPC_MAC2_CRC_ENABLE),
647                LPC_ENET_MAC2(pldat->net_base));
648         writel(ENET_MAXF_SIZE, LPC_ENET_MAXF(pldat->net_base));
649 
650         /* Collision window, gap */
651         writel((LPC_CLRT_LOAD_RETRY_MAX(0xF) |
652                 LPC_CLRT_LOAD_COLLISION_WINDOW(0x37)),
653                LPC_ENET_CLRT(pldat->net_base));
654         writel(LPC_IPGR_LOAD_PART2(0x12), LPC_ENET_IPGR(pldat->net_base));
655 
656         if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII)
657                 writel(LPC_COMMAND_PASSRUNTFRAME,
658                        LPC_ENET_COMMAND(pldat->net_base));
659         else {
660                 writel((LPC_COMMAND_PASSRUNTFRAME | LPC_COMMAND_RMII),
661                        LPC_ENET_COMMAND(pldat->net_base));
662                 writel(LPC_SUPP_RESET_RMII, LPC_ENET_SUPP(pldat->net_base));
663         }
664 
665         __lpc_params_setup(pldat);
666 
667         /* Setup TX and RX descriptors */
668         __lpc_txrx_desc_setup(pldat);
669 
670         /* Setup packet filtering */
671         writel((LPC_RXFLTRW_ACCEPTUBROADCAST | LPC_RXFLTRW_ACCEPTPERFECT),
672                LPC_ENET_RXFILTER_CTRL(pldat->net_base));
673 
674         /* Get the next TX buffer output index */
675         pldat->num_used_tx_buffs = 0;
676         pldat->last_tx_idx =
677                 readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));
678 
679         /* Clear and enable interrupts */
680         writel(0xFFFF, LPC_ENET_INTCLEAR(pldat->net_base));
681         smp_wmb();
682         lpc_eth_enable_int(pldat->net_base);
683 
684         /* Enable controller */
685         tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
686         tmp |= LPC_COMMAND_RXENABLE | LPC_COMMAND_TXENABLE;
687         writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
688         tmp = readl(LPC_ENET_MAC1(pldat->net_base));
689         tmp |= LPC_MAC1_RECV_ENABLE;
690         writel(tmp, LPC_ENET_MAC1(pldat->net_base));
691 }
692 
693 static void __lpc_eth_shutdown(struct netdata_local *pldat)
694 {
695         /* Reset ethernet and power down PHY */
696         __lpc_eth_reset(pldat);
697         writel(0, LPC_ENET_MAC1(pldat->net_base));
698         writel(0, LPC_ENET_MAC2(pldat->net_base));
699 }
700 
701 /*
702  * MAC<--->PHY support functions
703  */
704 static int lpc_mdio_read(struct mii_bus *bus, int phy_id, int phyreg)
705 {
706         struct netdata_local *pldat = bus->priv;
707         unsigned long timeout = jiffies + msecs_to_jiffies(100);
708         int lps;
709 
710         writel(((phy_id << 8) | phyreg), LPC_ENET_MADR(pldat->net_base));
711         writel(LPC_MCMD_READ, LPC_ENET_MCMD(pldat->net_base));
712 
713         /* Wait for unbusy status */
714         while (readl(LPC_ENET_MIND(pldat->net_base)) & LPC_MIND_BUSY) {
715                 if (time_after(jiffies, timeout))
716                         return -EIO;
717                 cpu_relax();
718         }
719 
720         lps = readl(LPC_ENET_MRDD(pldat->net_base));
721         writel(0, LPC_ENET_MCMD(pldat->net_base));
722 
723         return lps;
724 }
725 
726 static int lpc_mdio_write(struct mii_bus *bus, int phy_id, int phyreg,
727                         u16 phydata)
728 {
729         struct netdata_local *pldat = bus->priv;
730         unsigned long timeout = jiffies + msecs_to_jiffies(100);
731 
732         writel(((phy_id << 8) | phyreg), LPC_ENET_MADR(pldat->net_base));
733         writel(phydata, LPC_ENET_MWTD(pldat->net_base));
734 
735         /* Wait for completion */
736         while (readl(LPC_ENET_MIND(pldat->net_base)) & LPC_MIND_BUSY) {
737                 if (time_after(jiffies, timeout))
738                         return -EIO;
739                 cpu_relax();
740         }
741 
742         return 0;
743 }
744 
745 static int lpc_mdio_reset(struct mii_bus *bus)
746 {
747         return __lpc_mii_mngt_reset((struct netdata_local *)bus->priv);
748 }
749 
750 static void lpc_handle_link_change(struct net_device *ndev)
751 {
752         struct netdata_local *pldat = netdev_priv(ndev);
753         struct phy_device *phydev = pldat->phy_dev;
754         unsigned long flags;
755 
756         bool status_change = false;
757 
758         spin_lock_irqsave(&pldat->lock, flags);
759 
760         if (phydev->link) {
761                 if ((pldat->speed != phydev->speed) ||
762                     (pldat->duplex != phydev->duplex)) {
763                         pldat->speed = phydev->speed;
764                         pldat->duplex = phydev->duplex;
765                         status_change = true;
766                 }
767         }
768 
769         if (phydev->link != pldat->link) {
770                 if (!phydev->link) {
771                         pldat->speed = 0;
772                         pldat->duplex = -1;
773                 }
774                 pldat->link = phydev->link;
775 
776                 status_change = true;
777         }
778 
779         spin_unlock_irqrestore(&pldat->lock, flags);
780 
781         if (status_change)
782                 __lpc_params_setup(pldat);
783 }
784 
785 static int lpc_mii_probe(struct net_device *ndev)
786 {
787         struct netdata_local *pldat = netdev_priv(ndev);
788         struct phy_device *phydev = phy_find_first(pldat->mii_bus);
789 
790         if (!phydev) {
791                 netdev_err(ndev, "no PHY found\n");
792                 return -ENODEV;
793         }
794 
795         /* Attach to the PHY */
796         if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII)
797                 netdev_info(ndev, "using MII interface\n");
798         else
799                 netdev_info(ndev, "using RMII interface\n");
800         phydev = phy_connect(ndev, phydev_name(phydev),
801                              &lpc_handle_link_change,
802                              lpc_phy_interface_mode(&pldat->pdev->dev));
803 
804         if (IS_ERR(phydev)) {
805                 netdev_err(ndev, "Could not attach to PHY\n");
806                 return PTR_ERR(phydev);
807         }
808 
809         /* mask with MAC supported features */
810         phydev->supported &= PHY_BASIC_FEATURES;
811 
812         phydev->advertising = phydev->supported;
813 
814         pldat->link = 0;
815         pldat->speed = 0;
816         pldat->duplex = -1;
817         pldat->phy_dev = phydev;
818 
819         phy_attached_info(phydev);
820 
821         return 0;
822 }
823 
824 static int lpc_mii_init(struct netdata_local *pldat)
825 {
826         int err = -ENXIO;
827 
828         pldat->mii_bus = mdiobus_alloc();
829         if (!pldat->mii_bus) {
830                 err = -ENOMEM;
831                 goto err_out;
832         }
833 
834         /* Setup MII mode */
835         if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII)
836                 writel(LPC_COMMAND_PASSRUNTFRAME,
837                        LPC_ENET_COMMAND(pldat->net_base));
838         else {
839                 writel((LPC_COMMAND_PASSRUNTFRAME | LPC_COMMAND_RMII),
840                        LPC_ENET_COMMAND(pldat->net_base));
841                 writel(LPC_SUPP_RESET_RMII, LPC_ENET_SUPP(pldat->net_base));
842         }
843 
844         pldat->mii_bus->name = "lpc_mii_bus";
845         pldat->mii_bus->read = &lpc_mdio_read;
846         pldat->mii_bus->write = &lpc_mdio_write;
847         pldat->mii_bus->reset = &lpc_mdio_reset;
848         snprintf(pldat->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
849                  pldat->pdev->name, pldat->pdev->id);
850         pldat->mii_bus->priv = pldat;
851         pldat->mii_bus->parent = &pldat->pdev->dev;
852 
853         platform_set_drvdata(pldat->pdev, pldat->mii_bus);
854 
855         if (mdiobus_register(pldat->mii_bus))
856                 goto err_out_unregister_bus;
857 
858         if (lpc_mii_probe(pldat->ndev) != 0)
859                 goto err_out_unregister_bus;
860 
861         return 0;
862 
863 err_out_unregister_bus:
864         mdiobus_unregister(pldat->mii_bus);
865         mdiobus_free(pldat->mii_bus);
866 err_out:
867         return err;
868 }
869 
870 static void __lpc_handle_xmit(struct net_device *ndev)
871 {
872         struct netdata_local *pldat = netdev_priv(ndev);
873         u32 txcidx, *ptxstat, txstat;
874 
875         txcidx = readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));
876         while (pldat->last_tx_idx != txcidx) {
877                 unsigned int skblen = pldat->skblen[pldat->last_tx_idx];
878 
879                 /* A buffer is available, get buffer status */
880                 ptxstat = &pldat->tx_stat_v[pldat->last_tx_idx];
881                 txstat = *ptxstat;
882 
883                 /* Next buffer and decrement used buffer counter */
884                 pldat->num_used_tx_buffs--;
885                 pldat->last_tx_idx++;
886                 if (pldat->last_tx_idx >= ENET_TX_DESC)
887                         pldat->last_tx_idx = 0;
888 
889                 /* Update collision counter */
890                 ndev->stats.collisions += TXSTATUS_COLLISIONS_GET(txstat);
891 
892                 /* Any errors occurred? */
893                 if (txstat & TXSTATUS_ERROR) {
894                         if (txstat & TXSTATUS_UNDERRUN) {
895                                 /* FIFO underrun */
896                                 ndev->stats.tx_fifo_errors++;
897                         }
898                         if (txstat & TXSTATUS_LATECOLL) {
899                                 /* Late collision */
900                                 ndev->stats.tx_aborted_errors++;
901                         }
902                         if (txstat & TXSTATUS_EXCESSCOLL) {
903                                 /* Excessive collision */
904                                 ndev->stats.tx_aborted_errors++;
905                         }
906                         if (txstat & TXSTATUS_EXCESSDEFER) {
907                                 /* Defer limit */
908                                 ndev->stats.tx_aborted_errors++;
909                         }
910                         ndev->stats.tx_errors++;
911                 } else {
912                         /* Update stats */
913                         ndev->stats.tx_packets++;
914                         ndev->stats.tx_bytes += skblen;
915                 }
916 
917                 txcidx = readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));
918         }
919 
920         if (pldat->num_used_tx_buffs <= ENET_TX_DESC/2) {
921                 if (netif_queue_stopped(ndev))
922                         netif_wake_queue(ndev);
923         }
924 }
925 
926 static int __lpc_handle_recv(struct net_device *ndev, int budget)
927 {
928         struct netdata_local *pldat = netdev_priv(ndev);
929         struct sk_buff *skb;
930         u32 rxconsidx, len, ethst;
931         struct rx_status_t *prxstat;
932         u8 *prdbuf;
933         int rx_done = 0;
934 
935         /* Get the current RX buffer indexes */
936         rxconsidx = readl(LPC_ENET_RXCONSUMEINDEX(pldat->net_base));
937         while (rx_done < budget && rxconsidx !=
938                         readl(LPC_ENET_RXPRODUCEINDEX(pldat->net_base))) {
939                 /* Get pointer to receive status */
940                 prxstat = &pldat->rx_stat_v[rxconsidx];
941                 len = (prxstat->statusinfo & RXSTATUS_SIZE) + 1;
942 
943                 /* Status error? */
944                 ethst = prxstat->statusinfo;
945                 if ((ethst & (RXSTATUS_ERROR | RXSTATUS_STATUS_ERROR)) ==
946                     (RXSTATUS_ERROR | RXSTATUS_RANGE))
947                         ethst &= ~RXSTATUS_ERROR;
948 
949                 if (ethst & RXSTATUS_ERROR) {
950                         int si = prxstat->statusinfo;
951                         /* Check statuses */
952                         if (si & RXSTATUS_OVERRUN) {
953                                 /* Overrun error */
954                                 ndev->stats.rx_fifo_errors++;
955                         } else if (si & RXSTATUS_CRC) {
956                                 /* CRC error */
957                                 ndev->stats.rx_crc_errors++;
958                         } else if (si & RXSTATUS_LENGTH) {
959                                 /* Length error */
960                                 ndev->stats.rx_length_errors++;
961                         } else if (si & RXSTATUS_ERROR) {
962                                 /* Other error */
963                                 ndev->stats.rx_length_errors++;
964                         }
965                         ndev->stats.rx_errors++;
966                 } else {
967                         /* Packet is good */
968                         skb = dev_alloc_skb(len);
969                         if (!skb) {
970                                 ndev->stats.rx_dropped++;
971                         } else {
972                                 prdbuf = skb_put(skb, len);
973 
974                                 /* Copy packet from buffer */
975                                 memcpy(prdbuf, pldat->rx_buff_v +
976                                         rxconsidx * ENET_MAXF_SIZE, len);
977 
978                                 /* Pass to upper layer */
979                                 skb->protocol = eth_type_trans(skb, ndev);
980                                 netif_receive_skb(skb);
981                                 ndev->stats.rx_packets++;
982                                 ndev->stats.rx_bytes += len;
983                         }
984                 }
985 
986                 /* Increment consume index */
987                 rxconsidx = rxconsidx + 1;
988                 if (rxconsidx >= ENET_RX_DESC)
989                         rxconsidx = 0;
990                 writel(rxconsidx,
991                        LPC_ENET_RXCONSUMEINDEX(pldat->net_base));
992                 rx_done++;
993         }
994 
995         return rx_done;
996 }
997 
998 static int lpc_eth_poll(struct napi_struct *napi, int budget)
999 {
1000         struct netdata_local *pldat = container_of(napi,
1001                         struct netdata_local, napi);
1002         struct net_device *ndev = pldat->ndev;
1003         int rx_done = 0;
1004         struct netdev_queue *txq = netdev_get_tx_queue(ndev, 0);
1005 
1006         __netif_tx_lock(txq, smp_processor_id());
1007         __lpc_handle_xmit(ndev);
1008         __netif_tx_unlock(txq);
1009         rx_done = __lpc_handle_recv(ndev, budget);
1010 
1011         if (rx_done < budget) {
1012                 napi_complete(napi);
1013                 lpc_eth_enable_int(pldat->net_base);
1014         }
1015 
1016         return rx_done;
1017 }
1018 
1019 static irqreturn_t __lpc_eth_interrupt(int irq, void *dev_id)
1020 {
1021         struct net_device *ndev = dev_id;
1022         struct netdata_local *pldat = netdev_priv(ndev);
1023         u32 tmp;
1024 
1025         spin_lock(&pldat->lock);
1026 
1027         tmp = readl(LPC_ENET_INTSTATUS(pldat->net_base));
1028         /* Clear interrupts */
1029         writel(tmp, LPC_ENET_INTCLEAR(pldat->net_base));
1030 
1031         lpc_eth_disable_int(pldat->net_base);
1032         if (likely(napi_schedule_prep(&pldat->napi)))
1033                 __napi_schedule(&pldat->napi);
1034 
1035         spin_unlock(&pldat->lock);
1036 
1037         return IRQ_HANDLED;
1038 }
1039 
1040 static int lpc_eth_close(struct net_device *ndev)
1041 {
1042         unsigned long flags;
1043         struct netdata_local *pldat = netdev_priv(ndev);
1044 
1045         if (netif_msg_ifdown(pldat))
1046                 dev_dbg(&pldat->pdev->dev, "shutting down %s\n", ndev->name);
1047 
1048         napi_disable(&pldat->napi);
1049         netif_stop_queue(ndev);
1050 
1051         if (pldat->phy_dev)
1052                 phy_stop(pldat->phy_dev);
1053 
1054         spin_lock_irqsave(&pldat->lock, flags);
1055         __lpc_eth_reset(pldat);
1056         netif_carrier_off(ndev);
1057         writel(0, LPC_ENET_MAC1(pldat->net_base));
1058         writel(0, LPC_ENET_MAC2(pldat->net_base));
1059         spin_unlock_irqrestore(&pldat->lock, flags);
1060 
1061         __lpc_eth_clock_enable(pldat, false);
1062 
1063         return 0;
1064 }
1065 
1066 static int lpc_eth_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1067 {
1068         struct netdata_local *pldat = netdev_priv(ndev);
1069         u32 len, txidx;
1070         u32 *ptxstat;
1071         struct txrx_desc_t *ptxrxdesc;
1072 
1073         len = skb->len;
1074 
1075         spin_lock_irq(&pldat->lock);
1076 
1077         if (pldat->num_used_tx_buffs >= (ENET_TX_DESC - 1)) {
1078                 /* This function should never be called when there are no
1079                    buffers */
1080                 netif_stop_queue(ndev);
1081                 spin_unlock_irq(&pldat->lock);
1082                 WARN(1, "BUG! TX request when no free TX buffers!\n");
1083                 return NETDEV_TX_BUSY;
1084         }
1085 
1086         /* Get the next TX descriptor index */
1087         txidx = readl(LPC_ENET_TXPRODUCEINDEX(pldat->net_base));
1088 
1089         /* Setup control for the transfer */
1090         ptxstat = &pldat->tx_stat_v[txidx];
1091         *ptxstat = 0;
1092         ptxrxdesc = &pldat->tx_desc_v[txidx];
1093         ptxrxdesc->control =
1094                 (len - 1) | TXDESC_CONTROL_LAST | TXDESC_CONTROL_INT;
1095 
1096         /* Copy data to the DMA buffer */
1097         memcpy(pldat->tx_buff_v + txidx * ENET_MAXF_SIZE, skb->data, len);
1098 
1099         /* Save the buffer and increment the buffer counter */
1100         pldat->skblen[txidx] = len;
1101         pldat->num_used_tx_buffs++;
1102 
1103         /* Start transmit */
1104         txidx++;
1105         if (txidx >= ENET_TX_DESC)
1106                 txidx = 0;
1107         writel(txidx, LPC_ENET_TXPRODUCEINDEX(pldat->net_base));
1108 
1109         /* Stop queue if no more TX buffers */
1110         if (pldat->num_used_tx_buffs >= (ENET_TX_DESC - 1))
1111                 netif_stop_queue(ndev);
1112 
1113         spin_unlock_irq(&pldat->lock);
1114 
1115         dev_kfree_skb(skb);
1116         return NETDEV_TX_OK;
1117 }
1118 
1119 static int lpc_set_mac_address(struct net_device *ndev, void *p)
1120 {
1121         struct sockaddr *addr = p;
1122         struct netdata_local *pldat = netdev_priv(ndev);
1123         unsigned long flags;
1124 
1125         if (!is_valid_ether_addr(addr->sa_data))
1126                 return -EADDRNOTAVAIL;
1127         memcpy(ndev->dev_addr, addr->sa_data, ETH_ALEN);
1128 
1129         spin_lock_irqsave(&pldat->lock, flags);
1130 
1131         /* Set station address */
1132         __lpc_set_mac(pldat, ndev->dev_addr);
1133 
1134         spin_unlock_irqrestore(&pldat->lock, flags);
1135 
1136         return 0;
1137 }
1138 
1139 static void lpc_eth_set_multicast_list(struct net_device *ndev)
1140 {
1141         struct netdata_local *pldat = netdev_priv(ndev);
1142         struct netdev_hw_addr_list *mcptr = &ndev->mc;
1143         struct netdev_hw_addr *ha;
1144         u32 tmp32, hash_val, hashlo, hashhi;
1145         unsigned long flags;
1146 
1147         spin_lock_irqsave(&pldat->lock, flags);
1148 
1149         /* Set station address */
1150         __lpc_set_mac(pldat, ndev->dev_addr);
1151 
1152         tmp32 =  LPC_RXFLTRW_ACCEPTUBROADCAST | LPC_RXFLTRW_ACCEPTPERFECT;
1153 
1154         if (ndev->flags & IFF_PROMISC)
1155                 tmp32 |= LPC_RXFLTRW_ACCEPTUNICAST |
1156                         LPC_RXFLTRW_ACCEPTUMULTICAST;
1157         if (ndev->flags & IFF_ALLMULTI)
1158                 tmp32 |= LPC_RXFLTRW_ACCEPTUMULTICAST;
1159 
1160         if (netdev_hw_addr_list_count(mcptr))
1161                 tmp32 |= LPC_RXFLTRW_ACCEPTUMULTICASTHASH;
1162 
1163         writel(tmp32, LPC_ENET_RXFILTER_CTRL(pldat->net_base));
1164 
1165 
1166         /* Set initial hash table */
1167         hashlo = 0x0;
1168         hashhi = 0x0;
1169 
1170         /* 64 bits : multicast address in hash table */
1171         netdev_hw_addr_list_for_each(ha, mcptr) {
1172                 hash_val = (ether_crc(6, ha->addr) >> 23) & 0x3F;
1173 
1174                 if (hash_val >= 32)
1175                         hashhi |= 1 << (hash_val - 32);
1176                 else
1177                         hashlo |= 1 << hash_val;
1178         }
1179 
1180         writel(hashlo, LPC_ENET_HASHFILTERL(pldat->net_base));
1181         writel(hashhi, LPC_ENET_HASHFILTERH(pldat->net_base));
1182 
1183         spin_unlock_irqrestore(&pldat->lock, flags);
1184 }
1185 
1186 static int lpc_eth_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1187 {
1188         struct netdata_local *pldat = netdev_priv(ndev);
1189         struct phy_device *phydev = pldat->phy_dev;
1190 
1191         if (!netif_running(ndev))
1192                 return -EINVAL;
1193 
1194         if (!phydev)
1195                 return -ENODEV;
1196 
1197         return phy_mii_ioctl(phydev, req, cmd);
1198 }
1199 
1200 static int lpc_eth_open(struct net_device *ndev)
1201 {
1202         struct netdata_local *pldat = netdev_priv(ndev);
1203 
1204         if (netif_msg_ifup(pldat))
1205                 dev_dbg(&pldat->pdev->dev, "enabling %s\n", ndev->name);
1206 
1207         __lpc_eth_clock_enable(pldat, true);
1208 
1209         /* Suspended PHY makes LPC ethernet core block, so resume now */
1210         phy_resume(pldat->phy_dev);
1211 
1212         /* Reset and initialize */
1213         __lpc_eth_reset(pldat);
1214         __lpc_eth_init(pldat);
1215 
1216         /* schedule a link state check */
1217         phy_start(pldat->phy_dev);
1218         netif_start_queue(ndev);
1219         napi_enable(&pldat->napi);
1220 
1221         return 0;
1222 }
1223 
1224 /*
1225  * Ethtool ops
1226  */
1227 static void lpc_eth_ethtool_getdrvinfo(struct net_device *ndev,
1228         struct ethtool_drvinfo *info)
1229 {
1230         strlcpy(info->driver, MODNAME, sizeof(info->driver));
1231         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1232         strlcpy(info->bus_info, dev_name(ndev->dev.parent),
1233                 sizeof(info->bus_info));
1234 }
1235 
1236 static u32 lpc_eth_ethtool_getmsglevel(struct net_device *ndev)
1237 {
1238         struct netdata_local *pldat = netdev_priv(ndev);
1239 
1240         return pldat->msg_enable;
1241 }
1242 
1243 static void lpc_eth_ethtool_setmsglevel(struct net_device *ndev, u32 level)
1244 {
1245         struct netdata_local *pldat = netdev_priv(ndev);
1246 
1247         pldat->msg_enable = level;
1248 }
1249 
1250 static int lpc_eth_ethtool_getsettings(struct net_device *ndev,
1251         struct ethtool_cmd *cmd)
1252 {
1253         struct netdata_local *pldat = netdev_priv(ndev);
1254         struct phy_device *phydev = pldat->phy_dev;
1255 
1256         if (!phydev)
1257                 return -EOPNOTSUPP;
1258 
1259         return phy_ethtool_gset(phydev, cmd);
1260 }
1261 
1262 static int lpc_eth_ethtool_setsettings(struct net_device *ndev,
1263         struct ethtool_cmd *cmd)
1264 {
1265         struct netdata_local *pldat = netdev_priv(ndev);
1266         struct phy_device *phydev = pldat->phy_dev;
1267 
1268         if (!phydev)
1269                 return -EOPNOTSUPP;
1270 
1271         return phy_ethtool_sset(phydev, cmd);
1272 }
1273 
1274 static const struct ethtool_ops lpc_eth_ethtool_ops = {
1275         .get_drvinfo    = lpc_eth_ethtool_getdrvinfo,
1276         .get_settings   = lpc_eth_ethtool_getsettings,
1277         .set_settings   = lpc_eth_ethtool_setsettings,
1278         .get_msglevel   = lpc_eth_ethtool_getmsglevel,
1279         .set_msglevel   = lpc_eth_ethtool_setmsglevel,
1280         .get_link       = ethtool_op_get_link,
1281 };
1282 
1283 static const struct net_device_ops lpc_netdev_ops = {
1284         .ndo_open               = lpc_eth_open,
1285         .ndo_stop               = lpc_eth_close,
1286         .ndo_start_xmit         = lpc_eth_hard_start_xmit,
1287         .ndo_set_rx_mode        = lpc_eth_set_multicast_list,
1288         .ndo_do_ioctl           = lpc_eth_ioctl,
1289         .ndo_set_mac_address    = lpc_set_mac_address,
1290         .ndo_validate_addr      = eth_validate_addr,
1291         .ndo_change_mtu         = eth_change_mtu,
1292 };
1293 
1294 static int lpc_eth_drv_probe(struct platform_device *pdev)
1295 {
1296         struct resource *res;
1297         struct net_device *ndev;
1298         struct netdata_local *pldat;
1299         struct phy_device *phydev;
1300         dma_addr_t dma_handle;
1301         int irq, ret;
1302         u32 tmp;
1303 
1304         /* Setup network interface for RMII or MII mode */
1305         tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
1306         tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
1307         if (lpc_phy_interface_mode(&pdev->dev) == PHY_INTERFACE_MODE_MII)
1308                 tmp |= LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS;
1309         else
1310                 tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
1311         __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
1312 
1313         /* Get platform resources */
1314         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1315         irq = platform_get_irq(pdev, 0);
1316         if (!res || irq < 0) {
1317                 dev_err(&pdev->dev, "error getting resources.\n");
1318                 ret = -ENXIO;
1319                 goto err_exit;
1320         }
1321 
1322         /* Allocate net driver data structure */
1323         ndev = alloc_etherdev(sizeof(struct netdata_local));
1324         if (!ndev) {
1325                 dev_err(&pdev->dev, "could not allocate device.\n");
1326                 ret = -ENOMEM;
1327                 goto err_exit;
1328         }
1329 
1330         SET_NETDEV_DEV(ndev, &pdev->dev);
1331 
1332         pldat = netdev_priv(ndev);
1333         pldat->pdev = pdev;
1334         pldat->ndev = ndev;
1335 
1336         spin_lock_init(&pldat->lock);
1337 
1338         /* Save resources */
1339         ndev->irq = irq;
1340 
1341         /* Get clock for the device */
1342         pldat->clk = clk_get(&pdev->dev, NULL);
1343         if (IS_ERR(pldat->clk)) {
1344                 dev_err(&pdev->dev, "error getting clock.\n");
1345                 ret = PTR_ERR(pldat->clk);
1346                 goto err_out_free_dev;
1347         }
1348 
1349         /* Enable network clock */
1350         __lpc_eth_clock_enable(pldat, true);
1351 
1352         /* Map IO space */
1353         pldat->net_base = ioremap(res->start, resource_size(res));
1354         if (!pldat->net_base) {
1355                 dev_err(&pdev->dev, "failed to map registers\n");
1356                 ret = -ENOMEM;
1357                 goto err_out_disable_clocks;
1358         }
1359         ret = request_irq(ndev->irq, __lpc_eth_interrupt, 0,
1360                           ndev->name, ndev);
1361         if (ret) {
1362                 dev_err(&pdev->dev, "error requesting interrupt.\n");
1363                 goto err_out_iounmap;
1364         }
1365 
1366         /* Setup driver functions */
1367         ndev->netdev_ops = &lpc_netdev_ops;
1368         ndev->ethtool_ops = &lpc_eth_ethtool_ops;
1369         ndev->watchdog_timeo = msecs_to_jiffies(2500);
1370 
1371         /* Get size of DMA buffers/descriptors region */
1372         pldat->dma_buff_size = (ENET_TX_DESC + ENET_RX_DESC) * (ENET_MAXF_SIZE +
1373                 sizeof(struct txrx_desc_t) + sizeof(struct rx_status_t));
1374         pldat->dma_buff_base_v = 0;
1375 
1376         if (use_iram_for_net(&pldat->pdev->dev)) {
1377                 dma_handle = LPC32XX_IRAM_BASE;
1378                 if (pldat->dma_buff_size <= lpc32xx_return_iram_size())
1379                         pldat->dma_buff_base_v =
1380                                 io_p2v(LPC32XX_IRAM_BASE);
1381                 else
1382                         netdev_err(ndev,
1383                                 "IRAM not big enough for net buffers, using SDRAM instead.\n");
1384         }
1385 
1386         if (pldat->dma_buff_base_v == 0) {
1387                 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1388                 if (ret)
1389                         goto err_out_free_irq;
1390 
1391                 pldat->dma_buff_size = PAGE_ALIGN(pldat->dma_buff_size);
1392 
1393                 /* Allocate a chunk of memory for the DMA ethernet buffers
1394                    and descriptors */
1395                 pldat->dma_buff_base_v =
1396                         dma_alloc_coherent(&pldat->pdev->dev,
1397                                            pldat->dma_buff_size, &dma_handle,
1398                                            GFP_KERNEL);
1399                 if (pldat->dma_buff_base_v == NULL) {
1400                         ret = -ENOMEM;
1401                         goto err_out_free_irq;
1402                 }
1403         }
1404         pldat->dma_buff_base_p = dma_handle;
1405 
1406         netdev_dbg(ndev, "IO address space     :%pR\n", res);
1407         netdev_dbg(ndev, "IO address size      :%d\n", resource_size(res));
1408         netdev_dbg(ndev, "IO address (mapped)  :0x%p\n",
1409                         pldat->net_base);
1410         netdev_dbg(ndev, "IRQ number           :%d\n", ndev->irq);
1411         netdev_dbg(ndev, "DMA buffer size      :%d\n", pldat->dma_buff_size);
1412         netdev_dbg(ndev, "DMA buffer P address :0x%08x\n",
1413                         pldat->dma_buff_base_p);
1414         netdev_dbg(ndev, "DMA buffer V address :0x%p\n",
1415                         pldat->dma_buff_base_v);
1416 
1417         /* Get MAC address from current HW setting (POR state is all zeros) */
1418         __lpc_get_mac(pldat, ndev->dev_addr);
1419 
1420         if (!is_valid_ether_addr(ndev->dev_addr)) {
1421                 const char *macaddr = of_get_mac_address(pdev->dev.of_node);
1422                 if (macaddr)
1423                         memcpy(ndev->dev_addr, macaddr, ETH_ALEN);
1424         }
1425         if (!is_valid_ether_addr(ndev->dev_addr))
1426                 eth_hw_addr_random(ndev);
1427 
1428         /* Reset the ethernet controller */
1429         __lpc_eth_reset(pldat);
1430 
1431         /* then shut everything down to save power */
1432         __lpc_eth_shutdown(pldat);
1433 
1434         /* Set default parameters */
1435         pldat->msg_enable = NETIF_MSG_LINK;
1436 
1437         /* Force an MII interface reset and clock setup */
1438         __lpc_mii_mngt_reset(pldat);
1439 
1440         /* Force default PHY interface setup in chip, this will probably be
1441            changed by the PHY driver */
1442         pldat->link = 0;
1443         pldat->speed = 100;
1444         pldat->duplex = DUPLEX_FULL;
1445         __lpc_params_setup(pldat);
1446 
1447         netif_napi_add(ndev, &pldat->napi, lpc_eth_poll, NAPI_WEIGHT);
1448 
1449         ret = register_netdev(ndev);
1450         if (ret) {
1451                 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1452                 goto err_out_dma_unmap;
1453         }
1454         platform_set_drvdata(pdev, ndev);
1455 
1456         ret = lpc_mii_init(pldat);
1457         if (ret)
1458                 goto err_out_unregister_netdev;
1459 
1460         netdev_info(ndev, "LPC mac at 0x%08x irq %d\n",
1461                res->start, ndev->irq);
1462 
1463         phydev = pldat->phy_dev;
1464 
1465         device_init_wakeup(&pdev->dev, 1);
1466         device_set_wakeup_enable(&pdev->dev, 0);
1467 
1468         return 0;
1469 
1470 err_out_unregister_netdev:
1471         unregister_netdev(ndev);
1472 err_out_dma_unmap:
1473         if (!use_iram_for_net(&pldat->pdev->dev) ||
1474             pldat->dma_buff_size > lpc32xx_return_iram_size())
1475                 dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size,
1476                                   pldat->dma_buff_base_v,
1477                                   pldat->dma_buff_base_p);
1478 err_out_free_irq:
1479         free_irq(ndev->irq, ndev);
1480 err_out_iounmap:
1481         iounmap(pldat->net_base);
1482 err_out_disable_clocks:
1483         clk_disable_unprepare(pldat->clk);
1484         clk_put(pldat->clk);
1485 err_out_free_dev:
1486         free_netdev(ndev);
1487 err_exit:
1488         pr_err("%s: not found (%d).\n", MODNAME, ret);
1489         return ret;
1490 }
1491 
1492 static int lpc_eth_drv_remove(struct platform_device *pdev)
1493 {
1494         struct net_device *ndev = platform_get_drvdata(pdev);
1495         struct netdata_local *pldat = netdev_priv(ndev);
1496 
1497         unregister_netdev(ndev);
1498 
1499         if (!use_iram_for_net(&pldat->pdev->dev) ||
1500             pldat->dma_buff_size > lpc32xx_return_iram_size())
1501                 dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size,
1502                                   pldat->dma_buff_base_v,
1503                                   pldat->dma_buff_base_p);
1504         free_irq(ndev->irq, ndev);
1505         iounmap(pldat->net_base);
1506         mdiobus_unregister(pldat->mii_bus);
1507         mdiobus_free(pldat->mii_bus);
1508         clk_disable_unprepare(pldat->clk);
1509         clk_put(pldat->clk);
1510         free_netdev(ndev);
1511 
1512         return 0;
1513 }
1514 
1515 #ifdef CONFIG_PM
1516 static int lpc_eth_drv_suspend(struct platform_device *pdev,
1517         pm_message_t state)
1518 {
1519         struct net_device *ndev = platform_get_drvdata(pdev);
1520         struct netdata_local *pldat = netdev_priv(ndev);
1521 
1522         if (device_may_wakeup(&pdev->dev))
1523                 enable_irq_wake(ndev->irq);
1524 
1525         if (ndev) {
1526                 if (netif_running(ndev)) {
1527                         netif_device_detach(ndev);
1528                         __lpc_eth_shutdown(pldat);
1529                         clk_disable_unprepare(pldat->clk);
1530 
1531                         /*
1532                          * Reset again now clock is disable to be sure
1533                          * EMC_MDC is down
1534                          */
1535                         __lpc_eth_reset(pldat);
1536                 }
1537         }
1538 
1539         return 0;
1540 }
1541 
1542 static int lpc_eth_drv_resume(struct platform_device *pdev)
1543 {
1544         struct net_device *ndev = platform_get_drvdata(pdev);
1545         struct netdata_local *pldat;
1546 
1547         if (device_may_wakeup(&pdev->dev))
1548                 disable_irq_wake(ndev->irq);
1549 
1550         if (ndev) {
1551                 if (netif_running(ndev)) {
1552                         pldat = netdev_priv(ndev);
1553 
1554                         /* Enable interface clock */
1555                         clk_enable(pldat->clk);
1556 
1557                         /* Reset and initialize */
1558                         __lpc_eth_reset(pldat);
1559                         __lpc_eth_init(pldat);
1560 
1561                         netif_device_attach(ndev);
1562                 }
1563         }
1564 
1565         return 0;
1566 }
1567 #endif
1568 
1569 #ifdef CONFIG_OF
1570 static const struct of_device_id lpc_eth_match[] = {
1571         { .compatible = "nxp,lpc-eth" },
1572         { }
1573 };
1574 MODULE_DEVICE_TABLE(of, lpc_eth_match);
1575 #endif
1576 
1577 static struct platform_driver lpc_eth_driver = {
1578         .probe          = lpc_eth_drv_probe,
1579         .remove         = lpc_eth_drv_remove,
1580 #ifdef CONFIG_PM
1581         .suspend        = lpc_eth_drv_suspend,
1582         .resume         = lpc_eth_drv_resume,
1583 #endif
1584         .driver         = {
1585                 .name   = MODNAME,
1586                 .of_match_table = of_match_ptr(lpc_eth_match),
1587         },
1588 };
1589 
1590 module_platform_driver(lpc_eth_driver);
1591 
1592 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
1593 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
1594 MODULE_DESCRIPTION("LPC Ethernet Driver");
1595 MODULE_LICENSE("GPL");
1596 

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