Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/net/ethernet/nuvoton/w90p910_ether.c

  1 /*
  2  * Copyright (c) 2008-2009 Nuvoton technology corporation.
  3  *
  4  * Wan ZongShun <mcuos.com@gmail.com>
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License as published by
  8  * the Free Software Foundation;version 2 of the License.
  9  *
 10  */
 11 
 12 #include <linux/module.h>
 13 #include <linux/init.h>
 14 #include <linux/mii.h>
 15 #include <linux/netdevice.h>
 16 #include <linux/etherdevice.h>
 17 #include <linux/skbuff.h>
 18 #include <linux/ethtool.h>
 19 #include <linux/platform_device.h>
 20 #include <linux/clk.h>
 21 #include <linux/gfp.h>
 22 
 23 #define DRV_MODULE_NAME         "w90p910-emc"
 24 #define DRV_MODULE_VERSION      "0.1"
 25 
 26 /* Ethernet MAC Registers */
 27 #define REG_CAMCMR              0x00
 28 #define REG_CAMEN               0x04
 29 #define REG_CAMM_BASE           0x08
 30 #define REG_CAML_BASE           0x0c
 31 #define REG_TXDLSA              0x88
 32 #define REG_RXDLSA              0x8C
 33 #define REG_MCMDR               0x90
 34 #define REG_MIID                0x94
 35 #define REG_MIIDA               0x98
 36 #define REG_FFTCR               0x9C
 37 #define REG_TSDR                0xa0
 38 #define REG_RSDR                0xa4
 39 #define REG_DMARFC              0xa8
 40 #define REG_MIEN                0xac
 41 #define REG_MISTA               0xb0
 42 #define REG_CTXDSA              0xcc
 43 #define REG_CTXBSA              0xd0
 44 #define REG_CRXDSA              0xd4
 45 #define REG_CRXBSA              0xd8
 46 
 47 /* mac controller bit */
 48 #define MCMDR_RXON              0x01
 49 #define MCMDR_ACP               (0x01 << 3)
 50 #define MCMDR_SPCRC             (0x01 << 5)
 51 #define MCMDR_TXON              (0x01 << 8)
 52 #define MCMDR_FDUP              (0x01 << 18)
 53 #define MCMDR_ENMDC             (0x01 << 19)
 54 #define MCMDR_OPMOD             (0x01 << 20)
 55 #define SWR                     (0x01 << 24)
 56 
 57 /* cam command regiser */
 58 #define CAMCMR_AUP              0x01
 59 #define CAMCMR_AMP              (0x01 << 1)
 60 #define CAMCMR_ABP              (0x01 << 2)
 61 #define CAMCMR_CCAM             (0x01 << 3)
 62 #define CAMCMR_ECMP             (0x01 << 4)
 63 #define CAM0EN                  0x01
 64 
 65 /* mac mii controller bit */
 66 #define MDCCR                   (0x0a << 20)
 67 #define PHYAD                   (0x01 << 8)
 68 #define PHYWR                   (0x01 << 16)
 69 #define PHYBUSY                 (0x01 << 17)
 70 #define PHYPRESP                (0x01 << 18)
 71 #define CAM_ENTRY_SIZE          0x08
 72 
 73 /* rx and tx status */
 74 #define TXDS_TXCP               (0x01 << 19)
 75 #define RXDS_CRCE               (0x01 << 17)
 76 #define RXDS_PTLE               (0x01 << 19)
 77 #define RXDS_RXGD               (0x01 << 20)
 78 #define RXDS_ALIE               (0x01 << 21)
 79 #define RXDS_RP                 (0x01 << 22)
 80 
 81 /* mac interrupt status*/
 82 #define MISTA_EXDEF             (0x01 << 19)
 83 #define MISTA_TXBERR            (0x01 << 24)
 84 #define MISTA_TDU               (0x01 << 23)
 85 #define MISTA_RDU               (0x01 << 10)
 86 #define MISTA_RXBERR            (0x01 << 11)
 87 
 88 #define ENSTART                 0x01
 89 #define ENRXINTR                0x01
 90 #define ENRXGD                  (0x01 << 4)
 91 #define ENRXBERR                (0x01 << 11)
 92 #define ENTXINTR                (0x01 << 16)
 93 #define ENTXCP                  (0x01 << 18)
 94 #define ENTXABT                 (0x01 << 21)
 95 #define ENTXBERR                (0x01 << 24)
 96 #define ENMDC                   (0x01 << 19)
 97 #define PHYBUSY                 (0x01 << 17)
 98 #define MDCCR_VAL               0xa00000
 99 
100 /* rx and tx owner bit */
101 #define RX_OWEN_DMA             (0x01 << 31)
102 #define RX_OWEN_CPU             (~(0x03 << 30))
103 #define TX_OWEN_DMA             (0x01 << 31)
104 #define TX_OWEN_CPU             (~(0x01 << 31))
105 
106 /* tx frame desc controller bit */
107 #define MACTXINTEN              0x04
108 #define CRCMODE                 0x02
109 #define PADDINGMODE             0x01
110 
111 /* fftcr controller bit */
112 #define TXTHD                   (0x03 << 8)
113 #define BLENGTH                 (0x01 << 20)
114 
115 /* global setting for driver */
116 #define RX_DESC_SIZE            50
117 #define TX_DESC_SIZE            10
118 #define MAX_RBUFF_SZ            0x600
119 #define MAX_TBUFF_SZ            0x600
120 #define TX_TIMEOUT              (HZ/2)
121 #define DELAY                   1000
122 #define CAM0                    0x0
123 
124 static int w90p910_mdio_read(struct net_device *dev, int phy_id, int reg);
125 
126 struct w90p910_rxbd {
127         unsigned int sl;
128         unsigned int buffer;
129         unsigned int reserved;
130         unsigned int next;
131 };
132 
133 struct w90p910_txbd {
134         unsigned int mode;
135         unsigned int buffer;
136         unsigned int sl;
137         unsigned int next;
138 };
139 
140 struct recv_pdesc {
141         struct w90p910_rxbd desclist[RX_DESC_SIZE];
142         char recv_buf[RX_DESC_SIZE][MAX_RBUFF_SZ];
143 };
144 
145 struct tran_pdesc {
146         struct w90p910_txbd desclist[TX_DESC_SIZE];
147         char tran_buf[TX_DESC_SIZE][MAX_TBUFF_SZ];
148 };
149 
150 struct  w90p910_ether {
151         struct recv_pdesc *rdesc;
152         struct tran_pdesc *tdesc;
153         dma_addr_t rdesc_phys;
154         dma_addr_t tdesc_phys;
155         struct net_device_stats stats;
156         struct platform_device *pdev;
157         struct resource *res;
158         struct sk_buff *skb;
159         struct clk *clk;
160         struct clk *rmiiclk;
161         struct mii_if_info mii;
162         struct timer_list check_timer;
163         void __iomem *reg;
164         int rxirq;
165         int txirq;
166         unsigned int cur_tx;
167         unsigned int cur_rx;
168         unsigned int finish_tx;
169         unsigned int rx_packets;
170         unsigned int rx_bytes;
171         unsigned int start_tx_ptr;
172         unsigned int start_rx_ptr;
173         unsigned int linkflag;
174 };
175 
176 static void update_linkspeed_register(struct net_device *dev,
177                                 unsigned int speed, unsigned int duplex)
178 {
179         struct w90p910_ether *ether = netdev_priv(dev);
180         unsigned int val;
181 
182         val = __raw_readl(ether->reg + REG_MCMDR);
183 
184         if (speed == SPEED_100) {
185                 /* 100 full/half duplex */
186                 if (duplex == DUPLEX_FULL) {
187                         val |= (MCMDR_OPMOD | MCMDR_FDUP);
188                 } else {
189                         val |= MCMDR_OPMOD;
190                         val &= ~MCMDR_FDUP;
191                 }
192         } else {
193                 /* 10 full/half duplex */
194                 if (duplex == DUPLEX_FULL) {
195                         val |= MCMDR_FDUP;
196                         val &= ~MCMDR_OPMOD;
197                 } else {
198                         val &= ~(MCMDR_FDUP | MCMDR_OPMOD);
199                 }
200         }
201 
202         __raw_writel(val, ether->reg + REG_MCMDR);
203 }
204 
205 static void update_linkspeed(struct net_device *dev)
206 {
207         struct w90p910_ether *ether = netdev_priv(dev);
208         struct platform_device *pdev;
209         unsigned int bmsr, bmcr, lpa, speed, duplex;
210 
211         pdev = ether->pdev;
212 
213         if (!mii_link_ok(&ether->mii)) {
214                 ether->linkflag = 0x0;
215                 netif_carrier_off(dev);
216                 dev_warn(&pdev->dev, "%s: Link down.\n", dev->name);
217                 return;
218         }
219 
220         if (ether->linkflag == 1)
221                 return;
222 
223         bmsr = w90p910_mdio_read(dev, ether->mii.phy_id, MII_BMSR);
224         bmcr = w90p910_mdio_read(dev, ether->mii.phy_id, MII_BMCR);
225 
226         if (bmcr & BMCR_ANENABLE) {
227                 if (!(bmsr & BMSR_ANEGCOMPLETE))
228                         return;
229 
230                 lpa = w90p910_mdio_read(dev, ether->mii.phy_id, MII_LPA);
231 
232                 if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF))
233                         speed = SPEED_100;
234                 else
235                         speed = SPEED_10;
236 
237                 if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL))
238                         duplex = DUPLEX_FULL;
239                 else
240                         duplex = DUPLEX_HALF;
241 
242         } else {
243                 speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
244                 duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
245         }
246 
247         update_linkspeed_register(dev, speed, duplex);
248 
249         dev_info(&pdev->dev, "%s: Link now %i-%s\n", dev->name, speed,
250                         (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
251         ether->linkflag = 0x01;
252 
253         netif_carrier_on(dev);
254 }
255 
256 static void w90p910_check_link(unsigned long dev_id)
257 {
258         struct net_device *dev = (struct net_device *) dev_id;
259         struct w90p910_ether *ether = netdev_priv(dev);
260 
261         update_linkspeed(dev);
262         mod_timer(&ether->check_timer, jiffies + msecs_to_jiffies(1000));
263 }
264 
265 static void w90p910_write_cam(struct net_device *dev,
266                                 unsigned int x, unsigned char *pval)
267 {
268         struct w90p910_ether *ether = netdev_priv(dev);
269         unsigned int msw, lsw;
270 
271         msw = (pval[0] << 24) | (pval[1] << 16) | (pval[2] << 8) | pval[3];
272 
273         lsw = (pval[4] << 24) | (pval[5] << 16);
274 
275         __raw_writel(lsw, ether->reg + REG_CAML_BASE + x * CAM_ENTRY_SIZE);
276         __raw_writel(msw, ether->reg + REG_CAMM_BASE + x * CAM_ENTRY_SIZE);
277 }
278 
279 static int w90p910_init_desc(struct net_device *dev)
280 {
281         struct w90p910_ether *ether;
282         struct w90p910_txbd  *tdesc;
283         struct w90p910_rxbd  *rdesc;
284         struct platform_device *pdev;
285         unsigned int i;
286 
287         ether = netdev_priv(dev);
288         pdev = ether->pdev;
289 
290         ether->tdesc = dma_alloc_coherent(&pdev->dev, sizeof(struct tran_pdesc),
291                                           &ether->tdesc_phys, GFP_KERNEL);
292         if (!ether->tdesc)
293                 return -ENOMEM;
294 
295         ether->rdesc = dma_alloc_coherent(&pdev->dev, sizeof(struct recv_pdesc),
296                                           &ether->rdesc_phys, GFP_KERNEL);
297         if (!ether->rdesc) {
298                 dma_free_coherent(&pdev->dev, sizeof(struct tran_pdesc),
299                                   ether->tdesc, ether->tdesc_phys);
300                 return -ENOMEM;
301         }
302 
303         for (i = 0; i < TX_DESC_SIZE; i++) {
304                 unsigned int offset;
305 
306                 tdesc = &(ether->tdesc->desclist[i]);
307 
308                 if (i == TX_DESC_SIZE - 1)
309                         offset = offsetof(struct tran_pdesc, desclist[0]);
310                 else
311                         offset = offsetof(struct tran_pdesc, desclist[i + 1]);
312 
313                 tdesc->next = ether->tdesc_phys + offset;
314                 tdesc->buffer = ether->tdesc_phys +
315                         offsetof(struct tran_pdesc, tran_buf[i]);
316                 tdesc->sl = 0;
317                 tdesc->mode = 0;
318         }
319 
320         ether->start_tx_ptr = ether->tdesc_phys;
321 
322         for (i = 0; i < RX_DESC_SIZE; i++) {
323                 unsigned int offset;
324 
325                 rdesc = &(ether->rdesc->desclist[i]);
326 
327                 if (i == RX_DESC_SIZE - 1)
328                         offset = offsetof(struct recv_pdesc, desclist[0]);
329                 else
330                         offset = offsetof(struct recv_pdesc, desclist[i + 1]);
331 
332                 rdesc->next = ether->rdesc_phys + offset;
333                 rdesc->sl = RX_OWEN_DMA;
334                 rdesc->buffer = ether->rdesc_phys +
335                         offsetof(struct recv_pdesc, recv_buf[i]);
336           }
337 
338         ether->start_rx_ptr = ether->rdesc_phys;
339 
340         return 0;
341 }
342 
343 static void w90p910_set_fifo_threshold(struct net_device *dev)
344 {
345         struct w90p910_ether *ether = netdev_priv(dev);
346         unsigned int val;
347 
348         val = TXTHD | BLENGTH;
349         __raw_writel(val, ether->reg + REG_FFTCR);
350 }
351 
352 static void w90p910_return_default_idle(struct net_device *dev)
353 {
354         struct w90p910_ether *ether = netdev_priv(dev);
355         unsigned int val;
356 
357         val = __raw_readl(ether->reg + REG_MCMDR);
358         val |= SWR;
359         __raw_writel(val, ether->reg + REG_MCMDR);
360 }
361 
362 static void w90p910_trigger_rx(struct net_device *dev)
363 {
364         struct w90p910_ether *ether = netdev_priv(dev);
365 
366         __raw_writel(ENSTART, ether->reg + REG_RSDR);
367 }
368 
369 static void w90p910_trigger_tx(struct net_device *dev)
370 {
371         struct w90p910_ether *ether = netdev_priv(dev);
372 
373         __raw_writel(ENSTART, ether->reg + REG_TSDR);
374 }
375 
376 static void w90p910_enable_mac_interrupt(struct net_device *dev)
377 {
378         struct w90p910_ether *ether = netdev_priv(dev);
379         unsigned int val;
380 
381         val = ENTXINTR | ENRXINTR | ENRXGD | ENTXCP;
382         val |= ENTXBERR | ENRXBERR | ENTXABT;
383 
384         __raw_writel(val, ether->reg + REG_MIEN);
385 }
386 
387 static void w90p910_get_and_clear_int(struct net_device *dev,
388                                                         unsigned int *val)
389 {
390         struct w90p910_ether *ether = netdev_priv(dev);
391 
392         *val = __raw_readl(ether->reg + REG_MISTA);
393         __raw_writel(*val, ether->reg + REG_MISTA);
394 }
395 
396 static void w90p910_set_global_maccmd(struct net_device *dev)
397 {
398         struct w90p910_ether *ether = netdev_priv(dev);
399         unsigned int val;
400 
401         val = __raw_readl(ether->reg + REG_MCMDR);
402         val |= MCMDR_SPCRC | MCMDR_ENMDC | MCMDR_ACP | ENMDC;
403         __raw_writel(val, ether->reg + REG_MCMDR);
404 }
405 
406 static void w90p910_enable_cam(struct net_device *dev)
407 {
408         struct w90p910_ether *ether = netdev_priv(dev);
409         unsigned int val;
410 
411         w90p910_write_cam(dev, CAM0, dev->dev_addr);
412 
413         val = __raw_readl(ether->reg + REG_CAMEN);
414         val |= CAM0EN;
415         __raw_writel(val, ether->reg + REG_CAMEN);
416 }
417 
418 static void w90p910_enable_cam_command(struct net_device *dev)
419 {
420         struct w90p910_ether *ether = netdev_priv(dev);
421         unsigned int val;
422 
423         val = CAMCMR_ECMP | CAMCMR_ABP | CAMCMR_AMP;
424         __raw_writel(val, ether->reg + REG_CAMCMR);
425 }
426 
427 static void w90p910_enable_tx(struct net_device *dev, unsigned int enable)
428 {
429         struct w90p910_ether *ether = netdev_priv(dev);
430         unsigned int val;
431 
432         val = __raw_readl(ether->reg + REG_MCMDR);
433 
434         if (enable)
435                 val |= MCMDR_TXON;
436         else
437                 val &= ~MCMDR_TXON;
438 
439         __raw_writel(val, ether->reg + REG_MCMDR);
440 }
441 
442 static void w90p910_enable_rx(struct net_device *dev, unsigned int enable)
443 {
444         struct w90p910_ether *ether = netdev_priv(dev);
445         unsigned int val;
446 
447         val = __raw_readl(ether->reg + REG_MCMDR);
448 
449         if (enable)
450                 val |= MCMDR_RXON;
451         else
452                 val &= ~MCMDR_RXON;
453 
454         __raw_writel(val, ether->reg + REG_MCMDR);
455 }
456 
457 static void w90p910_set_curdest(struct net_device *dev)
458 {
459         struct w90p910_ether *ether = netdev_priv(dev);
460 
461         __raw_writel(ether->start_rx_ptr, ether->reg + REG_RXDLSA);
462         __raw_writel(ether->start_tx_ptr, ether->reg + REG_TXDLSA);
463 }
464 
465 static void w90p910_reset_mac(struct net_device *dev)
466 {
467         struct w90p910_ether *ether = netdev_priv(dev);
468 
469         w90p910_enable_tx(dev, 0);
470         w90p910_enable_rx(dev, 0);
471         w90p910_set_fifo_threshold(dev);
472         w90p910_return_default_idle(dev);
473 
474         if (!netif_queue_stopped(dev))
475                 netif_stop_queue(dev);
476 
477         w90p910_init_desc(dev);
478 
479         dev->trans_start = jiffies; /* prevent tx timeout */
480         ether->cur_tx = 0x0;
481         ether->finish_tx = 0x0;
482         ether->cur_rx = 0x0;
483 
484         w90p910_set_curdest(dev);
485         w90p910_enable_cam(dev);
486         w90p910_enable_cam_command(dev);
487         w90p910_enable_mac_interrupt(dev);
488         w90p910_enable_tx(dev, 1);
489         w90p910_enable_rx(dev, 1);
490         w90p910_trigger_tx(dev);
491         w90p910_trigger_rx(dev);
492 
493         dev->trans_start = jiffies; /* prevent tx timeout */
494 
495         if (netif_queue_stopped(dev))
496                 netif_wake_queue(dev);
497 }
498 
499 static void w90p910_mdio_write(struct net_device *dev,
500                                         int phy_id, int reg, int data)
501 {
502         struct w90p910_ether *ether = netdev_priv(dev);
503         struct platform_device *pdev;
504         unsigned int val, i;
505 
506         pdev = ether->pdev;
507 
508         __raw_writel(data, ether->reg + REG_MIID);
509 
510         val = (phy_id << 0x08) | reg;
511         val |= PHYBUSY | PHYWR | MDCCR_VAL;
512         __raw_writel(val, ether->reg + REG_MIIDA);
513 
514         for (i = 0; i < DELAY; i++) {
515                 if ((__raw_readl(ether->reg + REG_MIIDA) & PHYBUSY) == 0)
516                         break;
517         }
518 
519         if (i == DELAY)
520                 dev_warn(&pdev->dev, "mdio write timed out\n");
521 }
522 
523 static int w90p910_mdio_read(struct net_device *dev, int phy_id, int reg)
524 {
525         struct w90p910_ether *ether = netdev_priv(dev);
526         struct platform_device *pdev;
527         unsigned int val, i, data;
528 
529         pdev = ether->pdev;
530 
531         val = (phy_id << 0x08) | reg;
532         val |= PHYBUSY | MDCCR_VAL;
533         __raw_writel(val, ether->reg + REG_MIIDA);
534 
535         for (i = 0; i < DELAY; i++) {
536                 if ((__raw_readl(ether->reg + REG_MIIDA) & PHYBUSY) == 0)
537                         break;
538         }
539 
540         if (i == DELAY) {
541                 dev_warn(&pdev->dev, "mdio read timed out\n");
542                 data = 0xffff;
543         } else {
544                 data = __raw_readl(ether->reg + REG_MIID);
545         }
546 
547         return data;
548 }
549 
550 static int w90p910_set_mac_address(struct net_device *dev, void *addr)
551 {
552         struct sockaddr *address = addr;
553 
554         if (!is_valid_ether_addr(address->sa_data))
555                 return -EADDRNOTAVAIL;
556 
557         memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
558         w90p910_write_cam(dev, CAM0, dev->dev_addr);
559 
560         return 0;
561 }
562 
563 static int w90p910_ether_close(struct net_device *dev)
564 {
565         struct w90p910_ether *ether = netdev_priv(dev);
566         struct platform_device *pdev;
567 
568         pdev = ether->pdev;
569 
570         dma_free_coherent(&pdev->dev, sizeof(struct recv_pdesc),
571                                         ether->rdesc, ether->rdesc_phys);
572         dma_free_coherent(&pdev->dev, sizeof(struct tran_pdesc),
573                                         ether->tdesc, ether->tdesc_phys);
574 
575         netif_stop_queue(dev);
576 
577         del_timer_sync(&ether->check_timer);
578         clk_disable(ether->rmiiclk);
579         clk_disable(ether->clk);
580 
581         free_irq(ether->txirq, dev);
582         free_irq(ether->rxirq, dev);
583 
584         return 0;
585 }
586 
587 static struct net_device_stats *w90p910_ether_stats(struct net_device *dev)
588 {
589         struct w90p910_ether *ether;
590 
591         ether = netdev_priv(dev);
592 
593         return &ether->stats;
594 }
595 
596 static int w90p910_send_frame(struct net_device *dev,
597                                         unsigned char *data, int length)
598 {
599         struct w90p910_ether *ether;
600         struct w90p910_txbd *txbd;
601         struct platform_device *pdev;
602         unsigned char *buffer;
603 
604         ether = netdev_priv(dev);
605         pdev = ether->pdev;
606 
607         txbd = &ether->tdesc->desclist[ether->cur_tx];
608         buffer = ether->tdesc->tran_buf[ether->cur_tx];
609 
610         if (length > 1514) {
611                 dev_err(&pdev->dev, "send data %d bytes, check it\n", length);
612                 length = 1514;
613         }
614 
615         txbd->sl = length & 0xFFFF;
616 
617         memcpy(buffer, data, length);
618 
619         txbd->mode = TX_OWEN_DMA | PADDINGMODE | CRCMODE | MACTXINTEN;
620 
621         w90p910_enable_tx(dev, 1);
622 
623         w90p910_trigger_tx(dev);
624 
625         if (++ether->cur_tx >= TX_DESC_SIZE)
626                 ether->cur_tx = 0;
627 
628         txbd = &ether->tdesc->desclist[ether->cur_tx];
629 
630         if (txbd->mode & TX_OWEN_DMA)
631                 netif_stop_queue(dev);
632 
633         return 0;
634 }
635 
636 static int w90p910_ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
637 {
638         struct w90p910_ether *ether = netdev_priv(dev);
639 
640         if (!(w90p910_send_frame(dev, skb->data, skb->len))) {
641                 ether->skb = skb;
642                 dev_kfree_skb_irq(skb);
643                 return 0;
644         }
645         return -EAGAIN;
646 }
647 
648 static irqreturn_t w90p910_tx_interrupt(int irq, void *dev_id)
649 {
650         struct w90p910_ether *ether;
651         struct w90p910_txbd  *txbd;
652         struct platform_device *pdev;
653         struct net_device *dev;
654         unsigned int cur_entry, entry, status;
655 
656         dev = dev_id;
657         ether = netdev_priv(dev);
658         pdev = ether->pdev;
659 
660         w90p910_get_and_clear_int(dev, &status);
661 
662         cur_entry = __raw_readl(ether->reg + REG_CTXDSA);
663 
664         entry = ether->tdesc_phys +
665                 offsetof(struct tran_pdesc, desclist[ether->finish_tx]);
666 
667         while (entry != cur_entry) {
668                 txbd = &ether->tdesc->desclist[ether->finish_tx];
669 
670                 if (++ether->finish_tx >= TX_DESC_SIZE)
671                         ether->finish_tx = 0;
672 
673                 if (txbd->sl & TXDS_TXCP) {
674                         ether->stats.tx_packets++;
675                         ether->stats.tx_bytes += txbd->sl & 0xFFFF;
676                 } else {
677                         ether->stats.tx_errors++;
678                 }
679 
680                 txbd->sl = 0x0;
681                 txbd->mode = 0x0;
682 
683                 if (netif_queue_stopped(dev))
684                         netif_wake_queue(dev);
685 
686                 entry = ether->tdesc_phys +
687                         offsetof(struct tran_pdesc, desclist[ether->finish_tx]);
688         }
689 
690         if (status & MISTA_EXDEF) {
691                 dev_err(&pdev->dev, "emc defer exceed interrupt\n");
692         } else if (status & MISTA_TXBERR) {
693                 dev_err(&pdev->dev, "emc bus error interrupt\n");
694                 w90p910_reset_mac(dev);
695         } else if (status & MISTA_TDU) {
696                 if (netif_queue_stopped(dev))
697                         netif_wake_queue(dev);
698         }
699 
700         return IRQ_HANDLED;
701 }
702 
703 static void netdev_rx(struct net_device *dev)
704 {
705         struct w90p910_ether *ether;
706         struct w90p910_rxbd *rxbd;
707         struct platform_device *pdev;
708         struct sk_buff *skb;
709         unsigned char *data;
710         unsigned int length, status, val, entry;
711 
712         ether = netdev_priv(dev);
713         pdev = ether->pdev;
714 
715         rxbd = &ether->rdesc->desclist[ether->cur_rx];
716 
717         do {
718                 val = __raw_readl(ether->reg + REG_CRXDSA);
719 
720                 entry = ether->rdesc_phys +
721                         offsetof(struct recv_pdesc, desclist[ether->cur_rx]);
722 
723                 if (val == entry)
724                         break;
725 
726                 status = rxbd->sl;
727                 length = status & 0xFFFF;
728 
729                 if (status & RXDS_RXGD) {
730                         data = ether->rdesc->recv_buf[ether->cur_rx];
731                         skb = netdev_alloc_skb(dev, length + 2);
732                         if (!skb) {
733                                 ether->stats.rx_dropped++;
734                                 return;
735                         }
736 
737                         skb_reserve(skb, 2);
738                         skb_put(skb, length);
739                         skb_copy_to_linear_data(skb, data, length);
740                         skb->protocol = eth_type_trans(skb, dev);
741                         ether->stats.rx_packets++;
742                         ether->stats.rx_bytes += length;
743                         netif_rx(skb);
744                 } else {
745                         ether->stats.rx_errors++;
746 
747                         if (status & RXDS_RP) {
748                                 dev_err(&pdev->dev, "rx runt err\n");
749                                 ether->stats.rx_length_errors++;
750                         } else if (status & RXDS_CRCE) {
751                                 dev_err(&pdev->dev, "rx crc err\n");
752                                 ether->stats.rx_crc_errors++;
753                         } else if (status & RXDS_ALIE) {
754                                 dev_err(&pdev->dev, "rx aligment err\n");
755                                 ether->stats.rx_frame_errors++;
756                         } else if (status & RXDS_PTLE) {
757                                 dev_err(&pdev->dev, "rx longer err\n");
758                                 ether->stats.rx_over_errors++;
759                         }
760                 }
761 
762                 rxbd->sl = RX_OWEN_DMA;
763                 rxbd->reserved = 0x0;
764 
765                 if (++ether->cur_rx >= RX_DESC_SIZE)
766                         ether->cur_rx = 0;
767 
768                 rxbd = &ether->rdesc->desclist[ether->cur_rx];
769 
770         } while (1);
771 }
772 
773 static irqreturn_t w90p910_rx_interrupt(int irq, void *dev_id)
774 {
775         struct net_device *dev;
776         struct w90p910_ether  *ether;
777         struct platform_device *pdev;
778         unsigned int status;
779 
780         dev = dev_id;
781         ether = netdev_priv(dev);
782         pdev = ether->pdev;
783 
784         w90p910_get_and_clear_int(dev, &status);
785 
786         if (status & MISTA_RDU) {
787                 netdev_rx(dev);
788                 w90p910_trigger_rx(dev);
789 
790                 return IRQ_HANDLED;
791         } else if (status & MISTA_RXBERR) {
792                 dev_err(&pdev->dev, "emc rx bus error\n");
793                 w90p910_reset_mac(dev);
794         }
795 
796         netdev_rx(dev);
797         return IRQ_HANDLED;
798 }
799 
800 static int w90p910_ether_open(struct net_device *dev)
801 {
802         struct w90p910_ether *ether;
803         struct platform_device *pdev;
804 
805         ether = netdev_priv(dev);
806         pdev = ether->pdev;
807 
808         w90p910_reset_mac(dev);
809         w90p910_set_fifo_threshold(dev);
810         w90p910_set_curdest(dev);
811         w90p910_enable_cam(dev);
812         w90p910_enable_cam_command(dev);
813         w90p910_enable_mac_interrupt(dev);
814         w90p910_set_global_maccmd(dev);
815         w90p910_enable_rx(dev, 1);
816 
817         clk_enable(ether->rmiiclk);
818         clk_enable(ether->clk);
819 
820         ether->rx_packets = 0x0;
821         ether->rx_bytes = 0x0;
822 
823         if (request_irq(ether->txirq, w90p910_tx_interrupt,
824                                                 0x0, pdev->name, dev)) {
825                 dev_err(&pdev->dev, "register irq tx failed\n");
826                 return -EAGAIN;
827         }
828 
829         if (request_irq(ether->rxirq, w90p910_rx_interrupt,
830                                                 0x0, pdev->name, dev)) {
831                 dev_err(&pdev->dev, "register irq rx failed\n");
832                 free_irq(ether->txirq, dev);
833                 return -EAGAIN;
834         }
835 
836         mod_timer(&ether->check_timer, jiffies + msecs_to_jiffies(1000));
837         netif_start_queue(dev);
838         w90p910_trigger_rx(dev);
839 
840         dev_info(&pdev->dev, "%s is OPENED\n", dev->name);
841 
842         return 0;
843 }
844 
845 static void w90p910_ether_set_multicast_list(struct net_device *dev)
846 {
847         struct w90p910_ether *ether;
848         unsigned int rx_mode;
849 
850         ether = netdev_priv(dev);
851 
852         if (dev->flags & IFF_PROMISC)
853                 rx_mode = CAMCMR_AUP | CAMCMR_AMP | CAMCMR_ABP | CAMCMR_ECMP;
854         else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev))
855                 rx_mode = CAMCMR_AMP | CAMCMR_ABP | CAMCMR_ECMP;
856         else
857                 rx_mode = CAMCMR_ECMP | CAMCMR_ABP;
858         __raw_writel(rx_mode, ether->reg + REG_CAMCMR);
859 }
860 
861 static int w90p910_ether_ioctl(struct net_device *dev,
862                                                 struct ifreq *ifr, int cmd)
863 {
864         struct w90p910_ether *ether = netdev_priv(dev);
865         struct mii_ioctl_data *data = if_mii(ifr);
866 
867         return generic_mii_ioctl(&ether->mii, data, cmd, NULL);
868 }
869 
870 static void w90p910_get_drvinfo(struct net_device *dev,
871                                         struct ethtool_drvinfo *info)
872 {
873         strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
874         strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
875 }
876 
877 static int w90p910_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
878 {
879         struct w90p910_ether *ether = netdev_priv(dev);
880         return mii_ethtool_gset(&ether->mii, cmd);
881 }
882 
883 static int w90p910_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
884 {
885         struct w90p910_ether *ether = netdev_priv(dev);
886         return mii_ethtool_sset(&ether->mii, cmd);
887 }
888 
889 static int w90p910_nway_reset(struct net_device *dev)
890 {
891         struct w90p910_ether *ether = netdev_priv(dev);
892         return mii_nway_restart(&ether->mii);
893 }
894 
895 static u32 w90p910_get_link(struct net_device *dev)
896 {
897         struct w90p910_ether *ether = netdev_priv(dev);
898         return mii_link_ok(&ether->mii);
899 }
900 
901 static const struct ethtool_ops w90p910_ether_ethtool_ops = {
902         .get_settings   = w90p910_get_settings,
903         .set_settings   = w90p910_set_settings,
904         .get_drvinfo    = w90p910_get_drvinfo,
905         .nway_reset     = w90p910_nway_reset,
906         .get_link       = w90p910_get_link,
907 };
908 
909 static const struct net_device_ops w90p910_ether_netdev_ops = {
910         .ndo_open               = w90p910_ether_open,
911         .ndo_stop               = w90p910_ether_close,
912         .ndo_start_xmit         = w90p910_ether_start_xmit,
913         .ndo_get_stats          = w90p910_ether_stats,
914         .ndo_set_rx_mode        = w90p910_ether_set_multicast_list,
915         .ndo_set_mac_address    = w90p910_set_mac_address,
916         .ndo_do_ioctl           = w90p910_ether_ioctl,
917         .ndo_validate_addr      = eth_validate_addr,
918         .ndo_change_mtu         = eth_change_mtu,
919 };
920 
921 static void __init get_mac_address(struct net_device *dev)
922 {
923         struct w90p910_ether *ether = netdev_priv(dev);
924         struct platform_device *pdev;
925         char addr[ETH_ALEN];
926 
927         pdev = ether->pdev;
928 
929         addr[0] = 0x00;
930         addr[1] = 0x02;
931         addr[2] = 0xac;
932         addr[3] = 0x55;
933         addr[4] = 0x88;
934         addr[5] = 0xa8;
935 
936         if (is_valid_ether_addr(addr))
937                 memcpy(dev->dev_addr, &addr, ETH_ALEN);
938         else
939                 dev_err(&pdev->dev, "invalid mac address\n");
940 }
941 
942 static int w90p910_ether_setup(struct net_device *dev)
943 {
944         struct w90p910_ether *ether = netdev_priv(dev);
945 
946         ether_setup(dev);
947         dev->netdev_ops = &w90p910_ether_netdev_ops;
948         dev->ethtool_ops = &w90p910_ether_ethtool_ops;
949 
950         dev->tx_queue_len = 16;
951         dev->dma = 0x0;
952         dev->watchdog_timeo = TX_TIMEOUT;
953 
954         get_mac_address(dev);
955 
956         ether->cur_tx = 0x0;
957         ether->cur_rx = 0x0;
958         ether->finish_tx = 0x0;
959         ether->linkflag = 0x0;
960         ether->mii.phy_id = 0x01;
961         ether->mii.phy_id_mask = 0x1f;
962         ether->mii.reg_num_mask = 0x1f;
963         ether->mii.dev = dev;
964         ether->mii.mdio_read = w90p910_mdio_read;
965         ether->mii.mdio_write = w90p910_mdio_write;
966 
967         setup_timer(&ether->check_timer, w90p910_check_link,
968                                                 (unsigned long)dev);
969 
970         return 0;
971 }
972 
973 static int w90p910_ether_probe(struct platform_device *pdev)
974 {
975         struct w90p910_ether *ether;
976         struct net_device *dev;
977         int error;
978 
979         dev = alloc_etherdev(sizeof(struct w90p910_ether));
980         if (!dev)
981                 return -ENOMEM;
982 
983         ether = netdev_priv(dev);
984 
985         ether->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
986         if (ether->res == NULL) {
987                 dev_err(&pdev->dev, "failed to get I/O memory\n");
988                 error = -ENXIO;
989                 goto failed_free;
990         }
991 
992         if (!request_mem_region(ether->res->start,
993                                 resource_size(ether->res), pdev->name)) {
994                 dev_err(&pdev->dev, "failed to request I/O memory\n");
995                 error = -EBUSY;
996                 goto failed_free;
997         }
998 
999         ether->reg = ioremap(ether->res->start, resource_size(ether->res));
1000         if (ether->reg == NULL) {
1001                 dev_err(&pdev->dev, "failed to remap I/O memory\n");
1002                 error = -ENXIO;
1003                 goto failed_free_mem;
1004         }
1005 
1006         ether->txirq = platform_get_irq(pdev, 0);
1007         if (ether->txirq < 0) {
1008                 dev_err(&pdev->dev, "failed to get ether tx irq\n");
1009                 error = -ENXIO;
1010                 goto failed_free_io;
1011         }
1012 
1013         ether->rxirq = platform_get_irq(pdev, 1);
1014         if (ether->rxirq < 0) {
1015                 dev_err(&pdev->dev, "failed to get ether rx irq\n");
1016                 error = -ENXIO;
1017                 goto failed_free_io;
1018         }
1019 
1020         platform_set_drvdata(pdev, dev);
1021 
1022         ether->clk = clk_get(&pdev->dev, NULL);
1023         if (IS_ERR(ether->clk)) {
1024                 dev_err(&pdev->dev, "failed to get ether clock\n");
1025                 error = PTR_ERR(ether->clk);
1026                 goto failed_free_io;
1027         }
1028 
1029         ether->rmiiclk = clk_get(&pdev->dev, "RMII");
1030         if (IS_ERR(ether->rmiiclk)) {
1031                 dev_err(&pdev->dev, "failed to get ether clock\n");
1032                 error = PTR_ERR(ether->rmiiclk);
1033                 goto failed_put_clk;
1034         }
1035 
1036         ether->pdev = pdev;
1037 
1038         w90p910_ether_setup(dev);
1039 
1040         error = register_netdev(dev);
1041         if (error != 0) {
1042                 dev_err(&pdev->dev, "Regiter EMC w90p910 FAILED\n");
1043                 error = -ENODEV;
1044                 goto failed_put_rmiiclk;
1045         }
1046 
1047         return 0;
1048 failed_put_rmiiclk:
1049         clk_put(ether->rmiiclk);
1050 failed_put_clk:
1051         clk_put(ether->clk);
1052 failed_free_io:
1053         iounmap(ether->reg);
1054 failed_free_mem:
1055         release_mem_region(ether->res->start, resource_size(ether->res));
1056 failed_free:
1057         free_netdev(dev);
1058         return error;
1059 }
1060 
1061 static int w90p910_ether_remove(struct platform_device *pdev)
1062 {
1063         struct net_device *dev = platform_get_drvdata(pdev);
1064         struct w90p910_ether *ether = netdev_priv(dev);
1065 
1066         unregister_netdev(dev);
1067 
1068         clk_put(ether->rmiiclk);
1069         clk_put(ether->clk);
1070 
1071         iounmap(ether->reg);
1072         release_mem_region(ether->res->start, resource_size(ether->res));
1073 
1074         del_timer_sync(&ether->check_timer);
1075 
1076         free_netdev(dev);
1077         return 0;
1078 }
1079 
1080 static struct platform_driver w90p910_ether_driver = {
1081         .probe          = w90p910_ether_probe,
1082         .remove         = w90p910_ether_remove,
1083         .driver         = {
1084                 .name   = "nuc900-emc",
1085                 .owner  = THIS_MODULE,
1086         },
1087 };
1088 
1089 module_platform_driver(w90p910_ether_driver);
1090 
1091 MODULE_AUTHOR("Wan ZongShun <mcuos.com@gmail.com>");
1092 MODULE_DESCRIPTION("w90p910 MAC driver!");
1093 MODULE_LICENSE("GPL");
1094 MODULE_ALIAS("platform:nuc900-emc");
1095 
1096 

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