Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/net/ethernet/moxa/moxart_ether.c

  1 /* MOXA ART Ethernet (RTL8201CP) driver.
  2  *
  3  * Copyright (C) 2013 Jonas Jensen
  4  *
  5  * Jonas Jensen <jonas.jensen@gmail.com>
  6  *
  7  * Based on code from
  8  * Moxa Technology Co., Ltd. <www.moxa.com>
  9  *
 10  * This file is licensed under the terms of the GNU General Public
 11  * License version 2.  This program is licensed "as is" without any
 12  * warranty of any kind, whether express or implied.
 13  */
 14 
 15 #include <linux/module.h>
 16 #include <linux/netdevice.h>
 17 #include <linux/etherdevice.h>
 18 #include <linux/skbuff.h>
 19 #include <linux/dma-mapping.h>
 20 #include <linux/ethtool.h>
 21 #include <linux/platform_device.h>
 22 #include <linux/interrupt.h>
 23 #include <linux/irq.h>
 24 #include <linux/of_address.h>
 25 #include <linux/of_irq.h>
 26 #include <linux/crc32.h>
 27 #include <linux/crc32c.h>
 28 
 29 #include "moxart_ether.h"
 30 
 31 static inline void moxart_emac_write(struct net_device *ndev,
 32                                      unsigned int reg, unsigned long value)
 33 {
 34         struct moxart_mac_priv_t *priv = netdev_priv(ndev);
 35 
 36         writel(value, priv->base + reg);
 37 }
 38 
 39 static void moxart_update_mac_address(struct net_device *ndev)
 40 {
 41         moxart_emac_write(ndev, REG_MAC_MS_ADDRESS,
 42                           ((ndev->dev_addr[0] << 8) | (ndev->dev_addr[1])));
 43         moxart_emac_write(ndev, REG_MAC_MS_ADDRESS + 4,
 44                           ((ndev->dev_addr[2] << 24) |
 45                            (ndev->dev_addr[3] << 16) |
 46                            (ndev->dev_addr[4] << 8) |
 47                            (ndev->dev_addr[5])));
 48 }
 49 
 50 static int moxart_set_mac_address(struct net_device *ndev, void *addr)
 51 {
 52         struct sockaddr *address = addr;
 53 
 54         if (!is_valid_ether_addr(address->sa_data))
 55                 return -EADDRNOTAVAIL;
 56 
 57         memcpy(ndev->dev_addr, address->sa_data, ndev->addr_len);
 58         moxart_update_mac_address(ndev);
 59 
 60         return 0;
 61 }
 62 
 63 static void moxart_mac_free_memory(struct net_device *ndev)
 64 {
 65         struct moxart_mac_priv_t *priv = netdev_priv(ndev);
 66         int i;
 67 
 68         for (i = 0; i < RX_DESC_NUM; i++)
 69                 dma_unmap_single(&ndev->dev, priv->rx_mapping[i],
 70                                  priv->rx_buf_size, DMA_FROM_DEVICE);
 71 
 72         if (priv->tx_desc_base)
 73                 dma_free_coherent(NULL, TX_REG_DESC_SIZE * TX_DESC_NUM,
 74                                   priv->tx_desc_base, priv->tx_base);
 75 
 76         if (priv->rx_desc_base)
 77                 dma_free_coherent(NULL, RX_REG_DESC_SIZE * RX_DESC_NUM,
 78                                   priv->rx_desc_base, priv->rx_base);
 79 
 80         kfree(priv->tx_buf_base);
 81         kfree(priv->rx_buf_base);
 82 }
 83 
 84 static void moxart_mac_reset(struct net_device *ndev)
 85 {
 86         struct moxart_mac_priv_t *priv = netdev_priv(ndev);
 87 
 88         writel(SW_RST, priv->base + REG_MAC_CTRL);
 89         while (readl(priv->base + REG_MAC_CTRL) & SW_RST)
 90                 mdelay(10);
 91 
 92         writel(0, priv->base + REG_INTERRUPT_MASK);
 93 
 94         priv->reg_maccr = RX_BROADPKT | FULLDUP | CRC_APD | RX_FTL;
 95 }
 96 
 97 static void moxart_mac_enable(struct net_device *ndev)
 98 {
 99         struct moxart_mac_priv_t *priv = netdev_priv(ndev);
100 
101         writel(0x00001010, priv->base + REG_INT_TIMER_CTRL);
102         writel(0x00000001, priv->base + REG_APOLL_TIMER_CTRL);
103         writel(0x00000390, priv->base + REG_DMA_BLEN_CTRL);
104 
105         priv->reg_imr |= (RPKT_FINISH_M | XPKT_FINISH_M);
106         writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK);
107 
108         priv->reg_maccr |= (RCV_EN | XMT_EN | RDMA_EN | XDMA_EN);
109         writel(priv->reg_maccr, priv->base + REG_MAC_CTRL);
110 }
111 
112 static void moxart_mac_setup_desc_ring(struct net_device *ndev)
113 {
114         struct moxart_mac_priv_t *priv = netdev_priv(ndev);
115         void __iomem *desc;
116         int i;
117 
118         for (i = 0; i < TX_DESC_NUM; i++) {
119                 desc = priv->tx_desc_base + i * TX_REG_DESC_SIZE;
120                 memset(desc, 0, TX_REG_DESC_SIZE);
121 
122                 priv->tx_buf[i] = priv->tx_buf_base + priv->tx_buf_size * i;
123         }
124         writel(TX_DESC1_END, desc + TX_REG_OFFSET_DESC1);
125 
126         priv->tx_head = 0;
127         priv->tx_tail = 0;
128 
129         for (i = 0; i < RX_DESC_NUM; i++) {
130                 desc = priv->rx_desc_base + i * RX_REG_DESC_SIZE;
131                 memset(desc, 0, RX_REG_DESC_SIZE);
132                 writel(RX_DESC0_DMA_OWN, desc + RX_REG_OFFSET_DESC0);
133                 writel(RX_BUF_SIZE & RX_DESC1_BUF_SIZE_MASK,
134                        desc + RX_REG_OFFSET_DESC1);
135 
136                 priv->rx_buf[i] = priv->rx_buf_base + priv->rx_buf_size * i;
137                 priv->rx_mapping[i] = dma_map_single(&ndev->dev,
138                                                      priv->rx_buf[i],
139                                                      priv->rx_buf_size,
140                                                      DMA_FROM_DEVICE);
141                 if (dma_mapping_error(&ndev->dev, priv->rx_mapping[i]))
142                         netdev_err(ndev, "DMA mapping error\n");
143 
144                 writel(priv->rx_mapping[i],
145                        desc + RX_REG_OFFSET_DESC2 + RX_DESC2_ADDRESS_PHYS);
146                 writel(priv->rx_buf[i],
147                        desc + RX_REG_OFFSET_DESC2 + RX_DESC2_ADDRESS_VIRT);
148         }
149         writel(RX_DESC1_END, desc + RX_REG_OFFSET_DESC1);
150 
151         priv->rx_head = 0;
152 
153         /* reset the MAC controler TX/RX desciptor base address */
154         writel(priv->tx_base, priv->base + REG_TXR_BASE_ADDRESS);
155         writel(priv->rx_base, priv->base + REG_RXR_BASE_ADDRESS);
156 }
157 
158 static int moxart_mac_open(struct net_device *ndev)
159 {
160         struct moxart_mac_priv_t *priv = netdev_priv(ndev);
161 
162         if (!is_valid_ether_addr(ndev->dev_addr))
163                 return -EADDRNOTAVAIL;
164 
165         napi_enable(&priv->napi);
166 
167         moxart_mac_reset(ndev);
168         moxart_update_mac_address(ndev);
169         moxart_mac_setup_desc_ring(ndev);
170         moxart_mac_enable(ndev);
171         netif_start_queue(ndev);
172 
173         netdev_dbg(ndev, "%s: IMR=0x%x, MACCR=0x%x\n",
174                    __func__, readl(priv->base + REG_INTERRUPT_MASK),
175                    readl(priv->base + REG_MAC_CTRL));
176 
177         return 0;
178 }
179 
180 static int moxart_mac_stop(struct net_device *ndev)
181 {
182         struct moxart_mac_priv_t *priv = netdev_priv(ndev);
183 
184         napi_disable(&priv->napi);
185 
186         netif_stop_queue(ndev);
187 
188         /* disable all interrupts */
189         writel(0, priv->base + REG_INTERRUPT_MASK);
190 
191         /* disable all functions */
192         writel(0, priv->base + REG_MAC_CTRL);
193 
194         return 0;
195 }
196 
197 static int moxart_rx_poll(struct napi_struct *napi, int budget)
198 {
199         struct moxart_mac_priv_t *priv = container_of(napi,
200                                                       struct moxart_mac_priv_t,
201                                                       napi);
202         struct net_device *ndev = priv->ndev;
203         struct sk_buff *skb;
204         void __iomem *desc;
205         unsigned int desc0, len;
206         int rx_head = priv->rx_head;
207         int rx = 0;
208 
209         while (rx < budget) {
210                 desc = priv->rx_desc_base + (RX_REG_DESC_SIZE * rx_head);
211                 desc0 = readl(desc + RX_REG_OFFSET_DESC0);
212 
213                 if (desc0 & RX_DESC0_DMA_OWN)
214                         break;
215 
216                 if (desc0 & (RX_DESC0_ERR | RX_DESC0_CRC_ERR | RX_DESC0_FTL |
217                              RX_DESC0_RUNT | RX_DESC0_ODD_NB)) {
218                         net_dbg_ratelimited("packet error\n");
219                         priv->stats.rx_dropped++;
220                         priv->stats.rx_errors++;
221                         goto rx_next;
222                 }
223 
224                 len = desc0 & RX_DESC0_FRAME_LEN_MASK;
225 
226                 if (len > RX_BUF_SIZE)
227                         len = RX_BUF_SIZE;
228 
229                 dma_sync_single_for_cpu(&ndev->dev,
230                                         priv->rx_mapping[rx_head],
231                                         priv->rx_buf_size, DMA_FROM_DEVICE);
232                 skb = netdev_alloc_skb_ip_align(ndev, len);
233 
234                 if (unlikely(!skb)) {
235                         net_dbg_ratelimited("netdev_alloc_skb_ip_align failed\n");
236                         priv->stats.rx_dropped++;
237                         priv->stats.rx_errors++;
238                         goto rx_next;
239                 }
240 
241                 memcpy(skb->data, priv->rx_buf[rx_head], len);
242                 skb_put(skb, len);
243                 skb->protocol = eth_type_trans(skb, ndev);
244                 napi_gro_receive(&priv->napi, skb);
245                 rx++;
246 
247                 ndev->last_rx = jiffies;
248                 priv->stats.rx_packets++;
249                 priv->stats.rx_bytes += len;
250                 if (desc0 & RX_DESC0_MULTICAST)
251                         priv->stats.multicast++;
252 
253 rx_next:
254                 writel(RX_DESC0_DMA_OWN, desc + RX_REG_OFFSET_DESC0);
255 
256                 rx_head = RX_NEXT(rx_head);
257                 priv->rx_head = rx_head;
258         }
259 
260         if (rx < budget) {
261                 napi_complete(napi);
262         }
263 
264         priv->reg_imr |= RPKT_FINISH_M;
265         writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK);
266 
267         return rx;
268 }
269 
270 static void moxart_tx_finished(struct net_device *ndev)
271 {
272         struct moxart_mac_priv_t *priv = netdev_priv(ndev);
273         unsigned tx_head = priv->tx_head;
274         unsigned tx_tail = priv->tx_tail;
275 
276         while (tx_tail != tx_head) {
277                 dma_unmap_single(&ndev->dev, priv->tx_mapping[tx_tail],
278                                  priv->tx_len[tx_tail], DMA_TO_DEVICE);
279 
280                 priv->stats.tx_packets++;
281                 priv->stats.tx_bytes += priv->tx_skb[tx_tail]->len;
282 
283                 dev_kfree_skb_irq(priv->tx_skb[tx_tail]);
284                 priv->tx_skb[tx_tail] = NULL;
285 
286                 tx_tail = TX_NEXT(tx_tail);
287         }
288         priv->tx_tail = tx_tail;
289 }
290 
291 static irqreturn_t moxart_mac_interrupt(int irq, void *dev_id)
292 {
293         struct net_device *ndev = (struct net_device *) dev_id;
294         struct moxart_mac_priv_t *priv = netdev_priv(ndev);
295         unsigned int ists = readl(priv->base + REG_INTERRUPT_STATUS);
296 
297         if (ists & XPKT_OK_INT_STS)
298                 moxart_tx_finished(ndev);
299 
300         if (ists & RPKT_FINISH) {
301                 if (napi_schedule_prep(&priv->napi)) {
302                         priv->reg_imr &= ~RPKT_FINISH_M;
303                         writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK);
304                         __napi_schedule(&priv->napi);
305                 }
306         }
307 
308         return IRQ_HANDLED;
309 }
310 
311 static int moxart_mac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
312 {
313         struct moxart_mac_priv_t *priv = netdev_priv(ndev);
314         void __iomem *desc;
315         unsigned int len;
316         unsigned int tx_head = priv->tx_head;
317         u32 txdes1;
318         int ret = NETDEV_TX_BUSY;
319 
320         desc = priv->tx_desc_base + (TX_REG_DESC_SIZE * tx_head);
321 
322         spin_lock_irq(&priv->txlock);
323         if (readl(desc + TX_REG_OFFSET_DESC0) & TX_DESC0_DMA_OWN) {
324                 net_dbg_ratelimited("no TX space for packet\n");
325                 priv->stats.tx_dropped++;
326                 goto out_unlock;
327         }
328 
329         len = skb->len > TX_BUF_SIZE ? TX_BUF_SIZE : skb->len;
330 
331         priv->tx_mapping[tx_head] = dma_map_single(&ndev->dev, skb->data,
332                                                    len, DMA_TO_DEVICE);
333         if (dma_mapping_error(&ndev->dev, priv->tx_mapping[tx_head])) {
334                 netdev_err(ndev, "DMA mapping error\n");
335                 goto out_unlock;
336         }
337 
338         priv->tx_len[tx_head] = len;
339         priv->tx_skb[tx_head] = skb;
340 
341         writel(priv->tx_mapping[tx_head],
342                desc + TX_REG_OFFSET_DESC2 + TX_DESC2_ADDRESS_PHYS);
343         writel(skb->data,
344                desc + TX_REG_OFFSET_DESC2 + TX_DESC2_ADDRESS_VIRT);
345 
346         if (skb->len < ETH_ZLEN) {
347                 memset(&skb->data[skb->len],
348                        0, ETH_ZLEN - skb->len);
349                 len = ETH_ZLEN;
350         }
351 
352         dma_sync_single_for_device(&ndev->dev, priv->tx_mapping[tx_head],
353                                    priv->tx_buf_size, DMA_TO_DEVICE);
354 
355         txdes1 = TX_DESC1_LTS | TX_DESC1_FTS | (len & TX_DESC1_BUF_SIZE_MASK);
356         if (tx_head == TX_DESC_NUM_MASK)
357                 txdes1 |= TX_DESC1_END;
358         writel(txdes1, desc + TX_REG_OFFSET_DESC1);
359         writel(TX_DESC0_DMA_OWN, desc + TX_REG_OFFSET_DESC0);
360 
361         /* start to send packet */
362         writel(0xffffffff, priv->base + REG_TX_POLL_DEMAND);
363 
364         priv->tx_head = TX_NEXT(tx_head);
365 
366         ndev->trans_start = jiffies;
367         ret = NETDEV_TX_OK;
368 out_unlock:
369         spin_unlock_irq(&priv->txlock);
370 
371         return ret;
372 }
373 
374 static struct net_device_stats *moxart_mac_get_stats(struct net_device *ndev)
375 {
376         struct moxart_mac_priv_t *priv = netdev_priv(ndev);
377 
378         return &priv->stats;
379 }
380 
381 static void moxart_mac_setmulticast(struct net_device *ndev)
382 {
383         struct moxart_mac_priv_t *priv = netdev_priv(ndev);
384         struct netdev_hw_addr *ha;
385         int crc_val;
386 
387         netdev_for_each_mc_addr(ha, ndev) {
388                 crc_val = crc32_le(~0, ha->addr, ETH_ALEN);
389                 crc_val = (crc_val >> 26) & 0x3f;
390                 if (crc_val >= 32) {
391                         writel(readl(priv->base + REG_MCAST_HASH_TABLE1) |
392                                (1UL << (crc_val - 32)),
393                                priv->base + REG_MCAST_HASH_TABLE1);
394                 } else {
395                         writel(readl(priv->base + REG_MCAST_HASH_TABLE0) |
396                                (1UL << crc_val),
397                                priv->base + REG_MCAST_HASH_TABLE0);
398                 }
399         }
400 }
401 
402 static void moxart_mac_set_rx_mode(struct net_device *ndev)
403 {
404         struct moxart_mac_priv_t *priv = netdev_priv(ndev);
405 
406         spin_lock_irq(&priv->txlock);
407 
408         (ndev->flags & IFF_PROMISC) ? (priv->reg_maccr |= RCV_ALL) :
409                                       (priv->reg_maccr &= ~RCV_ALL);
410 
411         (ndev->flags & IFF_ALLMULTI) ? (priv->reg_maccr |= RX_MULTIPKT) :
412                                        (priv->reg_maccr &= ~RX_MULTIPKT);
413 
414         if ((ndev->flags & IFF_MULTICAST) && netdev_mc_count(ndev)) {
415                 priv->reg_maccr |= HT_MULTI_EN;
416                 moxart_mac_setmulticast(ndev);
417         } else {
418                 priv->reg_maccr &= ~HT_MULTI_EN;
419         }
420 
421         writel(priv->reg_maccr, priv->base + REG_MAC_CTRL);
422 
423         spin_unlock_irq(&priv->txlock);
424 }
425 
426 static struct net_device_ops moxart_netdev_ops = {
427         .ndo_open               = moxart_mac_open,
428         .ndo_stop               = moxart_mac_stop,
429         .ndo_start_xmit         = moxart_mac_start_xmit,
430         .ndo_get_stats          = moxart_mac_get_stats,
431         .ndo_set_rx_mode        = moxart_mac_set_rx_mode,
432         .ndo_set_mac_address    = moxart_set_mac_address,
433         .ndo_validate_addr      = eth_validate_addr,
434         .ndo_change_mtu         = eth_change_mtu,
435 };
436 
437 static int moxart_mac_probe(struct platform_device *pdev)
438 {
439         struct device *p_dev = &pdev->dev;
440         struct device_node *node = p_dev->of_node;
441         struct net_device *ndev;
442         struct moxart_mac_priv_t *priv;
443         struct resource *res;
444         unsigned int irq;
445         int ret;
446 
447         ndev = alloc_etherdev(sizeof(struct moxart_mac_priv_t));
448         if (!ndev)
449                 return -ENOMEM;
450 
451         irq = irq_of_parse_and_map(node, 0);
452         if (irq <= 0) {
453                 netdev_err(ndev, "irq_of_parse_and_map failed\n");
454                 ret = -EINVAL;
455                 goto irq_map_fail;
456         }
457 
458         priv = netdev_priv(ndev);
459         priv->ndev = ndev;
460 
461         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
462         ndev->base_addr = res->start;
463         priv->base = devm_ioremap_resource(p_dev, res);
464         ret = IS_ERR(priv->base);
465         if (ret) {
466                 dev_err(p_dev, "devm_ioremap_resource failed\n");
467                 goto init_fail;
468         }
469 
470         spin_lock_init(&priv->txlock);
471 
472         priv->tx_buf_size = TX_BUF_SIZE;
473         priv->rx_buf_size = RX_BUF_SIZE;
474 
475         priv->tx_desc_base = dma_alloc_coherent(NULL, TX_REG_DESC_SIZE *
476                                                 TX_DESC_NUM, &priv->tx_base,
477                                                 GFP_DMA | GFP_KERNEL);
478         if (priv->tx_desc_base == NULL) {
479                 ret = -ENOMEM;
480                 goto init_fail;
481         }
482 
483         priv->rx_desc_base = dma_alloc_coherent(NULL, RX_REG_DESC_SIZE *
484                                                 RX_DESC_NUM, &priv->rx_base,
485                                                 GFP_DMA | GFP_KERNEL);
486         if (priv->rx_desc_base == NULL) {
487                 ret = -ENOMEM;
488                 goto init_fail;
489         }
490 
491         priv->tx_buf_base = kmalloc(priv->tx_buf_size * TX_DESC_NUM,
492                                     GFP_ATOMIC);
493         if (!priv->tx_buf_base) {
494                 ret = -ENOMEM;
495                 goto init_fail;
496         }
497 
498         priv->rx_buf_base = kmalloc(priv->rx_buf_size * RX_DESC_NUM,
499                                     GFP_ATOMIC);
500         if (!priv->rx_buf_base) {
501                 ret = -ENOMEM;
502                 goto init_fail;
503         }
504 
505         platform_set_drvdata(pdev, ndev);
506 
507         ret = devm_request_irq(p_dev, irq, moxart_mac_interrupt, 0,
508                                pdev->name, ndev);
509         if (ret) {
510                 netdev_err(ndev, "devm_request_irq failed\n");
511                 goto init_fail;
512         }
513 
514         ether_setup(ndev);
515         ndev->netdev_ops = &moxart_netdev_ops;
516         netif_napi_add(ndev, &priv->napi, moxart_rx_poll, RX_DESC_NUM);
517         ndev->priv_flags |= IFF_UNICAST_FLT;
518         ndev->irq = irq;
519 
520         SET_NETDEV_DEV(ndev, &pdev->dev);
521 
522         ret = register_netdev(ndev);
523         if (ret) {
524                 free_netdev(ndev);
525                 goto init_fail;
526         }
527 
528         netdev_dbg(ndev, "%s: IRQ=%d address=%pM\n",
529                    __func__, ndev->irq, ndev->dev_addr);
530 
531         return 0;
532 
533 init_fail:
534         netdev_err(ndev, "init failed\n");
535         moxart_mac_free_memory(ndev);
536 irq_map_fail:
537         free_netdev(ndev);
538         return ret;
539 }
540 
541 static int moxart_remove(struct platform_device *pdev)
542 {
543         struct net_device *ndev = platform_get_drvdata(pdev);
544 
545         unregister_netdev(ndev);
546         free_irq(ndev->irq, ndev);
547         moxart_mac_free_memory(ndev);
548         free_netdev(ndev);
549 
550         return 0;
551 }
552 
553 static const struct of_device_id moxart_mac_match[] = {
554         { .compatible = "moxa,moxart-mac" },
555         { }
556 };
557 
558 static struct platform_driver moxart_mac_driver = {
559         .probe  = moxart_mac_probe,
560         .remove = moxart_remove,
561         .driver = {
562                 .name           = "moxart-ethernet",
563                 .owner          = THIS_MODULE,
564                 .of_match_table = moxart_mac_match,
565         },
566 };
567 module_platform_driver(moxart_mac_driver);
568 
569 MODULE_DESCRIPTION("MOXART RTL8201CP Ethernet driver");
570 MODULE_LICENSE("GPL v2");
571 MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>");
572 

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