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Linux/drivers/net/ethernet/marvell/pxa168_eth.c

  1 /*
  2  * PXA168 ethernet driver.
  3  * Most of the code is derived from mv643xx ethernet driver.
  4  *
  5  * Copyright (C) 2010 Marvell International Ltd.
  6  *              Sachin Sanap <ssanap@marvell.com>
  7  *              Zhangfei Gao <zgao6@marvell.com>
  8  *              Philip Rakity <prakity@marvell.com>
  9  *              Mark Brown <markb@marvell.com>
 10  *
 11  * This program is free software; you can redistribute it and/or
 12  * modify it under the terms of the GNU General Public License
 13  * as published by the Free Software Foundation; either version 2
 14  * of the License, or (at your option) any later version.
 15  *
 16  * This program is distributed in the hope that it will be useful,
 17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 19  * GNU General Public License for more details.
 20  *
 21  * You should have received a copy of the GNU General Public License
 22  * along with this program; if not, see <http://www.gnu.org/licenses/>.
 23  */
 24 
 25 #include <linux/bitops.h>
 26 #include <linux/clk.h>
 27 #include <linux/delay.h>
 28 #include <linux/dma-mapping.h>
 29 #include <linux/etherdevice.h>
 30 #include <linux/ethtool.h>
 31 #include <linux/in.h>
 32 #include <linux/interrupt.h>
 33 #include <linux/io.h>
 34 #include <linux/ip.h>
 35 #include <linux/kernel.h>
 36 #include <linux/module.h>
 37 #include <linux/of.h>
 38 #include <linux/of_net.h>
 39 #include <linux/phy.h>
 40 #include <linux/platform_device.h>
 41 #include <linux/pxa168_eth.h>
 42 #include <linux/tcp.h>
 43 #include <linux/types.h>
 44 #include <linux/udp.h>
 45 #include <linux/workqueue.h>
 46 
 47 #include <asm/pgtable.h>
 48 #include <asm/cacheflush.h>
 49 
 50 #define DRIVER_NAME     "pxa168-eth"
 51 #define DRIVER_VERSION  "0.3"
 52 
 53 /*
 54  * Registers
 55  */
 56 
 57 #define PHY_ADDRESS             0x0000
 58 #define SMI                     0x0010
 59 #define PORT_CONFIG             0x0400
 60 #define PORT_CONFIG_EXT         0x0408
 61 #define PORT_COMMAND            0x0410
 62 #define PORT_STATUS             0x0418
 63 #define HTPR                    0x0428
 64 #define MAC_ADDR_LOW            0x0430
 65 #define MAC_ADDR_HIGH           0x0438
 66 #define SDMA_CONFIG             0x0440
 67 #define SDMA_CMD                0x0448
 68 #define INT_CAUSE               0x0450
 69 #define INT_W_CLEAR             0x0454
 70 #define INT_MASK                0x0458
 71 #define ETH_F_RX_DESC_0         0x0480
 72 #define ETH_C_RX_DESC_0         0x04A0
 73 #define ETH_C_TX_DESC_1         0x04E4
 74 
 75 /* smi register */
 76 #define SMI_BUSY                (1 << 28)       /* 0 - Write, 1 - Read  */
 77 #define SMI_R_VALID             (1 << 27)       /* 0 - Write, 1 - Read  */
 78 #define SMI_OP_W                (0 << 26)       /* Write operation      */
 79 #define SMI_OP_R                (1 << 26)       /* Read operation */
 80 
 81 #define PHY_WAIT_ITERATIONS     10
 82 
 83 #define PXA168_ETH_PHY_ADDR_DEFAULT     0
 84 /* RX & TX descriptor command */
 85 #define BUF_OWNED_BY_DMA        (1 << 31)
 86 
 87 /* RX descriptor status */
 88 #define RX_EN_INT               (1 << 23)
 89 #define RX_FIRST_DESC           (1 << 17)
 90 #define RX_LAST_DESC            (1 << 16)
 91 #define RX_ERROR                (1 << 15)
 92 
 93 /* TX descriptor command */
 94 #define TX_EN_INT               (1 << 23)
 95 #define TX_GEN_CRC              (1 << 22)
 96 #define TX_ZERO_PADDING         (1 << 18)
 97 #define TX_FIRST_DESC           (1 << 17)
 98 #define TX_LAST_DESC            (1 << 16)
 99 #define TX_ERROR                (1 << 15)
100 
101 /* SDMA_CMD */
102 #define SDMA_CMD_AT             (1 << 31)
103 #define SDMA_CMD_TXDL           (1 << 24)
104 #define SDMA_CMD_TXDH           (1 << 23)
105 #define SDMA_CMD_AR             (1 << 15)
106 #define SDMA_CMD_ERD            (1 << 7)
107 
108 /* Bit definitions of the Port Config Reg */
109 #define PCR_DUPLEX_FULL         (1 << 15)
110 #define PCR_HS                  (1 << 12)
111 #define PCR_EN                  (1 << 7)
112 #define PCR_PM                  (1 << 0)
113 
114 /* Bit definitions of the Port Config Extend Reg */
115 #define PCXR_2BSM               (1 << 28)
116 #define PCXR_DSCP_EN            (1 << 21)
117 #define PCXR_RMII_EN            (1 << 20)
118 #define PCXR_AN_SPEED_DIS       (1 << 19)
119 #define PCXR_SPEED_100          (1 << 18)
120 #define PCXR_MFL_1518           (0 << 14)
121 #define PCXR_MFL_1536           (1 << 14)
122 #define PCXR_MFL_2048           (2 << 14)
123 #define PCXR_MFL_64K            (3 << 14)
124 #define PCXR_FLOWCTL_DIS        (1 << 12)
125 #define PCXR_FLP                (1 << 11)
126 #define PCXR_AN_FLOWCTL_DIS     (1 << 10)
127 #define PCXR_AN_DUPLEX_DIS      (1 << 9)
128 #define PCXR_PRIO_TX_OFF        3
129 #define PCXR_TX_HIGH_PRI        (7 << PCXR_PRIO_TX_OFF)
130 
131 /* Bit definitions of the SDMA Config Reg */
132 #define SDCR_BSZ_OFF            12
133 #define SDCR_BSZ8               (3 << SDCR_BSZ_OFF)
134 #define SDCR_BSZ4               (2 << SDCR_BSZ_OFF)
135 #define SDCR_BSZ2               (1 << SDCR_BSZ_OFF)
136 #define SDCR_BSZ1               (0 << SDCR_BSZ_OFF)
137 #define SDCR_BLMR               (1 << 6)
138 #define SDCR_BLMT               (1 << 7)
139 #define SDCR_RIFB               (1 << 9)
140 #define SDCR_RC_OFF             2
141 #define SDCR_RC_MAX_RETRANS     (0xf << SDCR_RC_OFF)
142 
143 /*
144  * Bit definitions of the Interrupt Cause Reg
145  * and Interrupt MASK Reg is the same
146  */
147 #define ICR_RXBUF               (1 << 0)
148 #define ICR_TXBUF_H             (1 << 2)
149 #define ICR_TXBUF_L             (1 << 3)
150 #define ICR_TXEND_H             (1 << 6)
151 #define ICR_TXEND_L             (1 << 7)
152 #define ICR_RXERR               (1 << 8)
153 #define ICR_TXERR_H             (1 << 10)
154 #define ICR_TXERR_L             (1 << 11)
155 #define ICR_TX_UDR              (1 << 13)
156 #define ICR_MII_CH              (1 << 28)
157 
158 #define ALL_INTS (ICR_TXBUF_H  | ICR_TXBUF_L  | ICR_TX_UDR |\
159                                 ICR_TXERR_H  | ICR_TXERR_L |\
160                                 ICR_TXEND_H  | ICR_TXEND_L |\
161                                 ICR_RXBUF | ICR_RXERR  | ICR_MII_CH)
162 
163 #define ETH_HW_IP_ALIGN         2       /* hw aligns IP header */
164 
165 #define NUM_RX_DESCS            64
166 #define NUM_TX_DESCS            64
167 
168 #define HASH_ADD                0
169 #define HASH_DELETE             1
170 #define HASH_ADDR_TABLE_SIZE    0x4000  /* 16K (1/2K address - PCR_HS == 1) */
171 #define HOP_NUMBER              12
172 
173 /* Bit definitions for Port status */
174 #define PORT_SPEED_100          (1 << 0)
175 #define FULL_DUPLEX             (1 << 1)
176 #define FLOW_CONTROL_DISABLED   (1 << 2)
177 #define LINK_UP                 (1 << 3)
178 
179 /* Bit definitions for work to be done */
180 #define WORK_TX_DONE            (1 << 1)
181 
182 /*
183  * Misc definitions.
184  */
185 #define SKB_DMA_REALIGN         ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
186 
187 struct rx_desc {
188         u32 cmd_sts;            /* Descriptor command status            */
189         u16 byte_cnt;           /* Descriptor buffer byte count         */
190         u16 buf_size;           /* Buffer size                          */
191         u32 buf_ptr;            /* Descriptor buffer pointer            */
192         u32 next_desc_ptr;      /* Next descriptor pointer              */
193 };
194 
195 struct tx_desc {
196         u32 cmd_sts;            /* Command/status field                 */
197         u16 reserved;
198         u16 byte_cnt;           /* buffer byte count                    */
199         u32 buf_ptr;            /* pointer to buffer for this descriptor */
200         u32 next_desc_ptr;      /* Pointer to next descriptor           */
201 };
202 
203 struct pxa168_eth_private {
204         int port_num;           /* User Ethernet port number    */
205         int phy_addr;
206         int phy_speed;
207         int phy_duplex;
208         phy_interface_t phy_intf;
209 
210         int rx_resource_err;    /* Rx ring resource error flag */
211 
212         /* Next available and first returning Rx resource */
213         int rx_curr_desc_q, rx_used_desc_q;
214 
215         /* Next available and first returning Tx resource */
216         int tx_curr_desc_q, tx_used_desc_q;
217 
218         struct rx_desc *p_rx_desc_area;
219         dma_addr_t rx_desc_dma;
220         int rx_desc_area_size;
221         struct sk_buff **rx_skb;
222 
223         struct tx_desc *p_tx_desc_area;
224         dma_addr_t tx_desc_dma;
225         int tx_desc_area_size;
226         struct sk_buff **tx_skb;
227 
228         struct work_struct tx_timeout_task;
229 
230         struct net_device *dev;
231         struct napi_struct napi;
232         u8 work_todo;
233         int skb_size;
234 
235         /* Size of Tx Ring per queue */
236         int tx_ring_size;
237         /* Number of tx descriptors in use */
238         int tx_desc_count;
239         /* Size of Rx Ring per queue */
240         int rx_ring_size;
241         /* Number of rx descriptors in use */
242         int rx_desc_count;
243 
244         /*
245          * Used in case RX Ring is empty, which can occur when
246          * system does not have resources (skb's)
247          */
248         struct timer_list timeout;
249         struct mii_bus *smi_bus;
250         struct phy_device *phy;
251 
252         /* clock */
253         struct clk *clk;
254         struct pxa168_eth_platform_data *pd;
255         /*
256          * Ethernet controller base address.
257          */
258         void __iomem *base;
259 
260         /* Pointer to the hardware address filter table */
261         void *htpr;
262         dma_addr_t htpr_dma;
263 };
264 
265 struct addr_table_entry {
266         __le32 lo;
267         __le32 hi;
268 };
269 
270 /* Bit fields of a Hash Table Entry */
271 enum hash_table_entry {
272         HASH_ENTRY_VALID = 1,
273         SKIP = 2,
274         HASH_ENTRY_RECEIVE_DISCARD = 4,
275         HASH_ENTRY_RECEIVE_DISCARD_BIT = 2
276 };
277 
278 static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd);
279 static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd);
280 static int pxa168_init_hw(struct pxa168_eth_private *pep);
281 static int pxa168_init_phy(struct net_device *dev);
282 static void eth_port_reset(struct net_device *dev);
283 static void eth_port_start(struct net_device *dev);
284 static int pxa168_eth_open(struct net_device *dev);
285 static int pxa168_eth_stop(struct net_device *dev);
286 
287 static inline u32 rdl(struct pxa168_eth_private *pep, int offset)
288 {
289         return readl(pep->base + offset);
290 }
291 
292 static inline void wrl(struct pxa168_eth_private *pep, int offset, u32 data)
293 {
294         writel(data, pep->base + offset);
295 }
296 
297 static void abort_dma(struct pxa168_eth_private *pep)
298 {
299         int delay;
300         int max_retries = 40;
301 
302         do {
303                 wrl(pep, SDMA_CMD, SDMA_CMD_AR | SDMA_CMD_AT);
304                 udelay(100);
305 
306                 delay = 10;
307                 while ((rdl(pep, SDMA_CMD) & (SDMA_CMD_AR | SDMA_CMD_AT))
308                        && delay-- > 0) {
309                         udelay(10);
310                 }
311         } while (max_retries-- > 0 && delay <= 0);
312 
313         if (max_retries <= 0)
314                 netdev_err(pep->dev, "%s : DMA Stuck\n", __func__);
315 }
316 
317 static void rxq_refill(struct net_device *dev)
318 {
319         struct pxa168_eth_private *pep = netdev_priv(dev);
320         struct sk_buff *skb;
321         struct rx_desc *p_used_rx_desc;
322         int used_rx_desc;
323 
324         while (pep->rx_desc_count < pep->rx_ring_size) {
325                 int size;
326 
327                 skb = netdev_alloc_skb(dev, pep->skb_size);
328                 if (!skb)
329                         break;
330                 if (SKB_DMA_REALIGN)
331                         skb_reserve(skb, SKB_DMA_REALIGN);
332                 pep->rx_desc_count++;
333                 /* Get 'used' Rx descriptor */
334                 used_rx_desc = pep->rx_used_desc_q;
335                 p_used_rx_desc = &pep->p_rx_desc_area[used_rx_desc];
336                 size = skb_end_pointer(skb) - skb->data;
337                 p_used_rx_desc->buf_ptr = dma_map_single(NULL,
338                                                          skb->data,
339                                                          size,
340                                                          DMA_FROM_DEVICE);
341                 p_used_rx_desc->buf_size = size;
342                 pep->rx_skb[used_rx_desc] = skb;
343 
344                 /* Return the descriptor to DMA ownership */
345                 wmb();
346                 p_used_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
347                 wmb();
348 
349                 /* Move the used descriptor pointer to the next descriptor */
350                 pep->rx_used_desc_q = (used_rx_desc + 1) % pep->rx_ring_size;
351 
352                 /* Any Rx return cancels the Rx resource error status */
353                 pep->rx_resource_err = 0;
354 
355                 skb_reserve(skb, ETH_HW_IP_ALIGN);
356         }
357 
358         /*
359          * If RX ring is empty of SKB, set a timer to try allocating
360          * again at a later time.
361          */
362         if (pep->rx_desc_count == 0) {
363                 pep->timeout.expires = jiffies + (HZ / 10);
364                 add_timer(&pep->timeout);
365         }
366 }
367 
368 static inline void rxq_refill_timer_wrapper(unsigned long data)
369 {
370         struct pxa168_eth_private *pep = (void *)data;
371         napi_schedule(&pep->napi);
372 }
373 
374 static inline u8 flip_8_bits(u8 x)
375 {
376         return (((x) & 0x01) << 3) | (((x) & 0x02) << 1)
377             | (((x) & 0x04) >> 1) | (((x) & 0x08) >> 3)
378             | (((x) & 0x10) << 3) | (((x) & 0x20) << 1)
379             | (((x) & 0x40) >> 1) | (((x) & 0x80) >> 3);
380 }
381 
382 static void nibble_swap_every_byte(unsigned char *mac_addr)
383 {
384         int i;
385         for (i = 0; i < ETH_ALEN; i++) {
386                 mac_addr[i] = ((mac_addr[i] & 0x0f) << 4) |
387                                 ((mac_addr[i] & 0xf0) >> 4);
388         }
389 }
390 
391 static void inverse_every_nibble(unsigned char *mac_addr)
392 {
393         int i;
394         for (i = 0; i < ETH_ALEN; i++)
395                 mac_addr[i] = flip_8_bits(mac_addr[i]);
396 }
397 
398 /*
399  * ----------------------------------------------------------------------------
400  * This function will calculate the hash function of the address.
401  * Inputs
402  * mac_addr_orig    - MAC address.
403  * Outputs
404  * return the calculated entry.
405  */
406 static u32 hash_function(unsigned char *mac_addr_orig)
407 {
408         u32 hash_result;
409         u32 addr0;
410         u32 addr1;
411         u32 addr2;
412         u32 addr3;
413         unsigned char mac_addr[ETH_ALEN];
414 
415         /* Make a copy of MAC address since we are going to performe bit
416          * operations on it
417          */
418         memcpy(mac_addr, mac_addr_orig, ETH_ALEN);
419 
420         nibble_swap_every_byte(mac_addr);
421         inverse_every_nibble(mac_addr);
422 
423         addr0 = (mac_addr[5] >> 2) & 0x3f;
424         addr1 = (mac_addr[5] & 0x03) | (((mac_addr[4] & 0x7f)) << 2);
425         addr2 = ((mac_addr[4] & 0x80) >> 7) | mac_addr[3] << 1;
426         addr3 = (mac_addr[2] & 0xff) | ((mac_addr[1] & 1) << 8);
427 
428         hash_result = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
429         hash_result = hash_result & 0x07ff;
430         return hash_result;
431 }
432 
433 /*
434  * ----------------------------------------------------------------------------
435  * This function will add/del an entry to the address table.
436  * Inputs
437  * pep - ETHERNET .
438  * mac_addr - MAC address.
439  * skip - if 1, skip this address.Used in case of deleting an entry which is a
440  *        part of chain in the hash table.We can't just delete the entry since
441  *        that will break the chain.We need to defragment the tables time to
442  *        time.
443  * rd   - 0 Discard packet upon match.
444  *      - 1 Receive packet upon match.
445  * Outputs
446  * address table entry is added/deleted.
447  * 0 if success.
448  * -ENOSPC if table full
449  */
450 static int add_del_hash_entry(struct pxa168_eth_private *pep,
451                               unsigned char *mac_addr,
452                               u32 rd, u32 skip, int del)
453 {
454         struct addr_table_entry *entry, *start;
455         u32 new_high;
456         u32 new_low;
457         u32 i;
458 
459         new_low = (((mac_addr[1] >> 4) & 0xf) << 15)
460             | (((mac_addr[1] >> 0) & 0xf) << 11)
461             | (((mac_addr[0] >> 4) & 0xf) << 7)
462             | (((mac_addr[0] >> 0) & 0xf) << 3)
463             | (((mac_addr[3] >> 4) & 0x1) << 31)
464             | (((mac_addr[3] >> 0) & 0xf) << 27)
465             | (((mac_addr[2] >> 4) & 0xf) << 23)
466             | (((mac_addr[2] >> 0) & 0xf) << 19)
467             | (skip << SKIP) | (rd << HASH_ENTRY_RECEIVE_DISCARD_BIT)
468             | HASH_ENTRY_VALID;
469 
470         new_high = (((mac_addr[5] >> 4) & 0xf) << 15)
471             | (((mac_addr[5] >> 0) & 0xf) << 11)
472             | (((mac_addr[4] >> 4) & 0xf) << 7)
473             | (((mac_addr[4] >> 0) & 0xf) << 3)
474             | (((mac_addr[3] >> 5) & 0x7) << 0);
475 
476         /*
477          * Pick the appropriate table, start scanning for free/reusable
478          * entries at the index obtained by hashing the specified MAC address
479          */
480         start = pep->htpr;
481         entry = start + hash_function(mac_addr);
482         for (i = 0; i < HOP_NUMBER; i++) {
483                 if (!(le32_to_cpu(entry->lo) & HASH_ENTRY_VALID)) {
484                         break;
485                 } else {
486                         /* if same address put in same position */
487                         if (((le32_to_cpu(entry->lo) & 0xfffffff8) ==
488                                 (new_low & 0xfffffff8)) &&
489                                 (le32_to_cpu(entry->hi) == new_high)) {
490                                 break;
491                         }
492                 }
493                 if (entry == start + 0x7ff)
494                         entry = start;
495                 else
496                         entry++;
497         }
498 
499         if (((le32_to_cpu(entry->lo) & 0xfffffff8) != (new_low & 0xfffffff8)) &&
500             (le32_to_cpu(entry->hi) != new_high) && del)
501                 return 0;
502 
503         if (i == HOP_NUMBER) {
504                 if (!del) {
505                         netdev_info(pep->dev,
506                                     "%s: table section is full, need to "
507                                     "move to 16kB implementation?\n",
508                                     __FILE__);
509                         return -ENOSPC;
510                 } else
511                         return 0;
512         }
513 
514         /*
515          * Update the selected entry
516          */
517         if (del) {
518                 entry->hi = 0;
519                 entry->lo = 0;
520         } else {
521                 entry->hi = cpu_to_le32(new_high);
522                 entry->lo = cpu_to_le32(new_low);
523         }
524 
525         return 0;
526 }
527 
528 /*
529  * ----------------------------------------------------------------------------
530  *  Create an addressTable entry from MAC address info
531  *  found in the specifed net_device struct
532  *
533  *  Input : pointer to ethernet interface network device structure
534  *  Output : N/A
535  */
536 static void update_hash_table_mac_address(struct pxa168_eth_private *pep,
537                                           unsigned char *oaddr,
538                                           unsigned char *addr)
539 {
540         /* Delete old entry */
541         if (oaddr)
542                 add_del_hash_entry(pep, oaddr, 1, 0, HASH_DELETE);
543         /* Add new entry */
544         add_del_hash_entry(pep, addr, 1, 0, HASH_ADD);
545 }
546 
547 static int init_hash_table(struct pxa168_eth_private *pep)
548 {
549         /*
550          * Hardware expects CPU to build a hash table based on a predefined
551          * hash function and populate it based on hardware address. The
552          * location of the hash table is identified by 32-bit pointer stored
553          * in HTPR internal register. Two possible sizes exists for the hash
554          * table 8kB (256kB of DRAM required (4 x 64 kB banks)) and 1/2kB
555          * (16kB of DRAM required (4 x 4 kB banks)).We currently only support
556          * 1/2kB.
557          */
558         /* TODO: Add support for 8kB hash table and alternative hash
559          * function.Driver can dynamically switch to them if the 1/2kB hash
560          * table is full.
561          */
562         if (pep->htpr == NULL) {
563                 pep->htpr = dma_zalloc_coherent(pep->dev->dev.parent,
564                                                 HASH_ADDR_TABLE_SIZE,
565                                                 &pep->htpr_dma, GFP_KERNEL);
566                 if (pep->htpr == NULL)
567                         return -ENOMEM;
568         } else {
569                 memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE);
570         }
571         wrl(pep, HTPR, pep->htpr_dma);
572         return 0;
573 }
574 
575 static void pxa168_eth_set_rx_mode(struct net_device *dev)
576 {
577         struct pxa168_eth_private *pep = netdev_priv(dev);
578         struct netdev_hw_addr *ha;
579         u32 val;
580 
581         val = rdl(pep, PORT_CONFIG);
582         if (dev->flags & IFF_PROMISC)
583                 val |= PCR_PM;
584         else
585                 val &= ~PCR_PM;
586         wrl(pep, PORT_CONFIG, val);
587 
588         /*
589          * Remove the old list of MAC address and add dev->addr
590          * and multicast address.
591          */
592         memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE);
593         update_hash_table_mac_address(pep, NULL, dev->dev_addr);
594 
595         netdev_for_each_mc_addr(ha, dev)
596                 update_hash_table_mac_address(pep, NULL, ha->addr);
597 }
598 
599 static void pxa168_eth_get_mac_address(struct net_device *dev,
600                                        unsigned char *addr)
601 {
602         struct pxa168_eth_private *pep = netdev_priv(dev);
603         unsigned int mac_h = rdl(pep, MAC_ADDR_HIGH);
604         unsigned int mac_l = rdl(pep, MAC_ADDR_LOW);
605 
606         addr[0] = (mac_h >> 24) & 0xff;
607         addr[1] = (mac_h >> 16) & 0xff;
608         addr[2] = (mac_h >> 8) & 0xff;
609         addr[3] = mac_h & 0xff;
610         addr[4] = (mac_l >> 8) & 0xff;
611         addr[5] = mac_l & 0xff;
612 }
613 
614 static int pxa168_eth_set_mac_address(struct net_device *dev, void *addr)
615 {
616         struct sockaddr *sa = addr;
617         struct pxa168_eth_private *pep = netdev_priv(dev);
618         unsigned char oldMac[ETH_ALEN];
619         u32 mac_h, mac_l;
620 
621         if (!is_valid_ether_addr(sa->sa_data))
622                 return -EADDRNOTAVAIL;
623         memcpy(oldMac, dev->dev_addr, ETH_ALEN);
624         memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
625 
626         mac_h = dev->dev_addr[0] << 24;
627         mac_h |= dev->dev_addr[1] << 16;
628         mac_h |= dev->dev_addr[2] << 8;
629         mac_h |= dev->dev_addr[3];
630         mac_l = dev->dev_addr[4] << 8;
631         mac_l |= dev->dev_addr[5];
632         wrl(pep, MAC_ADDR_HIGH, mac_h);
633         wrl(pep, MAC_ADDR_LOW, mac_l);
634 
635         netif_addr_lock_bh(dev);
636         update_hash_table_mac_address(pep, oldMac, dev->dev_addr);
637         netif_addr_unlock_bh(dev);
638         return 0;
639 }
640 
641 static void eth_port_start(struct net_device *dev)
642 {
643         unsigned int val = 0;
644         struct pxa168_eth_private *pep = netdev_priv(dev);
645         int tx_curr_desc, rx_curr_desc;
646 
647         phy_start(pep->phy);
648 
649         /* Assignment of Tx CTRP of given queue */
650         tx_curr_desc = pep->tx_curr_desc_q;
651         wrl(pep, ETH_C_TX_DESC_1,
652             (u32) (pep->tx_desc_dma + tx_curr_desc * sizeof(struct tx_desc)));
653 
654         /* Assignment of Rx CRDP of given queue */
655         rx_curr_desc = pep->rx_curr_desc_q;
656         wrl(pep, ETH_C_RX_DESC_0,
657             (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc)));
658 
659         wrl(pep, ETH_F_RX_DESC_0,
660             (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc)));
661 
662         /* Clear all interrupts */
663         wrl(pep, INT_CAUSE, 0);
664 
665         /* Enable all interrupts for receive, transmit and error. */
666         wrl(pep, INT_MASK, ALL_INTS);
667 
668         val = rdl(pep, PORT_CONFIG);
669         val |= PCR_EN;
670         wrl(pep, PORT_CONFIG, val);
671 
672         /* Start RX DMA engine */
673         val = rdl(pep, SDMA_CMD);
674         val |= SDMA_CMD_ERD;
675         wrl(pep, SDMA_CMD, val);
676 }
677 
678 static void eth_port_reset(struct net_device *dev)
679 {
680         struct pxa168_eth_private *pep = netdev_priv(dev);
681         unsigned int val = 0;
682 
683         /* Stop all interrupts for receive, transmit and error. */
684         wrl(pep, INT_MASK, 0);
685 
686         /* Clear all interrupts */
687         wrl(pep, INT_CAUSE, 0);
688 
689         /* Stop RX DMA */
690         val = rdl(pep, SDMA_CMD);
691         val &= ~SDMA_CMD_ERD;   /* abort dma command */
692 
693         /* Abort any transmit and receive operations and put DMA
694          * in idle state.
695          */
696         abort_dma(pep);
697 
698         /* Disable port */
699         val = rdl(pep, PORT_CONFIG);
700         val &= ~PCR_EN;
701         wrl(pep, PORT_CONFIG, val);
702 
703         phy_stop(pep->phy);
704 }
705 
706 /*
707  * txq_reclaim - Free the tx desc data for completed descriptors
708  * If force is non-zero, frees uncompleted descriptors as well
709  */
710 static int txq_reclaim(struct net_device *dev, int force)
711 {
712         struct pxa168_eth_private *pep = netdev_priv(dev);
713         struct tx_desc *desc;
714         u32 cmd_sts;
715         struct sk_buff *skb;
716         int tx_index;
717         dma_addr_t addr;
718         int count;
719         int released = 0;
720 
721         netif_tx_lock(dev);
722 
723         pep->work_todo &= ~WORK_TX_DONE;
724         while (pep->tx_desc_count > 0) {
725                 tx_index = pep->tx_used_desc_q;
726                 desc = &pep->p_tx_desc_area[tx_index];
727                 cmd_sts = desc->cmd_sts;
728                 if (!force && (cmd_sts & BUF_OWNED_BY_DMA)) {
729                         if (released > 0) {
730                                 goto txq_reclaim_end;
731                         } else {
732                                 released = -1;
733                                 goto txq_reclaim_end;
734                         }
735                 }
736                 pep->tx_used_desc_q = (tx_index + 1) % pep->tx_ring_size;
737                 pep->tx_desc_count--;
738                 addr = desc->buf_ptr;
739                 count = desc->byte_cnt;
740                 skb = pep->tx_skb[tx_index];
741                 if (skb)
742                         pep->tx_skb[tx_index] = NULL;
743 
744                 if (cmd_sts & TX_ERROR) {
745                         if (net_ratelimit())
746                                 netdev_err(dev, "Error in TX\n");
747                         dev->stats.tx_errors++;
748                 }
749                 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
750                 if (skb)
751                         dev_kfree_skb_irq(skb);
752                 released++;
753         }
754 txq_reclaim_end:
755         netif_tx_unlock(dev);
756         return released;
757 }
758 
759 static void pxa168_eth_tx_timeout(struct net_device *dev)
760 {
761         struct pxa168_eth_private *pep = netdev_priv(dev);
762 
763         netdev_info(dev, "TX timeout  desc_count %d\n", pep->tx_desc_count);
764 
765         schedule_work(&pep->tx_timeout_task);
766 }
767 
768 static void pxa168_eth_tx_timeout_task(struct work_struct *work)
769 {
770         struct pxa168_eth_private *pep = container_of(work,
771                                                  struct pxa168_eth_private,
772                                                  tx_timeout_task);
773         struct net_device *dev = pep->dev;
774         pxa168_eth_stop(dev);
775         pxa168_eth_open(dev);
776 }
777 
778 static int rxq_process(struct net_device *dev, int budget)
779 {
780         struct pxa168_eth_private *pep = netdev_priv(dev);
781         struct net_device_stats *stats = &dev->stats;
782         unsigned int received_packets = 0;
783         struct sk_buff *skb;
784 
785         while (budget-- > 0) {
786                 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
787                 struct rx_desc *rx_desc;
788                 unsigned int cmd_sts;
789 
790                 /* Do not process Rx ring in case of Rx ring resource error */
791                 if (pep->rx_resource_err)
792                         break;
793                 rx_curr_desc = pep->rx_curr_desc_q;
794                 rx_used_desc = pep->rx_used_desc_q;
795                 rx_desc = &pep->p_rx_desc_area[rx_curr_desc];
796                 cmd_sts = rx_desc->cmd_sts;
797                 rmb();
798                 if (cmd_sts & (BUF_OWNED_BY_DMA))
799                         break;
800                 skb = pep->rx_skb[rx_curr_desc];
801                 pep->rx_skb[rx_curr_desc] = NULL;
802 
803                 rx_next_curr_desc = (rx_curr_desc + 1) % pep->rx_ring_size;
804                 pep->rx_curr_desc_q = rx_next_curr_desc;
805 
806                 /* Rx descriptors exhausted. */
807                 /* Set the Rx ring resource error flag */
808                 if (rx_next_curr_desc == rx_used_desc)
809                         pep->rx_resource_err = 1;
810                 pep->rx_desc_count--;
811                 dma_unmap_single(NULL, rx_desc->buf_ptr,
812                                  rx_desc->buf_size,
813                                  DMA_FROM_DEVICE);
814                 received_packets++;
815                 /*
816                  * Update statistics.
817                  * Note byte count includes 4 byte CRC count
818                  */
819                 stats->rx_packets++;
820                 stats->rx_bytes += rx_desc->byte_cnt;
821                 /*
822                  * In case received a packet without first / last bits on OR
823                  * the error summary bit is on, the packets needs to be droped.
824                  */
825                 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
826                      (RX_FIRST_DESC | RX_LAST_DESC))
827                     || (cmd_sts & RX_ERROR)) {
828 
829                         stats->rx_dropped++;
830                         if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
831                             (RX_FIRST_DESC | RX_LAST_DESC)) {
832                                 if (net_ratelimit())
833                                         netdev_err(dev,
834                                                    "Rx pkt on multiple desc\n");
835                         }
836                         if (cmd_sts & RX_ERROR)
837                                 stats->rx_errors++;
838                         dev_kfree_skb_irq(skb);
839                 } else {
840                         /*
841                          * The -4 is for the CRC in the trailer of the
842                          * received packet
843                          */
844                         skb_put(skb, rx_desc->byte_cnt - 4);
845                         skb->protocol = eth_type_trans(skb, dev);
846                         netif_receive_skb(skb);
847                 }
848         }
849         /* Fill RX ring with skb's */
850         rxq_refill(dev);
851         return received_packets;
852 }
853 
854 static int pxa168_eth_collect_events(struct pxa168_eth_private *pep,
855                                      struct net_device *dev)
856 {
857         u32 icr;
858         int ret = 0;
859 
860         icr = rdl(pep, INT_CAUSE);
861         if (icr == 0)
862                 return IRQ_NONE;
863 
864         wrl(pep, INT_CAUSE, ~icr);
865         if (icr & (ICR_TXBUF_H | ICR_TXBUF_L)) {
866                 pep->work_todo |= WORK_TX_DONE;
867                 ret = 1;
868         }
869         if (icr & ICR_RXBUF)
870                 ret = 1;
871         return ret;
872 }
873 
874 static irqreturn_t pxa168_eth_int_handler(int irq, void *dev_id)
875 {
876         struct net_device *dev = (struct net_device *)dev_id;
877         struct pxa168_eth_private *pep = netdev_priv(dev);
878 
879         if (unlikely(!pxa168_eth_collect_events(pep, dev)))
880                 return IRQ_NONE;
881         /* Disable interrupts */
882         wrl(pep, INT_MASK, 0);
883         napi_schedule(&pep->napi);
884         return IRQ_HANDLED;
885 }
886 
887 static void pxa168_eth_recalc_skb_size(struct pxa168_eth_private *pep)
888 {
889         int skb_size;
890 
891         /*
892          * Reserve 2+14 bytes for an ethernet header (the hardware
893          * automatically prepends 2 bytes of dummy data to each
894          * received packet), 16 bytes for up to four VLAN tags, and
895          * 4 bytes for the trailing FCS -- 36 bytes total.
896          */
897         skb_size = pep->dev->mtu + 36;
898 
899         /*
900          * Make sure that the skb size is a multiple of 8 bytes, as
901          * the lower three bits of the receive descriptor's buffer
902          * size field are ignored by the hardware.
903          */
904         pep->skb_size = (skb_size + 7) & ~7;
905 
906         /*
907          * If NET_SKB_PAD is smaller than a cache line,
908          * netdev_alloc_skb() will cause skb->data to be misaligned
909          * to a cache line boundary.  If this is the case, include
910          * some extra space to allow re-aligning the data area.
911          */
912         pep->skb_size += SKB_DMA_REALIGN;
913 
914 }
915 
916 static int set_port_config_ext(struct pxa168_eth_private *pep)
917 {
918         int skb_size;
919 
920         pxa168_eth_recalc_skb_size(pep);
921         if  (pep->skb_size <= 1518)
922                 skb_size = PCXR_MFL_1518;
923         else if (pep->skb_size <= 1536)
924                 skb_size = PCXR_MFL_1536;
925         else if (pep->skb_size <= 2048)
926                 skb_size = PCXR_MFL_2048;
927         else
928                 skb_size = PCXR_MFL_64K;
929 
930         /* Extended Port Configuration */
931         wrl(pep, PORT_CONFIG_EXT,
932             PCXR_AN_SPEED_DIS |          /* Disable HW AN */
933             PCXR_AN_DUPLEX_DIS |
934             PCXR_AN_FLOWCTL_DIS |
935             PCXR_2BSM |                  /* Two byte prefix aligns IP hdr */
936             PCXR_DSCP_EN |               /* Enable DSCP in IP */
937             skb_size | PCXR_FLP |        /* do not force link pass */
938             PCXR_TX_HIGH_PRI);           /* Transmit - high priority queue */
939 
940         return 0;
941 }
942 
943 static void pxa168_eth_adjust_link(struct net_device *dev)
944 {
945         struct pxa168_eth_private *pep = netdev_priv(dev);
946         struct phy_device *phy = pep->phy;
947         u32 cfg, cfg_o = rdl(pep, PORT_CONFIG);
948         u32 cfgext, cfgext_o = rdl(pep, PORT_CONFIG_EXT);
949 
950         cfg = cfg_o & ~PCR_DUPLEX_FULL;
951         cfgext = cfgext_o & ~(PCXR_SPEED_100 | PCXR_FLOWCTL_DIS | PCXR_RMII_EN);
952 
953         if (phy->interface == PHY_INTERFACE_MODE_RMII)
954                 cfgext |= PCXR_RMII_EN;
955         if (phy->speed == SPEED_100)
956                 cfgext |= PCXR_SPEED_100;
957         if (phy->duplex)
958                 cfg |= PCR_DUPLEX_FULL;
959         if (!phy->pause)
960                 cfgext |= PCXR_FLOWCTL_DIS;
961 
962         /* Bail out if there has nothing changed */
963         if (cfg == cfg_o && cfgext == cfgext_o)
964                 return;
965 
966         wrl(pep, PORT_CONFIG, cfg);
967         wrl(pep, PORT_CONFIG_EXT, cfgext);
968 
969         phy_print_status(phy);
970 }
971 
972 static int pxa168_init_phy(struct net_device *dev)
973 {
974         struct pxa168_eth_private *pep = netdev_priv(dev);
975         struct ethtool_cmd cmd;
976         int err;
977 
978         if (pep->phy)
979                 return 0;
980 
981         pep->phy = mdiobus_scan(pep->smi_bus, pep->phy_addr);
982         if (IS_ERR(pep->phy))
983                 return PTR_ERR(pep->phy);
984         if (!pep->phy)
985                 return -ENODEV;
986 
987         err = phy_connect_direct(dev, pep->phy, pxa168_eth_adjust_link,
988                                  pep->phy_intf);
989         if (err)
990                 return err;
991 
992         err = pxa168_get_settings(dev, &cmd);
993         if (err)
994                 return err;
995 
996         cmd.phy_address = pep->phy_addr;
997         cmd.speed = pep->phy_speed;
998         cmd.duplex = pep->phy_duplex;
999         cmd.advertising = PHY_BASIC_FEATURES;
1000         cmd.autoneg = AUTONEG_ENABLE;
1001 
1002         if (cmd.speed != 0)
1003                 cmd.autoneg = AUTONEG_DISABLE;
1004 
1005         return pxa168_set_settings(dev, &cmd);
1006 }
1007 
1008 static int pxa168_init_hw(struct pxa168_eth_private *pep)
1009 {
1010         int err = 0;
1011 
1012         /* Disable interrupts */
1013         wrl(pep, INT_MASK, 0);
1014         wrl(pep, INT_CAUSE, 0);
1015         /* Write to ICR to clear interrupts. */
1016         wrl(pep, INT_W_CLEAR, 0);
1017         /* Abort any transmit and receive operations and put DMA
1018          * in idle state.
1019          */
1020         abort_dma(pep);
1021         /* Initialize address hash table */
1022         err = init_hash_table(pep);
1023         if (err)
1024                 return err;
1025         /* SDMA configuration */
1026         wrl(pep, SDMA_CONFIG, SDCR_BSZ8 |       /* Burst size = 32 bytes */
1027             SDCR_RIFB |                         /* Rx interrupt on frame */
1028             SDCR_BLMT |                         /* Little endian transmit */
1029             SDCR_BLMR |                         /* Little endian receive */
1030             SDCR_RC_MAX_RETRANS);               /* Max retransmit count */
1031         /* Port Configuration */
1032         wrl(pep, PORT_CONFIG, PCR_HS);          /* Hash size is 1/2kb */
1033         set_port_config_ext(pep);
1034 
1035         return err;
1036 }
1037 
1038 static int rxq_init(struct net_device *dev)
1039 {
1040         struct pxa168_eth_private *pep = netdev_priv(dev);
1041         struct rx_desc *p_rx_desc;
1042         int size = 0, i = 0;
1043         int rx_desc_num = pep->rx_ring_size;
1044 
1045         /* Allocate RX skb rings */
1046         pep->rx_skb = kzalloc(sizeof(*pep->rx_skb) * pep->rx_ring_size,
1047                              GFP_KERNEL);
1048         if (!pep->rx_skb)
1049                 return -ENOMEM;
1050 
1051         /* Allocate RX ring */
1052         pep->rx_desc_count = 0;
1053         size = pep->rx_ring_size * sizeof(struct rx_desc);
1054         pep->rx_desc_area_size = size;
1055         pep->p_rx_desc_area = dma_zalloc_coherent(pep->dev->dev.parent, size,
1056                                                   &pep->rx_desc_dma,
1057                                                   GFP_KERNEL);
1058         if (!pep->p_rx_desc_area)
1059                 goto out;
1060 
1061         /* initialize the next_desc_ptr links in the Rx descriptors ring */
1062         p_rx_desc = pep->p_rx_desc_area;
1063         for (i = 0; i < rx_desc_num; i++) {
1064                 p_rx_desc[i].next_desc_ptr = pep->rx_desc_dma +
1065                     ((i + 1) % rx_desc_num) * sizeof(struct rx_desc);
1066         }
1067         /* Save Rx desc pointer to driver struct. */
1068         pep->rx_curr_desc_q = 0;
1069         pep->rx_used_desc_q = 0;
1070         pep->rx_desc_area_size = rx_desc_num * sizeof(struct rx_desc);
1071         return 0;
1072 out:
1073         kfree(pep->rx_skb);
1074         return -ENOMEM;
1075 }
1076 
1077 static void rxq_deinit(struct net_device *dev)
1078 {
1079         struct pxa168_eth_private *pep = netdev_priv(dev);
1080         int curr;
1081 
1082         /* Free preallocated skb's on RX rings */
1083         for (curr = 0; pep->rx_desc_count && curr < pep->rx_ring_size; curr++) {
1084                 if (pep->rx_skb[curr]) {
1085                         dev_kfree_skb(pep->rx_skb[curr]);
1086                         pep->rx_desc_count--;
1087                 }
1088         }
1089         if (pep->rx_desc_count)
1090                 netdev_err(dev, "Error in freeing Rx Ring. %d skb's still\n",
1091                            pep->rx_desc_count);
1092         /* Free RX ring */
1093         if (pep->p_rx_desc_area)
1094                 dma_free_coherent(pep->dev->dev.parent, pep->rx_desc_area_size,
1095                                   pep->p_rx_desc_area, pep->rx_desc_dma);
1096         kfree(pep->rx_skb);
1097 }
1098 
1099 static int txq_init(struct net_device *dev)
1100 {
1101         struct pxa168_eth_private *pep = netdev_priv(dev);
1102         struct tx_desc *p_tx_desc;
1103         int size = 0, i = 0;
1104         int tx_desc_num = pep->tx_ring_size;
1105 
1106         pep->tx_skb = kzalloc(sizeof(*pep->tx_skb) * pep->tx_ring_size,
1107                              GFP_KERNEL);
1108         if (!pep->tx_skb)
1109                 return -ENOMEM;
1110 
1111         /* Allocate TX ring */
1112         pep->tx_desc_count = 0;
1113         size = pep->tx_ring_size * sizeof(struct tx_desc);
1114         pep->tx_desc_area_size = size;
1115         pep->p_tx_desc_area = dma_zalloc_coherent(pep->dev->dev.parent, size,
1116                                                   &pep->tx_desc_dma,
1117                                                   GFP_KERNEL);
1118         if (!pep->p_tx_desc_area)
1119                 goto out;
1120         /* Initialize the next_desc_ptr links in the Tx descriptors ring */
1121         p_tx_desc = pep->p_tx_desc_area;
1122         for (i = 0; i < tx_desc_num; i++) {
1123                 p_tx_desc[i].next_desc_ptr = pep->tx_desc_dma +
1124                     ((i + 1) % tx_desc_num) * sizeof(struct tx_desc);
1125         }
1126         pep->tx_curr_desc_q = 0;
1127         pep->tx_used_desc_q = 0;
1128         pep->tx_desc_area_size = tx_desc_num * sizeof(struct tx_desc);
1129         return 0;
1130 out:
1131         kfree(pep->tx_skb);
1132         return -ENOMEM;
1133 }
1134 
1135 static void txq_deinit(struct net_device *dev)
1136 {
1137         struct pxa168_eth_private *pep = netdev_priv(dev);
1138 
1139         /* Free outstanding skb's on TX ring */
1140         txq_reclaim(dev, 1);
1141         BUG_ON(pep->tx_used_desc_q != pep->tx_curr_desc_q);
1142         /* Free TX ring */
1143         if (pep->p_tx_desc_area)
1144                 dma_free_coherent(pep->dev->dev.parent, pep->tx_desc_area_size,
1145                                   pep->p_tx_desc_area, pep->tx_desc_dma);
1146         kfree(pep->tx_skb);
1147 }
1148 
1149 static int pxa168_eth_open(struct net_device *dev)
1150 {
1151         struct pxa168_eth_private *pep = netdev_priv(dev);
1152         int err;
1153 
1154         err = pxa168_init_phy(dev);
1155         if (err)
1156                 return err;
1157 
1158         err = request_irq(dev->irq, pxa168_eth_int_handler, 0, dev->name, dev);
1159         if (err) {
1160                 dev_err(&dev->dev, "can't assign irq\n");
1161                 return -EAGAIN;
1162         }
1163         pep->rx_resource_err = 0;
1164         err = rxq_init(dev);
1165         if (err != 0)
1166                 goto out_free_irq;
1167         err = txq_init(dev);
1168         if (err != 0)
1169                 goto out_free_rx_skb;
1170         pep->rx_used_desc_q = 0;
1171         pep->rx_curr_desc_q = 0;
1172 
1173         /* Fill RX ring with skb's */
1174         rxq_refill(dev);
1175         pep->rx_used_desc_q = 0;
1176         pep->rx_curr_desc_q = 0;
1177         netif_carrier_off(dev);
1178         napi_enable(&pep->napi);
1179         eth_port_start(dev);
1180         return 0;
1181 out_free_rx_skb:
1182         rxq_deinit(dev);
1183 out_free_irq:
1184         free_irq(dev->irq, dev);
1185         return err;
1186 }
1187 
1188 static int pxa168_eth_stop(struct net_device *dev)
1189 {
1190         struct pxa168_eth_private *pep = netdev_priv(dev);
1191         eth_port_reset(dev);
1192 
1193         /* Disable interrupts */
1194         wrl(pep, INT_MASK, 0);
1195         wrl(pep, INT_CAUSE, 0);
1196         /* Write to ICR to clear interrupts. */
1197         wrl(pep, INT_W_CLEAR, 0);
1198         napi_disable(&pep->napi);
1199         del_timer_sync(&pep->timeout);
1200         netif_carrier_off(dev);
1201         free_irq(dev->irq, dev);
1202         rxq_deinit(dev);
1203         txq_deinit(dev);
1204 
1205         return 0;
1206 }
1207 
1208 static int pxa168_eth_change_mtu(struct net_device *dev, int mtu)
1209 {
1210         int retval;
1211         struct pxa168_eth_private *pep = netdev_priv(dev);
1212 
1213         if ((mtu > 9500) || (mtu < 68))
1214                 return -EINVAL;
1215 
1216         dev->mtu = mtu;
1217         retval = set_port_config_ext(pep);
1218 
1219         if (!netif_running(dev))
1220                 return 0;
1221 
1222         /*
1223          * Stop and then re-open the interface. This will allocate RX
1224          * skbs of the new MTU.
1225          * There is a possible danger that the open will not succeed,
1226          * due to memory being full.
1227          */
1228         pxa168_eth_stop(dev);
1229         if (pxa168_eth_open(dev)) {
1230                 dev_err(&dev->dev,
1231                         "fatal error on re-opening device after MTU change\n");
1232         }
1233 
1234         return 0;
1235 }
1236 
1237 static int eth_alloc_tx_desc_index(struct pxa168_eth_private *pep)
1238 {
1239         int tx_desc_curr;
1240 
1241         tx_desc_curr = pep->tx_curr_desc_q;
1242         pep->tx_curr_desc_q = (tx_desc_curr + 1) % pep->tx_ring_size;
1243         BUG_ON(pep->tx_curr_desc_q == pep->tx_used_desc_q);
1244         pep->tx_desc_count++;
1245 
1246         return tx_desc_curr;
1247 }
1248 
1249 static int pxa168_rx_poll(struct napi_struct *napi, int budget)
1250 {
1251         struct pxa168_eth_private *pep =
1252             container_of(napi, struct pxa168_eth_private, napi);
1253         struct net_device *dev = pep->dev;
1254         int work_done = 0;
1255 
1256         /*
1257          * We call txq_reclaim every time since in NAPI interupts are disabled
1258          * and due to this we miss the TX_DONE interrupt,which is not updated in
1259          * interrupt status register.
1260          */
1261         txq_reclaim(dev, 0);
1262         if (netif_queue_stopped(dev)
1263             && pep->tx_ring_size - pep->tx_desc_count > 1) {
1264                 netif_wake_queue(dev);
1265         }
1266         work_done = rxq_process(dev, budget);
1267         if (work_done < budget) {
1268                 napi_complete(napi);
1269                 wrl(pep, INT_MASK, ALL_INTS);
1270         }
1271 
1272         return work_done;
1273 }
1274 
1275 static int pxa168_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1276 {
1277         struct pxa168_eth_private *pep = netdev_priv(dev);
1278         struct net_device_stats *stats = &dev->stats;
1279         struct tx_desc *desc;
1280         int tx_index;
1281         int length;
1282 
1283         tx_index = eth_alloc_tx_desc_index(pep);
1284         desc = &pep->p_tx_desc_area[tx_index];
1285         length = skb->len;
1286         pep->tx_skb[tx_index] = skb;
1287         desc->byte_cnt = length;
1288         desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
1289 
1290         skb_tx_timestamp(skb);
1291 
1292         wmb();
1293         desc->cmd_sts = BUF_OWNED_BY_DMA | TX_GEN_CRC | TX_FIRST_DESC |
1294                         TX_ZERO_PADDING | TX_LAST_DESC | TX_EN_INT;
1295         wmb();
1296         wrl(pep, SDMA_CMD, SDMA_CMD_TXDH | SDMA_CMD_ERD);
1297 
1298         stats->tx_bytes += length;
1299         stats->tx_packets++;
1300         dev->trans_start = jiffies;
1301         if (pep->tx_ring_size - pep->tx_desc_count <= 1) {
1302                 /* We handled the current skb, but now we are out of space.*/
1303                 netif_stop_queue(dev);
1304         }
1305 
1306         return NETDEV_TX_OK;
1307 }
1308 
1309 static int smi_wait_ready(struct pxa168_eth_private *pep)
1310 {
1311         int i = 0;
1312 
1313         /* wait for the SMI register to become available */
1314         for (i = 0; rdl(pep, SMI) & SMI_BUSY; i++) {
1315                 if (i == PHY_WAIT_ITERATIONS)
1316                         return -ETIMEDOUT;
1317                 msleep(10);
1318         }
1319 
1320         return 0;
1321 }
1322 
1323 static int pxa168_smi_read(struct mii_bus *bus, int phy_addr, int regnum)
1324 {
1325         struct pxa168_eth_private *pep = bus->priv;
1326         int i = 0;
1327         int val;
1328 
1329         if (smi_wait_ready(pep)) {
1330                 netdev_warn(pep->dev, "pxa168_eth: SMI bus busy timeout\n");
1331                 return -ETIMEDOUT;
1332         }
1333         wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | SMI_OP_R);
1334         /* now wait for the data to be valid */
1335         for (i = 0; !((val = rdl(pep, SMI)) & SMI_R_VALID); i++) {
1336                 if (i == PHY_WAIT_ITERATIONS) {
1337                         netdev_warn(pep->dev,
1338                                     "pxa168_eth: SMI bus read not valid\n");
1339                         return -ENODEV;
1340                 }
1341                 msleep(10);
1342         }
1343 
1344         return val & 0xffff;
1345 }
1346 
1347 static int pxa168_smi_write(struct mii_bus *bus, int phy_addr, int regnum,
1348                             u16 value)
1349 {
1350         struct pxa168_eth_private *pep = bus->priv;
1351 
1352         if (smi_wait_ready(pep)) {
1353                 netdev_warn(pep->dev, "pxa168_eth: SMI bus busy timeout\n");
1354                 return -ETIMEDOUT;
1355         }
1356 
1357         wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) |
1358             SMI_OP_W | (value & 0xffff));
1359 
1360         if (smi_wait_ready(pep)) {
1361                 netdev_err(pep->dev, "pxa168_eth: SMI bus busy timeout\n");
1362                 return -ETIMEDOUT;
1363         }
1364 
1365         return 0;
1366 }
1367 
1368 static int pxa168_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr,
1369                                int cmd)
1370 {
1371         struct pxa168_eth_private *pep = netdev_priv(dev);
1372         if (pep->phy != NULL)
1373                 return phy_mii_ioctl(pep->phy, ifr, cmd);
1374 
1375         return -EOPNOTSUPP;
1376 }
1377 
1378 static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1379 {
1380         struct pxa168_eth_private *pep = netdev_priv(dev);
1381         int err;
1382 
1383         err = phy_read_status(pep->phy);
1384         if (err == 0)
1385                 err = phy_ethtool_gset(pep->phy, cmd);
1386 
1387         return err;
1388 }
1389 
1390 static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1391 {
1392         struct pxa168_eth_private *pep = netdev_priv(dev);
1393 
1394         return phy_ethtool_sset(pep->phy, cmd);
1395 }
1396 
1397 static void pxa168_get_drvinfo(struct net_device *dev,
1398                                struct ethtool_drvinfo *info)
1399 {
1400         strlcpy(info->driver, DRIVER_NAME, sizeof(info->driver));
1401         strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
1402         strlcpy(info->fw_version, "N/A", sizeof(info->fw_version));
1403         strlcpy(info->bus_info, "N/A", sizeof(info->bus_info));
1404 }
1405 
1406 static const struct ethtool_ops pxa168_ethtool_ops = {
1407         .get_settings   = pxa168_get_settings,
1408         .set_settings   = pxa168_set_settings,
1409         .get_drvinfo    = pxa168_get_drvinfo,
1410         .get_link       = ethtool_op_get_link,
1411         .get_ts_info    = ethtool_op_get_ts_info,
1412 };
1413 
1414 static const struct net_device_ops pxa168_eth_netdev_ops = {
1415         .ndo_open               = pxa168_eth_open,
1416         .ndo_stop               = pxa168_eth_stop,
1417         .ndo_start_xmit         = pxa168_eth_start_xmit,
1418         .ndo_set_rx_mode        = pxa168_eth_set_rx_mode,
1419         .ndo_set_mac_address    = pxa168_eth_set_mac_address,
1420         .ndo_validate_addr      = eth_validate_addr,
1421         .ndo_do_ioctl           = pxa168_eth_do_ioctl,
1422         .ndo_change_mtu         = pxa168_eth_change_mtu,
1423         .ndo_tx_timeout         = pxa168_eth_tx_timeout,
1424 };
1425 
1426 static int pxa168_eth_probe(struct platform_device *pdev)
1427 {
1428         struct pxa168_eth_private *pep = NULL;
1429         struct net_device *dev = NULL;
1430         struct resource *res;
1431         struct clk *clk;
1432         struct device_node *np;
1433         const unsigned char *mac_addr = NULL;
1434         int err;
1435 
1436         printk(KERN_NOTICE "PXA168 10/100 Ethernet Driver\n");
1437 
1438         clk = devm_clk_get(&pdev->dev, NULL);
1439         if (IS_ERR(clk)) {
1440                 dev_err(&pdev->dev, "Fast Ethernet failed to get clock\n");
1441                 return -ENODEV;
1442         }
1443         clk_prepare_enable(clk);
1444 
1445         dev = alloc_etherdev(sizeof(struct pxa168_eth_private));
1446         if (!dev) {
1447                 err = -ENOMEM;
1448                 goto err_clk;
1449         }
1450 
1451         platform_set_drvdata(pdev, dev);
1452         pep = netdev_priv(dev);
1453         pep->dev = dev;
1454         pep->clk = clk;
1455 
1456         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1457         pep->base = devm_ioremap_resource(&pdev->dev, res);
1458         if (IS_ERR(pep->base)) {
1459                 err = -ENOMEM;
1460                 goto err_netdev;
1461         }
1462 
1463         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1464         BUG_ON(!res);
1465         dev->irq = res->start;
1466         dev->netdev_ops = &pxa168_eth_netdev_ops;
1467         dev->watchdog_timeo = 2 * HZ;
1468         dev->base_addr = 0;
1469         dev->ethtool_ops = &pxa168_ethtool_ops;
1470 
1471         INIT_WORK(&pep->tx_timeout_task, pxa168_eth_tx_timeout_task);
1472 
1473         if (pdev->dev.of_node)
1474                 mac_addr = of_get_mac_address(pdev->dev.of_node);
1475 
1476         if (mac_addr && is_valid_ether_addr(mac_addr)) {
1477                 ether_addr_copy(dev->dev_addr, mac_addr);
1478         } else {
1479                 /* try reading the mac address, if set by the bootloader */
1480                 pxa168_eth_get_mac_address(dev, dev->dev_addr);
1481                 if (!is_valid_ether_addr(dev->dev_addr)) {
1482                         dev_info(&pdev->dev, "Using random mac address\n");
1483                         eth_hw_addr_random(dev);
1484                 }
1485         }
1486 
1487         pep->rx_ring_size = NUM_RX_DESCS;
1488         pep->tx_ring_size = NUM_TX_DESCS;
1489 
1490         pep->pd = dev_get_platdata(&pdev->dev);
1491         if (pep->pd) {
1492                 if (pep->pd->rx_queue_size)
1493                         pep->rx_ring_size = pep->pd->rx_queue_size;
1494 
1495                 if (pep->pd->tx_queue_size)
1496                         pep->tx_ring_size = pep->pd->tx_queue_size;
1497 
1498                 pep->port_num = pep->pd->port_number;
1499                 pep->phy_addr = pep->pd->phy_addr;
1500                 pep->phy_speed = pep->pd->speed;
1501                 pep->phy_duplex = pep->pd->duplex;
1502                 pep->phy_intf = pep->pd->intf;
1503 
1504                 if (pep->pd->init)
1505                         pep->pd->init();
1506         } else if (pdev->dev.of_node) {
1507                 of_property_read_u32(pdev->dev.of_node, "port-id",
1508                                      &pep->port_num);
1509 
1510                 np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
1511                 if (!np) {
1512                         dev_err(&pdev->dev, "missing phy-handle\n");
1513                         err = -EINVAL;
1514                         goto err_netdev;
1515                 }
1516                 of_property_read_u32(np, "reg", &pep->phy_addr);
1517                 pep->phy_intf = of_get_phy_mode(pdev->dev.of_node);
1518         }
1519 
1520         /* Hardware supports only 3 ports */
1521         BUG_ON(pep->port_num > 2);
1522         netif_napi_add(dev, &pep->napi, pxa168_rx_poll, pep->rx_ring_size);
1523 
1524         memset(&pep->timeout, 0, sizeof(struct timer_list));
1525         init_timer(&pep->timeout);
1526         pep->timeout.function = rxq_refill_timer_wrapper;
1527         pep->timeout.data = (unsigned long)pep;
1528 
1529         pep->smi_bus = mdiobus_alloc();
1530         if (pep->smi_bus == NULL) {
1531                 err = -ENOMEM;
1532                 goto err_netdev;
1533         }
1534         pep->smi_bus->priv = pep;
1535         pep->smi_bus->name = "pxa168_eth smi";
1536         pep->smi_bus->read = pxa168_smi_read;
1537         pep->smi_bus->write = pxa168_smi_write;
1538         snprintf(pep->smi_bus->id, MII_BUS_ID_SIZE, "%s-%d",
1539                 pdev->name, pdev->id);
1540         pep->smi_bus->parent = &pdev->dev;
1541         pep->smi_bus->phy_mask = 0xffffffff;
1542         err = mdiobus_register(pep->smi_bus);
1543         if (err)
1544                 goto err_free_mdio;
1545 
1546         SET_NETDEV_DEV(dev, &pdev->dev);
1547         pxa168_init_hw(pep);
1548         err = register_netdev(dev);
1549         if (err)
1550                 goto err_mdiobus;
1551         return 0;
1552 
1553 err_mdiobus:
1554         mdiobus_unregister(pep->smi_bus);
1555 err_free_mdio:
1556         mdiobus_free(pep->smi_bus);
1557 err_netdev:
1558         free_netdev(dev);
1559 err_clk:
1560         clk_disable_unprepare(clk);
1561         return err;
1562 }
1563 
1564 static int pxa168_eth_remove(struct platform_device *pdev)
1565 {
1566         struct net_device *dev = platform_get_drvdata(pdev);
1567         struct pxa168_eth_private *pep = netdev_priv(dev);
1568 
1569         if (pep->htpr) {
1570                 dma_free_coherent(pep->dev->dev.parent, HASH_ADDR_TABLE_SIZE,
1571                                   pep->htpr, pep->htpr_dma);
1572                 pep->htpr = NULL;
1573         }
1574         if (pep->phy)
1575                 phy_disconnect(pep->phy);
1576         if (pep->clk) {
1577                 clk_disable_unprepare(pep->clk);
1578         }
1579 
1580         mdiobus_unregister(pep->smi_bus);
1581         mdiobus_free(pep->smi_bus);
1582         unregister_netdev(dev);
1583         cancel_work_sync(&pep->tx_timeout_task);
1584         free_netdev(dev);
1585         return 0;
1586 }
1587 
1588 static void pxa168_eth_shutdown(struct platform_device *pdev)
1589 {
1590         struct net_device *dev = platform_get_drvdata(pdev);
1591         eth_port_reset(dev);
1592 }
1593 
1594 #ifdef CONFIG_PM
1595 static int pxa168_eth_resume(struct platform_device *pdev)
1596 {
1597         return -ENOSYS;
1598 }
1599 
1600 static int pxa168_eth_suspend(struct platform_device *pdev, pm_message_t state)
1601 {
1602         return -ENOSYS;
1603 }
1604 
1605 #else
1606 #define pxa168_eth_resume NULL
1607 #define pxa168_eth_suspend NULL
1608 #endif
1609 
1610 static const struct of_device_id pxa168_eth_of_match[] = {
1611         { .compatible = "marvell,pxa168-eth" },
1612         { },
1613 };
1614 MODULE_DEVICE_TABLE(of, pxa168_eth_of_match);
1615 
1616 static struct platform_driver pxa168_eth_driver = {
1617         .probe = pxa168_eth_probe,
1618         .remove = pxa168_eth_remove,
1619         .shutdown = pxa168_eth_shutdown,
1620         .resume = pxa168_eth_resume,
1621         .suspend = pxa168_eth_suspend,
1622         .driver = {
1623                 .name           = DRIVER_NAME,
1624                 .of_match_table = of_match_ptr(pxa168_eth_of_match),
1625         },
1626 };
1627 
1628 module_platform_driver(pxa168_eth_driver);
1629 
1630 MODULE_LICENSE("GPL");
1631 MODULE_DESCRIPTION("Ethernet driver for Marvell PXA168");
1632 MODULE_ALIAS("platform:pxa168_eth");
1633 

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