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Linux/drivers/net/ethernet/marvell/mvneta.c

  1 /*
  2  * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
  3  *
  4  * Copyright (C) 2012 Marvell
  5  *
  6  * Rami Rosen <rosenr@marvell.com>
  7  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  8  *
  9  * This file is licensed under the terms of the GNU General Public
 10  * License version 2. This program is licensed "as is" without any
 11  * warranty of any kind, whether express or implied.
 12  */
 13 
 14 #include <linux/clk.h>
 15 #include <linux/cpu.h>
 16 #include <linux/etherdevice.h>
 17 #include <linux/if_vlan.h>
 18 #include <linux/inetdevice.h>
 19 #include <linux/interrupt.h>
 20 #include <linux/io.h>
 21 #include <linux/kernel.h>
 22 #include <linux/mbus.h>
 23 #include <linux/module.h>
 24 #include <linux/netdevice.h>
 25 #include <linux/of.h>
 26 #include <linux/of_address.h>
 27 #include <linux/of_irq.h>
 28 #include <linux/of_mdio.h>
 29 #include <linux/of_net.h>
 30 #include <linux/phy.h>
 31 #include <linux/platform_device.h>
 32 #include <linux/skbuff.h>
 33 #include <net/ip.h>
 34 #include <net/ipv6.h>
 35 #include <net/tso.h>
 36 
 37 /* Registers */
 38 #define MVNETA_RXQ_CONFIG_REG(q)                (0x1400 + ((q) << 2))
 39 #define      MVNETA_RXQ_HW_BUF_ALLOC            BIT(0)
 40 #define      MVNETA_RXQ_PKT_OFFSET_ALL_MASK     (0xf    << 8)
 41 #define      MVNETA_RXQ_PKT_OFFSET_MASK(offs)   ((offs) << 8)
 42 #define MVNETA_RXQ_THRESHOLD_REG(q)             (0x14c0 + ((q) << 2))
 43 #define      MVNETA_RXQ_NON_OCCUPIED(v)         ((v) << 16)
 44 #define MVNETA_RXQ_BASE_ADDR_REG(q)             (0x1480 + ((q) << 2))
 45 #define MVNETA_RXQ_SIZE_REG(q)                  (0x14a0 + ((q) << 2))
 46 #define      MVNETA_RXQ_BUF_SIZE_SHIFT          19
 47 #define      MVNETA_RXQ_BUF_SIZE_MASK           (0x1fff << 19)
 48 #define MVNETA_RXQ_STATUS_REG(q)                (0x14e0 + ((q) << 2))
 49 #define      MVNETA_RXQ_OCCUPIED_ALL_MASK       0x3fff
 50 #define MVNETA_RXQ_STATUS_UPDATE_REG(q)         (0x1500 + ((q) << 2))
 51 #define      MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT  16
 52 #define      MVNETA_RXQ_ADD_NON_OCCUPIED_MAX    255
 53 #define MVNETA_PORT_RX_RESET                    0x1cc0
 54 #define      MVNETA_PORT_RX_DMA_RESET           BIT(0)
 55 #define MVNETA_PHY_ADDR                         0x2000
 56 #define      MVNETA_PHY_ADDR_MASK               0x1f
 57 #define MVNETA_MBUS_RETRY                       0x2010
 58 #define MVNETA_UNIT_INTR_CAUSE                  0x2080
 59 #define MVNETA_UNIT_CONTROL                     0x20B0
 60 #define      MVNETA_PHY_POLLING_ENABLE          BIT(1)
 61 #define MVNETA_WIN_BASE(w)                      (0x2200 + ((w) << 3))
 62 #define MVNETA_WIN_SIZE(w)                      (0x2204 + ((w) << 3))
 63 #define MVNETA_WIN_REMAP(w)                     (0x2280 + ((w) << 2))
 64 #define MVNETA_BASE_ADDR_ENABLE                 0x2290
 65 #define MVNETA_ACCESS_PROTECT_ENABLE            0x2294
 66 #define MVNETA_PORT_CONFIG                      0x2400
 67 #define      MVNETA_UNI_PROMISC_MODE            BIT(0)
 68 #define      MVNETA_DEF_RXQ(q)                  ((q) << 1)
 69 #define      MVNETA_DEF_RXQ_ARP(q)              ((q) << 4)
 70 #define      MVNETA_TX_UNSET_ERR_SUM            BIT(12)
 71 #define      MVNETA_DEF_RXQ_TCP(q)              ((q) << 16)
 72 #define      MVNETA_DEF_RXQ_UDP(q)              ((q) << 19)
 73 #define      MVNETA_DEF_RXQ_BPDU(q)             ((q) << 22)
 74 #define      MVNETA_RX_CSUM_WITH_PSEUDO_HDR     BIT(25)
 75 #define      MVNETA_PORT_CONFIG_DEFL_VALUE(q)   (MVNETA_DEF_RXQ(q)       | \
 76                                                  MVNETA_DEF_RXQ_ARP(q)   | \
 77                                                  MVNETA_DEF_RXQ_TCP(q)   | \
 78                                                  MVNETA_DEF_RXQ_UDP(q)   | \
 79                                                  MVNETA_DEF_RXQ_BPDU(q)  | \
 80                                                  MVNETA_TX_UNSET_ERR_SUM | \
 81                                                  MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
 82 #define MVNETA_PORT_CONFIG_EXTEND                0x2404
 83 #define MVNETA_MAC_ADDR_LOW                      0x2414
 84 #define MVNETA_MAC_ADDR_HIGH                     0x2418
 85 #define MVNETA_SDMA_CONFIG                       0x241c
 86 #define      MVNETA_SDMA_BRST_SIZE_16            4
 87 #define      MVNETA_RX_BRST_SZ_MASK(burst)       ((burst) << 1)
 88 #define      MVNETA_RX_NO_DATA_SWAP              BIT(4)
 89 #define      MVNETA_TX_NO_DATA_SWAP              BIT(5)
 90 #define      MVNETA_DESC_SWAP                    BIT(6)
 91 #define      MVNETA_TX_BRST_SZ_MASK(burst)       ((burst) << 22)
 92 #define MVNETA_PORT_STATUS                       0x2444
 93 #define      MVNETA_TX_IN_PRGRS                  BIT(1)
 94 #define      MVNETA_TX_FIFO_EMPTY                BIT(8)
 95 #define MVNETA_RX_MIN_FRAME_SIZE                 0x247c
 96 #define MVNETA_SERDES_CFG                        0x24A0
 97 #define      MVNETA_SGMII_SERDES_PROTO           0x0cc7
 98 #define      MVNETA_QSGMII_SERDES_PROTO          0x0667
 99 #define MVNETA_TYPE_PRIO                         0x24bc
100 #define      MVNETA_FORCE_UNI                    BIT(21)
101 #define MVNETA_TXQ_CMD_1                         0x24e4
102 #define MVNETA_TXQ_CMD                           0x2448
103 #define      MVNETA_TXQ_DISABLE_SHIFT            8
104 #define      MVNETA_TXQ_ENABLE_MASK              0x000000ff
105 #define MVNETA_RX_DISCARD_FRAME_COUNT            0x2484
106 #define MVNETA_OVERRUN_FRAME_COUNT               0x2488
107 #define MVNETA_GMAC_CLOCK_DIVIDER                0x24f4
108 #define      MVNETA_GMAC_1MS_CLOCK_ENABLE        BIT(31)
109 #define MVNETA_ACC_MODE                          0x2500
110 #define MVNETA_CPU_MAP(cpu)                      (0x2540 + ((cpu) << 2))
111 #define      MVNETA_CPU_RXQ_ACCESS_ALL_MASK      0x000000ff
112 #define      MVNETA_CPU_TXQ_ACCESS_ALL_MASK      0x0000ff00
113 #define      MVNETA_CPU_RXQ_ACCESS(rxq)          BIT(rxq)
114 #define      MVNETA_CPU_TXQ_ACCESS(txq)          BIT(txq + 8)
115 #define MVNETA_RXQ_TIME_COAL_REG(q)              (0x2580 + ((q) << 2))
116 
117 /* Exception Interrupt Port/Queue Cause register
118  *
119  * Their behavior depend of the mapping done using the PCPX2Q
120  * registers. For a given CPU if the bit associated to a queue is not
121  * set, then for the register a read from this CPU will always return
122  * 0 and a write won't do anything
123  */
124 
125 #define MVNETA_INTR_NEW_CAUSE                    0x25a0
126 #define MVNETA_INTR_NEW_MASK                     0x25a4
127 
128 /* bits  0..7  = TXQ SENT, one bit per queue.
129  * bits  8..15 = RXQ OCCUP, one bit per queue.
130  * bits 16..23 = RXQ FREE, one bit per queue.
131  * bit  29 = OLD_REG_SUM, see old reg ?
132  * bit  30 = TX_ERR_SUM, one bit for 4 ports
133  * bit  31 = MISC_SUM,   one bit for 4 ports
134  */
135 #define      MVNETA_TX_INTR_MASK(nr_txqs)        (((1 << nr_txqs) - 1) << 0)
136 #define      MVNETA_TX_INTR_MASK_ALL             (0xff << 0)
137 #define      MVNETA_RX_INTR_MASK(nr_rxqs)        (((1 << nr_rxqs) - 1) << 8)
138 #define      MVNETA_RX_INTR_MASK_ALL             (0xff << 8)
139 #define      MVNETA_MISCINTR_INTR_MASK           BIT(31)
140 
141 #define MVNETA_INTR_OLD_CAUSE                    0x25a8
142 #define MVNETA_INTR_OLD_MASK                     0x25ac
143 
144 /* Data Path Port/Queue Cause Register */
145 #define MVNETA_INTR_MISC_CAUSE                   0x25b0
146 #define MVNETA_INTR_MISC_MASK                    0x25b4
147 
148 #define      MVNETA_CAUSE_PHY_STATUS_CHANGE      BIT(0)
149 #define      MVNETA_CAUSE_LINK_CHANGE            BIT(1)
150 #define      MVNETA_CAUSE_PTP                    BIT(4)
151 
152 #define      MVNETA_CAUSE_INTERNAL_ADDR_ERR      BIT(7)
153 #define      MVNETA_CAUSE_RX_OVERRUN             BIT(8)
154 #define      MVNETA_CAUSE_RX_CRC_ERROR           BIT(9)
155 #define      MVNETA_CAUSE_RX_LARGE_PKT           BIT(10)
156 #define      MVNETA_CAUSE_TX_UNDERUN             BIT(11)
157 #define      MVNETA_CAUSE_PRBS_ERR               BIT(12)
158 #define      MVNETA_CAUSE_PSC_SYNC_CHANGE        BIT(13)
159 #define      MVNETA_CAUSE_SERDES_SYNC_ERR        BIT(14)
160 
161 #define      MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT    16
162 #define      MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK   (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT)
163 #define      MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool)))
164 
165 #define      MVNETA_CAUSE_TXQ_ERROR_SHIFT        24
166 #define      MVNETA_CAUSE_TXQ_ERROR_ALL_MASK     (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT)
167 #define      MVNETA_CAUSE_TXQ_ERROR_MASK(q)      (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q)))
168 
169 #define MVNETA_INTR_ENABLE                       0x25b8
170 #define      MVNETA_TXQ_INTR_ENABLE_ALL_MASK     0x0000ff00
171 #define      MVNETA_RXQ_INTR_ENABLE_ALL_MASK     0x000000ff
172 
173 #define MVNETA_RXQ_CMD                           0x2680
174 #define      MVNETA_RXQ_DISABLE_SHIFT            8
175 #define      MVNETA_RXQ_ENABLE_MASK              0x000000ff
176 #define MVETH_TXQ_TOKEN_COUNT_REG(q)             (0x2700 + ((q) << 4))
177 #define MVETH_TXQ_TOKEN_CFG_REG(q)               (0x2704 + ((q) << 4))
178 #define MVNETA_GMAC_CTRL_0                       0x2c00
179 #define      MVNETA_GMAC_MAX_RX_SIZE_SHIFT       2
180 #define      MVNETA_GMAC_MAX_RX_SIZE_MASK        0x7ffc
181 #define      MVNETA_GMAC0_PORT_ENABLE            BIT(0)
182 #define MVNETA_GMAC_CTRL_2                       0x2c08
183 #define      MVNETA_GMAC2_INBAND_AN_ENABLE       BIT(0)
184 #define      MVNETA_GMAC2_PCS_ENABLE             BIT(3)
185 #define      MVNETA_GMAC2_PORT_RGMII             BIT(4)
186 #define      MVNETA_GMAC2_PORT_RESET             BIT(6)
187 #define MVNETA_GMAC_STATUS                       0x2c10
188 #define      MVNETA_GMAC_LINK_UP                 BIT(0)
189 #define      MVNETA_GMAC_SPEED_1000              BIT(1)
190 #define      MVNETA_GMAC_SPEED_100               BIT(2)
191 #define      MVNETA_GMAC_FULL_DUPLEX             BIT(3)
192 #define      MVNETA_GMAC_RX_FLOW_CTRL_ENABLE     BIT(4)
193 #define      MVNETA_GMAC_TX_FLOW_CTRL_ENABLE     BIT(5)
194 #define      MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE     BIT(6)
195 #define      MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE     BIT(7)
196 #define MVNETA_GMAC_AUTONEG_CONFIG               0x2c0c
197 #define      MVNETA_GMAC_FORCE_LINK_DOWN         BIT(0)
198 #define      MVNETA_GMAC_FORCE_LINK_PASS         BIT(1)
199 #define      MVNETA_GMAC_INBAND_AN_ENABLE        BIT(2)
200 #define      MVNETA_GMAC_CONFIG_MII_SPEED        BIT(5)
201 #define      MVNETA_GMAC_CONFIG_GMII_SPEED       BIT(6)
202 #define      MVNETA_GMAC_AN_SPEED_EN             BIT(7)
203 #define      MVNETA_GMAC_AN_FLOW_CTRL_EN         BIT(11)
204 #define      MVNETA_GMAC_CONFIG_FULL_DUPLEX      BIT(12)
205 #define      MVNETA_GMAC_AN_DUPLEX_EN            BIT(13)
206 #define MVNETA_MIB_COUNTERS_BASE                 0x3000
207 #define      MVNETA_MIB_LATE_COLLISION           0x7c
208 #define MVNETA_DA_FILT_SPEC_MCAST                0x3400
209 #define MVNETA_DA_FILT_OTH_MCAST                 0x3500
210 #define MVNETA_DA_FILT_UCAST_BASE                0x3600
211 #define MVNETA_TXQ_BASE_ADDR_REG(q)              (0x3c00 + ((q) << 2))
212 #define MVNETA_TXQ_SIZE_REG(q)                   (0x3c20 + ((q) << 2))
213 #define      MVNETA_TXQ_SENT_THRESH_ALL_MASK     0x3fff0000
214 #define      MVNETA_TXQ_SENT_THRESH_MASK(coal)   ((coal) << 16)
215 #define MVNETA_TXQ_UPDATE_REG(q)                 (0x3c60 + ((q) << 2))
216 #define      MVNETA_TXQ_DEC_SENT_SHIFT           16
217 #define MVNETA_TXQ_STATUS_REG(q)                 (0x3c40 + ((q) << 2))
218 #define      MVNETA_TXQ_SENT_DESC_SHIFT          16
219 #define      MVNETA_TXQ_SENT_DESC_MASK           0x3fff0000
220 #define MVNETA_PORT_TX_RESET                     0x3cf0
221 #define      MVNETA_PORT_TX_DMA_RESET            BIT(0)
222 #define MVNETA_TX_MTU                            0x3e0c
223 #define MVNETA_TX_TOKEN_SIZE                     0x3e14
224 #define      MVNETA_TX_TOKEN_SIZE_MAX            0xffffffff
225 #define MVNETA_TXQ_TOKEN_SIZE_REG(q)             (0x3e40 + ((q) << 2))
226 #define      MVNETA_TXQ_TOKEN_SIZE_MAX           0x7fffffff
227 
228 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK      0xff
229 
230 /* Descriptor ring Macros */
231 #define MVNETA_QUEUE_NEXT_DESC(q, index)        \
232         (((index) < (q)->last_desc) ? ((index) + 1) : 0)
233 
234 /* Various constants */
235 
236 /* Coalescing */
237 #define MVNETA_TXDONE_COAL_PKTS         1
238 #define MVNETA_RX_COAL_PKTS             32
239 #define MVNETA_RX_COAL_USEC             100
240 
241 /* The two bytes Marvell header. Either contains a special value used
242  * by Marvell switches when a specific hardware mode is enabled (not
243  * supported by this driver) or is filled automatically by zeroes on
244  * the RX side. Those two bytes being at the front of the Ethernet
245  * header, they allow to have the IP header aligned on a 4 bytes
246  * boundary automatically: the hardware skips those two bytes on its
247  * own.
248  */
249 #define MVNETA_MH_SIZE                  2
250 
251 #define MVNETA_VLAN_TAG_LEN             4
252 
253 #define MVNETA_CPU_D_CACHE_LINE_SIZE    32
254 #define MVNETA_TX_CSUM_DEF_SIZE         1600
255 #define MVNETA_TX_CSUM_MAX_SIZE         9800
256 #define MVNETA_ACC_MODE_EXT             1
257 
258 /* Timeout constants */
259 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC  1000
260 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC  1000
261 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT    10000
262 
263 #define MVNETA_TX_MTU_MAX               0x3ffff
264 
265 /* The RSS lookup table actually has 256 entries but we do not use
266  * them yet
267  */
268 #define MVNETA_RSS_LU_TABLE_SIZE        1
269 
270 /* TSO header size */
271 #define TSO_HEADER_SIZE 128
272 
273 /* Max number of Rx descriptors */
274 #define MVNETA_MAX_RXD 128
275 
276 /* Max number of Tx descriptors */
277 #define MVNETA_MAX_TXD 532
278 
279 /* Max number of allowed TCP segments for software TSO */
280 #define MVNETA_MAX_TSO_SEGS 100
281 
282 #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
283 
284 /* descriptor aligned size */
285 #define MVNETA_DESC_ALIGNED_SIZE        32
286 
287 #define MVNETA_RX_PKT_SIZE(mtu) \
288         ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
289               ETH_HLEN + ETH_FCS_LEN,                        \
290               MVNETA_CPU_D_CACHE_LINE_SIZE)
291 
292 #define IS_TSO_HEADER(txq, addr) \
293         ((addr >= txq->tso_hdrs_phys) && \
294          (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE))
295 
296 #define MVNETA_RX_BUF_SIZE(pkt_size)   ((pkt_size) + NET_SKB_PAD)
297 
298 struct mvneta_statistic {
299         unsigned short offset;
300         unsigned short type;
301         const char name[ETH_GSTRING_LEN];
302 };
303 
304 #define T_REG_32        32
305 #define T_REG_64        64
306 
307 static const struct mvneta_statistic mvneta_statistics[] = {
308         { 0x3000, T_REG_64, "good_octets_received", },
309         { 0x3010, T_REG_32, "good_frames_received", },
310         { 0x3008, T_REG_32, "bad_octets_received", },
311         { 0x3014, T_REG_32, "bad_frames_received", },
312         { 0x3018, T_REG_32, "broadcast_frames_received", },
313         { 0x301c, T_REG_32, "multicast_frames_received", },
314         { 0x3050, T_REG_32, "unrec_mac_control_received", },
315         { 0x3058, T_REG_32, "good_fc_received", },
316         { 0x305c, T_REG_32, "bad_fc_received", },
317         { 0x3060, T_REG_32, "undersize_received", },
318         { 0x3064, T_REG_32, "fragments_received", },
319         { 0x3068, T_REG_32, "oversize_received", },
320         { 0x306c, T_REG_32, "jabber_received", },
321         { 0x3070, T_REG_32, "mac_receive_error", },
322         { 0x3074, T_REG_32, "bad_crc_event", },
323         { 0x3078, T_REG_32, "collision", },
324         { 0x307c, T_REG_32, "late_collision", },
325         { 0x2484, T_REG_32, "rx_discard", },
326         { 0x2488, T_REG_32, "rx_overrun", },
327         { 0x3020, T_REG_32, "frames_64_octets", },
328         { 0x3024, T_REG_32, "frames_65_to_127_octets", },
329         { 0x3028, T_REG_32, "frames_128_to_255_octets", },
330         { 0x302c, T_REG_32, "frames_256_to_511_octets", },
331         { 0x3030, T_REG_32, "frames_512_to_1023_octets", },
332         { 0x3034, T_REG_32, "frames_1024_to_max_octets", },
333         { 0x3038, T_REG_64, "good_octets_sent", },
334         { 0x3040, T_REG_32, "good_frames_sent", },
335         { 0x3044, T_REG_32, "excessive_collision", },
336         { 0x3048, T_REG_32, "multicast_frames_sent", },
337         { 0x304c, T_REG_32, "broadcast_frames_sent", },
338         { 0x3054, T_REG_32, "fc_sent", },
339         { 0x300c, T_REG_32, "internal_mac_transmit_err", },
340 };
341 
342 struct mvneta_pcpu_stats {
343         struct  u64_stats_sync syncp;
344         u64     rx_packets;
345         u64     rx_bytes;
346         u64     tx_packets;
347         u64     tx_bytes;
348 };
349 
350 struct mvneta_pcpu_port {
351         /* Pointer to the shared port */
352         struct mvneta_port      *pp;
353 
354         /* Pointer to the CPU-local NAPI struct */
355         struct napi_struct      napi;
356 
357         /* Cause of the previous interrupt */
358         u32                     cause_rx_tx;
359 };
360 
361 struct mvneta_port {
362         struct mvneta_pcpu_port __percpu        *ports;
363         struct mvneta_pcpu_stats __percpu       *stats;
364 
365         int pkt_size;
366         unsigned int frag_size;
367         void __iomem *base;
368         struct mvneta_rx_queue *rxqs;
369         struct mvneta_tx_queue *txqs;
370         struct net_device *dev;
371         struct notifier_block cpu_notifier;
372         int rxq_def;
373         /* Protect the access to the percpu interrupt registers,
374          * ensuring that the configuration remains coherent.
375          */
376         spinlock_t lock;
377         bool is_stopped;
378 
379         /* Core clock */
380         struct clk *clk;
381         /* AXI clock */
382         struct clk *clk_bus;
383         u8 mcast_count[256];
384         u16 tx_ring_size;
385         u16 rx_ring_size;
386 
387         struct mii_bus *mii_bus;
388         struct phy_device *phy_dev;
389         phy_interface_t phy_interface;
390         struct device_node *phy_node;
391         unsigned int link;
392         unsigned int duplex;
393         unsigned int speed;
394         unsigned int tx_csum_limit;
395         unsigned int use_inband_status:1;
396 
397         u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
398 
399         u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
400 };
401 
402 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
403  * layout of the transmit and reception DMA descriptors, and their
404  * layout is therefore defined by the hardware design
405  */
406 
407 #define MVNETA_TX_L3_OFF_SHIFT  0
408 #define MVNETA_TX_IP_HLEN_SHIFT 8
409 #define MVNETA_TX_L4_UDP        BIT(16)
410 #define MVNETA_TX_L3_IP6        BIT(17)
411 #define MVNETA_TXD_IP_CSUM      BIT(18)
412 #define MVNETA_TXD_Z_PAD        BIT(19)
413 #define MVNETA_TXD_L_DESC       BIT(20)
414 #define MVNETA_TXD_F_DESC       BIT(21)
415 #define MVNETA_TXD_FLZ_DESC     (MVNETA_TXD_Z_PAD  | \
416                                  MVNETA_TXD_L_DESC | \
417                                  MVNETA_TXD_F_DESC)
418 #define MVNETA_TX_L4_CSUM_FULL  BIT(30)
419 #define MVNETA_TX_L4_CSUM_NOT   BIT(31)
420 
421 #define MVNETA_RXD_ERR_CRC              0x0
422 #define MVNETA_RXD_ERR_SUMMARY          BIT(16)
423 #define MVNETA_RXD_ERR_OVERRUN          BIT(17)
424 #define MVNETA_RXD_ERR_LEN              BIT(18)
425 #define MVNETA_RXD_ERR_RESOURCE         (BIT(17) | BIT(18))
426 #define MVNETA_RXD_ERR_CODE_MASK        (BIT(17) | BIT(18))
427 #define MVNETA_RXD_L3_IP4               BIT(25)
428 #define MVNETA_RXD_FIRST_LAST_DESC      (BIT(26) | BIT(27))
429 #define MVNETA_RXD_L4_CSUM_OK           BIT(30)
430 
431 #if defined(__LITTLE_ENDIAN)
432 struct mvneta_tx_desc {
433         u32  command;           /* Options used by HW for packet transmitting.*/
434         u16  reserverd1;        /* csum_l4 (for future use)             */
435         u16  data_size;         /* Data size of transmitted packet in bytes */
436         u32  buf_phys_addr;     /* Physical addr of transmitted buffer  */
437         u32  reserved2;         /* hw_cmd - (for future use, PMT)       */
438         u32  reserved3[4];      /* Reserved - (for future use)          */
439 };
440 
441 struct mvneta_rx_desc {
442         u32  status;            /* Info about received packet           */
443         u16  reserved1;         /* pnc_info - (for future use, PnC)     */
444         u16  data_size;         /* Size of received packet in bytes     */
445 
446         u32  buf_phys_addr;     /* Physical address of the buffer       */
447         u32  reserved2;         /* pnc_flow_id  (for future use, PnC)   */
448 
449         u32  buf_cookie;        /* cookie for access to RX buffer in rx path */
450         u16  reserved3;         /* prefetch_cmd, for future use         */
451         u16  reserved4;         /* csum_l4 - (for future use, PnC)      */
452 
453         u32  reserved5;         /* pnc_extra PnC (for future use, PnC)  */
454         u32  reserved6;         /* hw_cmd (for future use, PnC and HWF) */
455 };
456 #else
457 struct mvneta_tx_desc {
458         u16  data_size;         /* Data size of transmitted packet in bytes */
459         u16  reserverd1;        /* csum_l4 (for future use)             */
460         u32  command;           /* Options used by HW for packet transmitting.*/
461         u32  reserved2;         /* hw_cmd - (for future use, PMT)       */
462         u32  buf_phys_addr;     /* Physical addr of transmitted buffer  */
463         u32  reserved3[4];      /* Reserved - (for future use)          */
464 };
465 
466 struct mvneta_rx_desc {
467         u16  data_size;         /* Size of received packet in bytes     */
468         u16  reserved1;         /* pnc_info - (for future use, PnC)     */
469         u32  status;            /* Info about received packet           */
470 
471         u32  reserved2;         /* pnc_flow_id  (for future use, PnC)   */
472         u32  buf_phys_addr;     /* Physical address of the buffer       */
473 
474         u16  reserved4;         /* csum_l4 - (for future use, PnC)      */
475         u16  reserved3;         /* prefetch_cmd, for future use         */
476         u32  buf_cookie;        /* cookie for access to RX buffer in rx path */
477 
478         u32  reserved5;         /* pnc_extra PnC (for future use, PnC)  */
479         u32  reserved6;         /* hw_cmd (for future use, PnC and HWF) */
480 };
481 #endif
482 
483 struct mvneta_tx_queue {
484         /* Number of this TX queue, in the range 0-7 */
485         u8 id;
486 
487         /* Number of TX DMA descriptors in the descriptor ring */
488         int size;
489 
490         /* Number of currently used TX DMA descriptor in the
491          * descriptor ring
492          */
493         int count;
494         int tx_stop_threshold;
495         int tx_wake_threshold;
496 
497         /* Array of transmitted skb */
498         struct sk_buff **tx_skb;
499 
500         /* Index of last TX DMA descriptor that was inserted */
501         int txq_put_index;
502 
503         /* Index of the TX DMA descriptor to be cleaned up */
504         int txq_get_index;
505 
506         u32 done_pkts_coal;
507 
508         /* Virtual address of the TX DMA descriptors array */
509         struct mvneta_tx_desc *descs;
510 
511         /* DMA address of the TX DMA descriptors array */
512         dma_addr_t descs_phys;
513 
514         /* Index of the last TX DMA descriptor */
515         int last_desc;
516 
517         /* Index of the next TX DMA descriptor to process */
518         int next_desc_to_proc;
519 
520         /* DMA buffers for TSO headers */
521         char *tso_hdrs;
522 
523         /* DMA address of TSO headers */
524         dma_addr_t tso_hdrs_phys;
525 
526         /* Affinity mask for CPUs*/
527         cpumask_t affinity_mask;
528 };
529 
530 struct mvneta_rx_queue {
531         /* rx queue number, in the range 0-7 */
532         u8 id;
533 
534         /* num of rx descriptors in the rx descriptor ring */
535         int size;
536 
537         /* counter of times when mvneta_refill() failed */
538         int missed;
539 
540         u32 pkts_coal;
541         u32 time_coal;
542 
543         /* Virtual address of the RX DMA descriptors array */
544         struct mvneta_rx_desc *descs;
545 
546         /* DMA address of the RX DMA descriptors array */
547         dma_addr_t descs_phys;
548 
549         /* Index of the last RX DMA descriptor */
550         int last_desc;
551 
552         /* Index of the next RX DMA descriptor to process */
553         int next_desc_to_proc;
554 };
555 
556 /* The hardware supports eight (8) rx queues, but we are only allowing
557  * the first one to be used. Therefore, let's just allocate one queue.
558  */
559 static int rxq_number = 8;
560 static int txq_number = 8;
561 
562 static int rxq_def;
563 
564 static int rx_copybreak __read_mostly = 256;
565 
566 #define MVNETA_DRIVER_NAME "mvneta"
567 #define MVNETA_DRIVER_VERSION "1.0"
568 
569 /* Utility/helper methods */
570 
571 /* Write helper method */
572 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
573 {
574         writel(data, pp->base + offset);
575 }
576 
577 /* Read helper method */
578 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
579 {
580         return readl(pp->base + offset);
581 }
582 
583 /* Increment txq get counter */
584 static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq)
585 {
586         txq->txq_get_index++;
587         if (txq->txq_get_index == txq->size)
588                 txq->txq_get_index = 0;
589 }
590 
591 /* Increment txq put counter */
592 static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq)
593 {
594         txq->txq_put_index++;
595         if (txq->txq_put_index == txq->size)
596                 txq->txq_put_index = 0;
597 }
598 
599 
600 /* Clear all MIB counters */
601 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
602 {
603         int i;
604         u32 dummy;
605 
606         /* Perform dummy reads from MIB counters */
607         for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
608                 dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
609         dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT);
610         dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT);
611 }
612 
613 /* Get System Network Statistics */
614 struct rtnl_link_stats64 *mvneta_get_stats64(struct net_device *dev,
615                                              struct rtnl_link_stats64 *stats)
616 {
617         struct mvneta_port *pp = netdev_priv(dev);
618         unsigned int start;
619         int cpu;
620 
621         for_each_possible_cpu(cpu) {
622                 struct mvneta_pcpu_stats *cpu_stats;
623                 u64 rx_packets;
624                 u64 rx_bytes;
625                 u64 tx_packets;
626                 u64 tx_bytes;
627 
628                 cpu_stats = per_cpu_ptr(pp->stats, cpu);
629                 do {
630                         start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
631                         rx_packets = cpu_stats->rx_packets;
632                         rx_bytes   = cpu_stats->rx_bytes;
633                         tx_packets = cpu_stats->tx_packets;
634                         tx_bytes   = cpu_stats->tx_bytes;
635                 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
636 
637                 stats->rx_packets += rx_packets;
638                 stats->rx_bytes   += rx_bytes;
639                 stats->tx_packets += tx_packets;
640                 stats->tx_bytes   += tx_bytes;
641         }
642 
643         stats->rx_errors        = dev->stats.rx_errors;
644         stats->rx_dropped       = dev->stats.rx_dropped;
645 
646         stats->tx_dropped       = dev->stats.tx_dropped;
647 
648         return stats;
649 }
650 
651 /* Rx descriptors helper methods */
652 
653 /* Checks whether the RX descriptor having this status is both the first
654  * and the last descriptor for the RX packet. Each RX packet is currently
655  * received through a single RX descriptor, so not having each RX
656  * descriptor with its first and last bits set is an error
657  */
658 static int mvneta_rxq_desc_is_first_last(u32 status)
659 {
660         return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
661                 MVNETA_RXD_FIRST_LAST_DESC;
662 }
663 
664 /* Add number of descriptors ready to receive new packets */
665 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
666                                           struct mvneta_rx_queue *rxq,
667                                           int ndescs)
668 {
669         /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
670          * be added at once
671          */
672         while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
673                 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
674                             (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
675                              MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
676                 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
677         }
678 
679         mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
680                     (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
681 }
682 
683 /* Get number of RX descriptors occupied by received packets */
684 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
685                                         struct mvneta_rx_queue *rxq)
686 {
687         u32 val;
688 
689         val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
690         return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
691 }
692 
693 /* Update num of rx desc called upon return from rx path or
694  * from mvneta_rxq_drop_pkts().
695  */
696 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
697                                        struct mvneta_rx_queue *rxq,
698                                        int rx_done, int rx_filled)
699 {
700         u32 val;
701 
702         if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
703                 val = rx_done |
704                   (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
705                 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
706                 return;
707         }
708 
709         /* Only 255 descriptors can be added at once */
710         while ((rx_done > 0) || (rx_filled > 0)) {
711                 if (rx_done <= 0xff) {
712                         val = rx_done;
713                         rx_done = 0;
714                 } else {
715                         val = 0xff;
716                         rx_done -= 0xff;
717                 }
718                 if (rx_filled <= 0xff) {
719                         val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
720                         rx_filled = 0;
721                 } else {
722                         val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
723                         rx_filled -= 0xff;
724                 }
725                 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
726         }
727 }
728 
729 /* Get pointer to next RX descriptor to be processed by SW */
730 static struct mvneta_rx_desc *
731 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
732 {
733         int rx_desc = rxq->next_desc_to_proc;
734 
735         rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
736         prefetch(rxq->descs + rxq->next_desc_to_proc);
737         return rxq->descs + rx_desc;
738 }
739 
740 /* Change maximum receive size of the port. */
741 static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
742 {
743         u32 val;
744 
745         val =  mvreg_read(pp, MVNETA_GMAC_CTRL_0);
746         val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
747         val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
748                 MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
749         mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
750 }
751 
752 
753 /* Set rx queue offset */
754 static void mvneta_rxq_offset_set(struct mvneta_port *pp,
755                                   struct mvneta_rx_queue *rxq,
756                                   int offset)
757 {
758         u32 val;
759 
760         val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
761         val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
762 
763         /* Offset is in */
764         val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
765         mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
766 }
767 
768 
769 /* Tx descriptors helper methods */
770 
771 /* Update HW with number of TX descriptors to be sent */
772 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
773                                      struct mvneta_tx_queue *txq,
774                                      int pend_desc)
775 {
776         u32 val;
777 
778         /* Only 255 descriptors can be added at once ; Assume caller
779          * process TX desriptors in quanta less than 256
780          */
781         val = pend_desc;
782         mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
783 }
784 
785 /* Get pointer to next TX descriptor to be processed (send) by HW */
786 static struct mvneta_tx_desc *
787 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
788 {
789         int tx_desc = txq->next_desc_to_proc;
790 
791         txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
792         return txq->descs + tx_desc;
793 }
794 
795 /* Release the last allocated TX descriptor. Useful to handle DMA
796  * mapping failures in the TX path.
797  */
798 static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq)
799 {
800         if (txq->next_desc_to_proc == 0)
801                 txq->next_desc_to_proc = txq->last_desc - 1;
802         else
803                 txq->next_desc_to_proc--;
804 }
805 
806 /* Set rxq buf size */
807 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
808                                     struct mvneta_rx_queue *rxq,
809                                     int buf_size)
810 {
811         u32 val;
812 
813         val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
814 
815         val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
816         val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
817 
818         mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
819 }
820 
821 /* Disable buffer management (BM) */
822 static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
823                                   struct mvneta_rx_queue *rxq)
824 {
825         u32 val;
826 
827         val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
828         val &= ~MVNETA_RXQ_HW_BUF_ALLOC;
829         mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
830 }
831 
832 /* Start the Ethernet port RX and TX activity */
833 static void mvneta_port_up(struct mvneta_port *pp)
834 {
835         int queue;
836         u32 q_map;
837 
838         /* Enable all initialized TXs. */
839         q_map = 0;
840         for (queue = 0; queue < txq_number; queue++) {
841                 struct mvneta_tx_queue *txq = &pp->txqs[queue];
842                 if (txq->descs != NULL)
843                         q_map |= (1 << queue);
844         }
845         mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
846 
847         /* Enable all initialized RXQs. */
848         for (queue = 0; queue < rxq_number; queue++) {
849                 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
850 
851                 if (rxq->descs != NULL)
852                         q_map |= (1 << queue);
853         }
854         mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
855 }
856 
857 /* Stop the Ethernet port activity */
858 static void mvneta_port_down(struct mvneta_port *pp)
859 {
860         u32 val;
861         int count;
862 
863         /* Stop Rx port activity. Check port Rx activity. */
864         val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
865 
866         /* Issue stop command for active channels only */
867         if (val != 0)
868                 mvreg_write(pp, MVNETA_RXQ_CMD,
869                             val << MVNETA_RXQ_DISABLE_SHIFT);
870 
871         /* Wait for all Rx activity to terminate. */
872         count = 0;
873         do {
874                 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
875                         netdev_warn(pp->dev,
876                                     "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
877                                     val);
878                         break;
879                 }
880                 mdelay(1);
881 
882                 val = mvreg_read(pp, MVNETA_RXQ_CMD);
883         } while (val & 0xff);
884 
885         /* Stop Tx port activity. Check port Tx activity. Issue stop
886          * command for active channels only
887          */
888         val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
889 
890         if (val != 0)
891                 mvreg_write(pp, MVNETA_TXQ_CMD,
892                             (val << MVNETA_TXQ_DISABLE_SHIFT));
893 
894         /* Wait for all Tx activity to terminate. */
895         count = 0;
896         do {
897                 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
898                         netdev_warn(pp->dev,
899                                     "TIMEOUT for TX stopped status=0x%08x\n",
900                                     val);
901                         break;
902                 }
903                 mdelay(1);
904 
905                 /* Check TX Command reg that all Txqs are stopped */
906                 val = mvreg_read(pp, MVNETA_TXQ_CMD);
907 
908         } while (val & 0xff);
909 
910         /* Double check to verify that TX FIFO is empty */
911         count = 0;
912         do {
913                 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
914                         netdev_warn(pp->dev,
915                                     "TX FIFO empty timeout status=0x08%x\n",
916                                     val);
917                         break;
918                 }
919                 mdelay(1);
920 
921                 val = mvreg_read(pp, MVNETA_PORT_STATUS);
922         } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
923                  (val & MVNETA_TX_IN_PRGRS));
924 
925         udelay(200);
926 }
927 
928 /* Enable the port by setting the port enable bit of the MAC control register */
929 static void mvneta_port_enable(struct mvneta_port *pp)
930 {
931         u32 val;
932 
933         /* Enable port */
934         val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
935         val |= MVNETA_GMAC0_PORT_ENABLE;
936         mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
937 }
938 
939 /* Disable the port and wait for about 200 usec before retuning */
940 static void mvneta_port_disable(struct mvneta_port *pp)
941 {
942         u32 val;
943 
944         /* Reset the Enable bit in the Serial Control Register */
945         val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
946         val &= ~MVNETA_GMAC0_PORT_ENABLE;
947         mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
948 
949         udelay(200);
950 }
951 
952 /* Multicast tables methods */
953 
954 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
955 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
956 {
957         int offset;
958         u32 val;
959 
960         if (queue == -1) {
961                 val = 0;
962         } else {
963                 val = 0x1 | (queue << 1);
964                 val |= (val << 24) | (val << 16) | (val << 8);
965         }
966 
967         for (offset = 0; offset <= 0xc; offset += 4)
968                 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
969 }
970 
971 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
972 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
973 {
974         int offset;
975         u32 val;
976 
977         if (queue == -1) {
978                 val = 0;
979         } else {
980                 val = 0x1 | (queue << 1);
981                 val |= (val << 24) | (val << 16) | (val << 8);
982         }
983 
984         for (offset = 0; offset <= 0xfc; offset += 4)
985                 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
986 
987 }
988 
989 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
990 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
991 {
992         int offset;
993         u32 val;
994 
995         if (queue == -1) {
996                 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
997                 val = 0;
998         } else {
999                 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
1000                 val = 0x1 | (queue << 1);
1001                 val |= (val << 24) | (val << 16) | (val << 8);
1002         }
1003 
1004         for (offset = 0; offset <= 0xfc; offset += 4)
1005                 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
1006 }
1007 
1008 static void mvneta_set_autoneg(struct mvneta_port *pp, int enable)
1009 {
1010         u32 val;
1011 
1012         if (enable) {
1013                 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1014                 val &= ~(MVNETA_GMAC_FORCE_LINK_PASS |
1015                          MVNETA_GMAC_FORCE_LINK_DOWN |
1016                          MVNETA_GMAC_AN_FLOW_CTRL_EN);
1017                 val |= MVNETA_GMAC_INBAND_AN_ENABLE |
1018                        MVNETA_GMAC_AN_SPEED_EN |
1019                        MVNETA_GMAC_AN_DUPLEX_EN;
1020                 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1021 
1022                 val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
1023                 val |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
1024                 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
1025 
1026                 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
1027                 val |= MVNETA_GMAC2_INBAND_AN_ENABLE;
1028                 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
1029         } else {
1030                 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1031                 val &= ~(MVNETA_GMAC_INBAND_AN_ENABLE |
1032                        MVNETA_GMAC_AN_SPEED_EN |
1033                        MVNETA_GMAC_AN_DUPLEX_EN);
1034                 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1035 
1036                 val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
1037                 val &= ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
1038                 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
1039 
1040                 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
1041                 val &= ~MVNETA_GMAC2_INBAND_AN_ENABLE;
1042                 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
1043         }
1044 }
1045 
1046 static void mvneta_percpu_unmask_interrupt(void *arg)
1047 {
1048         struct mvneta_port *pp = arg;
1049 
1050         /* All the queue are unmasked, but actually only the ones
1051          * mapped to this CPU will be unmasked
1052          */
1053         mvreg_write(pp, MVNETA_INTR_NEW_MASK,
1054                     MVNETA_RX_INTR_MASK_ALL |
1055                     MVNETA_TX_INTR_MASK_ALL |
1056                     MVNETA_MISCINTR_INTR_MASK);
1057 }
1058 
1059 static void mvneta_percpu_mask_interrupt(void *arg)
1060 {
1061         struct mvneta_port *pp = arg;
1062 
1063         /* All the queue are masked, but actually only the ones
1064          * mapped to this CPU will be masked
1065          */
1066         mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
1067         mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
1068         mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
1069 }
1070 
1071 static void mvneta_percpu_clear_intr_cause(void *arg)
1072 {
1073         struct mvneta_port *pp = arg;
1074 
1075         /* All the queue are cleared, but actually only the ones
1076          * mapped to this CPU will be cleared
1077          */
1078         mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
1079         mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
1080         mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
1081 }
1082 
1083 /* This method sets defaults to the NETA port:
1084  *      Clears interrupt Cause and Mask registers.
1085  *      Clears all MAC tables.
1086  *      Sets defaults to all registers.
1087  *      Resets RX and TX descriptor rings.
1088  *      Resets PHY.
1089  * This method can be called after mvneta_port_down() to return the port
1090  *      settings to defaults.
1091  */
1092 static void mvneta_defaults_set(struct mvneta_port *pp)
1093 {
1094         int cpu;
1095         int queue;
1096         u32 val;
1097         int max_cpu = num_present_cpus();
1098 
1099         /* Clear all Cause registers */
1100         on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
1101 
1102         /* Mask all interrupts */
1103         on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
1104         mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
1105 
1106         /* Enable MBUS Retry bit16 */
1107         mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
1108 
1109         /* Set CPU queue access map. CPUs are assigned to the RX and
1110          * TX queues modulo their number. If there is only one TX
1111          * queue then it is assigned to the CPU associated to the
1112          * default RX queue.
1113          */
1114         for_each_present_cpu(cpu) {
1115                 int rxq_map = 0, txq_map = 0;
1116                 int rxq, txq;
1117 
1118                 for (rxq = 0; rxq < rxq_number; rxq++)
1119                         if ((rxq % max_cpu) == cpu)
1120                                 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
1121 
1122                 for (txq = 0; txq < txq_number; txq++)
1123                         if ((txq % max_cpu) == cpu)
1124                                 txq_map |= MVNETA_CPU_TXQ_ACCESS(txq);
1125 
1126                 /* With only one TX queue we configure a special case
1127                  * which will allow to get all the irq on a single
1128                  * CPU
1129                  */
1130                 if (txq_number == 1)
1131                         txq_map = (cpu == pp->rxq_def) ?
1132                                 MVNETA_CPU_TXQ_ACCESS(1) : 0;
1133 
1134                 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
1135         }
1136 
1137         /* Reset RX and TX DMAs */
1138         mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
1139         mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
1140 
1141         /* Disable Legacy WRR, Disable EJP, Release from reset */
1142         mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
1143         for (queue = 0; queue < txq_number; queue++) {
1144                 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
1145                 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
1146         }
1147 
1148         mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
1149         mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
1150 
1151         /* Set Port Acceleration Mode */
1152         val = MVNETA_ACC_MODE_EXT;
1153         mvreg_write(pp, MVNETA_ACC_MODE, val);
1154 
1155         /* Update val of portCfg register accordingly with all RxQueue types */
1156         val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
1157         mvreg_write(pp, MVNETA_PORT_CONFIG, val);
1158 
1159         val = 0;
1160         mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
1161         mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
1162 
1163         /* Build PORT_SDMA_CONFIG_REG */
1164         val = 0;
1165 
1166         /* Default burst size */
1167         val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1168         val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1169         val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
1170 
1171 #if defined(__BIG_ENDIAN)
1172         val |= MVNETA_DESC_SWAP;
1173 #endif
1174 
1175         /* Assign port SDMA configuration */
1176         mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
1177 
1178         /* Disable PHY polling in hardware, since we're using the
1179          * kernel phylib to do this.
1180          */
1181         val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
1182         val &= ~MVNETA_PHY_POLLING_ENABLE;
1183         mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
1184 
1185         mvneta_set_autoneg(pp, pp->use_inband_status);
1186         mvneta_set_ucast_table(pp, -1);
1187         mvneta_set_special_mcast_table(pp, -1);
1188         mvneta_set_other_mcast_table(pp, -1);
1189 
1190         /* Set port interrupt enable register - default enable all */
1191         mvreg_write(pp, MVNETA_INTR_ENABLE,
1192                     (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
1193                      | MVNETA_TXQ_INTR_ENABLE_ALL_MASK));
1194 
1195         mvneta_mib_counters_clear(pp);
1196 }
1197 
1198 /* Set max sizes for tx queues */
1199 static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size)
1200 
1201 {
1202         u32 val, size, mtu;
1203         int queue;
1204 
1205         mtu = max_tx_size * 8;
1206         if (mtu > MVNETA_TX_MTU_MAX)
1207                 mtu = MVNETA_TX_MTU_MAX;
1208 
1209         /* Set MTU */
1210         val = mvreg_read(pp, MVNETA_TX_MTU);
1211         val &= ~MVNETA_TX_MTU_MAX;
1212         val |= mtu;
1213         mvreg_write(pp, MVNETA_TX_MTU, val);
1214 
1215         /* TX token size and all TXQs token size must be larger that MTU */
1216         val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
1217 
1218         size = val & MVNETA_TX_TOKEN_SIZE_MAX;
1219         if (size < mtu) {
1220                 size = mtu;
1221                 val &= ~MVNETA_TX_TOKEN_SIZE_MAX;
1222                 val |= size;
1223                 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
1224         }
1225         for (queue = 0; queue < txq_number; queue++) {
1226                 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
1227 
1228                 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX;
1229                 if (size < mtu) {
1230                         size = mtu;
1231                         val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX;
1232                         val |= size;
1233                         mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
1234                 }
1235         }
1236 }
1237 
1238 /* Set unicast address */
1239 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
1240                                   int queue)
1241 {
1242         unsigned int unicast_reg;
1243         unsigned int tbl_offset;
1244         unsigned int reg_offset;
1245 
1246         /* Locate the Unicast table entry */
1247         last_nibble = (0xf & last_nibble);
1248 
1249         /* offset from unicast tbl base */
1250         tbl_offset = (last_nibble / 4) * 4;
1251 
1252         /* offset within the above reg  */
1253         reg_offset = last_nibble % 4;
1254 
1255         unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
1256 
1257         if (queue == -1) {
1258                 /* Clear accepts frame bit at specified unicast DA tbl entry */
1259                 unicast_reg &= ~(0xff << (8 * reg_offset));
1260         } else {
1261                 unicast_reg &= ~(0xff << (8 * reg_offset));
1262                 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1263         }
1264 
1265         mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
1266 }
1267 
1268 /* Set mac address */
1269 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
1270                                 int queue)
1271 {
1272         unsigned int mac_h;
1273         unsigned int mac_l;
1274 
1275         if (queue != -1) {
1276                 mac_l = (addr[4] << 8) | (addr[5]);
1277                 mac_h = (addr[0] << 24) | (addr[1] << 16) |
1278                         (addr[2] << 8) | (addr[3] << 0);
1279 
1280                 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1281                 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1282         }
1283 
1284         /* Accept frames of this address */
1285         mvneta_set_ucast_addr(pp, addr[5], queue);
1286 }
1287 
1288 /* Set the number of packets that will be received before RX interrupt
1289  * will be generated by HW.
1290  */
1291 static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
1292                                     struct mvneta_rx_queue *rxq, u32 value)
1293 {
1294         mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1295                     value | MVNETA_RXQ_NON_OCCUPIED(0));
1296         rxq->pkts_coal = value;
1297 }
1298 
1299 /* Set the time delay in usec before RX interrupt will be generated by
1300  * HW.
1301  */
1302 static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
1303                                     struct mvneta_rx_queue *rxq, u32 value)
1304 {
1305         u32 val;
1306         unsigned long clk_rate;
1307 
1308         clk_rate = clk_get_rate(pp->clk);
1309         val = (clk_rate / 1000000) * value;
1310 
1311         mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1312         rxq->time_coal = value;
1313 }
1314 
1315 /* Set threshold for TX_DONE pkts coalescing */
1316 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp,
1317                                          struct mvneta_tx_queue *txq, u32 value)
1318 {
1319         u32 val;
1320 
1321         val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1322 
1323         val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK;
1324         val |= MVNETA_TXQ_SENT_THRESH_MASK(value);
1325 
1326         mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1327 
1328         txq->done_pkts_coal = value;
1329 }
1330 
1331 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1332 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
1333                                 u32 phys_addr, u32 cookie)
1334 {
1335         rx_desc->buf_cookie = cookie;
1336         rx_desc->buf_phys_addr = phys_addr;
1337 }
1338 
1339 /* Decrement sent descriptors counter */
1340 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
1341                                      struct mvneta_tx_queue *txq,
1342                                      int sent_desc)
1343 {
1344         u32 val;
1345 
1346         /* Only 255 TX descriptors can be updated at once */
1347         while (sent_desc > 0xff) {
1348                 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
1349                 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1350                 sent_desc = sent_desc - 0xff;
1351         }
1352 
1353         val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
1354         mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1355 }
1356 
1357 /* Get number of TX descriptors already sent by HW */
1358 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
1359                                         struct mvneta_tx_queue *txq)
1360 {
1361         u32 val;
1362         int sent_desc;
1363 
1364         val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
1365         sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
1366                 MVNETA_TXQ_SENT_DESC_SHIFT;
1367 
1368         return sent_desc;
1369 }
1370 
1371 /* Get number of sent descriptors and decrement counter.
1372  *  The number of sent descriptors is returned.
1373  */
1374 static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp,
1375                                      struct mvneta_tx_queue *txq)
1376 {
1377         int sent_desc;
1378 
1379         /* Get number of sent descriptors */
1380         sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1381 
1382         /* Decrement sent descriptors counter */
1383         if (sent_desc)
1384                 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1385 
1386         return sent_desc;
1387 }
1388 
1389 /* Set TXQ descriptors fields relevant for CSUM calculation */
1390 static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
1391                                 int ip_hdr_len, int l4_proto)
1392 {
1393         u32 command;
1394 
1395         /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1396          * G_L4_chk, L4_type; required only for checksum
1397          * calculation
1398          */
1399         command =  l3_offs    << MVNETA_TX_L3_OFF_SHIFT;
1400         command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT;
1401 
1402         if (l3_proto == htons(ETH_P_IP))
1403                 command |= MVNETA_TXD_IP_CSUM;
1404         else
1405                 command |= MVNETA_TX_L3_IP6;
1406 
1407         if (l4_proto == IPPROTO_TCP)
1408                 command |=  MVNETA_TX_L4_CSUM_FULL;
1409         else if (l4_proto == IPPROTO_UDP)
1410                 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL;
1411         else
1412                 command |= MVNETA_TX_L4_CSUM_NOT;
1413 
1414         return command;
1415 }
1416 
1417 
1418 /* Display more error info */
1419 static void mvneta_rx_error(struct mvneta_port *pp,
1420                             struct mvneta_rx_desc *rx_desc)
1421 {
1422         u32 status = rx_desc->status;
1423 
1424         if (!mvneta_rxq_desc_is_first_last(status)) {
1425                 netdev_err(pp->dev,
1426                            "bad rx status %08x (buffer oversize), size=%d\n",
1427                            status, rx_desc->data_size);
1428                 return;
1429         }
1430 
1431         switch (status & MVNETA_RXD_ERR_CODE_MASK) {
1432         case MVNETA_RXD_ERR_CRC:
1433                 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
1434                            status, rx_desc->data_size);
1435                 break;
1436         case MVNETA_RXD_ERR_OVERRUN:
1437                 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
1438                            status, rx_desc->data_size);
1439                 break;
1440         case MVNETA_RXD_ERR_LEN:
1441                 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
1442                            status, rx_desc->data_size);
1443                 break;
1444         case MVNETA_RXD_ERR_RESOURCE:
1445                 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
1446                            status, rx_desc->data_size);
1447                 break;
1448         }
1449 }
1450 
1451 /* Handle RX checksum offload based on the descriptor's status */
1452 static void mvneta_rx_csum(struct mvneta_port *pp, u32 status,
1453                            struct sk_buff *skb)
1454 {
1455         if ((status & MVNETA_RXD_L3_IP4) &&
1456             (status & MVNETA_RXD_L4_CSUM_OK)) {
1457                 skb->csum = 0;
1458                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1459                 return;
1460         }
1461 
1462         skb->ip_summed = CHECKSUM_NONE;
1463 }
1464 
1465 /* Return tx queue pointer (find last set bit) according to <cause> returned
1466  * form tx_done reg. <cause> must not be null. The return value is always a
1467  * valid queue for matching the first one found in <cause>.
1468  */
1469 static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp,
1470                                                      u32 cause)
1471 {
1472         int queue = fls(cause) - 1;
1473 
1474         return &pp->txqs[queue];
1475 }
1476 
1477 /* Free tx queue skbuffs */
1478 static void mvneta_txq_bufs_free(struct mvneta_port *pp,
1479                                  struct mvneta_tx_queue *txq, int num)
1480 {
1481         int i;
1482 
1483         for (i = 0; i < num; i++) {
1484                 struct mvneta_tx_desc *tx_desc = txq->descs +
1485                         txq->txq_get_index;
1486                 struct sk_buff *skb = txq->tx_skb[txq->txq_get_index];
1487 
1488                 mvneta_txq_inc_get(txq);
1489 
1490                 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
1491                         dma_unmap_single(pp->dev->dev.parent,
1492                                          tx_desc->buf_phys_addr,
1493                                          tx_desc->data_size, DMA_TO_DEVICE);
1494                 if (!skb)
1495                         continue;
1496                 dev_kfree_skb_any(skb);
1497         }
1498 }
1499 
1500 /* Handle end of transmission */
1501 static void mvneta_txq_done(struct mvneta_port *pp,
1502                            struct mvneta_tx_queue *txq)
1503 {
1504         struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
1505         int tx_done;
1506 
1507         tx_done = mvneta_txq_sent_desc_proc(pp, txq);
1508         if (!tx_done)
1509                 return;
1510 
1511         mvneta_txq_bufs_free(pp, txq, tx_done);
1512 
1513         txq->count -= tx_done;
1514 
1515         if (netif_tx_queue_stopped(nq)) {
1516                 if (txq->count <= txq->tx_wake_threshold)
1517                         netif_tx_wake_queue(nq);
1518         }
1519 }
1520 
1521 static void *mvneta_frag_alloc(const struct mvneta_port *pp)
1522 {
1523         if (likely(pp->frag_size <= PAGE_SIZE))
1524                 return netdev_alloc_frag(pp->frag_size);
1525         else
1526                 return kmalloc(pp->frag_size, GFP_ATOMIC);
1527 }
1528 
1529 static void mvneta_frag_free(const struct mvneta_port *pp, void *data)
1530 {
1531         if (likely(pp->frag_size <= PAGE_SIZE))
1532                 skb_free_frag(data);
1533         else
1534                 kfree(data);
1535 }
1536 
1537 /* Refill processing */
1538 static int mvneta_rx_refill(struct mvneta_port *pp,
1539                             struct mvneta_rx_desc *rx_desc)
1540 
1541 {
1542         dma_addr_t phys_addr;
1543         void *data;
1544 
1545         data = mvneta_frag_alloc(pp);
1546         if (!data)
1547                 return -ENOMEM;
1548 
1549         phys_addr = dma_map_single(pp->dev->dev.parent, data,
1550                                    MVNETA_RX_BUF_SIZE(pp->pkt_size),
1551                                    DMA_FROM_DEVICE);
1552         if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) {
1553                 mvneta_frag_free(pp, data);
1554                 return -ENOMEM;
1555         }
1556 
1557         mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
1558         return 0;
1559 }
1560 
1561 /* Handle tx checksum */
1562 static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb)
1563 {
1564         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1565                 int ip_hdr_len = 0;
1566                 __be16 l3_proto = vlan_get_protocol(skb);
1567                 u8 l4_proto;
1568 
1569                 if (l3_proto == htons(ETH_P_IP)) {
1570                         struct iphdr *ip4h = ip_hdr(skb);
1571 
1572                         /* Calculate IPv4 checksum and L4 checksum */
1573                         ip_hdr_len = ip4h->ihl;
1574                         l4_proto = ip4h->protocol;
1575                 } else if (l3_proto == htons(ETH_P_IPV6)) {
1576                         struct ipv6hdr *ip6h = ipv6_hdr(skb);
1577 
1578                         /* Read l4_protocol from one of IPv6 extra headers */
1579                         if (skb_network_header_len(skb) > 0)
1580                                 ip_hdr_len = (skb_network_header_len(skb) >> 2);
1581                         l4_proto = ip6h->nexthdr;
1582                 } else
1583                         return MVNETA_TX_L4_CSUM_NOT;
1584 
1585                 return mvneta_txq_desc_csum(skb_network_offset(skb),
1586                                             l3_proto, ip_hdr_len, l4_proto);
1587         }
1588 
1589         return MVNETA_TX_L4_CSUM_NOT;
1590 }
1591 
1592 /* Drop packets received by the RXQ and free buffers */
1593 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
1594                                  struct mvneta_rx_queue *rxq)
1595 {
1596         int rx_done, i;
1597 
1598         rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1599         for (i = 0; i < rxq->size; i++) {
1600                 struct mvneta_rx_desc *rx_desc = rxq->descs + i;
1601                 void *data = (void *)rx_desc->buf_cookie;
1602 
1603                 dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
1604                                  MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
1605                 mvneta_frag_free(pp, data);
1606         }
1607 
1608         if (rx_done)
1609                 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1610 }
1611 
1612 /* Main rx processing */
1613 static int mvneta_rx(struct mvneta_port *pp, int rx_todo,
1614                      struct mvneta_rx_queue *rxq)
1615 {
1616         struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
1617         struct net_device *dev = pp->dev;
1618         int rx_done;
1619         u32 rcvd_pkts = 0;
1620         u32 rcvd_bytes = 0;
1621 
1622         /* Get number of received packets */
1623         rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1624 
1625         if (rx_todo > rx_done)
1626                 rx_todo = rx_done;
1627 
1628         rx_done = 0;
1629 
1630         /* Fairness NAPI loop */
1631         while (rx_done < rx_todo) {
1632                 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
1633                 struct sk_buff *skb;
1634                 unsigned char *data;
1635                 dma_addr_t phys_addr;
1636                 u32 rx_status;
1637                 int rx_bytes, err;
1638 
1639                 rx_done++;
1640                 rx_status = rx_desc->status;
1641                 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
1642                 data = (unsigned char *)rx_desc->buf_cookie;
1643                 phys_addr = rx_desc->buf_phys_addr;
1644 
1645                 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
1646                     (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1647                 err_drop_frame:
1648                         dev->stats.rx_errors++;
1649                         mvneta_rx_error(pp, rx_desc);
1650                         /* leave the descriptor untouched */
1651                         continue;
1652                 }
1653 
1654                 if (rx_bytes <= rx_copybreak) {
1655                         /* better copy a small frame and not unmap the DMA region */
1656                         skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
1657                         if (unlikely(!skb))
1658                                 goto err_drop_frame;
1659 
1660                         dma_sync_single_range_for_cpu(dev->dev.parent,
1661                                                       rx_desc->buf_phys_addr,
1662                                                       MVNETA_MH_SIZE + NET_SKB_PAD,
1663                                                       rx_bytes,
1664                                                       DMA_FROM_DEVICE);
1665                         memcpy(skb_put(skb, rx_bytes),
1666                                data + MVNETA_MH_SIZE + NET_SKB_PAD,
1667                                rx_bytes);
1668 
1669                         skb->protocol = eth_type_trans(skb, dev);
1670                         mvneta_rx_csum(pp, rx_status, skb);
1671                         napi_gro_receive(&port->napi, skb);
1672 
1673                         rcvd_pkts++;
1674                         rcvd_bytes += rx_bytes;
1675 
1676                         /* leave the descriptor and buffer untouched */
1677                         continue;
1678                 }
1679 
1680                 /* Refill processing */
1681                 err = mvneta_rx_refill(pp, rx_desc);
1682                 if (err) {
1683                         netdev_err(dev, "Linux processing - Can't refill\n");
1684                         rxq->missed++;
1685                         goto err_drop_frame;
1686                 }
1687 
1688                 skb = build_skb(data, pp->frag_size > PAGE_SIZE ? 0 : pp->frag_size);
1689 
1690                 /* After refill old buffer has to be unmapped regardless
1691                  * the skb is successfully built or not.
1692                  */
1693                 dma_unmap_single(dev->dev.parent, phys_addr,
1694                                  MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
1695 
1696                 if (!skb)
1697                         goto err_drop_frame;
1698 
1699                 rcvd_pkts++;
1700                 rcvd_bytes += rx_bytes;
1701 
1702                 /* Linux processing */
1703                 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
1704                 skb_put(skb, rx_bytes);
1705 
1706                 skb->protocol = eth_type_trans(skb, dev);
1707 
1708                 mvneta_rx_csum(pp, rx_status, skb);
1709 
1710                 napi_gro_receive(&port->napi, skb);
1711         }
1712 
1713         if (rcvd_pkts) {
1714                 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1715 
1716                 u64_stats_update_begin(&stats->syncp);
1717                 stats->rx_packets += rcvd_pkts;
1718                 stats->rx_bytes   += rcvd_bytes;
1719                 u64_stats_update_end(&stats->syncp);
1720         }
1721 
1722         /* Update rxq management counters */
1723         mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1724 
1725         return rx_done;
1726 }
1727 
1728 static inline void
1729 mvneta_tso_put_hdr(struct sk_buff *skb,
1730                    struct mvneta_port *pp, struct mvneta_tx_queue *txq)
1731 {
1732         struct mvneta_tx_desc *tx_desc;
1733         int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1734 
1735         txq->tx_skb[txq->txq_put_index] = NULL;
1736         tx_desc = mvneta_txq_next_desc_get(txq);
1737         tx_desc->data_size = hdr_len;
1738         tx_desc->command = mvneta_skb_tx_csum(pp, skb);
1739         tx_desc->command |= MVNETA_TXD_F_DESC;
1740         tx_desc->buf_phys_addr = txq->tso_hdrs_phys +
1741                                  txq->txq_put_index * TSO_HEADER_SIZE;
1742         mvneta_txq_inc_put(txq);
1743 }
1744 
1745 static inline int
1746 mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq,
1747                     struct sk_buff *skb, char *data, int size,
1748                     bool last_tcp, bool is_last)
1749 {
1750         struct mvneta_tx_desc *tx_desc;
1751 
1752         tx_desc = mvneta_txq_next_desc_get(txq);
1753         tx_desc->data_size = size;
1754         tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data,
1755                                                 size, DMA_TO_DEVICE);
1756         if (unlikely(dma_mapping_error(dev->dev.parent,
1757                      tx_desc->buf_phys_addr))) {
1758                 mvneta_txq_desc_put(txq);
1759                 return -ENOMEM;
1760         }
1761 
1762         tx_desc->command = 0;
1763         txq->tx_skb[txq->txq_put_index] = NULL;
1764 
1765         if (last_tcp) {
1766                 /* last descriptor in the TCP packet */
1767                 tx_desc->command = MVNETA_TXD_L_DESC;
1768 
1769                 /* last descriptor in SKB */
1770                 if (is_last)
1771                         txq->tx_skb[txq->txq_put_index] = skb;
1772         }
1773         mvneta_txq_inc_put(txq);
1774         return 0;
1775 }
1776 
1777 static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev,
1778                          struct mvneta_tx_queue *txq)
1779 {
1780         int total_len, data_left;
1781         int desc_count = 0;
1782         struct mvneta_port *pp = netdev_priv(dev);
1783         struct tso_t tso;
1784         int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1785         int i;
1786 
1787         /* Count needed descriptors */
1788         if ((txq->count + tso_count_descs(skb)) >= txq->size)
1789                 return 0;
1790 
1791         if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) {
1792                 pr_info("*** Is this even  possible???!?!?\n");
1793                 return 0;
1794         }
1795 
1796         /* Initialize the TSO handler, and prepare the first payload */
1797         tso_start(skb, &tso);
1798 
1799         total_len = skb->len - hdr_len;
1800         while (total_len > 0) {
1801                 char *hdr;
1802 
1803                 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
1804                 total_len -= data_left;
1805                 desc_count++;
1806 
1807                 /* prepare packet headers: MAC + IP + TCP */
1808                 hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE;
1809                 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
1810 
1811                 mvneta_tso_put_hdr(skb, pp, txq);
1812 
1813                 while (data_left > 0) {
1814                         int size;
1815                         desc_count++;
1816 
1817                         size = min_t(int, tso.size, data_left);
1818 
1819                         if (mvneta_tso_put_data(dev, txq, skb,
1820                                                  tso.data, size,
1821                                                  size == data_left,
1822                                                  total_len == 0))
1823                                 goto err_release;
1824                         data_left -= size;
1825 
1826                         tso_build_data(skb, &tso, size);
1827                 }
1828         }
1829 
1830         return desc_count;
1831 
1832 err_release:
1833         /* Release all used data descriptors; header descriptors must not
1834          * be DMA-unmapped.
1835          */
1836         for (i = desc_count - 1; i >= 0; i--) {
1837                 struct mvneta_tx_desc *tx_desc = txq->descs + i;
1838                 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
1839                         dma_unmap_single(pp->dev->dev.parent,
1840                                          tx_desc->buf_phys_addr,
1841                                          tx_desc->data_size,
1842                                          DMA_TO_DEVICE);
1843                 mvneta_txq_desc_put(txq);
1844         }
1845         return 0;
1846 }
1847 
1848 /* Handle tx fragmentation processing */
1849 static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb,
1850                                   struct mvneta_tx_queue *txq)
1851 {
1852         struct mvneta_tx_desc *tx_desc;
1853         int i, nr_frags = skb_shinfo(skb)->nr_frags;
1854 
1855         for (i = 0; i < nr_frags; i++) {
1856                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1857                 void *addr = page_address(frag->page.p) + frag->page_offset;
1858 
1859                 tx_desc = mvneta_txq_next_desc_get(txq);
1860                 tx_desc->data_size = frag->size;
1861 
1862                 tx_desc->buf_phys_addr =
1863                         dma_map_single(pp->dev->dev.parent, addr,
1864                                        tx_desc->data_size, DMA_TO_DEVICE);
1865 
1866                 if (dma_mapping_error(pp->dev->dev.parent,
1867                                       tx_desc->buf_phys_addr)) {
1868                         mvneta_txq_desc_put(txq);
1869                         goto error;
1870                 }
1871 
1872                 if (i == nr_frags - 1) {
1873                         /* Last descriptor */
1874                         tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
1875                         txq->tx_skb[txq->txq_put_index] = skb;
1876                 } else {
1877                         /* Descriptor in the middle: Not First, Not Last */
1878                         tx_desc->command = 0;
1879                         txq->tx_skb[txq->txq_put_index] = NULL;
1880                 }
1881                 mvneta_txq_inc_put(txq);
1882         }
1883 
1884         return 0;
1885 
1886 error:
1887         /* Release all descriptors that were used to map fragments of
1888          * this packet, as well as the corresponding DMA mappings
1889          */
1890         for (i = i - 1; i >= 0; i--) {
1891                 tx_desc = txq->descs + i;
1892                 dma_unmap_single(pp->dev->dev.parent,
1893                                  tx_desc->buf_phys_addr,
1894                                  tx_desc->data_size,
1895                                  DMA_TO_DEVICE);
1896                 mvneta_txq_desc_put(txq);
1897         }
1898 
1899         return -ENOMEM;
1900 }
1901 
1902 /* Main tx processing */
1903 static int mvneta_tx(struct sk_buff *skb, struct net_device *dev)
1904 {
1905         struct mvneta_port *pp = netdev_priv(dev);
1906         u16 txq_id = skb_get_queue_mapping(skb);
1907         struct mvneta_tx_queue *txq = &pp->txqs[txq_id];
1908         struct mvneta_tx_desc *tx_desc;
1909         int len = skb->len;
1910         int frags = 0;
1911         u32 tx_cmd;
1912 
1913         if (!netif_running(dev))
1914                 goto out;
1915 
1916         if (skb_is_gso(skb)) {
1917                 frags = mvneta_tx_tso(skb, dev, txq);
1918                 goto out;
1919         }
1920 
1921         frags = skb_shinfo(skb)->nr_frags + 1;
1922 
1923         /* Get a descriptor for the first part of the packet */
1924         tx_desc = mvneta_txq_next_desc_get(txq);
1925 
1926         tx_cmd = mvneta_skb_tx_csum(pp, skb);
1927 
1928         tx_desc->data_size = skb_headlen(skb);
1929 
1930         tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
1931                                                 tx_desc->data_size,
1932                                                 DMA_TO_DEVICE);
1933         if (unlikely(dma_mapping_error(dev->dev.parent,
1934                                        tx_desc->buf_phys_addr))) {
1935                 mvneta_txq_desc_put(txq);
1936                 frags = 0;
1937                 goto out;
1938         }
1939 
1940         if (frags == 1) {
1941                 /* First and Last descriptor */
1942                 tx_cmd |= MVNETA_TXD_FLZ_DESC;
1943                 tx_desc->command = tx_cmd;
1944                 txq->tx_skb[txq->txq_put_index] = skb;
1945                 mvneta_txq_inc_put(txq);
1946         } else {
1947                 /* First but not Last */
1948                 tx_cmd |= MVNETA_TXD_F_DESC;
1949                 txq->tx_skb[txq->txq_put_index] = NULL;
1950                 mvneta_txq_inc_put(txq);
1951                 tx_desc->command = tx_cmd;
1952                 /* Continue with other skb fragments */
1953                 if (mvneta_tx_frag_process(pp, skb, txq)) {
1954                         dma_unmap_single(dev->dev.parent,
1955                                          tx_desc->buf_phys_addr,
1956                                          tx_desc->data_size,
1957                                          DMA_TO_DEVICE);
1958                         mvneta_txq_desc_put(txq);
1959                         frags = 0;
1960                         goto out;
1961                 }
1962         }
1963 
1964 out:
1965         if (frags > 0) {
1966                 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1967                 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
1968 
1969                 txq->count += frags;
1970                 mvneta_txq_pend_desc_add(pp, txq, frags);
1971 
1972                 if (txq->count >= txq->tx_stop_threshold)
1973                         netif_tx_stop_queue(nq);
1974 
1975                 u64_stats_update_begin(&stats->syncp);
1976                 stats->tx_packets++;
1977                 stats->tx_bytes  += len;
1978                 u64_stats_update_end(&stats->syncp);
1979         } else {
1980                 dev->stats.tx_dropped++;
1981                 dev_kfree_skb_any(skb);
1982         }
1983 
1984         return NETDEV_TX_OK;
1985 }
1986 
1987 
1988 /* Free tx resources, when resetting a port */
1989 static void mvneta_txq_done_force(struct mvneta_port *pp,
1990                                   struct mvneta_tx_queue *txq)
1991 
1992 {
1993         int tx_done = txq->count;
1994 
1995         mvneta_txq_bufs_free(pp, txq, tx_done);
1996 
1997         /* reset txq */
1998         txq->count = 0;
1999         txq->txq_put_index = 0;
2000         txq->txq_get_index = 0;
2001 }
2002 
2003 /* Handle tx done - called in softirq context. The <cause_tx_done> argument
2004  * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL.
2005  */
2006 static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done)
2007 {
2008         struct mvneta_tx_queue *txq;
2009         struct netdev_queue *nq;
2010 
2011         while (cause_tx_done) {
2012                 txq = mvneta_tx_done_policy(pp, cause_tx_done);
2013 
2014                 nq = netdev_get_tx_queue(pp->dev, txq->id);
2015                 __netif_tx_lock(nq, smp_processor_id());
2016 
2017                 if (txq->count)
2018                         mvneta_txq_done(pp, txq);
2019 
2020                 __netif_tx_unlock(nq);
2021                 cause_tx_done &= ~((1 << txq->id));
2022         }
2023 }
2024 
2025 /* Compute crc8 of the specified address, using a unique algorithm ,
2026  * according to hw spec, different than generic crc8 algorithm
2027  */
2028 static int mvneta_addr_crc(unsigned char *addr)
2029 {
2030         int crc = 0;
2031         int i;
2032 
2033         for (i = 0; i < ETH_ALEN; i++) {
2034                 int j;
2035 
2036                 crc = (crc ^ addr[i]) << 8;
2037                 for (j = 7; j >= 0; j--) {
2038                         if (crc & (0x100 << j))
2039                                 crc ^= 0x107 << j;
2040                 }
2041         }
2042 
2043         return crc;
2044 }
2045 
2046 /* This method controls the net device special MAC multicast support.
2047  * The Special Multicast Table for MAC addresses supports MAC of the form
2048  * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2049  * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2050  * Table entries in the DA-Filter table. This method set the Special
2051  * Multicast Table appropriate entry.
2052  */
2053 static void mvneta_set_special_mcast_addr(struct mvneta_port *pp,
2054                                           unsigned char last_byte,
2055                                           int queue)
2056 {
2057         unsigned int smc_table_reg;
2058         unsigned int tbl_offset;
2059         unsigned int reg_offset;
2060 
2061         /* Register offset from SMC table base    */
2062         tbl_offset = (last_byte / 4);
2063         /* Entry offset within the above reg */
2064         reg_offset = last_byte % 4;
2065 
2066         smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
2067                                         + tbl_offset * 4));
2068 
2069         if (queue == -1)
2070                 smc_table_reg &= ~(0xff << (8 * reg_offset));
2071         else {
2072                 smc_table_reg &= ~(0xff << (8 * reg_offset));
2073                 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
2074         }
2075 
2076         mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
2077                     smc_table_reg);
2078 }
2079 
2080 /* This method controls the network device Other MAC multicast support.
2081  * The Other Multicast Table is used for multicast of another type.
2082  * A CRC-8 is used as an index to the Other Multicast Table entries
2083  * in the DA-Filter table.
2084  * The method gets the CRC-8 value from the calling routine and
2085  * sets the Other Multicast Table appropriate entry according to the
2086  * specified CRC-8 .
2087  */
2088 static void mvneta_set_other_mcast_addr(struct mvneta_port *pp,
2089                                         unsigned char crc8,
2090                                         int queue)
2091 {
2092         unsigned int omc_table_reg;
2093         unsigned int tbl_offset;
2094         unsigned int reg_offset;
2095 
2096         tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
2097         reg_offset = crc8 % 4;       /* Entry offset within the above reg   */
2098 
2099         omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
2100 
2101         if (queue == -1) {
2102                 /* Clear accepts frame bit at specified Other DA table entry */
2103                 omc_table_reg &= ~(0xff << (8 * reg_offset));
2104         } else {
2105                 omc_table_reg &= ~(0xff << (8 * reg_offset));
2106                 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
2107         }
2108 
2109         mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
2110 }
2111 
2112 /* The network device supports multicast using two tables:
2113  *    1) Special Multicast Table for MAC addresses of the form
2114  *       0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2115  *       The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2116  *       Table entries in the DA-Filter table.
2117  *    2) Other Multicast Table for multicast of another type. A CRC-8 value
2118  *       is used as an index to the Other Multicast Table entries in the
2119  *       DA-Filter table.
2120  */
2121 static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr,
2122                                  int queue)
2123 {
2124         unsigned char crc_result = 0;
2125 
2126         if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) {
2127                 mvneta_set_special_mcast_addr(pp, p_addr[5], queue);
2128                 return 0;
2129         }
2130 
2131         crc_result = mvneta_addr_crc(p_addr);
2132         if (queue == -1) {
2133                 if (pp->mcast_count[crc_result] == 0) {
2134                         netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n",
2135                                     crc_result);
2136                         return -EINVAL;
2137                 }
2138 
2139                 pp->mcast_count[crc_result]--;
2140                 if (pp->mcast_count[crc_result] != 0) {
2141                         netdev_info(pp->dev,
2142                                     "After delete there are %d valid Mcast for crc8=0x%02x\n",
2143                                     pp->mcast_count[crc_result], crc_result);
2144                         return -EINVAL;
2145                 }
2146         } else
2147                 pp->mcast_count[crc_result]++;
2148 
2149         mvneta_set_other_mcast_addr(pp, crc_result, queue);
2150 
2151         return 0;
2152 }
2153 
2154 /* Configure Fitering mode of Ethernet port */
2155 static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp,
2156                                           int is_promisc)
2157 {
2158         u32 port_cfg_reg, val;
2159 
2160         port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
2161 
2162         val = mvreg_read(pp, MVNETA_TYPE_PRIO);
2163 
2164         /* Set / Clear UPM bit in port configuration register */
2165         if (is_promisc) {
2166                 /* Accept all Unicast addresses */
2167                 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE;
2168                 val |= MVNETA_FORCE_UNI;
2169                 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
2170                 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
2171         } else {
2172                 /* Reject all Unicast addresses */
2173                 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE;
2174                 val &= ~MVNETA_FORCE_UNI;
2175         }
2176 
2177         mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
2178         mvreg_write(pp, MVNETA_TYPE_PRIO, val);
2179 }
2180 
2181 /* register unicast and multicast addresses */
2182 static void mvneta_set_rx_mode(struct net_device *dev)
2183 {
2184         struct mvneta_port *pp = netdev_priv(dev);
2185         struct netdev_hw_addr *ha;
2186 
2187         if (dev->flags & IFF_PROMISC) {
2188                 /* Accept all: Multicast + Unicast */
2189                 mvneta_rx_unicast_promisc_set(pp, 1);
2190                 mvneta_set_ucast_table(pp, pp->rxq_def);
2191                 mvneta_set_special_mcast_table(pp, pp->rxq_def);
2192                 mvneta_set_other_mcast_table(pp, pp->rxq_def);
2193         } else {
2194                 /* Accept single Unicast */
2195                 mvneta_rx_unicast_promisc_set(pp, 0);
2196                 mvneta_set_ucast_table(pp, -1);
2197                 mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def);
2198 
2199                 if (dev->flags & IFF_ALLMULTI) {
2200                         /* Accept all multicast */
2201                         mvneta_set_special_mcast_table(pp, pp->rxq_def);
2202                         mvneta_set_other_mcast_table(pp, pp->rxq_def);
2203                 } else {
2204                         /* Accept only initialized multicast */
2205                         mvneta_set_special_mcast_table(pp, -1);
2206                         mvneta_set_other_mcast_table(pp, -1);
2207 
2208                         if (!netdev_mc_empty(dev)) {
2209                                 netdev_for_each_mc_addr(ha, dev) {
2210                                         mvneta_mcast_addr_set(pp, ha->addr,
2211                                                               pp->rxq_def);
2212                                 }
2213                         }
2214                 }
2215         }
2216 }
2217 
2218 /* Interrupt handling - the callback for request_irq() */
2219 static irqreturn_t mvneta_isr(int irq, void *dev_id)
2220 {
2221         struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id;
2222 
2223         disable_percpu_irq(port->pp->dev->irq);
2224         napi_schedule(&port->napi);
2225 
2226         return IRQ_HANDLED;
2227 }
2228 
2229 static int mvneta_fixed_link_update(struct mvneta_port *pp,
2230                                     struct phy_device *phy)
2231 {
2232         struct fixed_phy_status status;
2233         struct fixed_phy_status changed = {};
2234         u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
2235 
2236         status.link = !!(gmac_stat & MVNETA_GMAC_LINK_UP);
2237         if (gmac_stat & MVNETA_GMAC_SPEED_1000)
2238                 status.speed = SPEED_1000;
2239         else if (gmac_stat & MVNETA_GMAC_SPEED_100)
2240                 status.speed = SPEED_100;
2241         else
2242                 status.speed = SPEED_10;
2243         status.duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX);
2244         changed.link = 1;
2245         changed.speed = 1;
2246         changed.duplex = 1;
2247         fixed_phy_update_state(phy, &status, &changed);
2248         return 0;
2249 }
2250 
2251 /* NAPI handler
2252  * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
2253  * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
2254  * Bits 8 -15 of the cause Rx Tx register indicate that are received
2255  * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
2256  * Each CPU has its own causeRxTx register
2257  */
2258 static int mvneta_poll(struct napi_struct *napi, int budget)
2259 {
2260         int rx_done = 0;
2261         u32 cause_rx_tx;
2262         int rx_queue;
2263         struct mvneta_port *pp = netdev_priv(napi->dev);
2264         struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
2265 
2266         if (!netif_running(pp->dev)) {
2267                 napi_complete(&port->napi);
2268                 return rx_done;
2269         }
2270 
2271         /* Read cause register */
2272         cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE);
2273         if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) {
2274                 u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE);
2275 
2276                 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
2277                 if (pp->use_inband_status && (cause_misc &
2278                                 (MVNETA_CAUSE_PHY_STATUS_CHANGE |
2279                                  MVNETA_CAUSE_LINK_CHANGE |
2280                                  MVNETA_CAUSE_PSC_SYNC_CHANGE))) {
2281                         mvneta_fixed_link_update(pp, pp->phy_dev);
2282                 }
2283         }
2284 
2285         /* Release Tx descriptors */
2286         if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) {
2287                 mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL));
2288                 cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL;
2289         }
2290 
2291         /* For the case where the last mvneta_poll did not process all
2292          * RX packets
2293          */
2294         rx_queue = fls(((cause_rx_tx >> 8) & 0xff));
2295 
2296         cause_rx_tx |= port->cause_rx_tx;
2297 
2298         if (rx_queue) {
2299                 rx_queue = rx_queue - 1;
2300                 rx_done = mvneta_rx(pp, budget, &pp->rxqs[rx_queue]);
2301         }
2302 
2303         budget -= rx_done;
2304 
2305         if (budget > 0) {
2306                 cause_rx_tx = 0;
2307                 napi_complete(&port->napi);
2308                 enable_percpu_irq(pp->dev->irq, 0);
2309         }
2310 
2311         port->cause_rx_tx = cause_rx_tx;
2312         return rx_done;
2313 }
2314 
2315 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
2316 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
2317                            int num)
2318 {
2319         int i;
2320 
2321         for (i = 0; i < num; i++) {
2322                 memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc));
2323                 if (mvneta_rx_refill(pp, rxq->descs + i) != 0) {
2324                         netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs  filled\n",
2325                                 __func__, rxq->id, i, num);
2326                         break;
2327                 }
2328         }
2329 
2330         /* Add this number of RX descriptors as non occupied (ready to
2331          * get packets)
2332          */
2333         mvneta_rxq_non_occup_desc_add(pp, rxq, i);
2334 
2335         return i;
2336 }
2337 
2338 /* Free all packets pending transmit from all TXQs and reset TX port */
2339 static void mvneta_tx_reset(struct mvneta_port *pp)
2340 {
2341         int queue;
2342 
2343         /* free the skb's in the tx ring */
2344         for (queue = 0; queue < txq_number; queue++)
2345                 mvneta_txq_done_force(pp, &pp->txqs[queue]);
2346 
2347         mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
2348         mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
2349 }
2350 
2351 static void mvneta_rx_reset(struct mvneta_port *pp)
2352 {
2353         mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
2354         mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
2355 }
2356 
2357 /* Rx/Tx queue initialization/cleanup methods */
2358 
2359 /* Create a specified RX queue */
2360 static int mvneta_rxq_init(struct mvneta_port *pp,
2361                            struct mvneta_rx_queue *rxq)
2362 
2363 {
2364         rxq->size = pp->rx_ring_size;
2365 
2366         /* Allocate memory for RX descriptors */
2367         rxq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2368                                         rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2369                                         &rxq->descs_phys, GFP_KERNEL);
2370         if (rxq->descs == NULL)
2371                 return -ENOMEM;
2372 
2373         BUG_ON(rxq->descs !=
2374                PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
2375 
2376         rxq->last_desc = rxq->size - 1;
2377 
2378         /* Set Rx descriptors queue starting address */
2379         mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
2380         mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
2381 
2382         /* Set Offset */
2383         mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD);
2384 
2385         /* Set coalescing pkts and time */
2386         mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2387         mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2388 
2389         /* Fill RXQ with buffers from RX pool */
2390         mvneta_rxq_buf_size_set(pp, rxq, MVNETA_RX_BUF_SIZE(pp->pkt_size));
2391         mvneta_rxq_bm_disable(pp, rxq);
2392         mvneta_rxq_fill(pp, rxq, rxq->size);
2393 
2394         return 0;
2395 }
2396 
2397 /* Cleanup Rx queue */
2398 static void mvneta_rxq_deinit(struct mvneta_port *pp,
2399                               struct mvneta_rx_queue *rxq)
2400 {
2401         mvneta_rxq_drop_pkts(pp, rxq);
2402 
2403         if (rxq->descs)
2404                 dma_free_coherent(pp->dev->dev.parent,
2405                                   rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2406                                   rxq->descs,
2407                                   rxq->descs_phys);
2408 
2409         rxq->descs             = NULL;
2410         rxq->last_desc         = 0;
2411         rxq->next_desc_to_proc = 0;
2412         rxq->descs_phys        = 0;
2413 }
2414 
2415 /* Create and initialize a tx queue */
2416 static int mvneta_txq_init(struct mvneta_port *pp,
2417                            struct mvneta_tx_queue *txq)
2418 {
2419         int cpu;
2420 
2421         txq->size = pp->tx_ring_size;
2422 
2423         /* A queue must always have room for at least one skb.
2424          * Therefore, stop the queue when the free entries reaches
2425          * the maximum number of descriptors per skb.
2426          */
2427         txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS;
2428         txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
2429 
2430 
2431         /* Allocate memory for TX descriptors */
2432         txq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2433                                         txq->size * MVNETA_DESC_ALIGNED_SIZE,
2434                                         &txq->descs_phys, GFP_KERNEL);
2435         if (txq->descs == NULL)
2436                 return -ENOMEM;
2437 
2438         /* Make sure descriptor address is cache line size aligned  */
2439         BUG_ON(txq->descs !=
2440                PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
2441 
2442         txq->last_desc = txq->size - 1;
2443 
2444         /* Set maximum bandwidth for enabled TXQs */
2445         mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
2446         mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
2447 
2448         /* Set Tx descriptors queue starting address */
2449         mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
2450         mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
2451 
2452         txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL);
2453         if (txq->tx_skb == NULL) {
2454                 dma_free_coherent(pp->dev->dev.parent,
2455                                   txq->size * MVNETA_DESC_ALIGNED_SIZE,
2456                                   txq->descs, txq->descs_phys);
2457                 return -ENOMEM;
2458         }
2459 
2460         /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2461         txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent,
2462                                            txq->size * TSO_HEADER_SIZE,
2463                                            &txq->tso_hdrs_phys, GFP_KERNEL);
2464         if (txq->tso_hdrs == NULL) {
2465                 kfree(txq->tx_skb);
2466                 dma_free_coherent(pp->dev->dev.parent,
2467                                   txq->size * MVNETA_DESC_ALIGNED_SIZE,
2468                                   txq->descs, txq->descs_phys);
2469                 return -ENOMEM;
2470         }
2471         mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2472 
2473         /* Setup XPS mapping */
2474         if (txq_number > 1)
2475                 cpu = txq->id % num_present_cpus();
2476         else
2477                 cpu = pp->rxq_def % num_present_cpus();
2478         cpumask_set_cpu(cpu, &txq->affinity_mask);
2479         netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id);
2480 
2481         return 0;
2482 }
2483 
2484 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
2485 static void mvneta_txq_deinit(struct mvneta_port *pp,
2486                               struct mvneta_tx_queue *txq)
2487 {
2488         kfree(txq->tx_skb);
2489 
2490         if (txq->tso_hdrs)
2491                 dma_free_coherent(pp->dev->dev.parent,
2492                                   txq->size * TSO_HEADER_SIZE,
2493                                   txq->tso_hdrs, txq->tso_hdrs_phys);
2494         if (txq->descs)
2495                 dma_free_coherent(pp->dev->dev.parent,
2496                                   txq->size * MVNETA_DESC_ALIGNED_SIZE,
2497                                   txq->descs, txq->descs_phys);
2498 
2499         txq->descs             = NULL;
2500         txq->last_desc         = 0;
2501         txq->next_desc_to_proc = 0;
2502         txq->descs_phys        = 0;
2503 
2504         /* Set minimum bandwidth for disabled TXQs */
2505         mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
2506         mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
2507 
2508         /* Set Tx descriptors queue starting address and size */
2509         mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
2510         mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
2511 }
2512 
2513 /* Cleanup all Tx queues */
2514 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
2515 {
2516         int queue;
2517 
2518         for (queue = 0; queue < txq_number; queue++)
2519                 mvneta_txq_deinit(pp, &pp->txqs[queue]);
2520 }
2521 
2522 /* Cleanup all Rx queues */
2523 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
2524 {
2525         int queue;
2526 
2527         for (queue = 0; queue < txq_number; queue++)
2528                 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
2529 }
2530 
2531 
2532 /* Init all Rx queues */
2533 static int mvneta_setup_rxqs(struct mvneta_port *pp)
2534 {
2535         int queue;
2536 
2537         for (queue = 0; queue < rxq_number; queue++) {
2538                 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
2539 
2540                 if (err) {
2541                         netdev_err(pp->dev, "%s: can't create rxq=%d\n",
2542                                    __func__, queue);
2543                         mvneta_cleanup_rxqs(pp);
2544                         return err;
2545                 }
2546         }
2547 
2548         return 0;
2549 }
2550 
2551 /* Init all tx queues */
2552 static int mvneta_setup_txqs(struct mvneta_port *pp)
2553 {
2554         int queue;
2555 
2556         for (queue = 0; queue < txq_number; queue++) {
2557                 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
2558                 if (err) {
2559                         netdev_err(pp->dev, "%s: can't create txq=%d\n",
2560                                    __func__, queue);
2561                         mvneta_cleanup_txqs(pp);
2562                         return err;
2563                 }
2564         }
2565 
2566         return 0;
2567 }
2568 
2569 static void mvneta_start_dev(struct mvneta_port *pp)
2570 {
2571         int cpu;
2572 
2573         mvneta_max_rx_size_set(pp, pp->pkt_size);
2574         mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
2575 
2576         /* start the Rx/Tx activity */
2577         mvneta_port_enable(pp);
2578 
2579         /* Enable polling on the port */
2580         for_each_online_cpu(cpu) {
2581                 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
2582 
2583                 napi_enable(&port->napi);
2584         }
2585 
2586         /* Unmask interrupts. It has to be done from each CPU */
2587         on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
2588 
2589         mvreg_write(pp, MVNETA_INTR_MISC_MASK,
2590                     MVNETA_CAUSE_PHY_STATUS_CHANGE |
2591                     MVNETA_CAUSE_LINK_CHANGE |
2592                     MVNETA_CAUSE_PSC_SYNC_CHANGE);
2593 
2594         phy_start(pp->phy_dev);
2595         netif_tx_start_all_queues(pp->dev);
2596 }
2597 
2598 static void mvneta_stop_dev(struct mvneta_port *pp)
2599 {
2600         unsigned int cpu;
2601 
2602         phy_stop(pp->phy_dev);
2603 
2604         for_each_online_cpu(cpu) {
2605                 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
2606 
2607                 napi_disable(&port->napi);
2608         }
2609 
2610         netif_carrier_off(pp->dev);
2611 
2612         mvneta_port_down(pp);
2613         netif_tx_stop_all_queues(pp->dev);
2614 
2615         /* Stop the port activity */
2616         mvneta_port_disable(pp);
2617 
2618         /* Clear all ethernet port interrupts */
2619         on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
2620 
2621         /* Mask all ethernet port interrupts */
2622         on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
2623 
2624         mvneta_tx_reset(pp);
2625         mvneta_rx_reset(pp);
2626 }
2627 
2628 /* Return positive if MTU is valid */
2629 static int mvneta_check_mtu_valid(struct net_device *dev, int mtu)
2630 {
2631         if (mtu < 68) {
2632                 netdev_err(dev, "cannot change mtu to less than 68\n");
2633                 return -EINVAL;
2634         }
2635 
2636         /* 9676 == 9700 - 20 and rounding to 8 */
2637         if (mtu > 9676) {
2638                 netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu);
2639                 mtu = 9676;
2640         }
2641 
2642         if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
2643                 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n",
2644                         mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8));
2645                 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8);
2646         }
2647 
2648         return mtu;
2649 }
2650 
2651 /* Change the device mtu */
2652 static int mvneta_change_mtu(struct net_device *dev, int mtu)
2653 {
2654         struct mvneta_port *pp = netdev_priv(dev);
2655         int ret;
2656 
2657         mtu = mvneta_check_mtu_valid(dev, mtu);
2658         if (mtu < 0)
2659                 return -EINVAL;
2660 
2661         dev->mtu = mtu;
2662 
2663         if (!netif_running(dev)) {
2664                 netdev_update_features(dev);
2665                 return 0;
2666         }
2667 
2668         /* The interface is running, so we have to force a
2669          * reallocation of the queues
2670          */
2671         mvneta_stop_dev(pp);
2672 
2673         mvneta_cleanup_txqs(pp);
2674         mvneta_cleanup_rxqs(pp);
2675 
2676         pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu);
2677         pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
2678                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2679 
2680         ret = mvneta_setup_rxqs(pp);
2681         if (ret) {
2682                 netdev_err(dev, "unable to setup rxqs after MTU change\n");
2683                 return ret;
2684         }
2685 
2686         ret = mvneta_setup_txqs(pp);
2687         if (ret) {
2688                 netdev_err(dev, "unable to setup txqs after MTU change\n");
2689                 return ret;
2690         }
2691 
2692         mvneta_start_dev(pp);
2693         mvneta_port_up(pp);
2694 
2695         netdev_update_features(dev);
2696 
2697         return 0;
2698 }
2699 
2700 static netdev_features_t mvneta_fix_features(struct net_device *dev,
2701                                              netdev_features_t features)
2702 {
2703         struct mvneta_port *pp = netdev_priv(dev);
2704 
2705         if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) {
2706                 features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO);
2707                 netdev_info(dev,
2708                             "Disable IP checksum for MTU greater than %dB\n",
2709                             pp->tx_csum_limit);
2710         }
2711 
2712         return features;
2713 }
2714 
2715 /* Get mac address */
2716 static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr)
2717 {
2718         u32 mac_addr_l, mac_addr_h;
2719 
2720         mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
2721         mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
2722         addr[0] = (mac_addr_h >> 24) & 0xFF;
2723         addr[1] = (mac_addr_h >> 16) & 0xFF;
2724         addr[2] = (mac_addr_h >> 8) & 0xFF;
2725         addr[3] = mac_addr_h & 0xFF;
2726         addr[4] = (mac_addr_l >> 8) & 0xFF;
2727         addr[5] = mac_addr_l & 0xFF;
2728 }
2729 
2730 /* Handle setting mac address */
2731 static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
2732 {
2733         struct mvneta_port *pp = netdev_priv(dev);
2734         struct sockaddr *sockaddr = addr;
2735         int ret;
2736 
2737         ret = eth_prepare_mac_addr_change(dev, addr);
2738         if (ret < 0)
2739                 return ret;
2740         /* Remove previous address table entry */
2741         mvneta_mac_addr_set(pp, dev->dev_addr, -1);
2742 
2743         /* Set new addr in hw */
2744         mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def);
2745 
2746         eth_commit_mac_addr_change(dev, addr);
2747         return 0;
2748 }
2749 
2750 static void mvneta_adjust_link(struct net_device *ndev)
2751 {
2752         struct mvneta_port *pp = netdev_priv(ndev);
2753         struct phy_device *phydev = pp->phy_dev;
2754         int status_change = 0;
2755 
2756         if (phydev->link) {
2757                 if ((pp->speed != phydev->speed) ||
2758                     (pp->duplex != phydev->duplex)) {
2759                         u32 val;
2760 
2761                         val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
2762                         val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
2763                                  MVNETA_GMAC_CONFIG_GMII_SPEED |
2764                                  MVNETA_GMAC_CONFIG_FULL_DUPLEX);
2765 
2766                         if (phydev->duplex)
2767                                 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
2768 
2769                         if (phydev->speed == SPEED_1000)
2770                                 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
2771                         else if (phydev->speed == SPEED_100)
2772                                 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
2773 
2774                         mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
2775 
2776                         pp->duplex = phydev->duplex;
2777                         pp->speed  = phydev->speed;
2778                 }
2779         }
2780 
2781         if (phydev->link != pp->link) {
2782                 if (!phydev->link) {
2783                         pp->duplex = -1;
2784                         pp->speed = 0;
2785                 }
2786 
2787                 pp->link = phydev->link;
2788                 status_change = 1;
2789         }
2790 
2791         if (status_change) {
2792                 if (phydev->link) {
2793                         if (!pp->use_inband_status) {
2794                                 u32 val = mvreg_read(pp,
2795                                                   MVNETA_GMAC_AUTONEG_CONFIG);
2796                                 val &= ~MVNETA_GMAC_FORCE_LINK_DOWN;
2797                                 val |= MVNETA_GMAC_FORCE_LINK_PASS;
2798                                 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
2799                                             val);
2800                         }
2801                         mvneta_port_up(pp);
2802                 } else {
2803                         if (!pp->use_inband_status) {
2804                                 u32 val = mvreg_read(pp,
2805                                                   MVNETA_GMAC_AUTONEG_CONFIG);
2806                                 val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
2807                                 val |= MVNETA_GMAC_FORCE_LINK_DOWN;
2808                                 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
2809                                             val);
2810                         }
2811                         mvneta_port_down(pp);
2812                 }
2813                 phy_print_status(phydev);
2814         }
2815 }
2816 
2817 static int mvneta_mdio_probe(struct mvneta_port *pp)
2818 {
2819         struct phy_device *phy_dev;
2820 
2821         phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0,
2822                                  pp->phy_interface);
2823         if (!phy_dev) {
2824                 netdev_err(pp->dev, "could not find the PHY\n");
2825                 return -ENODEV;
2826         }
2827 
2828         phy_dev->supported &= PHY_GBIT_FEATURES;
2829         phy_dev->advertising = phy_dev->supported;
2830 
2831         pp->phy_dev = phy_dev;
2832         pp->link    = 0;
2833         pp->duplex  = 0;
2834         pp->speed   = 0;
2835 
2836         return 0;
2837 }
2838 
2839 static void mvneta_mdio_remove(struct mvneta_port *pp)
2840 {
2841         phy_disconnect(pp->phy_dev);
2842         pp->phy_dev = NULL;
2843 }
2844 
2845 static void mvneta_percpu_enable(void *arg)
2846 {
2847         struct mvneta_port *pp = arg;
2848 
2849         enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE);
2850 }
2851 
2852 static void mvneta_percpu_disable(void *arg)
2853 {
2854         struct mvneta_port *pp = arg;
2855 
2856         disable_percpu_irq(pp->dev->irq);
2857 }
2858 
2859 /* Electing a CPU must be done in an atomic way: it should be done
2860  * after or before the removal/insertion of a CPU and this function is
2861  * not reentrant.
2862  */
2863 static void mvneta_percpu_elect(struct mvneta_port *pp)
2864 {
2865         int elected_cpu = 0, max_cpu, cpu, i = 0;
2866 
2867         /* Use the cpu associated to the rxq when it is online, in all
2868          * the other cases, use the cpu 0 which can't be offline.
2869          */
2870         if (cpu_online(pp->rxq_def))
2871                 elected_cpu = pp->rxq_def;
2872 
2873         max_cpu = num_present_cpus();
2874 
2875         for_each_online_cpu(cpu) {
2876                 int rxq_map = 0, txq_map = 0;
2877                 int rxq;
2878 
2879                 for (rxq = 0; rxq < rxq_number; rxq++)
2880                         if ((rxq % max_cpu) == cpu)
2881                                 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
2882 
2883                 if (cpu == elected_cpu)
2884                         /* Map the default receive queue queue to the
2885                          * elected CPU
2886                          */
2887                         rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def);
2888 
2889                 /* We update the TX queue map only if we have one
2890                  * queue. In this case we associate the TX queue to
2891                  * the CPU bound to the default RX queue
2892                  */
2893                 if (txq_number == 1)
2894                         txq_map = (cpu == elected_cpu) ?
2895                                 MVNETA_CPU_TXQ_ACCESS(1) : 0;
2896                 else
2897                         txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) &
2898                                 MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
2899 
2900                 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
2901 
2902                 /* Update the interrupt mask on each CPU according the
2903                  * new mapping
2904                  */
2905                 smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt,
2906                                          pp, true);
2907                 i++;
2908 
2909         }
2910 };
2911 
2912 static int mvneta_percpu_notifier(struct notifier_block *nfb,
2913                                   unsigned long action, void *hcpu)
2914 {
2915         struct mvneta_port *pp = container_of(nfb, struct mvneta_port,
2916                                               cpu_notifier);
2917         int cpu = (unsigned long)hcpu, other_cpu;
2918         struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
2919 
2920         switch (action) {
2921         case CPU_ONLINE:
2922         case CPU_ONLINE_FROZEN:
2923                 spin_lock(&pp->lock);
2924                 /* Configuring the driver for a new CPU while the
2925                  * driver is stopping is racy, so just avoid it.
2926                  */
2927                 if (pp->is_stopped) {
2928                         spin_unlock(&pp->lock);
2929                         break;
2930                 }
2931                 netif_tx_stop_all_queues(pp->dev);
2932 
2933                 /* We have to synchronise on tha napi of each CPU
2934                  * except the one just being waked up
2935                  */
2936                 for_each_online_cpu(other_cpu) {
2937                         if (other_cpu != cpu) {
2938                                 struct mvneta_pcpu_port *other_port =
2939                                         per_cpu_ptr(pp->ports, other_cpu);
2940 
2941                                 napi_synchronize(&other_port->napi);
2942                         }
2943                 }
2944 
2945                 /* Mask all ethernet port interrupts */
2946                 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
2947                 napi_enable(&port->napi);
2948 
2949 
2950                 /* Enable per-CPU interrupts on the CPU that is
2951                  * brought up.
2952                  */
2953                 smp_call_function_single(cpu, mvneta_percpu_enable,
2954                                          pp, true);
2955 
2956                 /* Enable per-CPU interrupt on the one CPU we care
2957                  * about.
2958                  */
2959                 mvneta_percpu_elect(pp);
2960 
2961                 /* Unmask all ethernet port interrupts */
2962                 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
2963                 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
2964                         MVNETA_CAUSE_PHY_STATUS_CHANGE |
2965                         MVNETA_CAUSE_LINK_CHANGE |
2966                         MVNETA_CAUSE_PSC_SYNC_CHANGE);
2967                 netif_tx_start_all_queues(pp->dev);
2968                 spin_unlock(&pp->lock);
2969                 break;
2970         case CPU_DOWN_PREPARE:
2971         case CPU_DOWN_PREPARE_FROZEN:
2972                 netif_tx_stop_all_queues(pp->dev);
2973                 /* Thanks to this lock we are sure that any pending
2974                  * cpu election is done
2975                  */
2976                 spin_lock(&pp->lock);
2977                 /* Mask all ethernet port interrupts */
2978                 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
2979                 spin_unlock(&pp->lock);
2980 
2981                 napi_synchronize(&port->napi);
2982                 napi_disable(&port->napi);
2983                 /* Disable per-CPU interrupts on the CPU that is
2984                  * brought down.
2985                  */
2986                 smp_call_function_single(cpu, mvneta_percpu_disable,
2987                                          pp, true);
2988 
2989                 break;
2990         case CPU_DEAD:
2991         case CPU_DEAD_FROZEN:
2992                 /* Check if a new CPU must be elected now this on is down */
2993                 spin_lock(&pp->lock);
2994                 mvneta_percpu_elect(pp);
2995                 spin_unlock(&pp->lock);
2996                 /* Unmask all ethernet port interrupts */
2997                 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
2998                 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
2999                         MVNETA_CAUSE_PHY_STATUS_CHANGE |
3000                         MVNETA_CAUSE_LINK_CHANGE |
3001                         MVNETA_CAUSE_PSC_SYNC_CHANGE);
3002                 netif_tx_start_all_queues(pp->dev);
3003                 break;
3004         }
3005 
3006         return NOTIFY_OK;
3007 }
3008 
3009 static int mvneta_open(struct net_device *dev)
3010 {
3011         struct mvneta_port *pp = netdev_priv(dev);
3012         int ret;
3013 
3014         pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
3015         pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
3016                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3017 
3018         ret = mvneta_setup_rxqs(pp);
3019         if (ret)
3020                 return ret;
3021 
3022         ret = mvneta_setup_txqs(pp);
3023         if (ret)
3024                 goto err_cleanup_rxqs;
3025 
3026         /* Connect to port interrupt line */
3027         ret = request_percpu_irq(pp->dev->irq, mvneta_isr,
3028                                  MVNETA_DRIVER_NAME, pp->ports);
3029         if (ret) {
3030                 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq);
3031                 goto err_cleanup_txqs;
3032         }
3033 
3034         /* Enable per-CPU interrupt on all the CPU to handle our RX
3035          * queue interrupts
3036          */
3037         on_each_cpu(mvneta_percpu_enable, pp, true);
3038 
3039         pp->is_stopped = false;
3040         /* Register a CPU notifier to handle the case where our CPU
3041          * might be taken offline.
3042          */
3043         register_cpu_notifier(&pp->cpu_notifier);
3044 
3045         /* In default link is down */
3046         netif_carrier_off(pp->dev);
3047 
3048         ret = mvneta_mdio_probe(pp);
3049         if (ret < 0) {
3050                 netdev_err(dev, "cannot probe MDIO bus\n");
3051                 goto err_free_irq;
3052         }
3053 
3054         mvneta_start_dev(pp);
3055 
3056         return 0;
3057 
3058 err_free_irq:
3059         free_percpu_irq(pp->dev->irq, pp->ports);
3060 err_cleanup_txqs:
3061         mvneta_cleanup_txqs(pp);
3062 err_cleanup_rxqs:
3063         mvneta_cleanup_rxqs(pp);
3064         return ret;
3065 }
3066 
3067 /* Stop the port, free port interrupt line */
3068 static int mvneta_stop(struct net_device *dev)
3069 {
3070         struct mvneta_port *pp = netdev_priv(dev);
3071 
3072         /* Inform that we are stopping so we don't want to setup the
3073          * driver for new CPUs in the notifiers
3074          */
3075         spin_lock(&pp->lock);
3076         pp->is_stopped = true;
3077         mvneta_stop_dev(pp);
3078         mvneta_mdio_remove(pp);
3079         unregister_cpu_notifier(&pp->cpu_notifier);
3080         /* Now that the notifier are unregistered, we can release le
3081          * lock
3082          */
3083         spin_unlock(&pp->lock);
3084         on_each_cpu(mvneta_percpu_disable, pp, true);
3085         free_percpu_irq(dev->irq, pp->ports);
3086         mvneta_cleanup_rxqs(pp);
3087         mvneta_cleanup_txqs(pp);
3088 
3089         return 0;
3090 }
3091 
3092 static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3093 {
3094         struct mvneta_port *pp = netdev_priv(dev);
3095 
3096         if (!pp->phy_dev)
3097                 return -ENOTSUPP;
3098 
3099         return phy_mii_ioctl(pp->phy_dev, ifr, cmd);
3100 }
3101 
3102 /* Ethtool methods */
3103 
3104 /* Get settings (phy address, speed) for ethtools */
3105 int mvneta_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3106 {
3107         struct mvneta_port *pp = netdev_priv(dev);
3108 
3109         if (!pp->phy_dev)
3110                 return -ENODEV;
3111 
3112         return phy_ethtool_gset(pp->phy_dev, cmd);
3113 }
3114 
3115 /* Set settings (phy address, speed) for ethtools */
3116 int mvneta_ethtool_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3117 {
3118         struct mvneta_port *pp = netdev_priv(dev);
3119         struct phy_device *phydev = pp->phy_dev;
3120 
3121         if (!phydev)
3122                 return -ENODEV;
3123 
3124         if ((cmd->autoneg == AUTONEG_ENABLE) != pp->use_inband_status) {
3125                 u32 val;
3126 
3127                 mvneta_set_autoneg(pp, cmd->autoneg == AUTONEG_ENABLE);
3128 
3129                 if (cmd->autoneg == AUTONEG_DISABLE) {
3130                         val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3131                         val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
3132                                  MVNETA_GMAC_CONFIG_GMII_SPEED |
3133                                  MVNETA_GMAC_CONFIG_FULL_DUPLEX);
3134 
3135                         if (phydev->duplex)
3136                                 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
3137 
3138                         if (phydev->speed == SPEED_1000)
3139                                 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
3140                         else if (phydev->speed == SPEED_100)
3141                                 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
3142 
3143                         mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
3144                 }
3145 
3146                 pp->use_inband_status = (cmd->autoneg == AUTONEG_ENABLE);
3147                 netdev_info(pp->dev, "autoneg status set to %i\n",
3148                             pp->use_inband_status);
3149 
3150                 if (netif_running(dev)) {
3151                         mvneta_port_down(pp);
3152                         mvneta_port_up(pp);
3153                 }
3154         }
3155 
3156         return phy_ethtool_sset(pp->phy_dev, cmd);
3157 }
3158 
3159 /* Set interrupt coalescing for ethtools */
3160 static int mvneta_ethtool_set_coalesce(struct net_device *dev,
3161                                        struct ethtool_coalesce *c)
3162 {
3163         struct mvneta_port *pp = netdev_priv(dev);
3164         int queue;
3165 
3166         for (queue = 0; queue < rxq_number; queue++) {
3167                 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
3168                 rxq->time_coal = c->rx_coalesce_usecs;
3169                 rxq->pkts_coal = c->rx_max_coalesced_frames;
3170                 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
3171                 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
3172         }
3173 
3174         for (queue = 0; queue < txq_number; queue++) {
3175                 struct mvneta_tx_queue *txq = &pp->txqs[queue];
3176                 txq->done_pkts_coal = c->tx_max_coalesced_frames;
3177                 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
3178         }
3179 
3180         return 0;
3181 }
3182 
3183 /* get coalescing for ethtools */
3184 static int mvneta_ethtool_get_coalesce(struct net_device *dev,
3185                                        struct ethtool_coalesce *c)
3186 {
3187         struct mvneta_port *pp = netdev_priv(dev);
3188 
3189         c->rx_coalesce_usecs        = pp->rxqs[0].time_coal;
3190         c->rx_max_coalesced_frames  = pp->rxqs[0].pkts_coal;
3191 
3192         c->tx_max_coalesced_frames =  pp->txqs[0].done_pkts_coal;
3193         return 0;
3194 }
3195 
3196 
3197 static void mvneta_ethtool_get_drvinfo(struct net_device *dev,
3198                                     struct ethtool_drvinfo *drvinfo)
3199 {
3200         strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME,
3201                 sizeof(drvinfo->driver));
3202         strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION,
3203                 sizeof(drvinfo->version));
3204         strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
3205                 sizeof(drvinfo->bus_info));
3206 }
3207 
3208 
3209 static void mvneta_ethtool_get_ringparam(struct net_device *netdev,
3210                                          struct ethtool_ringparam *ring)
3211 {
3212         struct mvneta_port *pp = netdev_priv(netdev);
3213 
3214         ring->rx_max_pending = MVNETA_MAX_RXD;
3215         ring->tx_max_pending = MVNETA_MAX_TXD;
3216         ring->rx_pending = pp->rx_ring_size;
3217         ring->tx_pending = pp->tx_ring_size;
3218 }
3219 
3220 static int mvneta_ethtool_set_ringparam(struct net_device *dev,
3221                                         struct ethtool_ringparam *ring)
3222 {
3223         struct mvneta_port *pp = netdev_priv(dev);
3224 
3225         if ((ring->rx_pending == 0) || (ring->tx_pending == 0))
3226                 return -EINVAL;
3227         pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ?
3228                 ring->rx_pending : MVNETA_MAX_RXD;
3229 
3230         pp->tx_ring_size = clamp_t(u16, ring->tx_pending,
3231                                    MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD);
3232         if (pp->tx_ring_size != ring->tx_pending)
3233                 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
3234                             pp->tx_ring_size, ring->tx_pending);
3235 
3236         if (netif_running(dev)) {
3237                 mvneta_stop(dev);
3238                 if (mvneta_open(dev)) {
3239                         netdev_err(dev,
3240                                    "error on opening device after ring param change\n");
3241                         return -ENOMEM;
3242                 }
3243         }
3244 
3245         return 0;
3246 }
3247 
3248 static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset,
3249                                        u8 *data)
3250 {
3251         if (sset == ETH_SS_STATS) {
3252                 int i;
3253 
3254                 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
3255                         memcpy(data + i * ETH_GSTRING_LEN,
3256                                mvneta_statistics[i].name, ETH_GSTRING_LEN);
3257         }
3258 }
3259 
3260 static void mvneta_ethtool_update_stats(struct mvneta_port *pp)
3261 {
3262         const struct mvneta_statistic *s;
3263         void __iomem *base = pp->base;
3264         u32 high, low, val;
3265         u64 val64;
3266         int i;
3267 
3268         for (i = 0, s = mvneta_statistics;
3269              s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics);
3270              s++, i++) {
3271                 switch (s->type) {
3272                 case T_REG_32:
3273                         val = readl_relaxed(base + s->offset);
3274                         pp->ethtool_stats[i] += val;
3275                         break;
3276                 case T_REG_64:
3277                         /* Docs say to read low 32-bit then high */
3278                         low = readl_relaxed(base + s->offset);
3279                         high = readl_relaxed(base + s->offset + 4);
3280                         val64 = (u64)high << 32 | low;
3281                         pp->ethtool_stats[i] += val64;
3282                         break;
3283                 }
3284         }
3285 }
3286 
3287 static void mvneta_ethtool_get_stats(struct net_device *dev,
3288                                      struct ethtool_stats *stats, u64 *data)
3289 {
3290         struct mvneta_port *pp = netdev_priv(dev);
3291         int i;
3292 
3293         mvneta_ethtool_update_stats(pp);
3294 
3295         for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
3296                 *data++ = pp->ethtool_stats[i];
3297 }
3298 
3299 static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset)
3300 {
3301         if (sset == ETH_SS_STATS)
3302                 return ARRAY_SIZE(mvneta_statistics);
3303         return -EOPNOTSUPP;
3304 }
3305 
3306 static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev)
3307 {
3308         return MVNETA_RSS_LU_TABLE_SIZE;
3309 }
3310 
3311 static int mvneta_ethtool_get_rxnfc(struct net_device *dev,
3312                                     struct ethtool_rxnfc *info,
3313                                     u32 *rules __always_unused)
3314 {
3315         switch (info->cmd) {
3316         case ETHTOOL_GRXRINGS:
3317                 info->data =  rxq_number;
3318                 return 0;
3319         case ETHTOOL_GRXFH:
3320                 return -EOPNOTSUPP;
3321         default:
3322                 return -EOPNOTSUPP;
3323         }
3324 }
3325 
3326 static int  mvneta_config_rss(struct mvneta_port *pp)
3327 {
3328         int cpu;
3329         u32 val;
3330 
3331         netif_tx_stop_all_queues(pp->dev);
3332 
3333         on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3334 
3335         /* We have to synchronise on the napi of each CPU */
3336         for_each_online_cpu(cpu) {
3337                 struct mvneta_pcpu_port *pcpu_port =
3338                         per_cpu_ptr(pp->ports, cpu);
3339 
3340                 napi_synchronize(&pcpu_port->napi);
3341                 napi_disable(&pcpu_port->napi);
3342         }
3343 
3344         pp->rxq_def = pp->indir[0];
3345 
3346         /* Update unicast mapping */
3347         mvneta_set_rx_mode(pp->dev);
3348 
3349         /* Update val of portCfg register accordingly with all RxQueue types */
3350         val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
3351         mvreg_write(pp, MVNETA_PORT_CONFIG, val);
3352 
3353         /* Update the elected CPU matching the new rxq_def */
3354         spin_lock(&pp->lock);
3355         mvneta_percpu_elect(pp);
3356         spin_unlock(&pp->lock);
3357 
3358         /* We have to synchronise on the napi of each CPU */
3359         for_each_online_cpu(cpu) {
3360                 struct mvneta_pcpu_port *pcpu_port =
3361                         per_cpu_ptr(pp->ports, cpu);
3362 
3363                 napi_enable(&pcpu_port->napi);
3364         }
3365 
3366         netif_tx_start_all_queues(pp->dev);
3367 
3368         return 0;
3369 }
3370 
3371 static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
3372                                    const u8 *key, const u8 hfunc)
3373 {
3374         struct mvneta_port *pp = netdev_priv(dev);
3375         /* We require at least one supported parameter to be changed
3376          * and no change in any of the unsupported parameters
3377          */
3378         if (key ||
3379             (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3380                 return -EOPNOTSUPP;
3381 
3382         if (!indir)
3383                 return 0;
3384 
3385         memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE);
3386 
3387         return mvneta_config_rss(pp);
3388 }
3389 
3390 static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3391                                    u8 *hfunc)
3392 {
3393         struct mvneta_port *pp = netdev_priv(dev);
3394 
3395         if (hfunc)
3396                 *hfunc = ETH_RSS_HASH_TOP;
3397 
3398         if (!indir)
3399                 return 0;
3400 
3401         memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE);
3402 
3403         return 0;
3404 }
3405 
3406 static const struct net_device_ops mvneta_netdev_ops = {
3407         .ndo_open            = mvneta_open,
3408         .ndo_stop            = mvneta_stop,
3409         .ndo_start_xmit      = mvneta_tx,
3410         .ndo_set_rx_mode     = mvneta_set_rx_mode,
3411         .ndo_set_mac_address = mvneta_set_mac_addr,
3412         .ndo_change_mtu      = mvneta_change_mtu,
3413         .ndo_fix_features    = mvneta_fix_features,
3414         .ndo_get_stats64     = mvneta_get_stats64,
3415         .ndo_do_ioctl        = mvneta_ioctl,
3416 };
3417 
3418 const struct ethtool_ops mvneta_eth_tool_ops = {
3419         .get_link       = ethtool_op_get_link,
3420         .get_settings   = mvneta_ethtool_get_settings,
3421         .set_settings   = mvneta_ethtool_set_settings,
3422         .set_coalesce   = mvneta_ethtool_set_coalesce,
3423         .get_coalesce   = mvneta_ethtool_get_coalesce,
3424         .get_drvinfo    = mvneta_ethtool_get_drvinfo,
3425         .get_ringparam  = mvneta_ethtool_get_ringparam,
3426         .set_ringparam  = mvneta_ethtool_set_ringparam,
3427         .get_strings    = mvneta_ethtool_get_strings,
3428         .get_ethtool_stats = mvneta_ethtool_get_stats,
3429         .get_sset_count = mvneta_ethtool_get_sset_count,
3430         .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size,
3431         .get_rxnfc      = mvneta_ethtool_get_rxnfc,
3432         .get_rxfh       = mvneta_ethtool_get_rxfh,
3433         .set_rxfh       = mvneta_ethtool_set_rxfh,
3434 };
3435 
3436 /* Initialize hw */
3437 static int mvneta_init(struct device *dev, struct mvneta_port *pp)
3438 {
3439         int queue;
3440 
3441         /* Disable port */
3442         mvneta_port_disable(pp);
3443 
3444         /* Set port default values */
3445         mvneta_defaults_set(pp);
3446 
3447         pp->txqs = devm_kcalloc(dev, txq_number, sizeof(struct mvneta_tx_queue),
3448                                 GFP_KERNEL);
3449         if (!pp->txqs)
3450                 return -ENOMEM;
3451 
3452         /* Initialize TX descriptor rings */
3453         for (queue = 0; queue < txq_number; queue++) {
3454                 struct mvneta_tx_queue *txq = &pp->txqs[queue];
3455                 txq->id = queue;
3456                 txq->size = pp->tx_ring_size;
3457                 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS;
3458         }
3459 
3460         pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(struct mvneta_rx_queue),
3461                                 GFP_KERNEL);
3462         if (!pp->rxqs)
3463                 return -ENOMEM;
3464 
3465         /* Create Rx descriptor rings */
3466         for (queue = 0; queue < rxq_number; queue++) {
3467                 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
3468                 rxq->id = queue;
3469                 rxq->size = pp->rx_ring_size;
3470                 rxq->pkts_coal = MVNETA_RX_COAL_PKTS;
3471                 rxq->time_coal = MVNETA_RX_COAL_USEC;
3472         }
3473 
3474         return 0;
3475 }
3476 
3477 /* platform glue : initialize decoding windows */
3478 static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
3479                                      const struct mbus_dram_target_info *dram)
3480 {
3481         u32 win_enable;
3482         u32 win_protect;
3483         int i;
3484 
3485         for (i = 0; i < 6; i++) {
3486                 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
3487                 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
3488 
3489                 if (i < 4)
3490                         mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
3491         }
3492 
3493         win_enable = 0x3f;
3494         win_protect = 0;
3495 
3496         for (i = 0; i < dram->num_cs; i++) {
3497                 const struct mbus_dram_window *cs = dram->cs + i;
3498                 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
3499                             (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
3500 
3501                 mvreg_write(pp, MVNETA_WIN_SIZE(i),
3502                             (cs->size - 1) & 0xffff0000);
3503 
3504                 win_enable &= ~(1 << i);
3505                 win_protect |= 3 << (2 * i);
3506         }
3507 
3508         mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
3509         mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
3510 }
3511 
3512 /* Power up the port */
3513 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
3514 {
3515         u32 ctrl;
3516 
3517         /* MAC Cause register should be cleared */
3518         mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
3519 
3520         ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
3521 
3522         /* Even though it might look weird, when we're configured in
3523          * SGMII or QSGMII mode, the RGMII bit needs to be set.
3524          */
3525         switch(phy_mode) {
3526         case PHY_INTERFACE_MODE_QSGMII:
3527                 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
3528                 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
3529                 break;
3530         case PHY_INTERFACE_MODE_SGMII:
3531                 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
3532                 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
3533                 break;
3534         case PHY_INTERFACE_MODE_RGMII:
3535         case PHY_INTERFACE_MODE_RGMII_ID:
3536                 ctrl |= MVNETA_GMAC2_PORT_RGMII;
3537                 break;
3538         default:
3539                 return -EINVAL;
3540         }
3541 
3542         /* Cancel Port Reset */
3543         ctrl &= ~MVNETA_GMAC2_PORT_RESET;
3544         mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
3545 
3546         while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
3547                 MVNETA_GMAC2_PORT_RESET) != 0)
3548                 continue;
3549 
3550         return 0;
3551 }
3552 
3553 /* Device initialization routine */
3554 static int mvneta_probe(struct platform_device *pdev)
3555 {
3556         const struct mbus_dram_target_info *dram_target_info;
3557         struct resource *res;
3558         struct device_node *dn = pdev->dev.of_node;
3559         struct device_node *phy_node;
3560         struct mvneta_port *pp;
3561         struct net_device *dev;
3562         const char *dt_mac_addr;
3563         char hw_mac_addr[ETH_ALEN];
3564         const char *mac_from;
3565         const char *managed;
3566         int tx_csum_limit;
3567         int phy_mode;
3568         int err;
3569         int cpu;
3570 
3571         dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number);
3572         if (!dev)
3573                 return -ENOMEM;
3574 
3575         dev->irq = irq_of_parse_and_map(dn, 0);
3576         if (dev->irq == 0) {
3577                 err = -EINVAL;
3578                 goto err_free_netdev;
3579         }
3580 
3581         phy_node = of_parse_phandle(dn, "phy", 0);
3582         if (!phy_node) {
3583                 if (!of_phy_is_fixed_link(dn)) {
3584                         dev_err(&pdev->dev, "no PHY specified\n");
3585                         err = -ENODEV;
3586                         goto err_free_irq;
3587                 }
3588 
3589                 err = of_phy_register_fixed_link(dn);
3590                 if (err < 0) {
3591                         dev_err(&pdev->dev, "cannot register fixed PHY\n");
3592                         goto err_free_irq;
3593                 }
3594 
3595                 /* In the case of a fixed PHY, the DT node associated
3596                  * to the PHY is the Ethernet MAC DT node.
3597                  */
3598                 phy_node = of_node_get(dn);
3599         }
3600 
3601         phy_mode = of_get_phy_mode(dn);
3602         if (phy_mode < 0) {
3603                 dev_err(&pdev->dev, "incorrect phy-mode\n");
3604                 err = -EINVAL;
3605                 goto err_put_phy_node;
3606         }
3607 
3608         dev->tx_queue_len = MVNETA_MAX_TXD;
3609         dev->watchdog_timeo = 5 * HZ;
3610         dev->netdev_ops = &mvneta_netdev_ops;
3611 
3612         dev->ethtool_ops = &mvneta_eth_tool_ops;
3613 
3614         pp = netdev_priv(dev);
3615         pp->phy_node = phy_node;
3616         pp->phy_interface = phy_mode;
3617 
3618         err = of_property_read_string(dn, "managed", &managed);
3619         pp->use_inband_status = (err == 0 &&
3620                                  strcmp(managed, "in-band-status") == 0);
3621         pp->cpu_notifier.notifier_call = mvneta_percpu_notifier;
3622 
3623         pp->rxq_def = rxq_def;
3624 
3625         pp->indir[0] = rxq_def;
3626 
3627         pp->clk = devm_clk_get(&pdev->dev, "core");
3628         if (IS_ERR(pp->clk))
3629                 pp->clk = devm_clk_get(&pdev->dev, NULL);
3630         if (IS_ERR(pp->clk)) {
3631                 err = PTR_ERR(pp->clk);
3632                 goto err_put_phy_node;
3633         }
3634 
3635         clk_prepare_enable(pp->clk);
3636 
3637         pp->clk_bus = devm_clk_get(&pdev->dev, "bus");
3638         if (!IS_ERR(pp->clk_bus))
3639                 clk_prepare_enable(pp->clk_bus);
3640 
3641         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3642         pp->base = devm_ioremap_resource(&pdev->dev, res);
3643         if (IS_ERR(pp->base)) {
3644                 err = PTR_ERR(pp->base);
3645                 goto err_clk;
3646         }
3647 
3648         /* Alloc per-cpu port structure */
3649         pp->ports = alloc_percpu(struct mvneta_pcpu_port);
3650         if (!pp->ports) {
3651                 err = -ENOMEM;
3652                 goto err_clk;
3653         }
3654 
3655         /* Alloc per-cpu stats */
3656         pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats);
3657         if (!pp->stats) {
3658                 err = -ENOMEM;
3659                 goto err_free_ports;
3660         }
3661 
3662         dt_mac_addr = of_get_mac_address(dn);
3663         if (dt_mac_addr) {
3664                 mac_from = "device tree";
3665                 memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN);
3666         } else {
3667                 mvneta_get_mac_addr(pp, hw_mac_addr);
3668                 if (is_valid_ether_addr(hw_mac_addr)) {
3669                         mac_from = "hardware";
3670                         memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN);
3671                 } else {
3672                         mac_from = "random";
3673                         eth_hw_addr_random(dev);
3674                 }
3675         }
3676 
3677         if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) {
3678                 if (tx_csum_limit < 0 ||
3679                     tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) {
3680                         tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
3681                         dev_info(&pdev->dev,
3682                                  "Wrong TX csum limit in DT, set to %dB\n",
3683                                  MVNETA_TX_CSUM_DEF_SIZE);
3684                 }
3685         } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) {
3686                 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
3687         } else {
3688                 tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE;
3689         }
3690 
3691         pp->tx_csum_limit = tx_csum_limit;
3692 
3693         pp->tx_ring_size = MVNETA_MAX_TXD;
3694         pp->rx_ring_size = MVNETA_MAX_RXD;
3695 
3696         pp->dev = dev;
3697         SET_NETDEV_DEV(dev, &pdev->dev);
3698 
3699         err = mvneta_init(&pdev->dev, pp);
3700         if (err < 0)
3701                 goto err_free_stats;
3702 
3703         err = mvneta_port_power_up(pp, phy_mode);
3704         if (err < 0) {
3705                 dev_err(&pdev->dev, "can't power up port\n");
3706                 goto err_free_stats;
3707         }
3708 
3709         dram_target_info = mv_mbus_dram_info();
3710         if (dram_target_info)
3711                 mvneta_conf_mbus_windows(pp, dram_target_info);
3712 
3713         for_each_present_cpu(cpu) {
3714                 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
3715 
3716                 netif_napi_add(dev, &port->napi, mvneta_poll, NAPI_POLL_WEIGHT);
3717                 port->pp = pp;
3718         }
3719 
3720         dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
3721         dev->hw_features |= dev->features;
3722         dev->vlan_features |= dev->features;
3723         dev->priv_flags |= IFF_UNICAST_FLT;
3724         dev->gso_max_segs = MVNETA_MAX_TSO_SEGS;
3725 
3726         err = register_netdev(dev);
3727         if (err < 0) {
3728                 dev_err(&pdev->dev, "failed to register\n");
3729                 goto err_free_stats;
3730         }
3731 
3732         netdev_info(dev, "Using %s mac address %pM\n", mac_from,
3733                     dev->dev_addr);
3734 
3735         platform_set_drvdata(pdev, pp->dev);
3736 
3737         if (pp->use_inband_status) {
3738                 struct phy_device *phy = of_phy_find_device(dn);
3739 
3740                 mvneta_fixed_link_update(pp, phy);
3741 
3742                 put_device(&phy->mdio.dev);
3743         }
3744 
3745         return 0;
3746 
3747 err_free_stats:
3748         free_percpu(pp->stats);
3749 err_free_ports:
3750         free_percpu(pp->ports);
3751 err_clk:
3752         clk_disable_unprepare(pp->clk_bus);
3753         clk_disable_unprepare(pp->clk);
3754 err_put_phy_node:
3755         of_node_put(phy_node);
3756 err_free_irq:
3757         irq_dispose_mapping(dev->irq);
3758 err_free_netdev:
3759         free_netdev(dev);
3760         return err;
3761 }
3762 
3763 /* Device removal routine */
3764 static int mvneta_remove(struct platform_device *pdev)
3765 {
3766         struct net_device  *dev = platform_get_drvdata(pdev);
3767         struct mvneta_port *pp = netdev_priv(dev);
3768 
3769         unregister_netdev(dev);
3770         clk_disable_unprepare(pp->clk_bus);
3771         clk_disable_unprepare(pp->clk);
3772         free_percpu(pp->ports);
3773         free_percpu(pp->stats);
3774         irq_dispose_mapping(dev->irq);
3775         of_node_put(pp->phy_node);
3776         free_netdev(dev);
3777 
3778         return 0;
3779 }
3780 
3781 static const struct of_device_id mvneta_match[] = {
3782         { .compatible = "marvell,armada-370-neta" },
3783         { .compatible = "marvell,armada-xp-neta" },
3784         { }
3785 };
3786 MODULE_DEVICE_TABLE(of, mvneta_match);
3787 
3788 static struct platform_driver mvneta_driver = {
3789         .probe = mvneta_probe,
3790         .remove = mvneta_remove,
3791         .driver = {
3792                 .name = MVNETA_DRIVER_NAME,
3793                 .of_match_table = mvneta_match,
3794         },
3795 };
3796 
3797 module_platform_driver(mvneta_driver);
3798 
3799 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
3800 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
3801 MODULE_LICENSE("GPL");
3802 
3803 module_param(rxq_number, int, S_IRUGO);
3804 module_param(txq_number, int, S_IRUGO);
3805 
3806 module_param(rxq_def, int, S_IRUGO);
3807 module_param(rx_copybreak, int, S_IRUGO | S_IWUSR);
3808 

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