Version:  2.0.40 2.2.26 2.4.37 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9

Linux/drivers/net/ethernet/marvell/mvneta.c

  1 /*
  2  * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
  3  *
  4  * Copyright (C) 2012 Marvell
  5  *
  6  * Rami Rosen <rosenr@marvell.com>
  7  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  8  *
  9  * This file is licensed under the terms of the GNU General Public
 10  * License version 2. This program is licensed "as is" without any
 11  * warranty of any kind, whether express or implied.
 12  */
 13 
 14 #include <linux/clk.h>
 15 #include <linux/cpu.h>
 16 #include <linux/etherdevice.h>
 17 #include <linux/if_vlan.h>
 18 #include <linux/inetdevice.h>
 19 #include <linux/interrupt.h>
 20 #include <linux/io.h>
 21 #include <linux/kernel.h>
 22 #include <linux/mbus.h>
 23 #include <linux/module.h>
 24 #include <linux/netdevice.h>
 25 #include <linux/of.h>
 26 #include <linux/of_address.h>
 27 #include <linux/of_irq.h>
 28 #include <linux/of_mdio.h>
 29 #include <linux/of_net.h>
 30 #include <linux/phy.h>
 31 #include <linux/platform_device.h>
 32 #include <linux/skbuff.h>
 33 #include <net/hwbm.h>
 34 #include "mvneta_bm.h"
 35 #include <net/ip.h>
 36 #include <net/ipv6.h>
 37 #include <net/tso.h>
 38 
 39 /* Registers */
 40 #define MVNETA_RXQ_CONFIG_REG(q)                (0x1400 + ((q) << 2))
 41 #define      MVNETA_RXQ_HW_BUF_ALLOC            BIT(0)
 42 #define      MVNETA_RXQ_SHORT_POOL_ID_SHIFT     4
 43 #define      MVNETA_RXQ_SHORT_POOL_ID_MASK      0x30
 44 #define      MVNETA_RXQ_LONG_POOL_ID_SHIFT      6
 45 #define      MVNETA_RXQ_LONG_POOL_ID_MASK       0xc0
 46 #define      MVNETA_RXQ_PKT_OFFSET_ALL_MASK     (0xf    << 8)
 47 #define      MVNETA_RXQ_PKT_OFFSET_MASK(offs)   ((offs) << 8)
 48 #define MVNETA_RXQ_THRESHOLD_REG(q)             (0x14c0 + ((q) << 2))
 49 #define      MVNETA_RXQ_NON_OCCUPIED(v)         ((v) << 16)
 50 #define MVNETA_RXQ_BASE_ADDR_REG(q)             (0x1480 + ((q) << 2))
 51 #define MVNETA_RXQ_SIZE_REG(q)                  (0x14a0 + ((q) << 2))
 52 #define      MVNETA_RXQ_BUF_SIZE_SHIFT          19
 53 #define      MVNETA_RXQ_BUF_SIZE_MASK           (0x1fff << 19)
 54 #define MVNETA_RXQ_STATUS_REG(q)                (0x14e0 + ((q) << 2))
 55 #define      MVNETA_RXQ_OCCUPIED_ALL_MASK       0x3fff
 56 #define MVNETA_RXQ_STATUS_UPDATE_REG(q)         (0x1500 + ((q) << 2))
 57 #define      MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT  16
 58 #define      MVNETA_RXQ_ADD_NON_OCCUPIED_MAX    255
 59 #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool)    (0x1700 + ((pool) << 2))
 60 #define      MVNETA_PORT_POOL_BUFFER_SZ_SHIFT   3
 61 #define      MVNETA_PORT_POOL_BUFFER_SZ_MASK    0xfff8
 62 #define MVNETA_PORT_RX_RESET                    0x1cc0
 63 #define      MVNETA_PORT_RX_DMA_RESET           BIT(0)
 64 #define MVNETA_PHY_ADDR                         0x2000
 65 #define      MVNETA_PHY_ADDR_MASK               0x1f
 66 #define MVNETA_MBUS_RETRY                       0x2010
 67 #define MVNETA_UNIT_INTR_CAUSE                  0x2080
 68 #define MVNETA_UNIT_CONTROL                     0x20B0
 69 #define      MVNETA_PHY_POLLING_ENABLE          BIT(1)
 70 #define MVNETA_WIN_BASE(w)                      (0x2200 + ((w) << 3))
 71 #define MVNETA_WIN_SIZE(w)                      (0x2204 + ((w) << 3))
 72 #define MVNETA_WIN_REMAP(w)                     (0x2280 + ((w) << 2))
 73 #define MVNETA_BASE_ADDR_ENABLE                 0x2290
 74 #define MVNETA_ACCESS_PROTECT_ENABLE            0x2294
 75 #define MVNETA_PORT_CONFIG                      0x2400
 76 #define      MVNETA_UNI_PROMISC_MODE            BIT(0)
 77 #define      MVNETA_DEF_RXQ(q)                  ((q) << 1)
 78 #define      MVNETA_DEF_RXQ_ARP(q)              ((q) << 4)
 79 #define      MVNETA_TX_UNSET_ERR_SUM            BIT(12)
 80 #define      MVNETA_DEF_RXQ_TCP(q)              ((q) << 16)
 81 #define      MVNETA_DEF_RXQ_UDP(q)              ((q) << 19)
 82 #define      MVNETA_DEF_RXQ_BPDU(q)             ((q) << 22)
 83 #define      MVNETA_RX_CSUM_WITH_PSEUDO_HDR     BIT(25)
 84 #define      MVNETA_PORT_CONFIG_DEFL_VALUE(q)   (MVNETA_DEF_RXQ(q)       | \
 85                                                  MVNETA_DEF_RXQ_ARP(q)   | \
 86                                                  MVNETA_DEF_RXQ_TCP(q)   | \
 87                                                  MVNETA_DEF_RXQ_UDP(q)   | \
 88                                                  MVNETA_DEF_RXQ_BPDU(q)  | \
 89                                                  MVNETA_TX_UNSET_ERR_SUM | \
 90                                                  MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
 91 #define MVNETA_PORT_CONFIG_EXTEND                0x2404
 92 #define MVNETA_MAC_ADDR_LOW                      0x2414
 93 #define MVNETA_MAC_ADDR_HIGH                     0x2418
 94 #define MVNETA_SDMA_CONFIG                       0x241c
 95 #define      MVNETA_SDMA_BRST_SIZE_16            4
 96 #define      MVNETA_RX_BRST_SZ_MASK(burst)       ((burst) << 1)
 97 #define      MVNETA_RX_NO_DATA_SWAP              BIT(4)
 98 #define      MVNETA_TX_NO_DATA_SWAP              BIT(5)
 99 #define      MVNETA_DESC_SWAP                    BIT(6)
100 #define      MVNETA_TX_BRST_SZ_MASK(burst)       ((burst) << 22)
101 #define MVNETA_PORT_STATUS                       0x2444
102 #define      MVNETA_TX_IN_PRGRS                  BIT(1)
103 #define      MVNETA_TX_FIFO_EMPTY                BIT(8)
104 #define MVNETA_RX_MIN_FRAME_SIZE                 0x247c
105 #define MVNETA_SERDES_CFG                        0x24A0
106 #define      MVNETA_SGMII_SERDES_PROTO           0x0cc7
107 #define      MVNETA_QSGMII_SERDES_PROTO          0x0667
108 #define MVNETA_TYPE_PRIO                         0x24bc
109 #define      MVNETA_FORCE_UNI                    BIT(21)
110 #define MVNETA_TXQ_CMD_1                         0x24e4
111 #define MVNETA_TXQ_CMD                           0x2448
112 #define      MVNETA_TXQ_DISABLE_SHIFT            8
113 #define      MVNETA_TXQ_ENABLE_MASK              0x000000ff
114 #define MVNETA_RX_DISCARD_FRAME_COUNT            0x2484
115 #define MVNETA_OVERRUN_FRAME_COUNT               0x2488
116 #define MVNETA_GMAC_CLOCK_DIVIDER                0x24f4
117 #define      MVNETA_GMAC_1MS_CLOCK_ENABLE        BIT(31)
118 #define MVNETA_ACC_MODE                          0x2500
119 #define MVNETA_BM_ADDRESS                        0x2504
120 #define MVNETA_CPU_MAP(cpu)                      (0x2540 + ((cpu) << 2))
121 #define      MVNETA_CPU_RXQ_ACCESS_ALL_MASK      0x000000ff
122 #define      MVNETA_CPU_TXQ_ACCESS_ALL_MASK      0x0000ff00
123 #define      MVNETA_CPU_RXQ_ACCESS(rxq)          BIT(rxq)
124 #define      MVNETA_CPU_TXQ_ACCESS(txq)          BIT(txq + 8)
125 #define MVNETA_RXQ_TIME_COAL_REG(q)              (0x2580 + ((q) << 2))
126 
127 /* Exception Interrupt Port/Queue Cause register
128  *
129  * Their behavior depend of the mapping done using the PCPX2Q
130  * registers. For a given CPU if the bit associated to a queue is not
131  * set, then for the register a read from this CPU will always return
132  * 0 and a write won't do anything
133  */
134 
135 #define MVNETA_INTR_NEW_CAUSE                    0x25a0
136 #define MVNETA_INTR_NEW_MASK                     0x25a4
137 
138 /* bits  0..7  = TXQ SENT, one bit per queue.
139  * bits  8..15 = RXQ OCCUP, one bit per queue.
140  * bits 16..23 = RXQ FREE, one bit per queue.
141  * bit  29 = OLD_REG_SUM, see old reg ?
142  * bit  30 = TX_ERR_SUM, one bit for 4 ports
143  * bit  31 = MISC_SUM,   one bit for 4 ports
144  */
145 #define      MVNETA_TX_INTR_MASK(nr_txqs)        (((1 << nr_txqs) - 1) << 0)
146 #define      MVNETA_TX_INTR_MASK_ALL             (0xff << 0)
147 #define      MVNETA_RX_INTR_MASK(nr_rxqs)        (((1 << nr_rxqs) - 1) << 8)
148 #define      MVNETA_RX_INTR_MASK_ALL             (0xff << 8)
149 #define      MVNETA_MISCINTR_INTR_MASK           BIT(31)
150 
151 #define MVNETA_INTR_OLD_CAUSE                    0x25a8
152 #define MVNETA_INTR_OLD_MASK                     0x25ac
153 
154 /* Data Path Port/Queue Cause Register */
155 #define MVNETA_INTR_MISC_CAUSE                   0x25b0
156 #define MVNETA_INTR_MISC_MASK                    0x25b4
157 
158 #define      MVNETA_CAUSE_PHY_STATUS_CHANGE      BIT(0)
159 #define      MVNETA_CAUSE_LINK_CHANGE            BIT(1)
160 #define      MVNETA_CAUSE_PTP                    BIT(4)
161 
162 #define      MVNETA_CAUSE_INTERNAL_ADDR_ERR      BIT(7)
163 #define      MVNETA_CAUSE_RX_OVERRUN             BIT(8)
164 #define      MVNETA_CAUSE_RX_CRC_ERROR           BIT(9)
165 #define      MVNETA_CAUSE_RX_LARGE_PKT           BIT(10)
166 #define      MVNETA_CAUSE_TX_UNDERUN             BIT(11)
167 #define      MVNETA_CAUSE_PRBS_ERR               BIT(12)
168 #define      MVNETA_CAUSE_PSC_SYNC_CHANGE        BIT(13)
169 #define      MVNETA_CAUSE_SERDES_SYNC_ERR        BIT(14)
170 
171 #define      MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT    16
172 #define      MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK   (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT)
173 #define      MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool)))
174 
175 #define      MVNETA_CAUSE_TXQ_ERROR_SHIFT        24
176 #define      MVNETA_CAUSE_TXQ_ERROR_ALL_MASK     (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT)
177 #define      MVNETA_CAUSE_TXQ_ERROR_MASK(q)      (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q)))
178 
179 #define MVNETA_INTR_ENABLE                       0x25b8
180 #define      MVNETA_TXQ_INTR_ENABLE_ALL_MASK     0x0000ff00
181 #define      MVNETA_RXQ_INTR_ENABLE_ALL_MASK     0x000000ff
182 
183 #define MVNETA_RXQ_CMD                           0x2680
184 #define      MVNETA_RXQ_DISABLE_SHIFT            8
185 #define      MVNETA_RXQ_ENABLE_MASK              0x000000ff
186 #define MVETH_TXQ_TOKEN_COUNT_REG(q)             (0x2700 + ((q) << 4))
187 #define MVETH_TXQ_TOKEN_CFG_REG(q)               (0x2704 + ((q) << 4))
188 #define MVNETA_GMAC_CTRL_0                       0x2c00
189 #define      MVNETA_GMAC_MAX_RX_SIZE_SHIFT       2
190 #define      MVNETA_GMAC_MAX_RX_SIZE_MASK        0x7ffc
191 #define      MVNETA_GMAC0_PORT_ENABLE            BIT(0)
192 #define MVNETA_GMAC_CTRL_2                       0x2c08
193 #define      MVNETA_GMAC2_INBAND_AN_ENABLE       BIT(0)
194 #define      MVNETA_GMAC2_PCS_ENABLE             BIT(3)
195 #define      MVNETA_GMAC2_PORT_RGMII             BIT(4)
196 #define      MVNETA_GMAC2_PORT_RESET             BIT(6)
197 #define MVNETA_GMAC_STATUS                       0x2c10
198 #define      MVNETA_GMAC_LINK_UP                 BIT(0)
199 #define      MVNETA_GMAC_SPEED_1000              BIT(1)
200 #define      MVNETA_GMAC_SPEED_100               BIT(2)
201 #define      MVNETA_GMAC_FULL_DUPLEX             BIT(3)
202 #define      MVNETA_GMAC_RX_FLOW_CTRL_ENABLE     BIT(4)
203 #define      MVNETA_GMAC_TX_FLOW_CTRL_ENABLE     BIT(5)
204 #define      MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE     BIT(6)
205 #define      MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE     BIT(7)
206 #define MVNETA_GMAC_AUTONEG_CONFIG               0x2c0c
207 #define      MVNETA_GMAC_FORCE_LINK_DOWN         BIT(0)
208 #define      MVNETA_GMAC_FORCE_LINK_PASS         BIT(1)
209 #define      MVNETA_GMAC_INBAND_AN_ENABLE        BIT(2)
210 #define      MVNETA_GMAC_CONFIG_MII_SPEED        BIT(5)
211 #define      MVNETA_GMAC_CONFIG_GMII_SPEED       BIT(6)
212 #define      MVNETA_GMAC_AN_SPEED_EN             BIT(7)
213 #define      MVNETA_GMAC_AN_FLOW_CTRL_EN         BIT(11)
214 #define      MVNETA_GMAC_CONFIG_FULL_DUPLEX      BIT(12)
215 #define      MVNETA_GMAC_AN_DUPLEX_EN            BIT(13)
216 #define MVNETA_MIB_COUNTERS_BASE                 0x3000
217 #define      MVNETA_MIB_LATE_COLLISION           0x7c
218 #define MVNETA_DA_FILT_SPEC_MCAST                0x3400
219 #define MVNETA_DA_FILT_OTH_MCAST                 0x3500
220 #define MVNETA_DA_FILT_UCAST_BASE                0x3600
221 #define MVNETA_TXQ_BASE_ADDR_REG(q)              (0x3c00 + ((q) << 2))
222 #define MVNETA_TXQ_SIZE_REG(q)                   (0x3c20 + ((q) << 2))
223 #define      MVNETA_TXQ_SENT_THRESH_ALL_MASK     0x3fff0000
224 #define      MVNETA_TXQ_SENT_THRESH_MASK(coal)   ((coal) << 16)
225 #define MVNETA_TXQ_UPDATE_REG(q)                 (0x3c60 + ((q) << 2))
226 #define      MVNETA_TXQ_DEC_SENT_SHIFT           16
227 #define MVNETA_TXQ_STATUS_REG(q)                 (0x3c40 + ((q) << 2))
228 #define      MVNETA_TXQ_SENT_DESC_SHIFT          16
229 #define      MVNETA_TXQ_SENT_DESC_MASK           0x3fff0000
230 #define MVNETA_PORT_TX_RESET                     0x3cf0
231 #define      MVNETA_PORT_TX_DMA_RESET            BIT(0)
232 #define MVNETA_TX_MTU                            0x3e0c
233 #define MVNETA_TX_TOKEN_SIZE                     0x3e14
234 #define      MVNETA_TX_TOKEN_SIZE_MAX            0xffffffff
235 #define MVNETA_TXQ_TOKEN_SIZE_REG(q)             (0x3e40 + ((q) << 2))
236 #define      MVNETA_TXQ_TOKEN_SIZE_MAX           0x7fffffff
237 
238 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK      0xff
239 
240 /* Descriptor ring Macros */
241 #define MVNETA_QUEUE_NEXT_DESC(q, index)        \
242         (((index) < (q)->last_desc) ? ((index) + 1) : 0)
243 
244 /* Various constants */
245 
246 /* Coalescing */
247 #define MVNETA_TXDONE_COAL_PKTS         0       /* interrupt per packet */
248 #define MVNETA_RX_COAL_PKTS             32
249 #define MVNETA_RX_COAL_USEC             100
250 
251 /* The two bytes Marvell header. Either contains a special value used
252  * by Marvell switches when a specific hardware mode is enabled (not
253  * supported by this driver) or is filled automatically by zeroes on
254  * the RX side. Those two bytes being at the front of the Ethernet
255  * header, they allow to have the IP header aligned on a 4 bytes
256  * boundary automatically: the hardware skips those two bytes on its
257  * own.
258  */
259 #define MVNETA_MH_SIZE                  2
260 
261 #define MVNETA_VLAN_TAG_LEN             4
262 
263 #define MVNETA_TX_CSUM_DEF_SIZE         1600
264 #define MVNETA_TX_CSUM_MAX_SIZE         9800
265 #define MVNETA_ACC_MODE_EXT1            1
266 #define MVNETA_ACC_MODE_EXT2            2
267 
268 #define MVNETA_MAX_DECODE_WIN           6
269 
270 /* Timeout constants */
271 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC  1000
272 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC  1000
273 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT    10000
274 
275 #define MVNETA_TX_MTU_MAX               0x3ffff
276 
277 /* The RSS lookup table actually has 256 entries but we do not use
278  * them yet
279  */
280 #define MVNETA_RSS_LU_TABLE_SIZE        1
281 
282 /* TSO header size */
283 #define TSO_HEADER_SIZE 128
284 
285 /* Max number of Rx descriptors */
286 #define MVNETA_MAX_RXD 128
287 
288 /* Max number of Tx descriptors */
289 #define MVNETA_MAX_TXD 532
290 
291 /* Max number of allowed TCP segments for software TSO */
292 #define MVNETA_MAX_TSO_SEGS 100
293 
294 #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
295 
296 /* descriptor aligned size */
297 #define MVNETA_DESC_ALIGNED_SIZE        32
298 
299 #define MVNETA_RX_PKT_SIZE(mtu) \
300         ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
301               ETH_HLEN + ETH_FCS_LEN,                        \
302               cache_line_size())
303 
304 #define IS_TSO_HEADER(txq, addr) \
305         ((addr >= txq->tso_hdrs_phys) && \
306          (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE))
307 
308 #define MVNETA_RX_GET_BM_POOL_ID(rxd) \
309         (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
310 
311 struct mvneta_statistic {
312         unsigned short offset;
313         unsigned short type;
314         const char name[ETH_GSTRING_LEN];
315 };
316 
317 #define T_REG_32        32
318 #define T_REG_64        64
319 
320 static const struct mvneta_statistic mvneta_statistics[] = {
321         { 0x3000, T_REG_64, "good_octets_received", },
322         { 0x3010, T_REG_32, "good_frames_received", },
323         { 0x3008, T_REG_32, "bad_octets_received", },
324         { 0x3014, T_REG_32, "bad_frames_received", },
325         { 0x3018, T_REG_32, "broadcast_frames_received", },
326         { 0x301c, T_REG_32, "multicast_frames_received", },
327         { 0x3050, T_REG_32, "unrec_mac_control_received", },
328         { 0x3058, T_REG_32, "good_fc_received", },
329         { 0x305c, T_REG_32, "bad_fc_received", },
330         { 0x3060, T_REG_32, "undersize_received", },
331         { 0x3064, T_REG_32, "fragments_received", },
332         { 0x3068, T_REG_32, "oversize_received", },
333         { 0x306c, T_REG_32, "jabber_received", },
334         { 0x3070, T_REG_32, "mac_receive_error", },
335         { 0x3074, T_REG_32, "bad_crc_event", },
336         { 0x3078, T_REG_32, "collision", },
337         { 0x307c, T_REG_32, "late_collision", },
338         { 0x2484, T_REG_32, "rx_discard", },
339         { 0x2488, T_REG_32, "rx_overrun", },
340         { 0x3020, T_REG_32, "frames_64_octets", },
341         { 0x3024, T_REG_32, "frames_65_to_127_octets", },
342         { 0x3028, T_REG_32, "frames_128_to_255_octets", },
343         { 0x302c, T_REG_32, "frames_256_to_511_octets", },
344         { 0x3030, T_REG_32, "frames_512_to_1023_octets", },
345         { 0x3034, T_REG_32, "frames_1024_to_max_octets", },
346         { 0x3038, T_REG_64, "good_octets_sent", },
347         { 0x3040, T_REG_32, "good_frames_sent", },
348         { 0x3044, T_REG_32, "excessive_collision", },
349         { 0x3048, T_REG_32, "multicast_frames_sent", },
350         { 0x304c, T_REG_32, "broadcast_frames_sent", },
351         { 0x3054, T_REG_32, "fc_sent", },
352         { 0x300c, T_REG_32, "internal_mac_transmit_err", },
353 };
354 
355 struct mvneta_pcpu_stats {
356         struct  u64_stats_sync syncp;
357         u64     rx_packets;
358         u64     rx_bytes;
359         u64     tx_packets;
360         u64     tx_bytes;
361 };
362 
363 struct mvneta_pcpu_port {
364         /* Pointer to the shared port */
365         struct mvneta_port      *pp;
366 
367         /* Pointer to the CPU-local NAPI struct */
368         struct napi_struct      napi;
369 
370         /* Cause of the previous interrupt */
371         u32                     cause_rx_tx;
372 };
373 
374 struct mvneta_port {
375         u8 id;
376         struct mvneta_pcpu_port __percpu        *ports;
377         struct mvneta_pcpu_stats __percpu       *stats;
378 
379         int pkt_size;
380         unsigned int frag_size;
381         void __iomem *base;
382         struct mvneta_rx_queue *rxqs;
383         struct mvneta_tx_queue *txqs;
384         struct net_device *dev;
385         struct hlist_node node_online;
386         struct hlist_node node_dead;
387         int rxq_def;
388         /* Protect the access to the percpu interrupt registers,
389          * ensuring that the configuration remains coherent.
390          */
391         spinlock_t lock;
392         bool is_stopped;
393 
394         /* Core clock */
395         struct clk *clk;
396         /* AXI clock */
397         struct clk *clk_bus;
398         u8 mcast_count[256];
399         u16 tx_ring_size;
400         u16 rx_ring_size;
401 
402         struct mii_bus *mii_bus;
403         phy_interface_t phy_interface;
404         struct device_node *phy_node;
405         unsigned int link;
406         unsigned int duplex;
407         unsigned int speed;
408         unsigned int tx_csum_limit;
409         unsigned int use_inband_status:1;
410 
411         struct mvneta_bm *bm_priv;
412         struct mvneta_bm_pool *pool_long;
413         struct mvneta_bm_pool *pool_short;
414         int bm_win_id;
415 
416         u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
417 
418         u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
419 };
420 
421 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
422  * layout of the transmit and reception DMA descriptors, and their
423  * layout is therefore defined by the hardware design
424  */
425 
426 #define MVNETA_TX_L3_OFF_SHIFT  0
427 #define MVNETA_TX_IP_HLEN_SHIFT 8
428 #define MVNETA_TX_L4_UDP        BIT(16)
429 #define MVNETA_TX_L3_IP6        BIT(17)
430 #define MVNETA_TXD_IP_CSUM      BIT(18)
431 #define MVNETA_TXD_Z_PAD        BIT(19)
432 #define MVNETA_TXD_L_DESC       BIT(20)
433 #define MVNETA_TXD_F_DESC       BIT(21)
434 #define MVNETA_TXD_FLZ_DESC     (MVNETA_TXD_Z_PAD  | \
435                                  MVNETA_TXD_L_DESC | \
436                                  MVNETA_TXD_F_DESC)
437 #define MVNETA_TX_L4_CSUM_FULL  BIT(30)
438 #define MVNETA_TX_L4_CSUM_NOT   BIT(31)
439 
440 #define MVNETA_RXD_ERR_CRC              0x0
441 #define MVNETA_RXD_BM_POOL_SHIFT        13
442 #define MVNETA_RXD_BM_POOL_MASK         (BIT(13) | BIT(14))
443 #define MVNETA_RXD_ERR_SUMMARY          BIT(16)
444 #define MVNETA_RXD_ERR_OVERRUN          BIT(17)
445 #define MVNETA_RXD_ERR_LEN              BIT(18)
446 #define MVNETA_RXD_ERR_RESOURCE         (BIT(17) | BIT(18))
447 #define MVNETA_RXD_ERR_CODE_MASK        (BIT(17) | BIT(18))
448 #define MVNETA_RXD_L3_IP4               BIT(25)
449 #define MVNETA_RXD_FIRST_LAST_DESC      (BIT(26) | BIT(27))
450 #define MVNETA_RXD_L4_CSUM_OK           BIT(30)
451 
452 #if defined(__LITTLE_ENDIAN)
453 struct mvneta_tx_desc {
454         u32  command;           /* Options used by HW for packet transmitting.*/
455         u16  reserverd1;        /* csum_l4 (for future use)             */
456         u16  data_size;         /* Data size of transmitted packet in bytes */
457         u32  buf_phys_addr;     /* Physical addr of transmitted buffer  */
458         u32  reserved2;         /* hw_cmd - (for future use, PMT)       */
459         u32  reserved3[4];      /* Reserved - (for future use)          */
460 };
461 
462 struct mvneta_rx_desc {
463         u32  status;            /* Info about received packet           */
464         u16  reserved1;         /* pnc_info - (for future use, PnC)     */
465         u16  data_size;         /* Size of received packet in bytes     */
466 
467         u32  buf_phys_addr;     /* Physical address of the buffer       */
468         u32  reserved2;         /* pnc_flow_id  (for future use, PnC)   */
469 
470         u32  buf_cookie;        /* cookie for access to RX buffer in rx path */
471         u16  reserved3;         /* prefetch_cmd, for future use         */
472         u16  reserved4;         /* csum_l4 - (for future use, PnC)      */
473 
474         u32  reserved5;         /* pnc_extra PnC (for future use, PnC)  */
475         u32  reserved6;         /* hw_cmd (for future use, PnC and HWF) */
476 };
477 #else
478 struct mvneta_tx_desc {
479         u16  data_size;         /* Data size of transmitted packet in bytes */
480         u16  reserverd1;        /* csum_l4 (for future use)             */
481         u32  command;           /* Options used by HW for packet transmitting.*/
482         u32  reserved2;         /* hw_cmd - (for future use, PMT)       */
483         u32  buf_phys_addr;     /* Physical addr of transmitted buffer  */
484         u32  reserved3[4];      /* Reserved - (for future use)          */
485 };
486 
487 struct mvneta_rx_desc {
488         u16  data_size;         /* Size of received packet in bytes     */
489         u16  reserved1;         /* pnc_info - (for future use, PnC)     */
490         u32  status;            /* Info about received packet           */
491 
492         u32  reserved2;         /* pnc_flow_id  (for future use, PnC)   */
493         u32  buf_phys_addr;     /* Physical address of the buffer       */
494 
495         u16  reserved4;         /* csum_l4 - (for future use, PnC)      */
496         u16  reserved3;         /* prefetch_cmd, for future use         */
497         u32  buf_cookie;        /* cookie for access to RX buffer in rx path */
498 
499         u32  reserved5;         /* pnc_extra PnC (for future use, PnC)  */
500         u32  reserved6;         /* hw_cmd (for future use, PnC and HWF) */
501 };
502 #endif
503 
504 struct mvneta_tx_queue {
505         /* Number of this TX queue, in the range 0-7 */
506         u8 id;
507 
508         /* Number of TX DMA descriptors in the descriptor ring */
509         int size;
510 
511         /* Number of currently used TX DMA descriptor in the
512          * descriptor ring
513          */
514         int count;
515         int tx_stop_threshold;
516         int tx_wake_threshold;
517 
518         /* Array of transmitted skb */
519         struct sk_buff **tx_skb;
520 
521         /* Index of last TX DMA descriptor that was inserted */
522         int txq_put_index;
523 
524         /* Index of the TX DMA descriptor to be cleaned up */
525         int txq_get_index;
526 
527         u32 done_pkts_coal;
528 
529         /* Virtual address of the TX DMA descriptors array */
530         struct mvneta_tx_desc *descs;
531 
532         /* DMA address of the TX DMA descriptors array */
533         dma_addr_t descs_phys;
534 
535         /* Index of the last TX DMA descriptor */
536         int last_desc;
537 
538         /* Index of the next TX DMA descriptor to process */
539         int next_desc_to_proc;
540 
541         /* DMA buffers for TSO headers */
542         char *tso_hdrs;
543 
544         /* DMA address of TSO headers */
545         dma_addr_t tso_hdrs_phys;
546 
547         /* Affinity mask for CPUs*/
548         cpumask_t affinity_mask;
549 };
550 
551 struct mvneta_rx_queue {
552         /* rx queue number, in the range 0-7 */
553         u8 id;
554 
555         /* num of rx descriptors in the rx descriptor ring */
556         int size;
557 
558         /* counter of times when mvneta_refill() failed */
559         int missed;
560 
561         u32 pkts_coal;
562         u32 time_coal;
563 
564         /* Virtual address of the RX DMA descriptors array */
565         struct mvneta_rx_desc *descs;
566 
567         /* DMA address of the RX DMA descriptors array */
568         dma_addr_t descs_phys;
569 
570         /* Index of the last RX DMA descriptor */
571         int last_desc;
572 
573         /* Index of the next RX DMA descriptor to process */
574         int next_desc_to_proc;
575 };
576 
577 static enum cpuhp_state online_hpstate;
578 /* The hardware supports eight (8) rx queues, but we are only allowing
579  * the first one to be used. Therefore, let's just allocate one queue.
580  */
581 static int rxq_number = 8;
582 static int txq_number = 8;
583 
584 static int rxq_def;
585 
586 static int rx_copybreak __read_mostly = 256;
587 
588 /* HW BM need that each port be identify by a unique ID */
589 static int global_port_id;
590 
591 #define MVNETA_DRIVER_NAME "mvneta"
592 #define MVNETA_DRIVER_VERSION "1.0"
593 
594 /* Utility/helper methods */
595 
596 /* Write helper method */
597 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
598 {
599         writel(data, pp->base + offset);
600 }
601 
602 /* Read helper method */
603 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
604 {
605         return readl(pp->base + offset);
606 }
607 
608 /* Increment txq get counter */
609 static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq)
610 {
611         txq->txq_get_index++;
612         if (txq->txq_get_index == txq->size)
613                 txq->txq_get_index = 0;
614 }
615 
616 /* Increment txq put counter */
617 static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq)
618 {
619         txq->txq_put_index++;
620         if (txq->txq_put_index == txq->size)
621                 txq->txq_put_index = 0;
622 }
623 
624 
625 /* Clear all MIB counters */
626 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
627 {
628         int i;
629         u32 dummy;
630 
631         /* Perform dummy reads from MIB counters */
632         for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
633                 dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
634         dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT);
635         dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT);
636 }
637 
638 /* Get System Network Statistics */
639 static struct rtnl_link_stats64 *
640 mvneta_get_stats64(struct net_device *dev,
641                    struct rtnl_link_stats64 *stats)
642 {
643         struct mvneta_port *pp = netdev_priv(dev);
644         unsigned int start;
645         int cpu;
646 
647         for_each_possible_cpu(cpu) {
648                 struct mvneta_pcpu_stats *cpu_stats;
649                 u64 rx_packets;
650                 u64 rx_bytes;
651                 u64 tx_packets;
652                 u64 tx_bytes;
653 
654                 cpu_stats = per_cpu_ptr(pp->stats, cpu);
655                 do {
656                         start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
657                         rx_packets = cpu_stats->rx_packets;
658                         rx_bytes   = cpu_stats->rx_bytes;
659                         tx_packets = cpu_stats->tx_packets;
660                         tx_bytes   = cpu_stats->tx_bytes;
661                 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
662 
663                 stats->rx_packets += rx_packets;
664                 stats->rx_bytes   += rx_bytes;
665                 stats->tx_packets += tx_packets;
666                 stats->tx_bytes   += tx_bytes;
667         }
668 
669         stats->rx_errors        = dev->stats.rx_errors;
670         stats->rx_dropped       = dev->stats.rx_dropped;
671 
672         stats->tx_dropped       = dev->stats.tx_dropped;
673 
674         return stats;
675 }
676 
677 /* Rx descriptors helper methods */
678 
679 /* Checks whether the RX descriptor having this status is both the first
680  * and the last descriptor for the RX packet. Each RX packet is currently
681  * received through a single RX descriptor, so not having each RX
682  * descriptor with its first and last bits set is an error
683  */
684 static int mvneta_rxq_desc_is_first_last(u32 status)
685 {
686         return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
687                 MVNETA_RXD_FIRST_LAST_DESC;
688 }
689 
690 /* Add number of descriptors ready to receive new packets */
691 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
692                                           struct mvneta_rx_queue *rxq,
693                                           int ndescs)
694 {
695         /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
696          * be added at once
697          */
698         while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
699                 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
700                             (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
701                              MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
702                 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
703         }
704 
705         mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
706                     (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
707 }
708 
709 /* Get number of RX descriptors occupied by received packets */
710 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
711                                         struct mvneta_rx_queue *rxq)
712 {
713         u32 val;
714 
715         val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
716         return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
717 }
718 
719 /* Update num of rx desc called upon return from rx path or
720  * from mvneta_rxq_drop_pkts().
721  */
722 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
723                                        struct mvneta_rx_queue *rxq,
724                                        int rx_done, int rx_filled)
725 {
726         u32 val;
727 
728         if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
729                 val = rx_done |
730                   (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
731                 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
732                 return;
733         }
734 
735         /* Only 255 descriptors can be added at once */
736         while ((rx_done > 0) || (rx_filled > 0)) {
737                 if (rx_done <= 0xff) {
738                         val = rx_done;
739                         rx_done = 0;
740                 } else {
741                         val = 0xff;
742                         rx_done -= 0xff;
743                 }
744                 if (rx_filled <= 0xff) {
745                         val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
746                         rx_filled = 0;
747                 } else {
748                         val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
749                         rx_filled -= 0xff;
750                 }
751                 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
752         }
753 }
754 
755 /* Get pointer to next RX descriptor to be processed by SW */
756 static struct mvneta_rx_desc *
757 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
758 {
759         int rx_desc = rxq->next_desc_to_proc;
760 
761         rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
762         prefetch(rxq->descs + rxq->next_desc_to_proc);
763         return rxq->descs + rx_desc;
764 }
765 
766 /* Change maximum receive size of the port. */
767 static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
768 {
769         u32 val;
770 
771         val =  mvreg_read(pp, MVNETA_GMAC_CTRL_0);
772         val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
773         val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
774                 MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
775         mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
776 }
777 
778 
779 /* Set rx queue offset */
780 static void mvneta_rxq_offset_set(struct mvneta_port *pp,
781                                   struct mvneta_rx_queue *rxq,
782                                   int offset)
783 {
784         u32 val;
785 
786         val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
787         val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
788 
789         /* Offset is in */
790         val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
791         mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
792 }
793 
794 
795 /* Tx descriptors helper methods */
796 
797 /* Update HW with number of TX descriptors to be sent */
798 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
799                                      struct mvneta_tx_queue *txq,
800                                      int pend_desc)
801 {
802         u32 val;
803 
804         /* Only 255 descriptors can be added at once ; Assume caller
805          * process TX desriptors in quanta less than 256
806          */
807         val = pend_desc;
808         mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
809 }
810 
811 /* Get pointer to next TX descriptor to be processed (send) by HW */
812 static struct mvneta_tx_desc *
813 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
814 {
815         int tx_desc = txq->next_desc_to_proc;
816 
817         txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
818         return txq->descs + tx_desc;
819 }
820 
821 /* Release the last allocated TX descriptor. Useful to handle DMA
822  * mapping failures in the TX path.
823  */
824 static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq)
825 {
826         if (txq->next_desc_to_proc == 0)
827                 txq->next_desc_to_proc = txq->last_desc - 1;
828         else
829                 txq->next_desc_to_proc--;
830 }
831 
832 /* Set rxq buf size */
833 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
834                                     struct mvneta_rx_queue *rxq,
835                                     int buf_size)
836 {
837         u32 val;
838 
839         val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
840 
841         val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
842         val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
843 
844         mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
845 }
846 
847 /* Disable buffer management (BM) */
848 static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
849                                   struct mvneta_rx_queue *rxq)
850 {
851         u32 val;
852 
853         val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
854         val &= ~MVNETA_RXQ_HW_BUF_ALLOC;
855         mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
856 }
857 
858 /* Enable buffer management (BM) */
859 static void mvneta_rxq_bm_enable(struct mvneta_port *pp,
860                                  struct mvneta_rx_queue *rxq)
861 {
862         u32 val;
863 
864         val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
865         val |= MVNETA_RXQ_HW_BUF_ALLOC;
866         mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
867 }
868 
869 /* Notify HW about port's assignment of pool for bigger packets */
870 static void mvneta_rxq_long_pool_set(struct mvneta_port *pp,
871                                      struct mvneta_rx_queue *rxq)
872 {
873         u32 val;
874 
875         val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
876         val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK;
877         val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT);
878 
879         mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
880 }
881 
882 /* Notify HW about port's assignment of pool for smaller packets */
883 static void mvneta_rxq_short_pool_set(struct mvneta_port *pp,
884                                       struct mvneta_rx_queue *rxq)
885 {
886         u32 val;
887 
888         val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
889         val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK;
890         val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT);
891 
892         mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
893 }
894 
895 /* Set port's receive buffer size for assigned BM pool */
896 static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp,
897                                               int buf_size,
898                                               u8 pool_id)
899 {
900         u32 val;
901 
902         if (!IS_ALIGNED(buf_size, 8)) {
903                 dev_warn(pp->dev->dev.parent,
904                          "illegal buf_size value %d, round to %d\n",
905                          buf_size, ALIGN(buf_size, 8));
906                 buf_size = ALIGN(buf_size, 8);
907         }
908 
909         val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id));
910         val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK;
911         mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val);
912 }
913 
914 /* Configure MBUS window in order to enable access BM internal SRAM */
915 static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize,
916                                   u8 target, u8 attr)
917 {
918         u32 win_enable, win_protect;
919         int i;
920 
921         win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE);
922 
923         if (pp->bm_win_id < 0) {
924                 /* Find first not occupied window */
925                 for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) {
926                         if (win_enable & (1 << i)) {
927                                 pp->bm_win_id = i;
928                                 break;
929                         }
930                 }
931                 if (i == MVNETA_MAX_DECODE_WIN)
932                         return -ENOMEM;
933         } else {
934                 i = pp->bm_win_id;
935         }
936 
937         mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
938         mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
939 
940         if (i < 4)
941                 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
942 
943         mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) |
944                     (attr << 8) | target);
945 
946         mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000);
947 
948         win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE);
949         win_protect |= 3 << (2 * i);
950         mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
951 
952         win_enable &= ~(1 << i);
953         mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
954 
955         return 0;
956 }
957 
958 /* Assign and initialize pools for port. In case of fail
959  * buffer manager will remain disabled for current port.
960  */
961 static int mvneta_bm_port_init(struct platform_device *pdev,
962                                struct mvneta_port *pp)
963 {
964         struct device_node *dn = pdev->dev.of_node;
965         u32 long_pool_id, short_pool_id, wsize;
966         u8 target, attr;
967         int err;
968 
969         /* Get BM window information */
970         err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize,
971                                          &target, &attr);
972         if (err < 0)
973                 return err;
974 
975         pp->bm_win_id = -1;
976 
977         /* Open NETA -> BM window */
978         err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize,
979                                      target, attr);
980         if (err < 0) {
981                 netdev_info(pp->dev, "fail to configure mbus window to BM\n");
982                 return err;
983         }
984 
985         if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) {
986                 netdev_info(pp->dev, "missing long pool id\n");
987                 return -EINVAL;
988         }
989 
990         /* Create port's long pool depending on mtu */
991         pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id,
992                                            MVNETA_BM_LONG, pp->id,
993                                            MVNETA_RX_PKT_SIZE(pp->dev->mtu));
994         if (!pp->pool_long) {
995                 netdev_info(pp->dev, "fail to obtain long pool for port\n");
996                 return -ENOMEM;
997         }
998 
999         pp->pool_long->port_map |= 1 << pp->id;
1000 
1001         mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size,
1002                                    pp->pool_long->id);
1003 
1004         /* If short pool id is not defined, assume using single pool */
1005         if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id))
1006                 short_pool_id = long_pool_id;
1007 
1008         /* Create port's short pool */
1009         pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id,
1010                                             MVNETA_BM_SHORT, pp->id,
1011                                             MVNETA_BM_SHORT_PKT_SIZE);
1012         if (!pp->pool_short) {
1013                 netdev_info(pp->dev, "fail to obtain short pool for port\n");
1014                 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
1015                 return -ENOMEM;
1016         }
1017 
1018         if (short_pool_id != long_pool_id) {
1019                 pp->pool_short->port_map |= 1 << pp->id;
1020                 mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size,
1021                                            pp->pool_short->id);
1022         }
1023 
1024         return 0;
1025 }
1026 
1027 /* Update settings of a pool for bigger packets */
1028 static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu)
1029 {
1030         struct mvneta_bm_pool *bm_pool = pp->pool_long;
1031         struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool;
1032         int num;
1033 
1034         /* Release all buffers from long pool */
1035         mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id);
1036         if (hwbm_pool->buf_num) {
1037                 WARN(1, "cannot free all buffers in pool %d\n",
1038                      bm_pool->id);
1039                 goto bm_mtu_err;
1040         }
1041 
1042         bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu);
1043         bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size);
1044         hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
1045                         SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size));
1046 
1047         /* Fill entire long pool */
1048         num = hwbm_pool_add(hwbm_pool, hwbm_pool->size, GFP_ATOMIC);
1049         if (num != hwbm_pool->size) {
1050                 WARN(1, "pool %d: %d of %d allocated\n",
1051                      bm_pool->id, num, hwbm_pool->size);
1052                 goto bm_mtu_err;
1053         }
1054         mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id);
1055 
1056         return;
1057 
1058 bm_mtu_err:
1059         mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
1060         mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id);
1061 
1062         pp->bm_priv = NULL;
1063         mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1);
1064         netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n");
1065 }
1066 
1067 /* Start the Ethernet port RX and TX activity */
1068 static void mvneta_port_up(struct mvneta_port *pp)
1069 {
1070         int queue;
1071         u32 q_map;
1072 
1073         /* Enable all initialized TXs. */
1074         q_map = 0;
1075         for (queue = 0; queue < txq_number; queue++) {
1076                 struct mvneta_tx_queue *txq = &pp->txqs[queue];
1077                 if (txq->descs != NULL)
1078                         q_map |= (1 << queue);
1079         }
1080         mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
1081 
1082         /* Enable all initialized RXQs. */
1083         for (queue = 0; queue < rxq_number; queue++) {
1084                 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
1085 
1086                 if (rxq->descs != NULL)
1087                         q_map |= (1 << queue);
1088         }
1089         mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
1090 }
1091 
1092 /* Stop the Ethernet port activity */
1093 static void mvneta_port_down(struct mvneta_port *pp)
1094 {
1095         u32 val;
1096         int count;
1097 
1098         /* Stop Rx port activity. Check port Rx activity. */
1099         val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
1100 
1101         /* Issue stop command for active channels only */
1102         if (val != 0)
1103                 mvreg_write(pp, MVNETA_RXQ_CMD,
1104                             val << MVNETA_RXQ_DISABLE_SHIFT);
1105 
1106         /* Wait for all Rx activity to terminate. */
1107         count = 0;
1108         do {
1109                 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
1110                         netdev_warn(pp->dev,
1111                                     "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n",
1112                                     val);
1113                         break;
1114                 }
1115                 mdelay(1);
1116 
1117                 val = mvreg_read(pp, MVNETA_RXQ_CMD);
1118         } while (val & MVNETA_RXQ_ENABLE_MASK);
1119 
1120         /* Stop Tx port activity. Check port Tx activity. Issue stop
1121          * command for active channels only
1122          */
1123         val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
1124 
1125         if (val != 0)
1126                 mvreg_write(pp, MVNETA_TXQ_CMD,
1127                             (val << MVNETA_TXQ_DISABLE_SHIFT));
1128 
1129         /* Wait for all Tx activity to terminate. */
1130         count = 0;
1131         do {
1132                 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
1133                         netdev_warn(pp->dev,
1134                                     "TIMEOUT for TX stopped status=0x%08x\n",
1135                                     val);
1136                         break;
1137                 }
1138                 mdelay(1);
1139 
1140                 /* Check TX Command reg that all Txqs are stopped */
1141                 val = mvreg_read(pp, MVNETA_TXQ_CMD);
1142 
1143         } while (val & MVNETA_TXQ_ENABLE_MASK);
1144 
1145         /* Double check to verify that TX FIFO is empty */
1146         count = 0;
1147         do {
1148                 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
1149                         netdev_warn(pp->dev,
1150                                     "TX FIFO empty timeout status=0x%08x\n",
1151                                     val);
1152                         break;
1153                 }
1154                 mdelay(1);
1155 
1156                 val = mvreg_read(pp, MVNETA_PORT_STATUS);
1157         } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
1158                  (val & MVNETA_TX_IN_PRGRS));
1159 
1160         udelay(200);
1161 }
1162 
1163 /* Enable the port by setting the port enable bit of the MAC control register */
1164 static void mvneta_port_enable(struct mvneta_port *pp)
1165 {
1166         u32 val;
1167 
1168         /* Enable port */
1169         val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
1170         val |= MVNETA_GMAC0_PORT_ENABLE;
1171         mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
1172 }
1173 
1174 /* Disable the port and wait for about 200 usec before retuning */
1175 static void mvneta_port_disable(struct mvneta_port *pp)
1176 {
1177         u32 val;
1178 
1179         /* Reset the Enable bit in the Serial Control Register */
1180         val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
1181         val &= ~MVNETA_GMAC0_PORT_ENABLE;
1182         mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
1183 
1184         udelay(200);
1185 }
1186 
1187 /* Multicast tables methods */
1188 
1189 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
1190 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
1191 {
1192         int offset;
1193         u32 val;
1194 
1195         if (queue == -1) {
1196                 val = 0;
1197         } else {
1198                 val = 0x1 | (queue << 1);
1199                 val |= (val << 24) | (val << 16) | (val << 8);
1200         }
1201 
1202         for (offset = 0; offset <= 0xc; offset += 4)
1203                 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
1204 }
1205 
1206 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
1207 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
1208 {
1209         int offset;
1210         u32 val;
1211 
1212         if (queue == -1) {
1213                 val = 0;
1214         } else {
1215                 val = 0x1 | (queue << 1);
1216                 val |= (val << 24) | (val << 16) | (val << 8);
1217         }
1218 
1219         for (offset = 0; offset <= 0xfc; offset += 4)
1220                 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
1221 
1222 }
1223 
1224 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
1225 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
1226 {
1227         int offset;
1228         u32 val;
1229 
1230         if (queue == -1) {
1231                 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
1232                 val = 0;
1233         } else {
1234                 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
1235                 val = 0x1 | (queue << 1);
1236                 val |= (val << 24) | (val << 16) | (val << 8);
1237         }
1238 
1239         for (offset = 0; offset <= 0xfc; offset += 4)
1240                 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
1241 }
1242 
1243 static void mvneta_set_autoneg(struct mvneta_port *pp, int enable)
1244 {
1245         u32 val;
1246 
1247         if (enable) {
1248                 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1249                 val &= ~(MVNETA_GMAC_FORCE_LINK_PASS |
1250                          MVNETA_GMAC_FORCE_LINK_DOWN |
1251                          MVNETA_GMAC_AN_FLOW_CTRL_EN);
1252                 val |= MVNETA_GMAC_INBAND_AN_ENABLE |
1253                        MVNETA_GMAC_AN_SPEED_EN |
1254                        MVNETA_GMAC_AN_DUPLEX_EN;
1255                 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1256 
1257                 val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
1258                 val |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
1259                 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
1260 
1261                 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
1262                 val |= MVNETA_GMAC2_INBAND_AN_ENABLE;
1263                 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
1264         } else {
1265                 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1266                 val &= ~(MVNETA_GMAC_INBAND_AN_ENABLE |
1267                        MVNETA_GMAC_AN_SPEED_EN |
1268                        MVNETA_GMAC_AN_DUPLEX_EN);
1269                 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1270 
1271                 val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
1272                 val &= ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
1273                 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
1274 
1275                 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
1276                 val &= ~MVNETA_GMAC2_INBAND_AN_ENABLE;
1277                 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
1278         }
1279 }
1280 
1281 static void mvneta_percpu_unmask_interrupt(void *arg)
1282 {
1283         struct mvneta_port *pp = arg;
1284 
1285         /* All the queue are unmasked, but actually only the ones
1286          * mapped to this CPU will be unmasked
1287          */
1288         mvreg_write(pp, MVNETA_INTR_NEW_MASK,
1289                     MVNETA_RX_INTR_MASK_ALL |
1290                     MVNETA_TX_INTR_MASK_ALL |
1291                     MVNETA_MISCINTR_INTR_MASK);
1292 }
1293 
1294 static void mvneta_percpu_mask_interrupt(void *arg)
1295 {
1296         struct mvneta_port *pp = arg;
1297 
1298         /* All the queue are masked, but actually only the ones
1299          * mapped to this CPU will be masked
1300          */
1301         mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
1302         mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
1303         mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
1304 }
1305 
1306 static void mvneta_percpu_clear_intr_cause(void *arg)
1307 {
1308         struct mvneta_port *pp = arg;
1309 
1310         /* All the queue are cleared, but actually only the ones
1311          * mapped to this CPU will be cleared
1312          */
1313         mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
1314         mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
1315         mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
1316 }
1317 
1318 /* This method sets defaults to the NETA port:
1319  *      Clears interrupt Cause and Mask registers.
1320  *      Clears all MAC tables.
1321  *      Sets defaults to all registers.
1322  *      Resets RX and TX descriptor rings.
1323  *      Resets PHY.
1324  * This method can be called after mvneta_port_down() to return the port
1325  *      settings to defaults.
1326  */
1327 static void mvneta_defaults_set(struct mvneta_port *pp)
1328 {
1329         int cpu;
1330         int queue;
1331         u32 val;
1332         int max_cpu = num_present_cpus();
1333 
1334         /* Clear all Cause registers */
1335         on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
1336 
1337         /* Mask all interrupts */
1338         on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
1339         mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
1340 
1341         /* Enable MBUS Retry bit16 */
1342         mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
1343 
1344         /* Set CPU queue access map. CPUs are assigned to the RX and
1345          * TX queues modulo their number. If there is only one TX
1346          * queue then it is assigned to the CPU associated to the
1347          * default RX queue.
1348          */
1349         for_each_present_cpu(cpu) {
1350                 int rxq_map = 0, txq_map = 0;
1351                 int rxq, txq;
1352 
1353                 for (rxq = 0; rxq < rxq_number; rxq++)
1354                         if ((rxq % max_cpu) == cpu)
1355                                 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
1356 
1357                 for (txq = 0; txq < txq_number; txq++)
1358                         if ((txq % max_cpu) == cpu)
1359                                 txq_map |= MVNETA_CPU_TXQ_ACCESS(txq);
1360 
1361                 /* With only one TX queue we configure a special case
1362                  * which will allow to get all the irq on a single
1363                  * CPU
1364                  */
1365                 if (txq_number == 1)
1366                         txq_map = (cpu == pp->rxq_def) ?
1367                                 MVNETA_CPU_TXQ_ACCESS(1) : 0;
1368 
1369                 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
1370         }
1371 
1372         /* Reset RX and TX DMAs */
1373         mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
1374         mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
1375 
1376         /* Disable Legacy WRR, Disable EJP, Release from reset */
1377         mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
1378         for (queue = 0; queue < txq_number; queue++) {
1379                 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
1380                 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
1381         }
1382 
1383         mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
1384         mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
1385 
1386         /* Set Port Acceleration Mode */
1387         if (pp->bm_priv)
1388                 /* HW buffer management + legacy parser */
1389                 val = MVNETA_ACC_MODE_EXT2;
1390         else
1391                 /* SW buffer management + legacy parser */
1392                 val = MVNETA_ACC_MODE_EXT1;
1393         mvreg_write(pp, MVNETA_ACC_MODE, val);
1394 
1395         if (pp->bm_priv)
1396                 mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr);
1397 
1398         /* Update val of portCfg register accordingly with all RxQueue types */
1399         val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
1400         mvreg_write(pp, MVNETA_PORT_CONFIG, val);
1401 
1402         val = 0;
1403         mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
1404         mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
1405 
1406         /* Build PORT_SDMA_CONFIG_REG */
1407         val = 0;
1408 
1409         /* Default burst size */
1410         val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1411         val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1412         val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
1413 
1414 #if defined(__BIG_ENDIAN)
1415         val |= MVNETA_DESC_SWAP;
1416 #endif
1417 
1418         /* Assign port SDMA configuration */
1419         mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
1420 
1421         /* Disable PHY polling in hardware, since we're using the
1422          * kernel phylib to do this.
1423          */
1424         val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
1425         val &= ~MVNETA_PHY_POLLING_ENABLE;
1426         mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
1427 
1428         mvneta_set_autoneg(pp, pp->use_inband_status);
1429         mvneta_set_ucast_table(pp, -1);
1430         mvneta_set_special_mcast_table(pp, -1);
1431         mvneta_set_other_mcast_table(pp, -1);
1432 
1433         /* Set port interrupt enable register - default enable all */
1434         mvreg_write(pp, MVNETA_INTR_ENABLE,
1435                     (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
1436                      | MVNETA_TXQ_INTR_ENABLE_ALL_MASK));
1437 
1438         mvneta_mib_counters_clear(pp);
1439 }
1440 
1441 /* Set max sizes for tx queues */
1442 static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size)
1443 
1444 {
1445         u32 val, size, mtu;
1446         int queue;
1447 
1448         mtu = max_tx_size * 8;
1449         if (mtu > MVNETA_TX_MTU_MAX)
1450                 mtu = MVNETA_TX_MTU_MAX;
1451 
1452         /* Set MTU */
1453         val = mvreg_read(pp, MVNETA_TX_MTU);
1454         val &= ~MVNETA_TX_MTU_MAX;
1455         val |= mtu;
1456         mvreg_write(pp, MVNETA_TX_MTU, val);
1457 
1458         /* TX token size and all TXQs token size must be larger that MTU */
1459         val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
1460 
1461         size = val & MVNETA_TX_TOKEN_SIZE_MAX;
1462         if (size < mtu) {
1463                 size = mtu;
1464                 val &= ~MVNETA_TX_TOKEN_SIZE_MAX;
1465                 val |= size;
1466                 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
1467         }
1468         for (queue = 0; queue < txq_number; queue++) {
1469                 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
1470 
1471                 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX;
1472                 if (size < mtu) {
1473                         size = mtu;
1474                         val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX;
1475                         val |= size;
1476                         mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
1477                 }
1478         }
1479 }
1480 
1481 /* Set unicast address */
1482 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
1483                                   int queue)
1484 {
1485         unsigned int unicast_reg;
1486         unsigned int tbl_offset;
1487         unsigned int reg_offset;
1488 
1489         /* Locate the Unicast table entry */
1490         last_nibble = (0xf & last_nibble);
1491 
1492         /* offset from unicast tbl base */
1493         tbl_offset = (last_nibble / 4) * 4;
1494 
1495         /* offset within the above reg  */
1496         reg_offset = last_nibble % 4;
1497 
1498         unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
1499 
1500         if (queue == -1) {
1501                 /* Clear accepts frame bit at specified unicast DA tbl entry */
1502                 unicast_reg &= ~(0xff << (8 * reg_offset));
1503         } else {
1504                 unicast_reg &= ~(0xff << (8 * reg_offset));
1505                 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1506         }
1507 
1508         mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
1509 }
1510 
1511 /* Set mac address */
1512 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
1513                                 int queue)
1514 {
1515         unsigned int mac_h;
1516         unsigned int mac_l;
1517 
1518         if (queue != -1) {
1519                 mac_l = (addr[4] << 8) | (addr[5]);
1520                 mac_h = (addr[0] << 24) | (addr[1] << 16) |
1521                         (addr[2] << 8) | (addr[3] << 0);
1522 
1523                 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1524                 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1525         }
1526 
1527         /* Accept frames of this address */
1528         mvneta_set_ucast_addr(pp, addr[5], queue);
1529 }
1530 
1531 /* Set the number of packets that will be received before RX interrupt
1532  * will be generated by HW.
1533  */
1534 static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
1535                                     struct mvneta_rx_queue *rxq, u32 value)
1536 {
1537         mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1538                     value | MVNETA_RXQ_NON_OCCUPIED(0));
1539         rxq->pkts_coal = value;
1540 }
1541 
1542 /* Set the time delay in usec before RX interrupt will be generated by
1543  * HW.
1544  */
1545 static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
1546                                     struct mvneta_rx_queue *rxq, u32 value)
1547 {
1548         u32 val;
1549         unsigned long clk_rate;
1550 
1551         clk_rate = clk_get_rate(pp->clk);
1552         val = (clk_rate / 1000000) * value;
1553 
1554         mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1555         rxq->time_coal = value;
1556 }
1557 
1558 /* Set threshold for TX_DONE pkts coalescing */
1559 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp,
1560                                          struct mvneta_tx_queue *txq, u32 value)
1561 {
1562         u32 val;
1563 
1564         val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1565 
1566         val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK;
1567         val |= MVNETA_TXQ_SENT_THRESH_MASK(value);
1568 
1569         mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1570 
1571         txq->done_pkts_coal = value;
1572 }
1573 
1574 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1575 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
1576                                 u32 phys_addr, u32 cookie)
1577 {
1578         rx_desc->buf_cookie = cookie;
1579         rx_desc->buf_phys_addr = phys_addr;
1580 }
1581 
1582 /* Decrement sent descriptors counter */
1583 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
1584                                      struct mvneta_tx_queue *txq,
1585                                      int sent_desc)
1586 {
1587         u32 val;
1588 
1589         /* Only 255 TX descriptors can be updated at once */
1590         while (sent_desc > 0xff) {
1591                 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
1592                 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1593                 sent_desc = sent_desc - 0xff;
1594         }
1595 
1596         val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
1597         mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1598 }
1599 
1600 /* Get number of TX descriptors already sent by HW */
1601 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
1602                                         struct mvneta_tx_queue *txq)
1603 {
1604         u32 val;
1605         int sent_desc;
1606 
1607         val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
1608         sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
1609                 MVNETA_TXQ_SENT_DESC_SHIFT;
1610 
1611         return sent_desc;
1612 }
1613 
1614 /* Get number of sent descriptors and decrement counter.
1615  *  The number of sent descriptors is returned.
1616  */
1617 static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp,
1618                                      struct mvneta_tx_queue *txq)
1619 {
1620         int sent_desc;
1621 
1622         /* Get number of sent descriptors */
1623         sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1624 
1625         /* Decrement sent descriptors counter */
1626         if (sent_desc)
1627                 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1628 
1629         return sent_desc;
1630 }
1631 
1632 /* Set TXQ descriptors fields relevant for CSUM calculation */
1633 static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
1634                                 int ip_hdr_len, int l4_proto)
1635 {
1636         u32 command;
1637 
1638         /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1639          * G_L4_chk, L4_type; required only for checksum
1640          * calculation
1641          */
1642         command =  l3_offs    << MVNETA_TX_L3_OFF_SHIFT;
1643         command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT;
1644 
1645         if (l3_proto == htons(ETH_P_IP))
1646                 command |= MVNETA_TXD_IP_CSUM;
1647         else
1648                 command |= MVNETA_TX_L3_IP6;
1649 
1650         if (l4_proto == IPPROTO_TCP)
1651                 command |=  MVNETA_TX_L4_CSUM_FULL;
1652         else if (l4_proto == IPPROTO_UDP)
1653                 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL;
1654         else
1655                 command |= MVNETA_TX_L4_CSUM_NOT;
1656 
1657         return command;
1658 }
1659 
1660 
1661 /* Display more error info */
1662 static void mvneta_rx_error(struct mvneta_port *pp,
1663                             struct mvneta_rx_desc *rx_desc)
1664 {
1665         u32 status = rx_desc->status;
1666 
1667         if (!mvneta_rxq_desc_is_first_last(status)) {
1668                 netdev_err(pp->dev,
1669                            "bad rx status %08x (buffer oversize), size=%d\n",
1670                            status, rx_desc->data_size);
1671                 return;
1672         }
1673 
1674         switch (status & MVNETA_RXD_ERR_CODE_MASK) {
1675         case MVNETA_RXD_ERR_CRC:
1676                 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
1677                            status, rx_desc->data_size);
1678                 break;
1679         case MVNETA_RXD_ERR_OVERRUN:
1680                 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
1681                            status, rx_desc->data_size);
1682                 break;
1683         case MVNETA_RXD_ERR_LEN:
1684                 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
1685                            status, rx_desc->data_size);
1686                 break;
1687         case MVNETA_RXD_ERR_RESOURCE:
1688                 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
1689                            status, rx_desc->data_size);
1690                 break;
1691         }
1692 }
1693 
1694 /* Handle RX checksum offload based on the descriptor's status */
1695 static void mvneta_rx_csum(struct mvneta_port *pp, u32 status,
1696                            struct sk_buff *skb)
1697 {
1698         if ((status & MVNETA_RXD_L3_IP4) &&
1699             (status & MVNETA_RXD_L4_CSUM_OK)) {
1700                 skb->csum = 0;
1701                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1702                 return;
1703         }
1704 
1705         skb->ip_summed = CHECKSUM_NONE;
1706 }
1707 
1708 /* Return tx queue pointer (find last set bit) according to <cause> returned
1709  * form tx_done reg. <cause> must not be null. The return value is always a
1710  * valid queue for matching the first one found in <cause>.
1711  */
1712 static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp,
1713                                                      u32 cause)
1714 {
1715         int queue = fls(cause) - 1;
1716 
1717         return &pp->txqs[queue];
1718 }
1719 
1720 /* Free tx queue skbuffs */
1721 static void mvneta_txq_bufs_free(struct mvneta_port *pp,
1722                                  struct mvneta_tx_queue *txq, int num)
1723 {
1724         int i;
1725 
1726         for (i = 0; i < num; i++) {
1727                 struct mvneta_tx_desc *tx_desc = txq->descs +
1728                         txq->txq_get_index;
1729                 struct sk_buff *skb = txq->tx_skb[txq->txq_get_index];
1730 
1731                 mvneta_txq_inc_get(txq);
1732 
1733                 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
1734                         dma_unmap_single(pp->dev->dev.parent,
1735                                          tx_desc->buf_phys_addr,
1736                                          tx_desc->data_size, DMA_TO_DEVICE);
1737                 if (!skb)
1738                         continue;
1739                 dev_kfree_skb_any(skb);
1740         }
1741 }
1742 
1743 /* Handle end of transmission */
1744 static void mvneta_txq_done(struct mvneta_port *pp,
1745                            struct mvneta_tx_queue *txq)
1746 {
1747         struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
1748         int tx_done;
1749 
1750         tx_done = mvneta_txq_sent_desc_proc(pp, txq);
1751         if (!tx_done)
1752                 return;
1753 
1754         mvneta_txq_bufs_free(pp, txq, tx_done);
1755 
1756         txq->count -= tx_done;
1757 
1758         if (netif_tx_queue_stopped(nq)) {
1759                 if (txq->count <= txq->tx_wake_threshold)
1760                         netif_tx_wake_queue(nq);
1761         }
1762 }
1763 
1764 void *mvneta_frag_alloc(unsigned int frag_size)
1765 {
1766         if (likely(frag_size <= PAGE_SIZE))
1767                 return netdev_alloc_frag(frag_size);
1768         else
1769                 return kmalloc(frag_size, GFP_ATOMIC);
1770 }
1771 EXPORT_SYMBOL_GPL(mvneta_frag_alloc);
1772 
1773 void mvneta_frag_free(unsigned int frag_size, void *data)
1774 {
1775         if (likely(frag_size <= PAGE_SIZE))
1776                 skb_free_frag(data);
1777         else
1778                 kfree(data);
1779 }
1780 EXPORT_SYMBOL_GPL(mvneta_frag_free);
1781 
1782 /* Refill processing for SW buffer management */
1783 static int mvneta_rx_refill(struct mvneta_port *pp,
1784                             struct mvneta_rx_desc *rx_desc)
1785 
1786 {
1787         dma_addr_t phys_addr;
1788         void *data;
1789 
1790         data = mvneta_frag_alloc(pp->frag_size);
1791         if (!data)
1792                 return -ENOMEM;
1793 
1794         phys_addr = dma_map_single(pp->dev->dev.parent, data,
1795                                    MVNETA_RX_BUF_SIZE(pp->pkt_size),
1796                                    DMA_FROM_DEVICE);
1797         if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) {
1798                 mvneta_frag_free(pp->frag_size, data);
1799                 return -ENOMEM;
1800         }
1801 
1802         mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
1803         return 0;
1804 }
1805 
1806 /* Handle tx checksum */
1807 static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb)
1808 {
1809         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1810                 int ip_hdr_len = 0;
1811                 __be16 l3_proto = vlan_get_protocol(skb);
1812                 u8 l4_proto;
1813 
1814                 if (l3_proto == htons(ETH_P_IP)) {
1815                         struct iphdr *ip4h = ip_hdr(skb);
1816 
1817                         /* Calculate IPv4 checksum and L4 checksum */
1818                         ip_hdr_len = ip4h->ihl;
1819                         l4_proto = ip4h->protocol;
1820                 } else if (l3_proto == htons(ETH_P_IPV6)) {
1821                         struct ipv6hdr *ip6h = ipv6_hdr(skb);
1822 
1823                         /* Read l4_protocol from one of IPv6 extra headers */
1824                         if (skb_network_header_len(skb) > 0)
1825                                 ip_hdr_len = (skb_network_header_len(skb) >> 2);
1826                         l4_proto = ip6h->nexthdr;
1827                 } else
1828                         return MVNETA_TX_L4_CSUM_NOT;
1829 
1830                 return mvneta_txq_desc_csum(skb_network_offset(skb),
1831                                             l3_proto, ip_hdr_len, l4_proto);
1832         }
1833 
1834         return MVNETA_TX_L4_CSUM_NOT;
1835 }
1836 
1837 /* Drop packets received by the RXQ and free buffers */
1838 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
1839                                  struct mvneta_rx_queue *rxq)
1840 {
1841         int rx_done, i;
1842 
1843         rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1844         if (rx_done)
1845                 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1846 
1847         if (pp->bm_priv) {
1848                 for (i = 0; i < rx_done; i++) {
1849                         struct mvneta_rx_desc *rx_desc =
1850                                                   mvneta_rxq_next_desc_get(rxq);
1851                         u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
1852                         struct mvneta_bm_pool *bm_pool;
1853 
1854                         bm_pool = &pp->bm_priv->bm_pools[pool_id];
1855                         /* Return dropped buffer to the pool */
1856                         mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
1857                                               rx_desc->buf_phys_addr);
1858                 }
1859                 return;
1860         }
1861 
1862         for (i = 0; i < rxq->size; i++) {
1863                 struct mvneta_rx_desc *rx_desc = rxq->descs + i;
1864                 void *data = (void *)rx_desc->buf_cookie;
1865 
1866                 dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
1867                                  MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
1868                 mvneta_frag_free(pp->frag_size, data);
1869         }
1870 }
1871 
1872 /* Main rx processing when using software buffer management */
1873 static int mvneta_rx_swbm(struct mvneta_port *pp, int rx_todo,
1874                           struct mvneta_rx_queue *rxq)
1875 {
1876         struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
1877         struct net_device *dev = pp->dev;
1878         int rx_done;
1879         u32 rcvd_pkts = 0;
1880         u32 rcvd_bytes = 0;
1881 
1882         /* Get number of received packets */
1883         rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1884 
1885         if (rx_todo > rx_done)
1886                 rx_todo = rx_done;
1887 
1888         rx_done = 0;
1889 
1890         /* Fairness NAPI loop */
1891         while (rx_done < rx_todo) {
1892                 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
1893                 struct sk_buff *skb;
1894                 unsigned char *data;
1895                 dma_addr_t phys_addr;
1896                 u32 rx_status, frag_size;
1897                 int rx_bytes, err;
1898 
1899                 rx_done++;
1900                 rx_status = rx_desc->status;
1901                 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
1902                 data = (unsigned char *)rx_desc->buf_cookie;
1903                 phys_addr = rx_desc->buf_phys_addr;
1904 
1905                 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
1906                     (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1907 err_drop_frame:
1908                         dev->stats.rx_errors++;
1909                         mvneta_rx_error(pp, rx_desc);
1910                         /* leave the descriptor untouched */
1911                         continue;
1912                 }
1913 
1914                 if (rx_bytes <= rx_copybreak) {
1915                 /* better copy a small frame and not unmap the DMA region */
1916                         skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
1917                         if (unlikely(!skb))
1918                                 goto err_drop_frame;
1919 
1920                         dma_sync_single_range_for_cpu(dev->dev.parent,
1921                                                       rx_desc->buf_phys_addr,
1922                                                       MVNETA_MH_SIZE + NET_SKB_PAD,
1923                                                       rx_bytes,
1924                                                       DMA_FROM_DEVICE);
1925                         memcpy(skb_put(skb, rx_bytes),
1926                                data + MVNETA_MH_SIZE + NET_SKB_PAD,
1927                                rx_bytes);
1928 
1929                         skb->protocol = eth_type_trans(skb, dev);
1930                         mvneta_rx_csum(pp, rx_status, skb);
1931                         napi_gro_receive(&port->napi, skb);
1932 
1933                         rcvd_pkts++;
1934                         rcvd_bytes += rx_bytes;
1935 
1936                         /* leave the descriptor and buffer untouched */
1937                         continue;
1938                 }
1939 
1940                 /* Refill processing */
1941                 err = mvneta_rx_refill(pp, rx_desc);
1942                 if (err) {
1943                         netdev_err(dev, "Linux processing - Can't refill\n");
1944                         rxq->missed++;
1945                         goto err_drop_frame;
1946                 }
1947 
1948                 frag_size = pp->frag_size;
1949 
1950                 skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size);
1951 
1952                 /* After refill old buffer has to be unmapped regardless
1953                  * the skb is successfully built or not.
1954                  */
1955                 dma_unmap_single(dev->dev.parent, phys_addr,
1956                                  MVNETA_RX_BUF_SIZE(pp->pkt_size),
1957                                  DMA_FROM_DEVICE);
1958 
1959                 if (!skb)
1960                         goto err_drop_frame;
1961 
1962                 rcvd_pkts++;
1963                 rcvd_bytes += rx_bytes;
1964 
1965                 /* Linux processing */
1966                 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
1967                 skb_put(skb, rx_bytes);
1968 
1969                 skb->protocol = eth_type_trans(skb, dev);
1970 
1971                 mvneta_rx_csum(pp, rx_status, skb);
1972 
1973                 napi_gro_receive(&port->napi, skb);
1974         }
1975 
1976         if (rcvd_pkts) {
1977                 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1978 
1979                 u64_stats_update_begin(&stats->syncp);
1980                 stats->rx_packets += rcvd_pkts;
1981                 stats->rx_bytes   += rcvd_bytes;
1982                 u64_stats_update_end(&stats->syncp);
1983         }
1984 
1985         /* Update rxq management counters */
1986         mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1987 
1988         return rx_done;
1989 }
1990 
1991 /* Main rx processing when using hardware buffer management */
1992 static int mvneta_rx_hwbm(struct mvneta_port *pp, int rx_todo,
1993                           struct mvneta_rx_queue *rxq)
1994 {
1995         struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
1996         struct net_device *dev = pp->dev;
1997         int rx_done;
1998         u32 rcvd_pkts = 0;
1999         u32 rcvd_bytes = 0;
2000 
2001         /* Get number of received packets */
2002         rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
2003 
2004         if (rx_todo > rx_done)
2005                 rx_todo = rx_done;
2006 
2007         rx_done = 0;
2008 
2009         /* Fairness NAPI loop */
2010         while (rx_done < rx_todo) {
2011                 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
2012                 struct mvneta_bm_pool *bm_pool = NULL;
2013                 struct sk_buff *skb;
2014                 unsigned char *data;
2015                 dma_addr_t phys_addr;
2016                 u32 rx_status, frag_size;
2017                 int rx_bytes, err;
2018                 u8 pool_id;
2019 
2020                 rx_done++;
2021                 rx_status = rx_desc->status;
2022                 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
2023                 data = (unsigned char *)rx_desc->buf_cookie;
2024                 phys_addr = rx_desc->buf_phys_addr;
2025                 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
2026                 bm_pool = &pp->bm_priv->bm_pools[pool_id];
2027 
2028                 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
2029                     (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
2030 err_drop_frame_ret_pool:
2031                         /* Return the buffer to the pool */
2032                         mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
2033                                               rx_desc->buf_phys_addr);
2034 err_drop_frame:
2035                         dev->stats.rx_errors++;
2036                         mvneta_rx_error(pp, rx_desc);
2037                         /* leave the descriptor untouched */
2038                         continue;
2039                 }
2040 
2041                 if (rx_bytes <= rx_copybreak) {
2042                         /* better copy a small frame and not unmap the DMA region */
2043                         skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
2044                         if (unlikely(!skb))
2045                                 goto err_drop_frame_ret_pool;
2046 
2047                         dma_sync_single_range_for_cpu(dev->dev.parent,
2048                                                       rx_desc->buf_phys_addr,
2049                                                       MVNETA_MH_SIZE + NET_SKB_PAD,
2050                                                       rx_bytes,
2051                                                       DMA_FROM_DEVICE);
2052                         memcpy(skb_put(skb, rx_bytes),
2053                                data + MVNETA_MH_SIZE + NET_SKB_PAD,
2054                                rx_bytes);
2055 
2056                         skb->protocol = eth_type_trans(skb, dev);
2057                         mvneta_rx_csum(pp, rx_status, skb);
2058                         napi_gro_receive(&port->napi, skb);
2059 
2060                         rcvd_pkts++;
2061                         rcvd_bytes += rx_bytes;
2062 
2063                         /* Return the buffer to the pool */
2064                         mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
2065                                               rx_desc->buf_phys_addr);
2066 
2067                         /* leave the descriptor and buffer untouched */
2068                         continue;
2069                 }
2070 
2071                 /* Refill processing */
2072                 err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC);
2073                 if (err) {
2074                         netdev_err(dev, "Linux processing - Can't refill\n");
2075                         rxq->missed++;
2076                         goto err_drop_frame_ret_pool;
2077                 }
2078 
2079                 frag_size = bm_pool->hwbm_pool.frag_size;
2080 
2081                 skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size);
2082 
2083                 /* After refill old buffer has to be unmapped regardless
2084                  * the skb is successfully built or not.
2085                  */
2086                 dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr,
2087                                  bm_pool->buf_size, DMA_FROM_DEVICE);
2088                 if (!skb)
2089                         goto err_drop_frame;
2090 
2091                 rcvd_pkts++;
2092                 rcvd_bytes += rx_bytes;
2093 
2094                 /* Linux processing */
2095                 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
2096                 skb_put(skb, rx_bytes);
2097 
2098                 skb->protocol = eth_type_trans(skb, dev);
2099 
2100                 mvneta_rx_csum(pp, rx_status, skb);
2101 
2102                 napi_gro_receive(&port->napi, skb);
2103         }
2104 
2105         if (rcvd_pkts) {
2106                 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2107 
2108                 u64_stats_update_begin(&stats->syncp);
2109                 stats->rx_packets += rcvd_pkts;
2110                 stats->rx_bytes   += rcvd_bytes;
2111                 u64_stats_update_end(&stats->syncp);
2112         }
2113 
2114         /* Update rxq management counters */
2115         mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
2116 
2117         return rx_done;
2118 }
2119 
2120 static inline void
2121 mvneta_tso_put_hdr(struct sk_buff *skb,
2122                    struct mvneta_port *pp, struct mvneta_tx_queue *txq)
2123 {
2124         struct mvneta_tx_desc *tx_desc;
2125         int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2126 
2127         txq->tx_skb[txq->txq_put_index] = NULL;
2128         tx_desc = mvneta_txq_next_desc_get(txq);
2129         tx_desc->data_size = hdr_len;
2130         tx_desc->command = mvneta_skb_tx_csum(pp, skb);
2131         tx_desc->command |= MVNETA_TXD_F_DESC;
2132         tx_desc->buf_phys_addr = txq->tso_hdrs_phys +
2133                                  txq->txq_put_index * TSO_HEADER_SIZE;
2134         mvneta_txq_inc_put(txq);
2135 }
2136 
2137 static inline int
2138 mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq,
2139                     struct sk_buff *skb, char *data, int size,
2140                     bool last_tcp, bool is_last)
2141 {
2142         struct mvneta_tx_desc *tx_desc;
2143 
2144         tx_desc = mvneta_txq_next_desc_get(txq);
2145         tx_desc->data_size = size;
2146         tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data,
2147                                                 size, DMA_TO_DEVICE);
2148         if (unlikely(dma_mapping_error(dev->dev.parent,
2149                      tx_desc->buf_phys_addr))) {
2150                 mvneta_txq_desc_put(txq);
2151                 return -ENOMEM;
2152         }
2153 
2154         tx_desc->command = 0;
2155         txq->tx_skb[txq->txq_put_index] = NULL;
2156 
2157         if (last_tcp) {
2158                 /* last descriptor in the TCP packet */
2159                 tx_desc->command = MVNETA_TXD_L_DESC;
2160 
2161                 /* last descriptor in SKB */
2162                 if (is_last)
2163                         txq->tx_skb[txq->txq_put_index] = skb;
2164         }
2165         mvneta_txq_inc_put(txq);
2166         return 0;
2167 }
2168 
2169 static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev,
2170                          struct mvneta_tx_queue *txq)
2171 {
2172         int total_len, data_left;
2173         int desc_count = 0;
2174         struct mvneta_port *pp = netdev_priv(dev);
2175         struct tso_t tso;
2176         int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2177         int i;
2178 
2179         /* Count needed descriptors */
2180         if ((txq->count + tso_count_descs(skb)) >= txq->size)
2181                 return 0;
2182 
2183         if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) {
2184                 pr_info("*** Is this even  possible???!?!?\n");
2185                 return 0;
2186         }
2187 
2188         /* Initialize the TSO handler, and prepare the first payload */
2189         tso_start(skb, &tso);
2190 
2191         total_len = skb->len - hdr_len;
2192         while (total_len > 0) {
2193                 char *hdr;
2194 
2195                 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
2196                 total_len -= data_left;
2197                 desc_count++;
2198 
2199                 /* prepare packet headers: MAC + IP + TCP */
2200                 hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE;
2201                 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
2202 
2203                 mvneta_tso_put_hdr(skb, pp, txq);
2204 
2205                 while (data_left > 0) {
2206                         int size;
2207                         desc_count++;
2208 
2209                         size = min_t(int, tso.size, data_left);
2210 
2211                         if (mvneta_tso_put_data(dev, txq, skb,
2212                                                  tso.data, size,
2213                                                  size == data_left,
2214                                                  total_len == 0))
2215                                 goto err_release;
2216                         data_left -= size;
2217 
2218                         tso_build_data(skb, &tso, size);
2219                 }
2220         }
2221 
2222         return desc_count;
2223 
2224 err_release:
2225         /* Release all used data descriptors; header descriptors must not
2226          * be DMA-unmapped.
2227          */
2228         for (i = desc_count - 1; i >= 0; i--) {
2229                 struct mvneta_tx_desc *tx_desc = txq->descs + i;
2230                 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
2231                         dma_unmap_single(pp->dev->dev.parent,
2232                                          tx_desc->buf_phys_addr,
2233                                          tx_desc->data_size,
2234                                          DMA_TO_DEVICE);
2235                 mvneta_txq_desc_put(txq);
2236         }
2237         return 0;
2238 }
2239 
2240 /* Handle tx fragmentation processing */
2241 static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb,
2242                                   struct mvneta_tx_queue *txq)
2243 {
2244         struct mvneta_tx_desc *tx_desc;
2245         int i, nr_frags = skb_shinfo(skb)->nr_frags;
2246 
2247         for (i = 0; i < nr_frags; i++) {
2248                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2249                 void *addr = page_address(frag->page.p) + frag->page_offset;
2250 
2251                 tx_desc = mvneta_txq_next_desc_get(txq);
2252                 tx_desc->data_size = frag->size;
2253 
2254                 tx_desc->buf_phys_addr =
2255                         dma_map_single(pp->dev->dev.parent, addr,
2256                                        tx_desc->data_size, DMA_TO_DEVICE);
2257 
2258                 if (dma_mapping_error(pp->dev->dev.parent,
2259                                       tx_desc->buf_phys_addr)) {
2260                         mvneta_txq_desc_put(txq);
2261                         goto error;
2262                 }
2263 
2264                 if (i == nr_frags - 1) {
2265                         /* Last descriptor */
2266                         tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
2267                         txq->tx_skb[txq->txq_put_index] = skb;
2268                 } else {
2269                         /* Descriptor in the middle: Not First, Not Last */
2270                         tx_desc->command = 0;
2271                         txq->tx_skb[txq->txq_put_index] = NULL;
2272                 }
2273                 mvneta_txq_inc_put(txq);
2274         }
2275 
2276         return 0;
2277 
2278 error:
2279         /* Release all descriptors that were used to map fragments of
2280          * this packet, as well as the corresponding DMA mappings
2281          */
2282         for (i = i - 1; i >= 0; i--) {
2283                 tx_desc = txq->descs + i;
2284                 dma_unmap_single(pp->dev->dev.parent,
2285                                  tx_desc->buf_phys_addr,
2286                                  tx_desc->data_size,
2287                                  DMA_TO_DEVICE);
2288                 mvneta_txq_desc_put(txq);
2289         }
2290 
2291         return -ENOMEM;
2292 }
2293 
2294 /* Main tx processing */
2295 static int mvneta_tx(struct sk_buff *skb, struct net_device *dev)
2296 {
2297         struct mvneta_port *pp = netdev_priv(dev);
2298         u16 txq_id = skb_get_queue_mapping(skb);
2299         struct mvneta_tx_queue *txq = &pp->txqs[txq_id];
2300         struct mvneta_tx_desc *tx_desc;
2301         int len = skb->len;
2302         int frags = 0;
2303         u32 tx_cmd;
2304 
2305         if (!netif_running(dev))
2306                 goto out;
2307 
2308         if (skb_is_gso(skb)) {
2309                 frags = mvneta_tx_tso(skb, dev, txq);
2310                 goto out;
2311         }
2312 
2313         frags = skb_shinfo(skb)->nr_frags + 1;
2314 
2315         /* Get a descriptor for the first part of the packet */
2316         tx_desc = mvneta_txq_next_desc_get(txq);
2317 
2318         tx_cmd = mvneta_skb_tx_csum(pp, skb);
2319 
2320         tx_desc->data_size = skb_headlen(skb);
2321 
2322         tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
2323                                                 tx_desc->data_size,
2324                                                 DMA_TO_DEVICE);
2325         if (unlikely(dma_mapping_error(dev->dev.parent,
2326                                        tx_desc->buf_phys_addr))) {
2327                 mvneta_txq_desc_put(txq);
2328                 frags = 0;
2329                 goto out;
2330         }
2331 
2332         if (frags == 1) {
2333                 /* First and Last descriptor */
2334                 tx_cmd |= MVNETA_TXD_FLZ_DESC;
2335                 tx_desc->command = tx_cmd;
2336                 txq->tx_skb[txq->txq_put_index] = skb;
2337                 mvneta_txq_inc_put(txq);
2338         } else {
2339                 /* First but not Last */
2340                 tx_cmd |= MVNETA_TXD_F_DESC;
2341                 txq->tx_skb[txq->txq_put_index] = NULL;
2342                 mvneta_txq_inc_put(txq);
2343                 tx_desc->command = tx_cmd;
2344                 /* Continue with other skb fragments */
2345                 if (mvneta_tx_frag_process(pp, skb, txq)) {
2346                         dma_unmap_single(dev->dev.parent,
2347                                          tx_desc->buf_phys_addr,
2348                                          tx_desc->data_size,
2349                                          DMA_TO_DEVICE);
2350                         mvneta_txq_desc_put(txq);
2351                         frags = 0;
2352                         goto out;
2353                 }
2354         }
2355 
2356 out:
2357         if (frags > 0) {
2358                 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2359                 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
2360 
2361                 txq->count += frags;
2362                 mvneta_txq_pend_desc_add(pp, txq, frags);
2363 
2364                 if (txq->count >= txq->tx_stop_threshold)
2365                         netif_tx_stop_queue(nq);
2366 
2367                 u64_stats_update_begin(&stats->syncp);
2368                 stats->tx_packets++;
2369                 stats->tx_bytes  += len;
2370                 u64_stats_update_end(&stats->syncp);
2371         } else {
2372                 dev->stats.tx_dropped++;
2373                 dev_kfree_skb_any(skb);
2374         }
2375 
2376         return NETDEV_TX_OK;
2377 }
2378 
2379 
2380 /* Free tx resources, when resetting a port */
2381 static void mvneta_txq_done_force(struct mvneta_port *pp,
2382                                   struct mvneta_tx_queue *txq)
2383 
2384 {
2385         int tx_done = txq->count;
2386 
2387         mvneta_txq_bufs_free(pp, txq, tx_done);
2388 
2389         /* reset txq */
2390         txq->count = 0;
2391         txq->txq_put_index = 0;
2392         txq->txq_get_index = 0;
2393 }
2394 
2395 /* Handle tx done - called in softirq context. The <cause_tx_done> argument
2396  * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL.
2397  */
2398 static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done)
2399 {
2400         struct mvneta_tx_queue *txq;
2401         struct netdev_queue *nq;
2402 
2403         while (cause_tx_done) {
2404                 txq = mvneta_tx_done_policy(pp, cause_tx_done);
2405 
2406                 nq = netdev_get_tx_queue(pp->dev, txq->id);
2407                 __netif_tx_lock(nq, smp_processor_id());
2408 
2409                 if (txq->count)
2410                         mvneta_txq_done(pp, txq);
2411 
2412                 __netif_tx_unlock(nq);
2413                 cause_tx_done &= ~((1 << txq->id));
2414         }
2415 }
2416 
2417 /* Compute crc8 of the specified address, using a unique algorithm ,
2418  * according to hw spec, different than generic crc8 algorithm
2419  */
2420 static int mvneta_addr_crc(unsigned char *addr)
2421 {
2422         int crc = 0;
2423         int i;
2424 
2425         for (i = 0; i < ETH_ALEN; i++) {
2426                 int j;
2427 
2428                 crc = (crc ^ addr[i]) << 8;
2429                 for (j = 7; j >= 0; j--) {
2430                         if (crc & (0x100 << j))
2431                                 crc ^= 0x107 << j;
2432                 }
2433         }
2434 
2435         return crc;
2436 }
2437 
2438 /* This method controls the net device special MAC multicast support.
2439  * The Special Multicast Table for MAC addresses supports MAC of the form
2440  * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2441  * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2442  * Table entries in the DA-Filter table. This method set the Special
2443  * Multicast Table appropriate entry.
2444  */
2445 static void mvneta_set_special_mcast_addr(struct mvneta_port *pp,
2446                                           unsigned char last_byte,
2447                                           int queue)
2448 {
2449         unsigned int smc_table_reg;
2450         unsigned int tbl_offset;
2451         unsigned int reg_offset;
2452 
2453         /* Register offset from SMC table base    */
2454         tbl_offset = (last_byte / 4);
2455         /* Entry offset within the above reg */
2456         reg_offset = last_byte % 4;
2457 
2458         smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
2459                                         + tbl_offset * 4));
2460 
2461         if (queue == -1)
2462                 smc_table_reg &= ~(0xff << (8 * reg_offset));
2463         else {
2464                 smc_table_reg &= ~(0xff << (8 * reg_offset));
2465                 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
2466         }
2467 
2468         mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
2469                     smc_table_reg);
2470 }
2471 
2472 /* This method controls the network device Other MAC multicast support.
2473  * The Other Multicast Table is used for multicast of another type.
2474  * A CRC-8 is used as an index to the Other Multicast Table entries
2475  * in the DA-Filter table.
2476  * The method gets the CRC-8 value from the calling routine and
2477  * sets the Other Multicast Table appropriate entry according to the
2478  * specified CRC-8 .
2479  */
2480 static void mvneta_set_other_mcast_addr(struct mvneta_port *pp,
2481                                         unsigned char crc8,
2482                                         int queue)
2483 {
2484         unsigned int omc_table_reg;
2485         unsigned int tbl_offset;
2486         unsigned int reg_offset;
2487 
2488         tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
2489         reg_offset = crc8 % 4;       /* Entry offset within the above reg   */
2490 
2491         omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
2492 
2493         if (queue == -1) {
2494                 /* Clear accepts frame bit at specified Other DA table entry */
2495                 omc_table_reg &= ~(0xff << (8 * reg_offset));
2496         } else {
2497                 omc_table_reg &= ~(0xff << (8 * reg_offset));
2498                 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
2499         }
2500 
2501         mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
2502 }
2503 
2504 /* The network device supports multicast using two tables:
2505  *    1) Special Multicast Table for MAC addresses of the form
2506  *       0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2507  *       The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2508  *       Table entries in the DA-Filter table.
2509  *    2) Other Multicast Table for multicast of another type. A CRC-8 value
2510  *       is used as an index to the Other Multicast Table entries in the
2511  *       DA-Filter table.
2512  */
2513 static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr,
2514                                  int queue)
2515 {
2516         unsigned char crc_result = 0;
2517 
2518         if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) {
2519                 mvneta_set_special_mcast_addr(pp, p_addr[5], queue);
2520                 return 0;
2521         }
2522 
2523         crc_result = mvneta_addr_crc(p_addr);
2524         if (queue == -1) {
2525                 if (pp->mcast_count[crc_result] == 0) {
2526                         netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n",
2527                                     crc_result);
2528                         return -EINVAL;
2529                 }
2530 
2531                 pp->mcast_count[crc_result]--;
2532                 if (pp->mcast_count[crc_result] != 0) {
2533                         netdev_info(pp->dev,
2534                                     "After delete there are %d valid Mcast for crc8=0x%02x\n",
2535                                     pp->mcast_count[crc_result], crc_result);
2536                         return -EINVAL;
2537                 }
2538         } else
2539                 pp->mcast_count[crc_result]++;
2540 
2541         mvneta_set_other_mcast_addr(pp, crc_result, queue);
2542 
2543         return 0;
2544 }
2545 
2546 /* Configure Fitering mode of Ethernet port */
2547 static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp,
2548                                           int is_promisc)
2549 {
2550         u32 port_cfg_reg, val;
2551 
2552         port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
2553 
2554         val = mvreg_read(pp, MVNETA_TYPE_PRIO);
2555 
2556         /* Set / Clear UPM bit in port configuration register */
2557         if (is_promisc) {
2558                 /* Accept all Unicast addresses */
2559                 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE;
2560                 val |= MVNETA_FORCE_UNI;
2561                 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
2562                 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
2563         } else {
2564                 /* Reject all Unicast addresses */
2565                 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE;
2566                 val &= ~MVNETA_FORCE_UNI;
2567         }
2568 
2569         mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
2570         mvreg_write(pp, MVNETA_TYPE_PRIO, val);
2571 }
2572 
2573 /* register unicast and multicast addresses */
2574 static void mvneta_set_rx_mode(struct net_device *dev)
2575 {
2576         struct mvneta_port *pp = netdev_priv(dev);
2577         struct netdev_hw_addr *ha;
2578 
2579         if (dev->flags & IFF_PROMISC) {
2580                 /* Accept all: Multicast + Unicast */
2581                 mvneta_rx_unicast_promisc_set(pp, 1);
2582                 mvneta_set_ucast_table(pp, pp->rxq_def);
2583                 mvneta_set_special_mcast_table(pp, pp->rxq_def);
2584                 mvneta_set_other_mcast_table(pp, pp->rxq_def);
2585         } else {
2586                 /* Accept single Unicast */
2587                 mvneta_rx_unicast_promisc_set(pp, 0);
2588                 mvneta_set_ucast_table(pp, -1);
2589                 mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def);
2590 
2591                 if (dev->flags & IFF_ALLMULTI) {
2592                         /* Accept all multicast */
2593                         mvneta_set_special_mcast_table(pp, pp->rxq_def);
2594                         mvneta_set_other_mcast_table(pp, pp->rxq_def);
2595                 } else {
2596                         /* Accept only initialized multicast */
2597                         mvneta_set_special_mcast_table(pp, -1);
2598                         mvneta_set_other_mcast_table(pp, -1);
2599 
2600                         if (!netdev_mc_empty(dev)) {
2601                                 netdev_for_each_mc_addr(ha, dev) {
2602                                         mvneta_mcast_addr_set(pp, ha->addr,
2603                                                               pp->rxq_def);
2604                                 }
2605                         }
2606                 }
2607         }
2608 }
2609 
2610 /* Interrupt handling - the callback for request_irq() */
2611 static irqreturn_t mvneta_isr(int irq, void *dev_id)
2612 {
2613         struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id;
2614 
2615         disable_percpu_irq(port->pp->dev->irq);
2616         napi_schedule(&port->napi);
2617 
2618         return IRQ_HANDLED;
2619 }
2620 
2621 static int mvneta_fixed_link_update(struct mvneta_port *pp,
2622                                     struct phy_device *phy)
2623 {
2624         struct fixed_phy_status status;
2625         struct fixed_phy_status changed = {};
2626         u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
2627 
2628         status.link = !!(gmac_stat & MVNETA_GMAC_LINK_UP);
2629         if (gmac_stat & MVNETA_GMAC_SPEED_1000)
2630                 status.speed = SPEED_1000;
2631         else if (gmac_stat & MVNETA_GMAC_SPEED_100)
2632                 status.speed = SPEED_100;
2633         else
2634                 status.speed = SPEED_10;
2635         status.duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX);
2636         changed.link = 1;
2637         changed.speed = 1;
2638         changed.duplex = 1;
2639         fixed_phy_update_state(phy, &status, &changed);
2640         return 0;
2641 }
2642 
2643 /* NAPI handler
2644  * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
2645  * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
2646  * Bits 8 -15 of the cause Rx Tx register indicate that are received
2647  * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
2648  * Each CPU has its own causeRxTx register
2649  */
2650 static int mvneta_poll(struct napi_struct *napi, int budget)
2651 {
2652         int rx_done = 0;
2653         u32 cause_rx_tx;
2654         int rx_queue;
2655         struct mvneta_port *pp = netdev_priv(napi->dev);
2656         struct net_device *ndev = pp->dev;
2657         struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
2658 
2659         if (!netif_running(pp->dev)) {
2660                 napi_complete(&port->napi);
2661                 return rx_done;
2662         }
2663 
2664         /* Read cause register */
2665         cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE);
2666         if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) {
2667                 u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE);
2668 
2669                 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
2670                 if (pp->use_inband_status && (cause_misc &
2671                                 (MVNETA_CAUSE_PHY_STATUS_CHANGE |
2672                                  MVNETA_CAUSE_LINK_CHANGE |
2673                                  MVNETA_CAUSE_PSC_SYNC_CHANGE))) {
2674                         mvneta_fixed_link_update(pp, ndev->phydev);
2675                 }
2676         }
2677 
2678         /* Release Tx descriptors */
2679         if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) {
2680                 mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL));
2681                 cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL;
2682         }
2683 
2684         /* For the case where the last mvneta_poll did not process all
2685          * RX packets
2686          */
2687         rx_queue = fls(((cause_rx_tx >> 8) & 0xff));
2688 
2689         cause_rx_tx |= port->cause_rx_tx;
2690 
2691         if (rx_queue) {
2692                 rx_queue = rx_queue - 1;
2693                 if (pp->bm_priv)
2694                         rx_done = mvneta_rx_hwbm(pp, budget, &pp->rxqs[rx_queue]);
2695                 else
2696                         rx_done = mvneta_rx_swbm(pp, budget, &pp->rxqs[rx_queue]);
2697         }
2698 
2699         budget -= rx_done;
2700 
2701         if (budget > 0) {
2702                 cause_rx_tx = 0;
2703                 napi_complete(&port->napi);
2704                 enable_percpu_irq(pp->dev->irq, 0);
2705         }
2706 
2707         port->cause_rx_tx = cause_rx_tx;
2708         return rx_done;
2709 }
2710 
2711 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
2712 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
2713                            int num)
2714 {
2715         int i;
2716 
2717         for (i = 0; i < num; i++) {
2718                 memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc));
2719                 if (mvneta_rx_refill(pp, rxq->descs + i) != 0) {
2720                         netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs  filled\n",
2721                                 __func__, rxq->id, i, num);
2722                         break;
2723                 }
2724         }
2725 
2726         /* Add this number of RX descriptors as non occupied (ready to
2727          * get packets)
2728          */
2729         mvneta_rxq_non_occup_desc_add(pp, rxq, i);
2730 
2731         return i;
2732 }
2733 
2734 /* Free all packets pending transmit from all TXQs and reset TX port */
2735 static void mvneta_tx_reset(struct mvneta_port *pp)
2736 {
2737         int queue;
2738 
2739         /* free the skb's in the tx ring */
2740         for (queue = 0; queue < txq_number; queue++)
2741                 mvneta_txq_done_force(pp, &pp->txqs[queue]);
2742 
2743         mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
2744         mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
2745 }
2746 
2747 static void mvneta_rx_reset(struct mvneta_port *pp)
2748 {
2749         mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
2750         mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
2751 }
2752 
2753 /* Rx/Tx queue initialization/cleanup methods */
2754 
2755 /* Create a specified RX queue */
2756 static int mvneta_rxq_init(struct mvneta_port *pp,
2757                            struct mvneta_rx_queue *rxq)
2758 
2759 {
2760         rxq->size = pp->rx_ring_size;
2761 
2762         /* Allocate memory for RX descriptors */
2763         rxq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2764                                         rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2765                                         &rxq->descs_phys, GFP_KERNEL);
2766         if (rxq->descs == NULL)
2767                 return -ENOMEM;
2768 
2769         rxq->last_desc = rxq->size - 1;
2770 
2771         /* Set Rx descriptors queue starting address */
2772         mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
2773         mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
2774 
2775         /* Set Offset */
2776         mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD);
2777 
2778         /* Set coalescing pkts and time */
2779         mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2780         mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2781 
2782         if (!pp->bm_priv) {
2783                 /* Fill RXQ with buffers from RX pool */
2784                 mvneta_rxq_buf_size_set(pp, rxq,
2785                                         MVNETA_RX_BUF_SIZE(pp->pkt_size));
2786                 mvneta_rxq_bm_disable(pp, rxq);
2787         } else {
2788                 mvneta_rxq_bm_enable(pp, rxq);
2789                 mvneta_rxq_long_pool_set(pp, rxq);
2790                 mvneta_rxq_short_pool_set(pp, rxq);
2791         }
2792 
2793         mvneta_rxq_fill(pp, rxq, rxq->size);
2794 
2795         return 0;
2796 }
2797 
2798 /* Cleanup Rx queue */
2799 static void mvneta_rxq_deinit(struct mvneta_port *pp,
2800                               struct mvneta_rx_queue *rxq)
2801 {
2802         mvneta_rxq_drop_pkts(pp, rxq);
2803 
2804         if (rxq->descs)
2805                 dma_free_coherent(pp->dev->dev.parent,
2806                                   rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2807                                   rxq->descs,
2808                                   rxq->descs_phys);
2809 
2810         rxq->descs             = NULL;
2811         rxq->last_desc         = 0;
2812         rxq->next_desc_to_proc = 0;
2813         rxq->descs_phys        = 0;
2814 }
2815 
2816 /* Create and initialize a tx queue */
2817 static int mvneta_txq_init(struct mvneta_port *pp,
2818                            struct mvneta_tx_queue *txq)
2819 {
2820         int cpu;
2821 
2822         txq->size = pp->tx_ring_size;
2823 
2824         /* A queue must always have room for at least one skb.
2825          * Therefore, stop the queue when the free entries reaches
2826          * the maximum number of descriptors per skb.
2827          */
2828         txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS;
2829         txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
2830 
2831 
2832         /* Allocate memory for TX descriptors */
2833         txq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2834                                         txq->size * MVNETA_DESC_ALIGNED_SIZE,
2835                                         &txq->descs_phys, GFP_KERNEL);
2836         if (txq->descs == NULL)
2837                 return -ENOMEM;
2838 
2839         txq->last_desc = txq->size - 1;
2840 
2841         /* Set maximum bandwidth for enabled TXQs */
2842         mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
2843         mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
2844 
2845         /* Set Tx descriptors queue starting address */
2846         mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
2847         mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
2848 
2849         txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL);
2850         if (txq->tx_skb == NULL) {
2851                 dma_free_coherent(pp->dev->dev.parent,
2852                                   txq->size * MVNETA_DESC_ALIGNED_SIZE,
2853                                   txq->descs, txq->descs_phys);
2854                 return -ENOMEM;
2855         }
2856 
2857         /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2858         txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent,
2859                                            txq->size * TSO_HEADER_SIZE,
2860                                            &txq->tso_hdrs_phys, GFP_KERNEL);
2861         if (txq->tso_hdrs == NULL) {
2862                 kfree(txq->tx_skb);
2863                 dma_free_coherent(pp->dev->dev.parent,
2864                                   txq->size * MVNETA_DESC_ALIGNED_SIZE,
2865                                   txq->descs, txq->descs_phys);
2866                 return -ENOMEM;
2867         }
2868         mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2869 
2870         /* Setup XPS mapping */
2871         if (txq_number > 1)
2872                 cpu = txq->id % num_present_cpus();
2873         else
2874                 cpu = pp->rxq_def % num_present_cpus();
2875         cpumask_set_cpu(cpu, &txq->affinity_mask);
2876         netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id);
2877 
2878         return 0;
2879 }
2880 
2881 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
2882 static void mvneta_txq_deinit(struct mvneta_port *pp,
2883                               struct mvneta_tx_queue *txq)
2884 {
2885         kfree(txq->tx_skb);
2886 
2887         if (txq->tso_hdrs)
2888                 dma_free_coherent(pp->dev->dev.parent,
2889                                   txq->size * TSO_HEADER_SIZE,
2890                                   txq->tso_hdrs, txq->tso_hdrs_phys);
2891         if (txq->descs)
2892                 dma_free_coherent(pp->dev->dev.parent,
2893                                   txq->size * MVNETA_DESC_ALIGNED_SIZE,
2894                                   txq->descs, txq->descs_phys);
2895 
2896         txq->descs             = NULL;
2897         txq->last_desc         = 0;
2898         txq->next_desc_to_proc = 0;
2899         txq->descs_phys        = 0;
2900 
2901         /* Set minimum bandwidth for disabled TXQs */
2902         mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
2903         mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
2904 
2905         /* Set Tx descriptors queue starting address and size */
2906         mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
2907         mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
2908 }
2909 
2910 /* Cleanup all Tx queues */
2911 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
2912 {
2913         int queue;
2914 
2915         for (queue = 0; queue < txq_number; queue++)
2916                 mvneta_txq_deinit(pp, &pp->txqs[queue]);
2917 }
2918 
2919 /* Cleanup all Rx queues */
2920 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
2921 {
2922         int queue;
2923 
2924         for (queue = 0; queue < txq_number; queue++)
2925                 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
2926 }
2927 
2928 
2929 /* Init all Rx queues */
2930 static int mvneta_setup_rxqs(struct mvneta_port *pp)
2931 {
2932         int queue;
2933 
2934         for (queue = 0; queue < rxq_number; queue++) {
2935                 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
2936 
2937                 if (err) {
2938                         netdev_err(pp->dev, "%s: can't create rxq=%d\n",
2939                                    __func__, queue);
2940                         mvneta_cleanup_rxqs(pp);
2941                         return err;
2942                 }
2943         }
2944 
2945         return 0;
2946 }
2947 
2948 /* Init all tx queues */
2949 static int mvneta_setup_txqs(struct mvneta_port *pp)
2950 {
2951         int queue;
2952 
2953         for (queue = 0; queue < txq_number; queue++) {
2954                 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
2955                 if (err) {
2956                         netdev_err(pp->dev, "%s: can't create txq=%d\n",
2957                                    __func__, queue);
2958                         mvneta_cleanup_txqs(pp);
2959                         return err;
2960                 }
2961         }
2962 
2963         return 0;
2964 }
2965 
2966 static void mvneta_start_dev(struct mvneta_port *pp)
2967 {
2968         int cpu;
2969         struct net_device *ndev = pp->dev;
2970 
2971         mvneta_max_rx_size_set(pp, pp->pkt_size);
2972         mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
2973 
2974         /* start the Rx/Tx activity */
2975         mvneta_port_enable(pp);
2976 
2977         /* Enable polling on the port */
2978         for_each_online_cpu(cpu) {
2979                 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
2980 
2981                 napi_enable(&port->napi);
2982         }
2983 
2984         /* Unmask interrupts. It has to be done from each CPU */
2985         on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
2986 
2987         mvreg_write(pp, MVNETA_INTR_MISC_MASK,
2988                     MVNETA_CAUSE_PHY_STATUS_CHANGE |
2989                     MVNETA_CAUSE_LINK_CHANGE |
2990                     MVNETA_CAUSE_PSC_SYNC_CHANGE);
2991 
2992         phy_start(ndev->phydev);
2993         netif_tx_start_all_queues(pp->dev);
2994 }
2995 
2996 static void mvneta_stop_dev(struct mvneta_port *pp)
2997 {
2998         unsigned int cpu;
2999         struct net_device *ndev = pp->dev;
3000 
3001         phy_stop(ndev->phydev);
3002 
3003         for_each_online_cpu(cpu) {
3004                 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
3005 
3006                 napi_disable(&port->napi);
3007         }
3008 
3009         netif_carrier_off(pp->dev);
3010 
3011         mvneta_port_down(pp);
3012         netif_tx_stop_all_queues(pp->dev);
3013 
3014         /* Stop the port activity */
3015         mvneta_port_disable(pp);
3016 
3017         /* Clear all ethernet port interrupts */
3018         on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
3019 
3020         /* Mask all ethernet port interrupts */
3021         on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3022 
3023         mvneta_tx_reset(pp);
3024         mvneta_rx_reset(pp);
3025 }
3026 
3027 /* Return positive if MTU is valid */
3028 static int mvneta_check_mtu_valid(struct net_device *dev, int mtu)
3029 {
3030         if (mtu < 68) {
3031                 netdev_err(dev, "cannot change mtu to less than 68\n");
3032                 return -EINVAL;
3033         }
3034 
3035         /* 9676 == 9700 - 20 and rounding to 8 */
3036         if (mtu > 9676) {
3037                 netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu);
3038                 mtu = 9676;
3039         }
3040 
3041         if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
3042                 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n",
3043                         mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8));
3044                 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8);
3045         }
3046 
3047         return mtu;
3048 }
3049 
3050 static void mvneta_percpu_enable(void *arg)
3051 {
3052         struct mvneta_port *pp = arg;
3053 
3054         enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE);
3055 }
3056 
3057 static void mvneta_percpu_disable(void *arg)
3058 {
3059         struct mvneta_port *pp = arg;
3060 
3061         disable_percpu_irq(pp->dev->irq);
3062 }
3063 
3064 /* Change the device mtu */
3065 static int mvneta_change_mtu(struct net_device *dev, int mtu)
3066 {
3067         struct mvneta_port *pp = netdev_priv(dev);
3068         int ret;
3069 
3070         mtu = mvneta_check_mtu_valid(dev, mtu);
3071         if (mtu < 0)
3072                 return -EINVAL;
3073 
3074         dev->mtu = mtu;
3075 
3076         if (!netif_running(dev)) {
3077                 if (pp->bm_priv)
3078                         mvneta_bm_update_mtu(pp, mtu);
3079 
3080                 netdev_update_features(dev);
3081                 return 0;
3082         }
3083 
3084         /* The interface is running, so we have to force a
3085          * reallocation of the queues
3086          */
3087         mvneta_stop_dev(pp);
3088         on_each_cpu(mvneta_percpu_disable, pp, true);
3089 
3090         mvneta_cleanup_txqs(pp);
3091         mvneta_cleanup_rxqs(pp);
3092 
3093         if (pp->bm_priv)
3094                 mvneta_bm_update_mtu(pp, mtu);
3095 
3096         pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu);
3097         pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
3098                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3099 
3100         ret = mvneta_setup_rxqs(pp);
3101         if (ret) {
3102                 netdev_err(dev, "unable to setup rxqs after MTU change\n");
3103                 return ret;
3104         }
3105 
3106         ret = mvneta_setup_txqs(pp);
3107         if (ret) {
3108                 netdev_err(dev, "unable to setup txqs after MTU change\n");
3109                 return ret;
3110         }
3111 
3112         on_each_cpu(mvneta_percpu_enable, pp, true);
3113         mvneta_start_dev(pp);
3114         mvneta_port_up(pp);
3115 
3116         netdev_update_features(dev);
3117 
3118         return 0;
3119 }
3120 
3121 static netdev_features_t mvneta_fix_features(struct net_device *dev,
3122                                              netdev_features_t features)
3123 {
3124         struct mvneta_port *pp = netdev_priv(dev);
3125 
3126         if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) {
3127                 features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO);
3128                 netdev_info(dev,
3129                             "Disable IP checksum for MTU greater than %dB\n",
3130                             pp->tx_csum_limit);
3131         }
3132 
3133         return features;
3134 }
3135 
3136 /* Get mac address */
3137 static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr)
3138 {
3139         u32 mac_addr_l, mac_addr_h;
3140 
3141         mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
3142         mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
3143         addr[0] = (mac_addr_h >> 24) & 0xFF;
3144         addr[1] = (mac_addr_h >> 16) & 0xFF;
3145         addr[2] = (mac_addr_h >> 8) & 0xFF;
3146         addr[3] = mac_addr_h & 0xFF;
3147         addr[4] = (mac_addr_l >> 8) & 0xFF;
3148         addr[5] = mac_addr_l & 0xFF;
3149 }
3150 
3151 /* Handle setting mac address */
3152 static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
3153 {
3154         struct mvneta_port *pp = netdev_priv(dev);
3155         struct sockaddr *sockaddr = addr;
3156         int ret;
3157 
3158         ret = eth_prepare_mac_addr_change(dev, addr);
3159         if (ret < 0)
3160                 return ret;
3161         /* Remove previous address table entry */
3162         mvneta_mac_addr_set(pp, dev->dev_addr, -1);
3163 
3164         /* Set new addr in hw */
3165         mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def);
3166 
3167         eth_commit_mac_addr_change(dev, addr);
3168         return 0;
3169 }
3170 
3171 static void mvneta_adjust_link(struct net_device *ndev)
3172 {
3173         struct mvneta_port *pp = netdev_priv(ndev);
3174         struct phy_device *phydev = ndev->phydev;
3175         int status_change = 0;
3176 
3177         if (phydev->link) {
3178                 if ((pp->speed != phydev->speed) ||
3179                     (pp->duplex != phydev->duplex)) {
3180                         u32 val;
3181 
3182                         val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3183                         val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
3184                                  MVNETA_GMAC_CONFIG_GMII_SPEED |
3185                                  MVNETA_GMAC_CONFIG_FULL_DUPLEX);
3186 
3187                         if (phydev->duplex)
3188                                 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
3189 
3190                         if (phydev->speed == SPEED_1000)
3191                                 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
3192                         else if (phydev->speed == SPEED_100)
3193                                 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
3194 
3195                         mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
3196 
3197                         pp->duplex = phydev->duplex;
3198                         pp->speed  = phydev->speed;
3199                 }
3200         }
3201 
3202         if (phydev->link != pp->link) {
3203                 if (!phydev->link) {
3204                         pp->duplex = -1;
3205                         pp->speed = 0;
3206                 }
3207 
3208                 pp->link = phydev->link;
3209                 status_change = 1;
3210         }
3211 
3212         if (status_change) {
3213                 if (phydev->link) {
3214                         if (!pp->use_inband_status) {
3215                                 u32 val = mvreg_read(pp,
3216                                                   MVNETA_GMAC_AUTONEG_CONFIG);
3217                                 val &= ~MVNETA_GMAC_FORCE_LINK_DOWN;
3218                                 val |= MVNETA_GMAC_FORCE_LINK_PASS;
3219                                 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3220                                             val);
3221                         }
3222                         mvneta_port_up(pp);
3223                 } else {
3224                         if (!pp->use_inband_status) {
3225                                 u32 val = mvreg_read(pp,
3226                                                   MVNETA_GMAC_AUTONEG_CONFIG);
3227                                 val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
3228                                 val |= MVNETA_GMAC_FORCE_LINK_DOWN;
3229                                 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3230                                             val);
3231                         }
3232                         mvneta_port_down(pp);
3233                 }
3234                 phy_print_status(phydev);
3235         }
3236 }
3237 
3238 static int mvneta_mdio_probe(struct mvneta_port *pp)
3239 {
3240         struct phy_device *phy_dev;
3241 
3242         phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0,
3243                                  pp->phy_interface);
3244         if (!phy_dev) {
3245                 netdev_err(pp->dev, "could not find the PHY\n");
3246                 return -ENODEV;
3247         }
3248 
3249         phy_dev->supported &= PHY_GBIT_FEATURES;
3250         phy_dev->advertising = phy_dev->supported;
3251 
3252         pp->link    = 0;
3253         pp->duplex  = 0;
3254         pp->speed   = 0;
3255 
3256         return 0;
3257 }
3258 
3259 static void mvneta_mdio_remove(struct mvneta_port *pp)
3260 {
3261         struct net_device *ndev = pp->dev;
3262 
3263         phy_disconnect(ndev->phydev);
3264 }
3265 
3266 /* Electing a CPU must be done in an atomic way: it should be done
3267  * after or before the removal/insertion of a CPU and this function is
3268  * not reentrant.
3269  */
3270 static void mvneta_percpu_elect(struct mvneta_port *pp)
3271 {
3272         int elected_cpu = 0, max_cpu, cpu, i = 0;
3273 
3274         /* Use the cpu associated to the rxq when it is online, in all
3275          * the other cases, use the cpu 0 which can't be offline.
3276          */
3277         if (cpu_online(pp->rxq_def))
3278                 elected_cpu = pp->rxq_def;
3279 
3280         max_cpu = num_present_cpus();
3281 
3282         for_each_online_cpu(cpu) {
3283                 int rxq_map = 0, txq_map = 0;
3284                 int rxq;
3285 
3286                 for (rxq = 0; rxq < rxq_number; rxq++)
3287                         if ((rxq % max_cpu) == cpu)
3288                                 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
3289 
3290                 if (cpu == elected_cpu)
3291                         /* Map the default receive queue queue to the
3292                          * elected CPU
3293                          */
3294                         rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def);
3295 
3296                 /* We update the TX queue map only if we have one
3297                  * queue. In this case we associate the TX queue to
3298                  * the CPU bound to the default RX queue
3299                  */
3300                 if (txq_number == 1)
3301                         txq_map = (cpu == elected_cpu) ?
3302                                 MVNETA_CPU_TXQ_ACCESS(1) : 0;
3303                 else
3304                         txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) &
3305                                 MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
3306 
3307                 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
3308 
3309                 /* Update the interrupt mask on each CPU according the
3310                  * new mapping
3311                  */
3312                 smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt,
3313                                          pp, true);
3314                 i++;
3315 
3316         }
3317 };
3318 
3319 static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node)
3320 {
3321         int other_cpu;
3322         struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
3323                                                   node_online);
3324         struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
3325 
3326 
3327         spin_lock(&pp->lock);
3328         /*
3329          * Configuring the driver for a new CPU while the driver is
3330          * stopping is racy, so just avoid it.
3331          */
3332         if (pp->is_stopped) {
3333                 spin_unlock(&pp->lock);
3334                 return 0;
3335         }
3336         netif_tx_stop_all_queues(pp->dev);
3337 
3338         /*
3339          * We have to synchronise on tha napi of each CPU except the one
3340          * just being woken up
3341          */
3342         for_each_online_cpu(other_cpu) {
3343                 if (other_cpu != cpu) {
3344                         struct mvneta_pcpu_port *other_port =
3345                                 per_cpu_ptr(pp->ports, other_cpu);
3346 
3347                         napi_synchronize(&other_port->napi);
3348                 }
3349         }
3350 
3351         /* Mask all ethernet port interrupts */
3352         on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3353         napi_enable(&port->napi);
3354 
3355         /*
3356          * Enable per-CPU interrupts on the CPU that is
3357          * brought up.
3358          */
3359         mvneta_percpu_enable(pp);
3360 
3361         /*
3362          * Enable per-CPU interrupt on the one CPU we care
3363          * about.
3364          */
3365         mvneta_percpu_elect(pp);
3366 
3367         /* Unmask all ethernet port interrupts */
3368         on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
3369         mvreg_write(pp, MVNETA_INTR_MISC_MASK,
3370                     MVNETA_CAUSE_PHY_STATUS_CHANGE |
3371                     MVNETA_CAUSE_LINK_CHANGE |
3372                     MVNETA_CAUSE_PSC_SYNC_CHANGE);
3373         netif_tx_start_all_queues(pp->dev);
3374         spin_unlock(&pp->lock);
3375         return 0;
3376 }
3377 
3378 static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node)
3379 {
3380         struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
3381                                                   node_online);
3382         struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
3383 
3384         /*
3385          * Thanks to this lock we are sure that any pending cpu election is
3386          * done.
3387          */
3388         spin_lock(&pp->lock);
3389         /* Mask all ethernet port interrupts */
3390         on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3391         spin_unlock(&pp->lock);
3392 
3393         napi_synchronize(&port->napi);
3394         napi_disable(&port->napi);
3395         /* Disable per-CPU interrupts on the CPU that is brought down. */
3396         mvneta_percpu_disable(pp);
3397         return 0;
3398 }
3399 
3400 static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node)
3401 {
3402         struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
3403                                                   node_dead);
3404 
3405         /* Check if a new CPU must be elected now this on is down */
3406         spin_lock(&pp->lock);
3407         mvneta_percpu_elect(pp);
3408         spin_unlock(&pp->lock);
3409         /* Unmask all ethernet port interrupts */
3410         on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
3411         mvreg_write(pp, MVNETA_INTR_MISC_MASK,
3412                     MVNETA_CAUSE_PHY_STATUS_CHANGE |
3413                     MVNETA_CAUSE_LINK_CHANGE |
3414                     MVNETA_CAUSE_PSC_SYNC_CHANGE);
3415         netif_tx_start_all_queues(pp->dev);
3416         return 0;
3417 }
3418 
3419 static int mvneta_open(struct net_device *dev)
3420 {
3421         struct mvneta_port *pp = netdev_priv(dev);
3422         int ret;
3423 
3424         pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
3425         pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
3426                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3427 
3428         ret = mvneta_setup_rxqs(pp);
3429         if (ret)
3430                 return ret;
3431 
3432         ret = mvneta_setup_txqs(pp);
3433         if (ret)
3434                 goto err_cleanup_rxqs;
3435 
3436         /* Connect to port interrupt line */
3437         ret = request_percpu_irq(pp->dev->irq, mvneta_isr,
3438                                  MVNETA_DRIVER_NAME, pp->ports);
3439         if (ret) {
3440                 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq);
3441                 goto err_cleanup_txqs;
3442         }
3443 
3444         /* Enable per-CPU interrupt on all the CPU to handle our RX
3445          * queue interrupts
3446          */
3447         on_each_cpu(mvneta_percpu_enable, pp, true);
3448 
3449         pp->is_stopped = false;
3450         /* Register a CPU notifier to handle the case where our CPU
3451          * might be taken offline.
3452          */
3453         ret = cpuhp_state_add_instance_nocalls(online_hpstate,
3454                                                &pp->node_online);
3455         if (ret)
3456                 goto err_free_irq;
3457 
3458         ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
3459                                                &pp->node_dead);
3460         if (ret)
3461                 goto err_free_online_hp;
3462 
3463         /* In default link is down */
3464         netif_carrier_off(pp->dev);
3465 
3466         ret = mvneta_mdio_probe(pp);
3467         if (ret < 0) {
3468                 netdev_err(dev, "cannot probe MDIO bus\n");
3469                 goto err_free_dead_hp;
3470         }
3471 
3472         mvneta_start_dev(pp);
3473 
3474         return 0;
3475 
3476 err_free_dead_hp:
3477         cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
3478                                             &pp->node_dead);
3479 err_free_online_hp:
3480         cpuhp_state_remove_instance_nocalls(online_hpstate, &pp->node_online);
3481 err_free_irq:
3482         on_each_cpu(mvneta_percpu_disable, pp, true);
3483         free_percpu_irq(pp->dev->irq, pp->ports);
3484 err_cleanup_txqs:
3485         mvneta_cleanup_txqs(pp);
3486 err_cleanup_rxqs:
3487         mvneta_cleanup_rxqs(pp);
3488         return ret;
3489 }
3490 
3491 /* Stop the port, free port interrupt line */
3492 static int mvneta_stop(struct net_device *dev)
3493 {
3494         struct mvneta_port *pp = netdev_priv(dev);
3495 
3496         /* Inform that we are stopping so we don't want to setup the
3497          * driver for new CPUs in the notifiers. The code of the
3498          * notifier for CPU online is protected by the same spinlock,
3499          * so when we get the lock, the notifer work is done.
3500          */
3501         spin_lock(&pp->lock);
3502         pp->is_stopped = true;
3503         spin_unlock(&pp->lock);
3504 
3505         mvneta_stop_dev(pp);
3506         mvneta_mdio_remove(pp);
3507 
3508         cpuhp_state_remove_instance_nocalls(online_hpstate, &pp->node_online);
3509         cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
3510                                             &pp->node_dead);
3511         on_each_cpu(mvneta_percpu_disable, pp, true);
3512         free_percpu_irq(dev->irq, pp->ports);
3513         mvneta_cleanup_rxqs(pp);
3514         mvneta_cleanup_txqs(pp);
3515 
3516         return 0;
3517 }
3518 
3519 static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3520 {
3521         if (!dev->phydev)
3522                 return -ENOTSUPP;
3523 
3524         return phy_mii_ioctl(dev->phydev, ifr, cmd);
3525 }
3526 
3527 /* Ethtool methods */
3528 
3529 /* Set link ksettings (phy address, speed) for ethtools */
3530 static int
3531 mvneta_ethtool_set_link_ksettings(struct net_device *ndev,
3532                                   const struct ethtool_link_ksettings *cmd)
3533 {
3534         struct mvneta_port *pp = netdev_priv(ndev);
3535         struct phy_device *phydev = ndev->phydev;
3536 
3537         if (!phydev)
3538                 return -ENODEV;
3539 
3540         if ((cmd->base.autoneg == AUTONEG_ENABLE) != pp->use_inband_status) {
3541                 u32 val;
3542 
3543                 mvneta_set_autoneg(pp, cmd->base.autoneg == AUTONEG_ENABLE);
3544 
3545                 if (cmd->base.autoneg == AUTONEG_DISABLE) {
3546                         val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3547                         val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
3548                                  MVNETA_GMAC_CONFIG_GMII_SPEED |
3549                                  MVNETA_GMAC_CONFIG_FULL_DUPLEX);
3550 
3551                         if (phydev->duplex)
3552                                 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
3553 
3554                         if (phydev->speed == SPEED_1000)
3555                                 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
3556                         else if (phydev->speed == SPEED_100)
3557                                 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
3558 
3559                         mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
3560                 }
3561 
3562                 pp->use_inband_status = (cmd->base.autoneg == AUTONEG_ENABLE);
3563                 netdev_info(pp->dev, "autoneg status set to %i\n",
3564                             pp->use_inband_status);
3565 
3566                 if (netif_running(ndev)) {
3567                         mvneta_port_down(pp);
3568                         mvneta_port_up(pp);
3569                 }
3570         }
3571 
3572         return phy_ethtool_ksettings_set(ndev->phydev, cmd);
3573 }
3574 
3575 /* Set interrupt coalescing for ethtools */
3576 static int mvneta_ethtool_set_coalesce(struct net_device *dev,
3577                                        struct ethtool_coalesce *c)
3578 {
3579         struct mvneta_port *pp = netdev_priv(dev);
3580         int queue;
3581 
3582         for (queue = 0; queue < rxq_number; queue++) {
3583                 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
3584                 rxq->time_coal = c->rx_coalesce_usecs;
3585                 rxq->pkts_coal = c->rx_max_coalesced_frames;
3586                 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
3587                 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
3588         }
3589 
3590         for (queue = 0; queue < txq_number; queue++) {
3591                 struct mvneta_tx_queue *txq = &pp->txqs[queue];
3592                 txq->done_pkts_coal = c->tx_max_coalesced_frames;
3593                 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
3594         }
3595 
3596         return 0;
3597 }
3598 
3599 /* get coalescing for ethtools */
3600 static int mvneta_ethtool_get_coalesce(struct net_device *dev,
3601                                        struct ethtool_coalesce *c)
3602 {
3603         struct mvneta_port *pp = netdev_priv(dev);
3604 
3605         c->rx_coalesce_usecs        = pp->rxqs[0].time_coal;
3606         c->rx_max_coalesced_frames  = pp->rxqs[0].pkts_coal;
3607 
3608         c->tx_max_coalesced_frames =  pp->txqs[0].done_pkts_coal;
3609         return 0;
3610 }
3611 
3612 
3613 static void mvneta_ethtool_get_drvinfo(struct net_device *dev,
3614                                     struct ethtool_drvinfo *drvinfo)
3615 {
3616         strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME,
3617                 sizeof(drvinfo->driver));
3618         strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION,
3619                 sizeof(drvinfo->version));
3620         strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
3621                 sizeof(drvinfo->bus_info));
3622 }
3623 
3624 
3625 static void mvneta_ethtool_get_ringparam(struct net_device *netdev,
3626                                          struct ethtool_ringparam *ring)
3627 {
3628         struct mvneta_port *pp = netdev_priv(netdev);
3629 
3630         ring->rx_max_pending = MVNETA_MAX_RXD;
3631         ring->tx_max_pending = MVNETA_MAX_TXD;
3632         ring->rx_pending = pp->rx_ring_size;
3633         ring->tx_pending = pp->tx_ring_size;
3634 }
3635 
3636 static int mvneta_ethtool_set_ringparam(struct net_device *dev,
3637                                         struct ethtool_ringparam *ring)
3638 {
3639         struct mvneta_port *pp = netdev_priv(dev);
3640 
3641         if ((ring->rx_pending == 0) || (ring->tx_pending == 0))
3642                 return -EINVAL;
3643         pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ?
3644                 ring->rx_pending : MVNETA_MAX_RXD;
3645 
3646         pp->tx_ring_size = clamp_t(u16, ring->tx_pending,
3647                                    MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD);
3648         if (pp->tx_ring_size != ring->tx_pending)
3649                 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
3650                             pp->tx_ring_size, ring->tx_pending);
3651 
3652         if (netif_running(dev)) {
3653                 mvneta_stop(dev);
3654                 if (mvneta_open(dev)) {
3655                         netdev_err(dev,
3656                                    "error on opening device after ring param change\n");
3657                         return -ENOMEM;
3658                 }
3659         }
3660 
3661         return 0;
3662 }
3663 
3664 static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset,
3665                                        u8 *data)
3666 {
3667         if (sset == ETH_SS_STATS) {
3668                 int i;
3669 
3670                 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
3671                         memcpy(data + i * ETH_GSTRING_LEN,
3672                                mvneta_statistics[i].name, ETH_GSTRING_LEN);
3673         }
3674 }
3675 
3676 static void mvneta_ethtool_update_stats(struct mvneta_port *pp)
3677 {
3678         const struct mvneta_statistic *s;
3679         void __iomem *base = pp->base;
3680         u32 high, low, val;
3681         u64 val64;
3682         int i;
3683 
3684         for (i = 0, s = mvneta_statistics;
3685              s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics);
3686              s++, i++) {
3687                 switch (s->type) {
3688                 case T_REG_32:
3689                         val = readl_relaxed(base + s->offset);
3690                         pp->ethtool_stats[i] += val;
3691                         break;
3692                 case T_REG_64:
3693                         /* Docs say to read low 32-bit then high */
3694                         low = readl_relaxed(base + s->offset);
3695                         high = readl_relaxed(base + s->offset + 4);
3696                         val64 = (u64)high << 32 | low;
3697                         pp->ethtool_stats[i] += val64;
3698                         break;
3699                 }
3700         }
3701 }
3702 
3703 static void mvneta_ethtool_get_stats(struct net_device *dev,
3704                                      struct ethtool_stats *stats, u64 *data)
3705 {
3706         struct mvneta_port *pp = netdev_priv(dev);
3707         int i;
3708 
3709         mvneta_ethtool_update_stats(pp);
3710 
3711         for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
3712                 *data++ = pp->ethtool_stats[i];
3713 }
3714 
3715 static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset)
3716 {
3717         if (sset == ETH_SS_STATS)
3718                 return ARRAY_SIZE(mvneta_statistics);
3719         return -EOPNOTSUPP;
3720 }
3721 
3722 static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev)
3723 {
3724         return MVNETA_RSS_LU_TABLE_SIZE;
3725 }
3726 
3727 static int mvneta_ethtool_get_rxnfc(struct net_device *dev,
3728                                     struct ethtool_rxnfc *info,
3729                                     u32 *rules __always_unused)
3730 {
3731         switch (info->cmd) {
3732         case ETHTOOL_GRXRINGS:
3733                 info->data =  rxq_number;
3734                 return 0;
3735         case ETHTOOL_GRXFH:
3736                 return -EOPNOTSUPP;
3737         default:
3738                 return -EOPNOTSUPP;
3739         }
3740 }
3741 
3742 static int  mvneta_config_rss(struct mvneta_port *pp)
3743 {
3744         int cpu;
3745         u32 val;
3746 
3747         netif_tx_stop_all_queues(pp->dev);
3748 
3749         on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3750 
3751         /* We have to synchronise on the napi of each CPU */
3752         for_each_online_cpu(cpu) {
3753                 struct mvneta_pcpu_port *pcpu_port =
3754                         per_cpu_ptr(pp->ports, cpu);
3755 
3756                 napi_synchronize(&pcpu_port->napi);
3757                 napi_disable(&pcpu_port->napi);
3758         }
3759 
3760         pp->rxq_def = pp->indir[0];
3761 
3762         /* Update unicast mapping */
3763         mvneta_set_rx_mode(pp->dev);
3764 
3765         /* Update val of portCfg register accordingly with all RxQueue types */
3766         val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
3767         mvreg_write(pp, MVNETA_PORT_CONFIG, val);
3768 
3769         /* Update the elected CPU matching the new rxq_def */
3770         spin_lock(&pp->lock);
3771         mvneta_percpu_elect(pp);
3772         spin_unlock(&pp->lock);
3773 
3774         /* We have to synchronise on the napi of each CPU */
3775         for_each_online_cpu(cpu) {
3776                 struct mvneta_pcpu_port *pcpu_port =
3777                         per_cpu_ptr(pp->ports, cpu);
3778 
3779                 napi_enable(&pcpu_port->napi);
3780         }
3781 
3782         netif_tx_start_all_queues(pp->dev);
3783 
3784         return 0;
3785 }
3786 
3787 static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
3788                                    const u8 *key, const u8 hfunc)
3789 {
3790         struct mvneta_port *pp = netdev_priv(dev);
3791         /* We require at least one supported parameter to be changed
3792          * and no change in any of the unsupported parameters
3793          */
3794         if (key ||
3795             (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3796                 return -EOPNOTSUPP;
3797 
3798         if (!indir)
3799                 return 0;
3800 
3801         memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE);
3802 
3803         return mvneta_config_rss(pp);
3804 }
3805 
3806 static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3807                                    u8 *hfunc)
3808 {
3809         struct mvneta_port *pp = netdev_priv(dev);
3810 
3811         if (hfunc)
3812                 *hfunc = ETH_RSS_HASH_TOP;
3813 
3814         if (!indir)
3815                 return 0;
3816 
3817         memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE);
3818 
3819         return 0;
3820 }
3821 
3822 static const struct net_device_ops mvneta_netdev_ops = {
3823         .ndo_open            = mvneta_open,
3824         .ndo_stop            = mvneta_stop,
3825         .ndo_start_xmit      = mvneta_tx,
3826         .ndo_set_rx_mode     = mvneta_set_rx_mode,
3827         .ndo_set_mac_address = mvneta_set_mac_addr,
3828         .ndo_change_mtu      = mvneta_change_mtu,
3829         .ndo_fix_features    = mvneta_fix_features,
3830         .ndo_get_stats64     = mvneta_get_stats64,
3831         .ndo_do_ioctl        = mvneta_ioctl,
3832 };
3833 
3834 const struct ethtool_ops mvneta_eth_tool_ops = {
3835         .get_link       = ethtool_op_get_link,
3836         .set_coalesce   = mvneta_ethtool_set_coalesce,
3837         .get_coalesce   = mvneta_ethtool_get_coalesce,
3838         .get_drvinfo    = mvneta_ethtool_get_drvinfo,
3839         .get_ringparam  = mvneta_ethtool_get_ringparam,
3840         .set_ringparam  = mvneta_ethtool_set_ringparam,
3841         .get_strings    = mvneta_ethtool_get_strings,
3842         .get_ethtool_stats = mvneta_ethtool_get_stats,
3843         .get_sset_count = mvneta_ethtool_get_sset_count,
3844         .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size,
3845         .get_rxnfc      = mvneta_ethtool_get_rxnfc,
3846         .get_rxfh       = mvneta_ethtool_get_rxfh,
3847         .set_rxfh       = mvneta_ethtool_set_rxfh,
3848         .get_link_ksettings = phy_ethtool_get_link_ksettings,
3849         .set_link_ksettings = mvneta_ethtool_set_link_ksettings,
3850 };
3851 
3852 /* Initialize hw */
3853 static int mvneta_init(struct device *dev, struct mvneta_port *pp)
3854 {
3855         int queue;
3856 
3857         /* Disable port */
3858         mvneta_port_disable(pp);
3859 
3860         /* Set port default values */
3861         mvneta_defaults_set(pp);
3862 
3863         pp->txqs = devm_kcalloc(dev, txq_number, sizeof(struct mvneta_tx_queue),
3864                                 GFP_KERNEL);
3865         if (!pp->txqs)
3866                 return -ENOMEM;
3867 
3868         /* Initialize TX descriptor rings */
3869         for (queue = 0; queue < txq_number; queue++) {
3870                 struct mvneta_tx_queue *txq = &pp->txqs[queue];
3871                 txq->id = queue;
3872                 txq->size = pp->tx_ring_size;
3873                 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS;
3874         }
3875 
3876         pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(struct mvneta_rx_queue),
3877                                 GFP_KERNEL);
3878         if (!pp->rxqs)
3879                 return -ENOMEM;
3880 
3881         /* Create Rx descriptor rings */
3882         for (queue = 0; queue < rxq_number; queue++) {
3883                 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
3884                 rxq->id = queue;
3885                 rxq->size = pp->rx_ring_size;
3886                 rxq->pkts_coal = MVNETA_RX_COAL_PKTS;
3887                 rxq->time_coal = MVNETA_RX_COAL_USEC;
3888         }
3889 
3890         return 0;
3891 }
3892 
3893 /* platform glue : initialize decoding windows */
3894 static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
3895                                      const struct mbus_dram_target_info *dram)
3896 {
3897         u32 win_enable;
3898         u32 win_protect;
3899         int i;
3900 
3901         for (i = 0; i < 6; i++) {
3902                 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
3903                 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
3904 
3905                 if (i < 4)
3906                         mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
3907         }
3908 
3909         win_enable = 0x3f;
3910         win_protect = 0;
3911 
3912         for (i = 0; i < dram->num_cs; i++) {
3913                 const struct mbus_dram_window *cs = dram->cs + i;
3914                 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
3915                             (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
3916 
3917                 mvreg_write(pp, MVNETA_WIN_SIZE(i),
3918                             (cs->size - 1) & 0xffff0000);
3919 
3920                 win_enable &= ~(1 << i);
3921                 win_protect |= 3 << (2 * i);
3922         }
3923 
3924         mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
3925         mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
3926 }
3927 
3928 /* Power up the port */
3929 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
3930 {
3931         u32 ctrl;
3932 
3933         /* MAC Cause register should be cleared */
3934         mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
3935 
3936         ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
3937 
3938         /* Even though it might look weird, when we're configured in
3939          * SGMII or QSGMII mode, the RGMII bit needs to be set.
3940          */
3941         switch(phy_mode) {
3942         case PHY_INTERFACE_MODE_QSGMII:
3943                 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
3944                 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
3945                 break;
3946         case PHY_INTERFACE_MODE_SGMII:
3947                 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
3948                 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
3949                 break;
3950         case PHY_INTERFACE_MODE_RGMII:
3951         case PHY_INTERFACE_MODE_RGMII_ID:
3952                 ctrl |= MVNETA_GMAC2_PORT_RGMII;
3953                 break;
3954         default:
3955                 return -EINVAL;
3956         }
3957 
3958         /* Cancel Port Reset */
3959         ctrl &= ~MVNETA_GMAC2_PORT_RESET;
3960         mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
3961 
3962         while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
3963                 MVNETA_GMAC2_PORT_RESET) != 0)
3964                 continue;
3965 
3966         return 0;
3967 }
3968 
3969 /* Device initialization routine */
3970 static int mvneta_probe(struct platform_device *pdev)
3971 {
3972         const struct mbus_dram_target_info *dram_target_info;
3973         struct resource *res;
3974         struct device_node *dn = pdev->dev.of_node;
3975         struct device_node *phy_node;
3976         struct device_node *bm_node;
3977         struct mvneta_port *pp;
3978         struct net_device *dev;
3979         const char *dt_mac_addr;
3980         char hw_mac_addr[ETH_ALEN];
3981         const char *mac_from;
3982         const char *managed;
3983         int tx_csum_limit;
3984         int phy_mode;
3985         int err;
3986         int cpu;
3987 
3988         dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number);
3989         if (!dev)
3990                 return -ENOMEM;
3991 
3992         dev->irq = irq_of_parse_and_map(dn, 0);
3993         if (dev->irq == 0) {
3994                 err = -EINVAL;
3995                 goto err_free_netdev;
3996         }
3997 
3998         phy_node = of_parse_phandle(dn, "phy", 0);
3999         if (!phy_node) {
4000                 if (!of_phy_is_fixed_link(dn)) {
4001                         dev_err(&pdev->dev, "no PHY specified\n");
4002                         err = -ENODEV;
4003                         goto err_free_irq;
4004                 }
4005 
4006                 err = of_phy_register_fixed_link(dn);
4007                 if (err < 0) {
4008                         dev_err(&pdev->dev, "cannot register fixed PHY\n");
4009                         goto err_free_irq;
4010                 }
4011 
4012                 /* In the case of a fixed PHY, the DT node associated
4013                  * to the PHY is the Ethernet MAC DT node.
4014                  */
4015                 phy_node = of_node_get(dn);
4016         }
4017 
4018         phy_mode = of_get_phy_mode(dn);
4019         if (phy_mode < 0) {
4020                 dev_err(&pdev->dev, "incorrect phy-mode\n");
4021                 err = -EINVAL;
4022                 goto err_put_phy_node;
4023         }
4024 
4025         dev->tx_queue_len = MVNETA_MAX_TXD;
4026         dev->watchdog_timeo = 5 * HZ;
4027         dev->netdev_ops = &mvneta_netdev_ops;
4028 
4029         dev->ethtool_ops = &mvneta_eth_tool_ops;
4030 
4031         pp = netdev_priv(dev);
4032         spin_lock_init(&pp->lock);
4033         pp->phy_node = phy_node;
4034         pp->phy_interface = phy_mode;
4035 
4036         err = of_property_read_string(dn, "managed", &managed);
4037         pp->use_inband_status = (err == 0 &&
4038                                  strcmp(managed, "in-band-status") == 0);
4039 
4040         pp->rxq_def = rxq_def;
4041 
4042         pp->indir[0] = rxq_def;
4043 
4044         pp->clk = devm_clk_get(&pdev->dev, "core");
4045         if (IS_ERR(pp->clk))
4046                 pp->clk = devm_clk_get(&pdev->dev, NULL);
4047         if (IS_ERR(pp->clk)) {
4048                 err = PTR_ERR(pp->clk);
4049                 goto err_put_phy_node;
4050         }
4051 
4052         clk_prepare_enable(pp->clk);
4053 
4054         pp->clk_bus = devm_clk_get(&pdev->dev, "bus");
4055         if (!IS_ERR(pp->clk_bus))
4056                 clk_prepare_enable(pp->clk_bus);
4057 
4058         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4059         pp->base = devm_ioremap_resource(&pdev->dev, res);
4060         if (IS_ERR(pp->base)) {
4061                 err = PTR_ERR(pp->base);
4062                 goto err_clk;
4063         }
4064 
4065         /* Alloc per-cpu port structure */
4066         pp->ports = alloc_percpu(struct mvneta_pcpu_port);
4067         if (!pp->ports) {
4068                 err = -ENOMEM;
4069                 goto err_clk;
4070         }
4071 
4072         /* Alloc per-cpu stats */
4073         pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats);
4074         if (!pp->stats) {
4075                 err = -ENOMEM;
4076                 goto err_free_ports;
4077         }
4078 
4079         dt_mac_addr = of_get_mac_address(dn);
4080         if (dt_mac_addr) {
4081                 mac_from = "device tree";
4082                 memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN);
4083         } else {
4084                 mvneta_get_mac_addr(pp, hw_mac_addr);
4085                 if (is_valid_ether_addr(hw_mac_addr)) {
4086                         mac_from = "hardware";
4087                         memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN);
4088                 } else {
4089                         mac_from = "random";
4090                         eth_hw_addr_random(dev);
4091                 }
4092         }
4093 
4094         if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) {
4095                 if (tx_csum_limit < 0 ||
4096                     tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) {
4097                         tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
4098                         dev_info(&pdev->dev,
4099                                  "Wrong TX csum limit in DT, set to %dB\n",
4100                                  MVNETA_TX_CSUM_DEF_SIZE);
4101                 }
4102         } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) {
4103                 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
4104         } else {
4105                 tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE;
4106         }
4107 
4108         pp->tx_csum_limit = tx_csum_limit;
4109 
4110         dram_target_info = mv_mbus_dram_info();
4111         if (dram_target_info)
4112                 mvneta_conf_mbus_windows(pp, dram_target_info);
4113 
4114         pp->tx_ring_size = MVNETA_MAX_TXD;
4115         pp->rx_ring_size = MVNETA_MAX_RXD;
4116 
4117         pp->dev = dev;
4118         SET_NETDEV_DEV(dev, &pdev->dev);
4119 
4120         pp->id = global_port_id++;
4121 
4122         /* Obtain access to BM resources if enabled and already initialized */
4123         bm_node = of_parse_phandle(dn, "buffer-manager", 0);
4124         if (bm_node && bm_node->data) {
4125                 pp->bm_priv = bm_node->data;
4126                 err = mvneta_bm_port_init(pdev, pp);
4127                 if (err < 0) {
4128                         dev_info(&pdev->dev, "use SW buffer management\n");
4129                         pp->bm_priv = NULL;
4130                 }
4131         }
4132         of_node_put(bm_node);
4133 
4134         err = mvneta_init(&pdev->dev, pp);
4135         if (err < 0)
4136                 goto err_netdev;
4137 
4138         err = mvneta_port_power_up(pp, phy_mode);
4139         if (err < 0) {
4140                 dev_err(&pdev->dev, "can't power up port\n");
4141                 goto err_netdev;
4142         }
4143 
4144         for_each_present_cpu(cpu) {
4145                 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
4146 
4147                 netif_napi_add(dev, &port->napi, mvneta_poll, NAPI_POLL_WEIGHT);
4148                 port->pp = pp;
4149         }
4150 
4151         dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
4152         dev->hw_features |= dev->features;
4153         dev->vlan_features |= dev->features;
4154         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
4155         dev->gso_max_segs = MVNETA_MAX_TSO_SEGS;
4156 
4157         err = register_netdev(dev);
4158         if (err < 0) {
4159                 dev_err(&pdev->dev, "failed to register\n");
4160                 goto err_free_stats;
4161         }
4162 
4163         netdev_info(dev, "Using %s mac address %pM\n", mac_from,
4164                     dev->dev_addr);
4165 
4166         platform_set_drvdata(pdev, pp->dev);
4167 
4168         if (pp->use_inband_status) {
4169                 struct phy_device *phy = of_phy_find_device(dn);
4170 
4171                 mvneta_fixed_link_update(pp, phy);
4172 
4173                 put_device(&phy->mdio.dev);
4174         }
4175 
4176         return 0;
4177 
4178 err_netdev:
4179         unregister_netdev(dev);
4180         if (pp->bm_priv) {
4181                 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
4182                 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
4183                                        1 << pp->id);
4184         }
4185 err_free_stats:
4186         free_percpu(pp->stats);
4187 err_free_ports:
4188         free_percpu(pp->ports);
4189 err_clk:
4190         clk_disable_unprepare(pp->clk_bus);
4191         clk_disable_unprepare(pp->clk);
4192 err_put_phy_node:
4193         of_node_put(phy_node);
4194         if (of_phy_is_fixed_link(dn))
4195                 of_phy_deregister_fixed_link(dn);
4196 err_free_irq:
4197         irq_dispose_mapping(dev->irq);
4198 err_free_netdev:
4199         free_netdev(dev);
4200         return err;
4201 }
4202 
4203 /* Device removal routine */
4204 static int mvneta_remove(struct platform_device *pdev)
4205 {
4206         struct net_device  *dev = platform_get_drvdata(pdev);
4207         struct device_node *dn = pdev->dev.of_node;
4208         struct mvneta_port *pp = netdev_priv(dev);
4209 
4210         unregister_netdev(dev);
4211         clk_disable_unprepare(pp->clk_bus);
4212         clk_disable_unprepare(pp->clk);
4213         free_percpu(pp->ports);
4214         free_percpu(pp->stats);
4215         if (of_phy_is_fixed_link(dn))
4216                 of_phy_deregister_fixed_link(dn);
4217         irq_dispose_mapping(dev->irq);
4218         of_node_put(pp->phy_node);
4219         free_netdev(dev);
4220 
4221         if (pp->bm_priv) {
4222                 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
4223                 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
4224                                        1 << pp->id);
4225         }
4226 
4227         return 0;
4228 }
4229 
4230 static const struct of_device_id mvneta_match[] = {
4231         { .compatible = "marvell,armada-370-neta" },
4232         { .compatible = "marvell,armada-xp-neta" },
4233         { }
4234 };
4235 MODULE_DEVICE_TABLE(of, mvneta_match);
4236 
4237 static struct platform_driver mvneta_driver = {
4238         .probe = mvneta_probe,
4239         .remove = mvneta_remove,
4240         .driver = {
4241                 .name = MVNETA_DRIVER_NAME,
4242                 .of_match_table = mvneta_match,
4243         },
4244 };
4245 
4246 static int __init mvneta_driver_init(void)
4247 {
4248         int ret;
4249 
4250         ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvmeta:online",
4251                                       mvneta_cpu_online,
4252                                       mvneta_cpu_down_prepare);
4253         if (ret < 0)
4254                 goto out;
4255         online_hpstate = ret;
4256         ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead",
4257                                       NULL, mvneta_cpu_dead);
4258         if (ret)
4259                 goto err_dead;
4260 
4261         ret = platform_driver_register(&mvneta_driver);
4262         if (ret)
4263                 goto err;
4264         return 0;
4265 
4266 err:
4267         cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD);
4268 err_dead:
4269         cpuhp_remove_multi_state(online_hpstate);
4270 out:
4271         return ret;
4272 }
4273 module_init(mvneta_driver_init);
4274 
4275 static void __exit mvneta_driver_exit(void)
4276 {
4277         platform_driver_unregister(&mvneta_driver);
4278         cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD);
4279         cpuhp_remove_multi_state(online_hpstate);
4280 }
4281 module_exit(mvneta_driver_exit);
4282 
4283 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
4284 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
4285 MODULE_LICENSE("GPL");
4286 
4287 module_param(rxq_number, int, S_IRUGO);
4288 module_param(txq_number, int, S_IRUGO);
4289 
4290 module_param(rxq_def, int, S_IRUGO);
4291 module_param(rx_copybreak, int, S_IRUGO | S_IWUSR);
4292 

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