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Linux/drivers/net/ethernet/marvell/mv643xx_eth.c

  1 /*
  2  * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
  3  * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
  4  *
  5  * Based on the 64360 driver from:
  6  * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
  7  *                    Rabeeh Khoury <rabeeh@marvell.com>
  8  *
  9  * Copyright (C) 2003 PMC-Sierra, Inc.,
 10  *      written by Manish Lachwani
 11  *
 12  * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
 13  *
 14  * Copyright (C) 2004-2006 MontaVista Software, Inc.
 15  *                         Dale Farnsworth <dale@farnsworth.org>
 16  *
 17  * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
 18  *                                   <sjhill@realitydiluted.com>
 19  *
 20  * Copyright (C) 2007-2008 Marvell Semiconductor
 21  *                         Lennert Buytenhek <buytenh@marvell.com>
 22  *
 23  * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de>
 24  *
 25  * This program is free software; you can redistribute it and/or
 26  * modify it under the terms of the GNU General Public License
 27  * as published by the Free Software Foundation; either version 2
 28  * of the License, or (at your option) any later version.
 29  *
 30  * This program is distributed in the hope that it will be useful,
 31  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 32  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 33  * GNU General Public License for more details.
 34  *
 35  * You should have received a copy of the GNU General Public License
 36  * along with this program; if not, see <http://www.gnu.org/licenses/>.
 37  */
 38 
 39 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 40 
 41 #include <linux/init.h>
 42 #include <linux/dma-mapping.h>
 43 #include <linux/in.h>
 44 #include <linux/ip.h>
 45 #include <net/tso.h>
 46 #include <linux/tcp.h>
 47 #include <linux/udp.h>
 48 #include <linux/etherdevice.h>
 49 #include <linux/delay.h>
 50 #include <linux/ethtool.h>
 51 #include <linux/platform_device.h>
 52 #include <linux/module.h>
 53 #include <linux/kernel.h>
 54 #include <linux/spinlock.h>
 55 #include <linux/workqueue.h>
 56 #include <linux/phy.h>
 57 #include <linux/mv643xx_eth.h>
 58 #include <linux/io.h>
 59 #include <linux/interrupt.h>
 60 #include <linux/types.h>
 61 #include <linux/slab.h>
 62 #include <linux/clk.h>
 63 #include <linux/of.h>
 64 #include <linux/of_irq.h>
 65 #include <linux/of_net.h>
 66 #include <linux/of_mdio.h>
 67 
 68 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
 69 static char mv643xx_eth_driver_version[] = "1.4";
 70 
 71 
 72 /*
 73  * Registers shared between all ports.
 74  */
 75 #define PHY_ADDR                        0x0000
 76 #define WINDOW_BASE(w)                  (0x0200 + ((w) << 3))
 77 #define WINDOW_SIZE(w)                  (0x0204 + ((w) << 3))
 78 #define WINDOW_REMAP_HIGH(w)            (0x0280 + ((w) << 2))
 79 #define WINDOW_BAR_ENABLE               0x0290
 80 #define WINDOW_PROTECT(w)               (0x0294 + ((w) << 4))
 81 
 82 /*
 83  * Main per-port registers.  These live at offset 0x0400 for
 84  * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
 85  */
 86 #define PORT_CONFIG                     0x0000
 87 #define  UNICAST_PROMISCUOUS_MODE       0x00000001
 88 #define PORT_CONFIG_EXT                 0x0004
 89 #define MAC_ADDR_LOW                    0x0014
 90 #define MAC_ADDR_HIGH                   0x0018
 91 #define SDMA_CONFIG                     0x001c
 92 #define  TX_BURST_SIZE_16_64BIT         0x01000000
 93 #define  TX_BURST_SIZE_4_64BIT          0x00800000
 94 #define  BLM_TX_NO_SWAP                 0x00000020
 95 #define  BLM_RX_NO_SWAP                 0x00000010
 96 #define  RX_BURST_SIZE_16_64BIT         0x00000008
 97 #define  RX_BURST_SIZE_4_64BIT          0x00000004
 98 #define PORT_SERIAL_CONTROL             0x003c
 99 #define  SET_MII_SPEED_TO_100           0x01000000
100 #define  SET_GMII_SPEED_TO_1000         0x00800000
101 #define  SET_FULL_DUPLEX_MODE           0x00200000
102 #define  MAX_RX_PACKET_9700BYTE         0x000a0000
103 #define  DISABLE_AUTO_NEG_SPEED_GMII    0x00002000
104 #define  DO_NOT_FORCE_LINK_FAIL         0x00000400
105 #define  SERIAL_PORT_CONTROL_RESERVED   0x00000200
106 #define  DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
107 #define  DISABLE_AUTO_NEG_FOR_DUPLEX    0x00000004
108 #define  FORCE_LINK_PASS                0x00000002
109 #define  SERIAL_PORT_ENABLE             0x00000001
110 #define PORT_STATUS                     0x0044
111 #define  TX_FIFO_EMPTY                  0x00000400
112 #define  TX_IN_PROGRESS                 0x00000080
113 #define  PORT_SPEED_MASK                0x00000030
114 #define  PORT_SPEED_1000                0x00000010
115 #define  PORT_SPEED_100                 0x00000020
116 #define  PORT_SPEED_10                  0x00000000
117 #define  FLOW_CONTROL_ENABLED           0x00000008
118 #define  FULL_DUPLEX                    0x00000004
119 #define  LINK_UP                        0x00000002
120 #define TXQ_COMMAND                     0x0048
121 #define TXQ_FIX_PRIO_CONF               0x004c
122 #define PORT_SERIAL_CONTROL1            0x004c
123 #define  CLK125_BYPASS_EN               0x00000010
124 #define TX_BW_RATE                      0x0050
125 #define TX_BW_MTU                       0x0058
126 #define TX_BW_BURST                     0x005c
127 #define INT_CAUSE                       0x0060
128 #define  INT_TX_END                     0x07f80000
129 #define  INT_TX_END_0                   0x00080000
130 #define  INT_RX                         0x000003fc
131 #define  INT_RX_0                       0x00000004
132 #define  INT_EXT                        0x00000002
133 #define INT_CAUSE_EXT                   0x0064
134 #define  INT_EXT_LINK_PHY               0x00110000
135 #define  INT_EXT_TX                     0x000000ff
136 #define INT_MASK                        0x0068
137 #define INT_MASK_EXT                    0x006c
138 #define TX_FIFO_URGENT_THRESHOLD        0x0074
139 #define RX_DISCARD_FRAME_CNT            0x0084
140 #define RX_OVERRUN_FRAME_CNT            0x0088
141 #define TXQ_FIX_PRIO_CONF_MOVED         0x00dc
142 #define TX_BW_RATE_MOVED                0x00e0
143 #define TX_BW_MTU_MOVED                 0x00e8
144 #define TX_BW_BURST_MOVED               0x00ec
145 #define RXQ_CURRENT_DESC_PTR(q)         (0x020c + ((q) << 4))
146 #define RXQ_COMMAND                     0x0280
147 #define TXQ_CURRENT_DESC_PTR(q)         (0x02c0 + ((q) << 2))
148 #define TXQ_BW_TOKENS(q)                (0x0300 + ((q) << 4))
149 #define TXQ_BW_CONF(q)                  (0x0304 + ((q) << 4))
150 #define TXQ_BW_WRR_CONF(q)              (0x0308 + ((q) << 4))
151 
152 /*
153  * Misc per-port registers.
154  */
155 #define MIB_COUNTERS(p)                 (0x1000 + ((p) << 7))
156 #define SPECIAL_MCAST_TABLE(p)          (0x1400 + ((p) << 10))
157 #define OTHER_MCAST_TABLE(p)            (0x1500 + ((p) << 10))
158 #define UNICAST_TABLE(p)                (0x1600 + ((p) << 10))
159 
160 
161 /*
162  * SDMA configuration register default value.
163  */
164 #if defined(__BIG_ENDIAN)
165 #define PORT_SDMA_CONFIG_DEFAULT_VALUE          \
166                 (RX_BURST_SIZE_4_64BIT  |       \
167                  TX_BURST_SIZE_4_64BIT)
168 #elif defined(__LITTLE_ENDIAN)
169 #define PORT_SDMA_CONFIG_DEFAULT_VALUE          \
170                 (RX_BURST_SIZE_4_64BIT  |       \
171                  BLM_RX_NO_SWAP         |       \
172                  BLM_TX_NO_SWAP         |       \
173                  TX_BURST_SIZE_4_64BIT)
174 #else
175 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
176 #endif
177 
178 
179 /*
180  * Misc definitions.
181  */
182 #define DEFAULT_RX_QUEUE_SIZE   128
183 #define DEFAULT_TX_QUEUE_SIZE   512
184 #define SKB_DMA_REALIGN         ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
185 
186 #define TSO_HEADER_SIZE         128
187 
188 /* Max number of allowed TCP segments for software TSO */
189 #define MV643XX_MAX_TSO_SEGS 100
190 #define MV643XX_MAX_SKB_DESCS (MV643XX_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
191 
192 #define IS_TSO_HEADER(txq, addr) \
193         ((addr >= txq->tso_hdrs_dma) && \
194          (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
195 
196 #define DESC_DMA_MAP_SINGLE 0
197 #define DESC_DMA_MAP_PAGE 1
198 
199 /*
200  * RX/TX descriptors.
201  */
202 #if defined(__BIG_ENDIAN)
203 struct rx_desc {
204         u16 byte_cnt;           /* Descriptor buffer byte count         */
205         u16 buf_size;           /* Buffer size                          */
206         u32 cmd_sts;            /* Descriptor command status            */
207         u32 next_desc_ptr;      /* Next descriptor pointer              */
208         u32 buf_ptr;            /* Descriptor buffer pointer            */
209 };
210 
211 struct tx_desc {
212         u16 byte_cnt;           /* buffer byte count                    */
213         u16 l4i_chk;            /* CPU provided TCP checksum            */
214         u32 cmd_sts;            /* Command/status field                 */
215         u32 next_desc_ptr;      /* Pointer to next descriptor           */
216         u32 buf_ptr;            /* pointer to buffer for this descriptor*/
217 };
218 #elif defined(__LITTLE_ENDIAN)
219 struct rx_desc {
220         u32 cmd_sts;            /* Descriptor command status            */
221         u16 buf_size;           /* Buffer size                          */
222         u16 byte_cnt;           /* Descriptor buffer byte count         */
223         u32 buf_ptr;            /* Descriptor buffer pointer            */
224         u32 next_desc_ptr;      /* Next descriptor pointer              */
225 };
226 
227 struct tx_desc {
228         u32 cmd_sts;            /* Command/status field                 */
229         u16 l4i_chk;            /* CPU provided TCP checksum            */
230         u16 byte_cnt;           /* buffer byte count                    */
231         u32 buf_ptr;            /* pointer to buffer for this descriptor*/
232         u32 next_desc_ptr;      /* Pointer to next descriptor           */
233 };
234 #else
235 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
236 #endif
237 
238 /* RX & TX descriptor command */
239 #define BUFFER_OWNED_BY_DMA             0x80000000
240 
241 /* RX & TX descriptor status */
242 #define ERROR_SUMMARY                   0x00000001
243 
244 /* RX descriptor status */
245 #define LAYER_4_CHECKSUM_OK             0x40000000
246 #define RX_ENABLE_INTERRUPT             0x20000000
247 #define RX_FIRST_DESC                   0x08000000
248 #define RX_LAST_DESC                    0x04000000
249 #define RX_IP_HDR_OK                    0x02000000
250 #define RX_PKT_IS_IPV4                  0x01000000
251 #define RX_PKT_IS_ETHERNETV2            0x00800000
252 #define RX_PKT_LAYER4_TYPE_MASK         0x00600000
253 #define RX_PKT_LAYER4_TYPE_TCP_IPV4     0x00000000
254 #define RX_PKT_IS_VLAN_TAGGED           0x00080000
255 
256 /* TX descriptor command */
257 #define TX_ENABLE_INTERRUPT             0x00800000
258 #define GEN_CRC                         0x00400000
259 #define TX_FIRST_DESC                   0x00200000
260 #define TX_LAST_DESC                    0x00100000
261 #define ZERO_PADDING                    0x00080000
262 #define GEN_IP_V4_CHECKSUM              0x00040000
263 #define GEN_TCP_UDP_CHECKSUM            0x00020000
264 #define UDP_FRAME                       0x00010000
265 #define MAC_HDR_EXTRA_4_BYTES           0x00008000
266 #define GEN_TCP_UDP_CHK_FULL            0x00000400
267 #define MAC_HDR_EXTRA_8_BYTES           0x00000200
268 
269 #define TX_IHL_SHIFT                    11
270 
271 
272 /* global *******************************************************************/
273 struct mv643xx_eth_shared_private {
274         /*
275          * Ethernet controller base address.
276          */
277         void __iomem *base;
278 
279         /*
280          * Per-port MBUS window access register value.
281          */
282         u32 win_protect;
283 
284         /*
285          * Hardware-specific parameters.
286          */
287         int extended_rx_coal_limit;
288         int tx_bw_control;
289         int tx_csum_limit;
290         struct clk *clk;
291 };
292 
293 #define TX_BW_CONTROL_ABSENT            0
294 #define TX_BW_CONTROL_OLD_LAYOUT        1
295 #define TX_BW_CONTROL_NEW_LAYOUT        2
296 
297 static int mv643xx_eth_open(struct net_device *dev);
298 static int mv643xx_eth_stop(struct net_device *dev);
299 
300 
301 /* per-port *****************************************************************/
302 struct mib_counters {
303         u64 good_octets_received;
304         u32 bad_octets_received;
305         u32 internal_mac_transmit_err;
306         u32 good_frames_received;
307         u32 bad_frames_received;
308         u32 broadcast_frames_received;
309         u32 multicast_frames_received;
310         u32 frames_64_octets;
311         u32 frames_65_to_127_octets;
312         u32 frames_128_to_255_octets;
313         u32 frames_256_to_511_octets;
314         u32 frames_512_to_1023_octets;
315         u32 frames_1024_to_max_octets;
316         u64 good_octets_sent;
317         u32 good_frames_sent;
318         u32 excessive_collision;
319         u32 multicast_frames_sent;
320         u32 broadcast_frames_sent;
321         u32 unrec_mac_control_received;
322         u32 fc_sent;
323         u32 good_fc_received;
324         u32 bad_fc_received;
325         u32 undersize_received;
326         u32 fragments_received;
327         u32 oversize_received;
328         u32 jabber_received;
329         u32 mac_receive_error;
330         u32 bad_crc_event;
331         u32 collision;
332         u32 late_collision;
333         /* Non MIB hardware counters */
334         u32 rx_discard;
335         u32 rx_overrun;
336 };
337 
338 struct rx_queue {
339         int index;
340 
341         int rx_ring_size;
342 
343         int rx_desc_count;
344         int rx_curr_desc;
345         int rx_used_desc;
346 
347         struct rx_desc *rx_desc_area;
348         dma_addr_t rx_desc_dma;
349         int rx_desc_area_size;
350         struct sk_buff **rx_skb;
351 };
352 
353 struct tx_queue {
354         int index;
355 
356         int tx_ring_size;
357 
358         int tx_desc_count;
359         int tx_curr_desc;
360         int tx_used_desc;
361 
362         int tx_stop_threshold;
363         int tx_wake_threshold;
364 
365         char *tso_hdrs;
366         dma_addr_t tso_hdrs_dma;
367 
368         struct tx_desc *tx_desc_area;
369         char *tx_desc_mapping; /* array to track the type of the dma mapping */
370         dma_addr_t tx_desc_dma;
371         int tx_desc_area_size;
372 
373         struct sk_buff_head tx_skb;
374 
375         unsigned long tx_packets;
376         unsigned long tx_bytes;
377         unsigned long tx_dropped;
378 };
379 
380 struct mv643xx_eth_private {
381         struct mv643xx_eth_shared_private *shared;
382         void __iomem *base;
383         int port_num;
384 
385         struct net_device *dev;
386 
387         struct phy_device *phy;
388 
389         struct timer_list mib_counters_timer;
390         spinlock_t mib_counters_lock;
391         struct mib_counters mib_counters;
392 
393         struct work_struct tx_timeout_task;
394 
395         struct napi_struct napi;
396         u32 int_mask;
397         u8 oom;
398         u8 work_link;
399         u8 work_tx;
400         u8 work_tx_end;
401         u8 work_rx;
402         u8 work_rx_refill;
403 
404         int skb_size;
405 
406         /*
407          * RX state.
408          */
409         int rx_ring_size;
410         unsigned long rx_desc_sram_addr;
411         int rx_desc_sram_size;
412         int rxq_count;
413         struct timer_list rx_oom;
414         struct rx_queue rxq[8];
415 
416         /*
417          * TX state.
418          */
419         int tx_ring_size;
420         unsigned long tx_desc_sram_addr;
421         int tx_desc_sram_size;
422         int txq_count;
423         struct tx_queue txq[8];
424 
425         /*
426          * Hardware-specific parameters.
427          */
428         struct clk *clk;
429         unsigned int t_clk;
430 };
431 
432 
433 /* port register accessors **************************************************/
434 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
435 {
436         return readl(mp->shared->base + offset);
437 }
438 
439 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
440 {
441         return readl(mp->base + offset);
442 }
443 
444 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
445 {
446         writel(data, mp->shared->base + offset);
447 }
448 
449 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
450 {
451         writel(data, mp->base + offset);
452 }
453 
454 
455 /* rxq/txq helper functions *************************************************/
456 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
457 {
458         return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
459 }
460 
461 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
462 {
463         return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
464 }
465 
466 static void rxq_enable(struct rx_queue *rxq)
467 {
468         struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
469         wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
470 }
471 
472 static void rxq_disable(struct rx_queue *rxq)
473 {
474         struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
475         u8 mask = 1 << rxq->index;
476 
477         wrlp(mp, RXQ_COMMAND, mask << 8);
478         while (rdlp(mp, RXQ_COMMAND) & mask)
479                 udelay(10);
480 }
481 
482 static void txq_reset_hw_ptr(struct tx_queue *txq)
483 {
484         struct mv643xx_eth_private *mp = txq_to_mp(txq);
485         u32 addr;
486 
487         addr = (u32)txq->tx_desc_dma;
488         addr += txq->tx_curr_desc * sizeof(struct tx_desc);
489         wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
490 }
491 
492 static void txq_enable(struct tx_queue *txq)
493 {
494         struct mv643xx_eth_private *mp = txq_to_mp(txq);
495         wrlp(mp, TXQ_COMMAND, 1 << txq->index);
496 }
497 
498 static void txq_disable(struct tx_queue *txq)
499 {
500         struct mv643xx_eth_private *mp = txq_to_mp(txq);
501         u8 mask = 1 << txq->index;
502 
503         wrlp(mp, TXQ_COMMAND, mask << 8);
504         while (rdlp(mp, TXQ_COMMAND) & mask)
505                 udelay(10);
506 }
507 
508 static void txq_maybe_wake(struct tx_queue *txq)
509 {
510         struct mv643xx_eth_private *mp = txq_to_mp(txq);
511         struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
512 
513         if (netif_tx_queue_stopped(nq)) {
514                 __netif_tx_lock(nq, smp_processor_id());
515                 if (txq->tx_desc_count <= txq->tx_wake_threshold)
516                         netif_tx_wake_queue(nq);
517                 __netif_tx_unlock(nq);
518         }
519 }
520 
521 static int rxq_process(struct rx_queue *rxq, int budget)
522 {
523         struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
524         struct net_device_stats *stats = &mp->dev->stats;
525         int rx;
526 
527         rx = 0;
528         while (rx < budget && rxq->rx_desc_count) {
529                 struct rx_desc *rx_desc;
530                 unsigned int cmd_sts;
531                 struct sk_buff *skb;
532                 u16 byte_cnt;
533 
534                 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
535 
536                 cmd_sts = rx_desc->cmd_sts;
537                 if (cmd_sts & BUFFER_OWNED_BY_DMA)
538                         break;
539                 rmb();
540 
541                 skb = rxq->rx_skb[rxq->rx_curr_desc];
542                 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
543 
544                 rxq->rx_curr_desc++;
545                 if (rxq->rx_curr_desc == rxq->rx_ring_size)
546                         rxq->rx_curr_desc = 0;
547 
548                 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
549                                  rx_desc->buf_size, DMA_FROM_DEVICE);
550                 rxq->rx_desc_count--;
551                 rx++;
552 
553                 mp->work_rx_refill |= 1 << rxq->index;
554 
555                 byte_cnt = rx_desc->byte_cnt;
556 
557                 /*
558                  * Update statistics.
559                  *
560                  * Note that the descriptor byte count includes 2 dummy
561                  * bytes automatically inserted by the hardware at the
562                  * start of the packet (which we don't count), and a 4
563                  * byte CRC at the end of the packet (which we do count).
564                  */
565                 stats->rx_packets++;
566                 stats->rx_bytes += byte_cnt - 2;
567 
568                 /*
569                  * In case we received a packet without first / last bits
570                  * on, or the error summary bit is set, the packet needs
571                  * to be dropped.
572                  */
573                 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
574                         != (RX_FIRST_DESC | RX_LAST_DESC))
575                         goto err;
576 
577                 /*
578                  * The -4 is for the CRC in the trailer of the
579                  * received packet
580                  */
581                 skb_put(skb, byte_cnt - 2 - 4);
582 
583                 if (cmd_sts & LAYER_4_CHECKSUM_OK)
584                         skb->ip_summed = CHECKSUM_UNNECESSARY;
585                 skb->protocol = eth_type_trans(skb, mp->dev);
586 
587                 napi_gro_receive(&mp->napi, skb);
588 
589                 continue;
590 
591 err:
592                 stats->rx_dropped++;
593 
594                 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
595                         (RX_FIRST_DESC | RX_LAST_DESC)) {
596                         if (net_ratelimit())
597                                 netdev_err(mp->dev,
598                                            "received packet spanning multiple descriptors\n");
599                 }
600 
601                 if (cmd_sts & ERROR_SUMMARY)
602                         stats->rx_errors++;
603 
604                 dev_kfree_skb(skb);
605         }
606 
607         if (rx < budget)
608                 mp->work_rx &= ~(1 << rxq->index);
609 
610         return rx;
611 }
612 
613 static int rxq_refill(struct rx_queue *rxq, int budget)
614 {
615         struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
616         int refilled;
617 
618         refilled = 0;
619         while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
620                 struct sk_buff *skb;
621                 int rx;
622                 struct rx_desc *rx_desc;
623                 int size;
624 
625                 skb = netdev_alloc_skb(mp->dev, mp->skb_size);
626 
627                 if (skb == NULL) {
628                         mp->oom = 1;
629                         goto oom;
630                 }
631 
632                 if (SKB_DMA_REALIGN)
633                         skb_reserve(skb, SKB_DMA_REALIGN);
634 
635                 refilled++;
636                 rxq->rx_desc_count++;
637 
638                 rx = rxq->rx_used_desc++;
639                 if (rxq->rx_used_desc == rxq->rx_ring_size)
640                         rxq->rx_used_desc = 0;
641 
642                 rx_desc = rxq->rx_desc_area + rx;
643 
644                 size = skb_end_pointer(skb) - skb->data;
645                 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
646                                                   skb->data, size,
647                                                   DMA_FROM_DEVICE);
648                 rx_desc->buf_size = size;
649                 rxq->rx_skb[rx] = skb;
650                 wmb();
651                 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
652                 wmb();
653 
654                 /*
655                  * The hardware automatically prepends 2 bytes of
656                  * dummy data to each received packet, so that the
657                  * IP header ends up 16-byte aligned.
658                  */
659                 skb_reserve(skb, 2);
660         }
661 
662         if (refilled < budget)
663                 mp->work_rx_refill &= ~(1 << rxq->index);
664 
665 oom:
666         return refilled;
667 }
668 
669 
670 /* tx ***********************************************************************/
671 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
672 {
673         int frag;
674 
675         for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
676                 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
677 
678                 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7)
679                         return 1;
680         }
681 
682         return 0;
683 }
684 
685 static inline __be16 sum16_as_be(__sum16 sum)
686 {
687         return (__force __be16)sum;
688 }
689 
690 static int skb_tx_csum(struct mv643xx_eth_private *mp, struct sk_buff *skb,
691                        u16 *l4i_chk, u32 *command, int length)
692 {
693         int ret;
694         u32 cmd = 0;
695 
696         if (skb->ip_summed == CHECKSUM_PARTIAL) {
697                 int hdr_len;
698                 int tag_bytes;
699 
700                 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
701                        skb->protocol != htons(ETH_P_8021Q));
702 
703                 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
704                 tag_bytes = hdr_len - ETH_HLEN;
705 
706                 if (length - hdr_len > mp->shared->tx_csum_limit ||
707                     unlikely(tag_bytes & ~12)) {
708                         ret = skb_checksum_help(skb);
709                         if (!ret)
710                                 goto no_csum;
711                         return ret;
712                 }
713 
714                 if (tag_bytes & 4)
715                         cmd |= MAC_HDR_EXTRA_4_BYTES;
716                 if (tag_bytes & 8)
717                         cmd |= MAC_HDR_EXTRA_8_BYTES;
718 
719                 cmd |= GEN_TCP_UDP_CHECKSUM | GEN_TCP_UDP_CHK_FULL |
720                            GEN_IP_V4_CHECKSUM   |
721                            ip_hdr(skb)->ihl << TX_IHL_SHIFT;
722 
723                 /* TODO: Revisit this. With the usage of GEN_TCP_UDP_CHK_FULL
724                  * it seems we don't need to pass the initial checksum. */
725                 switch (ip_hdr(skb)->protocol) {
726                 case IPPROTO_UDP:
727                         cmd |= UDP_FRAME;
728                         *l4i_chk = 0;
729                         break;
730                 case IPPROTO_TCP:
731                         *l4i_chk = 0;
732                         break;
733                 default:
734                         WARN(1, "protocol not supported");
735                 }
736         } else {
737 no_csum:
738                 /* Errata BTS #50, IHL must be 5 if no HW checksum */
739                 cmd |= 5 << TX_IHL_SHIFT;
740         }
741         *command = cmd;
742         return 0;
743 }
744 
745 static inline int
746 txq_put_data_tso(struct net_device *dev, struct tx_queue *txq,
747                  struct sk_buff *skb, char *data, int length,
748                  bool last_tcp, bool is_last)
749 {
750         int tx_index;
751         u32 cmd_sts;
752         struct tx_desc *desc;
753 
754         tx_index = txq->tx_curr_desc++;
755         if (txq->tx_curr_desc == txq->tx_ring_size)
756                 txq->tx_curr_desc = 0;
757         desc = &txq->tx_desc_area[tx_index];
758         txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
759 
760         desc->l4i_chk = 0;
761         desc->byte_cnt = length;
762 
763         if (length <= 8 && (uintptr_t)data & 0x7) {
764                 /* Copy unaligned small data fragment to TSO header data area */
765                 memcpy(txq->tso_hdrs + tx_index * TSO_HEADER_SIZE,
766                        data, length);
767                 desc->buf_ptr = txq->tso_hdrs_dma
768                         + tx_index * TSO_HEADER_SIZE;
769         } else {
770                 /* Alignment is okay, map buffer and hand off to hardware */
771                 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
772                 desc->buf_ptr = dma_map_single(dev->dev.parent, data,
773                         length, DMA_TO_DEVICE);
774                 if (unlikely(dma_mapping_error(dev->dev.parent,
775                                                desc->buf_ptr))) {
776                         WARN(1, "dma_map_single failed!\n");
777                         return -ENOMEM;
778                 }
779         }
780 
781         cmd_sts = BUFFER_OWNED_BY_DMA;
782         if (last_tcp) {
783                 /* last descriptor in the TCP packet */
784                 cmd_sts |= ZERO_PADDING | TX_LAST_DESC;
785                 /* last descriptor in SKB */
786                 if (is_last)
787                         cmd_sts |= TX_ENABLE_INTERRUPT;
788         }
789         desc->cmd_sts = cmd_sts;
790         return 0;
791 }
792 
793 static inline void
794 txq_put_hdr_tso(struct sk_buff *skb, struct tx_queue *txq, int length,
795                 u32 *first_cmd_sts, bool first_desc)
796 {
797         struct mv643xx_eth_private *mp = txq_to_mp(txq);
798         int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
799         int tx_index;
800         struct tx_desc *desc;
801         int ret;
802         u32 cmd_csum = 0;
803         u16 l4i_chk = 0;
804         u32 cmd_sts;
805 
806         tx_index = txq->tx_curr_desc;
807         desc = &txq->tx_desc_area[tx_index];
808 
809         ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_csum, length);
810         if (ret)
811                 WARN(1, "failed to prepare checksum!");
812 
813         /* Should we set this? Can't use the value from skb_tx_csum()
814          * as it's not the correct initial L4 checksum to use. */
815         desc->l4i_chk = 0;
816 
817         desc->byte_cnt = hdr_len;
818         desc->buf_ptr = txq->tso_hdrs_dma +
819                         txq->tx_curr_desc * TSO_HEADER_SIZE;
820         cmd_sts = cmd_csum | BUFFER_OWNED_BY_DMA  | TX_FIRST_DESC |
821                                    GEN_CRC;
822 
823         /* Defer updating the first command descriptor until all
824          * following descriptors have been written.
825          */
826         if (first_desc)
827                 *first_cmd_sts = cmd_sts;
828         else
829                 desc->cmd_sts = cmd_sts;
830 
831         txq->tx_curr_desc++;
832         if (txq->tx_curr_desc == txq->tx_ring_size)
833                 txq->tx_curr_desc = 0;
834 }
835 
836 static int txq_submit_tso(struct tx_queue *txq, struct sk_buff *skb,
837                           struct net_device *dev)
838 {
839         struct mv643xx_eth_private *mp = txq_to_mp(txq);
840         int total_len, data_left, ret;
841         int desc_count = 0;
842         struct tso_t tso;
843         int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
844         struct tx_desc *first_tx_desc;
845         u32 first_cmd_sts = 0;
846 
847         /* Count needed descriptors */
848         if ((txq->tx_desc_count + tso_count_descs(skb)) >= txq->tx_ring_size) {
849                 netdev_dbg(dev, "not enough descriptors for TSO!\n");
850                 return -EBUSY;
851         }
852 
853         first_tx_desc = &txq->tx_desc_area[txq->tx_curr_desc];
854 
855         /* Initialize the TSO handler, and prepare the first payload */
856         tso_start(skb, &tso);
857 
858         total_len = skb->len - hdr_len;
859         while (total_len > 0) {
860                 bool first_desc = (desc_count == 0);
861                 char *hdr;
862 
863                 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
864                 total_len -= data_left;
865                 desc_count++;
866 
867                 /* prepare packet headers: MAC + IP + TCP */
868                 hdr = txq->tso_hdrs + txq->tx_curr_desc * TSO_HEADER_SIZE;
869                 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
870                 txq_put_hdr_tso(skb, txq, data_left, &first_cmd_sts,
871                                 first_desc);
872 
873                 while (data_left > 0) {
874                         int size;
875                         desc_count++;
876 
877                         size = min_t(int, tso.size, data_left);
878                         ret = txq_put_data_tso(dev, txq, skb, tso.data, size,
879                                                size == data_left,
880                                                total_len == 0);
881                         if (ret)
882                                 goto err_release;
883                         data_left -= size;
884                         tso_build_data(skb, &tso, size);
885                 }
886         }
887 
888         __skb_queue_tail(&txq->tx_skb, skb);
889         skb_tx_timestamp(skb);
890 
891         /* ensure all other descriptors are written before first cmd_sts */
892         wmb();
893         first_tx_desc->cmd_sts = first_cmd_sts;
894 
895         /* clear TX_END status */
896         mp->work_tx_end &= ~(1 << txq->index);
897 
898         /* ensure all descriptors are written before poking hardware */
899         wmb();
900         txq_enable(txq);
901         txq->tx_desc_count += desc_count;
902         return 0;
903 err_release:
904         /* TODO: Release all used data descriptors; header descriptors must not
905          * be DMA-unmapped.
906          */
907         return ret;
908 }
909 
910 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
911 {
912         struct mv643xx_eth_private *mp = txq_to_mp(txq);
913         int nr_frags = skb_shinfo(skb)->nr_frags;
914         int frag;
915 
916         for (frag = 0; frag < nr_frags; frag++) {
917                 skb_frag_t *this_frag;
918                 int tx_index;
919                 struct tx_desc *desc;
920 
921                 this_frag = &skb_shinfo(skb)->frags[frag];
922                 tx_index = txq->tx_curr_desc++;
923                 if (txq->tx_curr_desc == txq->tx_ring_size)
924                         txq->tx_curr_desc = 0;
925                 desc = &txq->tx_desc_area[tx_index];
926                 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_PAGE;
927 
928                 /*
929                  * The last fragment will generate an interrupt
930                  * which will free the skb on TX completion.
931                  */
932                 if (frag == nr_frags - 1) {
933                         desc->cmd_sts = BUFFER_OWNED_BY_DMA |
934                                         ZERO_PADDING | TX_LAST_DESC |
935                                         TX_ENABLE_INTERRUPT;
936                 } else {
937                         desc->cmd_sts = BUFFER_OWNED_BY_DMA;
938                 }
939 
940                 desc->l4i_chk = 0;
941                 desc->byte_cnt = skb_frag_size(this_frag);
942                 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
943                                                  this_frag, 0, desc->byte_cnt,
944                                                  DMA_TO_DEVICE);
945         }
946 }
947 
948 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb,
949                           struct net_device *dev)
950 {
951         struct mv643xx_eth_private *mp = txq_to_mp(txq);
952         int nr_frags = skb_shinfo(skb)->nr_frags;
953         int tx_index;
954         struct tx_desc *desc;
955         u32 cmd_sts;
956         u16 l4i_chk;
957         int length, ret;
958 
959         cmd_sts = 0;
960         l4i_chk = 0;
961 
962         if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
963                 if (net_ratelimit())
964                         netdev_err(dev, "tx queue full?!\n");
965                 return -EBUSY;
966         }
967 
968         ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_sts, skb->len);
969         if (ret)
970                 return ret;
971         cmd_sts |= TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
972 
973         tx_index = txq->tx_curr_desc++;
974         if (txq->tx_curr_desc == txq->tx_ring_size)
975                 txq->tx_curr_desc = 0;
976         desc = &txq->tx_desc_area[tx_index];
977         txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
978 
979         if (nr_frags) {
980                 txq_submit_frag_skb(txq, skb);
981                 length = skb_headlen(skb);
982         } else {
983                 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
984                 length = skb->len;
985         }
986 
987         desc->l4i_chk = l4i_chk;
988         desc->byte_cnt = length;
989         desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
990                                        length, DMA_TO_DEVICE);
991 
992         __skb_queue_tail(&txq->tx_skb, skb);
993 
994         skb_tx_timestamp(skb);
995 
996         /* ensure all other descriptors are written before first cmd_sts */
997         wmb();
998         desc->cmd_sts = cmd_sts;
999 
1000         /* clear TX_END status */
1001         mp->work_tx_end &= ~(1 << txq->index);
1002 
1003         /* ensure all descriptors are written before poking hardware */
1004         wmb();
1005         txq_enable(txq);
1006 
1007         txq->tx_desc_count += nr_frags + 1;
1008 
1009         return 0;
1010 }
1011 
1012 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1013 {
1014         struct mv643xx_eth_private *mp = netdev_priv(dev);
1015         int length, queue, ret;
1016         struct tx_queue *txq;
1017         struct netdev_queue *nq;
1018 
1019         queue = skb_get_queue_mapping(skb);
1020         txq = mp->txq + queue;
1021         nq = netdev_get_tx_queue(dev, queue);
1022 
1023         if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
1024                 netdev_printk(KERN_DEBUG, dev,
1025                               "failed to linearize skb with tiny unaligned fragment\n");
1026                 return NETDEV_TX_BUSY;
1027         }
1028 
1029         length = skb->len;
1030 
1031         if (skb_is_gso(skb))
1032                 ret = txq_submit_tso(txq, skb, dev);
1033         else
1034                 ret = txq_submit_skb(txq, skb, dev);
1035         if (!ret) {
1036                 txq->tx_bytes += length;
1037                 txq->tx_packets++;
1038 
1039                 if (txq->tx_desc_count >= txq->tx_stop_threshold)
1040                         netif_tx_stop_queue(nq);
1041         } else {
1042                 txq->tx_dropped++;
1043                 dev_kfree_skb_any(skb);
1044         }
1045 
1046         return NETDEV_TX_OK;
1047 }
1048 
1049 
1050 /* tx napi ******************************************************************/
1051 static void txq_kick(struct tx_queue *txq)
1052 {
1053         struct mv643xx_eth_private *mp = txq_to_mp(txq);
1054         struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1055         u32 hw_desc_ptr;
1056         u32 expected_ptr;
1057 
1058         __netif_tx_lock(nq, smp_processor_id());
1059 
1060         if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1061                 goto out;
1062 
1063         hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1064         expected_ptr = (u32)txq->tx_desc_dma +
1065                                 txq->tx_curr_desc * sizeof(struct tx_desc);
1066 
1067         if (hw_desc_ptr != expected_ptr)
1068                 txq_enable(txq);
1069 
1070 out:
1071         __netif_tx_unlock(nq);
1072 
1073         mp->work_tx_end &= ~(1 << txq->index);
1074 }
1075 
1076 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
1077 {
1078         struct mv643xx_eth_private *mp = txq_to_mp(txq);
1079         struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1080         int reclaimed;
1081 
1082         __netif_tx_lock_bh(nq);
1083 
1084         reclaimed = 0;
1085         while (reclaimed < budget && txq->tx_desc_count > 0) {
1086                 int tx_index;
1087                 struct tx_desc *desc;
1088                 u32 cmd_sts;
1089                 char desc_dma_map;
1090 
1091                 tx_index = txq->tx_used_desc;
1092                 desc = &txq->tx_desc_area[tx_index];
1093                 desc_dma_map = txq->tx_desc_mapping[tx_index];
1094 
1095                 cmd_sts = desc->cmd_sts;
1096 
1097                 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1098                         if (!force)
1099                                 break;
1100                         desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1101                 }
1102 
1103                 txq->tx_used_desc = tx_index + 1;
1104                 if (txq->tx_used_desc == txq->tx_ring_size)
1105                         txq->tx_used_desc = 0;
1106 
1107                 reclaimed++;
1108                 txq->tx_desc_count--;
1109 
1110                 if (!IS_TSO_HEADER(txq, desc->buf_ptr)) {
1111 
1112                         if (desc_dma_map == DESC_DMA_MAP_PAGE)
1113                                 dma_unmap_page(mp->dev->dev.parent,
1114                                                desc->buf_ptr,
1115                                                desc->byte_cnt,
1116                                                DMA_TO_DEVICE);
1117                         else
1118                                 dma_unmap_single(mp->dev->dev.parent,
1119                                                  desc->buf_ptr,
1120                                                  desc->byte_cnt,
1121                                                  DMA_TO_DEVICE);
1122                 }
1123 
1124                 if (cmd_sts & TX_ENABLE_INTERRUPT) {
1125                         struct sk_buff *skb = __skb_dequeue(&txq->tx_skb);
1126 
1127                         if (!WARN_ON(!skb))
1128                                 dev_kfree_skb(skb);
1129                 }
1130 
1131                 if (cmd_sts & ERROR_SUMMARY) {
1132                         netdev_info(mp->dev, "tx error\n");
1133                         mp->dev->stats.tx_errors++;
1134                 }
1135 
1136         }
1137 
1138         __netif_tx_unlock_bh(nq);
1139 
1140         if (reclaimed < budget)
1141                 mp->work_tx &= ~(1 << txq->index);
1142 
1143         return reclaimed;
1144 }
1145 
1146 
1147 /* tx rate control **********************************************************/
1148 /*
1149  * Set total maximum TX rate (shared by all TX queues for this port)
1150  * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
1151  */
1152 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
1153 {
1154         int token_rate;
1155         int mtu;
1156         int bucket_size;
1157 
1158         token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1159         if (token_rate > 1023)
1160                 token_rate = 1023;
1161 
1162         mtu = (mp->dev->mtu + 255) >> 8;
1163         if (mtu > 63)
1164                 mtu = 63;
1165 
1166         bucket_size = (burst + 255) >> 8;
1167         if (bucket_size > 65535)
1168                 bucket_size = 65535;
1169 
1170         switch (mp->shared->tx_bw_control) {
1171         case TX_BW_CONTROL_OLD_LAYOUT:
1172                 wrlp(mp, TX_BW_RATE, token_rate);
1173                 wrlp(mp, TX_BW_MTU, mtu);
1174                 wrlp(mp, TX_BW_BURST, bucket_size);
1175                 break;
1176         case TX_BW_CONTROL_NEW_LAYOUT:
1177                 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1178                 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1179                 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
1180                 break;
1181         }
1182 }
1183 
1184 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1185 {
1186         struct mv643xx_eth_private *mp = txq_to_mp(txq);
1187         int token_rate;
1188         int bucket_size;
1189 
1190         token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1191         if (token_rate > 1023)
1192                 token_rate = 1023;
1193 
1194         bucket_size = (burst + 255) >> 8;
1195         if (bucket_size > 65535)
1196                 bucket_size = 65535;
1197 
1198         wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1199         wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
1200 }
1201 
1202 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1203 {
1204         struct mv643xx_eth_private *mp = txq_to_mp(txq);
1205         int off;
1206         u32 val;
1207 
1208         /*
1209          * Turn on fixed priority mode.
1210          */
1211         off = 0;
1212         switch (mp->shared->tx_bw_control) {
1213         case TX_BW_CONTROL_OLD_LAYOUT:
1214                 off = TXQ_FIX_PRIO_CONF;
1215                 break;
1216         case TX_BW_CONTROL_NEW_LAYOUT:
1217                 off = TXQ_FIX_PRIO_CONF_MOVED;
1218                 break;
1219         }
1220 
1221         if (off) {
1222                 val = rdlp(mp, off);
1223                 val |= 1 << txq->index;
1224                 wrlp(mp, off, val);
1225         }
1226 }
1227 
1228 
1229 /* mii management interface *************************************************/
1230 static void mv643xx_eth_adjust_link(struct net_device *dev)
1231 {
1232         struct mv643xx_eth_private *mp = netdev_priv(dev);
1233         u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
1234         u32 autoneg_disable = FORCE_LINK_PASS |
1235                      DISABLE_AUTO_NEG_SPEED_GMII |
1236                      DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1237                      DISABLE_AUTO_NEG_FOR_DUPLEX;
1238 
1239         if (mp->phy->autoneg == AUTONEG_ENABLE) {
1240                 /* enable auto negotiation */
1241                 pscr &= ~autoneg_disable;
1242                 goto out_write;
1243         }
1244 
1245         pscr |= autoneg_disable;
1246 
1247         if (mp->phy->speed == SPEED_1000) {
1248                 /* force gigabit, half duplex not supported */
1249                 pscr |= SET_GMII_SPEED_TO_1000;
1250                 pscr |= SET_FULL_DUPLEX_MODE;
1251                 goto out_write;
1252         }
1253 
1254         pscr &= ~SET_GMII_SPEED_TO_1000;
1255 
1256         if (mp->phy->speed == SPEED_100)
1257                 pscr |= SET_MII_SPEED_TO_100;
1258         else
1259                 pscr &= ~SET_MII_SPEED_TO_100;
1260 
1261         if (mp->phy->duplex == DUPLEX_FULL)
1262                 pscr |= SET_FULL_DUPLEX_MODE;
1263         else
1264                 pscr &= ~SET_FULL_DUPLEX_MODE;
1265 
1266 out_write:
1267         wrlp(mp, PORT_SERIAL_CONTROL, pscr);
1268 }
1269 
1270 /* statistics ***************************************************************/
1271 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1272 {
1273         struct mv643xx_eth_private *mp = netdev_priv(dev);
1274         struct net_device_stats *stats = &dev->stats;
1275         unsigned long tx_packets = 0;
1276         unsigned long tx_bytes = 0;
1277         unsigned long tx_dropped = 0;
1278         int i;
1279 
1280         for (i = 0; i < mp->txq_count; i++) {
1281                 struct tx_queue *txq = mp->txq + i;
1282 
1283                 tx_packets += txq->tx_packets;
1284                 tx_bytes += txq->tx_bytes;
1285                 tx_dropped += txq->tx_dropped;
1286         }
1287 
1288         stats->tx_packets = tx_packets;
1289         stats->tx_bytes = tx_bytes;
1290         stats->tx_dropped = tx_dropped;
1291 
1292         return stats;
1293 }
1294 
1295 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1296 {
1297         return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1298 }
1299 
1300 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1301 {
1302         int i;
1303 
1304         for (i = 0; i < 0x80; i += 4)
1305                 mib_read(mp, i);
1306 
1307         /* Clear non MIB hw counters also */
1308         rdlp(mp, RX_DISCARD_FRAME_CNT);
1309         rdlp(mp, RX_OVERRUN_FRAME_CNT);
1310 }
1311 
1312 static void mib_counters_update(struct mv643xx_eth_private *mp)
1313 {
1314         struct mib_counters *p = &mp->mib_counters;
1315 
1316         spin_lock_bh(&mp->mib_counters_lock);
1317         p->good_octets_received += mib_read(mp, 0x00);
1318         p->bad_octets_received += mib_read(mp, 0x08);
1319         p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1320         p->good_frames_received += mib_read(mp, 0x10);
1321         p->bad_frames_received += mib_read(mp, 0x14);
1322         p->broadcast_frames_received += mib_read(mp, 0x18);
1323         p->multicast_frames_received += mib_read(mp, 0x1c);
1324         p->frames_64_octets += mib_read(mp, 0x20);
1325         p->frames_65_to_127_octets += mib_read(mp, 0x24);
1326         p->frames_128_to_255_octets += mib_read(mp, 0x28);
1327         p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1328         p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1329         p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1330         p->good_octets_sent += mib_read(mp, 0x38);
1331         p->good_frames_sent += mib_read(mp, 0x40);
1332         p->excessive_collision += mib_read(mp, 0x44);
1333         p->multicast_frames_sent += mib_read(mp, 0x48);
1334         p->broadcast_frames_sent += mib_read(mp, 0x4c);
1335         p->unrec_mac_control_received += mib_read(mp, 0x50);
1336         p->fc_sent += mib_read(mp, 0x54);
1337         p->good_fc_received += mib_read(mp, 0x58);
1338         p->bad_fc_received += mib_read(mp, 0x5c);
1339         p->undersize_received += mib_read(mp, 0x60);
1340         p->fragments_received += mib_read(mp, 0x64);
1341         p->oversize_received += mib_read(mp, 0x68);
1342         p->jabber_received += mib_read(mp, 0x6c);
1343         p->mac_receive_error += mib_read(mp, 0x70);
1344         p->bad_crc_event += mib_read(mp, 0x74);
1345         p->collision += mib_read(mp, 0x78);
1346         p->late_collision += mib_read(mp, 0x7c);
1347         /* Non MIB hardware counters */
1348         p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1349         p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
1350         spin_unlock_bh(&mp->mib_counters_lock);
1351 }
1352 
1353 static void mib_counters_timer_wrapper(unsigned long _mp)
1354 {
1355         struct mv643xx_eth_private *mp = (void *)_mp;
1356         mib_counters_update(mp);
1357         mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1358 }
1359 
1360 
1361 /* interrupt coalescing *****************************************************/
1362 /*
1363  * Hardware coalescing parameters are set in units of 64 t_clk
1364  * cycles.  I.e.:
1365  *
1366  *      coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1367  *
1368  *      register_value = coal_delay_in_usec * t_clk_rate / 64000000
1369  *
1370  * In the ->set*() methods, we round the computed register value
1371  * to the nearest integer.
1372  */
1373 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1374 {
1375         u32 val = rdlp(mp, SDMA_CONFIG);
1376         u64 temp;
1377 
1378         if (mp->shared->extended_rx_coal_limit)
1379                 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1380         else
1381                 temp = (val & 0x003fff00) >> 8;
1382 
1383         temp *= 64000000;
1384         temp += mp->t_clk / 2;
1385         do_div(temp, mp->t_clk);
1386 
1387         return (unsigned int)temp;
1388 }
1389 
1390 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1391 {
1392         u64 temp;
1393         u32 val;
1394 
1395         temp = (u64)usec * mp->t_clk;
1396         temp += 31999999;
1397         do_div(temp, 64000000);
1398 
1399         val = rdlp(mp, SDMA_CONFIG);
1400         if (mp->shared->extended_rx_coal_limit) {
1401                 if (temp > 0xffff)
1402                         temp = 0xffff;
1403                 val &= ~0x023fff80;
1404                 val |= (temp & 0x8000) << 10;
1405                 val |= (temp & 0x7fff) << 7;
1406         } else {
1407                 if (temp > 0x3fff)
1408                         temp = 0x3fff;
1409                 val &= ~0x003fff00;
1410                 val |= (temp & 0x3fff) << 8;
1411         }
1412         wrlp(mp, SDMA_CONFIG, val);
1413 }
1414 
1415 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1416 {
1417         u64 temp;
1418 
1419         temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1420         temp *= 64000000;
1421         temp += mp->t_clk / 2;
1422         do_div(temp, mp->t_clk);
1423 
1424         return (unsigned int)temp;
1425 }
1426 
1427 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1428 {
1429         u64 temp;
1430 
1431         temp = (u64)usec * mp->t_clk;
1432         temp += 31999999;
1433         do_div(temp, 64000000);
1434 
1435         if (temp > 0x3fff)
1436                 temp = 0x3fff;
1437 
1438         wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1439 }
1440 
1441 
1442 /* ethtool ******************************************************************/
1443 struct mv643xx_eth_stats {
1444         char stat_string[ETH_GSTRING_LEN];
1445         int sizeof_stat;
1446         int netdev_off;
1447         int mp_off;
1448 };
1449 
1450 #define SSTAT(m)                                                \
1451         { #m, FIELD_SIZEOF(struct net_device_stats, m),         \
1452           offsetof(struct net_device, stats.m), -1 }
1453 
1454 #define MIBSTAT(m)                                              \
1455         { #m, FIELD_SIZEOF(struct mib_counters, m),             \
1456           -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1457 
1458 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1459         SSTAT(rx_packets),
1460         SSTAT(tx_packets),
1461         SSTAT(rx_bytes),
1462         SSTAT(tx_bytes),
1463         SSTAT(rx_errors),
1464         SSTAT(tx_errors),
1465         SSTAT(rx_dropped),
1466         SSTAT(tx_dropped),
1467         MIBSTAT(good_octets_received),
1468         MIBSTAT(bad_octets_received),
1469         MIBSTAT(internal_mac_transmit_err),
1470         MIBSTAT(good_frames_received),
1471         MIBSTAT(bad_frames_received),
1472         MIBSTAT(broadcast_frames_received),
1473         MIBSTAT(multicast_frames_received),
1474         MIBSTAT(frames_64_octets),
1475         MIBSTAT(frames_65_to_127_octets),
1476         MIBSTAT(frames_128_to_255_octets),
1477         MIBSTAT(frames_256_to_511_octets),
1478         MIBSTAT(frames_512_to_1023_octets),
1479         MIBSTAT(frames_1024_to_max_octets),
1480         MIBSTAT(good_octets_sent),
1481         MIBSTAT(good_frames_sent),
1482         MIBSTAT(excessive_collision),
1483         MIBSTAT(multicast_frames_sent),
1484         MIBSTAT(broadcast_frames_sent),
1485         MIBSTAT(unrec_mac_control_received),
1486         MIBSTAT(fc_sent),
1487         MIBSTAT(good_fc_received),
1488         MIBSTAT(bad_fc_received),
1489         MIBSTAT(undersize_received),
1490         MIBSTAT(fragments_received),
1491         MIBSTAT(oversize_received),
1492         MIBSTAT(jabber_received),
1493         MIBSTAT(mac_receive_error),
1494         MIBSTAT(bad_crc_event),
1495         MIBSTAT(collision),
1496         MIBSTAT(late_collision),
1497         MIBSTAT(rx_discard),
1498         MIBSTAT(rx_overrun),
1499 };
1500 
1501 static int
1502 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1503                              struct ethtool_cmd *cmd)
1504 {
1505         int err;
1506 
1507         err = phy_read_status(mp->phy);
1508         if (err == 0)
1509                 err = phy_ethtool_gset(mp->phy, cmd);
1510 
1511         /*
1512          * The MAC does not support 1000baseT_Half.
1513          */
1514         cmd->supported &= ~SUPPORTED_1000baseT_Half;
1515         cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1516 
1517         return err;
1518 }
1519 
1520 static int
1521 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
1522                                  struct ethtool_cmd *cmd)
1523 {
1524         u32 port_status;
1525 
1526         port_status = rdlp(mp, PORT_STATUS);
1527 
1528         cmd->supported = SUPPORTED_MII;
1529         cmd->advertising = ADVERTISED_MII;
1530         switch (port_status & PORT_SPEED_MASK) {
1531         case PORT_SPEED_10:
1532                 ethtool_cmd_speed_set(cmd, SPEED_10);
1533                 break;
1534         case PORT_SPEED_100:
1535                 ethtool_cmd_speed_set(cmd, SPEED_100);
1536                 break;
1537         case PORT_SPEED_1000:
1538                 ethtool_cmd_speed_set(cmd, SPEED_1000);
1539                 break;
1540         default:
1541                 cmd->speed = -1;
1542                 break;
1543         }
1544         cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1545         cmd->port = PORT_MII;
1546         cmd->phy_address = 0;
1547         cmd->transceiver = XCVR_INTERNAL;
1548         cmd->autoneg = AUTONEG_DISABLE;
1549         cmd->maxtxpkt = 1;
1550         cmd->maxrxpkt = 1;
1551 
1552         return 0;
1553 }
1554 
1555 static void
1556 mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1557 {
1558         struct mv643xx_eth_private *mp = netdev_priv(dev);
1559         wol->supported = 0;
1560         wol->wolopts = 0;
1561         if (mp->phy)
1562                 phy_ethtool_get_wol(mp->phy, wol);
1563 }
1564 
1565 static int
1566 mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1567 {
1568         struct mv643xx_eth_private *mp = netdev_priv(dev);
1569         int err;
1570 
1571         if (mp->phy == NULL)
1572                 return -EOPNOTSUPP;
1573 
1574         err = phy_ethtool_set_wol(mp->phy, wol);
1575         /* Given that mv643xx_eth works without the marvell-specific PHY driver,
1576          * this debugging hint is useful to have.
1577          */
1578         if (err == -EOPNOTSUPP)
1579                 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n");
1580         return err;
1581 }
1582 
1583 static int
1584 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1585 {
1586         struct mv643xx_eth_private *mp = netdev_priv(dev);
1587 
1588         if (mp->phy != NULL)
1589                 return mv643xx_eth_get_settings_phy(mp, cmd);
1590         else
1591                 return mv643xx_eth_get_settings_phyless(mp, cmd);
1592 }
1593 
1594 static int
1595 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1596 {
1597         struct mv643xx_eth_private *mp = netdev_priv(dev);
1598         int ret;
1599 
1600         if (mp->phy == NULL)
1601                 return -EINVAL;
1602 
1603         /*
1604          * The MAC does not support 1000baseT_Half.
1605          */
1606         cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1607 
1608         ret = phy_ethtool_sset(mp->phy, cmd);
1609         if (!ret)
1610                 mv643xx_eth_adjust_link(dev);
1611         return ret;
1612 }
1613 
1614 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1615                                     struct ethtool_drvinfo *drvinfo)
1616 {
1617         strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1618                 sizeof(drvinfo->driver));
1619         strlcpy(drvinfo->version, mv643xx_eth_driver_version,
1620                 sizeof(drvinfo->version));
1621         strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1622         strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
1623 }
1624 
1625 static int mv643xx_eth_nway_reset(struct net_device *dev)
1626 {
1627         struct mv643xx_eth_private *mp = netdev_priv(dev);
1628 
1629         if (mp->phy == NULL)
1630                 return -EINVAL;
1631 
1632         return genphy_restart_aneg(mp->phy);
1633 }
1634 
1635 static int
1636 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1637 {
1638         struct mv643xx_eth_private *mp = netdev_priv(dev);
1639 
1640         ec->rx_coalesce_usecs = get_rx_coal(mp);
1641         ec->tx_coalesce_usecs = get_tx_coal(mp);
1642 
1643         return 0;
1644 }
1645 
1646 static int
1647 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1648 {
1649         struct mv643xx_eth_private *mp = netdev_priv(dev);
1650 
1651         set_rx_coal(mp, ec->rx_coalesce_usecs);
1652         set_tx_coal(mp, ec->tx_coalesce_usecs);
1653 
1654         return 0;
1655 }
1656 
1657 static void
1658 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1659 {
1660         struct mv643xx_eth_private *mp = netdev_priv(dev);
1661 
1662         er->rx_max_pending = 4096;
1663         er->tx_max_pending = 4096;
1664 
1665         er->rx_pending = mp->rx_ring_size;
1666         er->tx_pending = mp->tx_ring_size;
1667 }
1668 
1669 static int
1670 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1671 {
1672         struct mv643xx_eth_private *mp = netdev_priv(dev);
1673 
1674         if (er->rx_mini_pending || er->rx_jumbo_pending)
1675                 return -EINVAL;
1676 
1677         mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1678         mp->tx_ring_size = clamp_t(unsigned int, er->tx_pending,
1679                                    MV643XX_MAX_SKB_DESCS * 2, 4096);
1680         if (mp->tx_ring_size != er->tx_pending)
1681                 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
1682                             mp->tx_ring_size, er->tx_pending);
1683 
1684         if (netif_running(dev)) {
1685                 mv643xx_eth_stop(dev);
1686                 if (mv643xx_eth_open(dev)) {
1687                         netdev_err(dev,
1688                                    "fatal error on re-opening device after ring param change\n");
1689                         return -ENOMEM;
1690                 }
1691         }
1692 
1693         return 0;
1694 }
1695 
1696 
1697 static int
1698 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
1699 {
1700         struct mv643xx_eth_private *mp = netdev_priv(dev);
1701         bool rx_csum = features & NETIF_F_RXCSUM;
1702 
1703         wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1704 
1705         return 0;
1706 }
1707 
1708 static void mv643xx_eth_get_strings(struct net_device *dev,
1709                                     uint32_t stringset, uint8_t *data)
1710 {
1711         int i;
1712 
1713         if (stringset == ETH_SS_STATS) {
1714                 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1715                         memcpy(data + i * ETH_GSTRING_LEN,
1716                                 mv643xx_eth_stats[i].stat_string,
1717                                 ETH_GSTRING_LEN);
1718                 }
1719         }
1720 }
1721 
1722 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1723                                           struct ethtool_stats *stats,
1724                                           uint64_t *data)
1725 {
1726         struct mv643xx_eth_private *mp = netdev_priv(dev);
1727         int i;
1728 
1729         mv643xx_eth_get_stats(dev);
1730         mib_counters_update(mp);
1731 
1732         for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1733                 const struct mv643xx_eth_stats *stat;
1734                 void *p;
1735 
1736                 stat = mv643xx_eth_stats + i;
1737 
1738                 if (stat->netdev_off >= 0)
1739                         p = ((void *)mp->dev) + stat->netdev_off;
1740                 else
1741                         p = ((void *)mp) + stat->mp_off;
1742 
1743                 data[i] = (stat->sizeof_stat == 8) ?
1744                                 *(uint64_t *)p : *(uint32_t *)p;
1745         }
1746 }
1747 
1748 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1749 {
1750         if (sset == ETH_SS_STATS)
1751                 return ARRAY_SIZE(mv643xx_eth_stats);
1752 
1753         return -EOPNOTSUPP;
1754 }
1755 
1756 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1757         .get_settings           = mv643xx_eth_get_settings,
1758         .set_settings           = mv643xx_eth_set_settings,
1759         .get_drvinfo            = mv643xx_eth_get_drvinfo,
1760         .nway_reset             = mv643xx_eth_nway_reset,
1761         .get_link               = ethtool_op_get_link,
1762         .get_coalesce           = mv643xx_eth_get_coalesce,
1763         .set_coalesce           = mv643xx_eth_set_coalesce,
1764         .get_ringparam          = mv643xx_eth_get_ringparam,
1765         .set_ringparam          = mv643xx_eth_set_ringparam,
1766         .get_strings            = mv643xx_eth_get_strings,
1767         .get_ethtool_stats      = mv643xx_eth_get_ethtool_stats,
1768         .get_sset_count         = mv643xx_eth_get_sset_count,
1769         .get_ts_info            = ethtool_op_get_ts_info,
1770         .get_wol                = mv643xx_eth_get_wol,
1771         .set_wol                = mv643xx_eth_set_wol,
1772 };
1773 
1774 
1775 /* address handling *********************************************************/
1776 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1777 {
1778         unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1779         unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1780 
1781         addr[0] = (mac_h >> 24) & 0xff;
1782         addr[1] = (mac_h >> 16) & 0xff;
1783         addr[2] = (mac_h >> 8) & 0xff;
1784         addr[3] = mac_h & 0xff;
1785         addr[4] = (mac_l >> 8) & 0xff;
1786         addr[5] = mac_l & 0xff;
1787 }
1788 
1789 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1790 {
1791         wrlp(mp, MAC_ADDR_HIGH,
1792                 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1793         wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1794 }
1795 
1796 static u32 uc_addr_filter_mask(struct net_device *dev)
1797 {
1798         struct netdev_hw_addr *ha;
1799         u32 nibbles;
1800 
1801         if (dev->flags & IFF_PROMISC)
1802                 return 0;
1803 
1804         nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1805         netdev_for_each_uc_addr(ha, dev) {
1806                 if (memcmp(dev->dev_addr, ha->addr, 5))
1807                         return 0;
1808                 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
1809                         return 0;
1810 
1811                 nibbles |= 1 << (ha->addr[5] & 0x0f);
1812         }
1813 
1814         return nibbles;
1815 }
1816 
1817 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1818 {
1819         struct mv643xx_eth_private *mp = netdev_priv(dev);
1820         u32 port_config;
1821         u32 nibbles;
1822         int i;
1823 
1824         uc_addr_set(mp, dev->dev_addr);
1825 
1826         port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1827 
1828         nibbles = uc_addr_filter_mask(dev);
1829         if (!nibbles) {
1830                 port_config |= UNICAST_PROMISCUOUS_MODE;
1831                 nibbles = 0xffff;
1832         }
1833 
1834         for (i = 0; i < 16; i += 4) {
1835                 int off = UNICAST_TABLE(mp->port_num) + i;
1836                 u32 v;
1837 
1838                 v = 0;
1839                 if (nibbles & 1)
1840                         v |= 0x00000001;
1841                 if (nibbles & 2)
1842                         v |= 0x00000100;
1843                 if (nibbles & 4)
1844                         v |= 0x00010000;
1845                 if (nibbles & 8)
1846                         v |= 0x01000000;
1847                 nibbles >>= 4;
1848 
1849                 wrl(mp, off, v);
1850         }
1851 
1852         wrlp(mp, PORT_CONFIG, port_config);
1853 }
1854 
1855 static int addr_crc(unsigned char *addr)
1856 {
1857         int crc = 0;
1858         int i;
1859 
1860         for (i = 0; i < 6; i++) {
1861                 int j;
1862 
1863                 crc = (crc ^ addr[i]) << 8;
1864                 for (j = 7; j >= 0; j--) {
1865                         if (crc & (0x100 << j))
1866                                 crc ^= 0x107 << j;
1867                 }
1868         }
1869 
1870         return crc;
1871 }
1872 
1873 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1874 {
1875         struct mv643xx_eth_private *mp = netdev_priv(dev);
1876         u32 *mc_spec;
1877         u32 *mc_other;
1878         struct netdev_hw_addr *ha;
1879         int i;
1880 
1881         if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI))
1882                 goto promiscuous;
1883 
1884         /* Allocate both mc_spec and mc_other tables */
1885         mc_spec = kcalloc(128, sizeof(u32), GFP_ATOMIC);
1886         if (!mc_spec)
1887                 goto promiscuous;
1888         mc_other = &mc_spec[64];
1889 
1890         netdev_for_each_mc_addr(ha, dev) {
1891                 u8 *a = ha->addr;
1892                 u32 *table;
1893                 u8 entry;
1894 
1895                 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1896                         table = mc_spec;
1897                         entry = a[5];
1898                 } else {
1899                         table = mc_other;
1900                         entry = addr_crc(a);
1901                 }
1902 
1903                 table[entry >> 2] |= 1 << (8 * (entry & 3));
1904         }
1905 
1906         for (i = 0; i < 64; i++) {
1907                 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1908                     mc_spec[i]);
1909                 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1910                     mc_other[i]);
1911         }
1912 
1913         kfree(mc_spec);
1914         return;
1915 
1916 promiscuous:
1917         for (i = 0; i < 64; i++) {
1918                 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1919                     0x01010101u);
1920                 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1921                     0x01010101u);
1922         }
1923 }
1924 
1925 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1926 {
1927         mv643xx_eth_program_unicast_filter(dev);
1928         mv643xx_eth_program_multicast_filter(dev);
1929 }
1930 
1931 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1932 {
1933         struct sockaddr *sa = addr;
1934 
1935         if (!is_valid_ether_addr(sa->sa_data))
1936                 return -EADDRNOTAVAIL;
1937 
1938         memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1939 
1940         netif_addr_lock_bh(dev);
1941         mv643xx_eth_program_unicast_filter(dev);
1942         netif_addr_unlock_bh(dev);
1943 
1944         return 0;
1945 }
1946 
1947 
1948 /* rx/tx queue initialisation ***********************************************/
1949 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1950 {
1951         struct rx_queue *rxq = mp->rxq + index;
1952         struct rx_desc *rx_desc;
1953         int size;
1954         int i;
1955 
1956         rxq->index = index;
1957 
1958         rxq->rx_ring_size = mp->rx_ring_size;
1959 
1960         rxq->rx_desc_count = 0;
1961         rxq->rx_curr_desc = 0;
1962         rxq->rx_used_desc = 0;
1963 
1964         size = rxq->rx_ring_size * sizeof(struct rx_desc);
1965 
1966         if (index == 0 && size <= mp->rx_desc_sram_size) {
1967                 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1968                                                 mp->rx_desc_sram_size);
1969                 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1970         } else {
1971                 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1972                                                        size, &rxq->rx_desc_dma,
1973                                                        GFP_KERNEL);
1974         }
1975 
1976         if (rxq->rx_desc_area == NULL) {
1977                 netdev_err(mp->dev,
1978                            "can't allocate rx ring (%d bytes)\n", size);
1979                 goto out;
1980         }
1981         memset(rxq->rx_desc_area, 0, size);
1982 
1983         rxq->rx_desc_area_size = size;
1984         rxq->rx_skb = kcalloc(rxq->rx_ring_size, sizeof(*rxq->rx_skb),
1985                                     GFP_KERNEL);
1986         if (rxq->rx_skb == NULL)
1987                 goto out_free;
1988 
1989         rx_desc = rxq->rx_desc_area;
1990         for (i = 0; i < rxq->rx_ring_size; i++) {
1991                 int nexti;
1992 
1993                 nexti = i + 1;
1994                 if (nexti == rxq->rx_ring_size)
1995                         nexti = 0;
1996 
1997                 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1998                                         nexti * sizeof(struct rx_desc);
1999         }
2000 
2001         return 0;
2002 
2003 
2004 out_free:
2005         if (index == 0 && size <= mp->rx_desc_sram_size)
2006                 iounmap(rxq->rx_desc_area);
2007         else
2008                 dma_free_coherent(mp->dev->dev.parent, size,
2009                                   rxq->rx_desc_area,
2010                                   rxq->rx_desc_dma);
2011 
2012 out:
2013         return -ENOMEM;
2014 }
2015 
2016 static void rxq_deinit(struct rx_queue *rxq)
2017 {
2018         struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
2019         int i;
2020 
2021         rxq_disable(rxq);
2022 
2023         for (i = 0; i < rxq->rx_ring_size; i++) {
2024                 if (rxq->rx_skb[i]) {
2025                         dev_kfree_skb(rxq->rx_skb[i]);
2026                         rxq->rx_desc_count--;
2027                 }
2028         }
2029 
2030         if (rxq->rx_desc_count) {
2031                 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
2032                            rxq->rx_desc_count);
2033         }
2034 
2035         if (rxq->index == 0 &&
2036             rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
2037                 iounmap(rxq->rx_desc_area);
2038         else
2039                 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
2040                                   rxq->rx_desc_area, rxq->rx_desc_dma);
2041 
2042         kfree(rxq->rx_skb);
2043 }
2044 
2045 static int txq_init(struct mv643xx_eth_private *mp, int index)
2046 {
2047         struct tx_queue *txq = mp->txq + index;
2048         struct tx_desc *tx_desc;
2049         int size;
2050         int ret;
2051         int i;
2052 
2053         txq->index = index;
2054 
2055         txq->tx_ring_size = mp->tx_ring_size;
2056 
2057         /* A queue must always have room for at least one skb.
2058          * Therefore, stop the queue when the free entries reaches
2059          * the maximum number of descriptors per skb.
2060          */
2061         txq->tx_stop_threshold = txq->tx_ring_size - MV643XX_MAX_SKB_DESCS;
2062         txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
2063 
2064         txq->tx_desc_count = 0;
2065         txq->tx_curr_desc = 0;
2066         txq->tx_used_desc = 0;
2067 
2068         size = txq->tx_ring_size * sizeof(struct tx_desc);
2069 
2070         if (index == 0 && size <= mp->tx_desc_sram_size) {
2071                 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
2072                                                 mp->tx_desc_sram_size);
2073                 txq->tx_desc_dma = mp->tx_desc_sram_addr;
2074         } else {
2075                 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
2076                                                        size, &txq->tx_desc_dma,
2077                                                        GFP_KERNEL);
2078         }
2079 
2080         if (txq->tx_desc_area == NULL) {
2081                 netdev_err(mp->dev,
2082                            "can't allocate tx ring (%d bytes)\n", size);
2083                 return -ENOMEM;
2084         }
2085         memset(txq->tx_desc_area, 0, size);
2086 
2087         txq->tx_desc_area_size = size;
2088 
2089         tx_desc = txq->tx_desc_area;
2090         for (i = 0; i < txq->tx_ring_size; i++) {
2091                 struct tx_desc *txd = tx_desc + i;
2092                 int nexti;
2093 
2094                 nexti = i + 1;
2095                 if (nexti == txq->tx_ring_size)
2096                         nexti = 0;
2097 
2098                 txd->cmd_sts = 0;
2099                 txd->next_desc_ptr = txq->tx_desc_dma +
2100                                         nexti * sizeof(struct tx_desc);
2101         }
2102 
2103         txq->tx_desc_mapping = kcalloc(txq->tx_ring_size, sizeof(char),
2104                                        GFP_KERNEL);
2105         if (!txq->tx_desc_mapping) {
2106                 ret = -ENOMEM;
2107                 goto err_free_desc_area;
2108         }
2109 
2110         /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2111         txq->tso_hdrs = dma_alloc_coherent(mp->dev->dev.parent,
2112                                            txq->tx_ring_size * TSO_HEADER_SIZE,
2113                                            &txq->tso_hdrs_dma, GFP_KERNEL);
2114         if (txq->tso_hdrs == NULL) {
2115                 ret = -ENOMEM;
2116                 goto err_free_desc_mapping;
2117         }
2118         skb_queue_head_init(&txq->tx_skb);
2119 
2120         return 0;
2121 
2122 err_free_desc_mapping:
2123         kfree(txq->tx_desc_mapping);
2124 err_free_desc_area:
2125         if (index == 0 && size <= mp->tx_desc_sram_size)
2126                 iounmap(txq->tx_desc_area);
2127         else
2128                 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2129                                   txq->tx_desc_area, txq->tx_desc_dma);
2130         return ret;
2131 }
2132 
2133 static void txq_deinit(struct tx_queue *txq)
2134 {
2135         struct mv643xx_eth_private *mp = txq_to_mp(txq);
2136 
2137         txq_disable(txq);
2138         txq_reclaim(txq, txq->tx_ring_size, 1);
2139 
2140         BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
2141 
2142         if (txq->index == 0 &&
2143             txq->tx_desc_area_size <= mp->tx_desc_sram_size)
2144                 iounmap(txq->tx_desc_area);
2145         else
2146                 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2147                                   txq->tx_desc_area, txq->tx_desc_dma);
2148         kfree(txq->tx_desc_mapping);
2149 
2150         if (txq->tso_hdrs)
2151                 dma_free_coherent(mp->dev->dev.parent,
2152                                   txq->tx_ring_size * TSO_HEADER_SIZE,
2153                                   txq->tso_hdrs, txq->tso_hdrs_dma);
2154 }
2155 
2156 
2157 /* netdev ops and related ***************************************************/
2158 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2159 {
2160         u32 int_cause;
2161         u32 int_cause_ext;
2162 
2163         int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
2164         if (int_cause == 0)
2165                 return 0;
2166 
2167         int_cause_ext = 0;
2168         if (int_cause & INT_EXT) {
2169                 int_cause &= ~INT_EXT;
2170                 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
2171         }
2172 
2173         if (int_cause) {
2174                 wrlp(mp, INT_CAUSE, ~int_cause);
2175                 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
2176                                 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
2177                 mp->work_rx |= (int_cause & INT_RX) >> 2;
2178         }
2179 
2180         int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2181         if (int_cause_ext) {
2182                 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
2183                 if (int_cause_ext & INT_EXT_LINK_PHY)
2184                         mp->work_link = 1;
2185                 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2186         }
2187 
2188         return 1;
2189 }
2190 
2191 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2192 {
2193         struct net_device *dev = (struct net_device *)dev_id;
2194         struct mv643xx_eth_private *mp = netdev_priv(dev);
2195 
2196         if (unlikely(!mv643xx_eth_collect_events(mp)))
2197                 return IRQ_NONE;
2198 
2199         wrlp(mp, INT_MASK, 0);
2200         napi_schedule(&mp->napi);
2201 
2202         return IRQ_HANDLED;
2203 }
2204 
2205 static void handle_link_event(struct mv643xx_eth_private *mp)
2206 {
2207         struct net_device *dev = mp->dev;
2208         u32 port_status;
2209         int speed;
2210         int duplex;
2211         int fc;
2212 
2213         port_status = rdlp(mp, PORT_STATUS);
2214         if (!(port_status & LINK_UP)) {
2215                 if (netif_carrier_ok(dev)) {
2216                         int i;
2217 
2218                         netdev_info(dev, "link down\n");
2219 
2220                         netif_carrier_off(dev);
2221 
2222                         for (i = 0; i < mp->txq_count; i++) {
2223                                 struct tx_queue *txq = mp->txq + i;
2224 
2225                                 txq_reclaim(txq, txq->tx_ring_size, 1);
2226                                 txq_reset_hw_ptr(txq);
2227                         }
2228                 }
2229                 return;
2230         }
2231 
2232         switch (port_status & PORT_SPEED_MASK) {
2233         case PORT_SPEED_10:
2234                 speed = 10;
2235                 break;
2236         case PORT_SPEED_100:
2237                 speed = 100;
2238                 break;
2239         case PORT_SPEED_1000:
2240                 speed = 1000;
2241                 break;
2242         default:
2243                 speed = -1;
2244                 break;
2245         }
2246         duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2247         fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2248 
2249         netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
2250                     speed, duplex ? "full" : "half", fc ? "en" : "dis");
2251 
2252         if (!netif_carrier_ok(dev))
2253                 netif_carrier_on(dev);
2254 }
2255 
2256 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
2257 {
2258         struct mv643xx_eth_private *mp;
2259         int work_done;
2260 
2261         mp = container_of(napi, struct mv643xx_eth_private, napi);
2262 
2263         if (unlikely(mp->oom)) {
2264                 mp->oom = 0;
2265                 del_timer(&mp->rx_oom);
2266         }
2267 
2268         work_done = 0;
2269         while (work_done < budget) {
2270                 u8 queue_mask;
2271                 int queue;
2272                 int work_tbd;
2273 
2274                 if (mp->work_link) {
2275                         mp->work_link = 0;
2276                         handle_link_event(mp);
2277                         work_done++;
2278                         continue;
2279                 }
2280 
2281                 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2282                 if (likely(!mp->oom))
2283                         queue_mask |= mp->work_rx_refill;
2284 
2285                 if (!queue_mask) {
2286                         if (mv643xx_eth_collect_events(mp))
2287                                 continue;
2288                         break;
2289                 }
2290 
2291                 queue = fls(queue_mask) - 1;
2292                 queue_mask = 1 << queue;
2293 
2294                 work_tbd = budget - work_done;
2295                 if (work_tbd > 16)
2296                         work_tbd = 16;
2297 
2298                 if (mp->work_tx_end & queue_mask) {
2299                         txq_kick(mp->txq + queue);
2300                 } else if (mp->work_tx & queue_mask) {
2301                         work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2302                         txq_maybe_wake(mp->txq + queue);
2303                 } else if (mp->work_rx & queue_mask) {
2304                         work_done += rxq_process(mp->rxq + queue, work_tbd);
2305                 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
2306                         work_done += rxq_refill(mp->rxq + queue, work_tbd);
2307                 } else {
2308                         BUG();
2309                 }
2310         }
2311 
2312         if (work_done < budget) {
2313                 if (mp->oom)
2314                         mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2315                 napi_complete(napi);
2316                 wrlp(mp, INT_MASK, mp->int_mask);
2317         }
2318 
2319         return work_done;
2320 }
2321 
2322 static inline void oom_timer_wrapper(unsigned long data)
2323 {
2324         struct mv643xx_eth_private *mp = (void *)data;
2325 
2326         napi_schedule(&mp->napi);
2327 }
2328 
2329 static void port_start(struct mv643xx_eth_private *mp)
2330 {
2331         u32 pscr;
2332         int i;
2333 
2334         /*
2335          * Perform PHY reset, if there is a PHY.
2336          */
2337         if (mp->phy != NULL) {
2338                 struct ethtool_cmd cmd;
2339 
2340                 mv643xx_eth_get_settings(mp->dev, &cmd);
2341                 phy_init_hw(mp->phy);
2342                 mv643xx_eth_set_settings(mp->dev, &cmd);
2343                 phy_start(mp->phy);
2344         }
2345 
2346         /*
2347          * Configure basic link parameters.
2348          */
2349         pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2350 
2351         pscr |= SERIAL_PORT_ENABLE;
2352         wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2353 
2354         pscr |= DO_NOT_FORCE_LINK_FAIL;
2355         if (mp->phy == NULL)
2356                 pscr |= FORCE_LINK_PASS;
2357         wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2358 
2359         /*
2360          * Configure TX path and queues.
2361          */
2362         tx_set_rate(mp, 1000000000, 16777216);
2363         for (i = 0; i < mp->txq_count; i++) {
2364                 struct tx_queue *txq = mp->txq + i;
2365 
2366                 txq_reset_hw_ptr(txq);
2367                 txq_set_rate(txq, 1000000000, 16777216);
2368                 txq_set_fixed_prio_mode(txq);
2369         }
2370 
2371         /*
2372          * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2373          * frames to RX queue #0, and include the pseudo-header when
2374          * calculating receive checksums.
2375          */
2376         mv643xx_eth_set_features(mp->dev, mp->dev->features);
2377 
2378         /*
2379          * Treat BPDUs as normal multicasts, and disable partition mode.
2380          */
2381         wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2382 
2383         /*
2384          * Add configured unicast addresses to address filter table.
2385          */
2386         mv643xx_eth_program_unicast_filter(mp->dev);
2387 
2388         /*
2389          * Enable the receive queues.
2390          */
2391         for (i = 0; i < mp->rxq_count; i++) {
2392                 struct rx_queue *rxq = mp->rxq + i;
2393                 u32 addr;
2394 
2395                 addr = (u32)rxq->rx_desc_dma;
2396                 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2397                 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2398 
2399                 rxq_enable(rxq);
2400         }
2401 }
2402 
2403 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2404 {
2405         int skb_size;
2406 
2407         /*
2408          * Reserve 2+14 bytes for an ethernet header (the hardware
2409          * automatically prepends 2 bytes of dummy data to each
2410          * received packet), 16 bytes for up to four VLAN tags, and
2411          * 4 bytes for the trailing FCS -- 36 bytes total.
2412          */
2413         skb_size = mp->dev->mtu + 36;
2414 
2415         /*
2416          * Make sure that the skb size is a multiple of 8 bytes, as
2417          * the lower three bits of the receive descriptor's buffer
2418          * size field are ignored by the hardware.
2419          */
2420         mp->skb_size = (skb_size + 7) & ~7;
2421 
2422         /*
2423          * If NET_SKB_PAD is smaller than a cache line,
2424          * netdev_alloc_skb() will cause skb->data to be misaligned
2425          * to a cache line boundary.  If this is the case, include
2426          * some extra space to allow re-aligning the data area.
2427          */
2428         mp->skb_size += SKB_DMA_REALIGN;
2429 }
2430 
2431 static int mv643xx_eth_open(struct net_device *dev)
2432 {
2433         struct mv643xx_eth_private *mp = netdev_priv(dev);
2434         int err;
2435         int i;
2436 
2437         wrlp(mp, INT_CAUSE, 0);
2438         wrlp(mp, INT_CAUSE_EXT, 0);
2439         rdlp(mp, INT_CAUSE_EXT);
2440 
2441         err = request_irq(dev->irq, mv643xx_eth_irq,
2442                           IRQF_SHARED, dev->name, dev);
2443         if (err) {
2444                 netdev_err(dev, "can't assign irq\n");
2445                 return -EAGAIN;
2446         }
2447 
2448         mv643xx_eth_recalc_skb_size(mp);
2449 
2450         napi_enable(&mp->napi);
2451 
2452         mp->int_mask = INT_EXT;
2453 
2454         for (i = 0; i < mp->rxq_count; i++) {
2455                 err = rxq_init(mp, i);
2456                 if (err) {
2457                         while (--i >= 0)
2458                                 rxq_deinit(mp->rxq + i);
2459                         goto out;
2460                 }
2461 
2462                 rxq_refill(mp->rxq + i, INT_MAX);
2463                 mp->int_mask |= INT_RX_0 << i;
2464         }
2465 
2466         if (mp->oom) {
2467                 mp->rx_oom.expires = jiffies + (HZ / 10);
2468                 add_timer(&mp->rx_oom);
2469         }
2470 
2471         for (i = 0; i < mp->txq_count; i++) {
2472                 err = txq_init(mp, i);
2473                 if (err) {
2474                         while (--i >= 0)
2475                                 txq_deinit(mp->txq + i);
2476                         goto out_free;
2477                 }
2478                 mp->int_mask |= INT_TX_END_0 << i;
2479         }
2480 
2481         add_timer(&mp->mib_counters_timer);
2482         port_start(mp);
2483 
2484         wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2485         wrlp(mp, INT_MASK, mp->int_mask);
2486 
2487         return 0;
2488 
2489 
2490 out_free:
2491         for (i = 0; i < mp->rxq_count; i++)
2492                 rxq_deinit(mp->rxq + i);
2493 out:
2494         free_irq(dev->irq, dev);
2495 
2496         return err;
2497 }
2498 
2499 static void port_reset(struct mv643xx_eth_private *mp)
2500 {
2501         unsigned int data;
2502         int i;
2503 
2504         for (i = 0; i < mp->rxq_count; i++)
2505                 rxq_disable(mp->rxq + i);
2506         for (i = 0; i < mp->txq_count; i++)
2507                 txq_disable(mp->txq + i);
2508 
2509         while (1) {
2510                 u32 ps = rdlp(mp, PORT_STATUS);
2511 
2512                 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2513                         break;
2514                 udelay(10);
2515         }
2516 
2517         /* Reset the Enable bit in the Configuration Register */
2518         data = rdlp(mp, PORT_SERIAL_CONTROL);
2519         data &= ~(SERIAL_PORT_ENABLE            |
2520                   DO_NOT_FORCE_LINK_FAIL        |
2521                   FORCE_LINK_PASS);
2522         wrlp(mp, PORT_SERIAL_CONTROL, data);
2523 }
2524 
2525 static int mv643xx_eth_stop(struct net_device *dev)
2526 {
2527         struct mv643xx_eth_private *mp = netdev_priv(dev);
2528         int i;
2529 
2530         wrlp(mp, INT_MASK_EXT, 0x00000000);
2531         wrlp(mp, INT_MASK, 0x00000000);
2532         rdlp(mp, INT_MASK);
2533 
2534         napi_disable(&mp->napi);
2535 
2536         del_timer_sync(&mp->rx_oom);
2537 
2538         netif_carrier_off(dev);
2539         if (mp->phy)
2540                 phy_stop(mp->phy);
2541         free_irq(dev->irq, dev);
2542 
2543         port_reset(mp);
2544         mv643xx_eth_get_stats(dev);
2545         mib_counters_update(mp);
2546         del_timer_sync(&mp->mib_counters_timer);
2547 
2548         for (i = 0; i < mp->rxq_count; i++)
2549                 rxq_deinit(mp->rxq + i);
2550         for (i = 0; i < mp->txq_count; i++)
2551                 txq_deinit(mp->txq + i);
2552 
2553         return 0;
2554 }
2555 
2556 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2557 {
2558         struct mv643xx_eth_private *mp = netdev_priv(dev);
2559         int ret;
2560 
2561         if (mp->phy == NULL)
2562                 return -ENOTSUPP;
2563 
2564         ret = phy_mii_ioctl(mp->phy, ifr, cmd);
2565         if (!ret)
2566                 mv643xx_eth_adjust_link(dev);
2567         return ret;
2568 }
2569 
2570 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2571 {
2572         struct mv643xx_eth_private *mp = netdev_priv(dev);
2573 
2574         if (new_mtu < 64 || new_mtu > 9500)
2575                 return -EINVAL;
2576 
2577         dev->mtu = new_mtu;
2578         mv643xx_eth_recalc_skb_size(mp);
2579         tx_set_rate(mp, 1000000000, 16777216);
2580 
2581         if (!netif_running(dev))
2582                 return 0;
2583 
2584         /*
2585          * Stop and then re-open the interface. This will allocate RX
2586          * skbs of the new MTU.
2587          * There is a possible danger that the open will not succeed,
2588          * due to memory being full.
2589          */
2590         mv643xx_eth_stop(dev);
2591         if (mv643xx_eth_open(dev)) {
2592                 netdev_err(dev,
2593                            "fatal error on re-opening device after MTU change\n");
2594         }
2595 
2596         return 0;
2597 }
2598 
2599 static void tx_timeout_task(struct work_struct *ugly)
2600 {
2601         struct mv643xx_eth_private *mp;
2602 
2603         mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2604         if (netif_running(mp->dev)) {
2605                 netif_tx_stop_all_queues(mp->dev);
2606                 port_reset(mp);
2607                 port_start(mp);
2608                 netif_tx_wake_all_queues(mp->dev);
2609         }
2610 }
2611 
2612 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2613 {
2614         struct mv643xx_eth_private *mp = netdev_priv(dev);
2615 
2616         netdev_info(dev, "tx timeout\n");
2617 
2618         schedule_work(&mp->tx_timeout_task);
2619 }
2620 
2621 #ifdef CONFIG_NET_POLL_CONTROLLER
2622 static void mv643xx_eth_netpoll(struct net_device *dev)
2623 {
2624         struct mv643xx_eth_private *mp = netdev_priv(dev);
2625 
2626         wrlp(mp, INT_MASK, 0x00000000);
2627         rdlp(mp, INT_MASK);
2628 
2629         mv643xx_eth_irq(dev->irq, dev);
2630 
2631         wrlp(mp, INT_MASK, mp->int_mask);
2632 }
2633 #endif
2634 
2635 
2636 /* platform glue ************************************************************/
2637 static void
2638 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2639                               const struct mbus_dram_target_info *dram)
2640 {
2641         void __iomem *base = msp->base;
2642         u32 win_enable;
2643         u32 win_protect;
2644         int i;
2645 
2646         for (i = 0; i < 6; i++) {
2647                 writel(0, base + WINDOW_BASE(i));
2648                 writel(0, base + WINDOW_SIZE(i));
2649                 if (i < 4)
2650                         writel(0, base + WINDOW_REMAP_HIGH(i));
2651         }
2652 
2653         win_enable = 0x3f;
2654         win_protect = 0;
2655 
2656         for (i = 0; i < dram->num_cs; i++) {
2657                 const struct mbus_dram_window *cs = dram->cs + i;
2658 
2659                 writel((cs->base & 0xffff0000) |
2660                         (cs->mbus_attr << 8) |
2661                         dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2662                 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2663 
2664                 win_enable &= ~(1 << i);
2665                 win_protect |= 3 << (2 * i);
2666         }
2667 
2668         writel(win_enable, base + WINDOW_BAR_ENABLE);
2669         msp->win_protect = win_protect;
2670 }
2671 
2672 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2673 {
2674         /*
2675          * Check whether we have a 14-bit coal limit field in bits
2676          * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2677          * SDMA config register.
2678          */
2679         writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2680         if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2681                 msp->extended_rx_coal_limit = 1;
2682         else
2683                 msp->extended_rx_coal_limit = 0;
2684 
2685         /*
2686          * Check whether the MAC supports TX rate control, and if
2687          * yes, whether its associated registers are in the old or
2688          * the new place.
2689          */
2690         writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2691         if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2692                 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2693         } else {
2694                 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2695                 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2696                         msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2697                 else
2698                         msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2699         }
2700 }
2701 
2702 #if defined(CONFIG_OF)
2703 static const struct of_device_id mv643xx_eth_shared_ids[] = {
2704         { .compatible = "marvell,orion-eth", },
2705         { .compatible = "marvell,kirkwood-eth", },
2706         { }
2707 };
2708 MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids);
2709 #endif
2710 
2711 #if defined(CONFIG_OF) && !defined(CONFIG_MV64X60)
2712 #define mv643xx_eth_property(_np, _name, _v)                            \
2713         do {                                                            \
2714                 u32 tmp;                                                \
2715                 if (!of_property_read_u32(_np, "marvell," _name, &tmp)) \
2716                         _v = tmp;                                       \
2717         } while (0)
2718 
2719 static struct platform_device *port_platdev[3];
2720 
2721 static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev,
2722                                           struct device_node *pnp)
2723 {
2724         struct platform_device *ppdev;
2725         struct mv643xx_eth_platform_data ppd;
2726         struct resource res;
2727         const char *mac_addr;
2728         int ret;
2729         int dev_num = 0;
2730 
2731         memset(&ppd, 0, sizeof(ppd));
2732         ppd.shared = pdev;
2733 
2734         memset(&res, 0, sizeof(res));
2735         if (!of_irq_to_resource(pnp, 0, &res)) {
2736                 dev_err(&pdev->dev, "missing interrupt on %s\n", pnp->name);
2737                 return -EINVAL;
2738         }
2739 
2740         if (of_property_read_u32(pnp, "reg", &ppd.port_number)) {
2741                 dev_err(&pdev->dev, "missing reg property on %s\n", pnp->name);
2742                 return -EINVAL;
2743         }
2744 
2745         if (ppd.port_number >= 3) {
2746                 dev_err(&pdev->dev, "invalid reg property on %s\n", pnp->name);
2747                 return -EINVAL;
2748         }
2749 
2750         while (dev_num < 3 && port_platdev[dev_num])
2751                 dev_num++;
2752 
2753         if (dev_num == 3) {
2754                 dev_err(&pdev->dev, "too many ports registered\n");
2755                 return -EINVAL;
2756         }
2757 
2758         mac_addr = of_get_mac_address(pnp);
2759         if (mac_addr)
2760                 memcpy(ppd.mac_addr, mac_addr, ETH_ALEN);
2761 
2762         mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size);
2763         mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr);
2764         mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size);
2765         mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size);
2766         mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr);
2767         mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size);
2768 
2769         ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0);
2770         if (!ppd.phy_node) {
2771                 ppd.phy_addr = MV643XX_ETH_PHY_NONE;
2772                 of_property_read_u32(pnp, "speed", &ppd.speed);
2773                 of_property_read_u32(pnp, "duplex", &ppd.duplex);
2774         }
2775 
2776         ppdev = platform_device_alloc(MV643XX_ETH_NAME, dev_num);
2777         if (!ppdev)
2778                 return -ENOMEM;
2779         ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
2780         ppdev->dev.of_node = pnp;
2781 
2782         ret = platform_device_add_resources(ppdev, &res, 1);
2783         if (ret)
2784                 goto port_err;
2785 
2786         ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
2787         if (ret)
2788                 goto port_err;
2789 
2790         ret = platform_device_add(ppdev);
2791         if (ret)
2792                 goto port_err;
2793 
2794         port_platdev[dev_num] = ppdev;
2795 
2796         return 0;
2797 
2798 port_err:
2799         platform_device_put(ppdev);
2800         return ret;
2801 }
2802 
2803 static int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2804 {
2805         struct mv643xx_eth_shared_platform_data *pd;
2806         struct device_node *pnp, *np = pdev->dev.of_node;
2807         int ret;
2808 
2809         /* bail out if not registered from DT */
2810         if (!np)
2811                 return 0;
2812 
2813         pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
2814         if (!pd)
2815                 return -ENOMEM;
2816         pdev->dev.platform_data = pd;
2817 
2818         mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit);
2819 
2820         for_each_available_child_of_node(np, pnp) {
2821                 ret = mv643xx_eth_shared_of_add_port(pdev, pnp);
2822                 if (ret) {
2823                         of_node_put(pnp);
2824                         return ret;
2825                 }
2826         }
2827         return 0;
2828 }
2829 
2830 static void mv643xx_eth_shared_of_remove(void)
2831 {
2832         int n;
2833 
2834         for (n = 0; n < 3; n++) {
2835                 platform_device_del(port_platdev[n]);
2836                 port_platdev[n] = NULL;
2837         }
2838 }
2839 #else
2840 static inline int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2841 {
2842         return 0;
2843 }
2844 
2845 static inline void mv643xx_eth_shared_of_remove(void)
2846 {
2847 }
2848 #endif
2849 
2850 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2851 {
2852         static int mv643xx_eth_version_printed;
2853         struct mv643xx_eth_shared_platform_data *pd;
2854         struct mv643xx_eth_shared_private *msp;
2855         const struct mbus_dram_target_info *dram;
2856         struct resource *res;
2857         int ret;
2858 
2859         if (!mv643xx_eth_version_printed++)
2860                 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2861                           mv643xx_eth_driver_version);
2862 
2863         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2864         if (res == NULL)
2865                 return -EINVAL;
2866 
2867         msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
2868         if (msp == NULL)
2869                 return -ENOMEM;
2870         platform_set_drvdata(pdev, msp);
2871 
2872         msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
2873         if (msp->base == NULL)
2874                 return -ENOMEM;
2875 
2876         msp->clk = devm_clk_get(&pdev->dev, NULL);
2877         if (!IS_ERR(msp->clk))
2878                 clk_prepare_enable(msp->clk);
2879 
2880         /*
2881          * (Re-)program MBUS remapping windows if we are asked to.
2882          */
2883         dram = mv_mbus_dram_info();
2884         if (dram)
2885                 mv643xx_eth_conf_mbus_windows(msp, dram);
2886 
2887         ret = mv643xx_eth_shared_of_probe(pdev);
2888         if (ret)
2889                 return ret;
2890         pd = dev_get_platdata(&pdev->dev);
2891 
2892         msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2893                                         pd->tx_csum_limit : 9 * 1024;
2894         infer_hw_params(msp);
2895 
2896         return 0;
2897 }
2898 
2899 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2900 {
2901         struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2902 
2903         mv643xx_eth_shared_of_remove();
2904         if (!IS_ERR(msp->clk))
2905                 clk_disable_unprepare(msp->clk);
2906         return 0;
2907 }
2908 
2909 static struct platform_driver mv643xx_eth_shared_driver = {
2910         .probe          = mv643xx_eth_shared_probe,
2911         .remove         = mv643xx_eth_shared_remove,
2912         .driver = {
2913                 .name   = MV643XX_ETH_SHARED_NAME,
2914                 .of_match_table = of_match_ptr(mv643xx_eth_shared_ids),
2915         },
2916 };
2917 
2918 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2919 {
2920         int addr_shift = 5 * mp->port_num;
2921         u32 data;
2922 
2923         data = rdl(mp, PHY_ADDR);
2924         data &= ~(0x1f << addr_shift);
2925         data |= (phy_addr & 0x1f) << addr_shift;
2926         wrl(mp, PHY_ADDR, data);
2927 }
2928 
2929 static int phy_addr_get(struct mv643xx_eth_private *mp)
2930 {
2931         unsigned int data;
2932 
2933         data = rdl(mp, PHY_ADDR);
2934 
2935         return (data >> (5 * mp->port_num)) & 0x1f;
2936 }
2937 
2938 static void set_params(struct mv643xx_eth_private *mp,
2939                        struct mv643xx_eth_platform_data *pd)
2940 {
2941         struct net_device *dev = mp->dev;
2942         unsigned int tx_ring_size;
2943 
2944         if (is_valid_ether_addr(pd->mac_addr))
2945                 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2946         else
2947                 uc_addr_get(mp, dev->dev_addr);
2948 
2949         mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2950         if (pd->rx_queue_size)
2951                 mp->rx_ring_size = pd->rx_queue_size;
2952         mp->rx_desc_sram_addr = pd->rx_sram_addr;
2953         mp->rx_desc_sram_size = pd->rx_sram_size;
2954 
2955         mp->rxq_count = pd->rx_queue_count ? : 1;
2956 
2957         tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2958         if (pd->tx_queue_size)
2959                 tx_ring_size = pd->tx_queue_size;
2960 
2961         mp->tx_ring_size = clamp_t(unsigned int, tx_ring_size,
2962                                    MV643XX_MAX_SKB_DESCS * 2, 4096);
2963         if (mp->tx_ring_size != tx_ring_size)
2964                 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
2965                             mp->tx_ring_size, tx_ring_size);
2966 
2967         mp->tx_desc_sram_addr = pd->tx_sram_addr;
2968         mp->tx_desc_sram_size = pd->tx_sram_size;
2969 
2970         mp->txq_count = pd->tx_queue_count ? : 1;
2971 }
2972 
2973 static int get_phy_mode(struct mv643xx_eth_private *mp)
2974 {
2975         struct device *dev = mp->dev->dev.parent;
2976         int iface = -1;
2977 
2978         if (dev->of_node)
2979                 iface = of_get_phy_mode(dev->of_node);
2980 
2981         /* Historical default if unspecified. We could also read/write
2982          * the interface state in the PSC1
2983          */
2984         if (iface < 0)
2985                 iface = PHY_INTERFACE_MODE_GMII;
2986         return iface;
2987 }
2988 
2989 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2990                                    int phy_addr)
2991 {
2992         struct phy_device *phydev;
2993         int start;
2994         int num;
2995         int i;
2996         char phy_id[MII_BUS_ID_SIZE + 3];
2997 
2998         if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2999                 start = phy_addr_get(mp) & 0x1f;
3000                 num = 32;
3001         } else {
3002                 start = phy_addr & 0x1f;
3003                 num = 1;
3004         }
3005 
3006         /* Attempt to connect to the PHY using orion-mdio */
3007         phydev = ERR_PTR(-ENODEV);
3008         for (i = 0; i < num; i++) {
3009                 int addr = (start + i) & 0x1f;
3010 
3011                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
3012                                 "orion-mdio-mii", addr);
3013 
3014                 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link,
3015                                      get_phy_mode(mp));
3016                 if (!IS_ERR(phydev)) {
3017                         phy_addr_set(mp, addr);
3018                         break;
3019                 }
3020         }
3021 
3022         return phydev;
3023 }
3024 
3025 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
3026 {
3027         struct phy_device *phy = mp->phy;
3028 
3029         if (speed == 0) {
3030                 phy->autoneg = AUTONEG_ENABLE;
3031                 phy->speed = 0;
3032                 phy->duplex = 0;
3033                 phy->advertising = phy->supported | ADVERTISED_Autoneg;
3034         } else {
3035                 phy->autoneg = AUTONEG_DISABLE;
3036                 phy->advertising = 0;
3037                 phy->speed = speed;
3038                 phy->duplex = duplex;
3039         }
3040         phy_start_aneg(phy);
3041 }
3042 
3043 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
3044 {
3045         u32 pscr;
3046 
3047         pscr = rdlp(mp, PORT_SERIAL_CONTROL);
3048         if (pscr & SERIAL_PORT_ENABLE) {
3049                 pscr &= ~SERIAL_PORT_ENABLE;
3050                 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
3051         }
3052 
3053         pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
3054         if (mp->phy == NULL) {
3055                 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
3056                 if (speed == SPEED_1000)
3057                         pscr |= SET_GMII_SPEED_TO_1000;
3058                 else if (speed == SPEED_100)
3059                         pscr |= SET_MII_SPEED_TO_100;
3060 
3061                 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
3062 
3063                 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
3064                 if (duplex == DUPLEX_FULL)
3065                         pscr |= SET_FULL_DUPLEX_MODE;
3066         }
3067 
3068         wrlp(mp, PORT_SERIAL_CONTROL, pscr);
3069 }
3070 
3071 static const struct net_device_ops mv643xx_eth_netdev_ops = {
3072         .ndo_open               = mv643xx_eth_open,
3073         .ndo_stop               = mv643xx_eth_stop,
3074         .ndo_start_xmit         = mv643xx_eth_xmit,
3075         .ndo_set_rx_mode        = mv643xx_eth_set_rx_mode,
3076         .ndo_set_mac_address    = mv643xx_eth_set_mac_address,
3077         .ndo_validate_addr      = eth_validate_addr,
3078         .ndo_do_ioctl           = mv643xx_eth_ioctl,
3079         .ndo_change_mtu         = mv643xx_eth_change_mtu,
3080         .ndo_set_features       = mv643xx_eth_set_features,
3081         .ndo_tx_timeout         = mv643xx_eth_tx_timeout,
3082         .ndo_get_stats          = mv643xx_eth_get_stats,
3083 #ifdef CONFIG_NET_POLL_CONTROLLER
3084         .ndo_poll_controller    = mv643xx_eth_netpoll,
3085 #endif
3086 };
3087 
3088 static int mv643xx_eth_probe(struct platform_device *pdev)
3089 {
3090         struct mv643xx_eth_platform_data *pd;
3091         struct mv643xx_eth_private *mp;
3092         struct net_device *dev;
3093         struct resource *res;
3094         int err;
3095 
3096         pd = dev_get_platdata(&pdev->dev);
3097         if (pd == NULL) {
3098                 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
3099                 return -ENODEV;
3100         }
3101 
3102         if (pd->shared == NULL) {
3103                 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
3104                 return -ENODEV;
3105         }
3106 
3107         dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
3108         if (!dev)
3109                 return -ENOMEM;
3110 
3111         SET_NETDEV_DEV(dev, &pdev->dev);
3112         mp = netdev_priv(dev);
3113         platform_set_drvdata(pdev, mp);
3114 
3115         mp->shared = platform_get_drvdata(pd->shared);
3116         mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
3117         mp->port_num = pd->port_number;
3118 
3119         mp->dev = dev;
3120 
3121         /* Kirkwood resets some registers on gated clocks. Especially
3122          * CLK125_BYPASS_EN must be cleared but is not available on
3123          * all other SoCs/System Controllers using this driver.
3124          */
3125         if (of_device_is_compatible(pdev->dev.of_node,
3126                                     "marvell,kirkwood-eth-port"))
3127                 wrlp(mp, PORT_SERIAL_CONTROL1,
3128                      rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
3129 
3130         /*
3131          * Start with a default rate, and if there is a clock, allow
3132          * it to override the default.
3133          */
3134         mp->t_clk = 133000000;
3135         mp->clk = devm_clk_get(&pdev->dev, NULL);
3136         if (!IS_ERR(mp->clk)) {
3137                 clk_prepare_enable(mp->clk);
3138                 mp->t_clk = clk_get_rate(mp->clk);
3139         } else if (!IS_ERR(mp->shared->clk)) {
3140                 mp->t_clk = clk_get_rate(mp->shared->clk);
3141         }
3142 
3143         set_params(mp, pd);
3144         netif_set_real_num_tx_queues(dev, mp->txq_count);
3145         netif_set_real_num_rx_queues(dev, mp->rxq_count);
3146 
3147         err = 0;
3148         if (pd->phy_node) {
3149                 mp->phy = of_phy_connect(mp->dev, pd->phy_node,
3150                                          mv643xx_eth_adjust_link, 0,
3151                                          get_phy_mode(mp));
3152                 if (!mp->phy)
3153                         err = -ENODEV;
3154                 else
3155                         phy_addr_set(mp, mp->phy->mdio.addr);
3156         } else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
3157                 mp->phy = phy_scan(mp, pd->phy_addr);
3158 
3159                 if (IS_ERR(mp->phy))
3160                         err = PTR_ERR(mp->phy);
3161                 else
3162                         phy_init(mp, pd->speed, pd->duplex);
3163         }
3164         if (err == -ENODEV) {
3165                 err = -EPROBE_DEFER;
3166                 goto out;
3167         }
3168         if (err)
3169                 goto out;
3170 
3171         dev->ethtool_ops = &mv643xx_eth_ethtool_ops;
3172 
3173         init_pscr(mp, pd->speed, pd->duplex);
3174 
3175 
3176         mib_counters_clear(mp);
3177 
3178         setup_timer(&mp->mib_counters_timer, mib_counters_timer_wrapper,
3179                     (unsigned long)mp);
3180         mp->mib_counters_timer.expires = jiffies + 30 * HZ;
3181 
3182         spin_lock_init(&mp->mib_counters_lock);
3183 
3184         INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
3185 
3186         netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT);
3187 
3188         setup_timer(&mp->rx_oom, oom_timer_wrapper, (unsigned long)mp);
3189 
3190 
3191         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
3192         BUG_ON(!res);
3193         dev->irq = res->start;
3194 
3195         dev->netdev_ops = &mv643xx_eth_netdev_ops;
3196 
3197         dev->watchdog_timeo = 2 * HZ;
3198         dev->base_addr = 0;
3199 
3200         dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
3201         dev->vlan_features = dev->features;
3202 
3203         dev->features |= NETIF_F_RXCSUM;
3204         dev->hw_features = dev->features;
3205 
3206         dev->priv_flags |= IFF_UNICAST_FLT;
3207         dev->gso_max_segs = MV643XX_MAX_TSO_SEGS;
3208 
3209         if (mp->shared->win_protect)
3210                 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
3211 
3212         netif_carrier_off(dev);
3213 
3214         wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
3215 
3216         set_rx_coal(mp, 250);
3217         set_tx_coal(mp, 0);
3218 
3219         err = register_netdev(dev);
3220         if (err)
3221                 goto out;
3222 
3223         netdev_notice(dev, "port %d with MAC address %pM\n",
3224                       mp->port_num, dev->dev_addr);
3225 
3226         if (mp->tx_desc_sram_size > 0)
3227                 netdev_notice(dev, "configured with sram\n");
3228 
3229         return 0;
3230 
3231 out:
3232         if (!IS_ERR(mp->clk))
3233                 clk_disable_unprepare(mp->clk);
3234         free_netdev(dev);
3235 
3236         return err;
3237 }
3238 
3239 static int mv643xx_eth_remove(struct platform_device *pdev)
3240 {
3241         struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3242 
3243         unregister_netdev(mp->dev);
3244         if (mp->phy != NULL)
3245                 phy_disconnect(mp->phy);
3246         cancel_work_sync(&mp->tx_timeout_task);
3247 
3248         if (!IS_ERR(mp->clk))
3249                 clk_disable_unprepare(mp->clk);
3250 
3251         free_netdev(mp->dev);
3252 
3253         return 0;
3254 }
3255 
3256 static void mv643xx_eth_shutdown(struct platform_device *pdev)
3257 {
3258         struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3259 
3260         /* Mask all interrupts on ethernet port */
3261         wrlp(mp, INT_MASK, 0);
3262         rdlp(mp, INT_MASK);
3263 
3264         if (netif_running(mp->dev))
3265                 port_reset(mp);
3266 }
3267 
3268 static struct platform_driver mv643xx_eth_driver = {
3269         .probe          = mv643xx_eth_probe,
3270         .remove         = mv643xx_eth_remove,
3271         .shutdown       = mv643xx_eth_shutdown,
3272         .driver = {
3273                 .name   = MV643XX_ETH_NAME,
3274         },
3275 };
3276 
3277 static struct platform_driver * const drivers[] = {
3278         &mv643xx_eth_shared_driver,
3279         &mv643xx_eth_driver,
3280 };
3281 
3282 static int __init mv643xx_eth_init_module(void)
3283 {
3284         return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
3285 }
3286 module_init(mv643xx_eth_init_module);
3287 
3288 static void __exit mv643xx_eth_cleanup_module(void)
3289 {
3290         platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
3291 }
3292 module_exit(mv643xx_eth_cleanup_module);
3293 
3294 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3295               "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3296 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3297 MODULE_LICENSE("GPL");
3298 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
3299 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
3300 

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