Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/drivers/net/ethernet/marvell/mv643xx_eth.c

  1 /*
  2  * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
  3  * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
  4  *
  5  * Based on the 64360 driver from:
  6  * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
  7  *                    Rabeeh Khoury <rabeeh@marvell.com>
  8  *
  9  * Copyright (C) 2003 PMC-Sierra, Inc.,
 10  *      written by Manish Lachwani
 11  *
 12  * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
 13  *
 14  * Copyright (C) 2004-2006 MontaVista Software, Inc.
 15  *                         Dale Farnsworth <dale@farnsworth.org>
 16  *
 17  * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
 18  *                                   <sjhill@realitydiluted.com>
 19  *
 20  * Copyright (C) 2007-2008 Marvell Semiconductor
 21  *                         Lennert Buytenhek <buytenh@marvell.com>
 22  *
 23  * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de>
 24  *
 25  * This program is free software; you can redistribute it and/or
 26  * modify it under the terms of the GNU General Public License
 27  * as published by the Free Software Foundation; either version 2
 28  * of the License, or (at your option) any later version.
 29  *
 30  * This program is distributed in the hope that it will be useful,
 31  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 32  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 33  * GNU General Public License for more details.
 34  *
 35  * You should have received a copy of the GNU General Public License
 36  * along with this program; if not, see <http://www.gnu.org/licenses/>.
 37  */
 38 
 39 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 40 
 41 #include <linux/init.h>
 42 #include <linux/dma-mapping.h>
 43 #include <linux/in.h>
 44 #include <linux/ip.h>
 45 #include <net/tso.h>
 46 #include <linux/tcp.h>
 47 #include <linux/udp.h>
 48 #include <linux/etherdevice.h>
 49 #include <linux/delay.h>
 50 #include <linux/ethtool.h>
 51 #include <linux/platform_device.h>
 52 #include <linux/module.h>
 53 #include <linux/kernel.h>
 54 #include <linux/spinlock.h>
 55 #include <linux/workqueue.h>
 56 #include <linux/phy.h>
 57 #include <linux/mv643xx_eth.h>
 58 #include <linux/io.h>
 59 #include <linux/interrupt.h>
 60 #include <linux/types.h>
 61 #include <linux/slab.h>
 62 #include <linux/clk.h>
 63 #include <linux/of.h>
 64 #include <linux/of_irq.h>
 65 #include <linux/of_net.h>
 66 #include <linux/of_mdio.h>
 67 
 68 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
 69 static char mv643xx_eth_driver_version[] = "1.4";
 70 
 71 
 72 /*
 73  * Registers shared between all ports.
 74  */
 75 #define PHY_ADDR                        0x0000
 76 #define WINDOW_BASE(w)                  (0x0200 + ((w) << 3))
 77 #define WINDOW_SIZE(w)                  (0x0204 + ((w) << 3))
 78 #define WINDOW_REMAP_HIGH(w)            (0x0280 + ((w) << 2))
 79 #define WINDOW_BAR_ENABLE               0x0290
 80 #define WINDOW_PROTECT(w)               (0x0294 + ((w) << 4))
 81 
 82 /*
 83  * Main per-port registers.  These live at offset 0x0400 for
 84  * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
 85  */
 86 #define PORT_CONFIG                     0x0000
 87 #define  UNICAST_PROMISCUOUS_MODE       0x00000001
 88 #define PORT_CONFIG_EXT                 0x0004
 89 #define MAC_ADDR_LOW                    0x0014
 90 #define MAC_ADDR_HIGH                   0x0018
 91 #define SDMA_CONFIG                     0x001c
 92 #define  TX_BURST_SIZE_16_64BIT         0x01000000
 93 #define  TX_BURST_SIZE_4_64BIT          0x00800000
 94 #define  BLM_TX_NO_SWAP                 0x00000020
 95 #define  BLM_RX_NO_SWAP                 0x00000010
 96 #define  RX_BURST_SIZE_16_64BIT         0x00000008
 97 #define  RX_BURST_SIZE_4_64BIT          0x00000004
 98 #define PORT_SERIAL_CONTROL             0x003c
 99 #define  SET_MII_SPEED_TO_100           0x01000000
100 #define  SET_GMII_SPEED_TO_1000         0x00800000
101 #define  SET_FULL_DUPLEX_MODE           0x00200000
102 #define  MAX_RX_PACKET_9700BYTE         0x000a0000
103 #define  DISABLE_AUTO_NEG_SPEED_GMII    0x00002000
104 #define  DO_NOT_FORCE_LINK_FAIL         0x00000400
105 #define  SERIAL_PORT_CONTROL_RESERVED   0x00000200
106 #define  DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
107 #define  DISABLE_AUTO_NEG_FOR_DUPLEX    0x00000004
108 #define  FORCE_LINK_PASS                0x00000002
109 #define  SERIAL_PORT_ENABLE             0x00000001
110 #define PORT_STATUS                     0x0044
111 #define  TX_FIFO_EMPTY                  0x00000400
112 #define  TX_IN_PROGRESS                 0x00000080
113 #define  PORT_SPEED_MASK                0x00000030
114 #define  PORT_SPEED_1000                0x00000010
115 #define  PORT_SPEED_100                 0x00000020
116 #define  PORT_SPEED_10                  0x00000000
117 #define  FLOW_CONTROL_ENABLED           0x00000008
118 #define  FULL_DUPLEX                    0x00000004
119 #define  LINK_UP                        0x00000002
120 #define TXQ_COMMAND                     0x0048
121 #define TXQ_FIX_PRIO_CONF               0x004c
122 #define PORT_SERIAL_CONTROL1            0x004c
123 #define  CLK125_BYPASS_EN               0x00000010
124 #define TX_BW_RATE                      0x0050
125 #define TX_BW_MTU                       0x0058
126 #define TX_BW_BURST                     0x005c
127 #define INT_CAUSE                       0x0060
128 #define  INT_TX_END                     0x07f80000
129 #define  INT_TX_END_0                   0x00080000
130 #define  INT_RX                         0x000003fc
131 #define  INT_RX_0                       0x00000004
132 #define  INT_EXT                        0x00000002
133 #define INT_CAUSE_EXT                   0x0064
134 #define  INT_EXT_LINK_PHY               0x00110000
135 #define  INT_EXT_TX                     0x000000ff
136 #define INT_MASK                        0x0068
137 #define INT_MASK_EXT                    0x006c
138 #define TX_FIFO_URGENT_THRESHOLD        0x0074
139 #define RX_DISCARD_FRAME_CNT            0x0084
140 #define RX_OVERRUN_FRAME_CNT            0x0088
141 #define TXQ_FIX_PRIO_CONF_MOVED         0x00dc
142 #define TX_BW_RATE_MOVED                0x00e0
143 #define TX_BW_MTU_MOVED                 0x00e8
144 #define TX_BW_BURST_MOVED               0x00ec
145 #define RXQ_CURRENT_DESC_PTR(q)         (0x020c + ((q) << 4))
146 #define RXQ_COMMAND                     0x0280
147 #define TXQ_CURRENT_DESC_PTR(q)         (0x02c0 + ((q) << 2))
148 #define TXQ_BW_TOKENS(q)                (0x0300 + ((q) << 4))
149 #define TXQ_BW_CONF(q)                  (0x0304 + ((q) << 4))
150 #define TXQ_BW_WRR_CONF(q)              (0x0308 + ((q) << 4))
151 
152 /*
153  * Misc per-port registers.
154  */
155 #define MIB_COUNTERS(p)                 (0x1000 + ((p) << 7))
156 #define SPECIAL_MCAST_TABLE(p)          (0x1400 + ((p) << 10))
157 #define OTHER_MCAST_TABLE(p)            (0x1500 + ((p) << 10))
158 #define UNICAST_TABLE(p)                (0x1600 + ((p) << 10))
159 
160 
161 /*
162  * SDMA configuration register default value.
163  */
164 #if defined(__BIG_ENDIAN)
165 #define PORT_SDMA_CONFIG_DEFAULT_VALUE          \
166                 (RX_BURST_SIZE_4_64BIT  |       \
167                  TX_BURST_SIZE_4_64BIT)
168 #elif defined(__LITTLE_ENDIAN)
169 #define PORT_SDMA_CONFIG_DEFAULT_VALUE          \
170                 (RX_BURST_SIZE_4_64BIT  |       \
171                  BLM_RX_NO_SWAP         |       \
172                  BLM_TX_NO_SWAP         |       \
173                  TX_BURST_SIZE_4_64BIT)
174 #else
175 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
176 #endif
177 
178 
179 /*
180  * Misc definitions.
181  */
182 #define DEFAULT_RX_QUEUE_SIZE   128
183 #define DEFAULT_TX_QUEUE_SIZE   512
184 #define SKB_DMA_REALIGN         ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
185 
186 #define TSO_HEADER_SIZE         128
187 
188 /* Max number of allowed TCP segments for software TSO */
189 #define MV643XX_MAX_TSO_SEGS 100
190 #define MV643XX_MAX_SKB_DESCS (MV643XX_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
191 
192 #define IS_TSO_HEADER(txq, addr) \
193         ((addr >= txq->tso_hdrs_dma) && \
194          (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
195 /*
196  * RX/TX descriptors.
197  */
198 #if defined(__BIG_ENDIAN)
199 struct rx_desc {
200         u16 byte_cnt;           /* Descriptor buffer byte count         */
201         u16 buf_size;           /* Buffer size                          */
202         u32 cmd_sts;            /* Descriptor command status            */
203         u32 next_desc_ptr;      /* Next descriptor pointer              */
204         u32 buf_ptr;            /* Descriptor buffer pointer            */
205 };
206 
207 struct tx_desc {
208         u16 byte_cnt;           /* buffer byte count                    */
209         u16 l4i_chk;            /* CPU provided TCP checksum            */
210         u32 cmd_sts;            /* Command/status field                 */
211         u32 next_desc_ptr;      /* Pointer to next descriptor           */
212         u32 buf_ptr;            /* pointer to buffer for this descriptor*/
213 };
214 #elif defined(__LITTLE_ENDIAN)
215 struct rx_desc {
216         u32 cmd_sts;            /* Descriptor command status            */
217         u16 buf_size;           /* Buffer size                          */
218         u16 byte_cnt;           /* Descriptor buffer byte count         */
219         u32 buf_ptr;            /* Descriptor buffer pointer            */
220         u32 next_desc_ptr;      /* Next descriptor pointer              */
221 };
222 
223 struct tx_desc {
224         u32 cmd_sts;            /* Command/status field                 */
225         u16 l4i_chk;            /* CPU provided TCP checksum            */
226         u16 byte_cnt;           /* buffer byte count                    */
227         u32 buf_ptr;            /* pointer to buffer for this descriptor*/
228         u32 next_desc_ptr;      /* Pointer to next descriptor           */
229 };
230 #else
231 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
232 #endif
233 
234 /* RX & TX descriptor command */
235 #define BUFFER_OWNED_BY_DMA             0x80000000
236 
237 /* RX & TX descriptor status */
238 #define ERROR_SUMMARY                   0x00000001
239 
240 /* RX descriptor status */
241 #define LAYER_4_CHECKSUM_OK             0x40000000
242 #define RX_ENABLE_INTERRUPT             0x20000000
243 #define RX_FIRST_DESC                   0x08000000
244 #define RX_LAST_DESC                    0x04000000
245 #define RX_IP_HDR_OK                    0x02000000
246 #define RX_PKT_IS_IPV4                  0x01000000
247 #define RX_PKT_IS_ETHERNETV2            0x00800000
248 #define RX_PKT_LAYER4_TYPE_MASK         0x00600000
249 #define RX_PKT_LAYER4_TYPE_TCP_IPV4     0x00000000
250 #define RX_PKT_IS_VLAN_TAGGED           0x00080000
251 
252 /* TX descriptor command */
253 #define TX_ENABLE_INTERRUPT             0x00800000
254 #define GEN_CRC                         0x00400000
255 #define TX_FIRST_DESC                   0x00200000
256 #define TX_LAST_DESC                    0x00100000
257 #define ZERO_PADDING                    0x00080000
258 #define GEN_IP_V4_CHECKSUM              0x00040000
259 #define GEN_TCP_UDP_CHECKSUM            0x00020000
260 #define UDP_FRAME                       0x00010000
261 #define MAC_HDR_EXTRA_4_BYTES           0x00008000
262 #define GEN_TCP_UDP_CHK_FULL            0x00000400
263 #define MAC_HDR_EXTRA_8_BYTES           0x00000200
264 
265 #define TX_IHL_SHIFT                    11
266 
267 
268 /* global *******************************************************************/
269 struct mv643xx_eth_shared_private {
270         /*
271          * Ethernet controller base address.
272          */
273         void __iomem *base;
274 
275         /*
276          * Per-port MBUS window access register value.
277          */
278         u32 win_protect;
279 
280         /*
281          * Hardware-specific parameters.
282          */
283         int extended_rx_coal_limit;
284         int tx_bw_control;
285         int tx_csum_limit;
286         struct clk *clk;
287 };
288 
289 #define TX_BW_CONTROL_ABSENT            0
290 #define TX_BW_CONTROL_OLD_LAYOUT        1
291 #define TX_BW_CONTROL_NEW_LAYOUT        2
292 
293 static int mv643xx_eth_open(struct net_device *dev);
294 static int mv643xx_eth_stop(struct net_device *dev);
295 
296 
297 /* per-port *****************************************************************/
298 struct mib_counters {
299         u64 good_octets_received;
300         u32 bad_octets_received;
301         u32 internal_mac_transmit_err;
302         u32 good_frames_received;
303         u32 bad_frames_received;
304         u32 broadcast_frames_received;
305         u32 multicast_frames_received;
306         u32 frames_64_octets;
307         u32 frames_65_to_127_octets;
308         u32 frames_128_to_255_octets;
309         u32 frames_256_to_511_octets;
310         u32 frames_512_to_1023_octets;
311         u32 frames_1024_to_max_octets;
312         u64 good_octets_sent;
313         u32 good_frames_sent;
314         u32 excessive_collision;
315         u32 multicast_frames_sent;
316         u32 broadcast_frames_sent;
317         u32 unrec_mac_control_received;
318         u32 fc_sent;
319         u32 good_fc_received;
320         u32 bad_fc_received;
321         u32 undersize_received;
322         u32 fragments_received;
323         u32 oversize_received;
324         u32 jabber_received;
325         u32 mac_receive_error;
326         u32 bad_crc_event;
327         u32 collision;
328         u32 late_collision;
329         /* Non MIB hardware counters */
330         u32 rx_discard;
331         u32 rx_overrun;
332 };
333 
334 struct rx_queue {
335         int index;
336 
337         int rx_ring_size;
338 
339         int rx_desc_count;
340         int rx_curr_desc;
341         int rx_used_desc;
342 
343         struct rx_desc *rx_desc_area;
344         dma_addr_t rx_desc_dma;
345         int rx_desc_area_size;
346         struct sk_buff **rx_skb;
347 };
348 
349 struct tx_queue {
350         int index;
351 
352         int tx_ring_size;
353 
354         int tx_desc_count;
355         int tx_curr_desc;
356         int tx_used_desc;
357 
358         int tx_stop_threshold;
359         int tx_wake_threshold;
360 
361         char *tso_hdrs;
362         dma_addr_t tso_hdrs_dma;
363 
364         struct tx_desc *tx_desc_area;
365         dma_addr_t tx_desc_dma;
366         int tx_desc_area_size;
367 
368         struct sk_buff_head tx_skb;
369 
370         unsigned long tx_packets;
371         unsigned long tx_bytes;
372         unsigned long tx_dropped;
373 };
374 
375 struct mv643xx_eth_private {
376         struct mv643xx_eth_shared_private *shared;
377         void __iomem *base;
378         int port_num;
379 
380         struct net_device *dev;
381 
382         struct phy_device *phy;
383 
384         struct timer_list mib_counters_timer;
385         spinlock_t mib_counters_lock;
386         struct mib_counters mib_counters;
387 
388         struct work_struct tx_timeout_task;
389 
390         struct napi_struct napi;
391         u32 int_mask;
392         u8 oom;
393         u8 work_link;
394         u8 work_tx;
395         u8 work_tx_end;
396         u8 work_rx;
397         u8 work_rx_refill;
398 
399         int skb_size;
400 
401         /*
402          * RX state.
403          */
404         int rx_ring_size;
405         unsigned long rx_desc_sram_addr;
406         int rx_desc_sram_size;
407         int rxq_count;
408         struct timer_list rx_oom;
409         struct rx_queue rxq[8];
410 
411         /*
412          * TX state.
413          */
414         int tx_ring_size;
415         unsigned long tx_desc_sram_addr;
416         int tx_desc_sram_size;
417         int txq_count;
418         struct tx_queue txq[8];
419 
420         /*
421          * Hardware-specific parameters.
422          */
423         struct clk *clk;
424         unsigned int t_clk;
425 };
426 
427 
428 /* port register accessors **************************************************/
429 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
430 {
431         return readl(mp->shared->base + offset);
432 }
433 
434 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
435 {
436         return readl(mp->base + offset);
437 }
438 
439 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
440 {
441         writel(data, mp->shared->base + offset);
442 }
443 
444 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
445 {
446         writel(data, mp->base + offset);
447 }
448 
449 
450 /* rxq/txq helper functions *************************************************/
451 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
452 {
453         return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
454 }
455 
456 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
457 {
458         return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
459 }
460 
461 static void rxq_enable(struct rx_queue *rxq)
462 {
463         struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
464         wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
465 }
466 
467 static void rxq_disable(struct rx_queue *rxq)
468 {
469         struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
470         u8 mask = 1 << rxq->index;
471 
472         wrlp(mp, RXQ_COMMAND, mask << 8);
473         while (rdlp(mp, RXQ_COMMAND) & mask)
474                 udelay(10);
475 }
476 
477 static void txq_reset_hw_ptr(struct tx_queue *txq)
478 {
479         struct mv643xx_eth_private *mp = txq_to_mp(txq);
480         u32 addr;
481 
482         addr = (u32)txq->tx_desc_dma;
483         addr += txq->tx_curr_desc * sizeof(struct tx_desc);
484         wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
485 }
486 
487 static void txq_enable(struct tx_queue *txq)
488 {
489         struct mv643xx_eth_private *mp = txq_to_mp(txq);
490         wrlp(mp, TXQ_COMMAND, 1 << txq->index);
491 }
492 
493 static void txq_disable(struct tx_queue *txq)
494 {
495         struct mv643xx_eth_private *mp = txq_to_mp(txq);
496         u8 mask = 1 << txq->index;
497 
498         wrlp(mp, TXQ_COMMAND, mask << 8);
499         while (rdlp(mp, TXQ_COMMAND) & mask)
500                 udelay(10);
501 }
502 
503 static void txq_maybe_wake(struct tx_queue *txq)
504 {
505         struct mv643xx_eth_private *mp = txq_to_mp(txq);
506         struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
507 
508         if (netif_tx_queue_stopped(nq)) {
509                 __netif_tx_lock(nq, smp_processor_id());
510                 if (txq->tx_desc_count <= txq->tx_wake_threshold)
511                         netif_tx_wake_queue(nq);
512                 __netif_tx_unlock(nq);
513         }
514 }
515 
516 static int rxq_process(struct rx_queue *rxq, int budget)
517 {
518         struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
519         struct net_device_stats *stats = &mp->dev->stats;
520         int rx;
521 
522         rx = 0;
523         while (rx < budget && rxq->rx_desc_count) {
524                 struct rx_desc *rx_desc;
525                 unsigned int cmd_sts;
526                 struct sk_buff *skb;
527                 u16 byte_cnt;
528 
529                 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
530 
531                 cmd_sts = rx_desc->cmd_sts;
532                 if (cmd_sts & BUFFER_OWNED_BY_DMA)
533                         break;
534                 rmb();
535 
536                 skb = rxq->rx_skb[rxq->rx_curr_desc];
537                 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
538 
539                 rxq->rx_curr_desc++;
540                 if (rxq->rx_curr_desc == rxq->rx_ring_size)
541                         rxq->rx_curr_desc = 0;
542 
543                 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
544                                  rx_desc->buf_size, DMA_FROM_DEVICE);
545                 rxq->rx_desc_count--;
546                 rx++;
547 
548                 mp->work_rx_refill |= 1 << rxq->index;
549 
550                 byte_cnt = rx_desc->byte_cnt;
551 
552                 /*
553                  * Update statistics.
554                  *
555                  * Note that the descriptor byte count includes 2 dummy
556                  * bytes automatically inserted by the hardware at the
557                  * start of the packet (which we don't count), and a 4
558                  * byte CRC at the end of the packet (which we do count).
559                  */
560                 stats->rx_packets++;
561                 stats->rx_bytes += byte_cnt - 2;
562 
563                 /*
564                  * In case we received a packet without first / last bits
565                  * on, or the error summary bit is set, the packet needs
566                  * to be dropped.
567                  */
568                 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
569                         != (RX_FIRST_DESC | RX_LAST_DESC))
570                         goto err;
571 
572                 /*
573                  * The -4 is for the CRC in the trailer of the
574                  * received packet
575                  */
576                 skb_put(skb, byte_cnt - 2 - 4);
577 
578                 if (cmd_sts & LAYER_4_CHECKSUM_OK)
579                         skb->ip_summed = CHECKSUM_UNNECESSARY;
580                 skb->protocol = eth_type_trans(skb, mp->dev);
581 
582                 napi_gro_receive(&mp->napi, skb);
583 
584                 continue;
585 
586 err:
587                 stats->rx_dropped++;
588 
589                 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
590                         (RX_FIRST_DESC | RX_LAST_DESC)) {
591                         if (net_ratelimit())
592                                 netdev_err(mp->dev,
593                                            "received packet spanning multiple descriptors\n");
594                 }
595 
596                 if (cmd_sts & ERROR_SUMMARY)
597                         stats->rx_errors++;
598 
599                 dev_kfree_skb(skb);
600         }
601 
602         if (rx < budget)
603                 mp->work_rx &= ~(1 << rxq->index);
604 
605         return rx;
606 }
607 
608 static int rxq_refill(struct rx_queue *rxq, int budget)
609 {
610         struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
611         int refilled;
612 
613         refilled = 0;
614         while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
615                 struct sk_buff *skb;
616                 int rx;
617                 struct rx_desc *rx_desc;
618                 int size;
619 
620                 skb = netdev_alloc_skb(mp->dev, mp->skb_size);
621 
622                 if (skb == NULL) {
623                         mp->oom = 1;
624                         goto oom;
625                 }
626 
627                 if (SKB_DMA_REALIGN)
628                         skb_reserve(skb, SKB_DMA_REALIGN);
629 
630                 refilled++;
631                 rxq->rx_desc_count++;
632 
633                 rx = rxq->rx_used_desc++;
634                 if (rxq->rx_used_desc == rxq->rx_ring_size)
635                         rxq->rx_used_desc = 0;
636 
637                 rx_desc = rxq->rx_desc_area + rx;
638 
639                 size = skb_end_pointer(skb) - skb->data;
640                 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
641                                                   skb->data, size,
642                                                   DMA_FROM_DEVICE);
643                 rx_desc->buf_size = size;
644                 rxq->rx_skb[rx] = skb;
645                 wmb();
646                 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
647                 wmb();
648 
649                 /*
650                  * The hardware automatically prepends 2 bytes of
651                  * dummy data to each received packet, so that the
652                  * IP header ends up 16-byte aligned.
653                  */
654                 skb_reserve(skb, 2);
655         }
656 
657         if (refilled < budget)
658                 mp->work_rx_refill &= ~(1 << rxq->index);
659 
660 oom:
661         return refilled;
662 }
663 
664 
665 /* tx ***********************************************************************/
666 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
667 {
668         int frag;
669 
670         for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
671                 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
672 
673                 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7)
674                         return 1;
675         }
676 
677         return 0;
678 }
679 
680 static inline __be16 sum16_as_be(__sum16 sum)
681 {
682         return (__force __be16)sum;
683 }
684 
685 static int skb_tx_csum(struct mv643xx_eth_private *mp, struct sk_buff *skb,
686                        u16 *l4i_chk, u32 *command, int length)
687 {
688         int ret;
689         u32 cmd = 0;
690 
691         if (skb->ip_summed == CHECKSUM_PARTIAL) {
692                 int hdr_len;
693                 int tag_bytes;
694 
695                 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
696                        skb->protocol != htons(ETH_P_8021Q));
697 
698                 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
699                 tag_bytes = hdr_len - ETH_HLEN;
700 
701                 if (length - hdr_len > mp->shared->tx_csum_limit ||
702                     unlikely(tag_bytes & ~12)) {
703                         ret = skb_checksum_help(skb);
704                         if (!ret)
705                                 goto no_csum;
706                         return ret;
707                 }
708 
709                 if (tag_bytes & 4)
710                         cmd |= MAC_HDR_EXTRA_4_BYTES;
711                 if (tag_bytes & 8)
712                         cmd |= MAC_HDR_EXTRA_8_BYTES;
713 
714                 cmd |= GEN_TCP_UDP_CHECKSUM | GEN_TCP_UDP_CHK_FULL |
715                            GEN_IP_V4_CHECKSUM   |
716                            ip_hdr(skb)->ihl << TX_IHL_SHIFT;
717 
718                 /* TODO: Revisit this. With the usage of GEN_TCP_UDP_CHK_FULL
719                  * it seems we don't need to pass the initial checksum. */
720                 switch (ip_hdr(skb)->protocol) {
721                 case IPPROTO_UDP:
722                         cmd |= UDP_FRAME;
723                         *l4i_chk = 0;
724                         break;
725                 case IPPROTO_TCP:
726                         *l4i_chk = 0;
727                         break;
728                 default:
729                         WARN(1, "protocol not supported");
730                 }
731         } else {
732 no_csum:
733                 /* Errata BTS #50, IHL must be 5 if no HW checksum */
734                 cmd |= 5 << TX_IHL_SHIFT;
735         }
736         *command = cmd;
737         return 0;
738 }
739 
740 static inline int
741 txq_put_data_tso(struct net_device *dev, struct tx_queue *txq,
742                  struct sk_buff *skb, char *data, int length,
743                  bool last_tcp, bool is_last)
744 {
745         int tx_index;
746         u32 cmd_sts;
747         struct tx_desc *desc;
748 
749         tx_index = txq->tx_curr_desc++;
750         if (txq->tx_curr_desc == txq->tx_ring_size)
751                 txq->tx_curr_desc = 0;
752         desc = &txq->tx_desc_area[tx_index];
753 
754         desc->l4i_chk = 0;
755         desc->byte_cnt = length;
756         desc->buf_ptr = dma_map_single(dev->dev.parent, data,
757                                        length, DMA_TO_DEVICE);
758         if (unlikely(dma_mapping_error(dev->dev.parent, desc->buf_ptr))) {
759                 WARN(1, "dma_map_single failed!\n");
760                 return -ENOMEM;
761         }
762 
763         cmd_sts = BUFFER_OWNED_BY_DMA;
764         if (last_tcp) {
765                 /* last descriptor in the TCP packet */
766                 cmd_sts |= ZERO_PADDING | TX_LAST_DESC;
767                 /* last descriptor in SKB */
768                 if (is_last)
769                         cmd_sts |= TX_ENABLE_INTERRUPT;
770         }
771         desc->cmd_sts = cmd_sts;
772         return 0;
773 }
774 
775 static inline void
776 txq_put_hdr_tso(struct sk_buff *skb, struct tx_queue *txq, int length)
777 {
778         struct mv643xx_eth_private *mp = txq_to_mp(txq);
779         int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
780         int tx_index;
781         struct tx_desc *desc;
782         int ret;
783         u32 cmd_csum = 0;
784         u16 l4i_chk = 0;
785 
786         tx_index = txq->tx_curr_desc;
787         desc = &txq->tx_desc_area[tx_index];
788 
789         ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_csum, length);
790         if (ret)
791                 WARN(1, "failed to prepare checksum!");
792 
793         /* Should we set this? Can't use the value from skb_tx_csum()
794          * as it's not the correct initial L4 checksum to use. */
795         desc->l4i_chk = 0;
796 
797         desc->byte_cnt = hdr_len;
798         desc->buf_ptr = txq->tso_hdrs_dma +
799                         txq->tx_curr_desc * TSO_HEADER_SIZE;
800         desc->cmd_sts = cmd_csum | BUFFER_OWNED_BY_DMA  | TX_FIRST_DESC |
801                                    GEN_CRC;
802 
803         txq->tx_curr_desc++;
804         if (txq->tx_curr_desc == txq->tx_ring_size)
805                 txq->tx_curr_desc = 0;
806 }
807 
808 static int txq_submit_tso(struct tx_queue *txq, struct sk_buff *skb,
809                           struct net_device *dev)
810 {
811         struct mv643xx_eth_private *mp = txq_to_mp(txq);
812         int total_len, data_left, ret;
813         int desc_count = 0;
814         struct tso_t tso;
815         int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
816 
817         /* Count needed descriptors */
818         if ((txq->tx_desc_count + tso_count_descs(skb)) >= txq->tx_ring_size) {
819                 netdev_dbg(dev, "not enough descriptors for TSO!\n");
820                 return -EBUSY;
821         }
822 
823         /* Initialize the TSO handler, and prepare the first payload */
824         tso_start(skb, &tso);
825 
826         total_len = skb->len - hdr_len;
827         while (total_len > 0) {
828                 char *hdr;
829 
830                 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
831                 total_len -= data_left;
832                 desc_count++;
833 
834                 /* prepare packet headers: MAC + IP + TCP */
835                 hdr = txq->tso_hdrs + txq->tx_curr_desc * TSO_HEADER_SIZE;
836                 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
837                 txq_put_hdr_tso(skb, txq, data_left);
838 
839                 while (data_left > 0) {
840                         int size;
841                         desc_count++;
842 
843                         size = min_t(int, tso.size, data_left);
844                         ret = txq_put_data_tso(dev, txq, skb, tso.data, size,
845                                                size == data_left,
846                                                total_len == 0);
847                         if (ret)
848                                 goto err_release;
849                         data_left -= size;
850                         tso_build_data(skb, &tso, size);
851                 }
852         }
853 
854         __skb_queue_tail(&txq->tx_skb, skb);
855         skb_tx_timestamp(skb);
856 
857         /* clear TX_END status */
858         mp->work_tx_end &= ~(1 << txq->index);
859 
860         /* ensure all descriptors are written before poking hardware */
861         wmb();
862         txq_enable(txq);
863         txq->tx_desc_count += desc_count;
864         return 0;
865 err_release:
866         /* TODO: Release all used data descriptors; header descriptors must not
867          * be DMA-unmapped.
868          */
869         return ret;
870 }
871 
872 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
873 {
874         struct mv643xx_eth_private *mp = txq_to_mp(txq);
875         int nr_frags = skb_shinfo(skb)->nr_frags;
876         int frag;
877 
878         for (frag = 0; frag < nr_frags; frag++) {
879                 skb_frag_t *this_frag;
880                 int tx_index;
881                 struct tx_desc *desc;
882                 void *addr;
883 
884                 this_frag = &skb_shinfo(skb)->frags[frag];
885                 addr = page_address(this_frag->page.p) + this_frag->page_offset;
886                 tx_index = txq->tx_curr_desc++;
887                 if (txq->tx_curr_desc == txq->tx_ring_size)
888                         txq->tx_curr_desc = 0;
889                 desc = &txq->tx_desc_area[tx_index];
890 
891                 /*
892                  * The last fragment will generate an interrupt
893                  * which will free the skb on TX completion.
894                  */
895                 if (frag == nr_frags - 1) {
896                         desc->cmd_sts = BUFFER_OWNED_BY_DMA |
897                                         ZERO_PADDING | TX_LAST_DESC |
898                                         TX_ENABLE_INTERRUPT;
899                 } else {
900                         desc->cmd_sts = BUFFER_OWNED_BY_DMA;
901                 }
902 
903                 desc->l4i_chk = 0;
904                 desc->byte_cnt = skb_frag_size(this_frag);
905                 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, addr,
906                                                desc->byte_cnt, DMA_TO_DEVICE);
907         }
908 }
909 
910 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb,
911                           struct net_device *dev)
912 {
913         struct mv643xx_eth_private *mp = txq_to_mp(txq);
914         int nr_frags = skb_shinfo(skb)->nr_frags;
915         int tx_index;
916         struct tx_desc *desc;
917         u32 cmd_sts;
918         u16 l4i_chk;
919         int length, ret;
920 
921         cmd_sts = 0;
922         l4i_chk = 0;
923 
924         if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
925                 if (net_ratelimit())
926                         netdev_err(dev, "tx queue full?!\n");
927                 return -EBUSY;
928         }
929 
930         ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_sts, skb->len);
931         if (ret)
932                 return ret;
933         cmd_sts |= TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
934 
935         tx_index = txq->tx_curr_desc++;
936         if (txq->tx_curr_desc == txq->tx_ring_size)
937                 txq->tx_curr_desc = 0;
938         desc = &txq->tx_desc_area[tx_index];
939 
940         if (nr_frags) {
941                 txq_submit_frag_skb(txq, skb);
942                 length = skb_headlen(skb);
943         } else {
944                 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
945                 length = skb->len;
946         }
947 
948         desc->l4i_chk = l4i_chk;
949         desc->byte_cnt = length;
950         desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
951                                        length, DMA_TO_DEVICE);
952 
953         __skb_queue_tail(&txq->tx_skb, skb);
954 
955         skb_tx_timestamp(skb);
956 
957         /* ensure all other descriptors are written before first cmd_sts */
958         wmb();
959         desc->cmd_sts = cmd_sts;
960 
961         /* clear TX_END status */
962         mp->work_tx_end &= ~(1 << txq->index);
963 
964         /* ensure all descriptors are written before poking hardware */
965         wmb();
966         txq_enable(txq);
967 
968         txq->tx_desc_count += nr_frags + 1;
969 
970         return 0;
971 }
972 
973 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
974 {
975         struct mv643xx_eth_private *mp = netdev_priv(dev);
976         int length, queue, ret;
977         struct tx_queue *txq;
978         struct netdev_queue *nq;
979 
980         queue = skb_get_queue_mapping(skb);
981         txq = mp->txq + queue;
982         nq = netdev_get_tx_queue(dev, queue);
983 
984         if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
985                 netdev_printk(KERN_DEBUG, dev,
986                               "failed to linearize skb with tiny unaligned fragment\n");
987                 return NETDEV_TX_BUSY;
988         }
989 
990         length = skb->len;
991 
992         if (skb_is_gso(skb))
993                 ret = txq_submit_tso(txq, skb, dev);
994         else
995                 ret = txq_submit_skb(txq, skb, dev);
996         if (!ret) {
997                 txq->tx_bytes += length;
998                 txq->tx_packets++;
999 
1000                 if (txq->tx_desc_count >= txq->tx_stop_threshold)
1001                         netif_tx_stop_queue(nq);
1002         } else {
1003                 txq->tx_dropped++;
1004                 dev_kfree_skb_any(skb);
1005         }
1006 
1007         return NETDEV_TX_OK;
1008 }
1009 
1010 
1011 /* tx napi ******************************************************************/
1012 static void txq_kick(struct tx_queue *txq)
1013 {
1014         struct mv643xx_eth_private *mp = txq_to_mp(txq);
1015         struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1016         u32 hw_desc_ptr;
1017         u32 expected_ptr;
1018 
1019         __netif_tx_lock(nq, smp_processor_id());
1020 
1021         if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1022                 goto out;
1023 
1024         hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1025         expected_ptr = (u32)txq->tx_desc_dma +
1026                                 txq->tx_curr_desc * sizeof(struct tx_desc);
1027 
1028         if (hw_desc_ptr != expected_ptr)
1029                 txq_enable(txq);
1030 
1031 out:
1032         __netif_tx_unlock(nq);
1033 
1034         mp->work_tx_end &= ~(1 << txq->index);
1035 }
1036 
1037 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
1038 {
1039         struct mv643xx_eth_private *mp = txq_to_mp(txq);
1040         struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1041         int reclaimed;
1042 
1043         __netif_tx_lock_bh(nq);
1044 
1045         reclaimed = 0;
1046         while (reclaimed < budget && txq->tx_desc_count > 0) {
1047                 int tx_index;
1048                 struct tx_desc *desc;
1049                 u32 cmd_sts;
1050 
1051                 tx_index = txq->tx_used_desc;
1052                 desc = &txq->tx_desc_area[tx_index];
1053                 cmd_sts = desc->cmd_sts;
1054 
1055                 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1056                         if (!force)
1057                                 break;
1058                         desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1059                 }
1060 
1061                 txq->tx_used_desc = tx_index + 1;
1062                 if (txq->tx_used_desc == txq->tx_ring_size)
1063                         txq->tx_used_desc = 0;
1064 
1065                 reclaimed++;
1066                 txq->tx_desc_count--;
1067 
1068                 if (!IS_TSO_HEADER(txq, desc->buf_ptr))
1069                         dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
1070                                          desc->byte_cnt, DMA_TO_DEVICE);
1071 
1072                 if (cmd_sts & TX_ENABLE_INTERRUPT) {
1073                         struct sk_buff *skb = __skb_dequeue(&txq->tx_skb);
1074 
1075                         if (!WARN_ON(!skb))
1076                                 dev_kfree_skb(skb);
1077                 }
1078 
1079                 if (cmd_sts & ERROR_SUMMARY) {
1080                         netdev_info(mp->dev, "tx error\n");
1081                         mp->dev->stats.tx_errors++;
1082                 }
1083 
1084         }
1085 
1086         __netif_tx_unlock_bh(nq);
1087 
1088         if (reclaimed < budget)
1089                 mp->work_tx &= ~(1 << txq->index);
1090 
1091         return reclaimed;
1092 }
1093 
1094 
1095 /* tx rate control **********************************************************/
1096 /*
1097  * Set total maximum TX rate (shared by all TX queues for this port)
1098  * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
1099  */
1100 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
1101 {
1102         int token_rate;
1103         int mtu;
1104         int bucket_size;
1105 
1106         token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1107         if (token_rate > 1023)
1108                 token_rate = 1023;
1109 
1110         mtu = (mp->dev->mtu + 255) >> 8;
1111         if (mtu > 63)
1112                 mtu = 63;
1113 
1114         bucket_size = (burst + 255) >> 8;
1115         if (bucket_size > 65535)
1116                 bucket_size = 65535;
1117 
1118         switch (mp->shared->tx_bw_control) {
1119         case TX_BW_CONTROL_OLD_LAYOUT:
1120                 wrlp(mp, TX_BW_RATE, token_rate);
1121                 wrlp(mp, TX_BW_MTU, mtu);
1122                 wrlp(mp, TX_BW_BURST, bucket_size);
1123                 break;
1124         case TX_BW_CONTROL_NEW_LAYOUT:
1125                 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1126                 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1127                 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
1128                 break;
1129         }
1130 }
1131 
1132 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1133 {
1134         struct mv643xx_eth_private *mp = txq_to_mp(txq);
1135         int token_rate;
1136         int bucket_size;
1137 
1138         token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1139         if (token_rate > 1023)
1140                 token_rate = 1023;
1141 
1142         bucket_size = (burst + 255) >> 8;
1143         if (bucket_size > 65535)
1144                 bucket_size = 65535;
1145 
1146         wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1147         wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
1148 }
1149 
1150 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1151 {
1152         struct mv643xx_eth_private *mp = txq_to_mp(txq);
1153         int off;
1154         u32 val;
1155 
1156         /*
1157          * Turn on fixed priority mode.
1158          */
1159         off = 0;
1160         switch (mp->shared->tx_bw_control) {
1161         case TX_BW_CONTROL_OLD_LAYOUT:
1162                 off = TXQ_FIX_PRIO_CONF;
1163                 break;
1164         case TX_BW_CONTROL_NEW_LAYOUT:
1165                 off = TXQ_FIX_PRIO_CONF_MOVED;
1166                 break;
1167         }
1168 
1169         if (off) {
1170                 val = rdlp(mp, off);
1171                 val |= 1 << txq->index;
1172                 wrlp(mp, off, val);
1173         }
1174 }
1175 
1176 
1177 /* mii management interface *************************************************/
1178 static void mv643xx_eth_adjust_link(struct net_device *dev)
1179 {
1180         struct mv643xx_eth_private *mp = netdev_priv(dev);
1181         u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
1182         u32 autoneg_disable = FORCE_LINK_PASS |
1183                      DISABLE_AUTO_NEG_SPEED_GMII |
1184                      DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1185                      DISABLE_AUTO_NEG_FOR_DUPLEX;
1186 
1187         if (mp->phy->autoneg == AUTONEG_ENABLE) {
1188                 /* enable auto negotiation */
1189                 pscr &= ~autoneg_disable;
1190                 goto out_write;
1191         }
1192 
1193         pscr |= autoneg_disable;
1194 
1195         if (mp->phy->speed == SPEED_1000) {
1196                 /* force gigabit, half duplex not supported */
1197                 pscr |= SET_GMII_SPEED_TO_1000;
1198                 pscr |= SET_FULL_DUPLEX_MODE;
1199                 goto out_write;
1200         }
1201 
1202         pscr &= ~SET_GMII_SPEED_TO_1000;
1203 
1204         if (mp->phy->speed == SPEED_100)
1205                 pscr |= SET_MII_SPEED_TO_100;
1206         else
1207                 pscr &= ~SET_MII_SPEED_TO_100;
1208 
1209         if (mp->phy->duplex == DUPLEX_FULL)
1210                 pscr |= SET_FULL_DUPLEX_MODE;
1211         else
1212                 pscr &= ~SET_FULL_DUPLEX_MODE;
1213 
1214 out_write:
1215         wrlp(mp, PORT_SERIAL_CONTROL, pscr);
1216 }
1217 
1218 /* statistics ***************************************************************/
1219 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1220 {
1221         struct mv643xx_eth_private *mp = netdev_priv(dev);
1222         struct net_device_stats *stats = &dev->stats;
1223         unsigned long tx_packets = 0;
1224         unsigned long tx_bytes = 0;
1225         unsigned long tx_dropped = 0;
1226         int i;
1227 
1228         for (i = 0; i < mp->txq_count; i++) {
1229                 struct tx_queue *txq = mp->txq + i;
1230 
1231                 tx_packets += txq->tx_packets;
1232                 tx_bytes += txq->tx_bytes;
1233                 tx_dropped += txq->tx_dropped;
1234         }
1235 
1236         stats->tx_packets = tx_packets;
1237         stats->tx_bytes = tx_bytes;
1238         stats->tx_dropped = tx_dropped;
1239 
1240         return stats;
1241 }
1242 
1243 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1244 {
1245         return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1246 }
1247 
1248 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1249 {
1250         int i;
1251 
1252         for (i = 0; i < 0x80; i += 4)
1253                 mib_read(mp, i);
1254 
1255         /* Clear non MIB hw counters also */
1256         rdlp(mp, RX_DISCARD_FRAME_CNT);
1257         rdlp(mp, RX_OVERRUN_FRAME_CNT);
1258 }
1259 
1260 static void mib_counters_update(struct mv643xx_eth_private *mp)
1261 {
1262         struct mib_counters *p = &mp->mib_counters;
1263 
1264         spin_lock_bh(&mp->mib_counters_lock);
1265         p->good_octets_received += mib_read(mp, 0x00);
1266         p->bad_octets_received += mib_read(mp, 0x08);
1267         p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1268         p->good_frames_received += mib_read(mp, 0x10);
1269         p->bad_frames_received += mib_read(mp, 0x14);
1270         p->broadcast_frames_received += mib_read(mp, 0x18);
1271         p->multicast_frames_received += mib_read(mp, 0x1c);
1272         p->frames_64_octets += mib_read(mp, 0x20);
1273         p->frames_65_to_127_octets += mib_read(mp, 0x24);
1274         p->frames_128_to_255_octets += mib_read(mp, 0x28);
1275         p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1276         p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1277         p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1278         p->good_octets_sent += mib_read(mp, 0x38);
1279         p->good_frames_sent += mib_read(mp, 0x40);
1280         p->excessive_collision += mib_read(mp, 0x44);
1281         p->multicast_frames_sent += mib_read(mp, 0x48);
1282         p->broadcast_frames_sent += mib_read(mp, 0x4c);
1283         p->unrec_mac_control_received += mib_read(mp, 0x50);
1284         p->fc_sent += mib_read(mp, 0x54);
1285         p->good_fc_received += mib_read(mp, 0x58);
1286         p->bad_fc_received += mib_read(mp, 0x5c);
1287         p->undersize_received += mib_read(mp, 0x60);
1288         p->fragments_received += mib_read(mp, 0x64);
1289         p->oversize_received += mib_read(mp, 0x68);
1290         p->jabber_received += mib_read(mp, 0x6c);
1291         p->mac_receive_error += mib_read(mp, 0x70);
1292         p->bad_crc_event += mib_read(mp, 0x74);
1293         p->collision += mib_read(mp, 0x78);
1294         p->late_collision += mib_read(mp, 0x7c);
1295         /* Non MIB hardware counters */
1296         p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1297         p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
1298         spin_unlock_bh(&mp->mib_counters_lock);
1299 }
1300 
1301 static void mib_counters_timer_wrapper(unsigned long _mp)
1302 {
1303         struct mv643xx_eth_private *mp = (void *)_mp;
1304         mib_counters_update(mp);
1305         mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1306 }
1307 
1308 
1309 /* interrupt coalescing *****************************************************/
1310 /*
1311  * Hardware coalescing parameters are set in units of 64 t_clk
1312  * cycles.  I.e.:
1313  *
1314  *      coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1315  *
1316  *      register_value = coal_delay_in_usec * t_clk_rate / 64000000
1317  *
1318  * In the ->set*() methods, we round the computed register value
1319  * to the nearest integer.
1320  */
1321 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1322 {
1323         u32 val = rdlp(mp, SDMA_CONFIG);
1324         u64 temp;
1325 
1326         if (mp->shared->extended_rx_coal_limit)
1327                 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1328         else
1329                 temp = (val & 0x003fff00) >> 8;
1330 
1331         temp *= 64000000;
1332         do_div(temp, mp->t_clk);
1333 
1334         return (unsigned int)temp;
1335 }
1336 
1337 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1338 {
1339         u64 temp;
1340         u32 val;
1341 
1342         temp = (u64)usec * mp->t_clk;
1343         temp += 31999999;
1344         do_div(temp, 64000000);
1345 
1346         val = rdlp(mp, SDMA_CONFIG);
1347         if (mp->shared->extended_rx_coal_limit) {
1348                 if (temp > 0xffff)
1349                         temp = 0xffff;
1350                 val &= ~0x023fff80;
1351                 val |= (temp & 0x8000) << 10;
1352                 val |= (temp & 0x7fff) << 7;
1353         } else {
1354                 if (temp > 0x3fff)
1355                         temp = 0x3fff;
1356                 val &= ~0x003fff00;
1357                 val |= (temp & 0x3fff) << 8;
1358         }
1359         wrlp(mp, SDMA_CONFIG, val);
1360 }
1361 
1362 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1363 {
1364         u64 temp;
1365 
1366         temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1367         temp *= 64000000;
1368         do_div(temp, mp->t_clk);
1369 
1370         return (unsigned int)temp;
1371 }
1372 
1373 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1374 {
1375         u64 temp;
1376 
1377         temp = (u64)usec * mp->t_clk;
1378         temp += 31999999;
1379         do_div(temp, 64000000);
1380 
1381         if (temp > 0x3fff)
1382                 temp = 0x3fff;
1383 
1384         wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1385 }
1386 
1387 
1388 /* ethtool ******************************************************************/
1389 struct mv643xx_eth_stats {
1390         char stat_string[ETH_GSTRING_LEN];
1391         int sizeof_stat;
1392         int netdev_off;
1393         int mp_off;
1394 };
1395 
1396 #define SSTAT(m)                                                \
1397         { #m, FIELD_SIZEOF(struct net_device_stats, m),         \
1398           offsetof(struct net_device, stats.m), -1 }
1399 
1400 #define MIBSTAT(m)                                              \
1401         { #m, FIELD_SIZEOF(struct mib_counters, m),             \
1402           -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1403 
1404 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1405         SSTAT(rx_packets),
1406         SSTAT(tx_packets),
1407         SSTAT(rx_bytes),
1408         SSTAT(tx_bytes),
1409         SSTAT(rx_errors),
1410         SSTAT(tx_errors),
1411         SSTAT(rx_dropped),
1412         SSTAT(tx_dropped),
1413         MIBSTAT(good_octets_received),
1414         MIBSTAT(bad_octets_received),
1415         MIBSTAT(internal_mac_transmit_err),
1416         MIBSTAT(good_frames_received),
1417         MIBSTAT(bad_frames_received),
1418         MIBSTAT(broadcast_frames_received),
1419         MIBSTAT(multicast_frames_received),
1420         MIBSTAT(frames_64_octets),
1421         MIBSTAT(frames_65_to_127_octets),
1422         MIBSTAT(frames_128_to_255_octets),
1423         MIBSTAT(frames_256_to_511_octets),
1424         MIBSTAT(frames_512_to_1023_octets),
1425         MIBSTAT(frames_1024_to_max_octets),
1426         MIBSTAT(good_octets_sent),
1427         MIBSTAT(good_frames_sent),
1428         MIBSTAT(excessive_collision),
1429         MIBSTAT(multicast_frames_sent),
1430         MIBSTAT(broadcast_frames_sent),
1431         MIBSTAT(unrec_mac_control_received),
1432         MIBSTAT(fc_sent),
1433         MIBSTAT(good_fc_received),
1434         MIBSTAT(bad_fc_received),
1435         MIBSTAT(undersize_received),
1436         MIBSTAT(fragments_received),
1437         MIBSTAT(oversize_received),
1438         MIBSTAT(jabber_received),
1439         MIBSTAT(mac_receive_error),
1440         MIBSTAT(bad_crc_event),
1441         MIBSTAT(collision),
1442         MIBSTAT(late_collision),
1443         MIBSTAT(rx_discard),
1444         MIBSTAT(rx_overrun),
1445 };
1446 
1447 static int
1448 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1449                              struct ethtool_cmd *cmd)
1450 {
1451         int err;
1452 
1453         err = phy_read_status(mp->phy);
1454         if (err == 0)
1455                 err = phy_ethtool_gset(mp->phy, cmd);
1456 
1457         /*
1458          * The MAC does not support 1000baseT_Half.
1459          */
1460         cmd->supported &= ~SUPPORTED_1000baseT_Half;
1461         cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1462 
1463         return err;
1464 }
1465 
1466 static int
1467 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
1468                                  struct ethtool_cmd *cmd)
1469 {
1470         u32 port_status;
1471 
1472         port_status = rdlp(mp, PORT_STATUS);
1473 
1474         cmd->supported = SUPPORTED_MII;
1475         cmd->advertising = ADVERTISED_MII;
1476         switch (port_status & PORT_SPEED_MASK) {
1477         case PORT_SPEED_10:
1478                 ethtool_cmd_speed_set(cmd, SPEED_10);
1479                 break;
1480         case PORT_SPEED_100:
1481                 ethtool_cmd_speed_set(cmd, SPEED_100);
1482                 break;
1483         case PORT_SPEED_1000:
1484                 ethtool_cmd_speed_set(cmd, SPEED_1000);
1485                 break;
1486         default:
1487                 cmd->speed = -1;
1488                 break;
1489         }
1490         cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1491         cmd->port = PORT_MII;
1492         cmd->phy_address = 0;
1493         cmd->transceiver = XCVR_INTERNAL;
1494         cmd->autoneg = AUTONEG_DISABLE;
1495         cmd->maxtxpkt = 1;
1496         cmd->maxrxpkt = 1;
1497 
1498         return 0;
1499 }
1500 
1501 static void
1502 mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1503 {
1504         struct mv643xx_eth_private *mp = netdev_priv(dev);
1505         wol->supported = 0;
1506         wol->wolopts = 0;
1507         if (mp->phy)
1508                 phy_ethtool_get_wol(mp->phy, wol);
1509 }
1510 
1511 static int
1512 mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1513 {
1514         struct mv643xx_eth_private *mp = netdev_priv(dev);
1515         int err;
1516 
1517         if (mp->phy == NULL)
1518                 return -EOPNOTSUPP;
1519 
1520         err = phy_ethtool_set_wol(mp->phy, wol);
1521         /* Given that mv643xx_eth works without the marvell-specific PHY driver,
1522          * this debugging hint is useful to have.
1523          */
1524         if (err == -EOPNOTSUPP)
1525                 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n");
1526         return err;
1527 }
1528 
1529 static int
1530 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1531 {
1532         struct mv643xx_eth_private *mp = netdev_priv(dev);
1533 
1534         if (mp->phy != NULL)
1535                 return mv643xx_eth_get_settings_phy(mp, cmd);
1536         else
1537                 return mv643xx_eth_get_settings_phyless(mp, cmd);
1538 }
1539 
1540 static int
1541 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1542 {
1543         struct mv643xx_eth_private *mp = netdev_priv(dev);
1544         int ret;
1545 
1546         if (mp->phy == NULL)
1547                 return -EINVAL;
1548 
1549         /*
1550          * The MAC does not support 1000baseT_Half.
1551          */
1552         cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1553 
1554         ret = phy_ethtool_sset(mp->phy, cmd);
1555         if (!ret)
1556                 mv643xx_eth_adjust_link(dev);
1557         return ret;
1558 }
1559 
1560 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1561                                     struct ethtool_drvinfo *drvinfo)
1562 {
1563         strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1564                 sizeof(drvinfo->driver));
1565         strlcpy(drvinfo->version, mv643xx_eth_driver_version,
1566                 sizeof(drvinfo->version));
1567         strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1568         strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
1569         drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1570 }
1571 
1572 static int mv643xx_eth_nway_reset(struct net_device *dev)
1573 {
1574         struct mv643xx_eth_private *mp = netdev_priv(dev);
1575 
1576         if (mp->phy == NULL)
1577                 return -EINVAL;
1578 
1579         return genphy_restart_aneg(mp->phy);
1580 }
1581 
1582 static int
1583 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1584 {
1585         struct mv643xx_eth_private *mp = netdev_priv(dev);
1586 
1587         ec->rx_coalesce_usecs = get_rx_coal(mp);
1588         ec->tx_coalesce_usecs = get_tx_coal(mp);
1589 
1590         return 0;
1591 }
1592 
1593 static int
1594 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1595 {
1596         struct mv643xx_eth_private *mp = netdev_priv(dev);
1597 
1598         set_rx_coal(mp, ec->rx_coalesce_usecs);
1599         set_tx_coal(mp, ec->tx_coalesce_usecs);
1600 
1601         return 0;
1602 }
1603 
1604 static void
1605 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1606 {
1607         struct mv643xx_eth_private *mp = netdev_priv(dev);
1608 
1609         er->rx_max_pending = 4096;
1610         er->tx_max_pending = 4096;
1611 
1612         er->rx_pending = mp->rx_ring_size;
1613         er->tx_pending = mp->tx_ring_size;
1614 }
1615 
1616 static int
1617 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1618 {
1619         struct mv643xx_eth_private *mp = netdev_priv(dev);
1620 
1621         if (er->rx_mini_pending || er->rx_jumbo_pending)
1622                 return -EINVAL;
1623 
1624         mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1625         mp->tx_ring_size = clamp_t(unsigned int, er->tx_pending,
1626                                    MV643XX_MAX_SKB_DESCS * 2, 4096);
1627         if (mp->tx_ring_size != er->tx_pending)
1628                 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
1629                             mp->tx_ring_size, er->tx_pending);
1630 
1631         if (netif_running(dev)) {
1632                 mv643xx_eth_stop(dev);
1633                 if (mv643xx_eth_open(dev)) {
1634                         netdev_err(dev,
1635                                    "fatal error on re-opening device after ring param change\n");
1636                         return -ENOMEM;
1637                 }
1638         }
1639 
1640         return 0;
1641 }
1642 
1643 
1644 static int
1645 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
1646 {
1647         struct mv643xx_eth_private *mp = netdev_priv(dev);
1648         bool rx_csum = features & NETIF_F_RXCSUM;
1649 
1650         wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1651 
1652         return 0;
1653 }
1654 
1655 static void mv643xx_eth_get_strings(struct net_device *dev,
1656                                     uint32_t stringset, uint8_t *data)
1657 {
1658         int i;
1659 
1660         if (stringset == ETH_SS_STATS) {
1661                 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1662                         memcpy(data + i * ETH_GSTRING_LEN,
1663                                 mv643xx_eth_stats[i].stat_string,
1664                                 ETH_GSTRING_LEN);
1665                 }
1666         }
1667 }
1668 
1669 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1670                                           struct ethtool_stats *stats,
1671                                           uint64_t *data)
1672 {
1673         struct mv643xx_eth_private *mp = netdev_priv(dev);
1674         int i;
1675 
1676         mv643xx_eth_get_stats(dev);
1677         mib_counters_update(mp);
1678 
1679         for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1680                 const struct mv643xx_eth_stats *stat;
1681                 void *p;
1682 
1683                 stat = mv643xx_eth_stats + i;
1684 
1685                 if (stat->netdev_off >= 0)
1686                         p = ((void *)mp->dev) + stat->netdev_off;
1687                 else
1688                         p = ((void *)mp) + stat->mp_off;
1689 
1690                 data[i] = (stat->sizeof_stat == 8) ?
1691                                 *(uint64_t *)p : *(uint32_t *)p;
1692         }
1693 }
1694 
1695 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1696 {
1697         if (sset == ETH_SS_STATS)
1698                 return ARRAY_SIZE(mv643xx_eth_stats);
1699 
1700         return -EOPNOTSUPP;
1701 }
1702 
1703 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1704         .get_settings           = mv643xx_eth_get_settings,
1705         .set_settings           = mv643xx_eth_set_settings,
1706         .get_drvinfo            = mv643xx_eth_get_drvinfo,
1707         .nway_reset             = mv643xx_eth_nway_reset,
1708         .get_link               = ethtool_op_get_link,
1709         .get_coalesce           = mv643xx_eth_get_coalesce,
1710         .set_coalesce           = mv643xx_eth_set_coalesce,
1711         .get_ringparam          = mv643xx_eth_get_ringparam,
1712         .set_ringparam          = mv643xx_eth_set_ringparam,
1713         .get_strings            = mv643xx_eth_get_strings,
1714         .get_ethtool_stats      = mv643xx_eth_get_ethtool_stats,
1715         .get_sset_count         = mv643xx_eth_get_sset_count,
1716         .get_ts_info            = ethtool_op_get_ts_info,
1717         .get_wol                = mv643xx_eth_get_wol,
1718         .set_wol                = mv643xx_eth_set_wol,
1719 };
1720 
1721 
1722 /* address handling *********************************************************/
1723 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1724 {
1725         unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1726         unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1727 
1728         addr[0] = (mac_h >> 24) & 0xff;
1729         addr[1] = (mac_h >> 16) & 0xff;
1730         addr[2] = (mac_h >> 8) & 0xff;
1731         addr[3] = mac_h & 0xff;
1732         addr[4] = (mac_l >> 8) & 0xff;
1733         addr[5] = mac_l & 0xff;
1734 }
1735 
1736 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1737 {
1738         wrlp(mp, MAC_ADDR_HIGH,
1739                 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1740         wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1741 }
1742 
1743 static u32 uc_addr_filter_mask(struct net_device *dev)
1744 {
1745         struct netdev_hw_addr *ha;
1746         u32 nibbles;
1747 
1748         if (dev->flags & IFF_PROMISC)
1749                 return 0;
1750 
1751         nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1752         netdev_for_each_uc_addr(ha, dev) {
1753                 if (memcmp(dev->dev_addr, ha->addr, 5))
1754                         return 0;
1755                 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
1756                         return 0;
1757 
1758                 nibbles |= 1 << (ha->addr[5] & 0x0f);
1759         }
1760 
1761         return nibbles;
1762 }
1763 
1764 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1765 {
1766         struct mv643xx_eth_private *mp = netdev_priv(dev);
1767         u32 port_config;
1768         u32 nibbles;
1769         int i;
1770 
1771         uc_addr_set(mp, dev->dev_addr);
1772 
1773         port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1774 
1775         nibbles = uc_addr_filter_mask(dev);
1776         if (!nibbles) {
1777                 port_config |= UNICAST_PROMISCUOUS_MODE;
1778                 nibbles = 0xffff;
1779         }
1780 
1781         for (i = 0; i < 16; i += 4) {
1782                 int off = UNICAST_TABLE(mp->port_num) + i;
1783                 u32 v;
1784 
1785                 v = 0;
1786                 if (nibbles & 1)
1787                         v |= 0x00000001;
1788                 if (nibbles & 2)
1789                         v |= 0x00000100;
1790                 if (nibbles & 4)
1791                         v |= 0x00010000;
1792                 if (nibbles & 8)
1793                         v |= 0x01000000;
1794                 nibbles >>= 4;
1795 
1796                 wrl(mp, off, v);
1797         }
1798 
1799         wrlp(mp, PORT_CONFIG, port_config);
1800 }
1801 
1802 static int addr_crc(unsigned char *addr)
1803 {
1804         int crc = 0;
1805         int i;
1806 
1807         for (i = 0; i < 6; i++) {
1808                 int j;
1809 
1810                 crc = (crc ^ addr[i]) << 8;
1811                 for (j = 7; j >= 0; j--) {
1812                         if (crc & (0x100 << j))
1813                                 crc ^= 0x107 << j;
1814                 }
1815         }
1816 
1817         return crc;
1818 }
1819 
1820 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1821 {
1822         struct mv643xx_eth_private *mp = netdev_priv(dev);
1823         u32 *mc_spec;
1824         u32 *mc_other;
1825         struct netdev_hw_addr *ha;
1826         int i;
1827 
1828         if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1829                 int port_num;
1830                 u32 accept;
1831 
1832 oom:
1833                 port_num = mp->port_num;
1834                 accept = 0x01010101;
1835                 for (i = 0; i < 0x100; i += 4) {
1836                         wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1837                         wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1838                 }
1839                 return;
1840         }
1841 
1842         mc_spec = kmalloc(0x200, GFP_ATOMIC);
1843         if (mc_spec == NULL)
1844                 goto oom;
1845         mc_other = mc_spec + (0x100 >> 2);
1846 
1847         memset(mc_spec, 0, 0x100);
1848         memset(mc_other, 0, 0x100);
1849 
1850         netdev_for_each_mc_addr(ha, dev) {
1851                 u8 *a = ha->addr;
1852                 u32 *table;
1853                 int entry;
1854 
1855                 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1856                         table = mc_spec;
1857                         entry = a[5];
1858                 } else {
1859                         table = mc_other;
1860                         entry = addr_crc(a);
1861                 }
1862 
1863                 table[entry >> 2] |= 1 << (8 * (entry & 3));
1864         }
1865 
1866         for (i = 0; i < 0x100; i += 4) {
1867                 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1868                 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1869         }
1870 
1871         kfree(mc_spec);
1872 }
1873 
1874 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1875 {
1876         mv643xx_eth_program_unicast_filter(dev);
1877         mv643xx_eth_program_multicast_filter(dev);
1878 }
1879 
1880 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1881 {
1882         struct sockaddr *sa = addr;
1883 
1884         if (!is_valid_ether_addr(sa->sa_data))
1885                 return -EADDRNOTAVAIL;
1886 
1887         memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1888 
1889         netif_addr_lock_bh(dev);
1890         mv643xx_eth_program_unicast_filter(dev);
1891         netif_addr_unlock_bh(dev);
1892 
1893         return 0;
1894 }
1895 
1896 
1897 /* rx/tx queue initialisation ***********************************************/
1898 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1899 {
1900         struct rx_queue *rxq = mp->rxq + index;
1901         struct rx_desc *rx_desc;
1902         int size;
1903         int i;
1904 
1905         rxq->index = index;
1906 
1907         rxq->rx_ring_size = mp->rx_ring_size;
1908 
1909         rxq->rx_desc_count = 0;
1910         rxq->rx_curr_desc = 0;
1911         rxq->rx_used_desc = 0;
1912 
1913         size = rxq->rx_ring_size * sizeof(struct rx_desc);
1914 
1915         if (index == 0 && size <= mp->rx_desc_sram_size) {
1916                 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1917                                                 mp->rx_desc_sram_size);
1918                 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1919         } else {
1920                 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1921                                                        size, &rxq->rx_desc_dma,
1922                                                        GFP_KERNEL);
1923         }
1924 
1925         if (rxq->rx_desc_area == NULL) {
1926                 netdev_err(mp->dev,
1927                            "can't allocate rx ring (%d bytes)\n", size);
1928                 goto out;
1929         }
1930         memset(rxq->rx_desc_area, 0, size);
1931 
1932         rxq->rx_desc_area_size = size;
1933         rxq->rx_skb = kcalloc(rxq->rx_ring_size, sizeof(*rxq->rx_skb),
1934                                     GFP_KERNEL);
1935         if (rxq->rx_skb == NULL)
1936                 goto out_free;
1937 
1938         rx_desc = rxq->rx_desc_area;
1939         for (i = 0; i < rxq->rx_ring_size; i++) {
1940                 int nexti;
1941 
1942                 nexti = i + 1;
1943                 if (nexti == rxq->rx_ring_size)
1944                         nexti = 0;
1945 
1946                 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1947                                         nexti * sizeof(struct rx_desc);
1948         }
1949 
1950         return 0;
1951 
1952 
1953 out_free:
1954         if (index == 0 && size <= mp->rx_desc_sram_size)
1955                 iounmap(rxq->rx_desc_area);
1956         else
1957                 dma_free_coherent(mp->dev->dev.parent, size,
1958                                   rxq->rx_desc_area,
1959                                   rxq->rx_desc_dma);
1960 
1961 out:
1962         return -ENOMEM;
1963 }
1964 
1965 static void rxq_deinit(struct rx_queue *rxq)
1966 {
1967         struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1968         int i;
1969 
1970         rxq_disable(rxq);
1971 
1972         for (i = 0; i < rxq->rx_ring_size; i++) {
1973                 if (rxq->rx_skb[i]) {
1974                         dev_kfree_skb(rxq->rx_skb[i]);
1975                         rxq->rx_desc_count--;
1976                 }
1977         }
1978 
1979         if (rxq->rx_desc_count) {
1980                 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
1981                            rxq->rx_desc_count);
1982         }
1983 
1984         if (rxq->index == 0 &&
1985             rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1986                 iounmap(rxq->rx_desc_area);
1987         else
1988                 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
1989                                   rxq->rx_desc_area, rxq->rx_desc_dma);
1990 
1991         kfree(rxq->rx_skb);
1992 }
1993 
1994 static int txq_init(struct mv643xx_eth_private *mp, int index)
1995 {
1996         struct tx_queue *txq = mp->txq + index;
1997         struct tx_desc *tx_desc;
1998         int size;
1999         int i;
2000 
2001         txq->index = index;
2002 
2003         txq->tx_ring_size = mp->tx_ring_size;
2004 
2005         /* A queue must always have room for at least one skb.
2006          * Therefore, stop the queue when the free entries reaches
2007          * the maximum number of descriptors per skb.
2008          */
2009         txq->tx_stop_threshold = txq->tx_ring_size - MV643XX_MAX_SKB_DESCS;
2010         txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
2011 
2012         txq->tx_desc_count = 0;
2013         txq->tx_curr_desc = 0;
2014         txq->tx_used_desc = 0;
2015 
2016         size = txq->tx_ring_size * sizeof(struct tx_desc);
2017 
2018         if (index == 0 && size <= mp->tx_desc_sram_size) {
2019                 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
2020                                                 mp->tx_desc_sram_size);
2021                 txq->tx_desc_dma = mp->tx_desc_sram_addr;
2022         } else {
2023                 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
2024                                                        size, &txq->tx_desc_dma,
2025                                                        GFP_KERNEL);
2026         }
2027 
2028         if (txq->tx_desc_area == NULL) {
2029                 netdev_err(mp->dev,
2030                            "can't allocate tx ring (%d bytes)\n", size);
2031                 return -ENOMEM;
2032         }
2033         memset(txq->tx_desc_area, 0, size);
2034 
2035         txq->tx_desc_area_size = size;
2036 
2037         tx_desc = txq->tx_desc_area;
2038         for (i = 0; i < txq->tx_ring_size; i++) {
2039                 struct tx_desc *txd = tx_desc + i;
2040                 int nexti;
2041 
2042                 nexti = i + 1;
2043                 if (nexti == txq->tx_ring_size)
2044                         nexti = 0;
2045 
2046                 txd->cmd_sts = 0;
2047                 txd->next_desc_ptr = txq->tx_desc_dma +
2048                                         nexti * sizeof(struct tx_desc);
2049         }
2050 
2051         /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2052         txq->tso_hdrs = dma_alloc_coherent(mp->dev->dev.parent,
2053                                            txq->tx_ring_size * TSO_HEADER_SIZE,
2054                                            &txq->tso_hdrs_dma, GFP_KERNEL);
2055         if (txq->tso_hdrs == NULL) {
2056                 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2057                                   txq->tx_desc_area, txq->tx_desc_dma);
2058                 return -ENOMEM;
2059         }
2060         skb_queue_head_init(&txq->tx_skb);
2061 
2062         return 0;
2063 }
2064 
2065 static void txq_deinit(struct tx_queue *txq)
2066 {
2067         struct mv643xx_eth_private *mp = txq_to_mp(txq);
2068 
2069         txq_disable(txq);
2070         txq_reclaim(txq, txq->tx_ring_size, 1);
2071 
2072         BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
2073 
2074         if (txq->index == 0 &&
2075             txq->tx_desc_area_size <= mp->tx_desc_sram_size)
2076                 iounmap(txq->tx_desc_area);
2077         else
2078                 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2079                                   txq->tx_desc_area, txq->tx_desc_dma);
2080         if (txq->tso_hdrs)
2081                 dma_free_coherent(mp->dev->dev.parent,
2082                                   txq->tx_ring_size * TSO_HEADER_SIZE,
2083                                   txq->tso_hdrs, txq->tso_hdrs_dma);
2084 }
2085 
2086 
2087 /* netdev ops and related ***************************************************/
2088 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2089 {
2090         u32 int_cause;
2091         u32 int_cause_ext;
2092 
2093         int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
2094         if (int_cause == 0)
2095                 return 0;
2096 
2097         int_cause_ext = 0;
2098         if (int_cause & INT_EXT) {
2099                 int_cause &= ~INT_EXT;
2100                 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
2101         }
2102 
2103         if (int_cause) {
2104                 wrlp(mp, INT_CAUSE, ~int_cause);
2105                 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
2106                                 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
2107                 mp->work_rx |= (int_cause & INT_RX) >> 2;
2108         }
2109 
2110         int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2111         if (int_cause_ext) {
2112                 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
2113                 if (int_cause_ext & INT_EXT_LINK_PHY)
2114                         mp->work_link = 1;
2115                 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2116         }
2117 
2118         return 1;
2119 }
2120 
2121 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2122 {
2123         struct net_device *dev = (struct net_device *)dev_id;
2124         struct mv643xx_eth_private *mp = netdev_priv(dev);
2125 
2126         if (unlikely(!mv643xx_eth_collect_events(mp)))
2127                 return IRQ_NONE;
2128 
2129         wrlp(mp, INT_MASK, 0);
2130         napi_schedule(&mp->napi);
2131 
2132         return IRQ_HANDLED;
2133 }
2134 
2135 static void handle_link_event(struct mv643xx_eth_private *mp)
2136 {
2137         struct net_device *dev = mp->dev;
2138         u32 port_status;
2139         int speed;
2140         int duplex;
2141         int fc;
2142 
2143         port_status = rdlp(mp, PORT_STATUS);
2144         if (!(port_status & LINK_UP)) {
2145                 if (netif_carrier_ok(dev)) {
2146                         int i;
2147 
2148                         netdev_info(dev, "link down\n");
2149 
2150                         netif_carrier_off(dev);
2151 
2152                         for (i = 0; i < mp->txq_count; i++) {
2153                                 struct tx_queue *txq = mp->txq + i;
2154 
2155                                 txq_reclaim(txq, txq->tx_ring_size, 1);
2156                                 txq_reset_hw_ptr(txq);
2157                         }
2158                 }
2159                 return;
2160         }
2161 
2162         switch (port_status & PORT_SPEED_MASK) {
2163         case PORT_SPEED_10:
2164                 speed = 10;
2165                 break;
2166         case PORT_SPEED_100:
2167                 speed = 100;
2168                 break;
2169         case PORT_SPEED_1000:
2170                 speed = 1000;
2171                 break;
2172         default:
2173                 speed = -1;
2174                 break;
2175         }
2176         duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2177         fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2178 
2179         netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
2180                     speed, duplex ? "full" : "half", fc ? "en" : "dis");
2181 
2182         if (!netif_carrier_ok(dev))
2183                 netif_carrier_on(dev);
2184 }
2185 
2186 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
2187 {
2188         struct mv643xx_eth_private *mp;
2189         int work_done;
2190 
2191         mp = container_of(napi, struct mv643xx_eth_private, napi);
2192 
2193         if (unlikely(mp->oom)) {
2194                 mp->oom = 0;
2195                 del_timer(&mp->rx_oom);
2196         }
2197 
2198         work_done = 0;
2199         while (work_done < budget) {
2200                 u8 queue_mask;
2201                 int queue;
2202                 int work_tbd;
2203 
2204                 if (mp->work_link) {
2205                         mp->work_link = 0;
2206                         handle_link_event(mp);
2207                         work_done++;
2208                         continue;
2209                 }
2210 
2211                 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2212                 if (likely(!mp->oom))
2213                         queue_mask |= mp->work_rx_refill;
2214 
2215                 if (!queue_mask) {
2216                         if (mv643xx_eth_collect_events(mp))
2217                                 continue;
2218                         break;
2219                 }
2220 
2221                 queue = fls(queue_mask) - 1;
2222                 queue_mask = 1 << queue;
2223 
2224                 work_tbd = budget - work_done;
2225                 if (work_tbd > 16)
2226                         work_tbd = 16;
2227 
2228                 if (mp->work_tx_end & queue_mask) {
2229                         txq_kick(mp->txq + queue);
2230                 } else if (mp->work_tx & queue_mask) {
2231                         work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2232                         txq_maybe_wake(mp->txq + queue);
2233                 } else if (mp->work_rx & queue_mask) {
2234                         work_done += rxq_process(mp->rxq + queue, work_tbd);
2235                 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
2236                         work_done += rxq_refill(mp->rxq + queue, work_tbd);
2237                 } else {
2238                         BUG();
2239                 }
2240         }
2241 
2242         if (work_done < budget) {
2243                 if (mp->oom)
2244                         mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2245                 napi_complete(napi);
2246                 wrlp(mp, INT_MASK, mp->int_mask);
2247         }
2248 
2249         return work_done;
2250 }
2251 
2252 static inline void oom_timer_wrapper(unsigned long data)
2253 {
2254         struct mv643xx_eth_private *mp = (void *)data;
2255 
2256         napi_schedule(&mp->napi);
2257 }
2258 
2259 static void port_start(struct mv643xx_eth_private *mp)
2260 {
2261         u32 pscr;
2262         int i;
2263 
2264         /*
2265          * Perform PHY reset, if there is a PHY.
2266          */
2267         if (mp->phy != NULL) {
2268                 struct ethtool_cmd cmd;
2269 
2270                 mv643xx_eth_get_settings(mp->dev, &cmd);
2271                 phy_init_hw(mp->phy);
2272                 mv643xx_eth_set_settings(mp->dev, &cmd);
2273                 phy_start(mp->phy);
2274         }
2275 
2276         /*
2277          * Configure basic link parameters.
2278          */
2279         pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2280 
2281         pscr |= SERIAL_PORT_ENABLE;
2282         wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2283 
2284         pscr |= DO_NOT_FORCE_LINK_FAIL;
2285         if (mp->phy == NULL)
2286                 pscr |= FORCE_LINK_PASS;
2287         wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2288 
2289         /*
2290          * Configure TX path and queues.
2291          */
2292         tx_set_rate(mp, 1000000000, 16777216);
2293         for (i = 0; i < mp->txq_count; i++) {
2294                 struct tx_queue *txq = mp->txq + i;
2295 
2296                 txq_reset_hw_ptr(txq);
2297                 txq_set_rate(txq, 1000000000, 16777216);
2298                 txq_set_fixed_prio_mode(txq);
2299         }
2300 
2301         /*
2302          * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2303          * frames to RX queue #0, and include the pseudo-header when
2304          * calculating receive checksums.
2305          */
2306         mv643xx_eth_set_features(mp->dev, mp->dev->features);
2307 
2308         /*
2309          * Treat BPDUs as normal multicasts, and disable partition mode.
2310          */
2311         wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2312 
2313         /*
2314          * Add configured unicast addresses to address filter table.
2315          */
2316         mv643xx_eth_program_unicast_filter(mp->dev);
2317 
2318         /*
2319          * Enable the receive queues.
2320          */
2321         for (i = 0; i < mp->rxq_count; i++) {
2322                 struct rx_queue *rxq = mp->rxq + i;
2323                 u32 addr;
2324 
2325                 addr = (u32)rxq->rx_desc_dma;
2326                 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2327                 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2328 
2329                 rxq_enable(rxq);
2330         }
2331 }
2332 
2333 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2334 {
2335         int skb_size;
2336 
2337         /*
2338          * Reserve 2+14 bytes for an ethernet header (the hardware
2339          * automatically prepends 2 bytes of dummy data to each
2340          * received packet), 16 bytes for up to four VLAN tags, and
2341          * 4 bytes for the trailing FCS -- 36 bytes total.
2342          */
2343         skb_size = mp->dev->mtu + 36;
2344 
2345         /*
2346          * Make sure that the skb size is a multiple of 8 bytes, as
2347          * the lower three bits of the receive descriptor's buffer
2348          * size field are ignored by the hardware.
2349          */
2350         mp->skb_size = (skb_size + 7) & ~7;
2351 
2352         /*
2353          * If NET_SKB_PAD is smaller than a cache line,
2354          * netdev_alloc_skb() will cause skb->data to be misaligned
2355          * to a cache line boundary.  If this is the case, include
2356          * some extra space to allow re-aligning the data area.
2357          */
2358         mp->skb_size += SKB_DMA_REALIGN;
2359 }
2360 
2361 static int mv643xx_eth_open(struct net_device *dev)
2362 {
2363         struct mv643xx_eth_private *mp = netdev_priv(dev);
2364         int err;
2365         int i;
2366 
2367         wrlp(mp, INT_CAUSE, 0);
2368         wrlp(mp, INT_CAUSE_EXT, 0);
2369         rdlp(mp, INT_CAUSE_EXT);
2370 
2371         err = request_irq(dev->irq, mv643xx_eth_irq,
2372                           IRQF_SHARED, dev->name, dev);
2373         if (err) {
2374                 netdev_err(dev, "can't assign irq\n");
2375                 return -EAGAIN;
2376         }
2377 
2378         mv643xx_eth_recalc_skb_size(mp);
2379 
2380         napi_enable(&mp->napi);
2381 
2382         mp->int_mask = INT_EXT;
2383 
2384         for (i = 0; i < mp->rxq_count; i++) {
2385                 err = rxq_init(mp, i);
2386                 if (err) {
2387                         while (--i >= 0)
2388                                 rxq_deinit(mp->rxq + i);
2389                         goto out;
2390                 }
2391 
2392                 rxq_refill(mp->rxq + i, INT_MAX);
2393                 mp->int_mask |= INT_RX_0 << i;
2394         }
2395 
2396         if (mp->oom) {
2397                 mp->rx_oom.expires = jiffies + (HZ / 10);
2398                 add_timer(&mp->rx_oom);
2399         }
2400 
2401         for (i = 0; i < mp->txq_count; i++) {
2402                 err = txq_init(mp, i);
2403                 if (err) {
2404                         while (--i >= 0)
2405                                 txq_deinit(mp->txq + i);
2406                         goto out_free;
2407                 }
2408                 mp->int_mask |= INT_TX_END_0 << i;
2409         }
2410 
2411         add_timer(&mp->mib_counters_timer);
2412         port_start(mp);
2413 
2414         wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2415         wrlp(mp, INT_MASK, mp->int_mask);
2416 
2417         return 0;
2418 
2419 
2420 out_free:
2421         for (i = 0; i < mp->rxq_count; i++)
2422                 rxq_deinit(mp->rxq + i);
2423 out:
2424         free_irq(dev->irq, dev);
2425 
2426         return err;
2427 }
2428 
2429 static void port_reset(struct mv643xx_eth_private *mp)
2430 {
2431         unsigned int data;
2432         int i;
2433 
2434         for (i = 0; i < mp->rxq_count; i++)
2435                 rxq_disable(mp->rxq + i);
2436         for (i = 0; i < mp->txq_count; i++)
2437                 txq_disable(mp->txq + i);
2438 
2439         while (1) {
2440                 u32 ps = rdlp(mp, PORT_STATUS);
2441 
2442                 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2443                         break;
2444                 udelay(10);
2445         }
2446 
2447         /* Reset the Enable bit in the Configuration Register */
2448         data = rdlp(mp, PORT_SERIAL_CONTROL);
2449         data &= ~(SERIAL_PORT_ENABLE            |
2450                   DO_NOT_FORCE_LINK_FAIL        |
2451                   FORCE_LINK_PASS);
2452         wrlp(mp, PORT_SERIAL_CONTROL, data);
2453 }
2454 
2455 static int mv643xx_eth_stop(struct net_device *dev)
2456 {
2457         struct mv643xx_eth_private *mp = netdev_priv(dev);
2458         int i;
2459 
2460         wrlp(mp, INT_MASK_EXT, 0x00000000);
2461         wrlp(mp, INT_MASK, 0x00000000);
2462         rdlp(mp, INT_MASK);
2463 
2464         napi_disable(&mp->napi);
2465 
2466         del_timer_sync(&mp->rx_oom);
2467 
2468         netif_carrier_off(dev);
2469         if (mp->phy)
2470                 phy_stop(mp->phy);
2471         free_irq(dev->irq, dev);
2472 
2473         port_reset(mp);
2474         mv643xx_eth_get_stats(dev);
2475         mib_counters_update(mp);
2476         del_timer_sync(&mp->mib_counters_timer);
2477 
2478         for (i = 0; i < mp->rxq_count; i++)
2479                 rxq_deinit(mp->rxq + i);
2480         for (i = 0; i < mp->txq_count; i++)
2481                 txq_deinit(mp->txq + i);
2482 
2483         return 0;
2484 }
2485 
2486 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2487 {
2488         struct mv643xx_eth_private *mp = netdev_priv(dev);
2489         int ret;
2490 
2491         if (mp->phy == NULL)
2492                 return -ENOTSUPP;
2493 
2494         ret = phy_mii_ioctl(mp->phy, ifr, cmd);
2495         if (!ret)
2496                 mv643xx_eth_adjust_link(dev);
2497         return ret;
2498 }
2499 
2500 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2501 {
2502         struct mv643xx_eth_private *mp = netdev_priv(dev);
2503 
2504         if (new_mtu < 64 || new_mtu > 9500)
2505                 return -EINVAL;
2506 
2507         dev->mtu = new_mtu;
2508         mv643xx_eth_recalc_skb_size(mp);
2509         tx_set_rate(mp, 1000000000, 16777216);
2510 
2511         if (!netif_running(dev))
2512                 return 0;
2513 
2514         /*
2515          * Stop and then re-open the interface. This will allocate RX
2516          * skbs of the new MTU.
2517          * There is a possible danger that the open will not succeed,
2518          * due to memory being full.
2519          */
2520         mv643xx_eth_stop(dev);
2521         if (mv643xx_eth_open(dev)) {
2522                 netdev_err(dev,
2523                            "fatal error on re-opening device after MTU change\n");
2524         }
2525 
2526         return 0;
2527 }
2528 
2529 static void tx_timeout_task(struct work_struct *ugly)
2530 {
2531         struct mv643xx_eth_private *mp;
2532 
2533         mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2534         if (netif_running(mp->dev)) {
2535                 netif_tx_stop_all_queues(mp->dev);
2536                 port_reset(mp);
2537                 port_start(mp);
2538                 netif_tx_wake_all_queues(mp->dev);
2539         }
2540 }
2541 
2542 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2543 {
2544         struct mv643xx_eth_private *mp = netdev_priv(dev);
2545 
2546         netdev_info(dev, "tx timeout\n");
2547 
2548         schedule_work(&mp->tx_timeout_task);
2549 }
2550 
2551 #ifdef CONFIG_NET_POLL_CONTROLLER
2552 static void mv643xx_eth_netpoll(struct net_device *dev)
2553 {
2554         struct mv643xx_eth_private *mp = netdev_priv(dev);
2555 
2556         wrlp(mp, INT_MASK, 0x00000000);
2557         rdlp(mp, INT_MASK);
2558 
2559         mv643xx_eth_irq(dev->irq, dev);
2560 
2561         wrlp(mp, INT_MASK, mp->int_mask);
2562 }
2563 #endif
2564 
2565 
2566 /* platform glue ************************************************************/
2567 static void
2568 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2569                               const struct mbus_dram_target_info *dram)
2570 {
2571         void __iomem *base = msp->base;
2572         u32 win_enable;
2573         u32 win_protect;
2574         int i;
2575 
2576         for (i = 0; i < 6; i++) {
2577                 writel(0, base + WINDOW_BASE(i));
2578                 writel(0, base + WINDOW_SIZE(i));
2579                 if (i < 4)
2580                         writel(0, base + WINDOW_REMAP_HIGH(i));
2581         }
2582 
2583         win_enable = 0x3f;
2584         win_protect = 0;
2585 
2586         for (i = 0; i < dram->num_cs; i++) {
2587                 const struct mbus_dram_window *cs = dram->cs + i;
2588 
2589                 writel((cs->base & 0xffff0000) |
2590                         (cs->mbus_attr << 8) |
2591                         dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2592                 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2593 
2594                 win_enable &= ~(1 << i);
2595                 win_protect |= 3 << (2 * i);
2596         }
2597 
2598         writel(win_enable, base + WINDOW_BAR_ENABLE);
2599         msp->win_protect = win_protect;
2600 }
2601 
2602 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2603 {
2604         /*
2605          * Check whether we have a 14-bit coal limit field in bits
2606          * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2607          * SDMA config register.
2608          */
2609         writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2610         if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2611                 msp->extended_rx_coal_limit = 1;
2612         else
2613                 msp->extended_rx_coal_limit = 0;
2614 
2615         /*
2616          * Check whether the MAC supports TX rate control, and if
2617          * yes, whether its associated registers are in the old or
2618          * the new place.
2619          */
2620         writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2621         if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2622                 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2623         } else {
2624                 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2625                 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2626                         msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2627                 else
2628                         msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2629         }
2630 }
2631 
2632 #if defined(CONFIG_OF)
2633 static const struct of_device_id mv643xx_eth_shared_ids[] = {
2634         { .compatible = "marvell,orion-eth", },
2635         { .compatible = "marvell,kirkwood-eth", },
2636         { }
2637 };
2638 MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids);
2639 #endif
2640 
2641 #if defined(CONFIG_OF) && !defined(CONFIG_MV64X60)
2642 #define mv643xx_eth_property(_np, _name, _v)                            \
2643         do {                                                            \
2644                 u32 tmp;                                                \
2645                 if (!of_property_read_u32(_np, "marvell," _name, &tmp)) \
2646                         _v = tmp;                                       \
2647         } while (0)
2648 
2649 static struct platform_device *port_platdev[3];
2650 
2651 static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev,
2652                                           struct device_node *pnp)
2653 {
2654         struct platform_device *ppdev;
2655         struct mv643xx_eth_platform_data ppd;
2656         struct resource res;
2657         const char *mac_addr;
2658         int ret;
2659         int dev_num = 0;
2660 
2661         memset(&ppd, 0, sizeof(ppd));
2662         ppd.shared = pdev;
2663 
2664         memset(&res, 0, sizeof(res));
2665         if (!of_irq_to_resource(pnp, 0, &res)) {
2666                 dev_err(&pdev->dev, "missing interrupt on %s\n", pnp->name);
2667                 return -EINVAL;
2668         }
2669 
2670         if (of_property_read_u32(pnp, "reg", &ppd.port_number)) {
2671                 dev_err(&pdev->dev, "missing reg property on %s\n", pnp->name);
2672                 return -EINVAL;
2673         }
2674 
2675         if (ppd.port_number >= 3) {
2676                 dev_err(&pdev->dev, "invalid reg property on %s\n", pnp->name);
2677                 return -EINVAL;
2678         }
2679 
2680         while (dev_num < 3 && port_platdev[dev_num])
2681                 dev_num++;
2682 
2683         if (dev_num == 3) {
2684                 dev_err(&pdev->dev, "too many ports registered\n");
2685                 return -EINVAL;
2686         }
2687 
2688         mac_addr = of_get_mac_address(pnp);
2689         if (mac_addr)
2690                 memcpy(ppd.mac_addr, mac_addr, ETH_ALEN);
2691 
2692         mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size);
2693         mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr);
2694         mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size);
2695         mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size);
2696         mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr);
2697         mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size);
2698 
2699         ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0);
2700         if (!ppd.phy_node) {
2701                 ppd.phy_addr = MV643XX_ETH_PHY_NONE;
2702                 of_property_read_u32(pnp, "speed", &ppd.speed);
2703                 of_property_read_u32(pnp, "duplex", &ppd.duplex);
2704         }
2705 
2706         ppdev = platform_device_alloc(MV643XX_ETH_NAME, dev_num);
2707         if (!ppdev)
2708                 return -ENOMEM;
2709         ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
2710         ppdev->dev.of_node = pnp;
2711 
2712         ret = platform_device_add_resources(ppdev, &res, 1);
2713         if (ret)
2714                 goto port_err;
2715 
2716         ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
2717         if (ret)
2718                 goto port_err;
2719 
2720         ret = platform_device_add(ppdev);
2721         if (ret)
2722                 goto port_err;
2723 
2724         port_platdev[dev_num] = ppdev;
2725 
2726         return 0;
2727 
2728 port_err:
2729         platform_device_put(ppdev);
2730         return ret;
2731 }
2732 
2733 static int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2734 {
2735         struct mv643xx_eth_shared_platform_data *pd;
2736         struct device_node *pnp, *np = pdev->dev.of_node;
2737         int ret;
2738 
2739         /* bail out if not registered from DT */
2740         if (!np)
2741                 return 0;
2742 
2743         pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
2744         if (!pd)
2745                 return -ENOMEM;
2746         pdev->dev.platform_data = pd;
2747 
2748         mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit);
2749 
2750         for_each_available_child_of_node(np, pnp) {
2751                 ret = mv643xx_eth_shared_of_add_port(pdev, pnp);
2752                 if (ret)
2753                         return ret;
2754         }
2755         return 0;
2756 }
2757 
2758 static void mv643xx_eth_shared_of_remove(void)
2759 {
2760         int n;
2761 
2762         for (n = 0; n < 3; n++) {
2763                 platform_device_del(port_platdev[n]);
2764                 port_platdev[n] = NULL;
2765         }
2766 }
2767 #else
2768 static inline int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2769 {
2770         return 0;
2771 }
2772 
2773 static inline void mv643xx_eth_shared_of_remove(void)
2774 {
2775 }
2776 #endif
2777 
2778 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2779 {
2780         static int mv643xx_eth_version_printed;
2781         struct mv643xx_eth_shared_platform_data *pd;
2782         struct mv643xx_eth_shared_private *msp;
2783         const struct mbus_dram_target_info *dram;
2784         struct resource *res;
2785         int ret;
2786 
2787         if (!mv643xx_eth_version_printed++)
2788                 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2789                           mv643xx_eth_driver_version);
2790 
2791         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2792         if (res == NULL)
2793                 return -EINVAL;
2794 
2795         msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
2796         if (msp == NULL)
2797                 return -ENOMEM;
2798         platform_set_drvdata(pdev, msp);
2799 
2800         msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
2801         if (msp->base == NULL)
2802                 return -ENOMEM;
2803 
2804         msp->clk = devm_clk_get(&pdev->dev, NULL);
2805         if (!IS_ERR(msp->clk))
2806                 clk_prepare_enable(msp->clk);
2807 
2808         /*
2809          * (Re-)program MBUS remapping windows if we are asked to.
2810          */
2811         dram = mv_mbus_dram_info();
2812         if (dram)
2813                 mv643xx_eth_conf_mbus_windows(msp, dram);
2814 
2815         ret = mv643xx_eth_shared_of_probe(pdev);
2816         if (ret)
2817                 return ret;
2818         pd = dev_get_platdata(&pdev->dev);
2819 
2820         msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2821                                         pd->tx_csum_limit : 9 * 1024;
2822         infer_hw_params(msp);
2823 
2824         return 0;
2825 }
2826 
2827 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2828 {
2829         struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2830 
2831         mv643xx_eth_shared_of_remove();
2832         if (!IS_ERR(msp->clk))
2833                 clk_disable_unprepare(msp->clk);
2834         return 0;
2835 }
2836 
2837 static struct platform_driver mv643xx_eth_shared_driver = {
2838         .probe          = mv643xx_eth_shared_probe,
2839         .remove         = mv643xx_eth_shared_remove,
2840         .driver = {
2841                 .name   = MV643XX_ETH_SHARED_NAME,
2842                 .owner  = THIS_MODULE,
2843                 .of_match_table = of_match_ptr(mv643xx_eth_shared_ids),
2844         },
2845 };
2846 
2847 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2848 {
2849         int addr_shift = 5 * mp->port_num;
2850         u32 data;
2851 
2852         data = rdl(mp, PHY_ADDR);
2853         data &= ~(0x1f << addr_shift);
2854         data |= (phy_addr & 0x1f) << addr_shift;
2855         wrl(mp, PHY_ADDR, data);
2856 }
2857 
2858 static int phy_addr_get(struct mv643xx_eth_private *mp)
2859 {
2860         unsigned int data;
2861 
2862         data = rdl(mp, PHY_ADDR);
2863 
2864         return (data >> (5 * mp->port_num)) & 0x1f;
2865 }
2866 
2867 static void set_params(struct mv643xx_eth_private *mp,
2868                        struct mv643xx_eth_platform_data *pd)
2869 {
2870         struct net_device *dev = mp->dev;
2871         unsigned int tx_ring_size;
2872 
2873         if (is_valid_ether_addr(pd->mac_addr))
2874                 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2875         else
2876                 uc_addr_get(mp, dev->dev_addr);
2877 
2878         mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2879         if (pd->rx_queue_size)
2880                 mp->rx_ring_size = pd->rx_queue_size;
2881         mp->rx_desc_sram_addr = pd->rx_sram_addr;
2882         mp->rx_desc_sram_size = pd->rx_sram_size;
2883 
2884         mp->rxq_count = pd->rx_queue_count ? : 1;
2885 
2886         tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2887         if (pd->tx_queue_size)
2888                 tx_ring_size = pd->tx_queue_size;
2889 
2890         mp->tx_ring_size = clamp_t(unsigned int, tx_ring_size,
2891                                    MV643XX_MAX_SKB_DESCS * 2, 4096);
2892         if (mp->tx_ring_size != tx_ring_size)
2893                 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
2894                             mp->tx_ring_size, tx_ring_size);
2895 
2896         mp->tx_desc_sram_addr = pd->tx_sram_addr;
2897         mp->tx_desc_sram_size = pd->tx_sram_size;
2898 
2899         mp->txq_count = pd->tx_queue_count ? : 1;
2900 }
2901 
2902 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2903                                    int phy_addr)
2904 {
2905         struct phy_device *phydev;
2906         int start;
2907         int num;
2908         int i;
2909         char phy_id[MII_BUS_ID_SIZE + 3];
2910 
2911         if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2912                 start = phy_addr_get(mp) & 0x1f;
2913                 num = 32;
2914         } else {
2915                 start = phy_addr & 0x1f;
2916                 num = 1;
2917         }
2918 
2919         /* Attempt to connect to the PHY using orion-mdio */
2920         phydev = ERR_PTR(-ENODEV);
2921         for (i = 0; i < num; i++) {
2922                 int addr = (start + i) & 0x1f;
2923 
2924                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2925                                 "orion-mdio-mii", addr);
2926 
2927                 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link,
2928                                 PHY_INTERFACE_MODE_GMII);
2929                 if (!IS_ERR(phydev)) {
2930                         phy_addr_set(mp, addr);
2931                         break;
2932                 }
2933         }
2934 
2935         return phydev;
2936 }
2937 
2938 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
2939 {
2940         struct phy_device *phy = mp->phy;
2941 
2942         if (speed == 0) {
2943                 phy->autoneg = AUTONEG_ENABLE;
2944                 phy->speed = 0;
2945                 phy->duplex = 0;
2946                 phy->advertising = phy->supported | ADVERTISED_Autoneg;
2947         } else {
2948                 phy->autoneg = AUTONEG_DISABLE;
2949                 phy->advertising = 0;
2950                 phy->speed = speed;
2951                 phy->duplex = duplex;
2952         }
2953         phy_start_aneg(phy);
2954 }
2955 
2956 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2957 {
2958         u32 pscr;
2959 
2960         pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2961         if (pscr & SERIAL_PORT_ENABLE) {
2962                 pscr &= ~SERIAL_PORT_ENABLE;
2963                 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2964         }
2965 
2966         pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2967         if (mp->phy == NULL) {
2968                 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2969                 if (speed == SPEED_1000)
2970                         pscr |= SET_GMII_SPEED_TO_1000;
2971                 else if (speed == SPEED_100)
2972                         pscr |= SET_MII_SPEED_TO_100;
2973 
2974                 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2975 
2976                 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2977                 if (duplex == DUPLEX_FULL)
2978                         pscr |= SET_FULL_DUPLEX_MODE;
2979         }
2980 
2981         wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2982 }
2983 
2984 static const struct net_device_ops mv643xx_eth_netdev_ops = {
2985         .ndo_open               = mv643xx_eth_open,
2986         .ndo_stop               = mv643xx_eth_stop,
2987         .ndo_start_xmit         = mv643xx_eth_xmit,
2988         .ndo_set_rx_mode        = mv643xx_eth_set_rx_mode,
2989         .ndo_set_mac_address    = mv643xx_eth_set_mac_address,
2990         .ndo_validate_addr      = eth_validate_addr,
2991         .ndo_do_ioctl           = mv643xx_eth_ioctl,
2992         .ndo_change_mtu         = mv643xx_eth_change_mtu,
2993         .ndo_set_features       = mv643xx_eth_set_features,
2994         .ndo_tx_timeout         = mv643xx_eth_tx_timeout,
2995         .ndo_get_stats          = mv643xx_eth_get_stats,
2996 #ifdef CONFIG_NET_POLL_CONTROLLER
2997         .ndo_poll_controller    = mv643xx_eth_netpoll,
2998 #endif
2999 };
3000 
3001 static int mv643xx_eth_probe(struct platform_device *pdev)
3002 {
3003         struct mv643xx_eth_platform_data *pd;
3004         struct mv643xx_eth_private *mp;
3005         struct net_device *dev;
3006         struct resource *res;
3007         int err;
3008 
3009         pd = dev_get_platdata(&pdev->dev);
3010         if (pd == NULL) {
3011                 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
3012                 return -ENODEV;
3013         }
3014 
3015         if (pd->shared == NULL) {
3016                 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
3017                 return -ENODEV;
3018         }
3019 
3020         dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
3021         if (!dev)
3022                 return -ENOMEM;
3023 
3024         mp = netdev_priv(dev);
3025         platform_set_drvdata(pdev, mp);
3026 
3027         mp->shared = platform_get_drvdata(pd->shared);
3028         mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
3029         mp->port_num = pd->port_number;
3030 
3031         mp->dev = dev;
3032 
3033         /* Kirkwood resets some registers on gated clocks. Especially
3034          * CLK125_BYPASS_EN must be cleared but is not available on
3035          * all other SoCs/System Controllers using this driver.
3036          */
3037         if (of_device_is_compatible(pdev->dev.of_node,
3038                                     "marvell,kirkwood-eth-port"))
3039                 wrlp(mp, PORT_SERIAL_CONTROL1,
3040                      rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
3041 
3042         /*
3043          * Start with a default rate, and if there is a clock, allow
3044          * it to override the default.
3045          */
3046         mp->t_clk = 133000000;
3047         mp->clk = devm_clk_get(&pdev->dev, NULL);
3048         if (!IS_ERR(mp->clk)) {
3049                 clk_prepare_enable(mp->clk);
3050                 mp->t_clk = clk_get_rate(mp->clk);
3051         } else if (!IS_ERR(mp->shared->clk)) {
3052                 mp->t_clk = clk_get_rate(mp->shared->clk);
3053         }
3054 
3055         set_params(mp, pd);
3056         netif_set_real_num_tx_queues(dev, mp->txq_count);
3057         netif_set_real_num_rx_queues(dev, mp->rxq_count);
3058 
3059         err = 0;
3060         if (pd->phy_node) {
3061                 mp->phy = of_phy_connect(mp->dev, pd->phy_node,
3062                                          mv643xx_eth_adjust_link, 0,
3063                                          PHY_INTERFACE_MODE_GMII);
3064                 if (!mp->phy)
3065                         err = -ENODEV;
3066                 else
3067                         phy_addr_set(mp, mp->phy->addr);
3068         } else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
3069                 mp->phy = phy_scan(mp, pd->phy_addr);
3070 
3071                 if (IS_ERR(mp->phy))
3072                         err = PTR_ERR(mp->phy);
3073                 else
3074                         phy_init(mp, pd->speed, pd->duplex);
3075         }
3076         if (err == -ENODEV) {
3077                 err = -EPROBE_DEFER;
3078                 goto out;
3079         }
3080         if (err)
3081                 goto out;
3082 
3083         dev->ethtool_ops = &mv643xx_eth_ethtool_ops;
3084 
3085         init_pscr(mp, pd->speed, pd->duplex);
3086 
3087 
3088         mib_counters_clear(mp);
3089 
3090         init_timer(&mp->mib_counters_timer);
3091         mp->mib_counters_timer.data = (unsigned long)mp;
3092         mp->mib_counters_timer.function = mib_counters_timer_wrapper;
3093         mp->mib_counters_timer.expires = jiffies + 30 * HZ;
3094 
3095         spin_lock_init(&mp->mib_counters_lock);
3096 
3097         INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
3098 
3099         netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT);
3100 
3101         init_timer(&mp->rx_oom);
3102         mp->rx_oom.data = (unsigned long)mp;
3103         mp->rx_oom.function = oom_timer_wrapper;
3104 
3105 
3106         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
3107         BUG_ON(!res);
3108         dev->irq = res->start;
3109 
3110         dev->netdev_ops = &mv643xx_eth_netdev_ops;
3111 
3112         dev->watchdog_timeo = 2 * HZ;
3113         dev->base_addr = 0;
3114 
3115         dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
3116         dev->vlan_features = dev->features;
3117 
3118         dev->features |= NETIF_F_RXCSUM;
3119         dev->hw_features = dev->features;
3120 
3121         dev->priv_flags |= IFF_UNICAST_FLT;
3122         dev->gso_max_segs = MV643XX_MAX_TSO_SEGS;
3123 
3124         SET_NETDEV_DEV(dev, &pdev->dev);
3125 
3126         if (mp->shared->win_protect)
3127                 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
3128 
3129         netif_carrier_off(dev);
3130 
3131         wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
3132 
3133         set_rx_coal(mp, 250);
3134         set_tx_coal(mp, 0);
3135 
3136         err = register_netdev(dev);
3137         if (err)
3138                 goto out;
3139 
3140         netdev_notice(dev, "port %d with MAC address %pM\n",
3141                       mp->port_num, dev->dev_addr);
3142 
3143         if (mp->tx_desc_sram_size > 0)
3144                 netdev_notice(dev, "configured with sram\n");
3145 
3146         return 0;
3147 
3148 out:
3149         if (!IS_ERR(mp->clk))
3150                 clk_disable_unprepare(mp->clk);
3151         free_netdev(dev);
3152 
3153         return err;
3154 }
3155 
3156 static int mv643xx_eth_remove(struct platform_device *pdev)
3157 {
3158         struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3159 
3160         unregister_netdev(mp->dev);
3161         if (mp->phy != NULL)
3162                 phy_disconnect(mp->phy);
3163         cancel_work_sync(&mp->tx_timeout_task);
3164 
3165         if (!IS_ERR(mp->clk))
3166                 clk_disable_unprepare(mp->clk);
3167 
3168         free_netdev(mp->dev);
3169 
3170         return 0;
3171 }
3172 
3173 static void mv643xx_eth_shutdown(struct platform_device *pdev)
3174 {
3175         struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3176 
3177         /* Mask all interrupts on ethernet port */
3178         wrlp(mp, INT_MASK, 0);
3179         rdlp(mp, INT_MASK);
3180 
3181         if (netif_running(mp->dev))
3182                 port_reset(mp);
3183 }
3184 
3185 static struct platform_driver mv643xx_eth_driver = {
3186         .probe          = mv643xx_eth_probe,
3187         .remove         = mv643xx_eth_remove,
3188         .shutdown       = mv643xx_eth_shutdown,
3189         .driver = {
3190                 .name   = MV643XX_ETH_NAME,
3191                 .owner  = THIS_MODULE,
3192         },
3193 };
3194 
3195 static int __init mv643xx_eth_init_module(void)
3196 {
3197         int rc;
3198 
3199         rc = platform_driver_register(&mv643xx_eth_shared_driver);
3200         if (!rc) {
3201                 rc = platform_driver_register(&mv643xx_eth_driver);
3202                 if (rc)
3203                         platform_driver_unregister(&mv643xx_eth_shared_driver);
3204         }
3205 
3206         return rc;
3207 }
3208 module_init(mv643xx_eth_init_module);
3209 
3210 static void __exit mv643xx_eth_cleanup_module(void)
3211 {
3212         platform_driver_unregister(&mv643xx_eth_driver);
3213         platform_driver_unregister(&mv643xx_eth_shared_driver);
3214 }
3215 module_exit(mv643xx_eth_cleanup_module);
3216 
3217 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3218               "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3219 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3220 MODULE_LICENSE("GPL");
3221 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
3222 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
3223 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us