Version:  2.0.40 2.2.26 2.4.37 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10

Linux/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

  1 /*******************************************************************************
  2 
  3   Intel 10 Gigabit PCI Express Linux driver
  4   Copyright(c) 1999 - 2014 Intel Corporation.
  5 
  6   This program is free software; you can redistribute it and/or modify it
  7   under the terms and conditions of the GNU General Public License,
  8   version 2, as published by the Free Software Foundation.
  9 
 10   This program is distributed in the hope it will be useful, but WITHOUT
 11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 13   more details.
 14 
 15   You should have received a copy of the GNU General Public License along with
 16   this program; if not, write to the Free Software Foundation, Inc.,
 17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 18 
 19   The full GNU General Public License is included in this distribution in
 20   the file called "COPYING".
 21 
 22   Contact Information:
 23   Linux NICS <linux.nics@intel.com>
 24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
 25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 26 
 27 *******************************************************************************/
 28 
 29 #include <linux/types.h>
 30 #include <linux/module.h>
 31 #include <linux/pci.h>
 32 #include <linux/netdevice.h>
 33 #include <linux/vmalloc.h>
 34 #include <linux/string.h>
 35 #include <linux/in.h>
 36 #include <linux/interrupt.h>
 37 #include <linux/ip.h>
 38 #include <linux/tcp.h>
 39 #include <linux/sctp.h>
 40 #include <linux/pkt_sched.h>
 41 #include <linux/ipv6.h>
 42 #include <linux/slab.h>
 43 #include <net/checksum.h>
 44 #include <net/ip6_checksum.h>
 45 #include <linux/etherdevice.h>
 46 #include <linux/ethtool.h>
 47 #include <linux/if.h>
 48 #include <linux/if_vlan.h>
 49 #include <linux/if_macvlan.h>
 50 #include <linux/if_bridge.h>
 51 #include <linux/prefetch.h>
 52 #include <scsi/fc/fc_fcoe.h>
 53 #include <net/vxlan.h>
 54 
 55 #ifdef CONFIG_OF
 56 #include <linux/of_net.h>
 57 #endif
 58 
 59 #ifdef CONFIG_SPARC
 60 #include <asm/idprom.h>
 61 #include <asm/prom.h>
 62 #endif
 63 
 64 #include "ixgbe.h"
 65 #include "ixgbe_common.h"
 66 #include "ixgbe_dcb_82599.h"
 67 #include "ixgbe_sriov.h"
 68 
 69 char ixgbe_driver_name[] = "ixgbe";
 70 static const char ixgbe_driver_string[] =
 71                               "Intel(R) 10 Gigabit PCI Express Network Driver";
 72 #ifdef IXGBE_FCOE
 73 char ixgbe_default_device_descr[] =
 74                               "Intel(R) 10 Gigabit Network Connection";
 75 #else
 76 static char ixgbe_default_device_descr[] =
 77                               "Intel(R) 10 Gigabit Network Connection";
 78 #endif
 79 #define DRV_VERSION "4.0.1-k"
 80 const char ixgbe_driver_version[] = DRV_VERSION;
 81 static const char ixgbe_copyright[] =
 82                                 "Copyright (c) 1999-2014 Intel Corporation.";
 83 
 84 static const struct ixgbe_info *ixgbe_info_tbl[] = {
 85         [board_82598]           = &ixgbe_82598_info,
 86         [board_82599]           = &ixgbe_82599_info,
 87         [board_X540]            = &ixgbe_X540_info,
 88         [board_X550]            = &ixgbe_X550_info,
 89         [board_X550EM_x]        = &ixgbe_X550EM_x_info,
 90 };
 91 
 92 /* ixgbe_pci_tbl - PCI Device ID Table
 93  *
 94  * Wildcard entries (PCI_ANY_ID) should come last
 95  * Last entry must be all 0s
 96  *
 97  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
 98  *   Class, Class Mask, private data (not used) }
 99  */
100 static const struct pci_device_id ixgbe_pci_tbl[] = {
101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
102         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
104         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
106         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
108         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
110         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
112         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
113         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
114         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
115         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
116         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
117         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
118         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
119         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
120         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
121         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
122         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
123         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
124         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
125         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
126         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
127         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
128         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
129         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
130         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
131         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
132         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
133         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
134         /* required last entry */
135         {0, }
136 };
137 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
138 
139 #ifdef CONFIG_IXGBE_DCA
140 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
141                             void *p);
142 static struct notifier_block dca_notifier = {
143         .notifier_call = ixgbe_notify_dca,
144         .next          = NULL,
145         .priority      = 0
146 };
147 #endif
148 
149 #ifdef CONFIG_PCI_IOV
150 static unsigned int max_vfs;
151 module_param(max_vfs, uint, 0);
152 MODULE_PARM_DESC(max_vfs,
153                  "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
154 #endif /* CONFIG_PCI_IOV */
155 
156 static unsigned int allow_unsupported_sfp;
157 module_param(allow_unsupported_sfp, uint, 0);
158 MODULE_PARM_DESC(allow_unsupported_sfp,
159                  "Allow unsupported and untested SFP+ modules on 82599-based adapters");
160 
161 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
162 static int debug = -1;
163 module_param(debug, int, 0);
164 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
165 
166 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
167 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
168 MODULE_LICENSE("GPL");
169 MODULE_VERSION(DRV_VERSION);
170 
171 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
172 
173 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
174                                           u32 reg, u16 *value)
175 {
176         struct pci_dev *parent_dev;
177         struct pci_bus *parent_bus;
178 
179         parent_bus = adapter->pdev->bus->parent;
180         if (!parent_bus)
181                 return -1;
182 
183         parent_dev = parent_bus->self;
184         if (!parent_dev)
185                 return -1;
186 
187         if (!pci_is_pcie(parent_dev))
188                 return -1;
189 
190         pcie_capability_read_word(parent_dev, reg, value);
191         if (*value == IXGBE_FAILED_READ_CFG_WORD &&
192             ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
193                 return -1;
194         return 0;
195 }
196 
197 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
198 {
199         struct ixgbe_hw *hw = &adapter->hw;
200         u16 link_status = 0;
201         int err;
202 
203         hw->bus.type = ixgbe_bus_type_pci_express;
204 
205         /* Get the negotiated link width and speed from PCI config space of the
206          * parent, as this device is behind a switch
207          */
208         err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
209 
210         /* assume caller will handle error case */
211         if (err)
212                 return err;
213 
214         hw->bus.width = ixgbe_convert_bus_width(link_status);
215         hw->bus.speed = ixgbe_convert_bus_speed(link_status);
216 
217         return 0;
218 }
219 
220 /**
221  * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
222  * @hw: hw specific details
223  *
224  * This function is used by probe to determine whether a device's PCI-Express
225  * bandwidth details should be gathered from the parent bus instead of from the
226  * device. Used to ensure that various locations all have the correct device ID
227  * checks.
228  */
229 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
230 {
231         switch (hw->device_id) {
232         case IXGBE_DEV_ID_82599_SFP_SF_QP:
233         case IXGBE_DEV_ID_82599_QSFP_SF_QP:
234                 return true;
235         default:
236                 return false;
237         }
238 }
239 
240 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
241                                      int expected_gts)
242 {
243         int max_gts = 0;
244         enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
245         enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
246         struct pci_dev *pdev;
247 
248         /* determine whether to use the the parent device
249          */
250         if (ixgbe_pcie_from_parent(&adapter->hw))
251                 pdev = adapter->pdev->bus->parent->self;
252         else
253                 pdev = adapter->pdev;
254 
255         if (pcie_get_minimum_link(pdev, &speed, &width) ||
256             speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
257                 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
258                 return;
259         }
260 
261         switch (speed) {
262         case PCIE_SPEED_2_5GT:
263                 /* 8b/10b encoding reduces max throughput by 20% */
264                 max_gts = 2 * width;
265                 break;
266         case PCIE_SPEED_5_0GT:
267                 /* 8b/10b encoding reduces max throughput by 20% */
268                 max_gts = 4 * width;
269                 break;
270         case PCIE_SPEED_8_0GT:
271                 /* 128b/130b encoding reduces throughput by less than 2% */
272                 max_gts = 8 * width;
273                 break;
274         default:
275                 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
276                 return;
277         }
278 
279         e_dev_info("PCI Express bandwidth of %dGT/s available\n",
280                    max_gts);
281         e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
282                    (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
283                     speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
284                     speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
285                     "Unknown"),
286                    width,
287                    (speed == PCIE_SPEED_2_5GT ? "20%" :
288                     speed == PCIE_SPEED_5_0GT ? "20%" :
289                     speed == PCIE_SPEED_8_0GT ? "<2%" :
290                     "Unknown"));
291 
292         if (max_gts < expected_gts) {
293                 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
294                 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
295                         expected_gts);
296                 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
297         }
298 }
299 
300 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
301 {
302         if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
303             !test_bit(__IXGBE_REMOVING, &adapter->state) &&
304             !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
305                 schedule_work(&adapter->service_task);
306 }
307 
308 static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
309 {
310         struct ixgbe_adapter *adapter = hw->back;
311 
312         if (!hw->hw_addr)
313                 return;
314         hw->hw_addr = NULL;
315         e_dev_err("Adapter removed\n");
316         if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
317                 ixgbe_service_event_schedule(adapter);
318 }
319 
320 static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
321 {
322         u32 value;
323 
324         /* The following check not only optimizes a bit by not
325          * performing a read on the status register when the
326          * register just read was a status register read that
327          * returned IXGBE_FAILED_READ_REG. It also blocks any
328          * potential recursion.
329          */
330         if (reg == IXGBE_STATUS) {
331                 ixgbe_remove_adapter(hw);
332                 return;
333         }
334         value = ixgbe_read_reg(hw, IXGBE_STATUS);
335         if (value == IXGBE_FAILED_READ_REG)
336                 ixgbe_remove_adapter(hw);
337 }
338 
339 /**
340  * ixgbe_read_reg - Read from device register
341  * @hw: hw specific details
342  * @reg: offset of register to read
343  *
344  * Returns : value read or IXGBE_FAILED_READ_REG if removed
345  *
346  * This function is used to read device registers. It checks for device
347  * removal by confirming any read that returns all ones by checking the
348  * status register value for all ones. This function avoids reading from
349  * the hardware if a removal was previously detected in which case it
350  * returns IXGBE_FAILED_READ_REG (all ones).
351  */
352 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
353 {
354         u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
355         u32 value;
356 
357         if (ixgbe_removed(reg_addr))
358                 return IXGBE_FAILED_READ_REG;
359         value = readl(reg_addr + reg);
360         if (unlikely(value == IXGBE_FAILED_READ_REG))
361                 ixgbe_check_remove(hw, reg);
362         return value;
363 }
364 
365 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
366 {
367         u16 value;
368 
369         pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
370         if (value == IXGBE_FAILED_READ_CFG_WORD) {
371                 ixgbe_remove_adapter(hw);
372                 return true;
373         }
374         return false;
375 }
376 
377 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
378 {
379         struct ixgbe_adapter *adapter = hw->back;
380         u16 value;
381 
382         if (ixgbe_removed(hw->hw_addr))
383                 return IXGBE_FAILED_READ_CFG_WORD;
384         pci_read_config_word(adapter->pdev, reg, &value);
385         if (value == IXGBE_FAILED_READ_CFG_WORD &&
386             ixgbe_check_cfg_remove(hw, adapter->pdev))
387                 return IXGBE_FAILED_READ_CFG_WORD;
388         return value;
389 }
390 
391 #ifdef CONFIG_PCI_IOV
392 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
393 {
394         struct ixgbe_adapter *adapter = hw->back;
395         u32 value;
396 
397         if (ixgbe_removed(hw->hw_addr))
398                 return IXGBE_FAILED_READ_CFG_DWORD;
399         pci_read_config_dword(adapter->pdev, reg, &value);
400         if (value == IXGBE_FAILED_READ_CFG_DWORD &&
401             ixgbe_check_cfg_remove(hw, adapter->pdev))
402                 return IXGBE_FAILED_READ_CFG_DWORD;
403         return value;
404 }
405 #endif /* CONFIG_PCI_IOV */
406 
407 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
408 {
409         struct ixgbe_adapter *adapter = hw->back;
410 
411         if (ixgbe_removed(hw->hw_addr))
412                 return;
413         pci_write_config_word(adapter->pdev, reg, value);
414 }
415 
416 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
417 {
418         BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
419 
420         /* flush memory to make sure state is correct before next watchdog */
421         smp_mb__before_atomic();
422         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
423 }
424 
425 struct ixgbe_reg_info {
426         u32 ofs;
427         char *name;
428 };
429 
430 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
431 
432         /* General Registers */
433         {IXGBE_CTRL, "CTRL"},
434         {IXGBE_STATUS, "STATUS"},
435         {IXGBE_CTRL_EXT, "CTRL_EXT"},
436 
437         /* Interrupt Registers */
438         {IXGBE_EICR, "EICR"},
439 
440         /* RX Registers */
441         {IXGBE_SRRCTL(0), "SRRCTL"},
442         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
443         {IXGBE_RDLEN(0), "RDLEN"},
444         {IXGBE_RDH(0), "RDH"},
445         {IXGBE_RDT(0), "RDT"},
446         {IXGBE_RXDCTL(0), "RXDCTL"},
447         {IXGBE_RDBAL(0), "RDBAL"},
448         {IXGBE_RDBAH(0), "RDBAH"},
449 
450         /* TX Registers */
451         {IXGBE_TDBAL(0), "TDBAL"},
452         {IXGBE_TDBAH(0), "TDBAH"},
453         {IXGBE_TDLEN(0), "TDLEN"},
454         {IXGBE_TDH(0), "TDH"},
455         {IXGBE_TDT(0), "TDT"},
456         {IXGBE_TXDCTL(0), "TXDCTL"},
457 
458         /* List Terminator */
459         { .name = NULL }
460 };
461 
462 
463 /*
464  * ixgbe_regdump - register printout routine
465  */
466 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
467 {
468         int i = 0, j = 0;
469         char rname[16];
470         u32 regs[64];
471 
472         switch (reginfo->ofs) {
473         case IXGBE_SRRCTL(0):
474                 for (i = 0; i < 64; i++)
475                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
476                 break;
477         case IXGBE_DCA_RXCTRL(0):
478                 for (i = 0; i < 64; i++)
479                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
480                 break;
481         case IXGBE_RDLEN(0):
482                 for (i = 0; i < 64; i++)
483                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
484                 break;
485         case IXGBE_RDH(0):
486                 for (i = 0; i < 64; i++)
487                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
488                 break;
489         case IXGBE_RDT(0):
490                 for (i = 0; i < 64; i++)
491                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
492                 break;
493         case IXGBE_RXDCTL(0):
494                 for (i = 0; i < 64; i++)
495                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
496                 break;
497         case IXGBE_RDBAL(0):
498                 for (i = 0; i < 64; i++)
499                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
500                 break;
501         case IXGBE_RDBAH(0):
502                 for (i = 0; i < 64; i++)
503                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
504                 break;
505         case IXGBE_TDBAL(0):
506                 for (i = 0; i < 64; i++)
507                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
508                 break;
509         case IXGBE_TDBAH(0):
510                 for (i = 0; i < 64; i++)
511                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
512                 break;
513         case IXGBE_TDLEN(0):
514                 for (i = 0; i < 64; i++)
515                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
516                 break;
517         case IXGBE_TDH(0):
518                 for (i = 0; i < 64; i++)
519                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
520                 break;
521         case IXGBE_TDT(0):
522                 for (i = 0; i < 64; i++)
523                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
524                 break;
525         case IXGBE_TXDCTL(0):
526                 for (i = 0; i < 64; i++)
527                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
528                 break;
529         default:
530                 pr_info("%-15s %08x\n", reginfo->name,
531                         IXGBE_READ_REG(hw, reginfo->ofs));
532                 return;
533         }
534 
535         for (i = 0; i < 8; i++) {
536                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
537                 pr_err("%-15s", rname);
538                 for (j = 0; j < 8; j++)
539                         pr_cont(" %08x", regs[i*8+j]);
540                 pr_cont("\n");
541         }
542 
543 }
544 
545 /*
546  * ixgbe_dump - Print registers, tx-rings and rx-rings
547  */
548 static void ixgbe_dump(struct ixgbe_adapter *adapter)
549 {
550         struct net_device *netdev = adapter->netdev;
551         struct ixgbe_hw *hw = &adapter->hw;
552         struct ixgbe_reg_info *reginfo;
553         int n = 0;
554         struct ixgbe_ring *tx_ring;
555         struct ixgbe_tx_buffer *tx_buffer;
556         union ixgbe_adv_tx_desc *tx_desc;
557         struct my_u0 { u64 a; u64 b; } *u0;
558         struct ixgbe_ring *rx_ring;
559         union ixgbe_adv_rx_desc *rx_desc;
560         struct ixgbe_rx_buffer *rx_buffer_info;
561         u32 staterr;
562         int i = 0;
563 
564         if (!netif_msg_hw(adapter))
565                 return;
566 
567         /* Print netdevice Info */
568         if (netdev) {
569                 dev_info(&adapter->pdev->dev, "Net device Info\n");
570                 pr_info("Device Name     state            "
571                         "trans_start      last_rx\n");
572                 pr_info("%-15s %016lX %016lX %016lX\n",
573                         netdev->name,
574                         netdev->state,
575                         netdev->trans_start,
576                         netdev->last_rx);
577         }
578 
579         /* Print Registers */
580         dev_info(&adapter->pdev->dev, "Register Dump\n");
581         pr_info(" Register Name   Value\n");
582         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
583              reginfo->name; reginfo++) {
584                 ixgbe_regdump(hw, reginfo);
585         }
586 
587         /* Print TX Ring Summary */
588         if (!netdev || !netif_running(netdev))
589                 return;
590 
591         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
592         pr_info(" %s     %s              %s        %s\n",
593                 "Queue [NTU] [NTC] [bi(ntc)->dma  ]",
594                 "leng", "ntw", "timestamp");
595         for (n = 0; n < adapter->num_tx_queues; n++) {
596                 tx_ring = adapter->tx_ring[n];
597                 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
598                 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
599                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
600                            (u64)dma_unmap_addr(tx_buffer, dma),
601                            dma_unmap_len(tx_buffer, len),
602                            tx_buffer->next_to_watch,
603                            (u64)tx_buffer->time_stamp);
604         }
605 
606         /* Print TX Rings */
607         if (!netif_msg_tx_done(adapter))
608                 goto rx_ring_summary;
609 
610         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
611 
612         /* Transmit Descriptor Formats
613          *
614          * 82598 Advanced Transmit Descriptor
615          *   +--------------------------------------------------------------+
616          * 0 |         Buffer Address [63:0]                                |
617          *   +--------------------------------------------------------------+
618          * 8 |  PAYLEN  | POPTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
619          *   +--------------------------------------------------------------+
620          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
621          *
622          * 82598 Advanced Transmit Descriptor (Write-Back Format)
623          *   +--------------------------------------------------------------+
624          * 0 |                          RSV [63:0]                          |
625          *   +--------------------------------------------------------------+
626          * 8 |            RSV           |  STA  |          NXTSEQ           |
627          *   +--------------------------------------------------------------+
628          *   63                       36 35   32 31                         0
629          *
630          * 82599+ Advanced Transmit Descriptor
631          *   +--------------------------------------------------------------+
632          * 0 |         Buffer Address [63:0]                                |
633          *   +--------------------------------------------------------------+
634          * 8 |PAYLEN  |POPTS|CC|IDX  |STA  |DCMD  |DTYP |MAC  |RSV  |DTALEN |
635          *   +--------------------------------------------------------------+
636          *   63     46 45 40 39 38 36 35 32 31  24 23 20 19 18 17 16 15     0
637          *
638          * 82599+ Advanced Transmit Descriptor (Write-Back Format)
639          *   +--------------------------------------------------------------+
640          * 0 |                          RSV [63:0]                          |
641          *   +--------------------------------------------------------------+
642          * 8 |            RSV           |  STA  |           RSV             |
643          *   +--------------------------------------------------------------+
644          *   63                       36 35   32 31                         0
645          */
646 
647         for (n = 0; n < adapter->num_tx_queues; n++) {
648                 tx_ring = adapter->tx_ring[n];
649                 pr_info("------------------------------------\n");
650                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
651                 pr_info("------------------------------------\n");
652                 pr_info("%s%s    %s              %s        %s          %s\n",
653                         "T [desc]     [address 63:0  ] ",
654                         "[PlPOIdStDDt Ln] [bi->dma       ] ",
655                         "leng", "ntw", "timestamp", "bi->skb");
656 
657                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
658                         tx_desc = IXGBE_TX_DESC(tx_ring, i);
659                         tx_buffer = &tx_ring->tx_buffer_info[i];
660                         u0 = (struct my_u0 *)tx_desc;
661                         if (dma_unmap_len(tx_buffer, len) > 0) {
662                                 pr_info("T [0x%03X]    %016llX %016llX %016llX %08X %p %016llX %p",
663                                         i,
664                                         le64_to_cpu(u0->a),
665                                         le64_to_cpu(u0->b),
666                                         (u64)dma_unmap_addr(tx_buffer, dma),
667                                         dma_unmap_len(tx_buffer, len),
668                                         tx_buffer->next_to_watch,
669                                         (u64)tx_buffer->time_stamp,
670                                         tx_buffer->skb);
671                                 if (i == tx_ring->next_to_use &&
672                                         i == tx_ring->next_to_clean)
673                                         pr_cont(" NTC/U\n");
674                                 else if (i == tx_ring->next_to_use)
675                                         pr_cont(" NTU\n");
676                                 else if (i == tx_ring->next_to_clean)
677                                         pr_cont(" NTC\n");
678                                 else
679                                         pr_cont("\n");
680 
681                                 if (netif_msg_pktdata(adapter) &&
682                                     tx_buffer->skb)
683                                         print_hex_dump(KERN_INFO, "",
684                                                 DUMP_PREFIX_ADDRESS, 16, 1,
685                                                 tx_buffer->skb->data,
686                                                 dma_unmap_len(tx_buffer, len),
687                                                 true);
688                         }
689                 }
690         }
691 
692         /* Print RX Rings Summary */
693 rx_ring_summary:
694         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
695         pr_info("Queue [NTU] [NTC]\n");
696         for (n = 0; n < adapter->num_rx_queues; n++) {
697                 rx_ring = adapter->rx_ring[n];
698                 pr_info("%5d %5X %5X\n",
699                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
700         }
701 
702         /* Print RX Rings */
703         if (!netif_msg_rx_status(adapter))
704                 return;
705 
706         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
707 
708         /* Receive Descriptor Formats
709          *
710          * 82598 Advanced Receive Descriptor (Read) Format
711          *    63                                           1        0
712          *    +-----------------------------------------------------+
713          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
714          *    +----------------------------------------------+------+
715          *  8 |       Header Buffer Address [63:1]           |  DD  |
716          *    +-----------------------------------------------------+
717          *
718          *
719          * 82598 Advanced Receive Descriptor (Write-Back) Format
720          *
721          *   63       48 47    32 31  30      21 20 16 15   4 3     0
722          *   +------------------------------------------------------+
723          * 0 |       RSS Hash /  |SPH| HDR_LEN  | RSV |Packet|  RSS |
724          *   | Packet   | IP     |   |          |     | Type | Type |
725          *   | Checksum | Ident  |   |          |     |      |      |
726          *   +------------------------------------------------------+
727          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
728          *   +------------------------------------------------------+
729          *   63       48 47    32 31            20 19               0
730          *
731          * 82599+ Advanced Receive Descriptor (Read) Format
732          *    63                                           1        0
733          *    +-----------------------------------------------------+
734          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
735          *    +----------------------------------------------+------+
736          *  8 |       Header Buffer Address [63:1]           |  DD  |
737          *    +-----------------------------------------------------+
738          *
739          *
740          * 82599+ Advanced Receive Descriptor (Write-Back) Format
741          *
742          *   63       48 47    32 31  30      21 20 17 16   4 3     0
743          *   +------------------------------------------------------+
744          * 0 |RSS / Frag Checksum|SPH| HDR_LEN  |RSC- |Packet|  RSS |
745          *   |/ RTT / PCoE_PARAM |   |          | CNT | Type | Type |
746          *   |/ Flow Dir Flt ID  |   |          |     |      |      |
747          *   +------------------------------------------------------+
748          * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
749          *   +------------------------------------------------------+
750          *   63       48 47    32 31          20 19                 0
751          */
752 
753         for (n = 0; n < adapter->num_rx_queues; n++) {
754                 rx_ring = adapter->rx_ring[n];
755                 pr_info("------------------------------------\n");
756                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
757                 pr_info("------------------------------------\n");
758                 pr_info("%s%s%s",
759                         "R  [desc]      [ PktBuf     A0] ",
760                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb       ] ",
761                         "<-- Adv Rx Read format\n");
762                 pr_info("%s%s%s",
763                         "RWB[desc]      [PcsmIpSHl PtRs] ",
764                         "[vl er S cks ln] ---------------- [bi->skb       ] ",
765                         "<-- Adv Rx Write-Back format\n");
766 
767                 for (i = 0; i < rx_ring->count; i++) {
768                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
769                         rx_desc = IXGBE_RX_DESC(rx_ring, i);
770                         u0 = (struct my_u0 *)rx_desc;
771                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
772                         if (staterr & IXGBE_RXD_STAT_DD) {
773                                 /* Descriptor Done */
774                                 pr_info("RWB[0x%03X]     %016llX "
775                                         "%016llX ---------------- %p", i,
776                                         le64_to_cpu(u0->a),
777                                         le64_to_cpu(u0->b),
778                                         rx_buffer_info->skb);
779                         } else {
780                                 pr_info("R  [0x%03X]     %016llX "
781                                         "%016llX %016llX %p", i,
782                                         le64_to_cpu(u0->a),
783                                         le64_to_cpu(u0->b),
784                                         (u64)rx_buffer_info->dma,
785                                         rx_buffer_info->skb);
786 
787                                 if (netif_msg_pktdata(adapter) &&
788                                     rx_buffer_info->dma) {
789                                         print_hex_dump(KERN_INFO, "",
790                                            DUMP_PREFIX_ADDRESS, 16, 1,
791                                            page_address(rx_buffer_info->page) +
792                                                     rx_buffer_info->page_offset,
793                                            ixgbe_rx_bufsz(rx_ring), true);
794                                 }
795                         }
796 
797                         if (i == rx_ring->next_to_use)
798                                 pr_cont(" NTU\n");
799                         else if (i == rx_ring->next_to_clean)
800                                 pr_cont(" NTC\n");
801                         else
802                                 pr_cont("\n");
803 
804                 }
805         }
806 }
807 
808 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
809 {
810         u32 ctrl_ext;
811 
812         /* Let firmware take over control of h/w */
813         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
814         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
815                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
816 }
817 
818 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
819 {
820         u32 ctrl_ext;
821 
822         /* Let firmware know the driver has taken over */
823         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
824         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
825                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
826 }
827 
828 /**
829  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
830  * @adapter: pointer to adapter struct
831  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
832  * @queue: queue to map the corresponding interrupt to
833  * @msix_vector: the vector to map to the corresponding queue
834  *
835  */
836 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
837                            u8 queue, u8 msix_vector)
838 {
839         u32 ivar, index;
840         struct ixgbe_hw *hw = &adapter->hw;
841         switch (hw->mac.type) {
842         case ixgbe_mac_82598EB:
843                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
844                 if (direction == -1)
845                         direction = 0;
846                 index = (((direction * 64) + queue) >> 2) & 0x1F;
847                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
848                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
849                 ivar |= (msix_vector << (8 * (queue & 0x3)));
850                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
851                 break;
852         case ixgbe_mac_82599EB:
853         case ixgbe_mac_X540:
854         case ixgbe_mac_X550:
855         case ixgbe_mac_X550EM_x:
856                 if (direction == -1) {
857                         /* other causes */
858                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
859                         index = ((queue & 1) * 8);
860                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
861                         ivar &= ~(0xFF << index);
862                         ivar |= (msix_vector << index);
863                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
864                         break;
865                 } else {
866                         /* tx or rx causes */
867                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
868                         index = ((16 * (queue & 1)) + (8 * direction));
869                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
870                         ivar &= ~(0xFF << index);
871                         ivar |= (msix_vector << index);
872                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
873                         break;
874                 }
875         default:
876                 break;
877         }
878 }
879 
880 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
881                                           u64 qmask)
882 {
883         u32 mask;
884 
885         switch (adapter->hw.mac.type) {
886         case ixgbe_mac_82598EB:
887                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
888                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
889                 break;
890         case ixgbe_mac_82599EB:
891         case ixgbe_mac_X540:
892         case ixgbe_mac_X550:
893         case ixgbe_mac_X550EM_x:
894                 mask = (qmask & 0xFFFFFFFF);
895                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
896                 mask = (qmask >> 32);
897                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
898                 break;
899         default:
900                 break;
901         }
902 }
903 
904 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
905                                       struct ixgbe_tx_buffer *tx_buffer)
906 {
907         if (tx_buffer->skb) {
908                 dev_kfree_skb_any(tx_buffer->skb);
909                 if (dma_unmap_len(tx_buffer, len))
910                         dma_unmap_single(ring->dev,
911                                          dma_unmap_addr(tx_buffer, dma),
912                                          dma_unmap_len(tx_buffer, len),
913                                          DMA_TO_DEVICE);
914         } else if (dma_unmap_len(tx_buffer, len)) {
915                 dma_unmap_page(ring->dev,
916                                dma_unmap_addr(tx_buffer, dma),
917                                dma_unmap_len(tx_buffer, len),
918                                DMA_TO_DEVICE);
919         }
920         tx_buffer->next_to_watch = NULL;
921         tx_buffer->skb = NULL;
922         dma_unmap_len_set(tx_buffer, len, 0);
923         /* tx_buffer must be completely set up in the transmit path */
924 }
925 
926 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
927 {
928         struct ixgbe_hw *hw = &adapter->hw;
929         struct ixgbe_hw_stats *hwstats = &adapter->stats;
930         int i;
931         u32 data;
932 
933         if ((hw->fc.current_mode != ixgbe_fc_full) &&
934             (hw->fc.current_mode != ixgbe_fc_rx_pause))
935                 return;
936 
937         switch (hw->mac.type) {
938         case ixgbe_mac_82598EB:
939                 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
940                 break;
941         default:
942                 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
943         }
944         hwstats->lxoffrxc += data;
945 
946         /* refill credits (no tx hang) if we received xoff */
947         if (!data)
948                 return;
949 
950         for (i = 0; i < adapter->num_tx_queues; i++)
951                 clear_bit(__IXGBE_HANG_CHECK_ARMED,
952                           &adapter->tx_ring[i]->state);
953 }
954 
955 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
956 {
957         struct ixgbe_hw *hw = &adapter->hw;
958         struct ixgbe_hw_stats *hwstats = &adapter->stats;
959         u32 xoff[8] = {0};
960         u8 tc;
961         int i;
962         bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
963 
964         if (adapter->ixgbe_ieee_pfc)
965                 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
966 
967         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
968                 ixgbe_update_xoff_rx_lfc(adapter);
969                 return;
970         }
971 
972         /* update stats for each tc, only valid with PFC enabled */
973         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
974                 u32 pxoffrxc;
975 
976                 switch (hw->mac.type) {
977                 case ixgbe_mac_82598EB:
978                         pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
979                         break;
980                 default:
981                         pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
982                 }
983                 hwstats->pxoffrxc[i] += pxoffrxc;
984                 /* Get the TC for given UP */
985                 tc = netdev_get_prio_tc_map(adapter->netdev, i);
986                 xoff[tc] += pxoffrxc;
987         }
988 
989         /* disarm tx queues that have received xoff frames */
990         for (i = 0; i < adapter->num_tx_queues; i++) {
991                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
992 
993                 tc = tx_ring->dcb_tc;
994                 if (xoff[tc])
995                         clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
996         }
997 }
998 
999 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
1000 {
1001         return ring->stats.packets;
1002 }
1003 
1004 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1005 {
1006         struct ixgbe_adapter *adapter;
1007         struct ixgbe_hw *hw;
1008         u32 head, tail;
1009 
1010         if (ring->l2_accel_priv)
1011                 adapter = ring->l2_accel_priv->real_adapter;
1012         else
1013                 adapter = netdev_priv(ring->netdev);
1014 
1015         hw = &adapter->hw;
1016         head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1017         tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
1018 
1019         if (head != tail)
1020                 return (head < tail) ?
1021                         tail - head : (tail + ring->count - head);
1022 
1023         return 0;
1024 }
1025 
1026 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1027 {
1028         u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1029         u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1030         u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
1031 
1032         clear_check_for_tx_hang(tx_ring);
1033 
1034         /*
1035          * Check for a hung queue, but be thorough. This verifies
1036          * that a transmit has been completed since the previous
1037          * check AND there is at least one packet pending. The
1038          * ARMED bit is set to indicate a potential hang. The
1039          * bit is cleared if a pause frame is received to remove
1040          * false hang detection due to PFC or 802.3x frames. By
1041          * requiring this to fail twice we avoid races with
1042          * pfc clearing the ARMED bit and conditions where we
1043          * run the check_tx_hang logic with a transmit completion
1044          * pending but without time to complete it yet.
1045          */
1046         if (tx_done_old == tx_done && tx_pending)
1047                 /* make sure it is true for two checks in a row */
1048                 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1049                                         &tx_ring->state);
1050         /* update completed stats and continue */
1051         tx_ring->tx_stats.tx_done_old = tx_done;
1052         /* reset the countdown */
1053         clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1054 
1055         return false;
1056 }
1057 
1058 /**
1059  * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1060  * @adapter: driver private struct
1061  **/
1062 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1063 {
1064 
1065         /* Do the reset outside of interrupt context */
1066         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1067                 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
1068                 e_warn(drv, "initiating reset due to tx timeout\n");
1069                 ixgbe_service_event_schedule(adapter);
1070         }
1071 }
1072 
1073 /**
1074  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
1075  * @q_vector: structure containing interrupt and ring information
1076  * @tx_ring: tx ring to clean
1077  **/
1078 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
1079                                struct ixgbe_ring *tx_ring)
1080 {
1081         struct ixgbe_adapter *adapter = q_vector->adapter;
1082         struct ixgbe_tx_buffer *tx_buffer;
1083         union ixgbe_adv_tx_desc *tx_desc;
1084         unsigned int total_bytes = 0, total_packets = 0;
1085         unsigned int budget = q_vector->tx.work_limit;
1086         unsigned int i = tx_ring->next_to_clean;
1087 
1088         if (test_bit(__IXGBE_DOWN, &adapter->state))
1089                 return true;
1090 
1091         tx_buffer = &tx_ring->tx_buffer_info[i];
1092         tx_desc = IXGBE_TX_DESC(tx_ring, i);
1093         i -= tx_ring->count;
1094 
1095         do {
1096                 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1097 
1098                 /* if next_to_watch is not set then there is no work pending */
1099                 if (!eop_desc)
1100                         break;
1101 
1102                 /* prevent any other reads prior to eop_desc */
1103                 read_barrier_depends();
1104 
1105                 /* if DD is not set pending work has not been completed */
1106                 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1107                         break;
1108 
1109                 /* clear next_to_watch to prevent false hangs */
1110                 tx_buffer->next_to_watch = NULL;
1111 
1112                 /* update the statistics for this packet */
1113                 total_bytes += tx_buffer->bytecount;
1114                 total_packets += tx_buffer->gso_segs;
1115 
1116                 /* free the skb */
1117                 dev_consume_skb_any(tx_buffer->skb);
1118 
1119                 /* unmap skb header data */
1120                 dma_unmap_single(tx_ring->dev,
1121                                  dma_unmap_addr(tx_buffer, dma),
1122                                  dma_unmap_len(tx_buffer, len),
1123                                  DMA_TO_DEVICE);
1124 
1125                 /* clear tx_buffer data */
1126                 tx_buffer->skb = NULL;
1127                 dma_unmap_len_set(tx_buffer, len, 0);
1128 
1129                 /* unmap remaining buffers */
1130                 while (tx_desc != eop_desc) {
1131                         tx_buffer++;
1132                         tx_desc++;
1133                         i++;
1134                         if (unlikely(!i)) {
1135                                 i -= tx_ring->count;
1136                                 tx_buffer = tx_ring->tx_buffer_info;
1137                                 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1138                         }
1139 
1140                         /* unmap any remaining paged data */
1141                         if (dma_unmap_len(tx_buffer, len)) {
1142                                 dma_unmap_page(tx_ring->dev,
1143                                                dma_unmap_addr(tx_buffer, dma),
1144                                                dma_unmap_len(tx_buffer, len),
1145                                                DMA_TO_DEVICE);
1146                                 dma_unmap_len_set(tx_buffer, len, 0);
1147                         }
1148                 }
1149 
1150                 /* move us one more past the eop_desc for start of next pkt */
1151                 tx_buffer++;
1152                 tx_desc++;
1153                 i++;
1154                 if (unlikely(!i)) {
1155                         i -= tx_ring->count;
1156                         tx_buffer = tx_ring->tx_buffer_info;
1157                         tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1158                 }
1159 
1160                 /* issue prefetch for next Tx descriptor */
1161                 prefetch(tx_desc);
1162 
1163                 /* update budget accounting */
1164                 budget--;
1165         } while (likely(budget));
1166 
1167         i += tx_ring->count;
1168         tx_ring->next_to_clean = i;
1169         u64_stats_update_begin(&tx_ring->syncp);
1170         tx_ring->stats.bytes += total_bytes;
1171         tx_ring->stats.packets += total_packets;
1172         u64_stats_update_end(&tx_ring->syncp);
1173         q_vector->tx.total_bytes += total_bytes;
1174         q_vector->tx.total_packets += total_packets;
1175 
1176         if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1177                 /* schedule immediate reset if we believe we hung */
1178                 struct ixgbe_hw *hw = &adapter->hw;
1179                 e_err(drv, "Detected Tx Unit Hang\n"
1180                         "  Tx Queue             <%d>\n"
1181                         "  TDH, TDT             <%x>, <%x>\n"
1182                         "  next_to_use          <%x>\n"
1183                         "  next_to_clean        <%x>\n"
1184                         "tx_buffer_info[next_to_clean]\n"
1185                         "  time_stamp           <%lx>\n"
1186                         "  jiffies              <%lx>\n",
1187                         tx_ring->queue_index,
1188                         IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1189                         IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
1190                         tx_ring->next_to_use, i,
1191                         tx_ring->tx_buffer_info[i].time_stamp, jiffies);
1192 
1193                 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1194 
1195                 e_info(probe,
1196                        "tx hang %d detected on queue %d, resetting adapter\n",
1197                         adapter->tx_timeout_count + 1, tx_ring->queue_index);
1198 
1199                 /* schedule immediate reset if we believe we hung */
1200                 ixgbe_tx_timeout_reset(adapter);
1201 
1202                 /* the adapter is about to reset, no point in enabling stuff */
1203                 return true;
1204         }
1205 
1206         netdev_tx_completed_queue(txring_txq(tx_ring),
1207                                   total_packets, total_bytes);
1208 
1209 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
1210         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1211                      (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
1212                 /* Make sure that anybody stopping the queue after this
1213                  * sees the new next_to_clean.
1214                  */
1215                 smp_mb();
1216                 if (__netif_subqueue_stopped(tx_ring->netdev,
1217                                              tx_ring->queue_index)
1218                     && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1219                         netif_wake_subqueue(tx_ring->netdev,
1220                                             tx_ring->queue_index);
1221                         ++tx_ring->tx_stats.restart_queue;
1222                 }
1223         }
1224 
1225         return !!budget;
1226 }
1227 
1228 #ifdef CONFIG_IXGBE_DCA
1229 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1230                                 struct ixgbe_ring *tx_ring,
1231                                 int cpu)
1232 {
1233         struct ixgbe_hw *hw = &adapter->hw;
1234         u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1235         u16 reg_offset;
1236 
1237         switch (hw->mac.type) {
1238         case ixgbe_mac_82598EB:
1239                 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1240                 break;
1241         case ixgbe_mac_82599EB:
1242         case ixgbe_mac_X540:
1243                 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1244                 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1245                 break;
1246         default:
1247                 /* for unknown hardware do not write register */
1248                 return;
1249         }
1250 
1251         /*
1252          * We can enable relaxed ordering for reads, but not writes when
1253          * DCA is enabled.  This is due to a known issue in some chipsets
1254          * which will cause the DCA tag to be cleared.
1255          */
1256         txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1257                   IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1258                   IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1259 
1260         IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1261 }
1262 
1263 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1264                                 struct ixgbe_ring *rx_ring,
1265                                 int cpu)
1266 {
1267         struct ixgbe_hw *hw = &adapter->hw;
1268         u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1269         u8 reg_idx = rx_ring->reg_idx;
1270 
1271 
1272         switch (hw->mac.type) {
1273         case ixgbe_mac_82599EB:
1274         case ixgbe_mac_X540:
1275                 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1276                 break;
1277         default:
1278                 break;
1279         }
1280 
1281         /*
1282          * We can enable relaxed ordering for reads, but not writes when
1283          * DCA is enabled.  This is due to a known issue in some chipsets
1284          * which will cause the DCA tag to be cleared.
1285          */
1286         rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1287                   IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1288 
1289         IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1290 }
1291 
1292 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1293 {
1294         struct ixgbe_adapter *adapter = q_vector->adapter;
1295         struct ixgbe_ring *ring;
1296         int cpu = get_cpu();
1297 
1298         if (q_vector->cpu == cpu)
1299                 goto out_no_update;
1300 
1301         ixgbe_for_each_ring(ring, q_vector->tx)
1302                 ixgbe_update_tx_dca(adapter, ring, cpu);
1303 
1304         ixgbe_for_each_ring(ring, q_vector->rx)
1305                 ixgbe_update_rx_dca(adapter, ring, cpu);
1306 
1307         q_vector->cpu = cpu;
1308 out_no_update:
1309         put_cpu();
1310 }
1311 
1312 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1313 {
1314         int i;
1315 
1316         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1317                 return;
1318 
1319         /* always use CB2 mode, difference is masked in the CB driver */
1320         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1321 
1322         for (i = 0; i < adapter->num_q_vectors; i++) {
1323                 adapter->q_vector[i]->cpu = -1;
1324                 ixgbe_update_dca(adapter->q_vector[i]);
1325         }
1326 }
1327 
1328 static int __ixgbe_notify_dca(struct device *dev, void *data)
1329 {
1330         struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1331         unsigned long event = *(unsigned long *)data;
1332 
1333         if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1334                 return 0;
1335 
1336         switch (event) {
1337         case DCA_PROVIDER_ADD:
1338                 /* if we're already enabled, don't do it again */
1339                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1340                         break;
1341                 if (dca_add_requester(dev) == 0) {
1342                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1343                         ixgbe_setup_dca(adapter);
1344                         break;
1345                 }
1346                 /* Fall Through since DCA is disabled. */
1347         case DCA_PROVIDER_REMOVE:
1348                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1349                         dca_remove_requester(dev);
1350                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1351                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1352                 }
1353                 break;
1354         }
1355 
1356         return 0;
1357 }
1358 
1359 #endif /* CONFIG_IXGBE_DCA */
1360 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1361                                  union ixgbe_adv_rx_desc *rx_desc,
1362                                  struct sk_buff *skb)
1363 {
1364         if (ring->netdev->features & NETIF_F_RXHASH)
1365                 skb_set_hash(skb,
1366                              le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1367                              PKT_HASH_TYPE_L3);
1368 }
1369 
1370 #ifdef IXGBE_FCOE
1371 /**
1372  * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1373  * @ring: structure containing ring specific data
1374  * @rx_desc: advanced rx descriptor
1375  *
1376  * Returns : true if it is FCoE pkt
1377  */
1378 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1379                                     union ixgbe_adv_rx_desc *rx_desc)
1380 {
1381         __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1382 
1383         return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1384                ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1385                 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1386                              IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1387 }
1388 
1389 #endif /* IXGBE_FCOE */
1390 /**
1391  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1392  * @ring: structure containing ring specific data
1393  * @rx_desc: current Rx descriptor being processed
1394  * @skb: skb currently being received and modified
1395  **/
1396 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1397                                      union ixgbe_adv_rx_desc *rx_desc,
1398                                      struct sk_buff *skb)
1399 {
1400         __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1401         __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1402         bool encap_pkt = false;
1403 
1404         skb_checksum_none_assert(skb);
1405 
1406         /* Rx csum disabled */
1407         if (!(ring->netdev->features & NETIF_F_RXCSUM))
1408                 return;
1409 
1410         if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) &&
1411             (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) {
1412                 encap_pkt = true;
1413                 skb->encapsulation = 1;
1414                 skb->ip_summed = CHECKSUM_NONE;
1415         }
1416 
1417         /* if IP and error */
1418         if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1419             ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1420                 ring->rx_stats.csum_err++;
1421                 return;
1422         }
1423 
1424         if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1425                 return;
1426 
1427         if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1428                 /*
1429                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1430                  * checksum errors.
1431                  */
1432                 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1433                     test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1434                         return;
1435 
1436                 ring->rx_stats.csum_err++;
1437                 return;
1438         }
1439 
1440         /* It must be a TCP or UDP packet with a valid checksum */
1441         skb->ip_summed = CHECKSUM_UNNECESSARY;
1442         if (encap_pkt) {
1443                 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1444                         return;
1445 
1446                 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
1447                         ring->rx_stats.csum_err++;
1448                         return;
1449                 }
1450                 /* If we checked the outer header let the stack know */
1451                 skb->csum_level = 1;
1452         }
1453 }
1454 
1455 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1456                                     struct ixgbe_rx_buffer *bi)
1457 {
1458         struct page *page = bi->page;
1459         dma_addr_t dma;
1460 
1461         /* since we are recycling buffers we should seldom need to alloc */
1462         if (likely(page))
1463                 return true;
1464 
1465         /* alloc new page for storage */
1466         page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1467         if (unlikely(!page)) {
1468                 rx_ring->rx_stats.alloc_rx_page_failed++;
1469                 return false;
1470         }
1471 
1472         /* map page for use */
1473         dma = dma_map_page(rx_ring->dev, page, 0,
1474                            ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1475 
1476         /*
1477          * if mapping failed free memory back to system since
1478          * there isn't much point in holding memory we can't use
1479          */
1480         if (dma_mapping_error(rx_ring->dev, dma)) {
1481                 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1482 
1483                 rx_ring->rx_stats.alloc_rx_page_failed++;
1484                 return false;
1485         }
1486 
1487         bi->dma = dma;
1488         bi->page = page;
1489         bi->page_offset = 0;
1490 
1491         return true;
1492 }
1493 
1494 /**
1495  * ixgbe_alloc_rx_buffers - Replace used receive buffers
1496  * @rx_ring: ring to place buffers on
1497  * @cleaned_count: number of buffers to replace
1498  **/
1499 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1500 {
1501         union ixgbe_adv_rx_desc *rx_desc;
1502         struct ixgbe_rx_buffer *bi;
1503         u16 i = rx_ring->next_to_use;
1504 
1505         /* nothing to do */
1506         if (!cleaned_count)
1507                 return;
1508 
1509         rx_desc = IXGBE_RX_DESC(rx_ring, i);
1510         bi = &rx_ring->rx_buffer_info[i];
1511         i -= rx_ring->count;
1512 
1513         do {
1514                 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1515                         break;
1516 
1517                 /*
1518                  * Refresh the desc even if buffer_addrs didn't change
1519                  * because each write-back erases this info.
1520                  */
1521                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1522 
1523                 rx_desc++;
1524                 bi++;
1525                 i++;
1526                 if (unlikely(!i)) {
1527                         rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1528                         bi = rx_ring->rx_buffer_info;
1529                         i -= rx_ring->count;
1530                 }
1531 
1532                 /* clear the status bits for the next_to_use descriptor */
1533                 rx_desc->wb.upper.status_error = 0;
1534 
1535                 cleaned_count--;
1536         } while (cleaned_count);
1537 
1538         i += rx_ring->count;
1539 
1540         if (rx_ring->next_to_use != i) {
1541                 rx_ring->next_to_use = i;
1542 
1543                 /* update next to alloc since we have filled the ring */
1544                 rx_ring->next_to_alloc = i;
1545 
1546                 /* Force memory writes to complete before letting h/w
1547                  * know there are new descriptors to fetch.  (Only
1548                  * applicable for weak-ordered memory model archs,
1549                  * such as IA-64).
1550                  */
1551                 wmb();
1552                 writel(i, rx_ring->tail);
1553         }
1554 }
1555 
1556 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1557                                    struct sk_buff *skb)
1558 {
1559         u16 hdr_len = skb_headlen(skb);
1560 
1561         /* set gso_size to avoid messing up TCP MSS */
1562         skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1563                                                  IXGBE_CB(skb)->append_cnt);
1564         skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1565 }
1566 
1567 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1568                                    struct sk_buff *skb)
1569 {
1570         /* if append_cnt is 0 then frame is not RSC */
1571         if (!IXGBE_CB(skb)->append_cnt)
1572                 return;
1573 
1574         rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1575         rx_ring->rx_stats.rsc_flush++;
1576 
1577         ixgbe_set_rsc_gso_size(rx_ring, skb);
1578 
1579         /* gso_size is computed using append_cnt so always clear it last */
1580         IXGBE_CB(skb)->append_cnt = 0;
1581 }
1582 
1583 /**
1584  * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1585  * @rx_ring: rx descriptor ring packet is being transacted on
1586  * @rx_desc: pointer to the EOP Rx descriptor
1587  * @skb: pointer to current skb being populated
1588  *
1589  * This function checks the ring, descriptor, and packet information in
1590  * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1591  * other fields within the skb.
1592  **/
1593 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1594                                      union ixgbe_adv_rx_desc *rx_desc,
1595                                      struct sk_buff *skb)
1596 {
1597         struct net_device *dev = rx_ring->netdev;
1598 
1599         ixgbe_update_rsc_stats(rx_ring, skb);
1600 
1601         ixgbe_rx_hash(rx_ring, rx_desc, skb);
1602 
1603         ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1604 
1605         if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
1606                 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb);
1607 
1608         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1609             ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1610                 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1611                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1612         }
1613 
1614         skb_record_rx_queue(skb, rx_ring->queue_index);
1615 
1616         skb->protocol = eth_type_trans(skb, dev);
1617 }
1618 
1619 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1620                          struct sk_buff *skb)
1621 {
1622         struct ixgbe_adapter *adapter = q_vector->adapter;
1623 
1624         if (ixgbe_qv_busy_polling(q_vector))
1625                 netif_receive_skb(skb);
1626         else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1627                 napi_gro_receive(&q_vector->napi, skb);
1628         else
1629                 netif_rx(skb);
1630 }
1631 
1632 /**
1633  * ixgbe_is_non_eop - process handling of non-EOP buffers
1634  * @rx_ring: Rx ring being processed
1635  * @rx_desc: Rx descriptor for current buffer
1636  * @skb: Current socket buffer containing buffer in progress
1637  *
1638  * This function updates next to clean.  If the buffer is an EOP buffer
1639  * this function exits returning false, otherwise it will place the
1640  * sk_buff in the next buffer to be chained and return true indicating
1641  * that this is in fact a non-EOP buffer.
1642  **/
1643 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1644                              union ixgbe_adv_rx_desc *rx_desc,
1645                              struct sk_buff *skb)
1646 {
1647         u32 ntc = rx_ring->next_to_clean + 1;
1648 
1649         /* fetch, update, and store next to clean */
1650         ntc = (ntc < rx_ring->count) ? ntc : 0;
1651         rx_ring->next_to_clean = ntc;
1652 
1653         prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1654 
1655         /* update RSC append count if present */
1656         if (ring_is_rsc_enabled(rx_ring)) {
1657                 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1658                                      cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1659 
1660                 if (unlikely(rsc_enabled)) {
1661                         u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1662 
1663                         rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1664                         IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1665 
1666                         /* update ntc based on RSC value */
1667                         ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1668                         ntc &= IXGBE_RXDADV_NEXTP_MASK;
1669                         ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1670                 }
1671         }
1672 
1673         /* if we are the last buffer then there is nothing else to do */
1674         if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1675                 return false;
1676 
1677         /* place skb in next buffer to be received */
1678         rx_ring->rx_buffer_info[ntc].skb = skb;
1679         rx_ring->rx_stats.non_eop_descs++;
1680 
1681         return true;
1682 }
1683 
1684 /**
1685  * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1686  * @rx_ring: rx descriptor ring packet is being transacted on
1687  * @skb: pointer to current skb being adjusted
1688  *
1689  * This function is an ixgbe specific version of __pskb_pull_tail.  The
1690  * main difference between this version and the original function is that
1691  * this function can make several assumptions about the state of things
1692  * that allow for significant optimizations versus the standard function.
1693  * As a result we can do things like drop a frag and maintain an accurate
1694  * truesize for the skb.
1695  */
1696 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1697                             struct sk_buff *skb)
1698 {
1699         struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1700         unsigned char *va;
1701         unsigned int pull_len;
1702 
1703         /*
1704          * it is valid to use page_address instead of kmap since we are
1705          * working with pages allocated out of the lomem pool per
1706          * alloc_page(GFP_ATOMIC)
1707          */
1708         va = skb_frag_address(frag);
1709 
1710         /*
1711          * we need the header to contain the greater of either ETH_HLEN or
1712          * 60 bytes if the skb->len is less than 60 for skb_pad.
1713          */
1714         pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
1715 
1716         /* align pull length to size of long to optimize memcpy performance */
1717         skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1718 
1719         /* update all of the pointers */
1720         skb_frag_size_sub(frag, pull_len);
1721         frag->page_offset += pull_len;
1722         skb->data_len -= pull_len;
1723         skb->tail += pull_len;
1724 }
1725 
1726 /**
1727  * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1728  * @rx_ring: rx descriptor ring packet is being transacted on
1729  * @skb: pointer to current skb being updated
1730  *
1731  * This function provides a basic DMA sync up for the first fragment of an
1732  * skb.  The reason for doing this is that the first fragment cannot be
1733  * unmapped until we have reached the end of packet descriptor for a buffer
1734  * chain.
1735  */
1736 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1737                                 struct sk_buff *skb)
1738 {
1739         /* if the page was released unmap it, else just sync our portion */
1740         if (unlikely(IXGBE_CB(skb)->page_released)) {
1741                 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1742                                ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1743                 IXGBE_CB(skb)->page_released = false;
1744         } else {
1745                 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1746 
1747                 dma_sync_single_range_for_cpu(rx_ring->dev,
1748                                               IXGBE_CB(skb)->dma,
1749                                               frag->page_offset,
1750                                               ixgbe_rx_bufsz(rx_ring),
1751                                               DMA_FROM_DEVICE);
1752         }
1753         IXGBE_CB(skb)->dma = 0;
1754 }
1755 
1756 /**
1757  * ixgbe_cleanup_headers - Correct corrupted or empty headers
1758  * @rx_ring: rx descriptor ring packet is being transacted on
1759  * @rx_desc: pointer to the EOP Rx descriptor
1760  * @skb: pointer to current skb being fixed
1761  *
1762  * Check for corrupted packet headers caused by senders on the local L2
1763  * embedded NIC switch not setting up their Tx Descriptors right.  These
1764  * should be very rare.
1765  *
1766  * Also address the case where we are pulling data in on pages only
1767  * and as such no data is present in the skb header.
1768  *
1769  * In addition if skb is not at least 60 bytes we need to pad it so that
1770  * it is large enough to qualify as a valid Ethernet frame.
1771  *
1772  * Returns true if an error was encountered and skb was freed.
1773  **/
1774 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1775                                   union ixgbe_adv_rx_desc *rx_desc,
1776                                   struct sk_buff *skb)
1777 {
1778         struct net_device *netdev = rx_ring->netdev;
1779 
1780         /* verify that the packet does not have any known errors */
1781         if (unlikely(ixgbe_test_staterr(rx_desc,
1782                                         IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1783             !(netdev->features & NETIF_F_RXALL))) {
1784                 dev_kfree_skb_any(skb);
1785                 return true;
1786         }
1787 
1788         /* place header in linear portion of buffer */
1789         if (skb_is_nonlinear(skb))
1790                 ixgbe_pull_tail(rx_ring, skb);
1791 
1792 #ifdef IXGBE_FCOE
1793         /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1794         if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1795                 return false;
1796 
1797 #endif
1798         /* if eth_skb_pad returns an error the skb was freed */
1799         if (eth_skb_pad(skb))
1800                 return true;
1801 
1802         return false;
1803 }
1804 
1805 /**
1806  * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1807  * @rx_ring: rx descriptor ring to store buffers on
1808  * @old_buff: donor buffer to have page reused
1809  *
1810  * Synchronizes page for reuse by the adapter
1811  **/
1812 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1813                                 struct ixgbe_rx_buffer *old_buff)
1814 {
1815         struct ixgbe_rx_buffer *new_buff;
1816         u16 nta = rx_ring->next_to_alloc;
1817 
1818         new_buff = &rx_ring->rx_buffer_info[nta];
1819 
1820         /* update, and store next to alloc */
1821         nta++;
1822         rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1823 
1824         /* transfer page from old buffer to new buffer */
1825         *new_buff = *old_buff;
1826 
1827         /* sync the buffer for use by the device */
1828         dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1829                                          new_buff->page_offset,
1830                                          ixgbe_rx_bufsz(rx_ring),
1831                                          DMA_FROM_DEVICE);
1832 }
1833 
1834 static inline bool ixgbe_page_is_reserved(struct page *page)
1835 {
1836         return (page_to_nid(page) != numa_mem_id()) || page->pfmemalloc;
1837 }
1838 
1839 /**
1840  * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1841  * @rx_ring: rx descriptor ring to transact packets on
1842  * @rx_buffer: buffer containing page to add
1843  * @rx_desc: descriptor containing length of buffer written by hardware
1844  * @skb: sk_buff to place the data into
1845  *
1846  * This function will add the data contained in rx_buffer->page to the skb.
1847  * This is done either through a direct copy if the data in the buffer is
1848  * less than the skb header size, otherwise it will just attach the page as
1849  * a frag to the skb.
1850  *
1851  * The function will then update the page offset if necessary and return
1852  * true if the buffer can be reused by the adapter.
1853  **/
1854 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1855                               struct ixgbe_rx_buffer *rx_buffer,
1856                               union ixgbe_adv_rx_desc *rx_desc,
1857                               struct sk_buff *skb)
1858 {
1859         struct page *page = rx_buffer->page;
1860         unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1861 #if (PAGE_SIZE < 8192)
1862         unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1863 #else
1864         unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1865         unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1866                                    ixgbe_rx_bufsz(rx_ring);
1867 #endif
1868 
1869         if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1870                 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1871 
1872                 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1873 
1874                 /* page is not reserved, we can reuse buffer as-is */
1875                 if (likely(!ixgbe_page_is_reserved(page)))
1876                         return true;
1877 
1878                 /* this page cannot be reused so discard it */
1879                 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1880                 return false;
1881         }
1882 
1883         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1884                         rx_buffer->page_offset, size, truesize);
1885 
1886         /* avoid re-using remote pages */
1887         if (unlikely(ixgbe_page_is_reserved(page)))
1888                 return false;
1889 
1890 #if (PAGE_SIZE < 8192)
1891         /* if we are only owner of page we can reuse it */
1892         if (unlikely(page_count(page) != 1))
1893                 return false;
1894 
1895         /* flip page offset to other buffer */
1896         rx_buffer->page_offset ^= truesize;
1897 #else
1898         /* move offset up to the next cache line */
1899         rx_buffer->page_offset += truesize;
1900 
1901         if (rx_buffer->page_offset > last_offset)
1902                 return false;
1903 #endif
1904 
1905         /* Even if we own the page, we are not allowed to use atomic_set()
1906          * This would break get_page_unless_zero() users.
1907          */
1908         atomic_inc(&page->_count);
1909 
1910         return true;
1911 }
1912 
1913 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1914                                              union ixgbe_adv_rx_desc *rx_desc)
1915 {
1916         struct ixgbe_rx_buffer *rx_buffer;
1917         struct sk_buff *skb;
1918         struct page *page;
1919 
1920         rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1921         page = rx_buffer->page;
1922         prefetchw(page);
1923 
1924         skb = rx_buffer->skb;
1925 
1926         if (likely(!skb)) {
1927                 void *page_addr = page_address(page) +
1928                                   rx_buffer->page_offset;
1929 
1930                 /* prefetch first cache line of first page */
1931                 prefetch(page_addr);
1932 #if L1_CACHE_BYTES < 128
1933                 prefetch(page_addr + L1_CACHE_BYTES);
1934 #endif
1935 
1936                 /* allocate a skb to store the frags */
1937                 skb = napi_alloc_skb(&rx_ring->q_vector->napi,
1938                                      IXGBE_RX_HDR_SIZE);
1939                 if (unlikely(!skb)) {
1940                         rx_ring->rx_stats.alloc_rx_buff_failed++;
1941                         return NULL;
1942                 }
1943 
1944                 /*
1945                  * we will be copying header into skb->data in
1946                  * pskb_may_pull so it is in our interest to prefetch
1947                  * it now to avoid a possible cache miss
1948                  */
1949                 prefetchw(skb->data);
1950 
1951                 /*
1952                  * Delay unmapping of the first packet. It carries the
1953                  * header information, HW may still access the header
1954                  * after the writeback.  Only unmap it when EOP is
1955                  * reached
1956                  */
1957                 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1958                         goto dma_sync;
1959 
1960                 IXGBE_CB(skb)->dma = rx_buffer->dma;
1961         } else {
1962                 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1963                         ixgbe_dma_sync_frag(rx_ring, skb);
1964 
1965 dma_sync:
1966                 /* we are reusing so sync this buffer for CPU use */
1967                 dma_sync_single_range_for_cpu(rx_ring->dev,
1968                                               rx_buffer->dma,
1969                                               rx_buffer->page_offset,
1970                                               ixgbe_rx_bufsz(rx_ring),
1971                                               DMA_FROM_DEVICE);
1972 
1973                 rx_buffer->skb = NULL;
1974         }
1975 
1976         /* pull page into skb */
1977         if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1978                 /* hand second half of page back to the ring */
1979                 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1980         } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1981                 /* the page has been released from the ring */
1982                 IXGBE_CB(skb)->page_released = true;
1983         } else {
1984                 /* we are not reusing the buffer so unmap it */
1985                 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1986                                ixgbe_rx_pg_size(rx_ring),
1987                                DMA_FROM_DEVICE);
1988         }
1989 
1990         /* clear contents of buffer_info */
1991         rx_buffer->page = NULL;
1992 
1993         return skb;
1994 }
1995 
1996 /**
1997  * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1998  * @q_vector: structure containing interrupt and ring information
1999  * @rx_ring: rx descriptor ring to transact packets on
2000  * @budget: Total limit on number of packets to process
2001  *
2002  * This function provides a "bounce buffer" approach to Rx interrupt
2003  * processing.  The advantage to this is that on systems that have
2004  * expensive overhead for IOMMU access this provides a means of avoiding
2005  * it by maintaining the mapping of the page to the syste.
2006  *
2007  * Returns amount of work completed
2008  **/
2009 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
2010                                struct ixgbe_ring *rx_ring,
2011                                const int budget)
2012 {
2013         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
2014 #ifdef IXGBE_FCOE
2015         struct ixgbe_adapter *adapter = q_vector->adapter;
2016         int ddp_bytes;
2017         unsigned int mss = 0;
2018 #endif /* IXGBE_FCOE */
2019         u16 cleaned_count = ixgbe_desc_unused(rx_ring);
2020 
2021         while (likely(total_rx_packets < budget)) {
2022                 union ixgbe_adv_rx_desc *rx_desc;
2023                 struct sk_buff *skb;
2024 
2025                 /* return some buffers to hardware, one at a time is too slow */
2026                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2027                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2028                         cleaned_count = 0;
2029                 }
2030 
2031                 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
2032 
2033                 if (!rx_desc->wb.upper.status_error)
2034                         break;
2035 
2036                 /* This memory barrier is needed to keep us from reading
2037                  * any other fields out of the rx_desc until we know the
2038                  * descriptor has been written back
2039                  */
2040                 dma_rmb();
2041 
2042                 /* retrieve a buffer from the ring */
2043                 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
2044 
2045                 /* exit if we failed to retrieve a buffer */
2046                 if (!skb)
2047                         break;
2048 
2049                 cleaned_count++;
2050 
2051                 /* place incomplete frames back on ring for completion */
2052                 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2053                         continue;
2054 
2055                 /* verify the packet layout is correct */
2056                 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2057                         continue;
2058 
2059                 /* probably a little skewed due to removing CRC */
2060                 total_rx_bytes += skb->len;
2061 
2062                 /* populate checksum, timestamp, VLAN, and protocol */
2063                 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2064 
2065 #ifdef IXGBE_FCOE
2066                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
2067                 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
2068                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
2069                         /* include DDPed FCoE data */
2070                         if (ddp_bytes > 0) {
2071                                 if (!mss) {
2072                                         mss = rx_ring->netdev->mtu -
2073                                                 sizeof(struct fcoe_hdr) -
2074                                                 sizeof(struct fc_frame_header) -
2075                                                 sizeof(struct fcoe_crc_eof);
2076                                         if (mss > 512)
2077                                                 mss &= ~511;
2078                                 }
2079                                 total_rx_bytes += ddp_bytes;
2080                                 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2081                                                                  mss);
2082                         }
2083                         if (!ddp_bytes) {
2084                                 dev_kfree_skb_any(skb);
2085                                 continue;
2086                         }
2087                 }
2088 
2089 #endif /* IXGBE_FCOE */
2090                 skb_mark_napi_id(skb, &q_vector->napi);
2091                 ixgbe_rx_skb(q_vector, skb);
2092 
2093                 /* update budget accounting */
2094                 total_rx_packets++;
2095         }
2096 
2097         u64_stats_update_begin(&rx_ring->syncp);
2098         rx_ring->stats.packets += total_rx_packets;
2099         rx_ring->stats.bytes += total_rx_bytes;
2100         u64_stats_update_end(&rx_ring->syncp);
2101         q_vector->rx.total_packets += total_rx_packets;
2102         q_vector->rx.total_bytes += total_rx_bytes;
2103 
2104         return total_rx_packets;
2105 }
2106 
2107 #ifdef CONFIG_NET_RX_BUSY_POLL
2108 /* must be called with local_bh_disable()d */
2109 static int ixgbe_low_latency_recv(struct napi_struct *napi)
2110 {
2111         struct ixgbe_q_vector *q_vector =
2112                         container_of(napi, struct ixgbe_q_vector, napi);
2113         struct ixgbe_adapter *adapter = q_vector->adapter;
2114         struct ixgbe_ring  *ring;
2115         int found = 0;
2116 
2117         if (test_bit(__IXGBE_DOWN, &adapter->state))
2118                 return LL_FLUSH_FAILED;
2119 
2120         if (!ixgbe_qv_lock_poll(q_vector))
2121                 return LL_FLUSH_BUSY;
2122 
2123         ixgbe_for_each_ring(ring, q_vector->rx) {
2124                 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
2125 #ifdef BP_EXTENDED_STATS
2126                 if (found)
2127                         ring->stats.cleaned += found;
2128                 else
2129                         ring->stats.misses++;
2130 #endif
2131                 if (found)
2132                         break;
2133         }
2134 
2135         ixgbe_qv_unlock_poll(q_vector);
2136 
2137         return found;
2138 }
2139 #endif  /* CONFIG_NET_RX_BUSY_POLL */
2140 
2141 /**
2142  * ixgbe_configure_msix - Configure MSI-X hardware
2143  * @adapter: board private structure
2144  *
2145  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2146  * interrupts.
2147  **/
2148 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2149 {
2150         struct ixgbe_q_vector *q_vector;
2151         int v_idx;
2152         u32 mask;
2153 
2154         /* Populate MSIX to EITR Select */
2155         if (adapter->num_vfs > 32) {
2156                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2157                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2158         }
2159 
2160         /*
2161          * Populate the IVAR table and set the ITR values to the
2162          * corresponding register.
2163          */
2164         for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2165                 struct ixgbe_ring *ring;
2166                 q_vector = adapter->q_vector[v_idx];
2167 
2168                 ixgbe_for_each_ring(ring, q_vector->rx)
2169                         ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2170 
2171                 ixgbe_for_each_ring(ring, q_vector->tx)
2172                         ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2173 
2174                 ixgbe_write_eitr(q_vector);
2175         }
2176 
2177         switch (adapter->hw.mac.type) {
2178         case ixgbe_mac_82598EB:
2179                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2180                                v_idx);
2181                 break;
2182         case ixgbe_mac_82599EB:
2183         case ixgbe_mac_X540:
2184         case ixgbe_mac_X550:
2185         case ixgbe_mac_X550EM_x:
2186                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
2187                 break;
2188         default:
2189                 break;
2190         }
2191         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2192 
2193         /* set up to autoclear timer, and the vectors */
2194         mask = IXGBE_EIMS_ENABLE_MASK;
2195         mask &= ~(IXGBE_EIMS_OTHER |
2196                   IXGBE_EIMS_MAILBOX |
2197                   IXGBE_EIMS_LSC);
2198 
2199         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2200 }
2201 
2202 enum latency_range {
2203         lowest_latency = 0,
2204         low_latency = 1,
2205         bulk_latency = 2,
2206         latency_invalid = 255
2207 };
2208 
2209 /**
2210  * ixgbe_update_itr - update the dynamic ITR value based on statistics
2211  * @q_vector: structure containing interrupt and ring information
2212  * @ring_container: structure containing ring performance data
2213  *
2214  *      Stores a new ITR value based on packets and byte
2215  *      counts during the last interrupt.  The advantage of per interrupt
2216  *      computation is faster updates and more accurate ITR for the current
2217  *      traffic pattern.  Constants in this function were computed
2218  *      based on theoretical maximum wire speed and thresholds were set based
2219  *      on testing data as well as attempting to minimize response time
2220  *      while increasing bulk throughput.
2221  *      this functionality is controlled by the InterruptThrottleRate module
2222  *      parameter (see ixgbe_param.c)
2223  **/
2224 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2225                              struct ixgbe_ring_container *ring_container)
2226 {
2227         int bytes = ring_container->total_bytes;
2228         int packets = ring_container->total_packets;
2229         u32 timepassed_us;
2230         u64 bytes_perint;
2231         u8 itr_setting = ring_container->itr;
2232 
2233         if (packets == 0)
2234                 return;
2235 
2236         /* simple throttlerate management
2237          *   0-10MB/s   lowest (100000 ints/s)
2238          *  10-20MB/s   low    (20000 ints/s)
2239          *  20-1249MB/s bulk   (8000 ints/s)
2240          */
2241         /* what was last interrupt timeslice? */
2242         timepassed_us = q_vector->itr >> 2;
2243         if (timepassed_us == 0)
2244                 return;
2245 
2246         bytes_perint = bytes / timepassed_us; /* bytes/usec */
2247 
2248         switch (itr_setting) {
2249         case lowest_latency:
2250                 if (bytes_perint > 10)
2251                         itr_setting = low_latency;
2252                 break;
2253         case low_latency:
2254                 if (bytes_perint > 20)
2255                         itr_setting = bulk_latency;
2256                 else if (bytes_perint <= 10)
2257                         itr_setting = lowest_latency;
2258                 break;
2259         case bulk_latency:
2260                 if (bytes_perint <= 20)
2261                         itr_setting = low_latency;
2262                 break;
2263         }
2264 
2265         /* clear work counters since we have the values we need */
2266         ring_container->total_bytes = 0;
2267         ring_container->total_packets = 0;
2268 
2269         /* write updated itr to ring container */
2270         ring_container->itr = itr_setting;
2271 }
2272 
2273 /**
2274  * ixgbe_write_eitr - write EITR register in hardware specific way
2275  * @q_vector: structure containing interrupt and ring information
2276  *
2277  * This function is made to be called by ethtool and by the driver
2278  * when it needs to update EITR registers at runtime.  Hardware
2279  * specific quirks/differences are taken care of here.
2280  */
2281 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2282 {
2283         struct ixgbe_adapter *adapter = q_vector->adapter;
2284         struct ixgbe_hw *hw = &adapter->hw;
2285         int v_idx = q_vector->v_idx;
2286         u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2287 
2288         switch (adapter->hw.mac.type) {
2289         case ixgbe_mac_82598EB:
2290                 /* must write high and low 16 bits to reset counter */
2291                 itr_reg |= (itr_reg << 16);
2292                 break;
2293         case ixgbe_mac_82599EB:
2294         case ixgbe_mac_X540:
2295         case ixgbe_mac_X550:
2296         case ixgbe_mac_X550EM_x:
2297                 /*
2298                  * set the WDIS bit to not clear the timer bits and cause an
2299                  * immediate assertion of the interrupt
2300                  */
2301                 itr_reg |= IXGBE_EITR_CNT_WDIS;
2302                 break;
2303         default:
2304                 break;
2305         }
2306         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2307 }
2308 
2309 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2310 {
2311         u32 new_itr = q_vector->itr;
2312         u8 current_itr;
2313 
2314         ixgbe_update_itr(q_vector, &q_vector->tx);
2315         ixgbe_update_itr(q_vector, &q_vector->rx);
2316 
2317         current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2318 
2319         switch (current_itr) {
2320         /* counts and packets in update_itr are dependent on these numbers */
2321         case lowest_latency:
2322                 new_itr = IXGBE_100K_ITR;
2323                 break;
2324         case low_latency:
2325                 new_itr = IXGBE_20K_ITR;
2326                 break;
2327         case bulk_latency:
2328                 new_itr = IXGBE_8K_ITR;
2329                 break;
2330         default:
2331                 break;
2332         }
2333 
2334         if (new_itr != q_vector->itr) {
2335                 /* do an exponential smoothing */
2336                 new_itr = (10 * new_itr * q_vector->itr) /
2337                           ((9 * new_itr) + q_vector->itr);
2338 
2339                 /* save the algorithm value here */
2340                 q_vector->itr = new_itr;
2341 
2342                 ixgbe_write_eitr(q_vector);
2343         }
2344 }
2345 
2346 /**
2347  * ixgbe_check_overtemp_subtask - check for over temperature
2348  * @adapter: pointer to adapter
2349  **/
2350 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2351 {
2352         struct ixgbe_hw *hw = &adapter->hw;
2353         u32 eicr = adapter->interrupt_event;
2354 
2355         if (test_bit(__IXGBE_DOWN, &adapter->state))
2356                 return;
2357 
2358         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2359             !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2360                 return;
2361 
2362         adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2363 
2364         switch (hw->device_id) {
2365         case IXGBE_DEV_ID_82599_T3_LOM:
2366                 /*
2367                  * Since the warning interrupt is for both ports
2368                  * we don't have to check if:
2369                  *  - This interrupt wasn't for our port.
2370                  *  - We may have missed the interrupt so always have to
2371                  *    check if we  got a LSC
2372                  */
2373                 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2374                     !(eicr & IXGBE_EICR_LSC))
2375                         return;
2376 
2377                 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2378                         u32 speed;
2379                         bool link_up = false;
2380 
2381                         hw->mac.ops.check_link(hw, &speed, &link_up, false);
2382 
2383                         if (link_up)
2384                                 return;
2385                 }
2386 
2387                 /* Check if this is not due to overtemp */
2388                 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2389                         return;
2390 
2391                 break;
2392         default:
2393                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2394                         return;
2395                 break;
2396         }
2397         e_crit(drv,
2398                "Network adapter has been stopped because it has over heated. "
2399                "Restart the computer. If the problem persists, "
2400                "power off the system and replace the adapter\n");
2401 
2402         adapter->interrupt_event = 0;
2403 }
2404 
2405 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2406 {
2407         struct ixgbe_hw *hw = &adapter->hw;
2408 
2409         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2410             (eicr & IXGBE_EICR_GPI_SDP1)) {
2411                 e_crit(probe, "Fan has stopped, replace the adapter\n");
2412                 /* write to clear the interrupt */
2413                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2414         }
2415 }
2416 
2417 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2418 {
2419         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2420                 return;
2421 
2422         switch (adapter->hw.mac.type) {
2423         case ixgbe_mac_82599EB:
2424                 /*
2425                  * Need to check link state so complete overtemp check
2426                  * on service task
2427                  */
2428                 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2429                     (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2430                         adapter->interrupt_event = eicr;
2431                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2432                         ixgbe_service_event_schedule(adapter);
2433                         return;
2434                 }
2435                 return;
2436         case ixgbe_mac_X540:
2437                 if (!(eicr & IXGBE_EICR_TS))
2438                         return;
2439                 break;
2440         default:
2441                 return;
2442         }
2443 
2444         e_crit(drv,
2445                "Network adapter has been stopped because it has over heated. "
2446                "Restart the computer. If the problem persists, "
2447                "power off the system and replace the adapter\n");
2448 }
2449 
2450 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2451 {
2452         struct ixgbe_hw *hw = &adapter->hw;
2453 
2454         if (eicr & IXGBE_EICR_GPI_SDP2) {
2455                 /* Clear the interrupt */
2456                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2457                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2458                         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2459                         ixgbe_service_event_schedule(adapter);
2460                 }
2461         }
2462 
2463         if (eicr & IXGBE_EICR_GPI_SDP1) {
2464                 /* Clear the interrupt */
2465                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2466                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2467                         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2468                         ixgbe_service_event_schedule(adapter);
2469                 }
2470         }
2471 }
2472 
2473 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2474 {
2475         struct ixgbe_hw *hw = &adapter->hw;
2476 
2477         adapter->lsc_int++;
2478         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2479         adapter->link_check_timeout = jiffies;
2480         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2481                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2482                 IXGBE_WRITE_FLUSH(hw);
2483                 ixgbe_service_event_schedule(adapter);
2484         }
2485 }
2486 
2487 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2488                                            u64 qmask)
2489 {
2490         u32 mask;
2491         struct ixgbe_hw *hw = &adapter->hw;
2492 
2493         switch (hw->mac.type) {
2494         case ixgbe_mac_82598EB:
2495                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2496                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2497                 break;
2498         case ixgbe_mac_82599EB:
2499         case ixgbe_mac_X540:
2500         case ixgbe_mac_X550:
2501         case ixgbe_mac_X550EM_x:
2502                 mask = (qmask & 0xFFFFFFFF);
2503                 if (mask)
2504                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2505                 mask = (qmask >> 32);
2506                 if (mask)
2507                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2508                 break;
2509         default:
2510                 break;
2511         }
2512         /* skip the flush */
2513 }
2514 
2515 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2516                                             u64 qmask)
2517 {
2518         u32 mask;
2519         struct ixgbe_hw *hw = &adapter->hw;
2520 
2521         switch (hw->mac.type) {
2522         case ixgbe_mac_82598EB:
2523                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2524                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2525                 break;
2526         case ixgbe_mac_82599EB:
2527         case ixgbe_mac_X540:
2528         case ixgbe_mac_X550:
2529         case ixgbe_mac_X550EM_x:
2530                 mask = (qmask & 0xFFFFFFFF);
2531                 if (mask)
2532                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2533                 mask = (qmask >> 32);
2534                 if (mask)
2535                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2536                 break;
2537         default:
2538                 break;
2539         }
2540         /* skip the flush */
2541 }
2542 
2543 /**
2544  * ixgbe_irq_enable - Enable default interrupt generation settings
2545  * @adapter: board private structure
2546  **/
2547 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2548                                     bool flush)
2549 {
2550         u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2551 
2552         /* don't reenable LSC while waiting for link */
2553         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2554                 mask &= ~IXGBE_EIMS_LSC;
2555 
2556         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2557                 switch (adapter->hw.mac.type) {
2558                 case ixgbe_mac_82599EB:
2559                         mask |= IXGBE_EIMS_GPI_SDP0;
2560                         break;
2561                 case ixgbe_mac_X540:
2562                 case ixgbe_mac_X550:
2563                 case ixgbe_mac_X550EM_x:
2564                         mask |= IXGBE_EIMS_TS;
2565                         break;
2566                 default:
2567                         break;
2568                 }
2569         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2570                 mask |= IXGBE_EIMS_GPI_SDP1;
2571         switch (adapter->hw.mac.type) {
2572         case ixgbe_mac_82599EB:
2573                 mask |= IXGBE_EIMS_GPI_SDP1;
2574                 mask |= IXGBE_EIMS_GPI_SDP2;
2575                 /* fall through */
2576         case ixgbe_mac_X540:
2577         case ixgbe_mac_X550:
2578         case ixgbe_mac_X550EM_x:
2579                 mask |= IXGBE_EIMS_ECC;
2580                 mask |= IXGBE_EIMS_MAILBOX;
2581                 break;
2582         default:
2583                 break;
2584         }
2585 
2586         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2587             !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2588                 mask |= IXGBE_EIMS_FLOW_DIR;
2589 
2590         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2591         if (queues)
2592                 ixgbe_irq_enable_queues(adapter, ~0);
2593         if (flush)
2594                 IXGBE_WRITE_FLUSH(&adapter->hw);
2595 }
2596 
2597 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2598 {
2599         struct ixgbe_adapter *adapter = data;
2600         struct ixgbe_hw *hw = &adapter->hw;
2601         u32 eicr;
2602 
2603         /*
2604          * Workaround for Silicon errata.  Use clear-by-write instead
2605          * of clear-by-read.  Reading with EICS will return the
2606          * interrupt causes without clearing, which later be done
2607          * with the write to EICR.
2608          */
2609         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2610 
2611         /* The lower 16bits of the EICR register are for the queue interrupts
2612          * which should be masked here in order to not accidently clear them if
2613          * the bits are high when ixgbe_msix_other is called. There is a race
2614          * condition otherwise which results in possible performance loss
2615          * especially if the ixgbe_msix_other interrupt is triggering
2616          * consistently (as it would when PPS is turned on for the X540 device)
2617          */
2618         eicr &= 0xFFFF0000;
2619 
2620         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2621 
2622         if (eicr & IXGBE_EICR_LSC)
2623                 ixgbe_check_lsc(adapter);
2624 
2625         if (eicr & IXGBE_EICR_MAILBOX)
2626                 ixgbe_msg_task(adapter);
2627 
2628         switch (hw->mac.type) {
2629         case ixgbe_mac_82599EB:
2630         case ixgbe_mac_X540:
2631         case ixgbe_mac_X550:
2632         case ixgbe_mac_X550EM_x:
2633                 if (eicr & IXGBE_EICR_ECC) {
2634                         e_info(link, "Received ECC Err, initiating reset\n");
2635                         adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2636                         ixgbe_service_event_schedule(adapter);
2637                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2638                 }
2639                 /* Handle Flow Director Full threshold interrupt */
2640                 if (eicr & IXGBE_EICR_FLOW_DIR) {
2641                         int reinit_count = 0;
2642                         int i;
2643                         for (i = 0; i < adapter->num_tx_queues; i++) {
2644                                 struct ixgbe_ring *ring = adapter->tx_ring[i];
2645                                 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2646                                                        &ring->state))
2647                                         reinit_count++;
2648                         }
2649                         if (reinit_count) {
2650                                 /* no more flow director interrupts until after init */
2651                                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2652                                 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2653                                 ixgbe_service_event_schedule(adapter);
2654                         }
2655                 }
2656                 ixgbe_check_sfp_event(adapter, eicr);
2657                 ixgbe_check_overtemp_event(adapter, eicr);
2658                 break;
2659         default:
2660                 break;
2661         }
2662 
2663         ixgbe_check_fan_failure(adapter, eicr);
2664 
2665         if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2666                 ixgbe_ptp_check_pps_event(adapter, eicr);
2667 
2668         /* re-enable the original interrupt state, no lsc, no queues */
2669         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2670                 ixgbe_irq_enable(adapter, false, false);
2671 
2672         return IRQ_HANDLED;
2673 }
2674 
2675 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2676 {
2677         struct ixgbe_q_vector *q_vector = data;
2678 
2679         /* EIAM disabled interrupts (on this vector) for us */
2680 
2681         if (q_vector->rx.ring || q_vector->tx.ring)
2682                 napi_schedule(&q_vector->napi);
2683 
2684         return IRQ_HANDLED;
2685 }
2686 
2687 /**
2688  * ixgbe_poll - NAPI Rx polling callback
2689  * @napi: structure for representing this polling device
2690  * @budget: how many packets driver is allowed to clean
2691  *
2692  * This function is used for legacy and MSI, NAPI mode
2693  **/
2694 int ixgbe_poll(struct napi_struct *napi, int budget)
2695 {
2696         struct ixgbe_q_vector *q_vector =
2697                                 container_of(napi, struct ixgbe_q_vector, napi);
2698         struct ixgbe_adapter *adapter = q_vector->adapter;
2699         struct ixgbe_ring *ring;
2700         int per_ring_budget;
2701         bool clean_complete = true;
2702 
2703 #ifdef CONFIG_IXGBE_DCA
2704         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2705                 ixgbe_update_dca(q_vector);
2706 #endif
2707 
2708         ixgbe_for_each_ring(ring, q_vector->tx)
2709                 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2710 
2711         if (!ixgbe_qv_lock_napi(q_vector))
2712                 return budget;
2713 
2714         /* attempt to distribute budget to each queue fairly, but don't allow
2715          * the budget to go below 1 because we'll exit polling */
2716         if (q_vector->rx.count > 1)
2717                 per_ring_budget = max(budget/q_vector->rx.count, 1);
2718         else
2719                 per_ring_budget = budget;
2720 
2721         ixgbe_for_each_ring(ring, q_vector->rx)
2722                 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2723                                    per_ring_budget) < per_ring_budget);
2724 
2725         ixgbe_qv_unlock_napi(q_vector);
2726         /* If all work not completed, return budget and keep polling */
2727         if (!clean_complete)
2728                 return budget;
2729 
2730         /* all work done, exit the polling mode */
2731         napi_complete(napi);
2732         if (adapter->rx_itr_setting & 1)
2733                 ixgbe_set_itr(q_vector);
2734         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2735                 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2736 
2737         return 0;
2738 }
2739 
2740 /**
2741  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2742  * @adapter: board private structure
2743  *
2744  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2745  * interrupts from the kernel.
2746  **/
2747 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2748 {
2749         struct net_device *netdev = adapter->netdev;
2750         int vector, err;
2751         int ri = 0, ti = 0;
2752 
2753         for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2754                 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2755                 struct msix_entry *entry = &adapter->msix_entries[vector];
2756 
2757                 if (q_vector->tx.ring && q_vector->rx.ring) {
2758                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2759                                  "%s-%s-%d", netdev->name, "TxRx", ri++);
2760                         ti++;
2761                 } else if (q_vector->rx.ring) {
2762                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2763                                  "%s-%s-%d", netdev->name, "rx", ri++);
2764                 } else if (q_vector->tx.ring) {
2765                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2766                                  "%s-%s-%d", netdev->name, "tx", ti++);
2767                 } else {
2768                         /* skip this unused q_vector */
2769                         continue;
2770                 }
2771                 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2772                                   q_vector->name, q_vector);
2773                 if (err) {
2774                         e_err(probe, "request_irq failed for MSIX interrupt "
2775                               "Error: %d\n", err);
2776                         goto free_queue_irqs;
2777                 }
2778                 /* If Flow Director is enabled, set interrupt affinity */
2779                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2780                         /* assign the mask for this irq */
2781                         irq_set_affinity_hint(entry->vector,
2782                                               &q_vector->affinity_mask);
2783                 }
2784         }
2785 
2786         err = request_irq(adapter->msix_entries[vector].vector,
2787                           ixgbe_msix_other, 0, netdev->name, adapter);
2788         if (err) {
2789                 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2790                 goto free_queue_irqs;
2791         }
2792 
2793         return 0;
2794 
2795 free_queue_irqs:
2796         while (vector) {
2797                 vector--;
2798                 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2799                                       NULL);
2800                 free_irq(adapter->msix_entries[vector].vector,
2801                          adapter->q_vector[vector]);
2802         }
2803         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2804         pci_disable_msix(adapter->pdev);
2805         kfree(adapter->msix_entries);
2806         adapter->msix_entries = NULL;
2807         return err;
2808 }
2809 
2810 /**
2811  * ixgbe_intr - legacy mode Interrupt Handler
2812  * @irq: interrupt number
2813  * @data: pointer to a network interface device structure
2814  **/
2815 static irqreturn_t ixgbe_intr(int irq, void *data)
2816 {
2817         struct ixgbe_adapter *adapter = data;
2818         struct ixgbe_hw *hw = &adapter->hw;
2819         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2820         u32 eicr;
2821 
2822         /*
2823          * Workaround for silicon errata #26 on 82598.  Mask the interrupt
2824          * before the read of EICR.
2825          */
2826         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2827 
2828         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2829          * therefore no explicit interrupt disable is necessary */
2830         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2831         if (!eicr) {
2832                 /*
2833                  * shared interrupt alert!
2834                  * make sure interrupts are enabled because the read will
2835                  * have disabled interrupts due to EIAM
2836                  * finish the workaround of silicon errata on 82598.  Unmask
2837                  * the interrupt that we masked before the EICR read.
2838                  */
2839                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2840                         ixgbe_irq_enable(adapter, true, true);
2841                 return IRQ_NONE;        /* Not our interrupt */
2842         }
2843 
2844         if (eicr & IXGBE_EICR_LSC)
2845                 ixgbe_check_lsc(adapter);
2846 
2847         switch (hw->mac.type) {
2848         case ixgbe_mac_82599EB:
2849                 ixgbe_check_sfp_event(adapter, eicr);
2850                 /* Fall through */
2851         case ixgbe_mac_X540:
2852         case ixgbe_mac_X550:
2853         case ixgbe_mac_X550EM_x:
2854                 if (eicr & IXGBE_EICR_ECC) {
2855                         e_info(link, "Received ECC Err, initiating reset\n");
2856                         adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2857                         ixgbe_service_event_schedule(adapter);
2858                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2859                 }
2860                 ixgbe_check_overtemp_event(adapter, eicr);
2861                 break;
2862         default:
2863                 break;
2864         }
2865 
2866         ixgbe_check_fan_failure(adapter, eicr);
2867         if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2868                 ixgbe_ptp_check_pps_event(adapter, eicr);
2869 
2870         /* would disable interrupts here but EIAM disabled it */
2871         napi_schedule(&q_vector->napi);
2872 
2873         /*
2874          * re-enable link(maybe) and non-queue interrupts, no flush.
2875          * ixgbe_poll will re-enable the queue interrupts
2876          */
2877         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2878                 ixgbe_irq_enable(adapter, false, false);
2879 
2880         return IRQ_HANDLED;
2881 }
2882 
2883 /**
2884  * ixgbe_request_irq - initialize interrupts
2885  * @adapter: board private structure
2886  *
2887  * Attempts to configure interrupts using the best available
2888  * capabilities of the hardware and kernel.
2889  **/
2890 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2891 {
2892         struct net_device *netdev = adapter->netdev;
2893         int err;
2894 
2895         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2896                 err = ixgbe_request_msix_irqs(adapter);
2897         else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2898                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2899                                   netdev->name, adapter);
2900         else
2901                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2902                                   netdev->name, adapter);
2903 
2904         if (err)
2905                 e_err(probe, "request_irq failed, Error %d\n", err);
2906 
2907         return err;
2908 }
2909 
2910 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2911 {
2912         int vector;
2913 
2914         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2915                 free_irq(adapter->pdev->irq, adapter);
2916                 return;
2917         }
2918 
2919         for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2920                 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2921                 struct msix_entry *entry = &adapter->msix_entries[vector];
2922 
2923                 /* free only the irqs that were actually requested */
2924                 if (!q_vector->rx.ring && !q_vector->tx.ring)
2925                         continue;
2926 
2927                 /* clear the affinity_mask in the IRQ descriptor */
2928                 irq_set_affinity_hint(entry->vector, NULL);
2929 
2930                 free_irq(entry->vector, q_vector);
2931         }
2932 
2933         free_irq(adapter->msix_entries[vector++].vector, adapter);
2934 }
2935 
2936 /**
2937  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2938  * @adapter: board private structure
2939  **/
2940 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2941 {
2942         switch (adapter->hw.mac.type) {
2943         case ixgbe_mac_82598EB:
2944                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2945                 break;
2946         case ixgbe_mac_82599EB:
2947         case ixgbe_mac_X540:
2948         case ixgbe_mac_X550:
2949         case ixgbe_mac_X550EM_x:
2950                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2951                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2952                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2953                 break;
2954         default:
2955                 break;
2956         }
2957         IXGBE_WRITE_FLUSH(&adapter->hw);
2958         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2959                 int vector;
2960 
2961                 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2962                         synchronize_irq(adapter->msix_entries[vector].vector);
2963 
2964                 synchronize_irq(adapter->msix_entries[vector++].vector);
2965         } else {
2966                 synchronize_irq(adapter->pdev->irq);
2967         }
2968 }
2969 
2970 /**
2971  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2972  *
2973  **/
2974 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2975 {
2976         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2977 
2978         ixgbe_write_eitr(q_vector);
2979 
2980         ixgbe_set_ivar(adapter, 0, 0, 0);
2981         ixgbe_set_ivar(adapter, 1, 0, 0);
2982 
2983         e_info(hw, "Legacy interrupt IVAR setup done\n");
2984 }
2985 
2986 /**
2987  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2988  * @adapter: board private structure
2989  * @ring: structure containing ring specific data
2990  *
2991  * Configure the Tx descriptor ring after a reset.
2992  **/
2993 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2994                              struct ixgbe_ring *ring)
2995 {
2996         struct ixgbe_hw *hw = &adapter->hw;
2997         u64 tdba = ring->dma;
2998         int wait_loop = 10;
2999         u32 txdctl = IXGBE_TXDCTL_ENABLE;
3000         u8 reg_idx = ring->reg_idx;
3001 
3002         /* disable queue to avoid issues while updating state */
3003         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
3004         IXGBE_WRITE_FLUSH(hw);
3005 
3006         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
3007                         (tdba & DMA_BIT_MASK(32)));
3008         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3009         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3010                         ring->count * sizeof(union ixgbe_adv_tx_desc));
3011         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3012         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
3013         ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
3014 
3015         /*
3016          * set WTHRESH to encourage burst writeback, it should not be set
3017          * higher than 1 when:
3018          * - ITR is 0 as it could cause false TX hangs
3019          * - ITR is set to > 100k int/sec and BQL is enabled
3020          *
3021          * In order to avoid issues WTHRESH + PTHRESH should always be equal
3022          * to or less than the number of on chip descriptors, which is
3023          * currently 40.
3024          */
3025         if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
3026                 txdctl |= (1 << 16);    /* WTHRESH = 1 */
3027         else
3028                 txdctl |= (8 << 16);    /* WTHRESH = 8 */
3029 
3030         /*
3031          * Setting PTHRESH to 32 both improves performance
3032          * and avoids a TX hang with DFP enabled
3033          */
3034         txdctl |= (1 << 8) |    /* HTHRESH = 1 */
3035                    32;          /* PTHRESH = 32 */
3036 
3037         /* reinitialize flowdirector state */
3038         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3039                 ring->atr_sample_rate = adapter->atr_sample_rate;
3040                 ring->atr_count = 0;
3041                 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3042         } else {
3043                 ring->atr_sample_rate = 0;
3044         }
3045 
3046         /* initialize XPS */
3047         if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3048                 struct ixgbe_q_vector *q_vector = ring->q_vector;
3049 
3050                 if (q_vector)
3051                         netif_set_xps_queue(ring->netdev,
3052                                             &q_vector->affinity_mask,
3053                                             ring->queue_index);
3054         }
3055 
3056         clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3057 
3058         /* enable queue */
3059         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3060 
3061         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3062         if (hw->mac.type == ixgbe_mac_82598EB &&
3063             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3064                 return;
3065 
3066         /* poll to verify queue is enabled */
3067         do {
3068                 usleep_range(1000, 2000);
3069                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3070         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3071         if (!wait_loop)
3072                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
3073 }
3074 
3075 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3076 {
3077         struct ixgbe_hw *hw = &adapter->hw;
3078         u32 rttdcs, mtqc;
3079         u8 tcs = netdev_get_num_tc(adapter->netdev);
3080 
3081         if (hw->mac.type == ixgbe_mac_82598EB)
3082                 return;
3083 
3084         /* disable the arbiter while setting MTQC */
3085         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3086         rttdcs |= IXGBE_RTTDCS_ARBDIS;
3087         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3088 
3089         /* set transmit pool layout */
3090         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3091                 mtqc = IXGBE_MTQC_VT_ENA;
3092                 if (tcs > 4)
3093                         mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3094                 else if (tcs > 1)
3095                         mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3096                 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3097                         mtqc |= IXGBE_MTQC_32VF;
3098                 else
3099                         mtqc |= IXGBE_MTQC_64VF;
3100         } else {
3101                 if (tcs > 4)
3102                         mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3103                 else if (tcs > 1)
3104                         mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3105                 else
3106                         mtqc = IXGBE_MTQC_64Q_1PB;
3107         }
3108 
3109         IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3110 
3111         /* Enable Security TX Buffer IFG for multiple pb */
3112         if (tcs) {
3113                 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3114                 sectx |= IXGBE_SECTX_DCB;
3115                 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
3116         }
3117 
3118         /* re-enable the arbiter */
3119         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3120         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3121 }
3122 
3123 /**
3124  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
3125  * @adapter: board private structure
3126  *
3127  * Configure the Tx unit of the MAC after a reset.
3128  **/
3129 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3130 {
3131         struct ixgbe_hw *hw = &adapter->hw;
3132         u32 dmatxctl;
3133         u32 i;
3134 
3135         ixgbe_setup_mtqc(adapter);
3136 
3137         if (hw->mac.type != ixgbe_mac_82598EB) {
3138                 /* DMATXCTL.EN must be before Tx queues are enabled */
3139                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3140                 dmatxctl |= IXGBE_DMATXCTL_TE;
3141                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3142         }
3143 
3144         /* Setup the HW Tx Head and Tail descriptor pointers */
3145         for (i = 0; i < adapter->num_tx_queues; i++)
3146                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
3147 }
3148 
3149 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3150                                  struct ixgbe_ring *ring)
3151 {
3152         struct ixgbe_hw *hw = &adapter->hw;
3153         u8 reg_idx = ring->reg_idx;
3154         u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3155 
3156         srrctl |= IXGBE_SRRCTL_DROP_EN;
3157 
3158         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3159 }
3160 
3161 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3162                                   struct ixgbe_ring *ring)
3163 {
3164         struct ixgbe_hw *hw = &adapter->hw;
3165         u8 reg_idx = ring->reg_idx;
3166         u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3167 
3168         srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3169 
3170         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3171 }
3172 
3173 #ifdef CONFIG_IXGBE_DCB
3174 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3175 #else
3176 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3177 #endif
3178 {
3179         int i;
3180         bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3181 
3182         if (adapter->ixgbe_ieee_pfc)
3183                 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3184 
3185         /*
3186          * We should set the drop enable bit if:
3187          *  SR-IOV is enabled
3188          *   or
3189          *  Number of Rx queues > 1 and flow control is disabled
3190          *
3191          *  This allows us to avoid head of line blocking for security
3192          *  and performance reasons.
3193          */
3194         if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3195             !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3196                 for (i = 0; i < adapter->num_rx_queues; i++)
3197                         ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3198         } else {
3199                 for (i = 0; i < adapter->num_rx_queues; i++)
3200                         ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3201         }
3202 }
3203 
3204 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3205 
3206 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3207                                    struct ixgbe_ring *rx_ring)
3208 {
3209         struct ixgbe_hw *hw = &adapter->hw;
3210         u32 srrctl;
3211         u8 reg_idx = rx_ring->reg_idx;
3212 
3213         if (hw->mac.type == ixgbe_mac_82598EB) {
3214                 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3215 
3216                 /*
3217                  * if VMDq is not active we must program one srrctl register
3218                  * per RSS queue since we have enabled RDRXCTL.MVMEN
3219                  */
3220                 reg_idx &= mask;
3221         }
3222 
3223         /* configure header buffer length, needed for RSC */
3224         srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3225 
3226         /* configure the packet buffer length */
3227         srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3228 
3229         /* configure descriptor type */
3230         srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3231 
3232         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3233 }
3234 
3235 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter, const u32 *seed)
3236 {
3237         struct ixgbe_hw *hw = &adapter->hw;
3238         u32 reta = 0;
3239         int i, j;
3240         int reta_entries = 128;
3241         u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3242         int indices_multi;
3243 
3244         /*
3245          * Program table for at least 2 queues w/ SR-IOV so that VFs can
3246          * make full use of any rings they may have.  We will use the
3247          * PSRTYPE register to control how many rings we use within the PF.
3248          */
3249         if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3250                 rss_i = 2;
3251 
3252         /* Fill out hash function seeds */
3253         for (i = 0; i < 10; i++)
3254                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3255 
3256         /* Fill out the redirection table as follows:
3257          * 82598: 128 (8 bit wide) entries containing pair of 4 bit RSS indices
3258          * 82599/X540: 128 (8 bit wide) entries containing 4 bit RSS index
3259          * X550: 512 (8 bit wide) entries containing 6 bit RSS index
3260          */
3261         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3262                 indices_multi = 0x11;
3263         else
3264                 indices_multi = 0x1;
3265 
3266         switch (adapter->hw.mac.type) {
3267         case ixgbe_mac_X550:
3268         case ixgbe_mac_X550EM_x:
3269                 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3270                         reta_entries = 512;
3271         default:
3272                 break;
3273         }
3274 
3275         /* Fill out redirection table */
3276         for (i = 0, j = 0; i < reta_entries; i++, j++) {
3277                 if (j == rss_i)
3278                         j = 0;
3279                 reta = (reta << 8) | (j * indices_multi);
3280                 if ((i & 3) == 3) {
3281                         if (i < 128)
3282                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3283                         else
3284                                 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3285                                                 reta);
3286                 }
3287         }
3288 }
3289 
3290 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter, const u32 *seed)
3291 {
3292         struct ixgbe_hw *hw = &adapter->hw;
3293         u32 vfreta = 0;
3294         u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3295         unsigned int pf_pool = adapter->num_vfs;
3296         int i, j;
3297 
3298         /* Fill out hash function seeds */
3299         for (i = 0; i < 10; i++)
3300                 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool), seed[i]);
3301 
3302         /* Fill out the redirection table */
3303         for (i = 0, j = 0; i < 64; i++, j++) {
3304                 if (j == rss_i)
3305                         j = 0;
3306                 vfreta = (vfreta << 8) | j;
3307                 if ((i & 3) == 3)
3308                         IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool),
3309                                         vfreta);
3310         }
3311 }
3312 
3313 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3314 {
3315         struct ixgbe_hw *hw = &adapter->hw;
3316         u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
3317         u32 rss_key[10];
3318         u32 rxcsum;
3319 
3320         /* Disable indicating checksum in descriptor, enables RSS hash */
3321         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3322         rxcsum |= IXGBE_RXCSUM_PCSD;
3323         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3324 
3325         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3326                 if (adapter->ring_feature[RING_F_RSS].mask)
3327                         mrqc = IXGBE_MRQC_RSSEN;
3328         } else {
3329                 u8 tcs = netdev_get_num_tc(adapter->netdev);
3330 
3331                 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3332                         if (tcs > 4)
3333                                 mrqc = IXGBE_MRQC_VMDQRT8TCEN;  /* 8 TCs */
3334                         else if (tcs > 1)
3335                                 mrqc = IXGBE_MRQC_VMDQRT4TCEN;  /* 4 TCs */
3336                         else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3337                                 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3338                         else
3339                                 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3340                 } else {
3341                         if (tcs > 4)
3342                                 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3343                         else if (tcs > 1)
3344                                 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3345                         else
3346                                 mrqc = IXGBE_MRQC_RSSEN;
3347                 }
3348         }
3349 
3350         /* Perform hash on these packet types */
3351         rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3352                      IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3353                      IXGBE_MRQC_RSS_FIELD_IPV6 |
3354                      IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3355 
3356         if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3357                 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3358         if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3359                 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3360 
3361         netdev_rss_key_fill(rss_key, sizeof(rss_key));
3362         if ((hw->mac.type >= ixgbe_mac_X550) &&
3363             (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3364                 unsigned int pf_pool = adapter->num_vfs;
3365 
3366                 /* Enable VF RSS mode */
3367                 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3368                 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3369 
3370                 /* Setup RSS through the VF registers */
3371                 ixgbe_setup_vfreta(adapter, rss_key);
3372                 vfmrqc = IXGBE_MRQC_RSSEN;
3373                 vfmrqc |= rss_field;
3374                 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc);
3375         } else {
3376                 ixgbe_setup_reta(adapter, rss_key);
3377                 mrqc |= rss_field;
3378                 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3379         }
3380 }
3381 
3382 /**
3383  * ixgbe_configure_rscctl - enable RSC for the indicated ring
3384  * @adapter:    address of board private structure
3385  * @index:      index of ring to set
3386  **/
3387 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3388                                    struct ixgbe_ring *ring)
3389 {
3390         struct ixgbe_hw *hw = &adapter->hw;
3391         u32 rscctrl;
3392         u8 reg_idx = ring->reg_idx;
3393 
3394         if (!ring_is_rsc_enabled(ring))
3395                 return;
3396 
3397         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3398         rscctrl |= IXGBE_RSCCTL_RSCEN;
3399         /*
3400          * we must limit the number of descriptors so that the
3401          * total size of max desc * buf_len is not greater
3402          * than 65536
3403          */
3404         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3405         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3406 }
3407 
3408 #define IXGBE_MAX_RX_DESC_POLL 10
3409 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3410                                        struct ixgbe_ring *ring)
3411 {
3412         struct ixgbe_hw *hw = &adapter->hw;
3413         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3414         u32 rxdctl;
3415         u8 reg_idx = ring->reg_idx;
3416 
3417         if (ixgbe_removed(hw->hw_addr))
3418                 return;
3419         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3420         if (hw->mac.type == ixgbe_mac_82598EB &&
3421             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3422                 return;
3423 
3424         do {
3425                 usleep_range(1000, 2000);
3426                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3427         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3428 
3429         if (!wait_loop) {
3430                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3431                       "the polling period\n", reg_idx);
3432         }
3433 }
3434 
3435 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3436                             struct ixgbe_ring *ring)
3437 {
3438         struct ixgbe_hw *hw = &adapter->hw;
3439         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3440         u32 rxdctl;
3441         u8 reg_idx = ring->reg_idx;
3442 
3443         if (ixgbe_removed(hw->hw_addr))
3444                 return;
3445         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3446         rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3447 
3448         /* write value back with RXDCTL.ENABLE bit cleared */
3449         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3450 
3451         if (hw->mac.type == ixgbe_mac_82598EB &&
3452             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3453                 return;
3454 
3455         /* the hardware may take up to 100us to really disable the rx queue */
3456         do {
3457                 udelay(10);
3458                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3459         } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3460 
3461         if (!wait_loop) {
3462                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3463                       "the polling period\n", reg_idx);
3464         }
3465 }
3466 
3467 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3468                              struct ixgbe_ring *ring)
3469 {
3470         struct ixgbe_hw *hw = &adapter->hw;
3471         u64 rdba = ring->dma;
3472         u32 rxdctl;
3473         u8 reg_idx = ring->reg_idx;
3474 
3475         /* disable queue to avoid issues while updating state */
3476         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3477         ixgbe_disable_rx_queue(adapter, ring);
3478 
3479         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3480         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3481         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3482                         ring->count * sizeof(union ixgbe_adv_rx_desc));
3483         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3484         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3485         ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
3486 
3487         ixgbe_configure_srrctl(adapter, ring);
3488         ixgbe_configure_rscctl(adapter, ring);
3489 
3490         if (hw->mac.type == ixgbe_mac_82598EB) {
3491                 /*
3492                  * enable cache line friendly hardware writes:
3493                  * PTHRESH=32 descriptors (half the internal cache),
3494                  * this also removes ugly rx_no_buffer_count increment
3495                  * HTHRESH=4 descriptors (to minimize latency on fetch)
3496                  * WTHRESH=8 burst writeback up to two cache lines
3497                  */
3498                 rxdctl &= ~0x3FFFFF;
3499                 rxdctl |=  0x080420;
3500         }
3501 
3502         /* enable receive descriptor ring */
3503         rxdctl |= IXGBE_RXDCTL_ENABLE;
3504         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3505 
3506         ixgbe_rx_desc_queue_enable(adapter, ring);
3507         ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3508 }
3509 
3510 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3511 {
3512         struct ixgbe_hw *hw = &adapter->hw;
3513         int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3514         u16 pool;
3515 
3516         /* PSRTYPE must be initialized in non 82598 adapters */
3517         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3518                       IXGBE_PSRTYPE_UDPHDR |
3519                       IXGBE_PSRTYPE_IPV4HDR |
3520                       IXGBE_PSRTYPE_L2HDR |
3521                       IXGBE_PSRTYPE_IPV6HDR;
3522 
3523         if (hw->mac.type == ixgbe_mac_82598EB)
3524                 return;
3525 
3526         if (rss_i > 3)
3527                 psrtype |= 2 << 29;
3528         else if (rss_i > 1)
3529                 psrtype |= 1 << 29;
3530 
3531         for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3532                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
3533 }
3534 
3535 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3536 {
3537         struct ixgbe_hw *hw = &adapter->hw;
3538         u32 reg_offset, vf_shift;
3539         u32 gcr_ext, vmdctl;
3540         int i;
3541 
3542         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3543                 return;
3544 
3545         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3546         vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3547         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3548         vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3549         vmdctl |= IXGBE_VT_CTL_REPLEN;
3550         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3551 
3552         vf_shift = VMDQ_P(0) % 32;
3553         reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3554 
3555         /* Enable only the PF's pool for Tx/Rx */
3556         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3557         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3558         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3559         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3560         if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3561                 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3562 
3563         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3564         hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3565 
3566         /*
3567          * Set up VF register offsets for selected VT Mode,
3568          * i.e. 32 or 64 VFs for SR-IOV
3569          */
3570         switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3571         case IXGBE_82599_VMDQ_8Q_MASK:
3572                 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3573                 break;
3574         case IXGBE_82599_VMDQ_4Q_MASK:
3575                 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3576                 break;
3577         default:
3578                 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3579                 break;
3580         }
3581 
3582         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3583 
3584 
3585         /* Enable MAC Anti-Spoofing */
3586         hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3587                                           adapter->num_vfs);
3588 
3589         /* Ensure LLDP is set for Ethertype Antispoofing if we will be
3590          * calling set_ethertype_anti_spoofing for each VF in loop below
3591          */
3592         if (hw->mac.ops.set_ethertype_anti_spoofing)
3593                 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP),
3594                                 (IXGBE_ETQF_FILTER_EN    | /* enable filter */
3595                                  IXGBE_ETQF_TX_ANTISPOOF | /* tx antispoof */
3596                                  IXGBE_ETH_P_LLDP));       /* LLDP eth type */
3597 
3598         /* For VFs that have spoof checking turned off */
3599         for (i = 0; i < adapter->num_vfs; i++) {
3600                 if (!adapter->vfinfo[i].spoofchk_enabled)
3601                         ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3602 
3603                 /* enable ethertype anti spoofing if hw supports it */
3604                 if (hw->mac.ops.set_ethertype_anti_spoofing)
3605                         hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
3606         }
3607 }
3608 
3609 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3610 {
3611         struct ixgbe_hw *hw = &adapter->hw;
3612         struct net_device *netdev = adapter->netdev;
3613         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3614         struct ixgbe_ring *rx_ring;
3615         int i;
3616         u32 mhadd, hlreg0;
3617 
3618 #ifdef IXGBE_FCOE
3619         /* adjust max frame to be able to do baby jumbo for FCoE */
3620         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3621             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3622                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3623 
3624 #endif /* IXGBE_FCOE */
3625 
3626         /* adjust max frame to be at least the size of a standard frame */
3627         if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3628                 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3629 
3630         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3631         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3632                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3633                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3634 
3635                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3636         }
3637 
3638         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3639         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3640         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3641         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3642 
3643         /*
3644          * Setup the HW Rx Head and Tail Descriptor Pointers and
3645          * the Base and Length of the Rx Descriptor Ring
3646          */
3647         for (i = 0; i < adapter->num_rx_queues; i++) {
3648                 rx_ring = adapter->rx_ring[i];
3649                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3650                         set_ring_rsc_enabled(rx_ring);
3651                 else
3652                         clear_ring_rsc_enabled(rx_ring);
3653         }
3654 }
3655 
3656 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3657 {
3658         struct ixgbe_hw *hw = &adapter->hw;
3659         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3660 
3661         switch (hw->mac.type) {
3662         case ixgbe_mac_X550:
3663         case ixgbe_mac_X550EM_x:
3664         case ixgbe_mac_82598EB:
3665                 /*
3666                  * For VMDq support of different descriptor types or
3667                  * buffer sizes through the use of multiple SRRCTL
3668                  * registers, RDRXCTL.MVMEN must be set to 1
3669                  *
3670                  * also, the manual doesn't mention it clearly but DCA hints
3671                  * will only use queue 0's tags unless this bit is set.  Side
3672                  * effects of setting this bit are only that SRRCTL must be
3673                  * fully programmed [0..15]
3674                  */
3675                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3676                 break;
3677         case ixgbe_mac_82599EB:
3678         case ixgbe_mac_X540:
3679                 /* Disable RSC for ACK packets */
3680                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3681                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3682                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3683                 /* hardware requires some bits to be set by default */
3684                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3685                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3686                 break;
3687         default:
3688                 /* We should do nothing since we don't know this hardware */
3689                 return;
3690         }
3691 
3692         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3693 }
3694 
3695 /**
3696  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3697  * @adapter: board private structure
3698  *
3699  * Configure the Rx unit of the MAC after a reset.
3700  **/
3701 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3702 {
3703         struct ixgbe_hw *hw = &adapter->hw;
3704         int i;
3705         u32 rxctrl, rfctl;
3706 
3707         /* disable receives while setting up the descriptors */
3708         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3709         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3710 
3711         ixgbe_setup_psrtype(adapter);
3712         ixgbe_setup_rdrxctl(adapter);
3713 
3714         /* RSC Setup */
3715         rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3716         rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3717         if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3718                 rfctl |= IXGBE_RFCTL_RSC_DIS;
3719         IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3720 
3721         /* Program registers for the distribution of queues */
3722         ixgbe_setup_mrqc(adapter);
3723 
3724         /* set_rx_buffer_len must be called before ring initialization */
3725         ixgbe_set_rx_buffer_len(adapter);
3726 
3727         /*
3728          * Setup the HW Rx Head and Tail Descriptor Pointers and
3729          * the Base and Length of the Rx Descriptor Ring
3730          */
3731         for (i = 0; i < adapter->num_rx_queues; i++)
3732                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3733 
3734         /* disable drop enable for 82598 parts */
3735         if (hw->mac.type == ixgbe_mac_82598EB)
3736                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3737 
3738         /* enable all receives */
3739         rxctrl |= IXGBE_RXCTRL_RXEN;
3740         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3741 }
3742 
3743 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3744                                  __be16 proto, u16 vid)
3745 {
3746         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3747         struct ixgbe_hw *hw = &adapter->hw;
3748 
3749         /* add VID to filter table */
3750         hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
3751         set_bit(vid, adapter->active_vlans);
3752 
3753         return 0;
3754 }
3755 
3756 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3757                                   __be16 proto, u16 vid)
3758 {
3759         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3760         struct ixgbe_hw *hw = &adapter->hw;
3761 
3762         /* remove VID from filter table */
3763         hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
3764         clear_bit(vid, adapter->active_vlans);
3765 
3766         return 0;
3767 }
3768 
3769 /**
3770  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3771  * @adapter: driver data
3772  */
3773 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3774 {
3775         struct ixgbe_hw *hw = &adapter->hw;
3776         u32 vlnctrl;
3777         int i, j;
3778 
3779         switch (hw->mac.type) {
3780         case ixgbe_mac_82598EB:
3781                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3782                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3783                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3784                 break;
3785         case ixgbe_mac_82599EB:
3786         case ixgbe_mac_X540:
3787         case ixgbe_mac_X550:
3788         case ixgbe_mac_X550EM_x:
3789                 for (i = 0; i < adapter->num_rx_queues; i++) {
3790                         struct ixgbe_ring *ring = adapter->rx_ring[i];
3791 
3792                         if (ring->l2_accel_priv)
3793                                 continue;
3794                         j = ring->reg_idx;
3795                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3796                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3797                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3798                 }
3799                 break;
3800         default:
3801                 break;
3802         }
3803 }
3804 
3805 /**
3806  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3807  * @adapter: driver data
3808  */
3809 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3810 {
3811         struct ixgbe_hw *hw = &adapter->hw;
3812         u32 vlnctrl;
3813         int i, j;
3814 
3815         switch (hw->mac.type) {
3816         case ixgbe_mac_82598EB:
3817                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3818                 vlnctrl |= IXGBE_VLNCTRL_VME;
3819                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3820                 break;
3821         case ixgbe_mac_82599EB:
3822         case ixgbe_mac_X540:
3823         case ixgbe_mac_X550:
3824         case ixgbe_mac_X550EM_x:
3825                 for (i = 0; i < adapter->num_rx_queues; i++) {
3826                         struct ixgbe_ring *ring = adapter->rx_ring[i];
3827 
3828                         if (ring->l2_accel_priv)
3829                                 continue;
3830                         j = ring->reg_idx;
3831                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3832                         vlnctrl |= IXGBE_RXDCTL_VME;
3833                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3834                 }
3835                 break;
3836         default:
3837                 break;
3838         }
3839 }
3840 
3841 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3842 {
3843         u16 vid;
3844 
3845         ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
3846 
3847         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3848                 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
3849 }
3850 
3851 /**
3852  * ixgbe_write_mc_addr_list - write multicast addresses to MTA
3853  * @netdev: network interface device structure
3854  *
3855  * Writes multicast address list to the MTA hash table.
3856  * Returns: -ENOMEM on failure
3857  *                0 on no addresses written
3858  *                X on writing X addresses to MTA
3859  **/
3860 static int ixgbe_write_mc_addr_list(struct net_device *netdev)
3861 {
3862         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3863         struct ixgbe_hw *hw = &adapter->hw;
3864 
3865         if (!netif_running(netdev))
3866                 return 0;
3867 
3868         if (hw->mac.ops.update_mc_addr_list)
3869                 hw->mac.ops.update_mc_addr_list(hw, netdev);
3870         else
3871                 return -ENOMEM;
3872 
3873 #ifdef CONFIG_PCI_IOV
3874         ixgbe_restore_vf_multicasts(adapter);
3875 #endif
3876 
3877         return netdev_mc_count(netdev);
3878 }
3879 
3880 #ifdef CONFIG_PCI_IOV
3881 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
3882 {
3883         struct ixgbe_hw *hw = &adapter->hw;
3884         int i;
3885         for (i = 0; i < hw->mac.num_rar_entries; i++) {
3886                 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
3887                         hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr,
3888                                             adapter->mac_table[i].queue,
3889                                             IXGBE_RAH_AV);
3890                 else
3891                         hw->mac.ops.clear_rar(hw, i);
3892 
3893                 adapter->mac_table[i].state &= ~(IXGBE_MAC_STATE_MODIFIED);
3894         }
3895 }
3896 #endif
3897 
3898 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
3899 {
3900         struct ixgbe_hw *hw = &adapter->hw;
3901         int i;
3902         for (i = 0; i < hw->mac.num_rar_entries; i++) {
3903                 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) {
3904                         if (adapter->mac_table[i].state &
3905                             IXGBE_MAC_STATE_IN_USE)
3906                                 hw->mac.ops.set_rar(hw, i,
3907                                                 adapter->mac_table[i].addr,
3908                                                 adapter->mac_table[i].queue,
3909                                                 IXGBE_RAH_AV);
3910                         else
3911                                 hw->mac.ops.clear_rar(hw, i);
3912 
3913                         adapter->mac_table[i].state &=
3914                                                 ~(IXGBE_MAC_STATE_MODIFIED);
3915                 }
3916         }
3917 }
3918 
3919 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
3920 {
3921         int i;
3922         struct ixgbe_hw *hw = &adapter->hw;
3923 
3924         for (i = 0; i < hw->mac.num_rar_entries; i++) {
3925                 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
3926                 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
3927                 memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
3928                 adapter->mac_table[i].queue = 0;
3929         }
3930         ixgbe_sync_mac_table(adapter);
3931 }
3932 
3933 static int ixgbe_available_rars(struct ixgbe_adapter *adapter)
3934 {
3935         struct ixgbe_hw *hw = &adapter->hw;
3936         int i, count = 0;
3937 
3938         for (i = 0; i < hw->mac.num_rar_entries; i++) {
3939                 if (adapter->mac_table[i].state == 0)
3940                         count++;
3941         }
3942         return count;
3943 }
3944 
3945 /* this function destroys the first RAR entry */
3946 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter,
3947                                          u8 *addr)
3948 {
3949         struct ixgbe_hw *hw = &adapter->hw;
3950 
3951         memcpy(&adapter->mac_table[0].addr, addr, ETH_ALEN);
3952         adapter->mac_table[0].queue = VMDQ_P(0);
3953         adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT |
3954                                        IXGBE_MAC_STATE_IN_USE);
3955         hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr,
3956                             adapter->mac_table[0].queue,
3957                             IXGBE_RAH_AV);
3958 }
3959 
3960 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
3961 {
3962         struct ixgbe_hw *hw = &adapter->hw;
3963         int i;
3964 
3965         if (is_zero_ether_addr(addr))
3966                 return -EINVAL;
3967 
3968         for (i = 0; i < hw->mac.num_rar_entries; i++) {
3969                 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
3970                         continue;
3971                 adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED |
3972                                                 IXGBE_MAC_STATE_IN_USE);
3973                 ether_addr_copy(adapter->mac_table[i].addr, addr);
3974                 adapter->mac_table[i].queue = queue;
3975                 ixgbe_sync_mac_table(adapter);
3976                 return i;
3977         }
3978         return -ENOMEM;
3979 }
3980 
3981 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
3982 {
3983         /* search table for addr, if found, set to 0 and sync */
3984         int i;
3985         struct ixgbe_hw *hw = &adapter->hw;
3986 
3987         if (is_zero_ether_addr(addr))
3988                 return -EINVAL;
3989 
3990         for (i = 0; i < hw->mac.num_rar_entries; i++) {
3991                 if (ether_addr_equal(addr, adapter->mac_table[i].addr) &&
3992                     adapter->mac_table[i].queue == queue) {
3993                         adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
3994                         adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
3995                         memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
3996                         adapter->mac_table[i].queue = 0;
3997                         ixgbe_sync_mac_table(adapter);
3998                         return 0;
3999                 }
4000         }
4001         return -ENOMEM;
4002 }
4003 /**
4004  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
4005  * @netdev: network interface device structure
4006  *
4007  * Writes unicast address list to the RAR table.
4008  * Returns: -ENOMEM on failure/insufficient address space
4009  *                0 on no addresses written
4010  *                X on writing X addresses to the RAR table
4011  **/
4012 static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
4013 {
4014         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4015         int count = 0;
4016 
4017         /* return ENOMEM indicating insufficient memory for addresses */
4018         if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter))
4019                 return -ENOMEM;
4020 
4021         if (!netdev_uc_empty(netdev)) {
4022                 struct netdev_hw_addr *ha;
4023                 netdev_for_each_uc_addr(ha, netdev) {
4024                         ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4025                         ixgbe_add_mac_filter(adapter, ha->addr, vfn);
4026                         count++;
4027                 }
4028         }
4029         return count;
4030 }
4031 
4032 /**
4033  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
4034  * @netdev: network interface device structure
4035  *
4036  * The set_rx_method entry point is called whenever the unicast/multicast
4037  * address list or the network interface flags are updated.  This routine is
4038  * responsible for configuring the hardware for proper unicast, multicast and
4039  * promiscuous mode.
4040  **/
4041 void ixgbe_set_rx_mode(struct net_device *netdev)
4042 {
4043         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4044         struct ixgbe_hw *hw = &adapter->hw;
4045         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
4046         u32 vlnctrl;
4047         int count;
4048 
4049         /* Check for Promiscuous and All Multicast modes */
4050         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4051         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4052 
4053         /* set all bits that we expect to always be set */
4054         fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
4055         fctrl |= IXGBE_FCTRL_BAM;
4056         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4057         fctrl |= IXGBE_FCTRL_PMCF;
4058 
4059         /* clear the bits we are changing the status of */
4060         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4061         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
4062         if (netdev->flags & IFF_PROMISC) {
4063                 hw->addr_ctrl.user_set_promisc = true;
4064                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4065                 vmolr |= IXGBE_VMOLR_MPE;
4066                 /* Only disable hardware filter vlans in promiscuous mode
4067                  * if SR-IOV and VMDQ are disabled - otherwise ensure
4068                  * that hardware VLAN filters remain enabled.
4069                  */
4070                 if (adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
4071                                       IXGBE_FLAG_SRIOV_ENABLED))
4072                         vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
4073         } else {
4074                 if (netdev->flags & IFF_ALLMULTI) {
4075                         fctrl |= IXGBE_FCTRL_MPE;
4076                         vmolr |= IXGBE_VMOLR_MPE;
4077                 }
4078                 vlnctrl |= IXGBE_VLNCTRL_VFE;
4079                 hw->addr_ctrl.user_set_promisc = false;
4080         }
4081 
4082         /*
4083          * Write addresses to available RAR registers, if there is not
4084          * sufficient space to store all the addresses then enable
4085          * unicast promiscuous mode
4086          */
4087         count = ixgbe_write_uc_addr_list(netdev, VMDQ_P(0));
4088         if (count < 0) {
4089                 fctrl |= IXGBE_FCTRL_UPE;
4090                 vmolr |= IXGBE_VMOLR_ROPE;
4091         }
4092 
4093         /* Write addresses to the MTA, if the attempt fails
4094          * then we should just turn on promiscuous mode so
4095          * that we can at least receive multicast traffic
4096          */
4097         count = ixgbe_write_mc_addr_list(netdev);
4098         if (count < 0) {
4099                 fctrl |= IXGBE_FCTRL_MPE;
4100                 vmolr |= IXGBE_VMOLR_MPE;
4101         } else if (count) {
4102                 vmolr |= IXGBE_VMOLR_ROMPE;
4103         }
4104 
4105         if (hw->mac.type != ixgbe_mac_82598EB) {
4106                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
4107                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4108                            IXGBE_VMOLR_ROPE);
4109                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
4110         }
4111 
4112         /* This is useful for sniffing bad packets. */
4113         if (adapter->netdev->features & NETIF_F_RXALL) {
4114                 /* UPE and MPE will be handled by normal PROMISC logic
4115                  * in e1000e_set_rx_mode */
4116                 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4117                           IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4118                           IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4119 
4120                 fctrl &= ~(IXGBE_FCTRL_DPF);
4121                 /* NOTE:  VLAN filtering is disabled by setting PROMISC */
4122         }
4123 
4124         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4125         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4126 
4127         if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
4128                 ixgbe_vlan_strip_enable(adapter);
4129         else
4130                 ixgbe_vlan_strip_disable(adapter);
4131 }
4132 
4133 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4134 {
4135         int q_idx;
4136 
4137         for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4138                 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
4139                 napi_enable(&adapter->q_vector[q_idx]->napi);
4140         }
4141 }
4142 
4143 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4144 {
4145         int q_idx;
4146 
4147         for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4148                 napi_disable(&adapter->q_vector[q_idx]->napi);
4149                 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
4150                         pr_info("QV %d locked\n", q_idx);
4151                         usleep_range(1000, 20000);
4152                 }
4153         }
4154 }
4155 
4156 #ifdef CONFIG_IXGBE_DCB
4157 /**
4158  * ixgbe_configure_dcb - Configure DCB hardware
4159  * @adapter: ixgbe adapter struct
4160  *
4161  * This is called by the driver on open to configure the DCB hardware.
4162  * This is also called by the gennetlink interface when reconfiguring
4163  * the DCB state.
4164  */
4165 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4166 {
4167         struct ixgbe_hw *hw = &adapter->hw;
4168         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4169 
4170         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4171                 if (hw->mac.type == ixgbe_mac_82598EB)
4172                         netif_set_gso_max_size(adapter->netdev, 65536);
4173                 return;
4174         }
4175 
4176         if (hw->mac.type == ixgbe_mac_82598EB)
4177                 netif_set_gso_max_size(adapter->netdev, 32768);
4178 
4179 #ifdef IXGBE_FCOE
4180         if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4181                 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
4182 #endif
4183 
4184         /* reconfigure the hardware */
4185         if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
4186                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4187                                                 DCB_TX_CONFIG);
4188                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4189                                                 DCB_RX_CONFIG);
4190                 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
4191         } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4192                 ixgbe_dcb_hw_ets(&adapter->hw,
4193                                  adapter->ixgbe_ieee_ets,
4194                                  max_frame);
4195                 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4196                                         adapter->ixgbe_ieee_pfc->pfc_en,
4197                                         adapter->ixgbe_ieee_ets->prio_tc);
4198         }
4199 
4200         /* Enable RSS Hash per TC */
4201         if (hw->mac.type != ixgbe_mac_82598EB) {
4202                 u32 msb = 0;
4203                 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
4204 
4205                 while (rss_i) {
4206                         msb++;
4207                         rss_i >>= 1;
4208                 }
4209 
4210                 /* write msb to all 8 TCs in one write */
4211                 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
4212         }
4213 }
4214 #endif
4215 
4216 /* Additional bittime to account for IXGBE framing */
4217 #define IXGBE_ETH_FRAMING 20
4218 
4219 /**
4220  * ixgbe_hpbthresh - calculate high water mark for flow control
4221  *
4222  * @adapter: board private structure to calculate for
4223  * @pb: packet buffer to calculate
4224  */
4225 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4226 {
4227         struct ixgbe_hw *hw = &adapter->hw;
4228         struct net_device *dev = adapter->netdev;
4229         int link, tc, kb, marker;
4230         u32 dv_id, rx_pba;
4231 
4232         /* Calculate max LAN frame size */
4233         tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4234 
4235 #ifdef IXGBE_FCOE
4236         /* FCoE traffic class uses FCOE jumbo frames */
4237         if ((dev->features & NETIF_F_FCOE_MTU) &&
4238             (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4239             (pb == ixgbe_fcoe_get_tc(adapter)))
4240                 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4241 #endif
4242 
4243         /* Calculate delay value for device */
4244         switch (hw->mac.type) {
4245         case ixgbe_mac_X540:
4246         case ixgbe_mac_X550:
4247         case ixgbe_mac_X550EM_x:
4248                 dv_id = IXGBE_DV_X540(link, tc);
4249                 break;
4250         default:
4251                 dv_id = IXGBE_DV(link, tc);
4252                 break;
4253         }
4254 
4255         /* Loopback switch introduces additional latency */
4256         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4257                 dv_id += IXGBE_B2BT(tc);
4258 
4259         /* Delay value is calculated in bit times convert to KB */
4260         kb = IXGBE_BT2KB(dv_id);
4261         rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4262 
4263         marker = rx_pba - kb;
4264 
4265         /* It is possible that the packet buffer is not large enough
4266          * to provide required headroom. In this case throw an error
4267          * to user and a do the best we can.
4268          */
4269         if (marker < 0) {
4270                 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4271                             "headroom to support flow control."
4272                             "Decrease MTU or number of traffic classes\n", pb);
4273                 marker = tc + 1;
4274         }
4275 
4276         return marker;
4277 }
4278 
4279 /**
4280  * ixgbe_lpbthresh - calculate low water mark for for flow control
4281  *
4282  * @adapter: board private structure to calculate for
4283  * @pb: packet buffer to calculate
4284  */
4285 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
4286 {
4287         struct ixgbe_hw *hw = &adapter->hw;
4288         struct net_device *dev = adapter->netdev;
4289         int tc;
4290         u32 dv_id;
4291 
4292         /* Calculate max LAN frame size */
4293         tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4294 
4295 #ifdef IXGBE_FCOE
4296         /* FCoE traffic class uses FCOE jumbo frames */
4297         if ((dev->features & NETIF_F_FCOE_MTU) &&
4298             (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4299             (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4300                 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4301 #endif
4302 
4303         /* Calculate delay value for device */
4304         switch (hw->mac.type) {
4305         case ixgbe_mac_X540:
4306         case ixgbe_mac_X550:
4307         case ixgbe_mac_X550EM_x:
4308                 dv_id = IXGBE_LOW_DV_X540(tc);
4309                 break;
4310         default:
4311                 dv_id = IXGBE_LOW_DV(tc);
4312                 break;
4313         }
4314 
4315         /* Delay value is calculated in bit times convert to KB */
4316         return IXGBE_BT2KB(dv_id);
4317 }
4318 
4319 /*
4320  * ixgbe_pbthresh_setup - calculate and setup high low water marks
4321  */
4322 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4323 {
4324         struct ixgbe_hw *hw = &adapter->hw;
4325         int num_tc = netdev_get_num_tc(adapter->netdev);
4326         int i;
4327 
4328         if (!num_tc)
4329                 num_tc = 1;
4330 
4331         for (i = 0; i < num_tc; i++) {
4332                 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
4333                 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
4334 
4335                 /* Low water marks must not be larger than high water marks */
4336                 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4337                         hw->fc.low_water[i] = 0;
4338         }
4339 
4340         for (; i < MAX_TRAFFIC_CLASS; i++)
4341                 hw->fc.high_water[i] = 0;
4342 }
4343 
4344 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4345 {
4346         struct ixgbe_hw *hw = &adapter->hw;
4347         int hdrm;
4348         u8 tc = netdev_get_num_tc(adapter->netdev);
4349 
4350         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4351             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4352                 hdrm = 32 << adapter->fdir_pballoc;
4353         else
4354                 hdrm = 0;
4355 
4356         hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
4357         ixgbe_pbthresh_setup(adapter);
4358 }
4359 
4360 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4361 {
4362         struct ixgbe_hw *hw = &adapter->hw;
4363         struct hlist_node *node2;
4364         struct ixgbe_fdir_filter *filter;
4365 
4366         spin_lock(&adapter->fdir_perfect_lock);
4367 
4368         if (!hlist_empty(&adapter->fdir_filter_list))
4369                 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4370 
4371         hlist_for_each_entry_safe(filter, node2,
4372                                   &adapter->fdir_filter_list, fdir_node) {
4373                 ixgbe_fdir_write_perfect_filter_82599(hw,
4374                                 &filter->filter,
4375                                 filter->sw_idx,
4376                                 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4377                                 IXGBE_FDIR_DROP_QUEUE :
4378                                 adapter->rx_ring[filter->action]->reg_idx);
4379         }
4380 
4381         spin_unlock(&adapter->fdir_perfect_lock);
4382 }
4383 
4384 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4385                                       struct ixgbe_adapter *adapter)
4386 {
4387         struct ixgbe_hw *hw = &adapter->hw;
4388         u32 vmolr;
4389 
4390         /* No unicast promiscuous support for VMDQ devices. */
4391         vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4392         vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4393 
4394         /* clear the affected bit */
4395         vmolr &= ~IXGBE_VMOLR_MPE;
4396 
4397         if (dev->flags & IFF_ALLMULTI) {
4398                 vmolr |= IXGBE_VMOLR_MPE;
4399         } else {
4400                 vmolr |= IXGBE_VMOLR_ROMPE;
4401                 hw->mac.ops.update_mc_addr_list(hw, dev);
4402         }
4403         ixgbe_write_uc_addr_list(adapter->netdev, pool);
4404         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4405 }
4406 
4407 static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4408 {
4409         struct ixgbe_adapter *adapter = vadapter->real_adapter;
4410         int rss_i = adapter->num_rx_queues_per_pool;
4411         struct ixgbe_hw *hw = &adapter->hw;
4412         u16 pool = vadapter->pool;
4413         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4414                       IXGBE_PSRTYPE_UDPHDR |
4415                       IXGBE_PSRTYPE_IPV4HDR |
4416                       IXGBE_PSRTYPE_L2HDR |
4417                       IXGBE_PSRTYPE_IPV6HDR;
4418 
4419         if (hw->mac.type == ixgbe_mac_82598EB)
4420                 return;
4421 
4422         if (rss_i > 3)
4423                 psrtype |= 2 << 29;
4424         else if (rss_i > 1)
4425                 psrtype |= 1 << 29;
4426 
4427         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4428 }
4429 
4430 /**
4431  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4432  * @rx_ring: ring to free buffers from
4433  **/
4434 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4435 {
4436         struct device *dev = rx_ring->dev;
4437         unsigned long size;
4438         u16 i;
4439 
4440         /* ring already cleared, nothing to do */
4441         if (!rx_ring->rx_buffer_info)
4442                 return;
4443 
4444         /* Free all the Rx ring sk_buffs */
4445         for (i = 0; i < rx_ring->count; i++) {
4446                 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
4447 
4448                 if (rx_buffer->skb) {
4449                         struct sk_buff *skb = rx_buffer->skb;
4450                         if (IXGBE_CB(skb)->page_released)
4451                                 dma_unmap_page(dev,
4452                                                IXGBE_CB(skb)->dma,
4453                                                ixgbe_rx_bufsz(rx_ring),
4454                                                DMA_FROM_DEVICE);
4455                         dev_kfree_skb(skb);
4456                         rx_buffer->skb = NULL;
4457                 }
4458 
4459                 if (!rx_buffer->page)
4460                         continue;
4461 
4462                 dma_unmap_page(dev, rx_buffer->dma,
4463                                ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
4464                 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring));
4465 
4466                 rx_buffer->page = NULL;
4467         }
4468 
4469         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4470         memset(rx_ring->rx_buffer_info, 0, size);
4471 
4472         /* Zero out the descriptor ring */
4473         memset(rx_ring->desc, 0, rx_ring->size);
4474 
4475         rx_ring->next_to_alloc = 0;
4476         rx_ring->next_to_clean = 0;
4477         rx_ring->next_to_use = 0;
4478 }
4479 
4480 static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4481                                    struct ixgbe_ring *rx_ring)
4482 {
4483         struct ixgbe_adapter *adapter = vadapter->real_adapter;
4484         int index = rx_ring->queue_index + vadapter->rx_base_queue;
4485 
4486         /* shutdown specific queue receive and wait for dma to settle */
4487         ixgbe_disable_rx_queue(adapter, rx_ring);
4488         usleep_range(10000, 20000);
4489         ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4490         ixgbe_clean_rx_ring(rx_ring);
4491         rx_ring->l2_accel_priv = NULL;
4492 }
4493 
4494 static int ixgbe_fwd_ring_down(struct net_device *vdev,
4495                                struct ixgbe_fwd_adapter *accel)
4496 {
4497         struct ixgbe_adapter *adapter = accel->real_adapter;
4498         unsigned int rxbase = accel->rx_base_queue;
4499         unsigned int txbase = accel->tx_base_queue;
4500         int i;
4501 
4502         netif_tx_stop_all_queues(vdev);
4503 
4504         for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4505                 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4506                 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4507         }
4508 
4509         for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4510                 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4511                 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4512         }
4513 
4514 
4515         return 0;
4516 }
4517 
4518 static int ixgbe_fwd_ring_up(struct net_device *vdev,
4519                              struct ixgbe_fwd_adapter *accel)
4520 {
4521         struct ixgbe_adapter *adapter = accel->real_adapter;
4522         unsigned int rxbase, txbase, queues;
4523         int i, baseq, err = 0;
4524 
4525         if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4526                 return 0;
4527 
4528         baseq = accel->pool * adapter->num_rx_queues_per_pool;
4529         netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4530                    accel->pool, adapter->num_rx_pools,
4531                    baseq, baseq + adapter->num_rx_queues_per_pool,
4532                    adapter->fwd_bitmask);
4533 
4534         accel->netdev = vdev;
4535         accel->rx_base_queue = rxbase = baseq;
4536         accel->tx_base_queue = txbase = baseq;
4537 
4538         for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4539                 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4540 
4541         for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4542                 adapter->rx_ring[rxbase + i]->netdev = vdev;
4543                 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4544                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4545         }
4546 
4547         for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4548                 adapter->tx_ring[txbase + i]->netdev = vdev;
4549                 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4550         }
4551 
4552         queues = min_t(unsigned int,
4553                        adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4554         err = netif_set_real_num_tx_queues(vdev, queues);
4555         if (err)
4556                 goto fwd_queue_err;
4557 
4558         err = netif_set_real_num_rx_queues(vdev, queues);
4559         if (err)
4560                 goto fwd_queue_err;
4561 
4562         if (is_valid_ether_addr(vdev->dev_addr))
4563                 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4564 
4565         ixgbe_fwd_psrtype(accel);
4566         ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4567         return err;
4568 fwd_queue_err:
4569         ixgbe_fwd_ring_down(vdev, accel);
4570         return err;
4571 }
4572 
4573 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4574 {
4575         struct net_device *upper;
4576         struct list_head *iter;
4577         int err;
4578 
4579         netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4580                 if (netif_is_macvlan(upper)) {
4581                         struct macvlan_dev *dfwd = netdev_priv(upper);
4582                         struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4583 
4584                         if (dfwd->fwd_priv) {
4585                                 err = ixgbe_fwd_ring_up(upper, vadapter);
4586                                 if (err)
4587                                         continue;
4588                         }
4589                 }
4590         }
4591 }
4592 
4593 static void ixgbe_configure(struct ixgbe_adapter *adapter)
4594 {
4595         struct ixgbe_hw *hw = &adapter->hw;
4596 
4597         ixgbe_configure_pb(adapter);
4598 #ifdef CONFIG_IXGBE_DCB
4599         ixgbe_configure_dcb(adapter);
4600 #endif
4601         /*
4602          * We must restore virtualization before VLANs or else
4603          * the VLVF registers will not be populated
4604          */
4605         ixgbe_configure_virtualization(adapter);
4606 
4607         ixgbe_set_rx_mode(adapter->netdev);
4608         ixgbe_restore_vlan(adapter);
4609 
4610         switch (hw->mac.type) {
4611         case ixgbe_mac_82599EB:
4612         case ixgbe_mac_X540:
4613                 hw->mac.ops.disable_rx_buff(hw);
4614                 break;
4615         default:
4616                 break;
4617         }
4618 
4619         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4620                 ixgbe_init_fdir_signature_82599(&adapter->hw,
4621                                                 adapter->fdir_pballoc);
4622         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4623                 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4624                                               adapter->fdir_pballoc);
4625                 ixgbe_fdir_filter_restore(adapter);
4626         }
4627 
4628         switch (hw->mac.type) {
4629         case ixgbe_mac_82599EB:
4630         case ixgbe_mac_X540:
4631                 hw->mac.ops.enable_rx_buff(hw);
4632                 break;
4633         default:
4634                 break;
4635         }
4636 
4637 #ifdef IXGBE_FCOE
4638         /* configure FCoE L2 filters, redirection table, and Rx control */
4639         ixgbe_configure_fcoe(adapter);
4640 
4641 #endif /* IXGBE_FCOE */
4642         ixgbe_configure_tx(adapter);
4643         ixgbe_configure_rx(adapter);
4644         ixgbe_configure_dfwd(adapter);
4645 }
4646 
4647 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4648 {
4649         switch (hw->phy.type) {
4650         case ixgbe_phy_sfp_avago:
4651         case ixgbe_phy_sfp_ftl:
4652         case ixgbe_phy_sfp_intel:
4653         case ixgbe_phy_sfp_unknown:
4654         case ixgbe_phy_sfp_passive_tyco:
4655         case ixgbe_phy_sfp_passive_unknown:
4656         case ixgbe_phy_sfp_active_unknown:
4657         case ixgbe_phy_sfp_ftl_active:
4658         case ixgbe_phy_qsfp_passive_unknown:
4659         case ixgbe_phy_qsfp_active_unknown:
4660         case ixgbe_phy_qsfp_intel:
4661         case ixgbe_phy_qsfp_unknown:
4662         /* ixgbe_phy_none is set when no SFP module is present */
4663         case ixgbe_phy_none:
4664                 return true;
4665         case ixgbe_phy_nl:
4666                 if (hw->mac.type == ixgbe_mac_82598EB)
4667                         return true;
4668         default:
4669                 return false;
4670         }
4671 }
4672 
4673 /**
4674  * ixgbe_sfp_link_config - set up SFP+ link
4675  * @adapter: pointer to private adapter struct
4676  **/
4677 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4678 {
4679         /*
4680          * We are assuming the worst case scenario here, and that
4681          * is that an SFP was inserted/removed after the reset
4682          * but before SFP detection was enabled.  As such the best
4683          * solution is to just start searching as soon as we start
4684          */
4685         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4686                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
4687 
4688         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
4689 }
4690 
4691 /**
4692  * ixgbe_non_sfp_link_config - set up non-SFP+ link
4693  * @hw: pointer to private hardware struct
4694  *
4695  * Returns 0 on success, negative on failure
4696  **/
4697 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
4698 {
4699         u32 speed;
4700         bool autoneg, link_up = false;
4701         u32 ret = IXGBE_ERR_LINK_SETUP;
4702 
4703         if (hw->mac.ops.check_link)
4704                 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
4705 
4706         if (ret)
4707                 return ret;
4708 
4709         speed = hw->phy.autoneg_advertised;
4710         if ((!speed) && (hw->mac.ops.get_link_capabilities))
4711                 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4712                                                         &autoneg);
4713         if (ret)
4714                 return ret;
4715 
4716         if (hw->mac.ops.setup_link)
4717                 ret = hw->mac.ops.setup_link(hw, speed, link_up);
4718 
4719         return ret;
4720 }
4721 
4722 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
4723 {
4724         struct ixgbe_hw *hw = &adapter->hw;
4725         u32 gpie = 0;
4726 
4727         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4728                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4729                        IXGBE_GPIE_OCD;
4730                 gpie |= IXGBE_GPIE_EIAME;
4731                 /*
4732                  * use EIAM to auto-mask when MSI-X interrupt is asserted
4733                  * this saves a register write for every interrupt
4734                  */
4735                 switch (hw->mac.type) {
4736                 case ixgbe_mac_82598EB:
4737                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4738                         break;
4739                 case ixgbe_mac_82599EB:
4740                 case ixgbe_mac_X540:
4741                 case ixgbe_mac_X550:
4742                 case ixgbe_mac_X550EM_x:
4743                 default:
4744                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4745                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4746                         break;
4747                 }
4748         } else {
4749                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4750                  * specifically only auto mask tx and rx interrupts */
4751                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4752         }
4753 
4754         /* XXX: to interrupt immediately for EICS writes, enable this */
4755         /* gpie |= IXGBE_GPIE_EIMEN; */
4756 
4757         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4758                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
4759 
4760                 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4761                 case IXGBE_82599_VMDQ_8Q_MASK:
4762                         gpie |= IXGBE_GPIE_VTMODE_16;
4763                         break;
4764                 case IXGBE_82599_VMDQ_4Q_MASK:
4765                         gpie |= IXGBE_GPIE_VTMODE_32;
4766                         break;
4767                 default:
4768                         gpie |= IXGBE_GPIE_VTMODE_64;
4769                         break;
4770                 }
4771         }
4772 
4773         /* Enable Thermal over heat sensor interrupt */
4774         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4775                 switch (adapter->hw.mac.type) {
4776                 case ixgbe_mac_82599EB:
4777                         gpie |= IXGBE_SDP0_GPIEN;
4778                         break;
4779                 case ixgbe_mac_X540:
4780                         gpie |= IXGBE_EIMS_TS;
4781                         break;
4782                 default:
4783                         break;
4784                 }
4785         }
4786 
4787         /* Enable fan failure interrupt */
4788         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
4789                 gpie |= IXGBE_SDP1_GPIEN;
4790 
4791         if (hw->mac.type == ixgbe_mac_82599EB) {
4792                 gpie |= IXGBE_SDP1_GPIEN;
4793                 gpie |= IXGBE_SDP2_GPIEN;
4794         }
4795 
4796         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4797 }
4798 
4799 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
4800 {
4801         struct ixgbe_hw *hw = &adapter->hw;
4802         int err;
4803         u32 ctrl_ext;
4804 
4805         ixgbe_get_hw_control(adapter);
4806         ixgbe_setup_gpie(adapter);
4807 
4808         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4809                 ixgbe_configure_msix(adapter);
4810         else
4811                 ixgbe_configure_msi_and_legacy(adapter);
4812 
4813         /* enable the optics for 82599 SFP+ fiber */
4814         if (hw->mac.ops.enable_tx_laser)
4815                 hw->mac.ops.enable_tx_laser(hw);
4816 
4817         smp_mb__before_atomic();
4818         clear_bit(__IXGBE_DOWN, &adapter->state);
4819         ixgbe_napi_enable_all(adapter);
4820 
4821         if (ixgbe_is_sfp(hw)) {
4822                 ixgbe_sfp_link_config(adapter);
4823         } else {
4824                 err = ixgbe_non_sfp_link_config(hw);
4825                 if (err)
4826                         e_err(probe, "link_config FAILED %d\n", err);
4827         }
4828 
4829         /* clear any pending interrupts, may auto mask */
4830         IXGBE_READ_REG(hw, IXGBE_EICR);
4831         ixgbe_irq_enable(adapter, true, true);
4832 
4833         /*
4834          * If this adapter has a fan, check to see if we had a failure
4835          * before we enabled the interrupt.
4836          */
4837         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4838                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4839                 if (esdp & IXGBE_ESDP_SDP1)
4840                         e_crit(drv, "Fan has stopped, replace the adapter\n");
4841         }
4842 
4843         /* bring the link up in the watchdog, this could race with our first
4844          * link up interrupt but shouldn't be a problem */
4845         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4846         adapter->link_check_timeout = jiffies;
4847         mod_timer(&adapter->service_timer, jiffies);
4848 
4849         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4850         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4851         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4852         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4853 }
4854 
4855 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4856 {
4857         WARN_ON(in_interrupt());
4858         /* put off any impending NetWatchDogTimeout */
4859         adapter->netdev->trans_start = jiffies;
4860 
4861         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4862                 usleep_range(1000, 2000);
4863         ixgbe_down(adapter);
4864         /*
4865          * If SR-IOV enabled then wait a bit before bringing the adapter
4866          * back up to give the VFs time to respond to the reset.  The
4867          * two second wait is based upon the watchdog timer cycle in
4868          * the VF driver.
4869          */
4870         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4871                 msleep(2000);
4872         ixgbe_up(adapter);
4873         clear_bit(__IXGBE_RESETTING, &adapter->state);
4874 }
4875 
4876 void ixgbe_up(struct ixgbe_adapter *adapter)
4877 {
4878         /* hardware has been reset, we need to reload some things */
4879         ixgbe_configure(adapter);
4880 
4881         ixgbe_up_complete(adapter);
4882 }
4883 
4884 void ixgbe_reset(struct ixgbe_adapter *adapter)
4885 {
4886         struct ixgbe_hw *hw = &adapter->hw;
4887         struct net_device *netdev = adapter->netdev;
4888         int err;
4889         u8 old_addr[ETH_ALEN];
4890 
4891         if (ixgbe_removed(hw->hw_addr))
4892                 return;
4893         /* lock SFP init bit to prevent race conditions with the watchdog */
4894         while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4895                 usleep_range(1000, 2000);
4896 
4897         /* clear all SFP and link config related flags while holding SFP_INIT */
4898         adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4899                              IXGBE_FLAG2_SFP_NEEDS_RESET);
4900         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4901 
4902         err = hw->mac.ops.init_hw(hw);
4903         switch (err) {
4904         case 0:
4905         case IXGBE_ERR_SFP_NOT_PRESENT:
4906         case IXGBE_ERR_SFP_NOT_SUPPORTED:
4907                 break;
4908         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4909                 e_dev_err("master disable timed out\n");
4910                 break;
4911         case IXGBE_ERR_EEPROM_VERSION:
4912                 /* We are running on a pre-production device, log a warning */
4913                 e_dev_warn("This device is a pre-production adapter/LOM. "
4914                            "Please be aware there may be issues associated with "
4915                            "your hardware.  If you are experiencing problems "
4916                            "please contact your Intel or hardware "
4917                            "representative who provided you with this "
4918                            "hardware.\n");
4919                 break;
4920         default:
4921                 e_dev_err("Hardware Error: %d\n", err);
4922         }
4923 
4924         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4925         /* do not flush user set addresses */
4926         memcpy(old_addr, &adapter->mac_table[0].addr, netdev->addr_len);
4927         ixgbe_flush_sw_mac_table(adapter);
4928         ixgbe_mac_set_default_filter(adapter, old_addr);
4929 
4930         /* update SAN MAC vmdq pool selection */
4931         if (hw->mac.san_mac_rar_index)
4932                 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
4933 
4934         if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
4935                 ixgbe_ptp_reset(adapter);
4936 }
4937 
4938 /**
4939  * ixgbe_clean_tx_ring - Free Tx Buffers
4940  * @tx_ring: ring to be cleaned
4941  **/
4942 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4943 {
4944         struct ixgbe_tx_buffer *tx_buffer_info;
4945         unsigned long size;
4946         u16 i;
4947 
4948         /* ring already cleared, nothing to do */
4949         if (!tx_ring->tx_buffer_info)
4950                 return;
4951 
4952         /* Free all the Tx ring sk_buffs */
4953         for (i = 0; i < tx_ring->count; i++) {
4954                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4955                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4956         }
4957 
4958         netdev_tx_reset_queue(txring_txq(tx_ring));
4959 
4960         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4961         memset(tx_ring->tx_buffer_info, 0, size);
4962 
4963         /* Zero out the descriptor ring */
4964         memset(tx_ring->desc, 0, tx_ring->size);
4965 
4966         tx_ring->next_to_use = 0;
4967         tx_ring->next_to_clean = 0;
4968 }
4969 
4970 /**
4971  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4972  * @adapter: board private structure
4973  **/
4974 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4975 {
4976         int i;
4977 
4978         for (i = 0; i < adapter->num_rx_queues; i++)
4979                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4980 }
4981 
4982 /**
4983  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4984  * @adapter: board private structure
4985  **/
4986 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4987 {
4988         int i;
4989 
4990         for (i = 0; i < adapter->num_tx_queues; i++)
4991                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4992 }
4993 
4994 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4995 {
4996         struct hlist_node *node2;
4997         struct ixgbe_fdir_filter *filter;
4998 
4999         spin_lock(&adapter->fdir_perfect_lock);
5000 
5001         hlist_for_each_entry_safe(filter, node2,
5002                                   &adapter->fdir_filter_list, fdir_node) {
5003                 hlist_del(&filter->fdir_node);
5004                 kfree(filter);
5005         }
5006         adapter->fdir_filter_count = 0;
5007 
5008         spin_unlock(&adapter->fdir_perfect_lock);
5009 }
5010 
5011 void ixgbe_down(struct ixgbe_adapter *adapter)
5012 {
5013         struct net_device *netdev = adapter->netdev;
5014         struct ixgbe_hw *hw = &adapter->hw;
5015         struct net_device *upper;
5016         struct list_head *iter;
5017         u32 rxctrl;
5018         int i;
5019 
5020         /* signal that we are down to the interrupt handler */
5021         if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5022                 return; /* do nothing if already down */
5023 
5024         /* disable receives */
5025         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5026         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
5027 
5028         /* disable all enabled rx queues */
5029         for (i = 0; i < adapter->num_rx_queues; i++)
5030                 /* this call also flushes the previous write */
5031                 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5032 
5033         usleep_range(10000, 20000);
5034 
5035         netif_tx_stop_all_queues(netdev);
5036 
5037         /* call carrier off first to avoid false dev_watchdog timeouts */
5038         netif_carrier_off(netdev);
5039         netif_tx_disable(netdev);
5040 
5041         /* disable any upper devices */
5042         netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5043                 if (netif_is_macvlan(upper)) {
5044                         struct macvlan_dev *vlan = netdev_priv(upper);
5045 
5046                         if (vlan->fwd_priv) {
5047                                 netif_tx_stop_all_queues(upper);
5048                                 netif_carrier_off(upper);
5049                                 netif_tx_disable(upper);
5050                         }
5051                 }
5052         }
5053 
5054         ixgbe_irq_disable(adapter);
5055 
5056         ixgbe_napi_disable_all(adapter);
5057 
5058         adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
5059                              IXGBE_FLAG2_RESET_REQUESTED);
5060         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5061 
5062         del_timer_sync(&adapter->service_timer);
5063 
5064         if (adapter->num_vfs) {
5065                 /* Clear EITR Select mapping */
5066                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
5067 
5068                 /* Mark all the VFs as inactive */
5069                 for (i = 0 ; i < adapter->num_vfs; i++)
5070                         adapter->vfinfo[i].clear_to_send = false;
5071 
5072                 /* ping all the active vfs to let them know we are going down */
5073                 ixgbe_ping_all_vfs(adapter);
5074 
5075                 /* Disable all VFTE/VFRE TX/RX */
5076                 ixgbe_disable_tx_rx(adapter);
5077         }
5078 
5079         /* disable transmits in the hardware now that interrupts are off */
5080         for (i = 0; i < adapter->num_tx_queues; i++) {
5081                 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
5082                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5083         }
5084 
5085         /* Disable the Tx DMA engine on 82599 and later MAC */
5086         switch (hw->mac.type) {
5087         case ixgbe_mac_82599EB:
5088         case ixgbe_mac_X540:
5089         case ixgbe_mac_X550:
5090         case ixgbe_mac_X550EM_x:
5091                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
5092                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5093                                  ~IXGBE_DMATXCTL_TE));
5094                 break;
5095         default:
5096                 break;
5097         }
5098 
5099         if (!pci_channel_offline(adapter->pdev))
5100                 ixgbe_reset(adapter);
5101 
5102         /* power down the optics for 82599 SFP+ fiber */
5103         if (hw->mac.ops.disable_tx_laser)
5104                 hw->mac.ops.disable_tx_laser(hw);
5105 
5106         ixgbe_clean_all_tx_rings(adapter);
5107         ixgbe_clean_all_rx_rings(adapter);
5108 
5109 #ifdef CONFIG_IXGBE_DCA
5110         /* since we reset the hardware DCA settings were cleared */
5111         ixgbe_setup_dca(adapter);
5112 #endif
5113 }
5114 
5115 /**
5116  * ixgbe_tx_timeout - Respond to a Tx Hang
5117  * @netdev: network interface device structure
5118  **/
5119 static void ixgbe_tx_timeout(struct net_device *netdev)
5120 {
5121         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5122 
5123         /* Do the reset outside of interrupt context */
5124         ixgbe_tx_timeout_reset(adapter);
5125 }
5126 
5127 /**
5128  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5129  * @adapter: board private structure to initialize
5130  *
5131  * ixgbe_sw_init initializes the Adapter private data structure.
5132  * Fields are initialized based on PCI device information and
5133  * OS network device settings (MTU size).
5134  **/
5135 static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
5136 {
5137         struct ixgbe_hw *hw = &adapter->hw;
5138         struct pci_dev *pdev = adapter->pdev;
5139         unsigned int rss, fdir;
5140         u32 fwsm;
5141 #ifdef CONFIG_IXGBE_DCB
5142         int j;
5143         struct tc_configuration *tc;
5144 #endif
5145 
5146         /* PCI config space info */
5147 
5148         hw->vendor_id = pdev->vendor;
5149         hw->device_id = pdev->device;
5150         hw->revision_id = pdev->revision;
5151         hw->subsystem_vendor_id = pdev->subsystem_vendor;
5152         hw->subsystem_device_id = pdev->subsystem_device;
5153 
5154         /* Set common capability flags and settings */
5155         rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
5156         adapter->ring_feature[RING_F_RSS].limit = rss;
5157         adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5158         adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5159         adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5160         adapter->atr_sample_rate = 20;
5161         fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5162         adapter->ring_feature[RING_F_FDIR].limit = fdir;
5163         adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5164 #ifdef CONFIG_IXGBE_DCA
5165         adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5166 #endif
5167 #ifdef IXGBE_FCOE
5168         adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5169         adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5170 #ifdef CONFIG_IXGBE_DCB
5171         /* Default traffic class to use for FCoE */
5172         adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5173 #endif /* CONFIG_IXGBE_DCB */
5174 #endif /* IXGBE_FCOE */
5175 
5176         adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5177                                      hw->mac.num_rar_entries,
5178                                      GFP_ATOMIC);
5179 
5180         /* Set MAC specific capability flags and exceptions */
5181         switch (hw->mac.type) {
5182         case ixgbe_mac_82598EB:
5183                 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5184                 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
5185 
5186                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5187                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5188 
5189                 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
5190                 adapter->ring_feature[RING_F_FDIR].limit = 0;
5191                 adapter->atr_sample_rate = 0;
5192                 adapter->fdir_pballoc = 0;
5193 #ifdef IXGBE_FCOE
5194                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5195                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5196 #ifdef CONFIG_IXGBE_DCB
5197                 adapter->fcoe.up = 0;
5198 #endif /* IXGBE_DCB */
5199 #endif /* IXGBE_FCOE */
5200                 break;
5201         case ixgbe_mac_82599EB:
5202                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5203                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5204                 break;
5205         case ixgbe_mac_X540:
5206                 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
5207                 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5208                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5209                 break;
5210         case ixgbe_mac_X550EM_x:
5211         case ixgbe_mac_X550:
5212 #ifdef CONFIG_IXGBE_DCA
5213                 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
5214 #endif
5215                 break;
5216         default:
5217                 break;
5218         }
5219 
5220 #ifdef IXGBE_FCOE
5221         /* FCoE support exists, always init the FCoE lock */
5222         spin_lock_init(&adapter->fcoe.lock);
5223 
5224 #endif
5225         /* n-tuple support exists, always init our spinlock */
5226         spin_lock_init(&adapter->fdir_perfect_lock);
5227 
5228 #ifdef CONFIG_IXGBE_DCB
5229         switch (hw->mac.type) {
5230         case ixgbe_mac_X540:
5231         case ixgbe_mac_X550:
5232         case ixgbe_mac_X550EM_x:
5233                 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5234                 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5235                 break;
5236         default:
5237                 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5238                 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5239                 break;
5240         }
5241 
5242         /* Configure DCB traffic classes */
5243         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5244                 tc = &adapter->dcb_cfg.tc_config[j];
5245                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5246                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5247                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5248                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5249                 tc->dcb_pfc = pfc_disabled;
5250         }
5251 
5252         /* Initialize default user to priority mapping, UPx->TC0 */
5253         tc = &adapter->dcb_cfg.tc_config[0];
5254         tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5255         tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5256 
5257         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5258         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5259         adapter->dcb_cfg.pfc_mode_enable = false;
5260         adapter->dcb_set_bitmap = 0x00;
5261         adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5262         memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5263                sizeof(adapter->temp_dcb_cfg));
5264 
5265 #endif
5266 
5267         /* default flow control settings */
5268         hw->fc.requested_mode = ixgbe_fc_full;
5269         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
5270         ixgbe_pbthresh_setup(adapter);
5271         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5272         hw->fc.send_xon = true;
5273         hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
5274 
5275 #ifdef CONFIG_PCI_IOV
5276         if (max_vfs > 0)
5277                 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5278 
5279         /* assign number of SR-IOV VFs */
5280         if (hw->mac.type != ixgbe_mac_82598EB) {
5281                 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
5282                         adapter->num_vfs = 0;
5283                         e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5284                 } else {
5285                         adapter->num_vfs = max_vfs;
5286                 }
5287         }
5288 #endif /* CONFIG_PCI_IOV */
5289 
5290         /* enable itr by default in dynamic mode */
5291         adapter->rx_itr_setting = 1;
5292         adapter->tx_itr_setting = 1;
5293 
5294         /* set default ring sizes */
5295         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5296         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5297 
5298         /* set default work limits */
5299         adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
5300 
5301         /* initialize eeprom parameters */
5302         if (ixgbe_init_eeprom_params_generic(hw)) {
5303                 e_dev_err("EEPROM initialization failed\n");
5304                 return -EIO;
5305         }
5306 
5307         /* PF holds first pool slot */
5308         set_bit(0, &adapter->fwd_bitmask);
5309         set_bit(__IXGBE_DOWN, &adapter->state);
5310 
5311         return 0;
5312 }
5313 
5314 /**
5315  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5316  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
5317  *
5318  * Return 0 on success, negative on failure
5319  **/
5320 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5321 {
5322         struct device *dev = tx_ring->dev;
5323         int orig_node = dev_to_node(dev);
5324         int ring_node = -1;
5325         int size;
5326 
5327         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5328 
5329         if (tx_ring->q_vector)
5330                 ring_node = tx_ring->q_vector->numa_node;
5331 
5332         tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
5333         if (!tx_ring->tx_buffer_info)
5334                 tx_ring->tx_buffer_info = vzalloc(size);
5335         if (!tx_ring->tx_buffer_info)
5336                 goto err;
5337 
5338         u64_stats_init(&tx_ring->syncp);
5339 
5340         /* round up to nearest 4K */
5341         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5342         tx_ring->size = ALIGN(tx_ring->size, 4096);
5343 
5344         set_dev_node(dev, ring_node);
5345         tx_ring->desc = dma_alloc_coherent(dev,
5346                                            tx_ring->size,
5347                                            &tx_ring->dma,
5348                                            GFP_KERNEL);
5349         set_dev_node(dev, orig_node);
5350         if (!tx_ring->desc)
5351                 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5352                                                    &tx_ring->dma, GFP_KERNEL);
5353         if (!tx_ring->desc)
5354                 goto err;
5355 
5356         tx_ring->next_to_use = 0;
5357         tx_ring->next_to_clean = 0;
5358         return 0;
5359 
5360 err:
5361         vfree(tx_ring->tx_buffer_info);
5362         tx_ring->tx_buffer_info = NULL;
5363         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5364         return -ENOMEM;
5365 }
5366 
5367 /**
5368  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5369  * @adapter: board private structure
5370  *
5371  * If this function returns with an error, then it's possible one or
5372  * more of the rings is populated (while the rest are not).  It is the
5373  * callers duty to clean those orphaned rings.
5374  *
5375  * Return 0 on success, negative on failure
5376  **/
5377 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5378 {
5379         int i, err = 0;
5380 
5381         for (i = 0; i < adapter->num_tx_queues; i++) {
5382                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5383                 if (!err)
5384                         continue;
5385 
5386                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5387                 goto err_setup_tx;
5388         }
5389 
5390         return 0;
5391 err_setup_tx:
5392         /* rewind the index freeing the rings as we go */
5393         while (i--)
5394                 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5395         return err;
5396 }
5397 
5398 /**
5399  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5400  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5401  *
5402  * Returns 0 on success, negative on failure
5403  **/
5404 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5405 {
5406         struct device *dev = rx_ring->dev;
5407         int orig_node = dev_to_node(dev);
5408         int ring_node = -1;
5409         int size;
5410 
5411         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5412 
5413         if (rx_ring->q_vector)
5414                 ring_node = rx_ring->q_vector->numa_node;
5415 
5416         rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
5417         if (!rx_ring->rx_buffer_info)
5418                 rx_ring->rx_buffer_info = vzalloc(size);
5419         if (!rx_ring->rx_buffer_info)
5420                 goto err;
5421 
5422         u64_stats_init(&rx_ring->syncp);
5423 
5424         /* Round up to nearest 4K */
5425         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5426         rx_ring->size = ALIGN(rx_ring->size, 4096);
5427 
5428         set_dev_node(dev, ring_node);
5429         rx_ring->desc = dma_alloc_coherent(dev,
5430                                            rx_ring->size,
5431                                            &rx_ring->dma,
5432                                            GFP_KERNEL);
5433         set_dev_node(dev, orig_node);
5434         if (!rx_ring->desc)
5435                 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5436                                                    &rx_ring->dma, GFP_KERNEL);
5437         if (!rx_ring->desc)
5438                 goto err;
5439 
5440         rx_ring->next_to_clean = 0;
5441         rx_ring->next_to_use = 0;
5442 
5443         return 0;
5444 err:
5445         vfree(rx_ring->rx_buffer_info);
5446         rx_ring->rx_buffer_info = NULL;
5447         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5448         return -ENOMEM;
5449 }
5450 
5451 /**
5452  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5453  * @adapter: board private structure
5454  *
5455  * If this function returns with an error, then it's possible one or
5456  * more of the rings is populated (while the rest are not).  It is the
5457  * callers duty to clean those orphaned rings.
5458  *
5459  * Return 0 on success, negative on failure
5460  **/
5461 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5462 {
5463         int i, err = 0;
5464 
5465         for (i = 0; i < adapter->num_rx_queues; i++) {
5466                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5467                 if (!err)
5468                         continue;
5469 
5470                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5471                 goto err_setup_rx;
5472         }
5473 
5474 #ifdef IXGBE_FCOE
5475         err = ixgbe_setup_fcoe_ddp_resources(adapter);
5476         if (!err)
5477 #endif
5478                 return 0;
5479 err_setup_rx:
5480         /* rewind the index freeing the rings as we go */
5481         while (i--)
5482                 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5483         return err;
5484 }
5485 
5486 /**
5487  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5488  * @tx_ring: Tx descriptor ring for a specific queue
5489  *
5490  * Free all transmit software resources
5491  **/
5492 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5493 {
5494         ixgbe_clean_tx_ring(tx_ring);
5495 
5496         vfree(tx_ring->tx_buffer_info);
5497         tx_ring->tx_buffer_info = NULL;
5498 
5499         /* if not set, then don't free */
5500         if (!tx_ring->desc)
5501                 return;
5502 
5503         dma_free_coherent(tx_ring->dev, tx_ring->size,
5504                           tx_ring->desc, tx_ring->dma);
5505 
5506         tx_ring->desc = NULL;
5507 }
5508 
5509 /**
5510  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5511  * @adapter: board private structure
5512  *
5513  * Free all transmit software resources
5514  **/
5515 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5516 {
5517         int i;
5518 
5519         for (i = 0; i < adapter->num_tx_queues; i++)
5520                 if (adapter->tx_ring[i]->desc)
5521                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5522 }
5523 
5524 /**
5525  * ixgbe_free_rx_resources - Free Rx Resources
5526  * @rx_ring: ring to clean the resources from
5527  *
5528  * Free all receive software resources
5529  **/
5530 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5531 {
5532         ixgbe_clean_rx_ring(rx_ring);
5533 
5534         vfree(rx_ring->rx_buffer_info);
5535         rx_ring->rx_buffer_info = NULL;
5536 
5537         /* if not set, then don't free */
5538         if (!rx_ring->desc)
5539                 return;
5540 
5541         dma_free_coherent(rx_ring->dev, rx_ring->size,
5542                           rx_ring->desc, rx_ring->dma);
5543 
5544         rx_ring->desc = NULL;
5545 }
5546 
5547 /**
5548  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5549  * @adapter: board private structure
5550  *
5551  * Free all receive software resources
5552  **/
5553 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5554 {
5555         int i;
5556 
5557 #ifdef IXGBE_FCOE
5558         ixgbe_free_fcoe_ddp_resources(adapter);
5559 
5560 #endif
5561         for (i = 0; i < adapter->num_rx_queues; i++)
5562                 if (adapter->rx_ring[i]->desc)
5563                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5564 }
5565 
5566 /**
5567  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5568  * @netdev: network interface device structure
5569  * @new_mtu: new value for maximum frame size
5570  *
5571  * Returns 0 on success, negative on failure
5572  **/
5573 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5574 {
5575         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5576         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5577 
5578         /* MTU < 68 is an error and causes problems on some kernels */
5579         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5580                 return -EINVAL;
5581 
5582         /*
5583          * For 82599EB we cannot allow legacy VFs to enable their receive
5584          * paths when MTU greater than 1500 is configured.  So display a
5585          * warning that legacy VFs will be disabled.
5586          */
5587         if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5588             (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
5589             (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
5590                 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
5591 
5592         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5593 
5594         /* must set new MTU before calling down or up */
5595         netdev->mtu = new_mtu;
5596 
5597         if (netif_running(netdev))
5598                 ixgbe_reinit_locked(adapter);
5599 
5600         return 0;
5601 }
5602 
5603 /**
5604  * ixgbe_open - Called when a network interface is made active
5605  * @netdev: network interface device structure
5606  *
5607  * Returns 0 on success, negative value on failure
5608  *
5609  * The open entry point is called when a network interface is made
5610  * active by the system (IFF_UP).  At this point all resources needed
5611  * for transmit and receive operations are allocated, the interrupt
5612  * handler is registered with the OS, the watchdog timer is started,
5613  * and the stack is notified that the interface is ready.
5614  **/
5615 static int ixgbe_open(struct net_device *netdev)
5616 {
5617         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5618         int err, queues;
5619 
5620         /* disallow open during test */
5621         if (test_bit(__IXGBE_TESTING, &adapter->state))
5622                 return -EBUSY;
5623 
5624         netif_carrier_off(netdev);
5625 
5626         /* allocate transmit descriptors */
5627         err = ixgbe_setup_all_tx_resources(adapter);
5628         if (err)
5629                 goto err_setup_tx;
5630 
5631         /* allocate receive descriptors */
5632         err = ixgbe_setup_all_rx_resources(adapter);
5633         if (err)
5634                 goto err_setup_rx;
5635 
5636         ixgbe_configure(adapter);
5637 
5638         err = ixgbe_request_irq(adapter);
5639         if (err)
5640                 goto err_req_irq;
5641 
5642         /* Notify the stack of the actual queue counts. */
5643         if (adapter->num_rx_pools > 1)
5644                 queues = adapter->num_rx_queues_per_pool;
5645         else
5646                 queues = adapter->num_tx_queues;
5647 
5648         err = netif_set_real_num_tx_queues(netdev, queues);
5649         if (err)
5650                 goto err_set_queues;
5651 
5652         if (adapter->num_rx_pools > 1 &&
5653             adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5654                 queues = IXGBE_MAX_L2A_QUEUES;
5655         else
5656                 queues = adapter->num_rx_queues;
5657         err = netif_set_real_num_rx_queues(netdev, queues);
5658         if (err)
5659                 goto err_set_queues;
5660 
5661         ixgbe_ptp_init(adapter);
5662 
5663         ixgbe_up_complete(adapter);
5664 
5665 #if IS_ENABLED(CONFIG_IXGBE_VXLAN)
5666         vxlan_get_rx_port(netdev);
5667 
5668 #endif
5669         return 0;
5670 
5671 err_set_queues:
5672         ixgbe_free_irq(adapter);
5673 err_req_irq:
5674         ixgbe_free_all_rx_resources(adapter);
5675 err_setup_rx:
5676         ixgbe_free_all_tx_resources(adapter);
5677 err_setup_tx:
5678         ixgbe_reset(adapter);
5679 
5680         return err;
5681 }
5682 
5683 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
5684 {
5685         ixgbe_ptp_suspend(adapter);
5686 
5687         ixgbe_down(adapter);
5688         ixgbe_free_irq(adapter);
5689 
5690         ixgbe_free_all_tx_resources(adapter);
5691         ixgbe_free_all_rx_resources(adapter);
5692 }
5693 
5694 /**
5695  * ixgbe_close - Disables a network interface
5696  * @netdev: network interface device structure
5697  *
5698  * Returns 0, this is not allowed to fail
5699  *
5700  * The close entry point is called when an interface is de-activated
5701  * by the OS.  The hardware is still under the drivers control, but
5702  * needs to be disabled.  A global MAC reset is issued to stop the
5703  * hardware, and all transmit and receive resources are freed.
5704  **/
5705 static int ixgbe_close(struct net_device *netdev)
5706 {
5707         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5708 
5709         ixgbe_ptp_stop(adapter);
5710 
5711         ixgbe_close_suspend(adapter);
5712 
5713         ixgbe_fdir_filter_exit(adapter);
5714 
5715         ixgbe_release_hw_control(adapter);
5716 
5717         return 0;
5718 }
5719 
5720 #ifdef CONFIG_PM
5721 static int ixgbe_resume(struct pci_dev *pdev)
5722 {
5723         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5724         struct net_device *netdev = adapter->netdev;
5725         u32 err;
5726 
5727         adapter->hw.hw_addr = adapter->io_addr;
5728         pci_set_power_state(pdev, PCI_D0);
5729         pci_restore_state(pdev);
5730         /*
5731          * pci_restore_state clears dev->state_saved so call
5732          * pci_save_state to restore it.
5733          */
5734         pci_save_state(pdev);
5735 
5736         err = pci_enable_device_mem(pdev);
5737         if (err) {
5738                 e_dev_err("Cannot enable PCI device from suspend\n");
5739                 return err;
5740         }
5741         smp_mb__before_atomic();
5742         clear_bit(__IXGBE_DISABLED, &adapter->state);
5743         pci_set_master(pdev);
5744 
5745         pci_wake_from_d3(pdev, false);
5746 
5747         ixgbe_reset(adapter);
5748 
5749         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5750 
5751         rtnl_lock();
5752         err = ixgbe_init_interrupt_scheme(adapter);
5753         if (!err && netif_running(netdev))
5754                 err = ixgbe_open(netdev);
5755 
5756         rtnl_unlock();
5757 
5758         if (err)
5759                 return err;
5760 
5761         netif_device_attach(netdev);
5762 
5763         return 0;
5764 }
5765 #endif /* CONFIG_PM */
5766 
5767 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5768 {
5769         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5770         struct net_device *netdev = adapter->netdev;
5771         struct ixgbe_hw *hw = &adapter->hw;
5772         u32 ctrl, fctrl;
5773         u32 wufc = adapter->wol;
5774 #ifdef CONFIG_PM
5775         int retval = 0;
5776 #endif
5777 
5778         netif_device_detach(netdev);
5779 
5780         rtnl_lock();
5781         if (netif_running(netdev))
5782                 ixgbe_close_suspend(adapter);
5783         rtnl_unlock();
5784 
5785         ixgbe_clear_interrupt_scheme(adapter);
5786 
5787 #ifdef CONFIG_PM
5788         retval = pci_save_state(pdev);
5789         if (retval)
5790                 return retval;
5791 
5792 #endif
5793         if (hw->mac.ops.stop_link_on_d3)
5794                 hw->mac.ops.stop_link_on_d3(hw);
5795 
5796         if (wufc) {
5797                 ixgbe_set_rx_mode(netdev);
5798 
5799                 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5800                 if (hw->mac.ops.enable_tx_laser)
5801                         hw->mac.ops.enable_tx_laser(hw);
5802 
5803                 /* turn on all-multi mode if wake on multicast is enabled */
5804                 if (wufc & IXGBE_WUFC_MC) {
5805                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5806                         fctrl |= IXGBE_FCTRL_MPE;
5807                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5808                 }
5809 
5810                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5811                 ctrl |= IXGBE_CTRL_GIO_DIS;
5812                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5813 
5814                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5815         } else {
5816                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5817                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5818         }
5819 
5820         switch (hw->mac.type) {
5821         case ixgbe_mac_82598EB:
5822                 pci_wake_from_d3(pdev, false);
5823                 break;
5824         case ixgbe_mac_82599EB:
5825         case ixgbe_mac_X540:
5826         case ixgbe_mac_X550:
5827         case ixgbe_mac_X550EM_x:
5828                 pci_wake_from_d3(pdev, !!wufc);
5829                 break;
5830         default:
5831                 break;
5832         }
5833 
5834         *enable_wake = !!wufc;
5835 
5836         ixgbe_release_hw_control(adapter);
5837 
5838         if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
5839                 pci_disable_device(pdev);
5840 
5841         return 0;
5842 }
5843 
5844 #ifdef CONFIG_PM
5845 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5846 {
5847         int retval;
5848         bool wake;
5849 
5850         retval = __ixgbe_shutdown(pdev, &wake);
5851         if (retval)
5852                 return retval;
5853 
5854         if (wake) {
5855                 pci_prepare_to_sleep(pdev);
5856         } else {
5857                 pci_wake_from_d3(pdev, false);
5858                 pci_set_power_state(pdev, PCI_D3hot);
5859         }
5860 
5861         return 0;
5862 }
5863 #endif /* CONFIG_PM */
5864 
5865 static void ixgbe_shutdown(struct pci_dev *pdev)
5866 {
5867         bool wake;
5868 
5869         __ixgbe_shutdown(pdev, &wake);
5870 
5871         if (system_state == SYSTEM_POWER_OFF) {
5872                 pci_wake_from_d3(pdev, wake);
5873                 pci_set_power_state(pdev, PCI_D3hot);
5874         }
5875 }
5876 
5877 /**
5878  * ixgbe_update_stats - Update the board statistics counters.
5879  * @adapter: board private structure
5880  **/
5881 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5882 {
5883         struct net_device *netdev = adapter->netdev;
5884         stru