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Linux/drivers/net/ethernet/freescale/gianfar_ptp.c

  1 /*
  2  * PTP 1588 clock using the eTSEC
  3  *
  4  * Copyright (C) 2010 OMICRON electronics GmbH
  5  *
  6  *  This program is free software; you can redistribute it and/or modify
  7  *  it under the terms of the GNU General Public License as published by
  8  *  the Free Software Foundation; either version 2 of the License, or
  9  *  (at your option) any later version.
 10  *
 11  *  This program is distributed in the hope that it will be useful,
 12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14  *  GNU General Public License for more details.
 15  *
 16  *  You should have received a copy of the GNU General Public License
 17  *  along with this program; if not, write to the Free Software
 18  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 19  */
 20 
 21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 22 
 23 #include <linux/device.h>
 24 #include <linux/hrtimer.h>
 25 #include <linux/interrupt.h>
 26 #include <linux/kernel.h>
 27 #include <linux/module.h>
 28 #include <linux/of.h>
 29 #include <linux/of_platform.h>
 30 #include <linux/timex.h>
 31 #include <linux/io.h>
 32 
 33 #include <linux/ptp_clock_kernel.h>
 34 
 35 #include "gianfar.h"
 36 
 37 /*
 38  * gianfar ptp registers
 39  * Generated by regen.tcl on Thu May 13 01:38:57 PM CEST 2010
 40  */
 41 struct gianfar_ptp_registers {
 42         u32 tmr_ctrl;     /* Timer control register */
 43         u32 tmr_tevent;   /* Timestamp event register */
 44         u32 tmr_temask;   /* Timer event mask register */
 45         u32 tmr_pevent;   /* Timestamp event register */
 46         u32 tmr_pemask;   /* Timer event mask register */
 47         u32 tmr_stat;     /* Timestamp status register */
 48         u32 tmr_cnt_h;    /* Timer counter high register */
 49         u32 tmr_cnt_l;    /* Timer counter low register */
 50         u32 tmr_add;      /* Timer drift compensation addend register */
 51         u32 tmr_acc;      /* Timer accumulator register */
 52         u32 tmr_prsc;     /* Timer prescale */
 53         u8  res1[4];
 54         u32 tmroff_h;     /* Timer offset high */
 55         u32 tmroff_l;     /* Timer offset low */
 56         u8  res2[8];
 57         u32 tmr_alarm1_h; /* Timer alarm 1 high register */
 58         u32 tmr_alarm1_l; /* Timer alarm 1 high register */
 59         u32 tmr_alarm2_h; /* Timer alarm 2 high register */
 60         u32 tmr_alarm2_l; /* Timer alarm 2 high register */
 61         u8  res3[48];
 62         u32 tmr_fiper1;   /* Timer fixed period interval */
 63         u32 tmr_fiper2;   /* Timer fixed period interval */
 64         u32 tmr_fiper3;   /* Timer fixed period interval */
 65         u8  res4[20];
 66         u32 tmr_etts1_h;  /* Timestamp of general purpose external trigger */
 67         u32 tmr_etts1_l;  /* Timestamp of general purpose external trigger */
 68         u32 tmr_etts2_h;  /* Timestamp of general purpose external trigger */
 69         u32 tmr_etts2_l;  /* Timestamp of general purpose external trigger */
 70 };
 71 
 72 /* Bit definitions for the TMR_CTRL register */
 73 #define ALM1P                 (1<<31) /* Alarm1 output polarity */
 74 #define ALM2P                 (1<<30) /* Alarm2 output polarity */
 75 #define FS                    (1<<28) /* FIPER start indication */
 76 #define PP1L                  (1<<27) /* Fiper1 pulse loopback mode enabled. */
 77 #define PP2L                  (1<<26) /* Fiper2 pulse loopback mode enabled. */
 78 #define TCLK_PERIOD_SHIFT     (16) /* 1588 timer reference clock period. */
 79 #define TCLK_PERIOD_MASK      (0x3ff)
 80 #define RTPE                  (1<<15) /* Record Tx Timestamp to PAL Enable. */
 81 #define FRD                   (1<<14) /* FIPER Realignment Disable */
 82 #define ESFDP                 (1<<11) /* External Tx/Rx SFD Polarity. */
 83 #define ESFDE                 (1<<10) /* External Tx/Rx SFD Enable. */
 84 #define ETEP2                 (1<<9) /* External trigger 2 edge polarity */
 85 #define ETEP1                 (1<<8) /* External trigger 1 edge polarity */
 86 #define COPH                  (1<<7) /* Generated clock output phase. */
 87 #define CIPH                  (1<<6) /* External oscillator input clock phase */
 88 #define TMSR                  (1<<5) /* Timer soft reset. */
 89 #define BYP                   (1<<3) /* Bypass drift compensated clock */
 90 #define TE                    (1<<2) /* 1588 timer enable. */
 91 #define CKSEL_SHIFT           (0)    /* 1588 Timer reference clock source */
 92 #define CKSEL_MASK            (0x3)
 93 
 94 /* Bit definitions for the TMR_TEVENT register */
 95 #define ETS2                  (1<<25) /* External trigger 2 timestamp sampled */
 96 #define ETS1                  (1<<24) /* External trigger 1 timestamp sampled */
 97 #define ALM2                  (1<<17) /* Current time = alarm time register 2 */
 98 #define ALM1                  (1<<16) /* Current time = alarm time register 1 */
 99 #define PP1                   (1<<7)  /* periodic pulse generated on FIPER1 */
100 #define PP2                   (1<<6)  /* periodic pulse generated on FIPER2 */
101 #define PP3                   (1<<5)  /* periodic pulse generated on FIPER3 */
102 
103 /* Bit definitions for the TMR_TEMASK register */
104 #define ETS2EN                (1<<25) /* External trigger 2 timestamp enable */
105 #define ETS1EN                (1<<24) /* External trigger 1 timestamp enable */
106 #define ALM2EN                (1<<17) /* Timer ALM2 event enable */
107 #define ALM1EN                (1<<16) /* Timer ALM1 event enable */
108 #define PP1EN                 (1<<7) /* Periodic pulse event 1 enable */
109 #define PP2EN                 (1<<6) /* Periodic pulse event 2 enable */
110 
111 /* Bit definitions for the TMR_PEVENT register */
112 #define TXP2                  (1<<9) /* PTP transmitted timestamp im TXTS2 */
113 #define TXP1                  (1<<8) /* PTP transmitted timestamp in TXTS1 */
114 #define RXP                   (1<<0) /* PTP frame has been received */
115 
116 /* Bit definitions for the TMR_PEMASK register */
117 #define TXP2EN                (1<<9) /* Transmit PTP packet event 2 enable */
118 #define TXP1EN                (1<<8) /* Transmit PTP packet event 1 enable */
119 #define RXPEN                 (1<<0) /* Receive PTP packet event enable */
120 
121 /* Bit definitions for the TMR_STAT register */
122 #define STAT_VEC_SHIFT        (0) /* Timer general purpose status vector */
123 #define STAT_VEC_MASK         (0x3f)
124 
125 /* Bit definitions for the TMR_PRSC register */
126 #define PRSC_OCK_SHIFT        (0) /* Output clock division/prescale factor. */
127 #define PRSC_OCK_MASK         (0xffff)
128 
129 
130 #define DRIVER          "gianfar_ptp"
131 #define DEFAULT_CKSEL   1
132 #define N_EXT_TS        2
133 #define REG_SIZE        sizeof(struct gianfar_ptp_registers)
134 
135 struct etsects {
136         struct gianfar_ptp_registers __iomem *regs;
137         spinlock_t lock; /* protects regs */
138         struct ptp_clock *clock;
139         struct ptp_clock_info caps;
140         struct resource *rsrc;
141         int irq;
142         u64 alarm_interval; /* for periodic alarm */
143         u64 alarm_value;
144         u32 tclk_period;  /* nanoseconds */
145         u32 tmr_prsc;
146         u32 tmr_add;
147         u32 cksel;
148         u32 tmr_fiper1;
149         u32 tmr_fiper2;
150 };
151 
152 /*
153  * Register access functions
154  */
155 
156 /* Caller must hold etsects->lock. */
157 static u64 tmr_cnt_read(struct etsects *etsects)
158 {
159         u64 ns;
160         u32 lo, hi;
161 
162         lo = gfar_read(&etsects->regs->tmr_cnt_l);
163         hi = gfar_read(&etsects->regs->tmr_cnt_h);
164         ns = ((u64) hi) << 32;
165         ns |= lo;
166         return ns;
167 }
168 
169 /* Caller must hold etsects->lock. */
170 static void tmr_cnt_write(struct etsects *etsects, u64 ns)
171 {
172         u32 hi = ns >> 32;
173         u32 lo = ns & 0xffffffff;
174 
175         gfar_write(&etsects->regs->tmr_cnt_l, lo);
176         gfar_write(&etsects->regs->tmr_cnt_h, hi);
177 }
178 
179 /* Caller must hold etsects->lock. */
180 static void set_alarm(struct etsects *etsects)
181 {
182         u64 ns;
183         u32 lo, hi;
184 
185         ns = tmr_cnt_read(etsects) + 1500000000ULL;
186         ns = div_u64(ns, 1000000000UL) * 1000000000ULL;
187         ns -= etsects->tclk_period;
188         hi = ns >> 32;
189         lo = ns & 0xffffffff;
190         gfar_write(&etsects->regs->tmr_alarm1_l, lo);
191         gfar_write(&etsects->regs->tmr_alarm1_h, hi);
192 }
193 
194 /* Caller must hold etsects->lock. */
195 static void set_fipers(struct etsects *etsects)
196 {
197         set_alarm(etsects);
198         gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
199         gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
200 }
201 
202 /*
203  * Interrupt service routine
204  */
205 
206 static irqreturn_t isr(int irq, void *priv)
207 {
208         struct etsects *etsects = priv;
209         struct ptp_clock_event event;
210         u64 ns;
211         u32 ack = 0, lo, hi, mask, val;
212 
213         val = gfar_read(&etsects->regs->tmr_tevent);
214 
215         if (val & ETS1) {
216                 ack |= ETS1;
217                 hi = gfar_read(&etsects->regs->tmr_etts1_h);
218                 lo = gfar_read(&etsects->regs->tmr_etts1_l);
219                 event.type = PTP_CLOCK_EXTTS;
220                 event.index = 0;
221                 event.timestamp = ((u64) hi) << 32;
222                 event.timestamp |= lo;
223                 ptp_clock_event(etsects->clock, &event);
224         }
225 
226         if (val & ETS2) {
227                 ack |= ETS2;
228                 hi = gfar_read(&etsects->regs->tmr_etts2_h);
229                 lo = gfar_read(&etsects->regs->tmr_etts2_l);
230                 event.type = PTP_CLOCK_EXTTS;
231                 event.index = 1;
232                 event.timestamp = ((u64) hi) << 32;
233                 event.timestamp |= lo;
234                 ptp_clock_event(etsects->clock, &event);
235         }
236 
237         if (val & ALM2) {
238                 ack |= ALM2;
239                 if (etsects->alarm_value) {
240                         event.type = PTP_CLOCK_ALARM;
241                         event.index = 0;
242                         event.timestamp = etsects->alarm_value;
243                         ptp_clock_event(etsects->clock, &event);
244                 }
245                 if (etsects->alarm_interval) {
246                         ns = etsects->alarm_value + etsects->alarm_interval;
247                         hi = ns >> 32;
248                         lo = ns & 0xffffffff;
249                         spin_lock(&etsects->lock);
250                         gfar_write(&etsects->regs->tmr_alarm2_l, lo);
251                         gfar_write(&etsects->regs->tmr_alarm2_h, hi);
252                         spin_unlock(&etsects->lock);
253                         etsects->alarm_value = ns;
254                 } else {
255                         gfar_write(&etsects->regs->tmr_tevent, ALM2);
256                         spin_lock(&etsects->lock);
257                         mask = gfar_read(&etsects->regs->tmr_temask);
258                         mask &= ~ALM2EN;
259                         gfar_write(&etsects->regs->tmr_temask, mask);
260                         spin_unlock(&etsects->lock);
261                         etsects->alarm_value = 0;
262                         etsects->alarm_interval = 0;
263                 }
264         }
265 
266         if (val & PP1) {
267                 ack |= PP1;
268                 event.type = PTP_CLOCK_PPS;
269                 ptp_clock_event(etsects->clock, &event);
270         }
271 
272         if (ack) {
273                 gfar_write(&etsects->regs->tmr_tevent, ack);
274                 return IRQ_HANDLED;
275         } else
276                 return IRQ_NONE;
277 }
278 
279 /*
280  * PTP clock operations
281  */
282 
283 static int ptp_gianfar_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
284 {
285         u64 adj;
286         u32 diff, tmr_add;
287         int neg_adj = 0;
288         struct etsects *etsects = container_of(ptp, struct etsects, caps);
289 
290         if (ppb < 0) {
291                 neg_adj = 1;
292                 ppb = -ppb;
293         }
294         tmr_add = etsects->tmr_add;
295         adj = tmr_add;
296         adj *= ppb;
297         diff = div_u64(adj, 1000000000ULL);
298 
299         tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff;
300 
301         gfar_write(&etsects->regs->tmr_add, tmr_add);
302 
303         return 0;
304 }
305 
306 static int ptp_gianfar_adjtime(struct ptp_clock_info *ptp, s64 delta)
307 {
308         s64 now;
309         unsigned long flags;
310         struct etsects *etsects = container_of(ptp, struct etsects, caps);
311 
312         spin_lock_irqsave(&etsects->lock, flags);
313 
314         now = tmr_cnt_read(etsects);
315         now += delta;
316         tmr_cnt_write(etsects, now);
317 
318         spin_unlock_irqrestore(&etsects->lock, flags);
319 
320         set_fipers(etsects);
321 
322         return 0;
323 }
324 
325 static int ptp_gianfar_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
326 {
327         u64 ns;
328         u32 remainder;
329         unsigned long flags;
330         struct etsects *etsects = container_of(ptp, struct etsects, caps);
331 
332         spin_lock_irqsave(&etsects->lock, flags);
333 
334         ns = tmr_cnt_read(etsects);
335 
336         spin_unlock_irqrestore(&etsects->lock, flags);
337 
338         ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
339         ts->tv_nsec = remainder;
340         return 0;
341 }
342 
343 static int ptp_gianfar_settime(struct ptp_clock_info *ptp,
344                                const struct timespec *ts)
345 {
346         u64 ns;
347         unsigned long flags;
348         struct etsects *etsects = container_of(ptp, struct etsects, caps);
349 
350         ns = ts->tv_sec * 1000000000ULL;
351         ns += ts->tv_nsec;
352 
353         spin_lock_irqsave(&etsects->lock, flags);
354 
355         tmr_cnt_write(etsects, ns);
356         set_fipers(etsects);
357 
358         spin_unlock_irqrestore(&etsects->lock, flags);
359 
360         return 0;
361 }
362 
363 static int ptp_gianfar_enable(struct ptp_clock_info *ptp,
364                               struct ptp_clock_request *rq, int on)
365 {
366         struct etsects *etsects = container_of(ptp, struct etsects, caps);
367         unsigned long flags;
368         u32 bit, mask;
369 
370         switch (rq->type) {
371         case PTP_CLK_REQ_EXTTS:
372                 switch (rq->extts.index) {
373                 case 0:
374                         bit = ETS1EN;
375                         break;
376                 case 1:
377                         bit = ETS2EN;
378                         break;
379                 default:
380                         return -EINVAL;
381                 }
382                 spin_lock_irqsave(&etsects->lock, flags);
383                 mask = gfar_read(&etsects->regs->tmr_temask);
384                 if (on)
385                         mask |= bit;
386                 else
387                         mask &= ~bit;
388                 gfar_write(&etsects->regs->tmr_temask, mask);
389                 spin_unlock_irqrestore(&etsects->lock, flags);
390                 return 0;
391 
392         case PTP_CLK_REQ_PPS:
393                 spin_lock_irqsave(&etsects->lock, flags);
394                 mask = gfar_read(&etsects->regs->tmr_temask);
395                 if (on)
396                         mask |= PP1EN;
397                 else
398                         mask &= ~PP1EN;
399                 gfar_write(&etsects->regs->tmr_temask, mask);
400                 spin_unlock_irqrestore(&etsects->lock, flags);
401                 return 0;
402 
403         default:
404                 break;
405         }
406 
407         return -EOPNOTSUPP;
408 }
409 
410 static struct ptp_clock_info ptp_gianfar_caps = {
411         .owner          = THIS_MODULE,
412         .name           = "gianfar clock",
413         .max_adj        = 512000,
414         .n_alarm        = 0,
415         .n_ext_ts       = N_EXT_TS,
416         .n_per_out      = 0,
417         .n_pins         = 0,
418         .pps            = 1,
419         .adjfreq        = ptp_gianfar_adjfreq,
420         .adjtime        = ptp_gianfar_adjtime,
421         .gettime        = ptp_gianfar_gettime,
422         .settime        = ptp_gianfar_settime,
423         .enable         = ptp_gianfar_enable,
424 };
425 
426 /* OF device tree */
427 
428 static int get_of_u32(struct device_node *node, char *str, u32 *val)
429 {
430         int plen;
431         const u32 *prop = of_get_property(node, str, &plen);
432 
433         if (!prop || plen != sizeof(*prop))
434                 return -1;
435         *val = *prop;
436         return 0;
437 }
438 
439 static int gianfar_ptp_probe(struct platform_device *dev)
440 {
441         struct device_node *node = dev->dev.of_node;
442         struct etsects *etsects;
443         struct timespec now;
444         int err = -ENOMEM;
445         u32 tmr_ctrl;
446         unsigned long flags;
447 
448         etsects = kzalloc(sizeof(*etsects), GFP_KERNEL);
449         if (!etsects)
450                 goto no_memory;
451 
452         err = -ENODEV;
453 
454         etsects->caps = ptp_gianfar_caps;
455 
456         if (get_of_u32(node, "fsl,cksel", &etsects->cksel))
457                 etsects->cksel = DEFAULT_CKSEL;
458 
459         if (get_of_u32(node, "fsl,tclk-period", &etsects->tclk_period) ||
460             get_of_u32(node, "fsl,tmr-prsc", &etsects->tmr_prsc) ||
461             get_of_u32(node, "fsl,tmr-add", &etsects->tmr_add) ||
462             get_of_u32(node, "fsl,tmr-fiper1", &etsects->tmr_fiper1) ||
463             get_of_u32(node, "fsl,tmr-fiper2", &etsects->tmr_fiper2) ||
464             get_of_u32(node, "fsl,max-adj", &etsects->caps.max_adj)) {
465                 pr_err("device tree node missing required elements\n");
466                 goto no_node;
467         }
468 
469         etsects->irq = platform_get_irq(dev, 0);
470 
471         if (etsects->irq == NO_IRQ) {
472                 pr_err("irq not in device tree\n");
473                 goto no_node;
474         }
475         if (request_irq(etsects->irq, isr, 0, DRIVER, etsects)) {
476                 pr_err("request_irq failed\n");
477                 goto no_node;
478         }
479 
480         etsects->rsrc = platform_get_resource(dev, IORESOURCE_MEM, 0);
481         if (!etsects->rsrc) {
482                 pr_err("no resource\n");
483                 goto no_resource;
484         }
485         if (request_resource(&iomem_resource, etsects->rsrc)) {
486                 pr_err("resource busy\n");
487                 goto no_resource;
488         }
489 
490         spin_lock_init(&etsects->lock);
491 
492         etsects->regs = ioremap(etsects->rsrc->start,
493                                 resource_size(etsects->rsrc));
494         if (!etsects->regs) {
495                 pr_err("ioremap ptp registers failed\n");
496                 goto no_ioremap;
497         }
498         getnstimeofday(&now);
499         ptp_gianfar_settime(&etsects->caps, &now);
500 
501         tmr_ctrl =
502           (etsects->tclk_period & TCLK_PERIOD_MASK) << TCLK_PERIOD_SHIFT |
503           (etsects->cksel & CKSEL_MASK) << CKSEL_SHIFT;
504 
505         spin_lock_irqsave(&etsects->lock, flags);
506 
507         gfar_write(&etsects->regs->tmr_ctrl,   tmr_ctrl);
508         gfar_write(&etsects->regs->tmr_add,    etsects->tmr_add);
509         gfar_write(&etsects->regs->tmr_prsc,   etsects->tmr_prsc);
510         gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
511         gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
512         set_alarm(etsects);
513         gfar_write(&etsects->regs->tmr_ctrl,   tmr_ctrl|FS|RTPE|TE|FRD);
514 
515         spin_unlock_irqrestore(&etsects->lock, flags);
516 
517         etsects->clock = ptp_clock_register(&etsects->caps, &dev->dev);
518         if (IS_ERR(etsects->clock)) {
519                 err = PTR_ERR(etsects->clock);
520                 goto no_clock;
521         }
522         gfar_phc_index = ptp_clock_index(etsects->clock);
523 
524         platform_set_drvdata(dev, etsects);
525 
526         return 0;
527 
528 no_clock:
529         iounmap(etsects->regs);
530 no_ioremap:
531         release_resource(etsects->rsrc);
532 no_resource:
533         free_irq(etsects->irq, etsects);
534 no_node:
535         kfree(etsects);
536 no_memory:
537         return err;
538 }
539 
540 static int gianfar_ptp_remove(struct platform_device *dev)
541 {
542         struct etsects *etsects = platform_get_drvdata(dev);
543 
544         gfar_write(&etsects->regs->tmr_temask, 0);
545         gfar_write(&etsects->regs->tmr_ctrl,   0);
546 
547         gfar_phc_index = -1;
548         ptp_clock_unregister(etsects->clock);
549         iounmap(etsects->regs);
550         release_resource(etsects->rsrc);
551         free_irq(etsects->irq, etsects);
552         kfree(etsects);
553 
554         return 0;
555 }
556 
557 static struct of_device_id match_table[] = {
558         { .compatible = "fsl,etsec-ptp" },
559         {},
560 };
561 
562 static struct platform_driver gianfar_ptp_driver = {
563         .driver = {
564                 .name           = "gianfar_ptp",
565                 .of_match_table = match_table,
566                 .owner          = THIS_MODULE,
567         },
568         .probe       = gianfar_ptp_probe,
569         .remove      = gianfar_ptp_remove,
570 };
571 
572 module_platform_driver(gianfar_ptp_driver);
573 
574 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
575 MODULE_DESCRIPTION("PTP clock using the eTSEC");
576 MODULE_LICENSE("GPL");
577 

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