Version:  2.0.40 2.2.26 2.4.37 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15

Linux/drivers/net/ethernet/freescale/fsl_pq_mdio.c

  1 /*
  2  * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
  3  * Provides Bus interface for MIIM regs
  4  *
  5  * Author: Andy Fleming <afleming@freescale.com>
  6  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  7  *
  8  * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
  9  *
 10  * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips)
 11  *
 12  * This program is free software; you can redistribute  it and/or modify it
 13  * under  the terms of  the GNU General  Public License as published by the
 14  * Free Software Foundation;  either version 2 of the  License, or (at your
 15  * option) any later version.
 16  *
 17  */
 18 
 19 #include <linux/kernel.h>
 20 #include <linux/string.h>
 21 #include <linux/errno.h>
 22 #include <linux/slab.h>
 23 #include <linux/delay.h>
 24 #include <linux/module.h>
 25 #include <linux/mii.h>
 26 #include <linux/of_address.h>
 27 #include <linux/of_mdio.h>
 28 #include <linux/of_device.h>
 29 
 30 #include <asm/io.h>
 31 #include <asm/ucc.h>    /* for ucc_set_qe_mux_mii_mng() */
 32 
 33 #include "gianfar.h"
 34 
 35 #define MIIMIND_BUSY            0x00000001
 36 #define MIIMIND_NOTVALID        0x00000004
 37 #define MIIMCFG_INIT_VALUE      0x00000007
 38 #define MIIMCFG_RESET           0x80000000
 39 
 40 #define MII_READ_COMMAND        0x00000001
 41 
 42 struct fsl_pq_mii {
 43         u32 miimcfg;    /* MII management configuration reg */
 44         u32 miimcom;    /* MII management command reg */
 45         u32 miimadd;    /* MII management address reg */
 46         u32 miimcon;    /* MII management control reg */
 47         u32 miimstat;   /* MII management status reg */
 48         u32 miimind;    /* MII management indication reg */
 49 };
 50 
 51 struct fsl_pq_mdio {
 52         u8 res1[16];
 53         u32 ieventm;    /* MDIO Interrupt event register (for etsec2)*/
 54         u32 imaskm;     /* MDIO Interrupt mask register (for etsec2)*/
 55         u8 res2[4];
 56         u32 emapm;      /* MDIO Event mapping register (for etsec2)*/
 57         u8 res3[1280];
 58         struct fsl_pq_mii mii;
 59         u8 res4[28];
 60         u32 utbipar;    /* TBI phy address reg (only on UCC) */
 61         u8 res5[2728];
 62 } __packed;
 63 
 64 /* Number of microseconds to wait for an MII register to respond */
 65 #define MII_TIMEOUT     1000
 66 
 67 struct fsl_pq_mdio_priv {
 68         void __iomem *map;
 69         struct fsl_pq_mii __iomem *regs;
 70         int irqs[PHY_MAX_ADDR];
 71 };
 72 
 73 /*
 74  * Per-device-type data.  Each type of device tree node that we support gets
 75  * one of these.
 76  *
 77  * @mii_offset: the offset of the MII registers within the memory map of the
 78  * node.  Some nodes define only the MII registers, and some define the whole
 79  * MAC (which includes the MII registers).
 80  *
 81  * @get_tbipa: determines the address of the TBIPA register
 82  *
 83  * @ucc_configure: a special function for extra QE configuration
 84  */
 85 struct fsl_pq_mdio_data {
 86         unsigned int mii_offset;        /* offset of the MII registers */
 87         uint32_t __iomem * (*get_tbipa)(void __iomem *p);
 88         void (*ucc_configure)(phys_addr_t start, phys_addr_t end);
 89 };
 90 
 91 /*
 92  * Write value to the PHY at mii_id at register regnum, on the bus attached
 93  * to the local interface, which may be different from the generic mdio bus
 94  * (tied to a single interface), waiting until the write is done before
 95  * returning. This is helpful in programming interfaces like the TBI which
 96  * control interfaces like onchip SERDES and are always tied to the local
 97  * mdio pins, which may not be the same as system mdio bus, used for
 98  * controlling the external PHYs, for example.
 99  */
100 static int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
101                 u16 value)
102 {
103         struct fsl_pq_mdio_priv *priv = bus->priv;
104         struct fsl_pq_mii __iomem *regs = priv->regs;
105         u32 status;
106 
107         /* Set the PHY address and the register address we want to write */
108         out_be32(&regs->miimadd, (mii_id << 8) | regnum);
109 
110         /* Write out the value we want */
111         out_be32(&regs->miimcon, value);
112 
113         /* Wait for the transaction to finish */
114         status = spin_event_timeout(!(in_be32(&regs->miimind) & MIIMIND_BUSY),
115                                     MII_TIMEOUT, 0);
116 
117         return status ? 0 : -ETIMEDOUT;
118 }
119 
120 /*
121  * Read the bus for PHY at addr mii_id, register regnum, and return the value.
122  * Clears miimcom first.
123  *
124  * All PHY operation done on the bus attached to the local interface, which
125  * may be different from the generic mdio bus.  This is helpful in programming
126  * interfaces like the TBI which, in turn, control interfaces like on-chip
127  * SERDES and are always tied to the local mdio pins, which may not be the
128  * same as system mdio bus, used for controlling the external PHYs, for eg.
129  */
130 static int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
131 {
132         struct fsl_pq_mdio_priv *priv = bus->priv;
133         struct fsl_pq_mii __iomem *regs = priv->regs;
134         u32 status;
135         u16 value;
136 
137         /* Set the PHY address and the register address we want to read */
138         out_be32(&regs->miimadd, (mii_id << 8) | regnum);
139 
140         /* Clear miimcom, and then initiate a read */
141         out_be32(&regs->miimcom, 0);
142         out_be32(&regs->miimcom, MII_READ_COMMAND);
143 
144         /* Wait for the transaction to finish, normally less than 100us */
145         status = spin_event_timeout(!(in_be32(&regs->miimind) &
146                                     (MIIMIND_NOTVALID | MIIMIND_BUSY)),
147                                     MII_TIMEOUT, 0);
148         if (!status)
149                 return -ETIMEDOUT;
150 
151         /* Grab the value of the register from miimstat */
152         value = in_be32(&regs->miimstat);
153 
154         dev_dbg(&bus->dev, "read %04x from address %x/%x\n", value, mii_id, regnum);
155         return value;
156 }
157 
158 /* Reset the MIIM registers, and wait for the bus to free */
159 static int fsl_pq_mdio_reset(struct mii_bus *bus)
160 {
161         struct fsl_pq_mdio_priv *priv = bus->priv;
162         struct fsl_pq_mii __iomem *regs = priv->regs;
163         u32 status;
164 
165         mutex_lock(&bus->mdio_lock);
166 
167         /* Reset the management interface */
168         out_be32(&regs->miimcfg, MIIMCFG_RESET);
169 
170         /* Setup the MII Mgmt clock speed */
171         out_be32(&regs->miimcfg, MIIMCFG_INIT_VALUE);
172 
173         /* Wait until the bus is free */
174         status = spin_event_timeout(!(in_be32(&regs->miimind) & MIIMIND_BUSY),
175                                     MII_TIMEOUT, 0);
176 
177         mutex_unlock(&bus->mdio_lock);
178 
179         if (!status) {
180                 dev_err(&bus->dev, "timeout waiting for MII bus\n");
181                 return -EBUSY;
182         }
183 
184         return 0;
185 }
186 
187 #if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE)
188 /*
189  * This is mildly evil, but so is our hardware for doing this.
190  * Also, we have to cast back to struct gfar because of
191  * definition weirdness done in gianfar.h.
192  */
193 static uint32_t __iomem *get_gfar_tbipa(void __iomem *p)
194 {
195         struct gfar __iomem *enet_regs = p;
196 
197         return &enet_regs->tbipa;
198 }
199 
200 /*
201  * Return the TBIPAR address for an eTSEC2 node
202  */
203 static uint32_t __iomem *get_etsec_tbipa(void __iomem *p)
204 {
205         return p;
206 }
207 #endif
208 
209 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE)
210 /*
211  * Return the TBIPAR address for a QE MDIO node
212  */
213 static uint32_t __iomem *get_ucc_tbipa(void __iomem *p)
214 {
215         struct fsl_pq_mdio __iomem *mdio = p;
216 
217         return &mdio->utbipar;
218 }
219 
220 /*
221  * Find the UCC node that controls the given MDIO node
222  *
223  * For some reason, the QE MDIO nodes are not children of the UCC devices
224  * that control them.  Therefore, we need to scan all UCC nodes looking for
225  * the one that encompases the given MDIO node.  We do this by comparing
226  * physical addresses.  The 'start' and 'end' addresses of the MDIO node are
227  * passed, and the correct UCC node will cover the entire address range.
228  *
229  * This assumes that there is only one QE MDIO node in the entire device tree.
230  */
231 static void ucc_configure(phys_addr_t start, phys_addr_t end)
232 {
233         static bool found_mii_master;
234         struct device_node *np = NULL;
235 
236         if (found_mii_master)
237                 return;
238 
239         for_each_compatible_node(np, NULL, "ucc_geth") {
240                 struct resource res;
241                 const uint32_t *iprop;
242                 uint32_t id;
243                 int ret;
244 
245                 ret = of_address_to_resource(np, 0, &res);
246                 if (ret < 0) {
247                         pr_debug("fsl-pq-mdio: no address range in node %s\n",
248                                  np->full_name);
249                         continue;
250                 }
251 
252                 /* if our mdio regs fall within this UCC regs range */
253                 if ((start < res.start) || (end > res.end))
254                         continue;
255 
256                 iprop = of_get_property(np, "cell-index", NULL);
257                 if (!iprop) {
258                         iprop = of_get_property(np, "device-id", NULL);
259                         if (!iprop) {
260                                 pr_debug("fsl-pq-mdio: no UCC ID in node %s\n",
261                                          np->full_name);
262                                 continue;
263                         }
264                 }
265 
266                 id = be32_to_cpup(iprop);
267 
268                 /*
269                  * cell-index and device-id for QE nodes are
270                  * numbered from 1, not 0.
271                  */
272                 if (ucc_set_qe_mux_mii_mng(id - 1) < 0) {
273                         pr_debug("fsl-pq-mdio: invalid UCC ID in node %s\n",
274                                  np->full_name);
275                         continue;
276                 }
277 
278                 pr_debug("fsl-pq-mdio: setting node UCC%u to MII master\n", id);
279                 found_mii_master = true;
280         }
281 }
282 
283 #endif
284 
285 static struct of_device_id fsl_pq_mdio_match[] = {
286 #if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE)
287         {
288                 .compatible = "fsl,gianfar-tbi",
289                 .data = &(struct fsl_pq_mdio_data) {
290                         .mii_offset = 0,
291                         .get_tbipa = get_gfar_tbipa,
292                 },
293         },
294         {
295                 .compatible = "fsl,gianfar-mdio",
296                 .data = &(struct fsl_pq_mdio_data) {
297                         .mii_offset = 0,
298                         .get_tbipa = get_gfar_tbipa,
299                 },
300         },
301         {
302                 .type = "mdio",
303                 .compatible = "gianfar",
304                 .data = &(struct fsl_pq_mdio_data) {
305                         .mii_offset = offsetof(struct fsl_pq_mdio, mii),
306                         .get_tbipa = get_gfar_tbipa,
307                 },
308         },
309         {
310                 .compatible = "fsl,etsec2-tbi",
311                 .data = &(struct fsl_pq_mdio_data) {
312                         .mii_offset = offsetof(struct fsl_pq_mdio, mii),
313                         .get_tbipa = get_etsec_tbipa,
314                 },
315         },
316         {
317                 .compatible = "fsl,etsec2-mdio",
318                 .data = &(struct fsl_pq_mdio_data) {
319                         .mii_offset = offsetof(struct fsl_pq_mdio, mii),
320                         .get_tbipa = get_etsec_tbipa,
321                 },
322         },
323 #endif
324 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE)
325         {
326                 .compatible = "fsl,ucc-mdio",
327                 .data = &(struct fsl_pq_mdio_data) {
328                         .mii_offset = 0,
329                         .get_tbipa = get_ucc_tbipa,
330                         .ucc_configure = ucc_configure,
331                 },
332         },
333         {
334                 /* Legacy UCC MDIO node */
335                 .type = "mdio",
336                 .compatible = "ucc_geth_phy",
337                 .data = &(struct fsl_pq_mdio_data) {
338                         .mii_offset = 0,
339                         .get_tbipa = get_ucc_tbipa,
340                         .ucc_configure = ucc_configure,
341                 },
342         },
343 #endif
344         /* No Kconfig option for Fman support yet */
345         {
346                 .compatible = "fsl,fman-mdio",
347                 .data = &(struct fsl_pq_mdio_data) {
348                         .mii_offset = 0,
349                         /* Fman TBI operations are handled elsewhere */
350                 },
351         },
352 
353         {},
354 };
355 MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match);
356 
357 static int fsl_pq_mdio_probe(struct platform_device *pdev)
358 {
359         const struct of_device_id *id =
360                 of_match_device(fsl_pq_mdio_match, &pdev->dev);
361         const struct fsl_pq_mdio_data *data = id->data;
362         struct device_node *np = pdev->dev.of_node;
363         struct resource res;
364         struct device_node *tbi;
365         struct fsl_pq_mdio_priv *priv;
366         struct mii_bus *new_bus;
367         int err;
368 
369         dev_dbg(&pdev->dev, "found %s compatible node\n", id->compatible);
370 
371         new_bus = mdiobus_alloc_size(sizeof(*priv));
372         if (!new_bus)
373                 return -ENOMEM;
374 
375         priv = new_bus->priv;
376         new_bus->name = "Freescale PowerQUICC MII Bus",
377         new_bus->read = &fsl_pq_mdio_read;
378         new_bus->write = &fsl_pq_mdio_write;
379         new_bus->reset = &fsl_pq_mdio_reset;
380         new_bus->irq = priv->irqs;
381 
382         err = of_address_to_resource(np, 0, &res);
383         if (err < 0) {
384                 dev_err(&pdev->dev, "could not obtain address information\n");
385                 goto error;
386         }
387 
388         snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s@%llx", np->name,
389                 (unsigned long long)res.start);
390 
391         priv->map = of_iomap(np, 0);
392         if (!priv->map) {
393                 err = -ENOMEM;
394                 goto error;
395         }
396 
397         /*
398          * Some device tree nodes represent only the MII registers, and
399          * others represent the MAC and MII registers.  The 'mii_offset' field
400          * contains the offset of the MII registers inside the mapped register
401          * space.
402          */
403         if (data->mii_offset > resource_size(&res)) {
404                 dev_err(&pdev->dev, "invalid register map\n");
405                 err = -EINVAL;
406                 goto error;
407         }
408         priv->regs = priv->map + data->mii_offset;
409 
410         new_bus->parent = &pdev->dev;
411         platform_set_drvdata(pdev, new_bus);
412 
413         if (data->get_tbipa) {
414                 for_each_child_of_node(np, tbi) {
415                         if (strcmp(tbi->type, "tbi-phy") == 0) {
416                                 dev_dbg(&pdev->dev, "found TBI PHY node %s\n",
417                                         strrchr(tbi->full_name, '/') + 1);
418                                 break;
419                         }
420                 }
421 
422                 if (tbi) {
423                         const u32 *prop = of_get_property(tbi, "reg", NULL);
424                         uint32_t __iomem *tbipa;
425 
426                         if (!prop) {
427                                 dev_err(&pdev->dev,
428                                         "missing 'reg' property in node %s\n",
429                                         tbi->full_name);
430                                 err = -EBUSY;
431                                 goto error;
432                         }
433 
434                         tbipa = data->get_tbipa(priv->map);
435 
436                         out_be32(tbipa, be32_to_cpup(prop));
437                 }
438         }
439 
440         if (data->ucc_configure)
441                 data->ucc_configure(res.start, res.end);
442 
443         err = of_mdiobus_register(new_bus, np);
444         if (err) {
445                 dev_err(&pdev->dev, "cannot register %s as MDIO bus\n",
446                         new_bus->name);
447                 goto error;
448         }
449 
450         return 0;
451 
452 error:
453         if (priv->map)
454                 iounmap(priv->map);
455 
456         kfree(new_bus);
457 
458         return err;
459 }
460 
461 
462 static int fsl_pq_mdio_remove(struct platform_device *pdev)
463 {
464         struct device *device = &pdev->dev;
465         struct mii_bus *bus = dev_get_drvdata(device);
466         struct fsl_pq_mdio_priv *priv = bus->priv;
467 
468         mdiobus_unregister(bus);
469 
470         iounmap(priv->map);
471         mdiobus_free(bus);
472 
473         return 0;
474 }
475 
476 static struct platform_driver fsl_pq_mdio_driver = {
477         .driver = {
478                 .name = "fsl-pq_mdio",
479                 .owner = THIS_MODULE,
480                 .of_match_table = fsl_pq_mdio_match,
481         },
482         .probe = fsl_pq_mdio_probe,
483         .remove = fsl_pq_mdio_remove,
484 };
485 
486 module_platform_driver(fsl_pq_mdio_driver);
487 
488 MODULE_LICENSE("GPL");
489 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us