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Linux/drivers/net/ethernet/faraday/ftgmac100.c

  1 /*
  2  * Faraday FTGMAC100 Gigabit Ethernet
  3  *
  4  * (C) Copyright 2009-2011 Faraday Technology
  5  * Po-Yu Chuang <ratbert@faraday-tech.com>
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License as published by
  9  * the Free Software Foundation; either version 2 of the License, or
 10  * (at your option) any later version.
 11  *
 12  * This program is distributed in the hope that it will be useful,
 13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 15  * GNU General Public License for more details.
 16  *
 17  * You should have received a copy of the GNU General Public License
 18  * along with this program; if not, write to the Free Software
 19  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 20  */
 21 
 22 #define pr_fmt(fmt)     KBUILD_MODNAME ": " fmt
 23 
 24 #include <linux/dma-mapping.h>
 25 #include <linux/etherdevice.h>
 26 #include <linux/ethtool.h>
 27 #include <linux/interrupt.h>
 28 #include <linux/io.h>
 29 #include <linux/module.h>
 30 #include <linux/netdevice.h>
 31 #include <linux/phy.h>
 32 #include <linux/platform_device.h>
 33 #include <net/ip.h>
 34 #include <net/ncsi.h>
 35 
 36 #include "ftgmac100.h"
 37 
 38 #define DRV_NAME        "ftgmac100"
 39 #define DRV_VERSION     "0.7"
 40 
 41 #define RX_QUEUE_ENTRIES        256     /* must be power of 2 */
 42 #define TX_QUEUE_ENTRIES        512     /* must be power of 2 */
 43 
 44 #define MAX_PKT_SIZE            1518
 45 #define RX_BUF_SIZE             PAGE_SIZE       /* must be smaller than 0x3fff */
 46 
 47 /******************************************************************************
 48  * private data
 49  *****************************************************************************/
 50 struct ftgmac100_descs {
 51         struct ftgmac100_rxdes rxdes[RX_QUEUE_ENTRIES];
 52         struct ftgmac100_txdes txdes[TX_QUEUE_ENTRIES];
 53 };
 54 
 55 struct ftgmac100 {
 56         struct resource *res;
 57         void __iomem *base;
 58         int irq;
 59 
 60         struct ftgmac100_descs *descs;
 61         dma_addr_t descs_dma_addr;
 62 
 63         unsigned int rx_pointer;
 64         unsigned int tx_clean_pointer;
 65         unsigned int tx_pointer;
 66         unsigned int tx_pending;
 67 
 68         spinlock_t tx_lock;
 69 
 70         struct net_device *netdev;
 71         struct device *dev;
 72         struct ncsi_dev *ndev;
 73         struct napi_struct napi;
 74 
 75         struct mii_bus *mii_bus;
 76         int old_speed;
 77         int int_mask_all;
 78         bool use_ncsi;
 79         bool enabled;
 80 };
 81 
 82 static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv,
 83                                    struct ftgmac100_rxdes *rxdes, gfp_t gfp);
 84 
 85 /******************************************************************************
 86  * internal functions (hardware register access)
 87  *****************************************************************************/
 88 static void ftgmac100_set_rx_ring_base(struct ftgmac100 *priv, dma_addr_t addr)
 89 {
 90         iowrite32(addr, priv->base + FTGMAC100_OFFSET_RXR_BADR);
 91 }
 92 
 93 static void ftgmac100_set_rx_buffer_size(struct ftgmac100 *priv,
 94                 unsigned int size)
 95 {
 96         size = FTGMAC100_RBSR_SIZE(size);
 97         iowrite32(size, priv->base + FTGMAC100_OFFSET_RBSR);
 98 }
 99 
100 static void ftgmac100_set_normal_prio_tx_ring_base(struct ftgmac100 *priv,
101                                                    dma_addr_t addr)
102 {
103         iowrite32(addr, priv->base + FTGMAC100_OFFSET_NPTXR_BADR);
104 }
105 
106 static void ftgmac100_txdma_normal_prio_start_polling(struct ftgmac100 *priv)
107 {
108         iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD);
109 }
110 
111 static int ftgmac100_reset_hw(struct ftgmac100 *priv)
112 {
113         struct net_device *netdev = priv->netdev;
114         int i;
115 
116         /* NOTE: reset clears all registers */
117         iowrite32(FTGMAC100_MACCR_SW_RST, priv->base + FTGMAC100_OFFSET_MACCR);
118         for (i = 0; i < 5; i++) {
119                 unsigned int maccr;
120 
121                 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
122                 if (!(maccr & FTGMAC100_MACCR_SW_RST))
123                         return 0;
124 
125                 udelay(1000);
126         }
127 
128         netdev_err(netdev, "software reset failed\n");
129         return -EIO;
130 }
131 
132 static void ftgmac100_set_mac(struct ftgmac100 *priv, const unsigned char *mac)
133 {
134         unsigned int maddr = mac[0] << 8 | mac[1];
135         unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
136 
137         iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR);
138         iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR);
139 }
140 
141 static void ftgmac100_setup_mac(struct ftgmac100 *priv)
142 {
143         u8 mac[ETH_ALEN];
144         unsigned int m;
145         unsigned int l;
146         void *addr;
147 
148         addr = device_get_mac_address(priv->dev, mac, ETH_ALEN);
149         if (addr) {
150                 ether_addr_copy(priv->netdev->dev_addr, mac);
151                 dev_info(priv->dev, "Read MAC address %pM from device tree\n",
152                          mac);
153                 return;
154         }
155 
156         m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR);
157         l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR);
158 
159         mac[0] = (m >> 8) & 0xff;
160         mac[1] = m & 0xff;
161         mac[2] = (l >> 24) & 0xff;
162         mac[3] = (l >> 16) & 0xff;
163         mac[4] = (l >> 8) & 0xff;
164         mac[5] = l & 0xff;
165 
166         if (is_valid_ether_addr(mac)) {
167                 ether_addr_copy(priv->netdev->dev_addr, mac);
168                 dev_info(priv->dev, "Read MAC address %pM from chip\n", mac);
169         } else {
170                 eth_hw_addr_random(priv->netdev);
171                 dev_info(priv->dev, "Generated random MAC address %pM\n",
172                          priv->netdev->dev_addr);
173         }
174 }
175 
176 static int ftgmac100_set_mac_addr(struct net_device *dev, void *p)
177 {
178         int ret;
179 
180         ret = eth_prepare_mac_addr_change(dev, p);
181         if (ret < 0)
182                 return ret;
183 
184         eth_commit_mac_addr_change(dev, p);
185         ftgmac100_set_mac(netdev_priv(dev), dev->dev_addr);
186 
187         return 0;
188 }
189 
190 static void ftgmac100_init_hw(struct ftgmac100 *priv)
191 {
192         /* setup ring buffer base registers */
193         ftgmac100_set_rx_ring_base(priv,
194                                    priv->descs_dma_addr +
195                                    offsetof(struct ftgmac100_descs, rxdes));
196         ftgmac100_set_normal_prio_tx_ring_base(priv,
197                                                priv->descs_dma_addr +
198                                                offsetof(struct ftgmac100_descs, txdes));
199 
200         ftgmac100_set_rx_buffer_size(priv, RX_BUF_SIZE);
201 
202         iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1), priv->base + FTGMAC100_OFFSET_APTC);
203 
204         ftgmac100_set_mac(priv, priv->netdev->dev_addr);
205 }
206 
207 #define MACCR_ENABLE_ALL        (FTGMAC100_MACCR_TXDMA_EN       | \
208                                  FTGMAC100_MACCR_RXDMA_EN       | \
209                                  FTGMAC100_MACCR_TXMAC_EN       | \
210                                  FTGMAC100_MACCR_RXMAC_EN       | \
211                                  FTGMAC100_MACCR_FULLDUP        | \
212                                  FTGMAC100_MACCR_CRC_APD        | \
213                                  FTGMAC100_MACCR_RX_RUNT        | \
214                                  FTGMAC100_MACCR_RX_BROADPKT)
215 
216 static void ftgmac100_start_hw(struct ftgmac100 *priv, int speed)
217 {
218         int maccr = MACCR_ENABLE_ALL;
219 
220         switch (speed) {
221         default:
222         case 10:
223                 break;
224 
225         case 100:
226                 maccr |= FTGMAC100_MACCR_FAST_MODE;
227                 break;
228 
229         case 1000:
230                 maccr |= FTGMAC100_MACCR_GIGA_MODE;
231                 break;
232         }
233 
234         iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
235 }
236 
237 static void ftgmac100_stop_hw(struct ftgmac100 *priv)
238 {
239         iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR);
240 }
241 
242 /******************************************************************************
243  * internal functions (receive descriptor)
244  *****************************************************************************/
245 static bool ftgmac100_rxdes_first_segment(struct ftgmac100_rxdes *rxdes)
246 {
247         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FRS);
248 }
249 
250 static bool ftgmac100_rxdes_last_segment(struct ftgmac100_rxdes *rxdes)
251 {
252         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_LRS);
253 }
254 
255 static bool ftgmac100_rxdes_packet_ready(struct ftgmac100_rxdes *rxdes)
256 {
257         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY);
258 }
259 
260 static void ftgmac100_rxdes_set_dma_own(struct ftgmac100_rxdes *rxdes)
261 {
262         /* clear status bits */
263         rxdes->rxdes0 &= cpu_to_le32(FTGMAC100_RXDES0_EDORR);
264 }
265 
266 static bool ftgmac100_rxdes_rx_error(struct ftgmac100_rxdes *rxdes)
267 {
268         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ERR);
269 }
270 
271 static bool ftgmac100_rxdes_crc_error(struct ftgmac100_rxdes *rxdes)
272 {
273         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_CRC_ERR);
274 }
275 
276 static bool ftgmac100_rxdes_frame_too_long(struct ftgmac100_rxdes *rxdes)
277 {
278         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FTL);
279 }
280 
281 static bool ftgmac100_rxdes_runt(struct ftgmac100_rxdes *rxdes)
282 {
283         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RUNT);
284 }
285 
286 static bool ftgmac100_rxdes_odd_nibble(struct ftgmac100_rxdes *rxdes)
287 {
288         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ODD_NB);
289 }
290 
291 static unsigned int ftgmac100_rxdes_data_length(struct ftgmac100_rxdes *rxdes)
292 {
293         return le32_to_cpu(rxdes->rxdes0) & FTGMAC100_RXDES0_VDBC;
294 }
295 
296 static bool ftgmac100_rxdes_multicast(struct ftgmac100_rxdes *rxdes)
297 {
298         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_MULTICAST);
299 }
300 
301 static void ftgmac100_rxdes_set_end_of_ring(struct ftgmac100_rxdes *rxdes)
302 {
303         rxdes->rxdes0 |= cpu_to_le32(FTGMAC100_RXDES0_EDORR);
304 }
305 
306 static void ftgmac100_rxdes_set_dma_addr(struct ftgmac100_rxdes *rxdes,
307                                          dma_addr_t addr)
308 {
309         rxdes->rxdes3 = cpu_to_le32(addr);
310 }
311 
312 static dma_addr_t ftgmac100_rxdes_get_dma_addr(struct ftgmac100_rxdes *rxdes)
313 {
314         return le32_to_cpu(rxdes->rxdes3);
315 }
316 
317 static bool ftgmac100_rxdes_is_tcp(struct ftgmac100_rxdes *rxdes)
318 {
319         return (rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)) ==
320                cpu_to_le32(FTGMAC100_RXDES1_PROT_TCPIP);
321 }
322 
323 static bool ftgmac100_rxdes_is_udp(struct ftgmac100_rxdes *rxdes)
324 {
325         return (rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)) ==
326                cpu_to_le32(FTGMAC100_RXDES1_PROT_UDPIP);
327 }
328 
329 static bool ftgmac100_rxdes_tcpcs_err(struct ftgmac100_rxdes *rxdes)
330 {
331         return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_TCP_CHKSUM_ERR);
332 }
333 
334 static bool ftgmac100_rxdes_udpcs_err(struct ftgmac100_rxdes *rxdes)
335 {
336         return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_UDP_CHKSUM_ERR);
337 }
338 
339 static bool ftgmac100_rxdes_ipcs_err(struct ftgmac100_rxdes *rxdes)
340 {
341         return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_IP_CHKSUM_ERR);
342 }
343 
344 /*
345  * rxdes2 is not used by hardware. We use it to keep track of page.
346  * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
347  */
348 static void ftgmac100_rxdes_set_page(struct ftgmac100_rxdes *rxdes, struct page *page)
349 {
350         rxdes->rxdes2 = (unsigned int)page;
351 }
352 
353 static struct page *ftgmac100_rxdes_get_page(struct ftgmac100_rxdes *rxdes)
354 {
355         return (struct page *)rxdes->rxdes2;
356 }
357 
358 /******************************************************************************
359  * internal functions (receive)
360  *****************************************************************************/
361 static int ftgmac100_next_rx_pointer(int pointer)
362 {
363         return (pointer + 1) & (RX_QUEUE_ENTRIES - 1);
364 }
365 
366 static void ftgmac100_rx_pointer_advance(struct ftgmac100 *priv)
367 {
368         priv->rx_pointer = ftgmac100_next_rx_pointer(priv->rx_pointer);
369 }
370 
371 static struct ftgmac100_rxdes *ftgmac100_current_rxdes(struct ftgmac100 *priv)
372 {
373         return &priv->descs->rxdes[priv->rx_pointer];
374 }
375 
376 static struct ftgmac100_rxdes *
377 ftgmac100_rx_locate_first_segment(struct ftgmac100 *priv)
378 {
379         struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv);
380 
381         while (ftgmac100_rxdes_packet_ready(rxdes)) {
382                 if (ftgmac100_rxdes_first_segment(rxdes))
383                         return rxdes;
384 
385                 ftgmac100_rxdes_set_dma_own(rxdes);
386                 ftgmac100_rx_pointer_advance(priv);
387                 rxdes = ftgmac100_current_rxdes(priv);
388         }
389 
390         return NULL;
391 }
392 
393 static bool ftgmac100_rx_packet_error(struct ftgmac100 *priv,
394                                       struct ftgmac100_rxdes *rxdes)
395 {
396         struct net_device *netdev = priv->netdev;
397         bool error = false;
398 
399         if (unlikely(ftgmac100_rxdes_rx_error(rxdes))) {
400                 if (net_ratelimit())
401                         netdev_info(netdev, "rx err\n");
402 
403                 netdev->stats.rx_errors++;
404                 error = true;
405         }
406 
407         if (unlikely(ftgmac100_rxdes_crc_error(rxdes))) {
408                 if (net_ratelimit())
409                         netdev_info(netdev, "rx crc err\n");
410 
411                 netdev->stats.rx_crc_errors++;
412                 error = true;
413         } else if (unlikely(ftgmac100_rxdes_ipcs_err(rxdes))) {
414                 if (net_ratelimit())
415                         netdev_info(netdev, "rx IP checksum err\n");
416 
417                 error = true;
418         }
419 
420         if (unlikely(ftgmac100_rxdes_frame_too_long(rxdes))) {
421                 if (net_ratelimit())
422                         netdev_info(netdev, "rx frame too long\n");
423 
424                 netdev->stats.rx_length_errors++;
425                 error = true;
426         } else if (unlikely(ftgmac100_rxdes_runt(rxdes))) {
427                 if (net_ratelimit())
428                         netdev_info(netdev, "rx runt\n");
429 
430                 netdev->stats.rx_length_errors++;
431                 error = true;
432         } else if (unlikely(ftgmac100_rxdes_odd_nibble(rxdes))) {
433                 if (net_ratelimit())
434                         netdev_info(netdev, "rx odd nibble\n");
435 
436                 netdev->stats.rx_length_errors++;
437                 error = true;
438         }
439 
440         return error;
441 }
442 
443 static void ftgmac100_rx_drop_packet(struct ftgmac100 *priv)
444 {
445         struct net_device *netdev = priv->netdev;
446         struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv);
447         bool done = false;
448 
449         if (net_ratelimit())
450                 netdev_dbg(netdev, "drop packet %p\n", rxdes);
451 
452         do {
453                 if (ftgmac100_rxdes_last_segment(rxdes))
454                         done = true;
455 
456                 ftgmac100_rxdes_set_dma_own(rxdes);
457                 ftgmac100_rx_pointer_advance(priv);
458                 rxdes = ftgmac100_current_rxdes(priv);
459         } while (!done && ftgmac100_rxdes_packet_ready(rxdes));
460 
461         netdev->stats.rx_dropped++;
462 }
463 
464 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed)
465 {
466         struct net_device *netdev = priv->netdev;
467         struct ftgmac100_rxdes *rxdes;
468         struct sk_buff *skb;
469         bool done = false;
470 
471         rxdes = ftgmac100_rx_locate_first_segment(priv);
472         if (!rxdes)
473                 return false;
474 
475         if (unlikely(ftgmac100_rx_packet_error(priv, rxdes))) {
476                 ftgmac100_rx_drop_packet(priv);
477                 return true;
478         }
479 
480         /* start processing */
481         skb = netdev_alloc_skb_ip_align(netdev, 128);
482         if (unlikely(!skb)) {
483                 if (net_ratelimit())
484                         netdev_err(netdev, "rx skb alloc failed\n");
485 
486                 ftgmac100_rx_drop_packet(priv);
487                 return true;
488         }
489 
490         if (unlikely(ftgmac100_rxdes_multicast(rxdes)))
491                 netdev->stats.multicast++;
492 
493         /*
494          * It seems that HW does checksum incorrectly with fragmented packets,
495          * so we are conservative here - if HW checksum error, let software do
496          * the checksum again.
497          */
498         if ((ftgmac100_rxdes_is_tcp(rxdes) && !ftgmac100_rxdes_tcpcs_err(rxdes)) ||
499             (ftgmac100_rxdes_is_udp(rxdes) && !ftgmac100_rxdes_udpcs_err(rxdes)))
500                 skb->ip_summed = CHECKSUM_UNNECESSARY;
501 
502         do {
503                 dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes);
504                 struct page *page = ftgmac100_rxdes_get_page(rxdes);
505                 unsigned int size;
506 
507                 dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
508 
509                 size = ftgmac100_rxdes_data_length(rxdes);
510                 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, page, 0, size);
511 
512                 skb->len += size;
513                 skb->data_len += size;
514                 skb->truesize += PAGE_SIZE;
515 
516                 if (ftgmac100_rxdes_last_segment(rxdes))
517                         done = true;
518 
519                 ftgmac100_alloc_rx_page(priv, rxdes, GFP_ATOMIC);
520 
521                 ftgmac100_rx_pointer_advance(priv);
522                 rxdes = ftgmac100_current_rxdes(priv);
523         } while (!done);
524 
525         /* Small frames are copied into linear part of skb to free one page */
526         if (skb->len <= 128) {
527                 skb->truesize -= PAGE_SIZE;
528                 __pskb_pull_tail(skb, skb->len);
529         } else {
530                 /* We pull the minimum amount into linear part */
531                 __pskb_pull_tail(skb, ETH_HLEN);
532         }
533         skb->protocol = eth_type_trans(skb, netdev);
534 
535         netdev->stats.rx_packets++;
536         netdev->stats.rx_bytes += skb->len;
537 
538         /* push packet to protocol stack */
539         napi_gro_receive(&priv->napi, skb);
540 
541         (*processed)++;
542         return true;
543 }
544 
545 /******************************************************************************
546  * internal functions (transmit descriptor)
547  *****************************************************************************/
548 static void ftgmac100_txdes_reset(struct ftgmac100_txdes *txdes)
549 {
550         /* clear all except end of ring bit */
551         txdes->txdes0 &= cpu_to_le32(FTGMAC100_TXDES0_EDOTR);
552         txdes->txdes1 = 0;
553         txdes->txdes2 = 0;
554         txdes->txdes3 = 0;
555 }
556 
557 static bool ftgmac100_txdes_owned_by_dma(struct ftgmac100_txdes *txdes)
558 {
559         return txdes->txdes0 & cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN);
560 }
561 
562 static void ftgmac100_txdes_set_dma_own(struct ftgmac100_txdes *txdes)
563 {
564         /*
565          * Make sure dma own bit will not be set before any other
566          * descriptor fields.
567          */
568         wmb();
569         txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN);
570 }
571 
572 static void ftgmac100_txdes_set_end_of_ring(struct ftgmac100_txdes *txdes)
573 {
574         txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_EDOTR);
575 }
576 
577 static void ftgmac100_txdes_set_first_segment(struct ftgmac100_txdes *txdes)
578 {
579         txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_FTS);
580 }
581 
582 static void ftgmac100_txdes_set_last_segment(struct ftgmac100_txdes *txdes)
583 {
584         txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_LTS);
585 }
586 
587 static void ftgmac100_txdes_set_buffer_size(struct ftgmac100_txdes *txdes,
588                                             unsigned int len)
589 {
590         txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXBUF_SIZE(len));
591 }
592 
593 static void ftgmac100_txdes_set_txint(struct ftgmac100_txdes *txdes)
594 {
595         txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TXIC);
596 }
597 
598 static void ftgmac100_txdes_set_tcpcs(struct ftgmac100_txdes *txdes)
599 {
600         txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TCP_CHKSUM);
601 }
602 
603 static void ftgmac100_txdes_set_udpcs(struct ftgmac100_txdes *txdes)
604 {
605         txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_UDP_CHKSUM);
606 }
607 
608 static void ftgmac100_txdes_set_ipcs(struct ftgmac100_txdes *txdes)
609 {
610         txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_IP_CHKSUM);
611 }
612 
613 static void ftgmac100_txdes_set_dma_addr(struct ftgmac100_txdes *txdes,
614                                          dma_addr_t addr)
615 {
616         txdes->txdes3 = cpu_to_le32(addr);
617 }
618 
619 static dma_addr_t ftgmac100_txdes_get_dma_addr(struct ftgmac100_txdes *txdes)
620 {
621         return le32_to_cpu(txdes->txdes3);
622 }
623 
624 /*
625  * txdes2 is not used by hardware. We use it to keep track of socket buffer.
626  * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
627  */
628 static void ftgmac100_txdes_set_skb(struct ftgmac100_txdes *txdes,
629                                     struct sk_buff *skb)
630 {
631         txdes->txdes2 = (unsigned int)skb;
632 }
633 
634 static struct sk_buff *ftgmac100_txdes_get_skb(struct ftgmac100_txdes *txdes)
635 {
636         return (struct sk_buff *)txdes->txdes2;
637 }
638 
639 /******************************************************************************
640  * internal functions (transmit)
641  *****************************************************************************/
642 static int ftgmac100_next_tx_pointer(int pointer)
643 {
644         return (pointer + 1) & (TX_QUEUE_ENTRIES - 1);
645 }
646 
647 static void ftgmac100_tx_pointer_advance(struct ftgmac100 *priv)
648 {
649         priv->tx_pointer = ftgmac100_next_tx_pointer(priv->tx_pointer);
650 }
651 
652 static void ftgmac100_tx_clean_pointer_advance(struct ftgmac100 *priv)
653 {
654         priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv->tx_clean_pointer);
655 }
656 
657 static struct ftgmac100_txdes *ftgmac100_current_txdes(struct ftgmac100 *priv)
658 {
659         return &priv->descs->txdes[priv->tx_pointer];
660 }
661 
662 static struct ftgmac100_txdes *
663 ftgmac100_current_clean_txdes(struct ftgmac100 *priv)
664 {
665         return &priv->descs->txdes[priv->tx_clean_pointer];
666 }
667 
668 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv)
669 {
670         struct net_device *netdev = priv->netdev;
671         struct ftgmac100_txdes *txdes;
672         struct sk_buff *skb;
673         dma_addr_t map;
674 
675         if (priv->tx_pending == 0)
676                 return false;
677 
678         txdes = ftgmac100_current_clean_txdes(priv);
679 
680         if (ftgmac100_txdes_owned_by_dma(txdes))
681                 return false;
682 
683         skb = ftgmac100_txdes_get_skb(txdes);
684         map = ftgmac100_txdes_get_dma_addr(txdes);
685 
686         netdev->stats.tx_packets++;
687         netdev->stats.tx_bytes += skb->len;
688 
689         dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
690 
691         dev_kfree_skb(skb);
692 
693         ftgmac100_txdes_reset(txdes);
694 
695         ftgmac100_tx_clean_pointer_advance(priv);
696 
697         spin_lock(&priv->tx_lock);
698         priv->tx_pending--;
699         spin_unlock(&priv->tx_lock);
700         netif_wake_queue(netdev);
701 
702         return true;
703 }
704 
705 static void ftgmac100_tx_complete(struct ftgmac100 *priv)
706 {
707         while (ftgmac100_tx_complete_packet(priv))
708                 ;
709 }
710 
711 static int ftgmac100_xmit(struct ftgmac100 *priv, struct sk_buff *skb,
712                           dma_addr_t map)
713 {
714         struct net_device *netdev = priv->netdev;
715         struct ftgmac100_txdes *txdes;
716         unsigned int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len;
717 
718         txdes = ftgmac100_current_txdes(priv);
719         ftgmac100_tx_pointer_advance(priv);
720 
721         /* setup TX descriptor */
722         ftgmac100_txdes_set_skb(txdes, skb);
723         ftgmac100_txdes_set_dma_addr(txdes, map);
724         ftgmac100_txdes_set_buffer_size(txdes, len);
725 
726         ftgmac100_txdes_set_first_segment(txdes);
727         ftgmac100_txdes_set_last_segment(txdes);
728         ftgmac100_txdes_set_txint(txdes);
729         if (skb->ip_summed == CHECKSUM_PARTIAL) {
730                 __be16 protocol = skb->protocol;
731 
732                 if (protocol == cpu_to_be16(ETH_P_IP)) {
733                         u8 ip_proto = ip_hdr(skb)->protocol;
734 
735                         ftgmac100_txdes_set_ipcs(txdes);
736                         if (ip_proto == IPPROTO_TCP)
737                                 ftgmac100_txdes_set_tcpcs(txdes);
738                         else if (ip_proto == IPPROTO_UDP)
739                                 ftgmac100_txdes_set_udpcs(txdes);
740                 }
741         }
742 
743         spin_lock(&priv->tx_lock);
744         priv->tx_pending++;
745         if (priv->tx_pending == TX_QUEUE_ENTRIES)
746                 netif_stop_queue(netdev);
747 
748         /* start transmit */
749         ftgmac100_txdes_set_dma_own(txdes);
750         spin_unlock(&priv->tx_lock);
751 
752         ftgmac100_txdma_normal_prio_start_polling(priv);
753 
754         return NETDEV_TX_OK;
755 }
756 
757 /******************************************************************************
758  * internal functions (buffer)
759  *****************************************************************************/
760 static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv,
761                                    struct ftgmac100_rxdes *rxdes, gfp_t gfp)
762 {
763         struct net_device *netdev = priv->netdev;
764         struct page *page;
765         dma_addr_t map;
766 
767         page = alloc_page(gfp);
768         if (!page) {
769                 if (net_ratelimit())
770                         netdev_err(netdev, "failed to allocate rx page\n");
771                 return -ENOMEM;
772         }
773 
774         map = dma_map_page(priv->dev, page, 0, RX_BUF_SIZE, DMA_FROM_DEVICE);
775         if (unlikely(dma_mapping_error(priv->dev, map))) {
776                 if (net_ratelimit())
777                         netdev_err(netdev, "failed to map rx page\n");
778                 __free_page(page);
779                 return -ENOMEM;
780         }
781 
782         ftgmac100_rxdes_set_page(rxdes, page);
783         ftgmac100_rxdes_set_dma_addr(rxdes, map);
784         ftgmac100_rxdes_set_dma_own(rxdes);
785         return 0;
786 }
787 
788 static void ftgmac100_free_buffers(struct ftgmac100 *priv)
789 {
790         int i;
791 
792         for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
793                 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
794                 struct page *page = ftgmac100_rxdes_get_page(rxdes);
795                 dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes);
796 
797                 if (!page)
798                         continue;
799 
800                 dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
801                 __free_page(page);
802         }
803 
804         for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
805                 struct ftgmac100_txdes *txdes = &priv->descs->txdes[i];
806                 struct sk_buff *skb = ftgmac100_txdes_get_skb(txdes);
807                 dma_addr_t map = ftgmac100_txdes_get_dma_addr(txdes);
808 
809                 if (!skb)
810                         continue;
811 
812                 dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
813                 kfree_skb(skb);
814         }
815 
816         dma_free_coherent(priv->dev, sizeof(struct ftgmac100_descs),
817                           priv->descs, priv->descs_dma_addr);
818 }
819 
820 static int ftgmac100_alloc_buffers(struct ftgmac100 *priv)
821 {
822         int i;
823 
824         priv->descs = dma_zalloc_coherent(priv->dev,
825                                           sizeof(struct ftgmac100_descs),
826                                           &priv->descs_dma_addr, GFP_KERNEL);
827         if (!priv->descs)
828                 return -ENOMEM;
829 
830         /* initialize RX ring */
831         ftgmac100_rxdes_set_end_of_ring(&priv->descs->rxdes[RX_QUEUE_ENTRIES - 1]);
832 
833         for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
834                 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
835 
836                 if (ftgmac100_alloc_rx_page(priv, rxdes, GFP_KERNEL))
837                         goto err;
838         }
839 
840         /* initialize TX ring */
841         ftgmac100_txdes_set_end_of_ring(&priv->descs->txdes[TX_QUEUE_ENTRIES - 1]);
842         return 0;
843 
844 err:
845         ftgmac100_free_buffers(priv);
846         return -ENOMEM;
847 }
848 
849 /******************************************************************************
850  * internal functions (mdio)
851  *****************************************************************************/
852 static void ftgmac100_adjust_link(struct net_device *netdev)
853 {
854         struct ftgmac100 *priv = netdev_priv(netdev);
855         struct phy_device *phydev = netdev->phydev;
856         int ier;
857 
858         if (phydev->speed == priv->old_speed)
859                 return;
860 
861         priv->old_speed = phydev->speed;
862 
863         ier = ioread32(priv->base + FTGMAC100_OFFSET_IER);
864 
865         /* disable all interrupts */
866         iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
867 
868         netif_stop_queue(netdev);
869         ftgmac100_stop_hw(priv);
870 
871         netif_start_queue(netdev);
872         ftgmac100_init_hw(priv);
873         ftgmac100_start_hw(priv, phydev->speed);
874 
875         /* re-enable interrupts */
876         iowrite32(ier, priv->base + FTGMAC100_OFFSET_IER);
877 }
878 
879 static int ftgmac100_mii_probe(struct ftgmac100 *priv)
880 {
881         struct net_device *netdev = priv->netdev;
882         struct phy_device *phydev;
883 
884         phydev = phy_find_first(priv->mii_bus);
885         if (!phydev) {
886                 netdev_info(netdev, "%s: no PHY found\n", netdev->name);
887                 return -ENODEV;
888         }
889 
890         phydev = phy_connect(netdev, phydev_name(phydev),
891                              &ftgmac100_adjust_link, PHY_INTERFACE_MODE_GMII);
892 
893         if (IS_ERR(phydev)) {
894                 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name);
895                 return PTR_ERR(phydev);
896         }
897 
898         return 0;
899 }
900 
901 /******************************************************************************
902  * struct mii_bus functions
903  *****************************************************************************/
904 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
905 {
906         struct net_device *netdev = bus->priv;
907         struct ftgmac100 *priv = netdev_priv(netdev);
908         unsigned int phycr;
909         int i;
910 
911         phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
912 
913         /* preserve MDC cycle threshold */
914         phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
915 
916         phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
917                  FTGMAC100_PHYCR_REGAD(regnum) |
918                  FTGMAC100_PHYCR_MIIRD;
919 
920         iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
921 
922         for (i = 0; i < 10; i++) {
923                 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
924 
925                 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
926                         int data;
927 
928                         data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA);
929                         return FTGMAC100_PHYDATA_MIIRDATA(data);
930                 }
931 
932                 udelay(100);
933         }
934 
935         netdev_err(netdev, "mdio read timed out\n");
936         return -EIO;
937 }
938 
939 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr,
940                                    int regnum, u16 value)
941 {
942         struct net_device *netdev = bus->priv;
943         struct ftgmac100 *priv = netdev_priv(netdev);
944         unsigned int phycr;
945         int data;
946         int i;
947 
948         phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
949 
950         /* preserve MDC cycle threshold */
951         phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
952 
953         phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
954                  FTGMAC100_PHYCR_REGAD(regnum) |
955                  FTGMAC100_PHYCR_MIIWR;
956 
957         data = FTGMAC100_PHYDATA_MIIWDATA(value);
958 
959         iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA);
960         iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
961 
962         for (i = 0; i < 10; i++) {
963                 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
964 
965                 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0)
966                         return 0;
967 
968                 udelay(100);
969         }
970 
971         netdev_err(netdev, "mdio write timed out\n");
972         return -EIO;
973 }
974 
975 /******************************************************************************
976  * struct ethtool_ops functions
977  *****************************************************************************/
978 static void ftgmac100_get_drvinfo(struct net_device *netdev,
979                                   struct ethtool_drvinfo *info)
980 {
981         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
982         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
983         strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info));
984 }
985 
986 static const struct ethtool_ops ftgmac100_ethtool_ops = {
987         .get_drvinfo            = ftgmac100_get_drvinfo,
988         .get_link               = ethtool_op_get_link,
989         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
990         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
991 };
992 
993 /******************************************************************************
994  * interrupt handler
995  *****************************************************************************/
996 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id)
997 {
998         struct net_device *netdev = dev_id;
999         struct ftgmac100 *priv = netdev_priv(netdev);
1000 
1001         /* When running in NCSI mode, the interface should be ready for
1002          * receiving or transmitting NCSI packets before it's opened.
1003          */
1004         if (likely(priv->use_ncsi || netif_running(netdev))) {
1005                 /* Disable interrupts for polling */
1006                 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1007                 napi_schedule(&priv->napi);
1008         }
1009 
1010         return IRQ_HANDLED;
1011 }
1012 
1013 /******************************************************************************
1014  * struct napi_struct functions
1015  *****************************************************************************/
1016 static int ftgmac100_poll(struct napi_struct *napi, int budget)
1017 {
1018         struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi);
1019         struct net_device *netdev = priv->netdev;
1020         unsigned int status;
1021         bool completed = true;
1022         int rx = 0;
1023 
1024         status = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
1025         iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR);
1026 
1027         if (status & (FTGMAC100_INT_RPKT_BUF | FTGMAC100_INT_NO_RXBUF)) {
1028                 /*
1029                  * FTGMAC100_INT_RPKT_BUF:
1030                  *      RX DMA has received packets into RX buffer successfully
1031                  *
1032                  * FTGMAC100_INT_NO_RXBUF:
1033                  *      RX buffer unavailable
1034                  */
1035                 bool retry;
1036 
1037                 do {
1038                         retry = ftgmac100_rx_packet(priv, &rx);
1039                 } while (retry && rx < budget);
1040 
1041                 if (retry && rx == budget)
1042                         completed = false;
1043         }
1044 
1045         if (status & (FTGMAC100_INT_XPKT_ETH | FTGMAC100_INT_XPKT_LOST)) {
1046                 /*
1047                  * FTGMAC100_INT_XPKT_ETH:
1048                  *      packet transmitted to ethernet successfully
1049                  *
1050                  * FTGMAC100_INT_XPKT_LOST:
1051                  *      packet transmitted to ethernet lost due to late
1052                  *      collision or excessive collision
1053                  */
1054                 ftgmac100_tx_complete(priv);
1055         }
1056 
1057         if (status & priv->int_mask_all & (FTGMAC100_INT_NO_RXBUF |
1058                         FTGMAC100_INT_RPKT_LOST | FTGMAC100_INT_AHB_ERR |
1059                         FTGMAC100_INT_PHYSTS_CHG)) {
1060                 if (net_ratelimit())
1061                         netdev_info(netdev, "[ISR] = 0x%x: %s%s%s%s\n", status,
1062                                     status & FTGMAC100_INT_NO_RXBUF ? "NO_RXBUF " : "",
1063                                     status & FTGMAC100_INT_RPKT_LOST ? "RPKT_LOST " : "",
1064                                     status & FTGMAC100_INT_AHB_ERR ? "AHB_ERR " : "",
1065                                     status & FTGMAC100_INT_PHYSTS_CHG ? "PHYSTS_CHG" : "");
1066 
1067                 if (status & FTGMAC100_INT_NO_RXBUF) {
1068                         /* RX buffer unavailable */
1069                         netdev->stats.rx_over_errors++;
1070                 }
1071 
1072                 if (status & FTGMAC100_INT_RPKT_LOST) {
1073                         /* received packet lost due to RX FIFO full */
1074                         netdev->stats.rx_fifo_errors++;
1075                 }
1076         }
1077 
1078         if (completed) {
1079                 napi_complete(napi);
1080 
1081                 /* enable all interrupts */
1082                 iowrite32(priv->int_mask_all,
1083                           priv->base + FTGMAC100_OFFSET_IER);
1084         }
1085 
1086         return rx;
1087 }
1088 
1089 /******************************************************************************
1090  * struct net_device_ops functions
1091  *****************************************************************************/
1092 static int ftgmac100_open(struct net_device *netdev)
1093 {
1094         struct ftgmac100 *priv = netdev_priv(netdev);
1095         int err;
1096 
1097         err = ftgmac100_alloc_buffers(priv);
1098         if (err) {
1099                 netdev_err(netdev, "failed to allocate buffers\n");
1100                 goto err_alloc;
1101         }
1102 
1103         err = request_irq(priv->irq, ftgmac100_interrupt, 0, netdev->name, netdev);
1104         if (err) {
1105                 netdev_err(netdev, "failed to request irq %d\n", priv->irq);
1106                 goto err_irq;
1107         }
1108 
1109         priv->rx_pointer = 0;
1110         priv->tx_clean_pointer = 0;
1111         priv->tx_pointer = 0;
1112         priv->tx_pending = 0;
1113 
1114         err = ftgmac100_reset_hw(priv);
1115         if (err)
1116                 goto err_hw;
1117 
1118         ftgmac100_init_hw(priv);
1119         ftgmac100_start_hw(priv, priv->use_ncsi ? 100 : 10);
1120         if (netdev->phydev)
1121                 phy_start(netdev->phydev);
1122         else if (priv->use_ncsi)
1123                 netif_carrier_on(netdev);
1124 
1125         napi_enable(&priv->napi);
1126         netif_start_queue(netdev);
1127 
1128         /* enable all interrupts */
1129         iowrite32(priv->int_mask_all, priv->base + FTGMAC100_OFFSET_IER);
1130 
1131         /* Start the NCSI device */
1132         if (priv->use_ncsi) {
1133                 err = ncsi_start_dev(priv->ndev);
1134                 if (err)
1135                         goto err_ncsi;
1136         }
1137 
1138         priv->enabled = true;
1139 
1140         return 0;
1141 
1142 err_ncsi:
1143         napi_disable(&priv->napi);
1144         netif_stop_queue(netdev);
1145         iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1146 err_hw:
1147         free_irq(priv->irq, netdev);
1148 err_irq:
1149         ftgmac100_free_buffers(priv);
1150 err_alloc:
1151         return err;
1152 }
1153 
1154 static int ftgmac100_stop(struct net_device *netdev)
1155 {
1156         struct ftgmac100 *priv = netdev_priv(netdev);
1157 
1158         if (!priv->enabled)
1159                 return 0;
1160 
1161         /* disable all interrupts */
1162         priv->enabled = false;
1163         iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1164 
1165         netif_stop_queue(netdev);
1166         napi_disable(&priv->napi);
1167         if (netdev->phydev)
1168                 phy_stop(netdev->phydev);
1169 
1170         ftgmac100_stop_hw(priv);
1171         free_irq(priv->irq, netdev);
1172         ftgmac100_free_buffers(priv);
1173 
1174         return 0;
1175 }
1176 
1177 static int ftgmac100_hard_start_xmit(struct sk_buff *skb,
1178                                      struct net_device *netdev)
1179 {
1180         struct ftgmac100 *priv = netdev_priv(netdev);
1181         dma_addr_t map;
1182 
1183         if (unlikely(skb->len > MAX_PKT_SIZE)) {
1184                 if (net_ratelimit())
1185                         netdev_dbg(netdev, "tx packet too big\n");
1186 
1187                 netdev->stats.tx_dropped++;
1188                 kfree_skb(skb);
1189                 return NETDEV_TX_OK;
1190         }
1191 
1192         map = dma_map_single(priv->dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
1193         if (unlikely(dma_mapping_error(priv->dev, map))) {
1194                 /* drop packet */
1195                 if (net_ratelimit())
1196                         netdev_err(netdev, "map socket buffer failed\n");
1197 
1198                 netdev->stats.tx_dropped++;
1199                 kfree_skb(skb);
1200                 return NETDEV_TX_OK;
1201         }
1202 
1203         return ftgmac100_xmit(priv, skb, map);
1204 }
1205 
1206 /* optional */
1207 static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1208 {
1209         if (!netdev->phydev)
1210                 return -ENXIO;
1211 
1212         return phy_mii_ioctl(netdev->phydev, ifr, cmd);
1213 }
1214 
1215 static const struct net_device_ops ftgmac100_netdev_ops = {
1216         .ndo_open               = ftgmac100_open,
1217         .ndo_stop               = ftgmac100_stop,
1218         .ndo_start_xmit         = ftgmac100_hard_start_xmit,
1219         .ndo_set_mac_address    = ftgmac100_set_mac_addr,
1220         .ndo_validate_addr      = eth_validate_addr,
1221         .ndo_do_ioctl           = ftgmac100_do_ioctl,
1222 };
1223 
1224 static int ftgmac100_setup_mdio(struct net_device *netdev)
1225 {
1226         struct ftgmac100 *priv = netdev_priv(netdev);
1227         struct platform_device *pdev = to_platform_device(priv->dev);
1228         int i, err = 0;
1229 
1230         /* initialize mdio bus */
1231         priv->mii_bus = mdiobus_alloc();
1232         if (!priv->mii_bus)
1233                 return -EIO;
1234 
1235         priv->mii_bus->name = "ftgmac100_mdio";
1236         snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
1237                  pdev->name, pdev->id);
1238         priv->mii_bus->priv = priv->netdev;
1239         priv->mii_bus->read = ftgmac100_mdiobus_read;
1240         priv->mii_bus->write = ftgmac100_mdiobus_write;
1241 
1242         for (i = 0; i < PHY_MAX_ADDR; i++)
1243                 priv->mii_bus->irq[i] = PHY_POLL;
1244 
1245         err = mdiobus_register(priv->mii_bus);
1246         if (err) {
1247                 dev_err(priv->dev, "Cannot register MDIO bus!\n");
1248                 goto err_register_mdiobus;
1249         }
1250 
1251         err = ftgmac100_mii_probe(priv);
1252         if (err) {
1253                 dev_err(priv->dev, "MII Probe failed!\n");
1254                 goto err_mii_probe;
1255         }
1256 
1257         return 0;
1258 
1259 err_mii_probe:
1260         mdiobus_unregister(priv->mii_bus);
1261 err_register_mdiobus:
1262         mdiobus_free(priv->mii_bus);
1263         return err;
1264 }
1265 
1266 static void ftgmac100_destroy_mdio(struct net_device *netdev)
1267 {
1268         struct ftgmac100 *priv = netdev_priv(netdev);
1269 
1270         if (!netdev->phydev)
1271                 return;
1272 
1273         phy_disconnect(netdev->phydev);
1274         mdiobus_unregister(priv->mii_bus);
1275         mdiobus_free(priv->mii_bus);
1276 }
1277 
1278 static void ftgmac100_ncsi_handler(struct ncsi_dev *nd)
1279 {
1280         if (unlikely(nd->state != ncsi_dev_state_functional))
1281                 return;
1282 
1283         netdev_info(nd->dev, "NCSI interface %s\n",
1284                     nd->link_up ? "up" : "down");
1285 }
1286 
1287 /******************************************************************************
1288  * struct platform_driver functions
1289  *****************************************************************************/
1290 static int ftgmac100_probe(struct platform_device *pdev)
1291 {
1292         struct resource *res;
1293         int irq;
1294         struct net_device *netdev;
1295         struct ftgmac100 *priv;
1296         int err = 0;
1297 
1298         if (!pdev)
1299                 return -ENODEV;
1300 
1301         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1302         if (!res)
1303                 return -ENXIO;
1304 
1305         irq = platform_get_irq(pdev, 0);
1306         if (irq < 0)
1307                 return irq;
1308 
1309         /* setup net_device */
1310         netdev = alloc_etherdev(sizeof(*priv));
1311         if (!netdev) {
1312                 err = -ENOMEM;
1313                 goto err_alloc_etherdev;
1314         }
1315 
1316         SET_NETDEV_DEV(netdev, &pdev->dev);
1317 
1318         netdev->ethtool_ops = &ftgmac100_ethtool_ops;
1319         netdev->netdev_ops = &ftgmac100_netdev_ops;
1320 
1321         platform_set_drvdata(pdev, netdev);
1322 
1323         /* setup private data */
1324         priv = netdev_priv(netdev);
1325         priv->netdev = netdev;
1326         priv->dev = &pdev->dev;
1327 
1328         spin_lock_init(&priv->tx_lock);
1329 
1330         /* initialize NAPI */
1331         netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64);
1332 
1333         /* map io memory */
1334         priv->res = request_mem_region(res->start, resource_size(res),
1335                                        dev_name(&pdev->dev));
1336         if (!priv->res) {
1337                 dev_err(&pdev->dev, "Could not reserve memory region\n");
1338                 err = -ENOMEM;
1339                 goto err_req_mem;
1340         }
1341 
1342         priv->base = ioremap(res->start, resource_size(res));
1343         if (!priv->base) {
1344                 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
1345                 err = -EIO;
1346                 goto err_ioremap;
1347         }
1348 
1349         priv->irq = irq;
1350 
1351         /* MAC address from chip or random one */
1352         ftgmac100_setup_mac(priv);
1353 
1354         priv->int_mask_all = (FTGMAC100_INT_RPKT_LOST |
1355                               FTGMAC100_INT_XPKT_ETH |
1356                               FTGMAC100_INT_XPKT_LOST |
1357                               FTGMAC100_INT_AHB_ERR |
1358                               FTGMAC100_INT_PHYSTS_CHG |
1359                               FTGMAC100_INT_RPKT_BUF |
1360                               FTGMAC100_INT_NO_RXBUF);
1361         if (pdev->dev.of_node &&
1362             of_get_property(pdev->dev.of_node, "use-ncsi", NULL)) {
1363                 if (!IS_ENABLED(CONFIG_NET_NCSI)) {
1364                         dev_err(&pdev->dev, "NCSI stack not enabled\n");
1365                         goto err_ncsi_dev;
1366                 }
1367 
1368                 dev_info(&pdev->dev, "Using NCSI interface\n");
1369                 priv->use_ncsi = true;
1370                 priv->int_mask_all &= ~FTGMAC100_INT_PHYSTS_CHG;
1371                 priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler);
1372                 if (!priv->ndev)
1373                         goto err_ncsi_dev;
1374         } else {
1375                 priv->use_ncsi = false;
1376                 err = ftgmac100_setup_mdio(netdev);
1377                 if (err)
1378                         goto err_setup_mdio;
1379         }
1380 
1381         /* We have to disable on-chip IP checksum functionality
1382          * when NCSI is enabled on the interface. It doesn't work
1383          * in that case.
1384          */
1385         netdev->features = NETIF_F_IP_CSUM | NETIF_F_GRO;
1386         if (priv->use_ncsi &&
1387             of_get_property(pdev->dev.of_node, "no-hw-checksum", NULL))
1388                 netdev->features &= ~NETIF_F_IP_CSUM;
1389 
1390 
1391         /* register network device */
1392         err = register_netdev(netdev);
1393         if (err) {
1394                 dev_err(&pdev->dev, "Failed to register netdev\n");
1395                 goto err_register_netdev;
1396         }
1397 
1398         netdev_info(netdev, "irq %d, mapped at %p\n", priv->irq, priv->base);
1399 
1400         return 0;
1401 
1402 err_ncsi_dev:
1403 err_register_netdev:
1404         ftgmac100_destroy_mdio(netdev);
1405 err_setup_mdio:
1406         iounmap(priv->base);
1407 err_ioremap:
1408         release_resource(priv->res);
1409 err_req_mem:
1410         netif_napi_del(&priv->napi);
1411         free_netdev(netdev);
1412 err_alloc_etherdev:
1413         return err;
1414 }
1415 
1416 static int __exit ftgmac100_remove(struct platform_device *pdev)
1417 {
1418         struct net_device *netdev;
1419         struct ftgmac100 *priv;
1420 
1421         netdev = platform_get_drvdata(pdev);
1422         priv = netdev_priv(netdev);
1423 
1424         unregister_netdev(netdev);
1425         ftgmac100_destroy_mdio(netdev);
1426 
1427         iounmap(priv->base);
1428         release_resource(priv->res);
1429 
1430         netif_napi_del(&priv->napi);
1431         free_netdev(netdev);
1432         return 0;
1433 }
1434 
1435 static const struct of_device_id ftgmac100_of_match[] = {
1436         { .compatible = "faraday,ftgmac100" },
1437         { }
1438 };
1439 MODULE_DEVICE_TABLE(of, ftgmac100_of_match);
1440 
1441 static struct platform_driver ftgmac100_driver = {
1442         .probe  = ftgmac100_probe,
1443         .remove = __exit_p(ftgmac100_remove),
1444         .driver = {
1445                 .name           = DRV_NAME,
1446                 .of_match_table = ftgmac100_of_match,
1447         },
1448 };
1449 module_platform_driver(ftgmac100_driver);
1450 
1451 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
1452 MODULE_DESCRIPTION("FTGMAC100 driver");
1453 MODULE_LICENSE("GPL");
1454 

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