Version:  2.0.40 2.2.26 2.4.37 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15

Linux/drivers/net/ethernet/faraday/ftgmac100.c

  1 /*
  2  * Faraday FTGMAC100 Gigabit Ethernet
  3  *
  4  * (C) Copyright 2009-2011 Faraday Technology
  5  * Po-Yu Chuang <ratbert@faraday-tech.com>
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License as published by
  9  * the Free Software Foundation; either version 2 of the License, or
 10  * (at your option) any later version.
 11  *
 12  * This program is distributed in the hope that it will be useful,
 13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 15  * GNU General Public License for more details.
 16  *
 17  * You should have received a copy of the GNU General Public License
 18  * along with this program; if not, write to the Free Software
 19  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 20  */
 21 
 22 #define pr_fmt(fmt)     KBUILD_MODNAME ": " fmt
 23 
 24 #include <linux/dma-mapping.h>
 25 #include <linux/etherdevice.h>
 26 #include <linux/ethtool.h>
 27 #include <linux/interrupt.h>
 28 #include <linux/io.h>
 29 #include <linux/module.h>
 30 #include <linux/netdevice.h>
 31 #include <linux/phy.h>
 32 #include <linux/platform_device.h>
 33 #include <net/ip.h>
 34 
 35 #include "ftgmac100.h"
 36 
 37 #define DRV_NAME        "ftgmac100"
 38 #define DRV_VERSION     "0.7"
 39 
 40 #define RX_QUEUE_ENTRIES        256     /* must be power of 2 */
 41 #define TX_QUEUE_ENTRIES        512     /* must be power of 2 */
 42 
 43 #define MAX_PKT_SIZE            1518
 44 #define RX_BUF_SIZE             PAGE_SIZE       /* must be smaller than 0x3fff */
 45 
 46 /******************************************************************************
 47  * private data
 48  *****************************************************************************/
 49 struct ftgmac100_descs {
 50         struct ftgmac100_rxdes rxdes[RX_QUEUE_ENTRIES];
 51         struct ftgmac100_txdes txdes[TX_QUEUE_ENTRIES];
 52 };
 53 
 54 struct ftgmac100 {
 55         struct resource *res;
 56         void __iomem *base;
 57         int irq;
 58 
 59         struct ftgmac100_descs *descs;
 60         dma_addr_t descs_dma_addr;
 61 
 62         unsigned int rx_pointer;
 63         unsigned int tx_clean_pointer;
 64         unsigned int tx_pointer;
 65         unsigned int tx_pending;
 66 
 67         spinlock_t tx_lock;
 68 
 69         struct net_device *netdev;
 70         struct device *dev;
 71         struct napi_struct napi;
 72 
 73         struct mii_bus *mii_bus;
 74         int phy_irq[PHY_MAX_ADDR];
 75         struct phy_device *phydev;
 76         int old_speed;
 77 };
 78 
 79 static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv,
 80                                    struct ftgmac100_rxdes *rxdes, gfp_t gfp);
 81 
 82 /******************************************************************************
 83  * internal functions (hardware register access)
 84  *****************************************************************************/
 85 #define INT_MASK_ALL_ENABLED    (FTGMAC100_INT_RPKT_LOST        | \
 86                                  FTGMAC100_INT_XPKT_ETH         | \
 87                                  FTGMAC100_INT_XPKT_LOST        | \
 88                                  FTGMAC100_INT_AHB_ERR          | \
 89                                  FTGMAC100_INT_PHYSTS_CHG       | \
 90                                  FTGMAC100_INT_RPKT_BUF         | \
 91                                  FTGMAC100_INT_NO_RXBUF)
 92 
 93 static void ftgmac100_set_rx_ring_base(struct ftgmac100 *priv, dma_addr_t addr)
 94 {
 95         iowrite32(addr, priv->base + FTGMAC100_OFFSET_RXR_BADR);
 96 }
 97 
 98 static void ftgmac100_set_rx_buffer_size(struct ftgmac100 *priv,
 99                 unsigned int size)
100 {
101         size = FTGMAC100_RBSR_SIZE(size);
102         iowrite32(size, priv->base + FTGMAC100_OFFSET_RBSR);
103 }
104 
105 static void ftgmac100_set_normal_prio_tx_ring_base(struct ftgmac100 *priv,
106                                                    dma_addr_t addr)
107 {
108         iowrite32(addr, priv->base + FTGMAC100_OFFSET_NPTXR_BADR);
109 }
110 
111 static void ftgmac100_txdma_normal_prio_start_polling(struct ftgmac100 *priv)
112 {
113         iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD);
114 }
115 
116 static int ftgmac100_reset_hw(struct ftgmac100 *priv)
117 {
118         struct net_device *netdev = priv->netdev;
119         int i;
120 
121         /* NOTE: reset clears all registers */
122         iowrite32(FTGMAC100_MACCR_SW_RST, priv->base + FTGMAC100_OFFSET_MACCR);
123         for (i = 0; i < 5; i++) {
124                 unsigned int maccr;
125 
126                 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
127                 if (!(maccr & FTGMAC100_MACCR_SW_RST))
128                         return 0;
129 
130                 udelay(1000);
131         }
132 
133         netdev_err(netdev, "software reset failed\n");
134         return -EIO;
135 }
136 
137 static void ftgmac100_set_mac(struct ftgmac100 *priv, const unsigned char *mac)
138 {
139         unsigned int maddr = mac[0] << 8 | mac[1];
140         unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
141 
142         iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR);
143         iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR);
144 }
145 
146 static void ftgmac100_init_hw(struct ftgmac100 *priv)
147 {
148         /* setup ring buffer base registers */
149         ftgmac100_set_rx_ring_base(priv,
150                                    priv->descs_dma_addr +
151                                    offsetof(struct ftgmac100_descs, rxdes));
152         ftgmac100_set_normal_prio_tx_ring_base(priv,
153                                                priv->descs_dma_addr +
154                                                offsetof(struct ftgmac100_descs, txdes));
155 
156         ftgmac100_set_rx_buffer_size(priv, RX_BUF_SIZE);
157 
158         iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1), priv->base + FTGMAC100_OFFSET_APTC);
159 
160         ftgmac100_set_mac(priv, priv->netdev->dev_addr);
161 }
162 
163 #define MACCR_ENABLE_ALL        (FTGMAC100_MACCR_TXDMA_EN       | \
164                                  FTGMAC100_MACCR_RXDMA_EN       | \
165                                  FTGMAC100_MACCR_TXMAC_EN       | \
166                                  FTGMAC100_MACCR_RXMAC_EN       | \
167                                  FTGMAC100_MACCR_FULLDUP        | \
168                                  FTGMAC100_MACCR_CRC_APD        | \
169                                  FTGMAC100_MACCR_RX_RUNT        | \
170                                  FTGMAC100_MACCR_RX_BROADPKT)
171 
172 static void ftgmac100_start_hw(struct ftgmac100 *priv, int speed)
173 {
174         int maccr = MACCR_ENABLE_ALL;
175 
176         switch (speed) {
177         default:
178         case 10:
179                 break;
180 
181         case 100:
182                 maccr |= FTGMAC100_MACCR_FAST_MODE;
183                 break;
184 
185         case 1000:
186                 maccr |= FTGMAC100_MACCR_GIGA_MODE;
187                 break;
188         }
189 
190         iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
191 }
192 
193 static void ftgmac100_stop_hw(struct ftgmac100 *priv)
194 {
195         iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR);
196 }
197 
198 /******************************************************************************
199  * internal functions (receive descriptor)
200  *****************************************************************************/
201 static bool ftgmac100_rxdes_first_segment(struct ftgmac100_rxdes *rxdes)
202 {
203         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FRS);
204 }
205 
206 static bool ftgmac100_rxdes_last_segment(struct ftgmac100_rxdes *rxdes)
207 {
208         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_LRS);
209 }
210 
211 static bool ftgmac100_rxdes_packet_ready(struct ftgmac100_rxdes *rxdes)
212 {
213         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY);
214 }
215 
216 static void ftgmac100_rxdes_set_dma_own(struct ftgmac100_rxdes *rxdes)
217 {
218         /* clear status bits */
219         rxdes->rxdes0 &= cpu_to_le32(FTGMAC100_RXDES0_EDORR);
220 }
221 
222 static bool ftgmac100_rxdes_rx_error(struct ftgmac100_rxdes *rxdes)
223 {
224         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ERR);
225 }
226 
227 static bool ftgmac100_rxdes_crc_error(struct ftgmac100_rxdes *rxdes)
228 {
229         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_CRC_ERR);
230 }
231 
232 static bool ftgmac100_rxdes_frame_too_long(struct ftgmac100_rxdes *rxdes)
233 {
234         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FTL);
235 }
236 
237 static bool ftgmac100_rxdes_runt(struct ftgmac100_rxdes *rxdes)
238 {
239         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RUNT);
240 }
241 
242 static bool ftgmac100_rxdes_odd_nibble(struct ftgmac100_rxdes *rxdes)
243 {
244         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ODD_NB);
245 }
246 
247 static unsigned int ftgmac100_rxdes_data_length(struct ftgmac100_rxdes *rxdes)
248 {
249         return le32_to_cpu(rxdes->rxdes0) & FTGMAC100_RXDES0_VDBC;
250 }
251 
252 static bool ftgmac100_rxdes_multicast(struct ftgmac100_rxdes *rxdes)
253 {
254         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_MULTICAST);
255 }
256 
257 static void ftgmac100_rxdes_set_end_of_ring(struct ftgmac100_rxdes *rxdes)
258 {
259         rxdes->rxdes0 |= cpu_to_le32(FTGMAC100_RXDES0_EDORR);
260 }
261 
262 static void ftgmac100_rxdes_set_dma_addr(struct ftgmac100_rxdes *rxdes,
263                                          dma_addr_t addr)
264 {
265         rxdes->rxdes3 = cpu_to_le32(addr);
266 }
267 
268 static dma_addr_t ftgmac100_rxdes_get_dma_addr(struct ftgmac100_rxdes *rxdes)
269 {
270         return le32_to_cpu(rxdes->rxdes3);
271 }
272 
273 static bool ftgmac100_rxdes_is_tcp(struct ftgmac100_rxdes *rxdes)
274 {
275         return (rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)) ==
276                cpu_to_le32(FTGMAC100_RXDES1_PROT_TCPIP);
277 }
278 
279 static bool ftgmac100_rxdes_is_udp(struct ftgmac100_rxdes *rxdes)
280 {
281         return (rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)) ==
282                cpu_to_le32(FTGMAC100_RXDES1_PROT_UDPIP);
283 }
284 
285 static bool ftgmac100_rxdes_tcpcs_err(struct ftgmac100_rxdes *rxdes)
286 {
287         return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_TCP_CHKSUM_ERR);
288 }
289 
290 static bool ftgmac100_rxdes_udpcs_err(struct ftgmac100_rxdes *rxdes)
291 {
292         return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_UDP_CHKSUM_ERR);
293 }
294 
295 static bool ftgmac100_rxdes_ipcs_err(struct ftgmac100_rxdes *rxdes)
296 {
297         return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_IP_CHKSUM_ERR);
298 }
299 
300 /*
301  * rxdes2 is not used by hardware. We use it to keep track of page.
302  * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
303  */
304 static void ftgmac100_rxdes_set_page(struct ftgmac100_rxdes *rxdes, struct page *page)
305 {
306         rxdes->rxdes2 = (unsigned int)page;
307 }
308 
309 static struct page *ftgmac100_rxdes_get_page(struct ftgmac100_rxdes *rxdes)
310 {
311         return (struct page *)rxdes->rxdes2;
312 }
313 
314 /******************************************************************************
315  * internal functions (receive)
316  *****************************************************************************/
317 static int ftgmac100_next_rx_pointer(int pointer)
318 {
319         return (pointer + 1) & (RX_QUEUE_ENTRIES - 1);
320 }
321 
322 static void ftgmac100_rx_pointer_advance(struct ftgmac100 *priv)
323 {
324         priv->rx_pointer = ftgmac100_next_rx_pointer(priv->rx_pointer);
325 }
326 
327 static struct ftgmac100_rxdes *ftgmac100_current_rxdes(struct ftgmac100 *priv)
328 {
329         return &priv->descs->rxdes[priv->rx_pointer];
330 }
331 
332 static struct ftgmac100_rxdes *
333 ftgmac100_rx_locate_first_segment(struct ftgmac100 *priv)
334 {
335         struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv);
336 
337         while (ftgmac100_rxdes_packet_ready(rxdes)) {
338                 if (ftgmac100_rxdes_first_segment(rxdes))
339                         return rxdes;
340 
341                 ftgmac100_rxdes_set_dma_own(rxdes);
342                 ftgmac100_rx_pointer_advance(priv);
343                 rxdes = ftgmac100_current_rxdes(priv);
344         }
345 
346         return NULL;
347 }
348 
349 static bool ftgmac100_rx_packet_error(struct ftgmac100 *priv,
350                                       struct ftgmac100_rxdes *rxdes)
351 {
352         struct net_device *netdev = priv->netdev;
353         bool error = false;
354 
355         if (unlikely(ftgmac100_rxdes_rx_error(rxdes))) {
356                 if (net_ratelimit())
357                         netdev_info(netdev, "rx err\n");
358 
359                 netdev->stats.rx_errors++;
360                 error = true;
361         }
362 
363         if (unlikely(ftgmac100_rxdes_crc_error(rxdes))) {
364                 if (net_ratelimit())
365                         netdev_info(netdev, "rx crc err\n");
366 
367                 netdev->stats.rx_crc_errors++;
368                 error = true;
369         } else if (unlikely(ftgmac100_rxdes_ipcs_err(rxdes))) {
370                 if (net_ratelimit())
371                         netdev_info(netdev, "rx IP checksum err\n");
372 
373                 error = true;
374         }
375 
376         if (unlikely(ftgmac100_rxdes_frame_too_long(rxdes))) {
377                 if (net_ratelimit())
378                         netdev_info(netdev, "rx frame too long\n");
379 
380                 netdev->stats.rx_length_errors++;
381                 error = true;
382         } else if (unlikely(ftgmac100_rxdes_runt(rxdes))) {
383                 if (net_ratelimit())
384                         netdev_info(netdev, "rx runt\n");
385 
386                 netdev->stats.rx_length_errors++;
387                 error = true;
388         } else if (unlikely(ftgmac100_rxdes_odd_nibble(rxdes))) {
389                 if (net_ratelimit())
390                         netdev_info(netdev, "rx odd nibble\n");
391 
392                 netdev->stats.rx_length_errors++;
393                 error = true;
394         }
395 
396         return error;
397 }
398 
399 static void ftgmac100_rx_drop_packet(struct ftgmac100 *priv)
400 {
401         struct net_device *netdev = priv->netdev;
402         struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv);
403         bool done = false;
404 
405         if (net_ratelimit())
406                 netdev_dbg(netdev, "drop packet %p\n", rxdes);
407 
408         do {
409                 if (ftgmac100_rxdes_last_segment(rxdes))
410                         done = true;
411 
412                 ftgmac100_rxdes_set_dma_own(rxdes);
413                 ftgmac100_rx_pointer_advance(priv);
414                 rxdes = ftgmac100_current_rxdes(priv);
415         } while (!done && ftgmac100_rxdes_packet_ready(rxdes));
416 
417         netdev->stats.rx_dropped++;
418 }
419 
420 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed)
421 {
422         struct net_device *netdev = priv->netdev;
423         struct ftgmac100_rxdes *rxdes;
424         struct sk_buff *skb;
425         bool done = false;
426 
427         rxdes = ftgmac100_rx_locate_first_segment(priv);
428         if (!rxdes)
429                 return false;
430 
431         if (unlikely(ftgmac100_rx_packet_error(priv, rxdes))) {
432                 ftgmac100_rx_drop_packet(priv);
433                 return true;
434         }
435 
436         /* start processing */
437         skb = netdev_alloc_skb_ip_align(netdev, 128);
438         if (unlikely(!skb)) {
439                 if (net_ratelimit())
440                         netdev_err(netdev, "rx skb alloc failed\n");
441 
442                 ftgmac100_rx_drop_packet(priv);
443                 return true;
444         }
445 
446         if (unlikely(ftgmac100_rxdes_multicast(rxdes)))
447                 netdev->stats.multicast++;
448 
449         /*
450          * It seems that HW does checksum incorrectly with fragmented packets,
451          * so we are conservative here - if HW checksum error, let software do
452          * the checksum again.
453          */
454         if ((ftgmac100_rxdes_is_tcp(rxdes) && !ftgmac100_rxdes_tcpcs_err(rxdes)) ||
455             (ftgmac100_rxdes_is_udp(rxdes) && !ftgmac100_rxdes_udpcs_err(rxdes)))
456                 skb->ip_summed = CHECKSUM_UNNECESSARY;
457 
458         do {
459                 dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes);
460                 struct page *page = ftgmac100_rxdes_get_page(rxdes);
461                 unsigned int size;
462 
463                 dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
464 
465                 size = ftgmac100_rxdes_data_length(rxdes);
466                 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, page, 0, size);
467 
468                 skb->len += size;
469                 skb->data_len += size;
470                 skb->truesize += PAGE_SIZE;
471 
472                 if (ftgmac100_rxdes_last_segment(rxdes))
473                         done = true;
474 
475                 ftgmac100_alloc_rx_page(priv, rxdes, GFP_ATOMIC);
476 
477                 ftgmac100_rx_pointer_advance(priv);
478                 rxdes = ftgmac100_current_rxdes(priv);
479         } while (!done);
480 
481         /* Small frames are copied into linear part of skb to free one page */
482         if (skb->len <= 128) {
483                 skb->truesize -= PAGE_SIZE;
484                 __pskb_pull_tail(skb, skb->len);
485         } else {
486                 /* We pull the minimum amount into linear part */
487                 __pskb_pull_tail(skb, ETH_HLEN);
488         }
489         skb->protocol = eth_type_trans(skb, netdev);
490 
491         netdev->stats.rx_packets++;
492         netdev->stats.rx_bytes += skb->len;
493 
494         /* push packet to protocol stack */
495         napi_gro_receive(&priv->napi, skb);
496 
497         (*processed)++;
498         return true;
499 }
500 
501 /******************************************************************************
502  * internal functions (transmit descriptor)
503  *****************************************************************************/
504 static void ftgmac100_txdes_reset(struct ftgmac100_txdes *txdes)
505 {
506         /* clear all except end of ring bit */
507         txdes->txdes0 &= cpu_to_le32(FTGMAC100_TXDES0_EDOTR);
508         txdes->txdes1 = 0;
509         txdes->txdes2 = 0;
510         txdes->txdes3 = 0;
511 }
512 
513 static bool ftgmac100_txdes_owned_by_dma(struct ftgmac100_txdes *txdes)
514 {
515         return txdes->txdes0 & cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN);
516 }
517 
518 static void ftgmac100_txdes_set_dma_own(struct ftgmac100_txdes *txdes)
519 {
520         /*
521          * Make sure dma own bit will not be set before any other
522          * descriptor fields.
523          */
524         wmb();
525         txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN);
526 }
527 
528 static void ftgmac100_txdes_set_end_of_ring(struct ftgmac100_txdes *txdes)
529 {
530         txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_EDOTR);
531 }
532 
533 static void ftgmac100_txdes_set_first_segment(struct ftgmac100_txdes *txdes)
534 {
535         txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_FTS);
536 }
537 
538 static void ftgmac100_txdes_set_last_segment(struct ftgmac100_txdes *txdes)
539 {
540         txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_LTS);
541 }
542 
543 static void ftgmac100_txdes_set_buffer_size(struct ftgmac100_txdes *txdes,
544                                             unsigned int len)
545 {
546         txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXBUF_SIZE(len));
547 }
548 
549 static void ftgmac100_txdes_set_txint(struct ftgmac100_txdes *txdes)
550 {
551         txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TXIC);
552 }
553 
554 static void ftgmac100_txdes_set_tcpcs(struct ftgmac100_txdes *txdes)
555 {
556         txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TCP_CHKSUM);
557 }
558 
559 static void ftgmac100_txdes_set_udpcs(struct ftgmac100_txdes *txdes)
560 {
561         txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_UDP_CHKSUM);
562 }
563 
564 static void ftgmac100_txdes_set_ipcs(struct ftgmac100_txdes *txdes)
565 {
566         txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_IP_CHKSUM);
567 }
568 
569 static void ftgmac100_txdes_set_dma_addr(struct ftgmac100_txdes *txdes,
570                                          dma_addr_t addr)
571 {
572         txdes->txdes3 = cpu_to_le32(addr);
573 }
574 
575 static dma_addr_t ftgmac100_txdes_get_dma_addr(struct ftgmac100_txdes *txdes)
576 {
577         return le32_to_cpu(txdes->txdes3);
578 }
579 
580 /*
581  * txdes2 is not used by hardware. We use it to keep track of socket buffer.
582  * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
583  */
584 static void ftgmac100_txdes_set_skb(struct ftgmac100_txdes *txdes,
585                                     struct sk_buff *skb)
586 {
587         txdes->txdes2 = (unsigned int)skb;
588 }
589 
590 static struct sk_buff *ftgmac100_txdes_get_skb(struct ftgmac100_txdes *txdes)
591 {
592         return (struct sk_buff *)txdes->txdes2;
593 }
594 
595 /******************************************************************************
596  * internal functions (transmit)
597  *****************************************************************************/
598 static int ftgmac100_next_tx_pointer(int pointer)
599 {
600         return (pointer + 1) & (TX_QUEUE_ENTRIES - 1);
601 }
602 
603 static void ftgmac100_tx_pointer_advance(struct ftgmac100 *priv)
604 {
605         priv->tx_pointer = ftgmac100_next_tx_pointer(priv->tx_pointer);
606 }
607 
608 static void ftgmac100_tx_clean_pointer_advance(struct ftgmac100 *priv)
609 {
610         priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv->tx_clean_pointer);
611 }
612 
613 static struct ftgmac100_txdes *ftgmac100_current_txdes(struct ftgmac100 *priv)
614 {
615         return &priv->descs->txdes[priv->tx_pointer];
616 }
617 
618 static struct ftgmac100_txdes *
619 ftgmac100_current_clean_txdes(struct ftgmac100 *priv)
620 {
621         return &priv->descs->txdes[priv->tx_clean_pointer];
622 }
623 
624 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv)
625 {
626         struct net_device *netdev = priv->netdev;
627         struct ftgmac100_txdes *txdes;
628         struct sk_buff *skb;
629         dma_addr_t map;
630 
631         if (priv->tx_pending == 0)
632                 return false;
633 
634         txdes = ftgmac100_current_clean_txdes(priv);
635 
636         if (ftgmac100_txdes_owned_by_dma(txdes))
637                 return false;
638 
639         skb = ftgmac100_txdes_get_skb(txdes);
640         map = ftgmac100_txdes_get_dma_addr(txdes);
641 
642         netdev->stats.tx_packets++;
643         netdev->stats.tx_bytes += skb->len;
644 
645         dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
646 
647         dev_kfree_skb(skb);
648 
649         ftgmac100_txdes_reset(txdes);
650 
651         ftgmac100_tx_clean_pointer_advance(priv);
652 
653         spin_lock(&priv->tx_lock);
654         priv->tx_pending--;
655         spin_unlock(&priv->tx_lock);
656         netif_wake_queue(netdev);
657 
658         return true;
659 }
660 
661 static void ftgmac100_tx_complete(struct ftgmac100 *priv)
662 {
663         while (ftgmac100_tx_complete_packet(priv))
664                 ;
665 }
666 
667 static int ftgmac100_xmit(struct ftgmac100 *priv, struct sk_buff *skb,
668                           dma_addr_t map)
669 {
670         struct net_device *netdev = priv->netdev;
671         struct ftgmac100_txdes *txdes;
672         unsigned int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len;
673 
674         txdes = ftgmac100_current_txdes(priv);
675         ftgmac100_tx_pointer_advance(priv);
676 
677         /* setup TX descriptor */
678         ftgmac100_txdes_set_skb(txdes, skb);
679         ftgmac100_txdes_set_dma_addr(txdes, map);
680         ftgmac100_txdes_set_buffer_size(txdes, len);
681 
682         ftgmac100_txdes_set_first_segment(txdes);
683         ftgmac100_txdes_set_last_segment(txdes);
684         ftgmac100_txdes_set_txint(txdes);
685         if (skb->ip_summed == CHECKSUM_PARTIAL) {
686                 __be16 protocol = skb->protocol;
687 
688                 if (protocol == cpu_to_be16(ETH_P_IP)) {
689                         u8 ip_proto = ip_hdr(skb)->protocol;
690 
691                         ftgmac100_txdes_set_ipcs(txdes);
692                         if (ip_proto == IPPROTO_TCP)
693                                 ftgmac100_txdes_set_tcpcs(txdes);
694                         else if (ip_proto == IPPROTO_UDP)
695                                 ftgmac100_txdes_set_udpcs(txdes);
696                 }
697         }
698 
699         spin_lock(&priv->tx_lock);
700         priv->tx_pending++;
701         if (priv->tx_pending == TX_QUEUE_ENTRIES)
702                 netif_stop_queue(netdev);
703 
704         /* start transmit */
705         ftgmac100_txdes_set_dma_own(txdes);
706         spin_unlock(&priv->tx_lock);
707 
708         ftgmac100_txdma_normal_prio_start_polling(priv);
709 
710         return NETDEV_TX_OK;
711 }
712 
713 /******************************************************************************
714  * internal functions (buffer)
715  *****************************************************************************/
716 static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv,
717                                    struct ftgmac100_rxdes *rxdes, gfp_t gfp)
718 {
719         struct net_device *netdev = priv->netdev;
720         struct page *page;
721         dma_addr_t map;
722 
723         page = alloc_page(gfp);
724         if (!page) {
725                 if (net_ratelimit())
726                         netdev_err(netdev, "failed to allocate rx page\n");
727                 return -ENOMEM;
728         }
729 
730         map = dma_map_page(priv->dev, page, 0, RX_BUF_SIZE, DMA_FROM_DEVICE);
731         if (unlikely(dma_mapping_error(priv->dev, map))) {
732                 if (net_ratelimit())
733                         netdev_err(netdev, "failed to map rx page\n");
734                 __free_page(page);
735                 return -ENOMEM;
736         }
737 
738         ftgmac100_rxdes_set_page(rxdes, page);
739         ftgmac100_rxdes_set_dma_addr(rxdes, map);
740         ftgmac100_rxdes_set_dma_own(rxdes);
741         return 0;
742 }
743 
744 static void ftgmac100_free_buffers(struct ftgmac100 *priv)
745 {
746         int i;
747 
748         for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
749                 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
750                 struct page *page = ftgmac100_rxdes_get_page(rxdes);
751                 dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes);
752 
753                 if (!page)
754                         continue;
755 
756                 dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
757                 __free_page(page);
758         }
759 
760         for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
761                 struct ftgmac100_txdes *txdes = &priv->descs->txdes[i];
762                 struct sk_buff *skb = ftgmac100_txdes_get_skb(txdes);
763                 dma_addr_t map = ftgmac100_txdes_get_dma_addr(txdes);
764 
765                 if (!skb)
766                         continue;
767 
768                 dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
769                 kfree_skb(skb);
770         }
771 
772         dma_free_coherent(priv->dev, sizeof(struct ftgmac100_descs),
773                           priv->descs, priv->descs_dma_addr);
774 }
775 
776 static int ftgmac100_alloc_buffers(struct ftgmac100 *priv)
777 {
778         int i;
779 
780         priv->descs = dma_zalloc_coherent(priv->dev,
781                                           sizeof(struct ftgmac100_descs),
782                                           &priv->descs_dma_addr, GFP_KERNEL);
783         if (!priv->descs)
784                 return -ENOMEM;
785 
786         /* initialize RX ring */
787         ftgmac100_rxdes_set_end_of_ring(&priv->descs->rxdes[RX_QUEUE_ENTRIES - 1]);
788 
789         for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
790                 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
791 
792                 if (ftgmac100_alloc_rx_page(priv, rxdes, GFP_KERNEL))
793                         goto err;
794         }
795 
796         /* initialize TX ring */
797         ftgmac100_txdes_set_end_of_ring(&priv->descs->txdes[TX_QUEUE_ENTRIES - 1]);
798         return 0;
799 
800 err:
801         ftgmac100_free_buffers(priv);
802         return -ENOMEM;
803 }
804 
805 /******************************************************************************
806  * internal functions (mdio)
807  *****************************************************************************/
808 static void ftgmac100_adjust_link(struct net_device *netdev)
809 {
810         struct ftgmac100 *priv = netdev_priv(netdev);
811         struct phy_device *phydev = priv->phydev;
812         int ier;
813 
814         if (phydev->speed == priv->old_speed)
815                 return;
816 
817         priv->old_speed = phydev->speed;
818 
819         ier = ioread32(priv->base + FTGMAC100_OFFSET_IER);
820 
821         /* disable all interrupts */
822         iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
823 
824         netif_stop_queue(netdev);
825         ftgmac100_stop_hw(priv);
826 
827         netif_start_queue(netdev);
828         ftgmac100_init_hw(priv);
829         ftgmac100_start_hw(priv, phydev->speed);
830 
831         /* re-enable interrupts */
832         iowrite32(ier, priv->base + FTGMAC100_OFFSET_IER);
833 }
834 
835 static int ftgmac100_mii_probe(struct ftgmac100 *priv)
836 {
837         struct net_device *netdev = priv->netdev;
838         struct phy_device *phydev = NULL;
839         int i;
840 
841         /* search for connect PHY device */
842         for (i = 0; i < PHY_MAX_ADDR; i++) {
843                 struct phy_device *tmp = priv->mii_bus->phy_map[i];
844 
845                 if (tmp) {
846                         phydev = tmp;
847                         break;
848                 }
849         }
850 
851         /* now we are supposed to have a proper phydev, to attach to... */
852         if (!phydev) {
853                 netdev_info(netdev, "%s: no PHY found\n", netdev->name);
854                 return -ENODEV;
855         }
856 
857         phydev = phy_connect(netdev, dev_name(&phydev->dev),
858                              &ftgmac100_adjust_link, PHY_INTERFACE_MODE_GMII);
859 
860         if (IS_ERR(phydev)) {
861                 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name);
862                 return PTR_ERR(phydev);
863         }
864 
865         priv->phydev = phydev;
866         return 0;
867 }
868 
869 /******************************************************************************
870  * struct mii_bus functions
871  *****************************************************************************/
872 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
873 {
874         struct net_device *netdev = bus->priv;
875         struct ftgmac100 *priv = netdev_priv(netdev);
876         unsigned int phycr;
877         int i;
878 
879         phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
880 
881         /* preserve MDC cycle threshold */
882         phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
883 
884         phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
885                  FTGMAC100_PHYCR_REGAD(regnum) |
886                  FTGMAC100_PHYCR_MIIRD;
887 
888         iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
889 
890         for (i = 0; i < 10; i++) {
891                 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
892 
893                 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
894                         int data;
895 
896                         data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA);
897                         return FTGMAC100_PHYDATA_MIIRDATA(data);
898                 }
899 
900                 udelay(100);
901         }
902 
903         netdev_err(netdev, "mdio read timed out\n");
904         return -EIO;
905 }
906 
907 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr,
908                                    int regnum, u16 value)
909 {
910         struct net_device *netdev = bus->priv;
911         struct ftgmac100 *priv = netdev_priv(netdev);
912         unsigned int phycr;
913         int data;
914         int i;
915 
916         phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
917 
918         /* preserve MDC cycle threshold */
919         phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
920 
921         phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
922                  FTGMAC100_PHYCR_REGAD(regnum) |
923                  FTGMAC100_PHYCR_MIIWR;
924 
925         data = FTGMAC100_PHYDATA_MIIWDATA(value);
926 
927         iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA);
928         iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
929 
930         for (i = 0; i < 10; i++) {
931                 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
932 
933                 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0)
934                         return 0;
935 
936                 udelay(100);
937         }
938 
939         netdev_err(netdev, "mdio write timed out\n");
940         return -EIO;
941 }
942 
943 /******************************************************************************
944  * struct ethtool_ops functions
945  *****************************************************************************/
946 static void ftgmac100_get_drvinfo(struct net_device *netdev,
947                                   struct ethtool_drvinfo *info)
948 {
949         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
950         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
951         strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info));
952 }
953 
954 static int ftgmac100_get_settings(struct net_device *netdev,
955                                   struct ethtool_cmd *cmd)
956 {
957         struct ftgmac100 *priv = netdev_priv(netdev);
958 
959         return phy_ethtool_gset(priv->phydev, cmd);
960 }
961 
962 static int ftgmac100_set_settings(struct net_device *netdev,
963                                   struct ethtool_cmd *cmd)
964 {
965         struct ftgmac100 *priv = netdev_priv(netdev);
966 
967         return phy_ethtool_sset(priv->phydev, cmd);
968 }
969 
970 static const struct ethtool_ops ftgmac100_ethtool_ops = {
971         .set_settings           = ftgmac100_set_settings,
972         .get_settings           = ftgmac100_get_settings,
973         .get_drvinfo            = ftgmac100_get_drvinfo,
974         .get_link               = ethtool_op_get_link,
975 };
976 
977 /******************************************************************************
978  * interrupt handler
979  *****************************************************************************/
980 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id)
981 {
982         struct net_device *netdev = dev_id;
983         struct ftgmac100 *priv = netdev_priv(netdev);
984 
985         if (likely(netif_running(netdev))) {
986                 /* Disable interrupts for polling */
987                 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
988                 napi_schedule(&priv->napi);
989         }
990 
991         return IRQ_HANDLED;
992 }
993 
994 /******************************************************************************
995  * struct napi_struct functions
996  *****************************************************************************/
997 static int ftgmac100_poll(struct napi_struct *napi, int budget)
998 {
999         struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi);
1000         struct net_device *netdev = priv->netdev;
1001         unsigned int status;
1002         bool completed = true;
1003         int rx = 0;
1004 
1005         status = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
1006         iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR);
1007 
1008         if (status & (FTGMAC100_INT_RPKT_BUF | FTGMAC100_INT_NO_RXBUF)) {
1009                 /*
1010                  * FTGMAC100_INT_RPKT_BUF:
1011                  *      RX DMA has received packets into RX buffer successfully
1012                  *
1013                  * FTGMAC100_INT_NO_RXBUF:
1014                  *      RX buffer unavailable
1015                  */
1016                 bool retry;
1017 
1018                 do {
1019                         retry = ftgmac100_rx_packet(priv, &rx);
1020                 } while (retry && rx < budget);
1021 
1022                 if (retry && rx == budget)
1023                         completed = false;
1024         }
1025 
1026         if (status & (FTGMAC100_INT_XPKT_ETH | FTGMAC100_INT_XPKT_LOST)) {
1027                 /*
1028                  * FTGMAC100_INT_XPKT_ETH:
1029                  *      packet transmitted to ethernet successfully
1030                  *
1031                  * FTGMAC100_INT_XPKT_LOST:
1032                  *      packet transmitted to ethernet lost due to late
1033                  *      collision or excessive collision
1034                  */
1035                 ftgmac100_tx_complete(priv);
1036         }
1037 
1038         if (status & (FTGMAC100_INT_NO_RXBUF | FTGMAC100_INT_RPKT_LOST |
1039                       FTGMAC100_INT_AHB_ERR | FTGMAC100_INT_PHYSTS_CHG)) {
1040                 if (net_ratelimit())
1041                         netdev_info(netdev, "[ISR] = 0x%x: %s%s%s%s\n", status,
1042                                     status & FTGMAC100_INT_NO_RXBUF ? "NO_RXBUF " : "",
1043                                     status & FTGMAC100_INT_RPKT_LOST ? "RPKT_LOST " : "",
1044                                     status & FTGMAC100_INT_AHB_ERR ? "AHB_ERR " : "",
1045                                     status & FTGMAC100_INT_PHYSTS_CHG ? "PHYSTS_CHG" : "");
1046 
1047                 if (status & FTGMAC100_INT_NO_RXBUF) {
1048                         /* RX buffer unavailable */
1049                         netdev->stats.rx_over_errors++;
1050                 }
1051 
1052                 if (status & FTGMAC100_INT_RPKT_LOST) {
1053                         /* received packet lost due to RX FIFO full */
1054                         netdev->stats.rx_fifo_errors++;
1055                 }
1056         }
1057 
1058         if (completed) {
1059                 napi_complete(napi);
1060 
1061                 /* enable all interrupts */
1062                 iowrite32(INT_MASK_ALL_ENABLED, priv->base + FTGMAC100_OFFSET_IER);
1063         }
1064 
1065         return rx;
1066 }
1067 
1068 /******************************************************************************
1069  * struct net_device_ops functions
1070  *****************************************************************************/
1071 static int ftgmac100_open(struct net_device *netdev)
1072 {
1073         struct ftgmac100 *priv = netdev_priv(netdev);
1074         int err;
1075 
1076         err = ftgmac100_alloc_buffers(priv);
1077         if (err) {
1078                 netdev_err(netdev, "failed to allocate buffers\n");
1079                 goto err_alloc;
1080         }
1081 
1082         err = request_irq(priv->irq, ftgmac100_interrupt, 0, netdev->name, netdev);
1083         if (err) {
1084                 netdev_err(netdev, "failed to request irq %d\n", priv->irq);
1085                 goto err_irq;
1086         }
1087 
1088         priv->rx_pointer = 0;
1089         priv->tx_clean_pointer = 0;
1090         priv->tx_pointer = 0;
1091         priv->tx_pending = 0;
1092 
1093         err = ftgmac100_reset_hw(priv);
1094         if (err)
1095                 goto err_hw;
1096 
1097         ftgmac100_init_hw(priv);
1098         ftgmac100_start_hw(priv, 10);
1099 
1100         phy_start(priv->phydev);
1101 
1102         napi_enable(&priv->napi);
1103         netif_start_queue(netdev);
1104 
1105         /* enable all interrupts */
1106         iowrite32(INT_MASK_ALL_ENABLED, priv->base + FTGMAC100_OFFSET_IER);
1107         return 0;
1108 
1109 err_hw:
1110         free_irq(priv->irq, netdev);
1111 err_irq:
1112         ftgmac100_free_buffers(priv);
1113 err_alloc:
1114         return err;
1115 }
1116 
1117 static int ftgmac100_stop(struct net_device *netdev)
1118 {
1119         struct ftgmac100 *priv = netdev_priv(netdev);
1120 
1121         /* disable all interrupts */
1122         iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1123 
1124         netif_stop_queue(netdev);
1125         napi_disable(&priv->napi);
1126         phy_stop(priv->phydev);
1127 
1128         ftgmac100_stop_hw(priv);
1129         free_irq(priv->irq, netdev);
1130         ftgmac100_free_buffers(priv);
1131 
1132         return 0;
1133 }
1134 
1135 static int ftgmac100_hard_start_xmit(struct sk_buff *skb,
1136                                      struct net_device *netdev)
1137 {
1138         struct ftgmac100 *priv = netdev_priv(netdev);
1139         dma_addr_t map;
1140 
1141         if (unlikely(skb->len > MAX_PKT_SIZE)) {
1142                 if (net_ratelimit())
1143                         netdev_dbg(netdev, "tx packet too big\n");
1144 
1145                 netdev->stats.tx_dropped++;
1146                 kfree_skb(skb);
1147                 return NETDEV_TX_OK;
1148         }
1149 
1150         map = dma_map_single(priv->dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
1151         if (unlikely(dma_mapping_error(priv->dev, map))) {
1152                 /* drop packet */
1153                 if (net_ratelimit())
1154                         netdev_err(netdev, "map socket buffer failed\n");
1155 
1156                 netdev->stats.tx_dropped++;
1157                 kfree_skb(skb);
1158                 return NETDEV_TX_OK;
1159         }
1160 
1161         return ftgmac100_xmit(priv, skb, map);
1162 }
1163 
1164 /* optional */
1165 static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1166 {
1167         struct ftgmac100 *priv = netdev_priv(netdev);
1168 
1169         return phy_mii_ioctl(priv->phydev, ifr, cmd);
1170 }
1171 
1172 static const struct net_device_ops ftgmac100_netdev_ops = {
1173         .ndo_open               = ftgmac100_open,
1174         .ndo_stop               = ftgmac100_stop,
1175         .ndo_start_xmit         = ftgmac100_hard_start_xmit,
1176         .ndo_set_mac_address    = eth_mac_addr,
1177         .ndo_validate_addr      = eth_validate_addr,
1178         .ndo_do_ioctl           = ftgmac100_do_ioctl,
1179 };
1180 
1181 /******************************************************************************
1182  * struct platform_driver functions
1183  *****************************************************************************/
1184 static int ftgmac100_probe(struct platform_device *pdev)
1185 {
1186         struct resource *res;
1187         int irq;
1188         struct net_device *netdev;
1189         struct ftgmac100 *priv;
1190         int err;
1191         int i;
1192 
1193         if (!pdev)
1194                 return -ENODEV;
1195 
1196         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1197         if (!res)
1198                 return -ENXIO;
1199 
1200         irq = platform_get_irq(pdev, 0);
1201         if (irq < 0)
1202                 return irq;
1203 
1204         /* setup net_device */
1205         netdev = alloc_etherdev(sizeof(*priv));
1206         if (!netdev) {
1207                 err = -ENOMEM;
1208                 goto err_alloc_etherdev;
1209         }
1210 
1211         SET_NETDEV_DEV(netdev, &pdev->dev);
1212 
1213         SET_ETHTOOL_OPS(netdev, &ftgmac100_ethtool_ops);
1214         netdev->netdev_ops = &ftgmac100_netdev_ops;
1215         netdev->features = NETIF_F_IP_CSUM | NETIF_F_GRO;
1216 
1217         platform_set_drvdata(pdev, netdev);
1218 
1219         /* setup private data */
1220         priv = netdev_priv(netdev);
1221         priv->netdev = netdev;
1222         priv->dev = &pdev->dev;
1223 
1224         spin_lock_init(&priv->tx_lock);
1225 
1226         /* initialize NAPI */
1227         netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64);
1228 
1229         /* map io memory */
1230         priv->res = request_mem_region(res->start, resource_size(res),
1231                                        dev_name(&pdev->dev));
1232         if (!priv->res) {
1233                 dev_err(&pdev->dev, "Could not reserve memory region\n");
1234                 err = -ENOMEM;
1235                 goto err_req_mem;
1236         }
1237 
1238         priv->base = ioremap(res->start, resource_size(res));
1239         if (!priv->base) {
1240                 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
1241                 err = -EIO;
1242                 goto err_ioremap;
1243         }
1244 
1245         priv->irq = irq;
1246 
1247         /* initialize mdio bus */
1248         priv->mii_bus = mdiobus_alloc();
1249         if (!priv->mii_bus) {
1250                 err = -EIO;
1251                 goto err_alloc_mdiobus;
1252         }
1253 
1254         priv->mii_bus->name = "ftgmac100_mdio";
1255         snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "ftgmac100_mii");
1256 
1257         priv->mii_bus->priv = netdev;
1258         priv->mii_bus->read = ftgmac100_mdiobus_read;
1259         priv->mii_bus->write = ftgmac100_mdiobus_write;
1260         priv->mii_bus->irq = priv->phy_irq;
1261 
1262         for (i = 0; i < PHY_MAX_ADDR; i++)
1263                 priv->mii_bus->irq[i] = PHY_POLL;
1264 
1265         err = mdiobus_register(priv->mii_bus);
1266         if (err) {
1267                 dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
1268                 goto err_register_mdiobus;
1269         }
1270 
1271         err = ftgmac100_mii_probe(priv);
1272         if (err) {
1273                 dev_err(&pdev->dev, "MII Probe failed!\n");
1274                 goto err_mii_probe;
1275         }
1276 
1277         /* register network device */
1278         err = register_netdev(netdev);
1279         if (err) {
1280                 dev_err(&pdev->dev, "Failed to register netdev\n");
1281                 goto err_register_netdev;
1282         }
1283 
1284         netdev_info(netdev, "irq %d, mapped at %p\n", priv->irq, priv->base);
1285 
1286         if (!is_valid_ether_addr(netdev->dev_addr)) {
1287                 eth_hw_addr_random(netdev);
1288                 netdev_info(netdev, "generated random MAC address %pM\n",
1289                             netdev->dev_addr);
1290         }
1291 
1292         return 0;
1293 
1294 err_register_netdev:
1295         phy_disconnect(priv->phydev);
1296 err_mii_probe:
1297         mdiobus_unregister(priv->mii_bus);
1298 err_register_mdiobus:
1299         mdiobus_free(priv->mii_bus);
1300 err_alloc_mdiobus:
1301         iounmap(priv->base);
1302 err_ioremap:
1303         release_resource(priv->res);
1304 err_req_mem:
1305         netif_napi_del(&priv->napi);
1306         free_netdev(netdev);
1307 err_alloc_etherdev:
1308         return err;
1309 }
1310 
1311 static int __exit ftgmac100_remove(struct platform_device *pdev)
1312 {
1313         struct net_device *netdev;
1314         struct ftgmac100 *priv;
1315 
1316         netdev = platform_get_drvdata(pdev);
1317         priv = netdev_priv(netdev);
1318 
1319         unregister_netdev(netdev);
1320 
1321         phy_disconnect(priv->phydev);
1322         mdiobus_unregister(priv->mii_bus);
1323         mdiobus_free(priv->mii_bus);
1324 
1325         iounmap(priv->base);
1326         release_resource(priv->res);
1327 
1328         netif_napi_del(&priv->napi);
1329         free_netdev(netdev);
1330         return 0;
1331 }
1332 
1333 static struct platform_driver ftgmac100_driver = {
1334         .probe          = ftgmac100_probe,
1335         .remove         = __exit_p(ftgmac100_remove),
1336         .driver         = {
1337                 .name   = DRV_NAME,
1338                 .owner  = THIS_MODULE,
1339         },
1340 };
1341 
1342 module_platform_driver(ftgmac100_driver);
1343 
1344 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
1345 MODULE_DESCRIPTION("FTGMAC100 driver");
1346 MODULE_LICENSE("GPL");
1347 

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