Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4

Linux/drivers/net/ethernet/ethoc.c

  1 /*
  2  * linux/drivers/net/ethernet/ethoc.c
  3  *
  4  * Copyright (C) 2007-2008 Avionic Design Development GmbH
  5  * Copyright (C) 2008-2009 Avionic Design GmbH
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License version 2 as
  9  * published by the Free Software Foundation.
 10  *
 11  * Written by Thierry Reding <thierry.reding@avionic-design.de>
 12  */
 13 
 14 #include <linux/dma-mapping.h>
 15 #include <linux/etherdevice.h>
 16 #include <linux/clk.h>
 17 #include <linux/crc32.h>
 18 #include <linux/interrupt.h>
 19 #include <linux/io.h>
 20 #include <linux/mii.h>
 21 #include <linux/phy.h>
 22 #include <linux/platform_device.h>
 23 #include <linux/sched.h>
 24 #include <linux/slab.h>
 25 #include <linux/of.h>
 26 #include <linux/module.h>
 27 #include <net/ethoc.h>
 28 
 29 static int buffer_size = 0x8000; /* 32 KBytes */
 30 module_param(buffer_size, int, 0);
 31 MODULE_PARM_DESC(buffer_size, "DMA buffer allocation size");
 32 
 33 /* register offsets */
 34 #define MODER           0x00
 35 #define INT_SOURCE      0x04
 36 #define INT_MASK        0x08
 37 #define IPGT            0x0c
 38 #define IPGR1           0x10
 39 #define IPGR2           0x14
 40 #define PACKETLEN       0x18
 41 #define COLLCONF        0x1c
 42 #define TX_BD_NUM       0x20
 43 #define CTRLMODER       0x24
 44 #define MIIMODER        0x28
 45 #define MIICOMMAND      0x2c
 46 #define MIIADDRESS      0x30
 47 #define MIITX_DATA      0x34
 48 #define MIIRX_DATA      0x38
 49 #define MIISTATUS       0x3c
 50 #define MAC_ADDR0       0x40
 51 #define MAC_ADDR1       0x44
 52 #define ETH_HASH0       0x48
 53 #define ETH_HASH1       0x4c
 54 #define ETH_TXCTRL      0x50
 55 #define ETH_END         0x54
 56 
 57 /* mode register */
 58 #define MODER_RXEN      (1 <<  0) /* receive enable */
 59 #define MODER_TXEN      (1 <<  1) /* transmit enable */
 60 #define MODER_NOPRE     (1 <<  2) /* no preamble */
 61 #define MODER_BRO       (1 <<  3) /* broadcast address */
 62 #define MODER_IAM       (1 <<  4) /* individual address mode */
 63 #define MODER_PRO       (1 <<  5) /* promiscuous mode */
 64 #define MODER_IFG       (1 <<  6) /* interframe gap for incoming frames */
 65 #define MODER_LOOP      (1 <<  7) /* loopback */
 66 #define MODER_NBO       (1 <<  8) /* no back-off */
 67 #define MODER_EDE       (1 <<  9) /* excess defer enable */
 68 #define MODER_FULLD     (1 << 10) /* full duplex */
 69 #define MODER_RESET     (1 << 11) /* FIXME: reset (undocumented) */
 70 #define MODER_DCRC      (1 << 12) /* delayed CRC enable */
 71 #define MODER_CRC       (1 << 13) /* CRC enable */
 72 #define MODER_HUGE      (1 << 14) /* huge packets enable */
 73 #define MODER_PAD       (1 << 15) /* padding enabled */
 74 #define MODER_RSM       (1 << 16) /* receive small packets */
 75 
 76 /* interrupt source and mask registers */
 77 #define INT_MASK_TXF    (1 << 0) /* transmit frame */
 78 #define INT_MASK_TXE    (1 << 1) /* transmit error */
 79 #define INT_MASK_RXF    (1 << 2) /* receive frame */
 80 #define INT_MASK_RXE    (1 << 3) /* receive error */
 81 #define INT_MASK_BUSY   (1 << 4)
 82 #define INT_MASK_TXC    (1 << 5) /* transmit control frame */
 83 #define INT_MASK_RXC    (1 << 6) /* receive control frame */
 84 
 85 #define INT_MASK_TX     (INT_MASK_TXF | INT_MASK_TXE)
 86 #define INT_MASK_RX     (INT_MASK_RXF | INT_MASK_RXE)
 87 
 88 #define INT_MASK_ALL ( \
 89                 INT_MASK_TXF | INT_MASK_TXE | \
 90                 INT_MASK_RXF | INT_MASK_RXE | \
 91                 INT_MASK_TXC | INT_MASK_RXC | \
 92                 INT_MASK_BUSY \
 93         )
 94 
 95 /* packet length register */
 96 #define PACKETLEN_MIN(min)              (((min) & 0xffff) << 16)
 97 #define PACKETLEN_MAX(max)              (((max) & 0xffff) <<  0)
 98 #define PACKETLEN_MIN_MAX(min, max)     (PACKETLEN_MIN(min) | \
 99                                         PACKETLEN_MAX(max))
100 
101 /* transmit buffer number register */
102 #define TX_BD_NUM_VAL(x)        (((x) <= 0x80) ? (x) : 0x80)
103 
104 /* control module mode register */
105 #define CTRLMODER_PASSALL       (1 << 0) /* pass all receive frames */
106 #define CTRLMODER_RXFLOW        (1 << 1) /* receive control flow */
107 #define CTRLMODER_TXFLOW        (1 << 2) /* transmit control flow */
108 
109 /* MII mode register */
110 #define MIIMODER_CLKDIV(x)      ((x) & 0xfe) /* needs to be an even number */
111 #define MIIMODER_NOPRE          (1 << 8) /* no preamble */
112 
113 /* MII command register */
114 #define MIICOMMAND_SCAN         (1 << 0) /* scan status */
115 #define MIICOMMAND_READ         (1 << 1) /* read status */
116 #define MIICOMMAND_WRITE        (1 << 2) /* write control data */
117 
118 /* MII address register */
119 #define MIIADDRESS_FIAD(x)              (((x) & 0x1f) << 0)
120 #define MIIADDRESS_RGAD(x)              (((x) & 0x1f) << 8)
121 #define MIIADDRESS_ADDR(phy, reg)       (MIIADDRESS_FIAD(phy) | \
122                                         MIIADDRESS_RGAD(reg))
123 
124 /* MII transmit data register */
125 #define MIITX_DATA_VAL(x)       ((x) & 0xffff)
126 
127 /* MII receive data register */
128 #define MIIRX_DATA_VAL(x)       ((x) & 0xffff)
129 
130 /* MII status register */
131 #define MIISTATUS_LINKFAIL      (1 << 0)
132 #define MIISTATUS_BUSY          (1 << 1)
133 #define MIISTATUS_INVALID       (1 << 2)
134 
135 /* TX buffer descriptor */
136 #define TX_BD_CS                (1 <<  0) /* carrier sense lost */
137 #define TX_BD_DF                (1 <<  1) /* defer indication */
138 #define TX_BD_LC                (1 <<  2) /* late collision */
139 #define TX_BD_RL                (1 <<  3) /* retransmission limit */
140 #define TX_BD_RETRY_MASK        (0x00f0)
141 #define TX_BD_RETRY(x)          (((x) & 0x00f0) >>  4)
142 #define TX_BD_UR                (1 <<  8) /* transmitter underrun */
143 #define TX_BD_CRC               (1 << 11) /* TX CRC enable */
144 #define TX_BD_PAD               (1 << 12) /* pad enable for short packets */
145 #define TX_BD_WRAP              (1 << 13)
146 #define TX_BD_IRQ               (1 << 14) /* interrupt request enable */
147 #define TX_BD_READY             (1 << 15) /* TX buffer ready */
148 #define TX_BD_LEN(x)            (((x) & 0xffff) << 16)
149 #define TX_BD_LEN_MASK          (0xffff << 16)
150 
151 #define TX_BD_STATS             (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
152                                 TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
153 
154 /* RX buffer descriptor */
155 #define RX_BD_LC        (1 <<  0) /* late collision */
156 #define RX_BD_CRC       (1 <<  1) /* RX CRC error */
157 #define RX_BD_SF        (1 <<  2) /* short frame */
158 #define RX_BD_TL        (1 <<  3) /* too long */
159 #define RX_BD_DN        (1 <<  4) /* dribble nibble */
160 #define RX_BD_IS        (1 <<  5) /* invalid symbol */
161 #define RX_BD_OR        (1 <<  6) /* receiver overrun */
162 #define RX_BD_MISS      (1 <<  7)
163 #define RX_BD_CF        (1 <<  8) /* control frame */
164 #define RX_BD_WRAP      (1 << 13)
165 #define RX_BD_IRQ       (1 << 14) /* interrupt request enable */
166 #define RX_BD_EMPTY     (1 << 15)
167 #define RX_BD_LEN(x)    (((x) & 0xffff) << 16)
168 
169 #define RX_BD_STATS     (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
170                         RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
171 
172 #define ETHOC_BUFSIZ            1536
173 #define ETHOC_ZLEN              64
174 #define ETHOC_BD_BASE           0x400
175 #define ETHOC_TIMEOUT           (HZ / 2)
176 #define ETHOC_MII_TIMEOUT       (1 + (HZ / 5))
177 
178 /**
179  * struct ethoc - driver-private device structure
180  * @iobase:     pointer to I/O memory region
181  * @membase:    pointer to buffer memory region
182  * @dma_alloc:  dma allocated buffer size
183  * @io_region_size:     I/O memory region size
184  * @num_bd:     number of buffer descriptors
185  * @num_tx:     number of send buffers
186  * @cur_tx:     last send buffer written
187  * @dty_tx:     last buffer actually sent
188  * @num_rx:     number of receive buffers
189  * @cur_rx:     current receive buffer
190  * @vma:        pointer to array of virtual memory addresses for buffers
191  * @netdev:     pointer to network device structure
192  * @napi:       NAPI structure
193  * @msg_enable: device state flags
194  * @lock:       device lock
195  * @phy:        attached PHY
196  * @mdio:       MDIO bus for PHY access
197  * @phy_id:     address of attached PHY
198  */
199 struct ethoc {
200         void __iomem *iobase;
201         void __iomem *membase;
202         int dma_alloc;
203         resource_size_t io_region_size;
204         bool big_endian;
205 
206         unsigned int num_bd;
207         unsigned int num_tx;
208         unsigned int cur_tx;
209         unsigned int dty_tx;
210 
211         unsigned int num_rx;
212         unsigned int cur_rx;
213 
214         void **vma;
215 
216         struct net_device *netdev;
217         struct napi_struct napi;
218         u32 msg_enable;
219 
220         spinlock_t lock;
221 
222         struct phy_device *phy;
223         struct mii_bus *mdio;
224         struct clk *clk;
225         s8 phy_id;
226 };
227 
228 /**
229  * struct ethoc_bd - buffer descriptor
230  * @stat:       buffer statistics
231  * @addr:       physical memory address
232  */
233 struct ethoc_bd {
234         u32 stat;
235         u32 addr;
236 };
237 
238 static inline u32 ethoc_read(struct ethoc *dev, loff_t offset)
239 {
240         if (dev->big_endian)
241                 return ioread32be(dev->iobase + offset);
242         else
243                 return ioread32(dev->iobase + offset);
244 }
245 
246 static inline void ethoc_write(struct ethoc *dev, loff_t offset, u32 data)
247 {
248         if (dev->big_endian)
249                 iowrite32be(data, dev->iobase + offset);
250         else
251                 iowrite32(data, dev->iobase + offset);
252 }
253 
254 static inline void ethoc_read_bd(struct ethoc *dev, int index,
255                 struct ethoc_bd *bd)
256 {
257         loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
258         bd->stat = ethoc_read(dev, offset + 0);
259         bd->addr = ethoc_read(dev, offset + 4);
260 }
261 
262 static inline void ethoc_write_bd(struct ethoc *dev, int index,
263                 const struct ethoc_bd *bd)
264 {
265         loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
266         ethoc_write(dev, offset + 0, bd->stat);
267         ethoc_write(dev, offset + 4, bd->addr);
268 }
269 
270 static inline void ethoc_enable_irq(struct ethoc *dev, u32 mask)
271 {
272         u32 imask = ethoc_read(dev, INT_MASK);
273         imask |= mask;
274         ethoc_write(dev, INT_MASK, imask);
275 }
276 
277 static inline void ethoc_disable_irq(struct ethoc *dev, u32 mask)
278 {
279         u32 imask = ethoc_read(dev, INT_MASK);
280         imask &= ~mask;
281         ethoc_write(dev, INT_MASK, imask);
282 }
283 
284 static inline void ethoc_ack_irq(struct ethoc *dev, u32 mask)
285 {
286         ethoc_write(dev, INT_SOURCE, mask);
287 }
288 
289 static inline void ethoc_enable_rx_and_tx(struct ethoc *dev)
290 {
291         u32 mode = ethoc_read(dev, MODER);
292         mode |= MODER_RXEN | MODER_TXEN;
293         ethoc_write(dev, MODER, mode);
294 }
295 
296 static inline void ethoc_disable_rx_and_tx(struct ethoc *dev)
297 {
298         u32 mode = ethoc_read(dev, MODER);
299         mode &= ~(MODER_RXEN | MODER_TXEN);
300         ethoc_write(dev, MODER, mode);
301 }
302 
303 static int ethoc_init_ring(struct ethoc *dev, unsigned long mem_start)
304 {
305         struct ethoc_bd bd;
306         int i;
307         void *vma;
308 
309         dev->cur_tx = 0;
310         dev->dty_tx = 0;
311         dev->cur_rx = 0;
312 
313         ethoc_write(dev, TX_BD_NUM, dev->num_tx);
314 
315         /* setup transmission buffers */
316         bd.addr = mem_start;
317         bd.stat = TX_BD_IRQ | TX_BD_CRC;
318         vma = dev->membase;
319 
320         for (i = 0; i < dev->num_tx; i++) {
321                 if (i == dev->num_tx - 1)
322                         bd.stat |= TX_BD_WRAP;
323 
324                 ethoc_write_bd(dev, i, &bd);
325                 bd.addr += ETHOC_BUFSIZ;
326 
327                 dev->vma[i] = vma;
328                 vma += ETHOC_BUFSIZ;
329         }
330 
331         bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
332 
333         for (i = 0; i < dev->num_rx; i++) {
334                 if (i == dev->num_rx - 1)
335                         bd.stat |= RX_BD_WRAP;
336 
337                 ethoc_write_bd(dev, dev->num_tx + i, &bd);
338                 bd.addr += ETHOC_BUFSIZ;
339 
340                 dev->vma[dev->num_tx + i] = vma;
341                 vma += ETHOC_BUFSIZ;
342         }
343 
344         return 0;
345 }
346 
347 static int ethoc_reset(struct ethoc *dev)
348 {
349         u32 mode;
350 
351         /* TODO: reset controller? */
352 
353         ethoc_disable_rx_and_tx(dev);
354 
355         /* TODO: setup registers */
356 
357         /* enable FCS generation and automatic padding */
358         mode = ethoc_read(dev, MODER);
359         mode |= MODER_CRC | MODER_PAD;
360         ethoc_write(dev, MODER, mode);
361 
362         /* set full-duplex mode */
363         mode = ethoc_read(dev, MODER);
364         mode |= MODER_FULLD;
365         ethoc_write(dev, MODER, mode);
366         ethoc_write(dev, IPGT, 0x15);
367 
368         ethoc_ack_irq(dev, INT_MASK_ALL);
369         ethoc_enable_irq(dev, INT_MASK_ALL);
370         ethoc_enable_rx_and_tx(dev);
371         return 0;
372 }
373 
374 static unsigned int ethoc_update_rx_stats(struct ethoc *dev,
375                 struct ethoc_bd *bd)
376 {
377         struct net_device *netdev = dev->netdev;
378         unsigned int ret = 0;
379 
380         if (bd->stat & RX_BD_TL) {
381                 dev_err(&netdev->dev, "RX: frame too long\n");
382                 netdev->stats.rx_length_errors++;
383                 ret++;
384         }
385 
386         if (bd->stat & RX_BD_SF) {
387                 dev_err(&netdev->dev, "RX: frame too short\n");
388                 netdev->stats.rx_length_errors++;
389                 ret++;
390         }
391 
392         if (bd->stat & RX_BD_DN) {
393                 dev_err(&netdev->dev, "RX: dribble nibble\n");
394                 netdev->stats.rx_frame_errors++;
395         }
396 
397         if (bd->stat & RX_BD_CRC) {
398                 dev_err(&netdev->dev, "RX: wrong CRC\n");
399                 netdev->stats.rx_crc_errors++;
400                 ret++;
401         }
402 
403         if (bd->stat & RX_BD_OR) {
404                 dev_err(&netdev->dev, "RX: overrun\n");
405                 netdev->stats.rx_over_errors++;
406                 ret++;
407         }
408 
409         if (bd->stat & RX_BD_MISS)
410                 netdev->stats.rx_missed_errors++;
411 
412         if (bd->stat & RX_BD_LC) {
413                 dev_err(&netdev->dev, "RX: late collision\n");
414                 netdev->stats.collisions++;
415                 ret++;
416         }
417 
418         return ret;
419 }
420 
421 static int ethoc_rx(struct net_device *dev, int limit)
422 {
423         struct ethoc *priv = netdev_priv(dev);
424         int count;
425 
426         for (count = 0; count < limit; ++count) {
427                 unsigned int entry;
428                 struct ethoc_bd bd;
429 
430                 entry = priv->num_tx + priv->cur_rx;
431                 ethoc_read_bd(priv, entry, &bd);
432                 if (bd.stat & RX_BD_EMPTY) {
433                         ethoc_ack_irq(priv, INT_MASK_RX);
434                         /* If packet (interrupt) came in between checking
435                          * BD_EMTPY and clearing the interrupt source, then we
436                          * risk missing the packet as the RX interrupt won't
437                          * trigger right away when we reenable it; hence, check
438                          * BD_EMTPY here again to make sure there isn't such a
439                          * packet waiting for us...
440                          */
441                         ethoc_read_bd(priv, entry, &bd);
442                         if (bd.stat & RX_BD_EMPTY)
443                                 break;
444                 }
445 
446                 if (ethoc_update_rx_stats(priv, &bd) == 0) {
447                         int size = bd.stat >> 16;
448                         struct sk_buff *skb;
449 
450                         size -= 4; /* strip the CRC */
451                         skb = netdev_alloc_skb_ip_align(dev, size);
452 
453                         if (likely(skb)) {
454                                 void *src = priv->vma[entry];
455                                 memcpy_fromio(skb_put(skb, size), src, size);
456                                 skb->protocol = eth_type_trans(skb, dev);
457                                 dev->stats.rx_packets++;
458                                 dev->stats.rx_bytes += size;
459                                 netif_receive_skb(skb);
460                         } else {
461                                 if (net_ratelimit())
462                                         dev_warn(&dev->dev,
463                                             "low on memory - packet dropped\n");
464 
465                                 dev->stats.rx_dropped++;
466                                 break;
467                         }
468                 }
469 
470                 /* clear the buffer descriptor so it can be reused */
471                 bd.stat &= ~RX_BD_STATS;
472                 bd.stat |=  RX_BD_EMPTY;
473                 ethoc_write_bd(priv, entry, &bd);
474                 if (++priv->cur_rx == priv->num_rx)
475                         priv->cur_rx = 0;
476         }
477 
478         return count;
479 }
480 
481 static void ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd)
482 {
483         struct net_device *netdev = dev->netdev;
484 
485         if (bd->stat & TX_BD_LC) {
486                 dev_err(&netdev->dev, "TX: late collision\n");
487                 netdev->stats.tx_window_errors++;
488         }
489 
490         if (bd->stat & TX_BD_RL) {
491                 dev_err(&netdev->dev, "TX: retransmit limit\n");
492                 netdev->stats.tx_aborted_errors++;
493         }
494 
495         if (bd->stat & TX_BD_UR) {
496                 dev_err(&netdev->dev, "TX: underrun\n");
497                 netdev->stats.tx_fifo_errors++;
498         }
499 
500         if (bd->stat & TX_BD_CS) {
501                 dev_err(&netdev->dev, "TX: carrier sense lost\n");
502                 netdev->stats.tx_carrier_errors++;
503         }
504 
505         if (bd->stat & TX_BD_STATS)
506                 netdev->stats.tx_errors++;
507 
508         netdev->stats.collisions += (bd->stat >> 4) & 0xf;
509         netdev->stats.tx_bytes += bd->stat >> 16;
510         netdev->stats.tx_packets++;
511 }
512 
513 static int ethoc_tx(struct net_device *dev, int limit)
514 {
515         struct ethoc *priv = netdev_priv(dev);
516         int count;
517         struct ethoc_bd bd;
518 
519         for (count = 0; count < limit; ++count) {
520                 unsigned int entry;
521 
522                 entry = priv->dty_tx & (priv->num_tx-1);
523 
524                 ethoc_read_bd(priv, entry, &bd);
525 
526                 if (bd.stat & TX_BD_READY || (priv->dty_tx == priv->cur_tx)) {
527                         ethoc_ack_irq(priv, INT_MASK_TX);
528                         /* If interrupt came in between reading in the BD
529                          * and clearing the interrupt source, then we risk
530                          * missing the event as the TX interrupt won't trigger
531                          * right away when we reenable it; hence, check
532                          * BD_EMPTY here again to make sure there isn't such an
533                          * event pending...
534                          */
535                         ethoc_read_bd(priv, entry, &bd);
536                         if (bd.stat & TX_BD_READY ||
537                             (priv->dty_tx == priv->cur_tx))
538                                 break;
539                 }
540 
541                 ethoc_update_tx_stats(priv, &bd);
542                 priv->dty_tx++;
543         }
544 
545         if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2))
546                 netif_wake_queue(dev);
547 
548         return count;
549 }
550 
551 static irqreturn_t ethoc_interrupt(int irq, void *dev_id)
552 {
553         struct net_device *dev = dev_id;
554         struct ethoc *priv = netdev_priv(dev);
555         u32 pending;
556         u32 mask;
557 
558         /* Figure out what triggered the interrupt...
559          * The tricky bit here is that the interrupt source bits get
560          * set in INT_SOURCE for an event regardless of whether that
561          * event is masked or not.  Thus, in order to figure out what
562          * triggered the interrupt, we need to remove the sources
563          * for all events that are currently masked.  This behaviour
564          * is not particularly well documented but reasonable...
565          */
566         mask = ethoc_read(priv, INT_MASK);
567         pending = ethoc_read(priv, INT_SOURCE);
568         pending &= mask;
569 
570         if (unlikely(pending == 0))
571                 return IRQ_NONE;
572 
573         ethoc_ack_irq(priv, pending);
574 
575         /* We always handle the dropped packet interrupt */
576         if (pending & INT_MASK_BUSY) {
577                 dev_err(&dev->dev, "packet dropped\n");
578                 dev->stats.rx_dropped++;
579         }
580 
581         /* Handle receive/transmit event by switching to polling */
582         if (pending & (INT_MASK_TX | INT_MASK_RX)) {
583                 ethoc_disable_irq(priv, INT_MASK_TX | INT_MASK_RX);
584                 napi_schedule(&priv->napi);
585         }
586 
587         return IRQ_HANDLED;
588 }
589 
590 static int ethoc_get_mac_address(struct net_device *dev, void *addr)
591 {
592         struct ethoc *priv = netdev_priv(dev);
593         u8 *mac = (u8 *)addr;
594         u32 reg;
595 
596         reg = ethoc_read(priv, MAC_ADDR0);
597         mac[2] = (reg >> 24) & 0xff;
598         mac[3] = (reg >> 16) & 0xff;
599         mac[4] = (reg >>  8) & 0xff;
600         mac[5] = (reg >>  0) & 0xff;
601 
602         reg = ethoc_read(priv, MAC_ADDR1);
603         mac[0] = (reg >>  8) & 0xff;
604         mac[1] = (reg >>  0) & 0xff;
605 
606         return 0;
607 }
608 
609 static int ethoc_poll(struct napi_struct *napi, int budget)
610 {
611         struct ethoc *priv = container_of(napi, struct ethoc, napi);
612         int rx_work_done = 0;
613         int tx_work_done = 0;
614 
615         rx_work_done = ethoc_rx(priv->netdev, budget);
616         tx_work_done = ethoc_tx(priv->netdev, budget);
617 
618         if (rx_work_done < budget && tx_work_done < budget) {
619                 napi_complete(napi);
620                 ethoc_enable_irq(priv, INT_MASK_TX | INT_MASK_RX);
621         }
622 
623         return rx_work_done;
624 }
625 
626 static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
627 {
628         struct ethoc *priv = bus->priv;
629         int i;
630 
631         ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
632         ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
633 
634         for (i = 0; i < 5; i++) {
635                 u32 status = ethoc_read(priv, MIISTATUS);
636                 if (!(status & MIISTATUS_BUSY)) {
637                         u32 data = ethoc_read(priv, MIIRX_DATA);
638                         /* reset MII command register */
639                         ethoc_write(priv, MIICOMMAND, 0);
640                         return data;
641                 }
642                 usleep_range(100, 200);
643         }
644 
645         return -EBUSY;
646 }
647 
648 static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
649 {
650         struct ethoc *priv = bus->priv;
651         int i;
652 
653         ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
654         ethoc_write(priv, MIITX_DATA, val);
655         ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
656 
657         for (i = 0; i < 5; i++) {
658                 u32 stat = ethoc_read(priv, MIISTATUS);
659                 if (!(stat & MIISTATUS_BUSY)) {
660                         /* reset MII command register */
661                         ethoc_write(priv, MIICOMMAND, 0);
662                         return 0;
663                 }
664                 usleep_range(100, 200);
665         }
666 
667         return -EBUSY;
668 }
669 
670 static void ethoc_mdio_poll(struct net_device *dev)
671 {
672 }
673 
674 static int ethoc_mdio_probe(struct net_device *dev)
675 {
676         struct ethoc *priv = netdev_priv(dev);
677         struct phy_device *phy;
678         int err;
679 
680         if (priv->phy_id != -1)
681                 phy = priv->mdio->phy_map[priv->phy_id];
682         else
683                 phy = phy_find_first(priv->mdio);
684 
685         if (!phy) {
686                 dev_err(&dev->dev, "no PHY found\n");
687                 return -ENXIO;
688         }
689 
690         err = phy_connect_direct(dev, phy, ethoc_mdio_poll,
691                                  PHY_INTERFACE_MODE_GMII);
692         if (err) {
693                 dev_err(&dev->dev, "could not attach to PHY\n");
694                 return err;
695         }
696 
697         priv->phy = phy;
698         phy->advertising &= ~(ADVERTISED_1000baseT_Full |
699                               ADVERTISED_1000baseT_Half);
700         phy->supported &= ~(SUPPORTED_1000baseT_Full |
701                             SUPPORTED_1000baseT_Half);
702 
703         return 0;
704 }
705 
706 static int ethoc_open(struct net_device *dev)
707 {
708         struct ethoc *priv = netdev_priv(dev);
709         int ret;
710 
711         ret = request_irq(dev->irq, ethoc_interrupt, IRQF_SHARED,
712                         dev->name, dev);
713         if (ret)
714                 return ret;
715 
716         ethoc_init_ring(priv, dev->mem_start);
717         ethoc_reset(priv);
718 
719         if (netif_queue_stopped(dev)) {
720                 dev_dbg(&dev->dev, " resuming queue\n");
721                 netif_wake_queue(dev);
722         } else {
723                 dev_dbg(&dev->dev, " starting queue\n");
724                 netif_start_queue(dev);
725         }
726 
727         phy_start(priv->phy);
728         napi_enable(&priv->napi);
729 
730         if (netif_msg_ifup(priv)) {
731                 dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n",
732                                 dev->base_addr, dev->mem_start, dev->mem_end);
733         }
734 
735         return 0;
736 }
737 
738 static int ethoc_stop(struct net_device *dev)
739 {
740         struct ethoc *priv = netdev_priv(dev);
741 
742         napi_disable(&priv->napi);
743 
744         if (priv->phy)
745                 phy_stop(priv->phy);
746 
747         ethoc_disable_rx_and_tx(priv);
748         free_irq(dev->irq, dev);
749 
750         if (!netif_queue_stopped(dev))
751                 netif_stop_queue(dev);
752 
753         return 0;
754 }
755 
756 static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
757 {
758         struct ethoc *priv = netdev_priv(dev);
759         struct mii_ioctl_data *mdio = if_mii(ifr);
760         struct phy_device *phy = NULL;
761 
762         if (!netif_running(dev))
763                 return -EINVAL;
764 
765         if (cmd != SIOCGMIIPHY) {
766                 if (mdio->phy_id >= PHY_MAX_ADDR)
767                         return -ERANGE;
768 
769                 phy = priv->mdio->phy_map[mdio->phy_id];
770                 if (!phy)
771                         return -ENODEV;
772         } else {
773                 phy = priv->phy;
774         }
775 
776         return phy_mii_ioctl(phy, ifr, cmd);
777 }
778 
779 static void ethoc_do_set_mac_address(struct net_device *dev)
780 {
781         struct ethoc *priv = netdev_priv(dev);
782         unsigned char *mac = dev->dev_addr;
783 
784         ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
785                                      (mac[4] <<  8) | (mac[5] <<  0));
786         ethoc_write(priv, MAC_ADDR1, (mac[0] <<  8) | (mac[1] <<  0));
787 }
788 
789 static int ethoc_set_mac_address(struct net_device *dev, void *p)
790 {
791         const struct sockaddr *addr = p;
792 
793         if (!is_valid_ether_addr(addr->sa_data))
794                 return -EADDRNOTAVAIL;
795         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
796         ethoc_do_set_mac_address(dev);
797         return 0;
798 }
799 
800 static void ethoc_set_multicast_list(struct net_device *dev)
801 {
802         struct ethoc *priv = netdev_priv(dev);
803         u32 mode = ethoc_read(priv, MODER);
804         struct netdev_hw_addr *ha;
805         u32 hash[2] = { 0, 0 };
806 
807         /* set loopback mode if requested */
808         if (dev->flags & IFF_LOOPBACK)
809                 mode |=  MODER_LOOP;
810         else
811                 mode &= ~MODER_LOOP;
812 
813         /* receive broadcast frames if requested */
814         if (dev->flags & IFF_BROADCAST)
815                 mode &= ~MODER_BRO;
816         else
817                 mode |=  MODER_BRO;
818 
819         /* enable promiscuous mode if requested */
820         if (dev->flags & IFF_PROMISC)
821                 mode |=  MODER_PRO;
822         else
823                 mode &= ~MODER_PRO;
824 
825         ethoc_write(priv, MODER, mode);
826 
827         /* receive multicast frames */
828         if (dev->flags & IFF_ALLMULTI) {
829                 hash[0] = 0xffffffff;
830                 hash[1] = 0xffffffff;
831         } else {
832                 netdev_for_each_mc_addr(ha, dev) {
833                         u32 crc = ether_crc(ETH_ALEN, ha->addr);
834                         int bit = (crc >> 26) & 0x3f;
835                         hash[bit >> 5] |= 1 << (bit & 0x1f);
836                 }
837         }
838 
839         ethoc_write(priv, ETH_HASH0, hash[0]);
840         ethoc_write(priv, ETH_HASH1, hash[1]);
841 }
842 
843 static int ethoc_change_mtu(struct net_device *dev, int new_mtu)
844 {
845         return -ENOSYS;
846 }
847 
848 static void ethoc_tx_timeout(struct net_device *dev)
849 {
850         struct ethoc *priv = netdev_priv(dev);
851         u32 pending = ethoc_read(priv, INT_SOURCE);
852         if (likely(pending))
853                 ethoc_interrupt(dev->irq, dev);
854 }
855 
856 static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev)
857 {
858         struct ethoc *priv = netdev_priv(dev);
859         struct ethoc_bd bd;
860         unsigned int entry;
861         void *dest;
862 
863         if (unlikely(skb->len > ETHOC_BUFSIZ)) {
864                 dev->stats.tx_errors++;
865                 goto out;
866         }
867 
868         entry = priv->cur_tx % priv->num_tx;
869         spin_lock_irq(&priv->lock);
870         priv->cur_tx++;
871 
872         ethoc_read_bd(priv, entry, &bd);
873         if (unlikely(skb->len < ETHOC_ZLEN))
874                 bd.stat |=  TX_BD_PAD;
875         else
876                 bd.stat &= ~TX_BD_PAD;
877 
878         dest = priv->vma[entry];
879         memcpy_toio(dest, skb->data, skb->len);
880 
881         bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
882         bd.stat |= TX_BD_LEN(skb->len);
883         ethoc_write_bd(priv, entry, &bd);
884 
885         bd.stat |= TX_BD_READY;
886         ethoc_write_bd(priv, entry, &bd);
887 
888         if (priv->cur_tx == (priv->dty_tx + priv->num_tx)) {
889                 dev_dbg(&dev->dev, "stopping queue\n");
890                 netif_stop_queue(dev);
891         }
892 
893         spin_unlock_irq(&priv->lock);
894         skb_tx_timestamp(skb);
895 out:
896         dev_kfree_skb(skb);
897         return NETDEV_TX_OK;
898 }
899 
900 static int ethoc_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
901 {
902         struct ethoc *priv = netdev_priv(dev);
903         struct phy_device *phydev = priv->phy;
904 
905         if (!phydev)
906                 return -EOPNOTSUPP;
907 
908         return phy_ethtool_gset(phydev, cmd);
909 }
910 
911 static int ethoc_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
912 {
913         struct ethoc *priv = netdev_priv(dev);
914         struct phy_device *phydev = priv->phy;
915 
916         if (!phydev)
917                 return -EOPNOTSUPP;
918 
919         return phy_ethtool_sset(phydev, cmd);
920 }
921 
922 static int ethoc_get_regs_len(struct net_device *netdev)
923 {
924         return ETH_END;
925 }
926 
927 static void ethoc_get_regs(struct net_device *dev, struct ethtool_regs *regs,
928                            void *p)
929 {
930         struct ethoc *priv = netdev_priv(dev);
931         u32 *regs_buff = p;
932         unsigned i;
933 
934         regs->version = 0;
935         for (i = 0; i < ETH_END / sizeof(u32); ++i)
936                 regs_buff[i] = ethoc_read(priv, i * sizeof(u32));
937 }
938 
939 static void ethoc_get_ringparam(struct net_device *dev,
940                                 struct ethtool_ringparam *ring)
941 {
942         struct ethoc *priv = netdev_priv(dev);
943 
944         ring->rx_max_pending = priv->num_bd - 1;
945         ring->rx_mini_max_pending = 0;
946         ring->rx_jumbo_max_pending = 0;
947         ring->tx_max_pending = priv->num_bd - 1;
948 
949         ring->rx_pending = priv->num_rx;
950         ring->rx_mini_pending = 0;
951         ring->rx_jumbo_pending = 0;
952         ring->tx_pending = priv->num_tx;
953 }
954 
955 static int ethoc_set_ringparam(struct net_device *dev,
956                                struct ethtool_ringparam *ring)
957 {
958         struct ethoc *priv = netdev_priv(dev);
959 
960         if (ring->tx_pending < 1 || ring->rx_pending < 1 ||
961             ring->tx_pending + ring->rx_pending > priv->num_bd)
962                 return -EINVAL;
963         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
964                 return -EINVAL;
965 
966         if (netif_running(dev)) {
967                 netif_tx_disable(dev);
968                 ethoc_disable_rx_and_tx(priv);
969                 ethoc_disable_irq(priv, INT_MASK_TX | INT_MASK_RX);
970                 synchronize_irq(dev->irq);
971         }
972 
973         priv->num_tx = rounddown_pow_of_two(ring->tx_pending);
974         priv->num_rx = ring->rx_pending;
975         ethoc_init_ring(priv, dev->mem_start);
976 
977         if (netif_running(dev)) {
978                 ethoc_enable_irq(priv, INT_MASK_TX | INT_MASK_RX);
979                 ethoc_enable_rx_and_tx(priv);
980                 netif_wake_queue(dev);
981         }
982         return 0;
983 }
984 
985 const struct ethtool_ops ethoc_ethtool_ops = {
986         .get_settings = ethoc_get_settings,
987         .set_settings = ethoc_set_settings,
988         .get_regs_len = ethoc_get_regs_len,
989         .get_regs = ethoc_get_regs,
990         .get_link = ethtool_op_get_link,
991         .get_ringparam = ethoc_get_ringparam,
992         .set_ringparam = ethoc_set_ringparam,
993         .get_ts_info = ethtool_op_get_ts_info,
994 };
995 
996 static const struct net_device_ops ethoc_netdev_ops = {
997         .ndo_open = ethoc_open,
998         .ndo_stop = ethoc_stop,
999         .ndo_do_ioctl = ethoc_ioctl,
1000         .ndo_set_mac_address = ethoc_set_mac_address,
1001         .ndo_set_rx_mode = ethoc_set_multicast_list,
1002         .ndo_change_mtu = ethoc_change_mtu,
1003         .ndo_tx_timeout = ethoc_tx_timeout,
1004         .ndo_start_xmit = ethoc_start_xmit,
1005 };
1006 
1007 /**
1008  * ethoc_probe - initialize OpenCores ethernet MAC
1009  * pdev:        platform device
1010  */
1011 static int ethoc_probe(struct platform_device *pdev)
1012 {
1013         struct net_device *netdev = NULL;
1014         struct resource *res = NULL;
1015         struct resource *mmio = NULL;
1016         struct resource *mem = NULL;
1017         struct ethoc *priv = NULL;
1018         unsigned int phy;
1019         int num_bd;
1020         int ret = 0;
1021         bool random_mac = false;
1022         struct ethoc_platform_data *pdata = dev_get_platdata(&pdev->dev);
1023         u32 eth_clkfreq = pdata ? pdata->eth_clkfreq : 0;
1024 
1025         /* allocate networking device */
1026         netdev = alloc_etherdev(sizeof(struct ethoc));
1027         if (!netdev) {
1028                 ret = -ENOMEM;
1029                 goto out;
1030         }
1031 
1032         SET_NETDEV_DEV(netdev, &pdev->dev);
1033         platform_set_drvdata(pdev, netdev);
1034 
1035         /* obtain I/O memory space */
1036         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1037         if (!res) {
1038                 dev_err(&pdev->dev, "cannot obtain I/O memory space\n");
1039                 ret = -ENXIO;
1040                 goto free;
1041         }
1042 
1043         mmio = devm_request_mem_region(&pdev->dev, res->start,
1044                         resource_size(res), res->name);
1045         if (!mmio) {
1046                 dev_err(&pdev->dev, "cannot request I/O memory space\n");
1047                 ret = -ENXIO;
1048                 goto free;
1049         }
1050 
1051         netdev->base_addr = mmio->start;
1052 
1053         /* obtain buffer memory space */
1054         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1055         if (res) {
1056                 mem = devm_request_mem_region(&pdev->dev, res->start,
1057                         resource_size(res), res->name);
1058                 if (!mem) {
1059                         dev_err(&pdev->dev, "cannot request memory space\n");
1060                         ret = -ENXIO;
1061                         goto free;
1062                 }
1063 
1064                 netdev->mem_start = mem->start;
1065                 netdev->mem_end   = mem->end;
1066         }
1067 
1068 
1069         /* obtain device IRQ number */
1070         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1071         if (!res) {
1072                 dev_err(&pdev->dev, "cannot obtain IRQ\n");
1073                 ret = -ENXIO;
1074                 goto free;
1075         }
1076 
1077         netdev->irq = res->start;
1078 
1079         /* setup driver-private data */
1080         priv = netdev_priv(netdev);
1081         priv->netdev = netdev;
1082         priv->dma_alloc = 0;
1083         priv->io_region_size = resource_size(mmio);
1084 
1085         priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr,
1086                         resource_size(mmio));
1087         if (!priv->iobase) {
1088                 dev_err(&pdev->dev, "cannot remap I/O memory space\n");
1089                 ret = -ENXIO;
1090                 goto error;
1091         }
1092 
1093         if (netdev->mem_end) {
1094                 priv->membase = devm_ioremap_nocache(&pdev->dev,
1095                         netdev->mem_start, resource_size(mem));
1096                 if (!priv->membase) {
1097                         dev_err(&pdev->dev, "cannot remap memory space\n");
1098                         ret = -ENXIO;
1099                         goto error;
1100                 }
1101         } else {
1102                 /* Allocate buffer memory */
1103                 priv->membase = dmam_alloc_coherent(&pdev->dev,
1104                         buffer_size, (void *)&netdev->mem_start,
1105                         GFP_KERNEL);
1106                 if (!priv->membase) {
1107                         dev_err(&pdev->dev, "cannot allocate %dB buffer\n",
1108                                 buffer_size);
1109                         ret = -ENOMEM;
1110                         goto error;
1111                 }
1112                 netdev->mem_end = netdev->mem_start + buffer_size;
1113                 priv->dma_alloc = buffer_size;
1114         }
1115 
1116         priv->big_endian = pdata ? pdata->big_endian :
1117                 of_device_is_big_endian(pdev->dev.of_node);
1118 
1119         /* calculate the number of TX/RX buffers, maximum 128 supported */
1120         num_bd = min_t(unsigned int,
1121                 128, (netdev->mem_end - netdev->mem_start + 1) / ETHOC_BUFSIZ);
1122         if (num_bd < 4) {
1123                 ret = -ENODEV;
1124                 goto error;
1125         }
1126         priv->num_bd = num_bd;
1127         /* num_tx must be a power of two */
1128         priv->num_tx = rounddown_pow_of_two(num_bd >> 1);
1129         priv->num_rx = num_bd - priv->num_tx;
1130 
1131         dev_dbg(&pdev->dev, "ethoc: num_tx: %d num_rx: %d\n",
1132                 priv->num_tx, priv->num_rx);
1133 
1134         priv->vma = devm_kzalloc(&pdev->dev, num_bd*sizeof(void *), GFP_KERNEL);
1135         if (!priv->vma) {
1136                 ret = -ENOMEM;
1137                 goto error;
1138         }
1139 
1140         /* Allow the platform setup code to pass in a MAC address. */
1141         if (pdata) {
1142                 memcpy(netdev->dev_addr, pdata->hwaddr, IFHWADDRLEN);
1143                 priv->phy_id = pdata->phy_id;
1144         } else {
1145                 const uint8_t *mac;
1146 
1147                 mac = of_get_property(pdev->dev.of_node,
1148                                       "local-mac-address",
1149                                       NULL);
1150                 if (mac)
1151                         memcpy(netdev->dev_addr, mac, IFHWADDRLEN);
1152                 priv->phy_id = -1;
1153         }
1154 
1155         /* Check that the given MAC address is valid. If it isn't, read the
1156          * current MAC from the controller.
1157          */
1158         if (!is_valid_ether_addr(netdev->dev_addr))
1159                 ethoc_get_mac_address(netdev, netdev->dev_addr);
1160 
1161         /* Check the MAC again for validity, if it still isn't choose and
1162          * program a random one.
1163          */
1164         if (!is_valid_ether_addr(netdev->dev_addr)) {
1165                 eth_random_addr(netdev->dev_addr);
1166                 random_mac = true;
1167         }
1168 
1169         ethoc_do_set_mac_address(netdev);
1170 
1171         if (random_mac)
1172                 netdev->addr_assign_type = NET_ADDR_RANDOM;
1173 
1174         /* Allow the platform setup code to adjust MII management bus clock. */
1175         if (!eth_clkfreq) {
1176                 struct clk *clk = devm_clk_get(&pdev->dev, NULL);
1177 
1178                 if (!IS_ERR(clk)) {
1179                         priv->clk = clk;
1180                         clk_prepare_enable(clk);
1181                         eth_clkfreq = clk_get_rate(clk);
1182                 }
1183         }
1184         if (eth_clkfreq) {
1185                 u32 clkdiv = MIIMODER_CLKDIV(eth_clkfreq / 2500000 + 1);
1186 
1187                 if (!clkdiv)
1188                         clkdiv = 2;
1189                 dev_dbg(&pdev->dev, "setting MII clkdiv to %u\n", clkdiv);
1190                 ethoc_write(priv, MIIMODER,
1191                             (ethoc_read(priv, MIIMODER) & MIIMODER_NOPRE) |
1192                             clkdiv);
1193         }
1194 
1195         /* register MII bus */
1196         priv->mdio = mdiobus_alloc();
1197         if (!priv->mdio) {
1198                 ret = -ENOMEM;
1199                 goto free;
1200         }
1201 
1202         priv->mdio->name = "ethoc-mdio";
1203         snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d",
1204                         priv->mdio->name, pdev->id);
1205         priv->mdio->read = ethoc_mdio_read;
1206         priv->mdio->write = ethoc_mdio_write;
1207         priv->mdio->priv = priv;
1208 
1209         priv->mdio->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1210         if (!priv->mdio->irq) {
1211                 ret = -ENOMEM;
1212                 goto free_mdio;
1213         }
1214 
1215         for (phy = 0; phy < PHY_MAX_ADDR; phy++)
1216                 priv->mdio->irq[phy] = PHY_POLL;
1217 
1218         ret = mdiobus_register(priv->mdio);
1219         if (ret) {
1220                 dev_err(&netdev->dev, "failed to register MDIO bus\n");
1221                 goto free_mdio;
1222         }
1223 
1224         ret = ethoc_mdio_probe(netdev);
1225         if (ret) {
1226                 dev_err(&netdev->dev, "failed to probe MDIO bus\n");
1227                 goto error;
1228         }
1229 
1230         /* setup the net_device structure */
1231         netdev->netdev_ops = &ethoc_netdev_ops;
1232         netdev->watchdog_timeo = ETHOC_TIMEOUT;
1233         netdev->features |= 0;
1234         netdev->ethtool_ops = &ethoc_ethtool_ops;
1235 
1236         /* setup NAPI */
1237         netif_napi_add(netdev, &priv->napi, ethoc_poll, 64);
1238 
1239         spin_lock_init(&priv->lock);
1240 
1241         ret = register_netdev(netdev);
1242         if (ret < 0) {
1243                 dev_err(&netdev->dev, "failed to register interface\n");
1244                 goto error2;
1245         }
1246 
1247         goto out;
1248 
1249 error2:
1250         netif_napi_del(&priv->napi);
1251 error:
1252         mdiobus_unregister(priv->mdio);
1253 free_mdio:
1254         kfree(priv->mdio->irq);
1255         mdiobus_free(priv->mdio);
1256 free:
1257         if (priv->clk)
1258                 clk_disable_unprepare(priv->clk);
1259         free_netdev(netdev);
1260 out:
1261         return ret;
1262 }
1263 
1264 /**
1265  * ethoc_remove - shutdown OpenCores ethernet MAC
1266  * @pdev:       platform device
1267  */
1268 static int ethoc_remove(struct platform_device *pdev)
1269 {
1270         struct net_device *netdev = platform_get_drvdata(pdev);
1271         struct ethoc *priv = netdev_priv(netdev);
1272 
1273         if (netdev) {
1274                 netif_napi_del(&priv->napi);
1275                 phy_disconnect(priv->phy);
1276                 priv->phy = NULL;
1277 
1278                 if (priv->mdio) {
1279                         mdiobus_unregister(priv->mdio);
1280                         kfree(priv->mdio->irq);
1281                         mdiobus_free(priv->mdio);
1282                 }
1283                 if (priv->clk)
1284                         clk_disable_unprepare(priv->clk);
1285                 unregister_netdev(netdev);
1286                 free_netdev(netdev);
1287         }
1288 
1289         return 0;
1290 }
1291 
1292 #ifdef CONFIG_PM
1293 static int ethoc_suspend(struct platform_device *pdev, pm_message_t state)
1294 {
1295         return -ENOSYS;
1296 }
1297 
1298 static int ethoc_resume(struct platform_device *pdev)
1299 {
1300         return -ENOSYS;
1301 }
1302 #else
1303 # define ethoc_suspend NULL
1304 # define ethoc_resume  NULL
1305 #endif
1306 
1307 static const struct of_device_id ethoc_match[] = {
1308         { .compatible = "opencores,ethoc", },
1309         {},
1310 };
1311 MODULE_DEVICE_TABLE(of, ethoc_match);
1312 
1313 static struct platform_driver ethoc_driver = {
1314         .probe   = ethoc_probe,
1315         .remove  = ethoc_remove,
1316         .suspend = ethoc_suspend,
1317         .resume  = ethoc_resume,
1318         .driver  = {
1319                 .name = "ethoc",
1320                 .of_match_table = ethoc_match,
1321         },
1322 };
1323 
1324 module_platform_driver(ethoc_driver);
1325 
1326 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1327 MODULE_DESCRIPTION("OpenCores Ethernet MAC driver");
1328 MODULE_LICENSE("GPL v2");
1329 
1330 

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