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Linux/drivers/net/ethernet/dec/tulip/de4x5.c

  1 /*  de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500
  2              ethernet driver for Linux.
  3 
  4     Copyright 1994, 1995 Digital Equipment Corporation.
  5 
  6     Testing resources for this driver have been made available
  7     in part by NASA Ames Research Center (mjacob@nas.nasa.gov).
  8 
  9     The author may be reached at davies@maniac.ultranet.com.
 10 
 11     This program is free software; you can redistribute  it and/or modify it
 12     under  the terms of  the GNU General  Public License as published by the
 13     Free Software Foundation;  either version 2 of the  License, or (at your
 14     option) any later version.
 15 
 16     THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR   IMPLIED
 17     WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 18     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 19     NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
 20     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 21     NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 22     USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 23     ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 24     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 25     THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 26 
 27     You should have received a copy of the  GNU General Public License along
 28     with this program; if not, write  to the Free Software Foundation, Inc.,
 29     675 Mass Ave, Cambridge, MA 02139, USA.
 30 
 31     Originally,   this  driver  was    written  for the  Digital   Equipment
 32     Corporation series of EtherWORKS ethernet cards:
 33 
 34         DE425 TP/COAX EISA
 35         DE434 TP PCI
 36         DE435 TP/COAX/AUI PCI
 37         DE450 TP/COAX/AUI PCI
 38         DE500 10/100 PCI Fasternet
 39 
 40     but it  will  now attempt  to  support all  cards which   conform to the
 41     Digital Semiconductor   SROM   Specification.    The  driver   currently
 42     recognises the following chips:
 43 
 44         DC21040  (no SROM)
 45         DC21041[A]
 46         DC21140[A]
 47         DC21142
 48         DC21143
 49 
 50     So far the driver is known to work with the following cards:
 51 
 52         KINGSTON
 53         Linksys
 54         ZNYX342
 55         SMC8432
 56         SMC9332 (w/new SROM)
 57         ZNYX31[45]
 58         ZNYX346 10/100 4 port (can act as a 10/100 bridge!)
 59 
 60     The driver has been tested on a relatively busy network using the DE425,
 61     DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
 62     16M of data to a DECstation 5000/200 as follows:
 63 
 64                 TCP           UDP
 65              TX     RX     TX     RX
 66     DE425   1030k  997k   1170k  1128k
 67     DE434   1063k  995k   1170k  1125k
 68     DE435   1063k  995k   1170k  1125k
 69     DE500   1063k  998k   1170k  1125k  in 10Mb/s mode
 70 
 71     All  values are typical (in   kBytes/sec) from a  sample  of 4 for  each
 72     measurement. Their error is +/-20k on a quiet (private) network and also
 73     depend on what load the CPU has.
 74 
 75     =========================================================================
 76     This driver  has been written substantially  from  scratch, although its
 77     inheritance of style and stack interface from 'ewrk3.c' and in turn from
 78     Donald Becker's 'lance.c' should be obvious. With the module autoload of
 79     every  usable DECchip board,  I  pinched Donald's 'next_module' field to
 80     link my modules together.
 81 
 82     Up to 15 EISA cards can be supported under this driver, limited primarily
 83     by the available IRQ lines.  I have  checked different configurations of
 84     multiple depca, EtherWORKS 3 cards and de4x5 cards and  have not found a
 85     problem yet (provided you have at least depca.c v0.38) ...
 86 
 87     PCI support has been added  to allow the driver  to work with the DE434,
 88     DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due
 89     to the differences in the EISA and PCI CSR address offsets from the base
 90     address.
 91 
 92     The ability to load this  driver as a loadable  module has been included
 93     and used extensively  during the driver development  (to save those long
 94     reboot sequences).  Loadable module support  under PCI and EISA has been
 95     achieved by letting the driver autoprobe as if it were compiled into the
 96     kernel. Do make sure  you're not sharing  interrupts with anything  that
 97     cannot accommodate  interrupt  sharing!
 98 
 99     To utilise this ability, you have to do 8 things:
100 
101     0) have a copy of the loadable modules code installed on your system.
102     1) copy de4x5.c from the  /linux/drivers/net directory to your favourite
103     temporary directory.
104     2) for fixed  autoprobes (not  recommended),  edit the source code  near
105     line 5594 to reflect the I/O address  you're using, or assign these when
106     loading by:
107 
108                    insmod de4x5 io=0xghh           where g = bus number
109                                                         hh = device number
110 
111        NB: autoprobing for modules is now supported by default. You may just
112            use:
113 
114                    insmod de4x5
115 
116            to load all available boards. For a specific board, still use
117            the 'io=?' above.
118     3) compile  de4x5.c, but include -DMODULE in  the command line to ensure
119     that the correct bits are compiled (see end of source code).
120     4) if you are wanting to add a new  card, goto 5. Otherwise, recompile a
121     kernel with the de4x5 configuration turned off and reboot.
122     5) insmod de4x5 [io=0xghh]
123     6) run the net startup bits for your new eth?? interface(s) manually
124     (usually /etc/rc.inet[12] at boot time).
125     7) enjoy!
126 
127     To unload a module, turn off the associated interface(s)
128     'ifconfig eth?? down' then 'rmmod de4x5'.
129 
130     Automedia detection is included so that in  principal you can disconnect
131     from, e.g.  TP, reconnect  to BNC  and  things will still work  (after a
132     pause whilst the   driver figures out   where its media went).  My tests
133     using ping showed that it appears to work....
134 
135     By  default,  the driver will  now   autodetect any  DECchip based card.
136     Should you have a need to restrict the driver to DIGITAL only cards, you
137     can compile with a  DEC_ONLY define, or if  loading as a module, use the
138     'dec_only=1'  parameter.
139 
140     I've changed the timing routines to  use the kernel timer and scheduling
141     functions  so that the  hangs  and other assorted problems that occurred
142     while autosensing the  media  should be gone.  A  bonus  for the DC21040
143     auto  media sense algorithm is  that it can now  use one that is more in
144     line with the  rest (the DC21040  chip doesn't  have a hardware  timer).
145     The downside is the 1 'jiffies' (10ms) resolution.
146 
147     IEEE 802.3u MII interface code has  been added in anticipation that some
148     products may use it in the future.
149 
150     The SMC9332 card  has a non-compliant SROM  which needs fixing -  I have
151     patched this  driver to detect it  because the SROM format used complies
152     to a previous DEC-STD format.
153 
154     I have removed the buffer copies needed for receive on Intels.  I cannot
155     remove them for   Alphas since  the  Tulip hardware   only does longword
156     aligned  DMA transfers  and  the  Alphas get   alignment traps with  non
157     longword aligned data copies (which makes them really slow). No comment.
158 
159     I  have added SROM decoding  routines to make this  driver work with any
160     card that  supports the Digital  Semiconductor SROM spec. This will help
161     all  cards running the dc2114x  series chips in particular.  Cards using
162     the dc2104x  chips should run correctly with  the basic  driver.  I'm in
163     debt to <mjacob@feral.com> for the  testing and feedback that helped get
164     this feature working.  So far we have  tested KINGSTON, SMC8432, SMC9332
165     (with the latest SROM complying  with the SROM spec  V3: their first was
166     broken), ZNYX342  and  LinkSys. ZYNX314 (dual  21041  MAC) and  ZNYX 315
167     (quad 21041 MAC)  cards also  appear  to work despite their  incorrectly
168     wired IRQs.
169 
170     I have added a temporary fix for interrupt problems when some SCSI cards
171     share the same interrupt as the DECchip based  cards. The problem occurs
172     because  the SCSI card wants to  grab the interrupt  as a fast interrupt
173     (runs the   service routine with interrupts turned   off) vs.  this card
174     which really needs to run the service routine with interrupts turned on.
175     This driver will  now   add the interrupt service   routine  as  a  fast
176     interrupt if it   is bounced from the   slow interrupt.  THIS IS NOT   A
177     RECOMMENDED WAY TO RUN THE DRIVER  and has been done  for a limited time
178     until  people   sort  out their  compatibility    issues and the  kernel
179     interrupt  service code  is  fixed.   YOU  SHOULD SEPARATE OUT  THE FAST
180     INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not
181     run on the same interrupt. PCMCIA/CardBus is another can of worms...
182 
183     Finally, I think  I have really  fixed  the module  loading problem with
184     more than one DECchip based  card.  As a  side effect, I don't mess with
185     the  device structure any  more which means that  if more than 1 card in
186     2.0.x is    installed (4  in   2.1.x),  the  user   will have   to  edit
187     linux/drivers/net/Space.c  to make room for  them. Hence, module loading
188     is  the preferred way to use   this driver, since  it  doesn't have this
189     limitation.
190 
191     Where SROM media  detection is used and  full duplex is specified in the
192     SROM,  the feature is  ignored unless  lp->params.fdx  is set at compile
193     time  OR during  a   module load  (insmod  de4x5   args='eth??:fdx' [see
194     below]).  This is because there  is no way  to automatically detect full
195     duplex   links  except through   autonegotiation.    When I  include the
196     autonegotiation feature in  the SROM autoconf  code, this detection will
197     occur automatically for that case.
198 
199     Command  line arguments are  now  allowed, similar  to passing arguments
200     through LILO. This will allow a per adapter board  set up of full duplex
201     and media. The only lexical constraints  are: the board name (dev->name)
202     appears in the list before its  parameters.  The list of parameters ends
203     either at the end of the parameter list or with another board name.  The
204     following parameters are allowed:
205 
206             fdx        for full duplex
207             autosense  to set the media/speed; with the following
208                        sub-parameters:
209                        TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO
210 
211     Case sensitivity is important  for  the sub-parameters. They *must*   be
212     upper case. Examples:
213 
214         insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
215 
216     For a compiled in driver, at or above line 548, place e.g.
217         #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
218 
219     Yes,  I know full duplex isn't  permissible on BNC  or AUI; they're just
220     examples. By default, full duplex is turned off and  AUTO is the default
221     autosense setting.  In reality, I expect only  the full duplex option to
222     be used. Note the use of single quotes in the two examples above and the
223     lack of commas to separate items. ALSO, you must get the requested media
224     correct in relation to what the adapter SROM says it has. There's no way
225     to  determine this in  advance other than by  trial and error and common
226     sense, e.g. call a BNC connectored port 'BNC', not '10Mb'.
227 
228     Changed the bus probing.  EISA used to be  done first,  followed by PCI.
229     Most people probably don't even know  what a de425 is today and the EISA
230     probe has messed  up some SCSI cards  in the past,  so now PCI is always
231     probed  first  followed by  EISA if  a) the architecture allows EISA and
232     either  b) there have been no PCI cards detected or  c) an EISA probe is
233     forced by  the user.  To force  a probe  include  "force_eisa"  in  your
234     insmod "args" line;  for built-in kernels either change the driver to do
235     this  automatically  or include  #define DE4X5_FORCE_EISA  on or  before
236     line 1040 in the driver.
237 
238     TO DO:
239     ------
240 
241     Revision History
242     ----------------
243 
244     Version   Date        Description
245 
246       0.1     17-Nov-94   Initial writing. ALPHA code release.
247       0.2     13-Jan-95   Added PCI support for DE435's.
248       0.21    19-Jan-95   Added auto media detection.
249       0.22    10-Feb-95   Fix interrupt handler call <chris@cosy.sbg.ac.at>.
250                           Fix recognition bug reported by <bkm@star.rl.ac.uk>.
251                           Add request/release_region code.
252                           Add loadable modules support for PCI.
253                           Clean up loadable modules support.
254       0.23    28-Feb-95   Added DC21041 and DC21140 support.
255                           Fix missed frame counter value and initialisation.
256                           Fixed EISA probe.
257       0.24    11-Apr-95   Change delay routine to use <linux/udelay>.
258                           Change TX_BUFFS_AVAIL macro.
259                           Change media autodetection to allow manual setting.
260                           Completed DE500 (DC21140) support.
261       0.241   18-Apr-95   Interim release without DE500 Autosense Algorithm.
262       0.242   10-May-95   Minor changes.
263       0.30    12-Jun-95   Timer fix for DC21140.
264                           Portability changes.
265                           Add ALPHA changes from <jestabro@ant.tay1.dec.com>.
266                           Add DE500 semi automatic autosense.
267                           Add Link Fail interrupt TP failure detection.
268                           Add timer based link change detection.
269                           Plugged a memory leak in de4x5_queue_pkt().
270       0.31    13-Jun-95   Fixed PCI stuff for 1.3.1.
271       0.32    26-Jun-95   Added verify_area() calls in de4x5_ioctl() from a
272                           suggestion by <heiko@colossus.escape.de>.
273       0.33     8-Aug-95   Add shared interrupt support (not released yet).
274       0.331   21-Aug-95   Fix de4x5_open() with fast CPUs.
275                           Fix de4x5_interrupt().
276                           Fix dc21140_autoconf() mess.
277                           No shared interrupt support.
278       0.332   11-Sep-95   Added MII management interface routines.
279       0.40     5-Mar-96   Fix setup frame timeout <maartenb@hpkuipc.cern.ch>.
280                           Add kernel timer code (h/w is too flaky).
281                           Add MII based PHY autosense.
282                           Add new multicasting code.
283                           Add new autosense algorithms for media/mode
284                           selection using kernel scheduling/timing.
285                           Re-formatted.
286                           Made changes suggested by <jeff@router.patch.net>:
287                             Change driver to detect all DECchip based cards
288                             with DEC_ONLY restriction a special case.
289                             Changed driver to autoprobe as a module. No irq
290                             checking is done now - assume BIOS is good!
291                           Added SMC9332 detection <manabe@Roy.dsl.tutics.ac.jp>
292       0.41    21-Mar-96   Don't check for get_hw_addr checksum unless DEC card
293                           only <niles@axp745gsfc.nasa.gov>
294                           Fix for multiple PCI cards reported by <jos@xos.nl>
295                           Duh, put the IRQF_SHARED flag into request_interrupt().
296                           Fix SMC ethernet address in enet_det[].
297                           Print chip name instead of "UNKNOWN" during boot.
298       0.42    26-Apr-96   Fix MII write TA bit error.
299                           Fix bug in dc21040 and dc21041 autosense code.
300                           Remove buffer copies on receive for Intels.
301                           Change sk_buff handling during media disconnects to
302                            eliminate DUP packets.
303                           Add dynamic TX thresholding.
304                           Change all chips to use perfect multicast filtering.
305                           Fix alloc_device() bug <jari@markkus2.fimr.fi>
306       0.43   21-Jun-96    Fix unconnected media TX retry bug.
307                           Add Accton to the list of broken cards.
308                           Fix TX under-run bug for non DC21140 chips.
309                           Fix boot command probe bug in alloc_device() as
310                            reported by <koen.gadeyne@barco.com> and
311                            <orava@nether.tky.hut.fi>.
312                           Add cache locks to prevent a race condition as
313                            reported by <csd@microplex.com> and
314                            <baba@beckman.uiuc.edu>.
315                           Upgraded alloc_device() code.
316       0.431  28-Jun-96    Fix potential bug in queue_pkt() from discussion
317                           with <csd@microplex.com>
318       0.44   13-Aug-96    Fix RX overflow bug in 2114[023] chips.
319                           Fix EISA probe bugs reported by <os2@kpi.kharkov.ua>
320                           and <michael@compurex.com>.
321       0.441   9-Sep-96    Change dc21041_autoconf() to probe quiet BNC media
322                            with a loopback packet.
323       0.442   9-Sep-96    Include AUI in dc21041 media printout. Bug reported
324                            by <bhat@mundook.cs.mu.OZ.AU>
325       0.45    8-Dec-96    Include endian functions for PPC use, from work
326                            by <cort@cs.nmt.edu> and <g.thomas@opengroup.org>.
327       0.451  28-Dec-96    Added fix to allow autoprobe for modules after
328                            suggestion from <mjacob@feral.com>.
329       0.5    30-Jan-97    Added SROM decoding functions.
330                           Updated debug flags.
331                           Fix sleep/wakeup calls for PCI cards, bug reported
332                            by <cross@gweep.lkg.dec.com>.
333                           Added multi-MAC, one SROM feature from discussion
334                            with <mjacob@feral.com>.
335                           Added full module autoprobe capability.
336                           Added attempt to use an SMC9332 with broken SROM.
337                           Added fix for ZYNX multi-mac cards that didn't
338                            get their IRQs wired correctly.
339       0.51   13-Feb-97    Added endian fixes for the SROM accesses from
340                            <paubert@iram.es>
341                           Fix init_connection() to remove extra device reset.
342                           Fix MAC/PHY reset ordering in dc21140m_autoconf().
343                           Fix initialisation problem with lp->timeout in
344                            typeX_infoblock() from <paubert@iram.es>.
345                           Fix MII PHY reset problem from work done by
346                            <paubert@iram.es>.
347       0.52   26-Apr-97    Some changes may not credit the right people -
348                            a disk crash meant I lost some mail.
349                           Change RX interrupt routine to drop rather than
350                            defer packets to avoid hang reported by
351                            <g.thomas@opengroup.org>.
352                           Fix srom_exec() to return for COMPACT and type 1
353                            infoblocks.
354                           Added DC21142 and DC21143 functions.
355                           Added byte counters from <phil@tazenda.demon.co.uk>
356                           Added IRQF_DISABLED temporary fix from
357                            <mjacob@feral.com>.
358       0.53   12-Nov-97    Fix the *_probe() to include 'eth??' name during
359                            module load: bug reported by
360                            <Piete.Brooks@cl.cam.ac.uk>
361                           Fix multi-MAC, one SROM, to work with 2114x chips:
362                            bug reported by <cmetz@inner.net>.
363                           Make above search independent of BIOS device scan
364                            direction.
365                           Completed DC2114[23] autosense functions.
366       0.531  21-Dec-97    Fix DE500-XA 100Mb/s bug reported by
367                            <robin@intercore.com
368                           Fix type1_infoblock() bug introduced in 0.53, from
369                            problem reports by
370                            <parmee@postecss.ncrfran.france.ncr.com> and
371                            <jo@ice.dillingen.baynet.de>.
372                           Added argument list to set up each board from either
373                            a module's command line or a compiled in #define.
374                           Added generic MII PHY functionality to deal with
375                            newer PHY chips.
376                           Fix the mess in 2.1.67.
377       0.532   5-Jan-98    Fix bug in mii_get_phy() reported by
378                            <redhat@cococo.net>.
379                           Fix bug in pci_probe() for 64 bit systems reported
380                            by <belliott@accessone.com>.
381       0.533   9-Jan-98    Fix more 64 bit bugs reported by <jal@cs.brown.edu>.
382       0.534  24-Jan-98    Fix last (?) endian bug from <geert@linux-m68k.org>
383       0.535  21-Feb-98    Fix Ethernet Address PROM reset bug for DC21040.
384       0.536  21-Mar-98    Change pci_probe() to use the pci_dev structure.
385                           **Incompatible with 2.0.x from here.**
386       0.540   5-Jul-98    Atomicize assertion of dev->interrupt for SMP
387                            from <lma@varesearch.com>
388                           Add TP, AUI and BNC cases to 21140m_autoconf() for
389                            case where a 21140 under SROM control uses, e.g. AUI
390                            from problem report by <delchini@lpnp09.in2p3.fr>
391                           Add MII parallel detection to 2114x_autoconf() for
392                            case where no autonegotiation partner exists from
393                            problem report by <mlapsley@ndirect.co.uk>.
394                           Add ability to force connection type directly even
395                            when using SROM control from problem report by
396                            <earl@exis.net>.
397                           Updated the PCI interface to conform with the latest
398                            version. I hope nothing is broken...
399                           Add TX done interrupt modification from suggestion
400                            by <Austin.Donnelly@cl.cam.ac.uk>.
401                           Fix is_anc_capable() bug reported by
402                            <Austin.Donnelly@cl.cam.ac.uk>.
403                           Fix type[13]_infoblock() bug: during MII search, PHY
404                            lp->rst not run because lp->ibn not initialised -
405                            from report & fix by <paubert@iram.es>.
406                           Fix probe bug with EISA & PCI cards present from
407                            report by <eirik@netcom.com>.
408       0.541  24-Aug-98    Fix compiler problems associated with i386-string
409                            ops from multiple bug reports and temporary fix
410                            from <paubert@iram.es>.
411                           Fix pci_probe() to correctly emulate the old
412                            pcibios_find_class() function.
413                           Add an_exception() for old ZYNX346 and fix compile
414                            warning on PPC & SPARC, from <ecd@skynet.be>.
415                           Fix lastPCI to correctly work with compiled in
416                            kernels and modules from bug report by
417                            <Zlatko.Calusic@CARNet.hr> et al.
418       0.542  15-Sep-98    Fix dc2114x_autoconf() to stop multiple messages
419                            when media is unconnected.
420                           Change dev->interrupt to lp->interrupt to ensure
421                            alignment for Alpha's and avoid their unaligned
422                            access traps. This flag is merely for log messages:
423                            should do something more definitive though...
424       0.543  30-Dec-98    Add SMP spin locking.
425       0.544   8-May-99    Fix for buggy SROM in Motorola embedded boards using
426                            a 21143 by <mmporter@home.com>.
427                           Change PCI/EISA bus probing order.
428       0.545  28-Nov-99    Further Moto SROM bug fix from
429                            <mporter@eng.mcd.mot.com>
430                           Remove double checking for DEBUG_RX in de4x5_dbg_rx()
431                            from report by <geert@linux-m68k.org>
432       0.546  22-Feb-01    Fixes Alpha XP1000 oops.  The srom_search function
433                            was causing a page fault when initializing the
434                            variable 'pb', on a non de4x5 PCI device, in this
435                            case a PCI bridge (DEC chip 21152). The value of
436                            'pb' is now only initialized if a de4x5 chip is
437                            present.
438                            <france@handhelds.org>
439       0.547  08-Nov-01    Use library crc32 functions by <Matt_Domsch@dell.com>
440       0.548  30-Aug-03    Big 2.6 cleanup. Ported to PCI/EISA probing and
441                            generic DMA APIs. Fixed DE425 support on Alpha.
442                            <maz@wild-wind.fr.eu.org>
443     =========================================================================
444 */
445 
446 #include <linux/module.h>
447 #include <linux/kernel.h>
448 #include <linux/string.h>
449 #include <linux/interrupt.h>
450 #include <linux/ptrace.h>
451 #include <linux/errno.h>
452 #include <linux/ioport.h>
453 #include <linux/pci.h>
454 #include <linux/eisa.h>
455 #include <linux/delay.h>
456 #include <linux/init.h>
457 #include <linux/spinlock.h>
458 #include <linux/crc32.h>
459 #include <linux/netdevice.h>
460 #include <linux/etherdevice.h>
461 #include <linux/skbuff.h>
462 #include <linux/time.h>
463 #include <linux/types.h>
464 #include <linux/unistd.h>
465 #include <linux/ctype.h>
466 #include <linux/dma-mapping.h>
467 #include <linux/moduleparam.h>
468 #include <linux/bitops.h>
469 #include <linux/gfp.h>
470 
471 #include <asm/io.h>
472 #include <asm/dma.h>
473 #include <asm/byteorder.h>
474 #include <asm/unaligned.h>
475 #include <asm/uaccess.h>
476 #ifdef CONFIG_PPC_PMAC
477 #include <asm/machdep.h>
478 #endif /* CONFIG_PPC_PMAC */
479 
480 #include "de4x5.h"
481 
482 static const char version[] =
483         KERN_INFO "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n";
484 
485 #define c_char const char
486 
487 /*
488 ** MII Information
489 */
490 struct phy_table {
491     int reset;              /* Hard reset required?                         */
492     int id;                 /* IEEE OUI                                     */
493     int ta;                 /* One cycle TA time - 802.3u is confusing here */
494     struct {                /* Non autonegotiation (parallel) speed det.    */
495         int reg;
496         int mask;
497         int value;
498     } spd;
499 };
500 
501 struct mii_phy {
502     int reset;              /* Hard reset required?                      */
503     int id;                 /* IEEE OUI                                  */
504     int ta;                 /* One cycle TA time                         */
505     struct {                /* Non autonegotiation (parallel) speed det. */
506         int reg;
507         int mask;
508         int value;
509     } spd;
510     int addr;               /* MII address for the PHY                   */
511     u_char  *gep;           /* Start of GEP sequence block in SROM       */
512     u_char  *rst;           /* Start of reset sequence in SROM           */
513     u_int mc;               /* Media Capabilities                        */
514     u_int ana;              /* NWay Advertisement                        */
515     u_int fdx;              /* Full DupleX capabilities for each media   */
516     u_int ttm;              /* Transmit Threshold Mode for each media    */
517     u_int mci;              /* 21142 MII Connector Interrupt info        */
518 };
519 
520 #define DE4X5_MAX_PHY 8     /* Allow up to 8 attached PHY devices per board */
521 
522 struct sia_phy {
523     u_char mc;              /* Media Code                                */
524     u_char ext;             /* csr13-15 valid when set                   */
525     int csr13;              /* SIA Connectivity Register                 */
526     int csr14;              /* SIA TX/RX Register                        */
527     int csr15;              /* SIA General Register                      */
528     int gepc;               /* SIA GEP Control Information               */
529     int gep;                /* SIA GEP Data                              */
530 };
531 
532 /*
533 ** Define the know universe of PHY devices that can be
534 ** recognised by this driver.
535 */
536 static struct phy_table phy_info[] = {
537     {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}},       /* National TX      */
538     {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}},       /* Broadcom T4      */
539     {0, SEEQ_T4    , 1, {0x12, 0x10, 0x10}},       /* SEEQ T4          */
540     {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}},       /* Cypress T4       */
541     {0, 0x7810     , 1, {0x14, 0x0800, 0x0800}}    /* Level One LTX970 */
542 };
543 
544 /*
545 ** These GENERIC values assumes that the PHY devices follow 802.3u and
546 ** allow parallel detection to set the link partner ability register.
547 ** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
548 */
549 #define GENERIC_REG   0x05      /* Autoneg. Link Partner Advertisement Reg. */
550 #define GENERIC_MASK  MII_ANLPA_100M /* All 100Mb/s Technologies            */
551 #define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4       */
552 
553 /*
554 ** Define special SROM detection cases
555 */
556 static c_char enet_det[][ETH_ALEN] = {
557     {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
558     {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
559 };
560 
561 #define SMC    1
562 #define ACCTON 2
563 
564 /*
565 ** SROM Repair definitions. If a broken SROM is detected a card may
566 ** use this information to help figure out what to do. This is a
567 ** "stab in the dark" and so far for SMC9332's only.
568 */
569 static c_char srom_repair_info[][100] = {
570     {0x00,0x1e,0x00,0x00,0x00,0x08,             /* SMC9332 */
571      0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
572      0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
573      0x00,0x18,}
574 };
575 
576 
577 #ifdef DE4X5_DEBUG
578 static int de4x5_debug = DE4X5_DEBUG;
579 #else
580 /*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/
581 static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION);
582 #endif
583 
584 /*
585 ** Allow per adapter set up. For modules this is simply a command line
586 ** parameter, e.g.:
587 ** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
588 **
589 ** For a compiled in driver, place e.g.
590 **     #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
591 ** here
592 */
593 #ifdef DE4X5_PARM
594 static char *args = DE4X5_PARM;
595 #else
596 static char *args;
597 #endif
598 
599 struct parameters {
600     bool fdx;
601     int autosense;
602 };
603 
604 #define DE4X5_AUTOSENSE_MS 250      /* msec autosense tick (DE500) */
605 
606 #define DE4X5_NDA 0xffe0            /* No Device (I/O) Address */
607 
608 /*
609 ** Ethernet PROM defines
610 */
611 #define PROBE_LENGTH    32
612 #define ETH_PROM_SIG    0xAA5500FFUL
613 
614 /*
615 ** Ethernet Info
616 */
617 #define PKT_BUF_SZ      1536            /* Buffer size for each Tx/Rx buffer */
618 #define IEEE802_3_SZ    1518            /* Packet + CRC */
619 #define MAX_PKT_SZ      1514            /* Maximum ethernet packet length */
620 #define MAX_DAT_SZ      1500            /* Maximum ethernet data length */
621 #define MIN_DAT_SZ      1               /* Minimum ethernet data length */
622 #define PKT_HDR_LEN     14              /* Addresses and data length info */
623 #define FAKE_FRAME_LEN  (MAX_PKT_SZ + 1)
624 #define QUEUE_PKT_TIMEOUT (3*HZ)        /* 3 second timeout */
625 
626 
627 /*
628 ** EISA bus defines
629 */
630 #define DE4X5_EISA_IO_PORTS   0x0c00    /* I/O port base address, slot 0 */
631 #define DE4X5_EISA_TOTAL_SIZE 0x100     /* I/O address extent */
632 
633 #define EISA_ALLOWED_IRQ_LIST  {5, 9, 10, 11}
634 
635 #define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
636 #define DE4X5_NAME_LENGTH 8
637 
638 static c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
639 
640 /*
641 ** Ethernet PROM defines for DC21040
642 */
643 #define PROBE_LENGTH    32
644 #define ETH_PROM_SIG    0xAA5500FFUL
645 
646 /*
647 ** PCI Bus defines
648 */
649 #define PCI_MAX_BUS_NUM      8
650 #define DE4X5_PCI_TOTAL_SIZE 0x80       /* I/O address extent */
651 #define DE4X5_CLASS_CODE     0x00020000 /* Network controller, Ethernet */
652 
653 /*
654 ** Memory Alignment. Each descriptor is 4 longwords long. To force a
655 ** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
656 ** DESC_ALIGN. ALIGN aligns the start address of the private memory area
657 ** and hence the RX descriptor ring's first entry.
658 */
659 #define DE4X5_ALIGN4      ((u_long)4 - 1)     /* 1 longword align */
660 #define DE4X5_ALIGN8      ((u_long)8 - 1)     /* 2 longword align */
661 #define DE4X5_ALIGN16     ((u_long)16 - 1)    /* 4 longword align */
662 #define DE4X5_ALIGN32     ((u_long)32 - 1)    /* 8 longword align */
663 #define DE4X5_ALIGN64     ((u_long)64 - 1)    /* 16 longword align */
664 #define DE4X5_ALIGN128    ((u_long)128 - 1)   /* 32 longword align */
665 
666 #define DE4X5_ALIGN         DE4X5_ALIGN32           /* Keep the DC21040 happy... */
667 #define DE4X5_CACHE_ALIGN   CAL_16LONG
668 #define DESC_SKIP_LEN DSL_0             /* Must agree with DESC_ALIGN */
669 /*#define DESC_ALIGN    u32 dummy[4];  / * Must agree with DESC_SKIP_LEN */
670 #define DESC_ALIGN
671 
672 #ifndef DEC_ONLY                        /* See README.de4x5 for using this */
673 static int dec_only;
674 #else
675 static int dec_only = 1;
676 #endif
677 
678 /*
679 ** DE4X5 IRQ ENABLE/DISABLE
680 */
681 #define ENABLE_IRQs { \
682     imr |= lp->irq_en;\
683     outl(imr, DE4X5_IMR);               /* Enable the IRQs */\
684 }
685 
686 #define DISABLE_IRQs {\
687     imr = inl(DE4X5_IMR);\
688     imr &= ~lp->irq_en;\
689     outl(imr, DE4X5_IMR);               /* Disable the IRQs */\
690 }
691 
692 #define UNMASK_IRQs {\
693     imr |= lp->irq_mask;\
694     outl(imr, DE4X5_IMR);               /* Unmask the IRQs */\
695 }
696 
697 #define MASK_IRQs {\
698     imr = inl(DE4X5_IMR);\
699     imr &= ~lp->irq_mask;\
700     outl(imr, DE4X5_IMR);               /* Mask the IRQs */\
701 }
702 
703 /*
704 ** DE4X5 START/STOP
705 */
706 #define START_DE4X5 {\
707     omr = inl(DE4X5_OMR);\
708     omr |= OMR_ST | OMR_SR;\
709     outl(omr, DE4X5_OMR);               /* Enable the TX and/or RX */\
710 }
711 
712 #define STOP_DE4X5 {\
713     omr = inl(DE4X5_OMR);\
714     omr &= ~(OMR_ST|OMR_SR);\
715     outl(omr, DE4X5_OMR);               /* Disable the TX and/or RX */ \
716 }
717 
718 /*
719 ** DE4X5 SIA RESET
720 */
721 #define RESET_SIA outl(0, DE4X5_SICR);  /* Reset SIA connectivity regs */
722 
723 /*
724 ** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS)
725 */
726 #define DE4X5_AUTOSENSE_MS  250
727 
728 /*
729 ** SROM Structure
730 */
731 struct de4x5_srom {
732     char sub_vendor_id[2];
733     char sub_system_id[2];
734     char reserved[12];
735     char id_block_crc;
736     char reserved2;
737     char version;
738     char num_controllers;
739     char ieee_addr[6];
740     char info[100];
741     short chksum;
742 };
743 #define SUB_VENDOR_ID 0x500a
744 
745 /*
746 ** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous
747 ** and have sizes of both a power of 2 and a multiple of 4.
748 ** A size of 256 bytes for each buffer could be chosen because over 90% of
749 ** all packets in our network are <256 bytes long and 64 longword alignment
750 ** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX
751 ** descriptors are needed for machines with an ALPHA CPU.
752 */
753 #define NUM_RX_DESC 8                   /* Number of RX descriptors   */
754 #define NUM_TX_DESC 32                  /* Number of TX descriptors   */
755 #define RX_BUFF_SZ  1536                /* Power of 2 for kmalloc and */
756                                         /* Multiple of 4 for DC21040  */
757                                         /* Allows 512 byte alignment  */
758 struct de4x5_desc {
759     volatile __le32 status;
760     __le32 des1;
761     __le32 buf;
762     __le32 next;
763     DESC_ALIGN
764 };
765 
766 /*
767 ** The DE4X5 private structure
768 */
769 #define DE4X5_PKT_STAT_SZ 16
770 #define DE4X5_PKT_BIN_SZ  128            /* Should be >=100 unless you
771                                             increase DE4X5_PKT_STAT_SZ */
772 
773 struct pkt_stats {
774         u_int bins[DE4X5_PKT_STAT_SZ];      /* Private stats counters       */
775         u_int unicast;
776         u_int multicast;
777         u_int broadcast;
778         u_int excessive_collisions;
779         u_int tx_underruns;
780         u_int excessive_underruns;
781         u_int rx_runt_frames;
782         u_int rx_collision;
783         u_int rx_dribble;
784         u_int rx_overflow;
785 };
786 
787 struct de4x5_private {
788     char adapter_name[80];                  /* Adapter name                 */
789     u_long interrupt;                       /* Aligned ISR flag             */
790     struct de4x5_desc *rx_ring;             /* RX descriptor ring           */
791     struct de4x5_desc *tx_ring;             /* TX descriptor ring           */
792     struct sk_buff *tx_skb[NUM_TX_DESC];    /* TX skb for freeing when sent */
793     struct sk_buff *rx_skb[NUM_RX_DESC];    /* RX skb's                     */
794     int rx_new, rx_old;                     /* RX descriptor ring pointers  */
795     int tx_new, tx_old;                     /* TX descriptor ring pointers  */
796     char setup_frame[SETUP_FRAME_LEN];      /* Holds MCA and PA info.       */
797     char frame[64];                         /* Min sized packet for loopback*/
798     spinlock_t lock;                        /* Adapter specific spinlock    */
799     struct net_device_stats stats;          /* Public stats                 */
800     struct pkt_stats pktStats;              /* Private stats counters       */
801     char rxRingSize;
802     char txRingSize;
803     int  bus;                               /* EISA or PCI                  */
804     int  bus_num;                           /* PCI Bus number               */
805     int  device;                            /* Device number on PCI bus     */
806     int  state;                             /* Adapter OPENED or CLOSED     */
807     int  chipset;                           /* DC21040, DC21041 or DC21140  */
808     s32  irq_mask;                          /* Interrupt Mask (Enable) bits */
809     s32  irq_en;                            /* Summary interrupt bits       */
810     int  media;                             /* Media (eg TP), mode (eg 100B)*/
811     int  c_media;                           /* Remember the last media conn */
812     bool fdx;                               /* media full duplex flag       */
813     int  linkOK;                            /* Link is OK                   */
814     int  autosense;                         /* Allow/disallow autosensing   */
815     bool tx_enable;                         /* Enable descriptor polling    */
816     int  setup_f;                           /* Setup frame filtering type   */
817     int  local_state;                       /* State within a 'media' state */
818     struct mii_phy phy[DE4X5_MAX_PHY];      /* List of attached PHY devices */
819     struct sia_phy sia;                     /* SIA PHY Information          */
820     int  active;                            /* Index to active PHY device   */
821     int  mii_cnt;                           /* Number of attached PHY's     */
822     int  timeout;                           /* Scheduling counter           */
823     struct timer_list timer;                /* Timer info for kernel        */
824     int tmp;                                /* Temporary global per card    */
825     struct {
826         u_long lock;                        /* Lock the cache accesses      */
827         s32 csr0;                           /* Saved Bus Mode Register      */
828         s32 csr6;                           /* Saved Operating Mode Reg.    */
829         s32 csr7;                           /* Saved IRQ Mask Register      */
830         s32 gep;                            /* Saved General Purpose Reg.   */
831         s32 gepc;                           /* Control info for GEP         */
832         s32 csr13;                          /* Saved SIA Connectivity Reg.  */
833         s32 csr14;                          /* Saved SIA TX/RX Register     */
834         s32 csr15;                          /* Saved SIA General Register   */
835         int save_cnt;                       /* Flag if state already saved  */
836         struct sk_buff_head queue;          /* Save the (re-ordered) skb's  */
837     } cache;
838     struct de4x5_srom srom;                 /* A copy of the SROM           */
839     int cfrv;                               /* Card CFRV copy */
840     int rx_ovf;                             /* Check for 'RX overflow' tag  */
841     bool useSROM;                           /* For non-DEC card use SROM    */
842     bool useMII;                            /* Infoblock using the MII      */
843     int asBitValid;                         /* Autosense bits in GEP?       */
844     int asPolarity;                         /* 0 => asserted high           */
845     int asBit;                              /* Autosense bit number in GEP  */
846     int defMedium;                          /* SROM default medium          */
847     int tcount;                             /* Last infoblock number        */
848     int infoblock_init;                     /* Initialised this infoblock?  */
849     int infoleaf_offset;                    /* SROM infoleaf for controller */
850     s32 infoblock_csr6;                     /* csr6 value in SROM infoblock */
851     int infoblock_media;                    /* infoblock media              */
852     int (*infoleaf_fn)(struct net_device *);    /* Pointer to infoleaf function */
853     u_char *rst;                            /* Pointer to Type 5 reset info */
854     u_char  ibn;                            /* Infoblock number             */
855     struct parameters params;               /* Command line/ #defined params */
856     struct device *gendev;                  /* Generic device */
857     dma_addr_t dma_rings;                   /* DMA handle for rings         */
858     int dma_size;                           /* Size of the DMA area         */
859     char *rx_bufs;                          /* rx bufs on alpha, sparc, ... */
860 };
861 
862 /*
863 ** To get around certain poxy cards that don't provide an SROM
864 ** for the second and more DECchip, I have to key off the first
865 ** chip's address. I'll assume there's not a bad SROM iff:
866 **
867 **      o the chipset is the same
868 **      o the bus number is the same and > 0
869 **      o the sum of all the returned hw address bytes is 0 or 0x5fa
870 **
871 ** Also have to save the irq for those cards whose hardware designers
872 ** can't follow the PCI to PCI Bridge Architecture spec.
873 */
874 static struct {
875     int chipset;
876     int bus;
877     int irq;
878     u_char addr[ETH_ALEN];
879 } last = {0,};
880 
881 /*
882 ** The transmit ring full condition is described by the tx_old and tx_new
883 ** pointers by:
884 **    tx_old            = tx_new    Empty ring
885 **    tx_old            = tx_new+1  Full ring
886 **    tx_old+txRingSize = tx_new+1  Full ring  (wrapped condition)
887 */
888 #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
889                         lp->tx_old+lp->txRingSize-lp->tx_new-1:\
890                         lp->tx_old               -lp->tx_new-1)
891 
892 #define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
893 
894 /*
895 ** Public Functions
896 */
897 static int     de4x5_open(struct net_device *dev);
898 static netdev_tx_t de4x5_queue_pkt(struct sk_buff *skb,
899                                          struct net_device *dev);
900 static irqreturn_t de4x5_interrupt(int irq, void *dev_id);
901 static int     de4x5_close(struct net_device *dev);
902 static struct  net_device_stats *de4x5_get_stats(struct net_device *dev);
903 static void    de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len);
904 static void    set_multicast_list(struct net_device *dev);
905 static int     de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
906 
907 /*
908 ** Private functions
909 */
910 static int     de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev);
911 static int     de4x5_init(struct net_device *dev);
912 static int     de4x5_sw_reset(struct net_device *dev);
913 static int     de4x5_rx(struct net_device *dev);
914 static int     de4x5_tx(struct net_device *dev);
915 static void    de4x5_ast(struct net_device *dev);
916 static int     de4x5_txur(struct net_device *dev);
917 static int     de4x5_rx_ovfc(struct net_device *dev);
918 
919 static int     autoconf_media(struct net_device *dev);
920 static void    create_packet(struct net_device *dev, char *frame, int len);
921 static void    load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb);
922 static int     dc21040_autoconf(struct net_device *dev);
923 static int     dc21041_autoconf(struct net_device *dev);
924 static int     dc21140m_autoconf(struct net_device *dev);
925 static int     dc2114x_autoconf(struct net_device *dev);
926 static int     srom_autoconf(struct net_device *dev);
927 static int     de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state, int (*fn)(struct net_device *, int), int (*asfn)(struct net_device *));
928 static int     dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct net_device *, int));
929 static int     test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
930 static int     test_for_100Mb(struct net_device *dev, int msec);
931 static int     wait_for_link(struct net_device *dev);
932 static int     test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec);
933 static int     is_spd_100(struct net_device *dev);
934 static int     is_100_up(struct net_device *dev);
935 static int     is_10_up(struct net_device *dev);
936 static int     is_anc_capable(struct net_device *dev);
937 static int     ping_media(struct net_device *dev, int msec);
938 static struct sk_buff *de4x5_alloc_rx_buff(struct net_device *dev, int index, int len);
939 static void    de4x5_free_rx_buffs(struct net_device *dev);
940 static void    de4x5_free_tx_buffs(struct net_device *dev);
941 static void    de4x5_save_skbs(struct net_device *dev);
942 static void    de4x5_rst_desc_ring(struct net_device *dev);
943 static void    de4x5_cache_state(struct net_device *dev, int flag);
944 static void    de4x5_put_cache(struct net_device *dev, struct sk_buff *skb);
945 static void    de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb);
946 static struct  sk_buff *de4x5_get_cache(struct net_device *dev);
947 static void    de4x5_setup_intr(struct net_device *dev);
948 static void    de4x5_init_connection(struct net_device *dev);
949 static int     de4x5_reset_phy(struct net_device *dev);
950 static void    reset_init_sia(struct net_device *dev, s32 sicr, s32 strr, s32 sigr);
951 static int     test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec);
952 static int     test_tp(struct net_device *dev, s32 msec);
953 static int     EISA_signature(char *name, struct device *device);
954 static int     PCI_signature(char *name, struct de4x5_private *lp);
955 static void    DevicePresent(struct net_device *dev, u_long iobase);
956 static void    enet_addr_rst(u_long aprom_addr);
957 static int     de4x5_bad_srom(struct de4x5_private *lp);
958 static short   srom_rd(u_long address, u_char offset);
959 static void    srom_latch(u_int command, u_long address);
960 static void    srom_command(u_int command, u_long address);
961 static void    srom_address(u_int command, u_long address, u_char offset);
962 static short   srom_data(u_int command, u_long address);
963 /*static void    srom_busy(u_int command, u_long address);*/
964 static void    sendto_srom(u_int command, u_long addr);
965 static int     getfrom_srom(u_long addr);
966 static int     srom_map_media(struct net_device *dev);
967 static int     srom_infoleaf_info(struct net_device *dev);
968 static void    srom_init(struct net_device *dev);
969 static void    srom_exec(struct net_device *dev, u_char *p);
970 static int     mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
971 static void    mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
972 static int     mii_rdata(u_long ioaddr);
973 static void    mii_wdata(int data, int len, u_long ioaddr);
974 static void    mii_ta(u_long rw, u_long ioaddr);
975 static int     mii_swap(int data, int len);
976 static void    mii_address(u_char addr, u_long ioaddr);
977 static void    sendto_mii(u32 command, int data, u_long ioaddr);
978 static int     getfrom_mii(u32 command, u_long ioaddr);
979 static int     mii_get_oui(u_char phyaddr, u_long ioaddr);
980 static int     mii_get_phy(struct net_device *dev);
981 static void    SetMulticastFilter(struct net_device *dev);
982 static int     get_hw_addr(struct net_device *dev);
983 static void    srom_repair(struct net_device *dev, int card);
984 static int     test_bad_enet(struct net_device *dev, int status);
985 static int     an_exception(struct de4x5_private *lp);
986 static char    *build_setup_frame(struct net_device *dev, int mode);
987 static void    disable_ast(struct net_device *dev);
988 static long    de4x5_switch_mac_port(struct net_device *dev);
989 static int     gep_rd(struct net_device *dev);
990 static void    gep_wr(s32 data, struct net_device *dev);
991 static void    yawn(struct net_device *dev, int state);
992 static void    de4x5_parse_params(struct net_device *dev);
993 static void    de4x5_dbg_open(struct net_device *dev);
994 static void    de4x5_dbg_mii(struct net_device *dev, int k);
995 static void    de4x5_dbg_media(struct net_device *dev);
996 static void    de4x5_dbg_srom(struct de4x5_srom *p);
997 static void    de4x5_dbg_rx(struct sk_buff *skb, int len);
998 static int     dc21041_infoleaf(struct net_device *dev);
999 static int     dc21140_infoleaf(struct net_device *dev);
1000 static int     dc21142_infoleaf(struct net_device *dev);
1001 static int     dc21143_infoleaf(struct net_device *dev);
1002 static int     type0_infoblock(struct net_device *dev, u_char count, u_char *p);
1003 static int     type1_infoblock(struct net_device *dev, u_char count, u_char *p);
1004 static int     type2_infoblock(struct net_device *dev, u_char count, u_char *p);
1005 static int     type3_infoblock(struct net_device *dev, u_char count, u_char *p);
1006 static int     type4_infoblock(struct net_device *dev, u_char count, u_char *p);
1007 static int     type5_infoblock(struct net_device *dev, u_char count, u_char *p);
1008 static int     compact_infoblock(struct net_device *dev, u_char count, u_char *p);
1009 
1010 /*
1011 ** Note now that module autoprobing is allowed under EISA and PCI. The
1012 ** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
1013 ** to "do the right thing".
1014 */
1015 
1016 static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED        */
1017 
1018 module_param(io, int, 0);
1019 module_param(de4x5_debug, int, 0);
1020 module_param(dec_only, int, 0);
1021 module_param(args, charp, 0);
1022 
1023 MODULE_PARM_DESC(io, "de4x5 I/O base address");
1024 MODULE_PARM_DESC(de4x5_debug, "de4x5 debug mask");
1025 MODULE_PARM_DESC(dec_only, "de4x5 probe only for Digital boards (0-1)");
1026 MODULE_PARM_DESC(args, "de4x5 full duplex and media type settings; see de4x5.c for details");
1027 MODULE_LICENSE("GPL");
1028 
1029 /*
1030 ** List the SROM infoleaf functions and chipsets
1031 */
1032 struct InfoLeaf {
1033     int chipset;
1034     int (*fn)(struct net_device *);
1035 };
1036 static struct InfoLeaf infoleaf_array[] = {
1037     {DC21041, dc21041_infoleaf},
1038     {DC21140, dc21140_infoleaf},
1039     {DC21142, dc21142_infoleaf},
1040     {DC21143, dc21143_infoleaf}
1041 };
1042 #define INFOLEAF_SIZE ARRAY_SIZE(infoleaf_array)
1043 
1044 /*
1045 ** List the SROM info block functions
1046 */
1047 static int (*dc_infoblock[])(struct net_device *dev, u_char, u_char *) = {
1048     type0_infoblock,
1049     type1_infoblock,
1050     type2_infoblock,
1051     type3_infoblock,
1052     type4_infoblock,
1053     type5_infoblock,
1054     compact_infoblock
1055 };
1056 
1057 #define COMPACT (ARRAY_SIZE(dc_infoblock) - 1)
1058 
1059 /*
1060 ** Miscellaneous defines...
1061 */
1062 #define RESET_DE4X5 {\
1063     int i;\
1064     i=inl(DE4X5_BMR);\
1065     mdelay(1);\
1066     outl(i | BMR_SWR, DE4X5_BMR);\
1067     mdelay(1);\
1068     outl(i, DE4X5_BMR);\
1069     mdelay(1);\
1070     for (i=0;i<5;i++) {inl(DE4X5_BMR); mdelay(1);}\
1071     mdelay(1);\
1072 }
1073 
1074 #define PHY_HARD_RESET {\
1075     outl(GEP_HRST, DE4X5_GEP);           /* Hard RESET the PHY dev. */\
1076     mdelay(1);                           /* Assert for 1ms */\
1077     outl(0x00, DE4X5_GEP);\
1078     mdelay(2);                           /* Wait for 2ms */\
1079 }
1080 
1081 static const struct net_device_ops de4x5_netdev_ops = {
1082     .ndo_open           = de4x5_open,
1083     .ndo_stop           = de4x5_close,
1084     .ndo_start_xmit     = de4x5_queue_pkt,
1085     .ndo_get_stats      = de4x5_get_stats,
1086     .ndo_set_rx_mode    = set_multicast_list,
1087     .ndo_do_ioctl       = de4x5_ioctl,
1088     .ndo_change_mtu     = eth_change_mtu,
1089     .ndo_set_mac_address= eth_mac_addr,
1090     .ndo_validate_addr  = eth_validate_addr,
1091 };
1092 
1093 
1094 static int
1095 de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev)
1096 {
1097     char name[DE4X5_NAME_LENGTH + 1];
1098     struct de4x5_private *lp = netdev_priv(dev);
1099     struct pci_dev *pdev = NULL;
1100     int i, status=0;
1101 
1102     dev_set_drvdata(gendev, dev);
1103 
1104     /* Ensure we're not sleeping */
1105     if (lp->bus == EISA) {
1106         outb(WAKEUP, PCI_CFPM);
1107     } else {
1108         pdev = to_pci_dev (gendev);
1109         pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
1110     }
1111     mdelay(10);
1112 
1113     RESET_DE4X5;
1114 
1115     if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
1116         return -ENXIO;                       /* Hardware could not reset */
1117     }
1118 
1119     /*
1120     ** Now find out what kind of DC21040/DC21041/DC21140 board we have.
1121     */
1122     lp->useSROM = false;
1123     if (lp->bus == PCI) {
1124         PCI_signature(name, lp);
1125     } else {
1126         EISA_signature(name, gendev);
1127     }
1128 
1129     if (*name == '\0') {                     /* Not found a board signature */
1130         return -ENXIO;
1131     }
1132 
1133     dev->base_addr = iobase;
1134     printk ("%s: %s at 0x%04lx", dev_name(gendev), name, iobase);
1135 
1136     status = get_hw_addr(dev);
1137     printk(", h/w address %pM\n", dev->dev_addr);
1138 
1139     if (status != 0) {
1140         printk("      which has an Ethernet PROM CRC error.\n");
1141         return -ENXIO;
1142     } else {
1143         skb_queue_head_init(&lp->cache.queue);
1144         lp->cache.gepc = GEP_INIT;
1145         lp->asBit = GEP_SLNK;
1146         lp->asPolarity = GEP_SLNK;
1147         lp->asBitValid = ~0;
1148         lp->timeout = -1;
1149         lp->gendev = gendev;
1150         spin_lock_init(&lp->lock);
1151         init_timer(&lp->timer);
1152         lp->timer.function = (void (*)(unsigned long))de4x5_ast;
1153         lp->timer.data = (unsigned long)dev;
1154         de4x5_parse_params(dev);
1155 
1156         /*
1157         ** Choose correct autosensing in case someone messed up
1158         */
1159         lp->autosense = lp->params.autosense;
1160         if (lp->chipset != DC21140) {
1161             if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1162                 lp->params.autosense = TP;
1163             }
1164             if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1165                 lp->params.autosense = BNC;
1166             }
1167         }
1168         lp->fdx = lp->params.fdx;
1169         sprintf(lp->adapter_name,"%s (%s)", name, dev_name(gendev));
1170 
1171         lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc);
1172 #if defined(__alpha__) || defined(__powerpc__) || defined(CONFIG_SPARC) || defined(DE4X5_DO_MEMCPY)
1173         lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + DE4X5_ALIGN;
1174 #endif
1175         lp->rx_ring = dma_alloc_coherent(gendev, lp->dma_size,
1176                                          &lp->dma_rings, GFP_ATOMIC);
1177         if (lp->rx_ring == NULL) {
1178             return -ENOMEM;
1179         }
1180 
1181         lp->tx_ring = lp->rx_ring + NUM_RX_DESC;
1182 
1183         /*
1184         ** Set up the RX descriptor ring (Intels)
1185         ** Allocate contiguous receive buffers, long word aligned (Alphas)
1186         */
1187 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY)
1188         for (i=0; i<NUM_RX_DESC; i++) {
1189             lp->rx_ring[i].status = 0;
1190             lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1191             lp->rx_ring[i].buf = 0;
1192             lp->rx_ring[i].next = 0;
1193             lp->rx_skb[i] = (struct sk_buff *) 1;     /* Dummy entry */
1194         }
1195 
1196 #else
1197         {
1198                 dma_addr_t dma_rx_bufs;
1199 
1200                 dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC)
1201                         * sizeof(struct de4x5_desc);
1202                 dma_rx_bufs = (dma_rx_bufs + DE4X5_ALIGN) & ~DE4X5_ALIGN;
1203                 lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC
1204                         + NUM_TX_DESC) + DE4X5_ALIGN) & ~DE4X5_ALIGN);
1205                 for (i=0; i<NUM_RX_DESC; i++) {
1206                         lp->rx_ring[i].status = 0;
1207                         lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1208                         lp->rx_ring[i].buf =
1209                                 cpu_to_le32(dma_rx_bufs+i*RX_BUFF_SZ);
1210                         lp->rx_ring[i].next = 0;
1211                         lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1212                 }
1213 
1214         }
1215 #endif
1216 
1217         barrier();
1218 
1219         lp->rxRingSize = NUM_RX_DESC;
1220         lp->txRingSize = NUM_TX_DESC;
1221 
1222         /* Write the end of list marker to the descriptor lists */
1223         lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1224         lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1225 
1226         /* Tell the adapter where the TX/RX rings are located. */
1227         outl(lp->dma_rings, DE4X5_RRBA);
1228         outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1229              DE4X5_TRBA);
1230 
1231         /* Initialise the IRQ mask and Enable/Disable */
1232         lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1233         lp->irq_en   = IMR_NIM | IMR_AIM;
1234 
1235         /* Create a loopback packet frame for later media probing */
1236         create_packet(dev, lp->frame, sizeof(lp->frame));
1237 
1238         /* Check if the RX overflow bug needs testing for */
1239         i = lp->cfrv & 0x000000fe;
1240         if ((lp->chipset == DC21140) && (i == 0x20)) {
1241             lp->rx_ovf = 1;
1242         }
1243 
1244         /* Initialise the SROM pointers if possible */
1245         if (lp->useSROM) {
1246             lp->state = INITIALISED;
1247             if (srom_infoleaf_info(dev)) {
1248                 dma_free_coherent (gendev, lp->dma_size,
1249                                lp->rx_ring, lp->dma_rings);
1250                 return -ENXIO;
1251             }
1252             srom_init(dev);
1253         }
1254 
1255         lp->state = CLOSED;
1256 
1257         /*
1258         ** Check for an MII interface
1259         */
1260         if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1261             mii_get_phy(dev);
1262         }
1263 
1264         printk("      and requires IRQ%d (provided by %s).\n", dev->irq,
1265                ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1266     }
1267 
1268     if (de4x5_debug & DEBUG_VERSION) {
1269         printk(version);
1270     }
1271 
1272     /* The DE4X5-specific entries in the device structure. */
1273     SET_NETDEV_DEV(dev, gendev);
1274     dev->netdev_ops = &de4x5_netdev_ops;
1275     dev->mem_start = 0;
1276 
1277     /* Fill in the generic fields of the device structure. */
1278     if ((status = register_netdev (dev))) {
1279             dma_free_coherent (gendev, lp->dma_size,
1280                                lp->rx_ring, lp->dma_rings);
1281             return status;
1282     }
1283 
1284     /* Let the adapter sleep to save power */
1285     yawn(dev, SLEEP);
1286 
1287     return status;
1288 }
1289 
1290 
1291 static int
1292 de4x5_open(struct net_device *dev)
1293 {
1294     struct de4x5_private *lp = netdev_priv(dev);
1295     u_long iobase = dev->base_addr;
1296     int i, status = 0;
1297     s32 omr;
1298 
1299     /* Allocate the RX buffers */
1300     for (i=0; i<lp->rxRingSize; i++) {
1301         if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
1302             de4x5_free_rx_buffs(dev);
1303             return -EAGAIN;
1304         }
1305     }
1306 
1307     /*
1308     ** Wake up the adapter
1309     */
1310     yawn(dev, WAKEUP);
1311 
1312     /*
1313     ** Re-initialize the DE4X5...
1314     */
1315     status = de4x5_init(dev);
1316     spin_lock_init(&lp->lock);
1317     lp->state = OPEN;
1318     de4x5_dbg_open(dev);
1319 
1320     if (request_irq(dev->irq, de4x5_interrupt, IRQF_SHARED,
1321                                                      lp->adapter_name, dev)) {
1322         printk("de4x5_open(): Requested IRQ%d is busy - attempting FAST/SHARE...", dev->irq);
1323         if (request_irq(dev->irq, de4x5_interrupt, IRQF_SHARED,
1324                                                      lp->adapter_name, dev)) {
1325             printk("\n              Cannot get IRQ- reconfigure your hardware.\n");
1326             disable_ast(dev);
1327             de4x5_free_rx_buffs(dev);
1328             de4x5_free_tx_buffs(dev);
1329             yawn(dev, SLEEP);
1330             lp->state = CLOSED;
1331             return -EAGAIN;
1332         } else {
1333             printk("\n              Succeeded, but you should reconfigure your hardware to avoid this.\n");
1334             printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1335         }
1336     }
1337 
1338     lp->interrupt = UNMASK_INTERRUPTS;
1339     netif_trans_update(dev); /* prevent tx timeout */
1340 
1341     START_DE4X5;
1342 
1343     de4x5_setup_intr(dev);
1344 
1345     if (de4x5_debug & DEBUG_OPEN) {
1346         printk("\tsts:  0x%08x\n", inl(DE4X5_STS));
1347         printk("\tbmr:  0x%08x\n", inl(DE4X5_BMR));
1348         printk("\timr:  0x%08x\n", inl(DE4X5_IMR));
1349         printk("\tomr:  0x%08x\n", inl(DE4X5_OMR));
1350         printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
1351         printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
1352         printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
1353         printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
1354     }
1355 
1356     return status;
1357 }
1358 
1359 /*
1360 ** Initialize the DE4X5 operating conditions. NB: a chip problem with the
1361 ** DC21140 requires using perfect filtering mode for that chip. Since I can't
1362 ** see why I'd want > 14 multicast addresses, I have changed all chips to use
1363 ** the perfect filtering mode. Keep the DMA burst length at 8: there seems
1364 ** to be data corruption problems if it is larger (UDP errors seen from a
1365 ** ttcp source).
1366 */
1367 static int
1368 de4x5_init(struct net_device *dev)
1369 {
1370     /* Lock out other processes whilst setting up the hardware */
1371     netif_stop_queue(dev);
1372 
1373     de4x5_sw_reset(dev);
1374 
1375     /* Autoconfigure the connected port */
1376     autoconf_media(dev);
1377 
1378     return 0;
1379 }
1380 
1381 static int
1382 de4x5_sw_reset(struct net_device *dev)
1383 {
1384     struct de4x5_private *lp = netdev_priv(dev);
1385     u_long iobase = dev->base_addr;
1386     int i, j, status = 0;
1387     s32 bmr, omr;
1388 
1389     /* Select the MII or SRL port now and RESET the MAC */
1390     if (!lp->useSROM) {
1391         if (lp->phy[lp->active].id != 0) {
1392             lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1393         } else {
1394             lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1395         }
1396         de4x5_switch_mac_port(dev);
1397     }
1398 
1399     /*
1400     ** Set the programmable burst length to 8 longwords for all the DC21140
1401     ** Fasternet chips and 4 longwords for all others: DMA errors result
1402     ** without these values. Cache align 16 long.
1403     */
1404     bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | DE4X5_CACHE_ALIGN;
1405     bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1406     outl(bmr, DE4X5_BMR);
1407 
1408     omr = inl(DE4X5_OMR) & ~OMR_PR;             /* Turn off promiscuous mode */
1409     if (lp->chipset == DC21140) {
1410         omr |= (OMR_SDP | OMR_SB);
1411     }
1412     lp->setup_f = PERFECT;
1413     outl(lp->dma_rings, DE4X5_RRBA);
1414     outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1415          DE4X5_TRBA);
1416 
1417     lp->rx_new = lp->rx_old = 0;
1418     lp->tx_new = lp->tx_old = 0;
1419 
1420     for (i = 0; i < lp->rxRingSize; i++) {
1421         lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1422     }
1423 
1424     for (i = 0; i < lp->txRingSize; i++) {
1425         lp->tx_ring[i].status = cpu_to_le32(0);
1426     }
1427 
1428     barrier();
1429 
1430     /* Build the setup frame depending on filtering mode */
1431     SetMulticastFilter(dev);
1432 
1433     load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1);
1434     outl(omr|OMR_ST, DE4X5_OMR);
1435 
1436     /* Poll for setup frame completion (adapter interrupts are disabled now) */
1437 
1438     for (j=0, i=0;(i<500) && (j==0);i++) {       /* Up to 500ms delay */
1439         mdelay(1);
1440         if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1441     }
1442     outl(omr, DE4X5_OMR);                        /* Stop everything! */
1443 
1444     if (j == 0) {
1445         printk("%s: Setup frame timed out, status %08x\n", dev->name,
1446                inl(DE4X5_STS));
1447         status = -EIO;
1448     }
1449 
1450     lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1451     lp->tx_old = lp->tx_new;
1452 
1453     return status;
1454 }
1455 
1456 /*
1457 ** Writes a socket buffer address to the next available transmit descriptor.
1458 */
1459 static netdev_tx_t
1460 de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev)
1461 {
1462     struct de4x5_private *lp = netdev_priv(dev);
1463     u_long iobase = dev->base_addr;
1464     u_long flags = 0;
1465 
1466     netif_stop_queue(dev);
1467     if (!lp->tx_enable)                   /* Cannot send for now */
1468                 goto tx_err;
1469 
1470     /*
1471     ** Clean out the TX ring asynchronously to interrupts - sometimes the
1472     ** interrupts are lost by delayed descriptor status updates relative to
1473     ** the irq assertion, especially with a busy PCI bus.
1474     */
1475     spin_lock_irqsave(&lp->lock, flags);
1476     de4x5_tx(dev);
1477     spin_unlock_irqrestore(&lp->lock, flags);
1478 
1479     /* Test if cache is already locked - requeue skb if so */
1480     if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1481                 goto tx_err;
1482 
1483     /* Transmit descriptor ring full or stale skb */
1484     if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) {
1485         if (lp->interrupt) {
1486             de4x5_putb_cache(dev, skb);          /* Requeue the buffer */
1487         } else {
1488             de4x5_put_cache(dev, skb);
1489         }
1490         if (de4x5_debug & DEBUG_TX) {
1491             printk("%s: transmit busy, lost media or stale skb found:\n  STS:%08x\n  tbusy:%d\n  IMR:%08x\n  OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx_new] > 1) ? "YES" : "NO");
1492         }
1493     } else if (skb->len > 0) {
1494         /* If we already have stuff queued locally, use that first */
1495         if (!skb_queue_empty(&lp->cache.queue) && !lp->interrupt) {
1496             de4x5_put_cache(dev, skb);
1497             skb = de4x5_get_cache(dev);
1498         }
1499 
1500         while (skb && !netif_queue_stopped(dev) &&
1501                (u_long) lp->tx_skb[lp->tx_new] <= 1) {
1502             spin_lock_irqsave(&lp->lock, flags);
1503             netif_stop_queue(dev);
1504             load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1505             lp->stats.tx_bytes += skb->len;
1506             outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */
1507 
1508             lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1509 
1510             if (TX_BUFFS_AVAIL) {
1511                 netif_start_queue(dev);         /* Another pkt may be queued */
1512             }
1513             skb = de4x5_get_cache(dev);
1514             spin_unlock_irqrestore(&lp->lock, flags);
1515         }
1516         if (skb) de4x5_putb_cache(dev, skb);
1517     }
1518 
1519     lp->cache.lock = 0;
1520 
1521     return NETDEV_TX_OK;
1522 tx_err:
1523         dev_kfree_skb_any(skb);
1524         return NETDEV_TX_OK;
1525 }
1526 
1527 /*
1528 ** The DE4X5 interrupt handler.
1529 **
1530 ** I/O Read/Writes through intermediate PCI bridges are never 'posted',
1531 ** so that the asserted interrupt always has some real data to work with -
1532 ** if these I/O accesses are ever changed to memory accesses, ensure the
1533 ** STS write is read immediately to complete the transaction if the adapter
1534 ** is not on bus 0. Lost interrupts can still occur when the PCI bus load
1535 ** is high and descriptor status bits cannot be set before the associated
1536 ** interrupt is asserted and this routine entered.
1537 */
1538 static irqreturn_t
1539 de4x5_interrupt(int irq, void *dev_id)
1540 {
1541     struct net_device *dev = dev_id;
1542     struct de4x5_private *lp;
1543     s32 imr, omr, sts, limit;
1544     u_long iobase;
1545     unsigned int handled = 0;
1546 
1547     lp = netdev_priv(dev);
1548     spin_lock(&lp->lock);
1549     iobase = dev->base_addr;
1550 
1551     DISABLE_IRQs;                        /* Ensure non re-entrancy */
1552 
1553     if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1554         printk("%s: Re-entering the interrupt handler.\n", dev->name);
1555 
1556     synchronize_irq(dev->irq);
1557 
1558     for (limit=0; limit<8; limit++) {
1559         sts = inl(DE4X5_STS);            /* Read IRQ status */
1560         outl(sts, DE4X5_STS);            /* Reset the board interrupts */
1561 
1562         if (!(sts & lp->irq_mask)) break;/* All done */
1563         handled = 1;
1564 
1565         if (sts & (STS_RI | STS_RU))     /* Rx interrupt (packet[s] arrived) */
1566           de4x5_rx(dev);
1567 
1568         if (sts & (STS_TI | STS_TU))     /* Tx interrupt (packet sent) */
1569           de4x5_tx(dev);
1570 
1571         if (sts & STS_LNF) {             /* TP Link has failed */
1572             lp->irq_mask &= ~IMR_LFM;
1573         }
1574 
1575         if (sts & STS_UNF) {             /* Transmit underrun */
1576             de4x5_txur(dev);
1577         }
1578 
1579         if (sts & STS_SE) {              /* Bus Error */
1580             STOP_DE4X5;
1581             printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1582                    dev->name, sts);
1583             spin_unlock(&lp->lock);
1584             return IRQ_HANDLED;
1585         }
1586     }
1587 
1588     /* Load the TX ring with any locally stored packets */
1589     if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1590         while (!skb_queue_empty(&lp->cache.queue) && !netif_queue_stopped(dev) && lp->tx_enable) {
1591             de4x5_queue_pkt(de4x5_get_cache(dev), dev);
1592         }
1593         lp->cache.lock = 0;
1594     }
1595 
1596     lp->interrupt = UNMASK_INTERRUPTS;
1597     ENABLE_IRQs;
1598     spin_unlock(&lp->lock);
1599 
1600     return IRQ_RETVAL(handled);
1601 }
1602 
1603 static int
1604 de4x5_rx(struct net_device *dev)
1605 {
1606     struct de4x5_private *lp = netdev_priv(dev);
1607     u_long iobase = dev->base_addr;
1608     int entry;
1609     s32 status;
1610 
1611     for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1612                                                             entry=lp->rx_new) {
1613         status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
1614 
1615         if (lp->rx_ovf) {
1616             if (inl(DE4X5_MFC) & MFC_FOCM) {
1617                 de4x5_rx_ovfc(dev);
1618                 break;
1619             }
1620         }
1621 
1622         if (status & RD_FS) {                 /* Remember the start of frame */
1623             lp->rx_old = entry;
1624         }
1625 
1626         if (status & RD_LS) {                 /* Valid frame status */
1627             if (lp->tx_enable) lp->linkOK++;
1628             if (status & RD_ES) {             /* There was an error. */
1629                 lp->stats.rx_errors++;        /* Update the error stats. */
1630                 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1631                 if (status & RD_CE)           lp->stats.rx_crc_errors++;
1632                 if (status & RD_OF)           lp->stats.rx_fifo_errors++;
1633                 if (status & RD_TL)           lp->stats.rx_length_errors++;
1634                 if (status & RD_RF)           lp->pktStats.rx_runt_frames++;
1635                 if (status & RD_CS)           lp->pktStats.rx_collision++;
1636                 if (status & RD_DB)           lp->pktStats.rx_dribble++;
1637                 if (status & RD_OF)           lp->pktStats.rx_overflow++;
1638             } else {                          /* A valid frame received */
1639                 struct sk_buff *skb;
1640                 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1641                                                                     >> 16) - 4;
1642 
1643                 if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
1644                     printk("%s: Insufficient memory; nuking packet.\n",
1645                                                                     dev->name);
1646                     lp->stats.rx_dropped++;
1647                 } else {
1648                     de4x5_dbg_rx(skb, pkt_len);
1649 
1650                     /* Push up the protocol stack */
1651                     skb->protocol=eth_type_trans(skb,dev);
1652                     de4x5_local_stats(dev, skb->data, pkt_len);
1653                     netif_rx(skb);
1654 
1655                     /* Update stats */
1656                     lp->stats.rx_packets++;
1657                     lp->stats.rx_bytes += pkt_len;
1658                 }
1659             }
1660 
1661             /* Change buffer ownership for this frame, back to the adapter */
1662             for (;lp->rx_old!=entry;lp->rx_old=(lp->rx_old + 1)%lp->rxRingSize) {
1663                 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1664                 barrier();
1665             }
1666             lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1667             barrier();
1668         }
1669 
1670         /*
1671         ** Update entry information
1672         */
1673         lp->rx_new = (lp->rx_new + 1) % lp->rxRingSize;
1674     }
1675 
1676     return 0;
1677 }
1678 
1679 static inline void
1680 de4x5_free_tx_buff(struct de4x5_private *lp, int entry)
1681 {
1682     dma_unmap_single(lp->gendev, le32_to_cpu(lp->tx_ring[entry].buf),
1683                      le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1,
1684                      DMA_TO_DEVICE);
1685     if ((u_long) lp->tx_skb[entry] > 1)
1686         dev_kfree_skb_irq(lp->tx_skb[entry]);
1687     lp->tx_skb[entry] = NULL;
1688 }
1689 
1690 /*
1691 ** Buffer sent - check for TX buffer errors.
1692 */
1693 static int
1694 de4x5_tx(struct net_device *dev)
1695 {
1696     struct de4x5_private *lp = netdev_priv(dev);
1697     u_long iobase = dev->base_addr;
1698     int entry;
1699     s32 status;
1700 
1701     for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1702         status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1703         if (status < 0) {                     /* Buffer not sent yet */
1704             break;
1705         } else if (status != 0x7fffffff) {    /* Not setup frame */
1706             if (status & TD_ES) {             /* An error happened */
1707                 lp->stats.tx_errors++;
1708                 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1709                 if (status & TD_LC) lp->stats.tx_window_errors++;
1710                 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1711                 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1712                 if (status & TD_DE) lp->stats.tx_aborted_errors++;
1713 
1714                 if (TX_PKT_PENDING) {
1715                     outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */
1716                 }
1717             } else {                      /* Packet sent */
1718                 lp->stats.tx_packets++;
1719                 if (lp->tx_enable) lp->linkOK++;
1720             }
1721             /* Update the collision counter */
1722             lp->stats.collisions += ((status & TD_EC) ? 16 :
1723                                                       ((status & TD_CC) >> 3));
1724 
1725             /* Free the buffer. */
1726             if (lp->tx_skb[entry] != NULL)
1727                 de4x5_free_tx_buff(lp, entry);
1728         }
1729 
1730         /* Update all the pointers */
1731         lp->tx_old = (lp->tx_old + 1) % lp->txRingSize;
1732     }
1733 
1734     /* Any resources available? */
1735     if (TX_BUFFS_AVAIL && netif_queue_stopped(dev)) {
1736         if (lp->interrupt)
1737             netif_wake_queue(dev);
1738         else
1739             netif_start_queue(dev);
1740     }
1741 
1742     return 0;
1743 }
1744 
1745 static void
1746 de4x5_ast(struct net_device *dev)
1747 {
1748         struct de4x5_private *lp = netdev_priv(dev);
1749         int next_tick = DE4X5_AUTOSENSE_MS;
1750         int dt;
1751 
1752         if (lp->useSROM)
1753                 next_tick = srom_autoconf(dev);
1754         else if (lp->chipset == DC21140)
1755                 next_tick = dc21140m_autoconf(dev);
1756         else if (lp->chipset == DC21041)
1757                 next_tick = dc21041_autoconf(dev);
1758         else if (lp->chipset == DC21040)
1759                 next_tick = dc21040_autoconf(dev);
1760         lp->linkOK = 0;
1761 
1762         dt = (next_tick * HZ) / 1000;
1763 
1764         if (!dt)
1765                 dt = 1;
1766 
1767         mod_timer(&lp->timer, jiffies + dt);
1768 }
1769 
1770 static int
1771 de4x5_txur(struct net_device *dev)
1772 {
1773     struct de4x5_private *lp = netdev_priv(dev);
1774     u_long iobase = dev->base_addr;
1775     int omr;
1776 
1777     omr = inl(DE4X5_OMR);
1778     if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1779         omr &= ~(OMR_ST|OMR_SR);
1780         outl(omr, DE4X5_OMR);
1781         while (inl(DE4X5_STS) & STS_TS);
1782         if ((omr & OMR_TR) < OMR_TR) {
1783             omr += 0x4000;
1784         } else {
1785             omr |= OMR_SF;
1786         }
1787         outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
1788     }
1789 
1790     return 0;
1791 }
1792 
1793 static int
1794 de4x5_rx_ovfc(struct net_device *dev)
1795 {
1796     struct de4x5_private *lp = netdev_priv(dev);
1797     u_long iobase = dev->base_addr;
1798     int omr;
1799 
1800     omr = inl(DE4X5_OMR);
1801     outl(omr & ~OMR_SR, DE4X5_OMR);
1802     while (inl(DE4X5_STS) & STS_RS);
1803 
1804     for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1805         lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1806         lp->rx_new = (lp->rx_new + 1) % lp->rxRingSize;
1807     }
1808 
1809     outl(omr, DE4X5_OMR);
1810 
1811     return 0;
1812 }
1813 
1814 static int
1815 de4x5_close(struct net_device *dev)
1816 {
1817     struct de4x5_private *lp = netdev_priv(dev);
1818     u_long iobase = dev->base_addr;
1819     s32 imr, omr;
1820 
1821     disable_ast(dev);
1822 
1823     netif_stop_queue(dev);
1824 
1825     if (de4x5_debug & DEBUG_CLOSE) {
1826         printk("%s: Shutting down ethercard, status was %8.8x.\n",
1827                dev->name, inl(DE4X5_STS));
1828     }
1829 
1830     /*
1831     ** We stop the DE4X5 here... mask interrupts and stop TX & RX
1832     */
1833     DISABLE_IRQs;
1834     STOP_DE4X5;
1835 
1836     /* Free the associated irq */
1837     free_irq(dev->irq, dev);
1838     lp->state = CLOSED;
1839 
1840     /* Free any socket buffers */
1841     de4x5_free_rx_buffs(dev);
1842     de4x5_free_tx_buffs(dev);
1843 
1844     /* Put the adapter to sleep to save power */
1845     yawn(dev, SLEEP);
1846 
1847     return 0;
1848 }
1849 
1850 static struct net_device_stats *
1851 de4x5_get_stats(struct net_device *dev)
1852 {
1853     struct de4x5_private *lp = netdev_priv(dev);
1854     u_long iobase = dev->base_addr;
1855 
1856     lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1857 
1858     return &lp->stats;
1859 }
1860 
1861 static void
1862 de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len)
1863 {
1864     struct de4x5_private *lp = netdev_priv(dev);
1865     int i;
1866 
1867     for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1868         if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1869             lp->pktStats.bins[i]++;
1870             i = DE4X5_PKT_STAT_SZ;
1871         }
1872     }
1873     if (is_multicast_ether_addr(buf)) {
1874         if (is_broadcast_ether_addr(buf)) {
1875             lp->pktStats.broadcast++;
1876         } else {
1877             lp->pktStats.multicast++;
1878         }
1879     } else if (ether_addr_equal(buf, dev->dev_addr)) {
1880         lp->pktStats.unicast++;
1881     }
1882 
1883     lp->pktStats.bins[0]++;       /* Duplicates stats.rx_packets */
1884     if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1885         memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1886     }
1887 }
1888 
1889 /*
1890 ** Removes the TD_IC flag from previous descriptor to improve TX performance.
1891 ** If the flag is changed on a descriptor that is being read by the hardware,
1892 ** I assume PCI transaction ordering will mean you are either successful or
1893 ** just miss asserting the change to the hardware. Anyway you're messing with
1894 ** a descriptor you don't own, but this shouldn't kill the chip provided
1895 ** the descriptor register is read only to the hardware.
1896 */
1897 static void
1898 load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb)
1899 {
1900     struct de4x5_private *lp = netdev_priv(dev);
1901     int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1);
1902     dma_addr_t buf_dma = dma_map_single(lp->gendev, buf, flags & TD_TBS1, DMA_TO_DEVICE);
1903 
1904     lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma);
1905     lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1906     lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
1907     lp->tx_skb[lp->tx_new] = skb;
1908     lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC);
1909     barrier();
1910 
1911     lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
1912     barrier();
1913 }
1914 
1915 /*
1916 ** Set or clear the multicast filter for this adaptor.
1917 */
1918 static void
1919 set_multicast_list(struct net_device *dev)
1920 {
1921     struct de4x5_private *lp = netdev_priv(dev);
1922     u_long iobase = dev->base_addr;
1923 
1924     /* First, double check that the adapter is open */
1925     if (lp->state == OPEN) {
1926         if (dev->flags & IFF_PROMISC) {         /* set promiscuous mode */
1927             u32 omr;
1928             omr = inl(DE4X5_OMR);
1929             omr |= OMR_PR;
1930             outl(omr, DE4X5_OMR);
1931         } else {
1932             SetMulticastFilter(dev);
1933             load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1934                                                         SETUP_FRAME_LEN, (struct sk_buff *)1);
1935 
1936             lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1937             outl(POLL_DEMAND, DE4X5_TPD);       /* Start the TX */
1938             netif_trans_update(dev); /* prevent tx timeout */
1939         }
1940     }
1941 }
1942 
1943 /*
1944 ** Calculate the hash code and update the logical address filter
1945 ** from a list of ethernet multicast addresses.
1946 ** Little endian crc one liner from Matt Thomas, DEC.
1947 */
1948 static void
1949 SetMulticastFilter(struct net_device *dev)
1950 {
1951     struct de4x5_private *lp = netdev_priv(dev);
1952     struct netdev_hw_addr *ha;
1953     u_long iobase = dev->base_addr;
1954     int i, bit, byte;
1955     u16 hashcode;
1956     u32 omr, crc;
1957     char *pa;
1958     unsigned char *addrs;
1959 
1960     omr = inl(DE4X5_OMR);
1961     omr &= ~(OMR_PR | OMR_PM);
1962     pa = build_setup_frame(dev, ALL);        /* Build the basic frame */
1963 
1964     if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 14)) {
1965         omr |= OMR_PM;                       /* Pass all multicasts */
1966     } else if (lp->setup_f == HASH_PERF) {   /* Hash Filtering */
1967         netdev_for_each_mc_addr(ha, dev) {
1968                 crc = ether_crc_le(ETH_ALEN, ha->addr);
1969                 hashcode = crc & HASH_BITS;  /* hashcode is 9 LSb of CRC */
1970 
1971                 byte = hashcode >> 3;        /* bit[3-8] -> byte in filter */
1972                 bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */
1973 
1974                 byte <<= 1;                  /* calc offset into setup frame */
1975                 if (byte & 0x02) {
1976                     byte -= 1;
1977                 }
1978                 lp->setup_frame[byte] |= bit;
1979         }
1980     } else {                                 /* Perfect filtering */
1981         netdev_for_each_mc_addr(ha, dev) {
1982             addrs = ha->addr;
1983             for (i=0; i<ETH_ALEN; i++) {
1984                 *(pa + (i&1)) = *addrs++;
1985                 if (i & 0x01) pa += 4;
1986             }
1987         }
1988     }
1989     outl(omr, DE4X5_OMR);
1990 }
1991 
1992 #ifdef CONFIG_EISA
1993 
1994 static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
1995 
1996 static int de4x5_eisa_probe(struct device *gendev)
1997 {
1998         struct eisa_device *edev;
1999         u_long iobase;
2000         u_char irq, regval;
2001         u_short vendor;
2002         u32 cfid;
2003         int status, device;
2004         struct net_device *dev;
2005         struct de4x5_private *lp;
2006 
2007         edev = to_eisa_device (gendev);
2008         iobase = edev->base_addr;
2009 
2010         if (!request_region (iobase, DE4X5_EISA_TOTAL_SIZE, "de4x5"))
2011                 return -EBUSY;
2012 
2013         if (!request_region (iobase + DE4X5_EISA_IO_PORTS,
2014                              DE4X5_EISA_TOTAL_SIZE, "de4x5")) {
2015                 status = -EBUSY;
2016                 goto release_reg_1;
2017         }
2018 
2019         if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2020                 status = -ENOMEM;
2021                 goto release_reg_2;
2022         }
2023         lp = netdev_priv(dev);
2024 
2025         cfid = (u32) inl(PCI_CFID);
2026         lp->cfrv = (u_short) inl(PCI_CFRV);
2027         device = (cfid >> 8) & 0x00ffff00;
2028         vendor = (u_short) cfid;
2029 
2030         /* Read the EISA Configuration Registers */
2031         regval = inb(EISA_REG0) & (ER0_INTL | ER0_INTT);
2032 #ifdef CONFIG_ALPHA
2033         /* Looks like the Jensen firmware (rev 2.2) doesn't really
2034          * care about the EISA configuration, and thus doesn't
2035          * configure the PLX bridge properly. Oh well... Simply mimic
2036          * the EISA config file to sort it out. */
2037 
2038         /* EISA REG1: Assert DecChip 21040 HW Reset */
2039         outb (ER1_IAM | 1, EISA_REG1);
2040         mdelay (1);
2041 
2042         /* EISA REG1: Deassert DecChip 21040 HW Reset */
2043         outb (ER1_IAM, EISA_REG1);
2044         mdelay (1);
2045 
2046         /* EISA REG3: R/W Burst Transfer Enable */
2047         outb (ER3_BWE | ER3_BRE, EISA_REG3);
2048 
2049         /* 32_bit slave/master, Preempt Time=23 bclks, Unlatched Interrupt */
2050         outb (ER0_BSW | ER0_BMW | ER0_EPT | regval, EISA_REG0);
2051 #endif
2052         irq = de4x5_irq[(regval >> 1) & 0x03];
2053 
2054         if (is_DC2114x) {
2055             device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2056         }
2057         lp->chipset = device;
2058         lp->bus = EISA;
2059 
2060         /* Write the PCI Configuration Registers */
2061         outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
2062         outl(0x00006000, PCI_CFLT);
2063         outl(iobase, PCI_CBIO);
2064 
2065         DevicePresent(dev, EISA_APROM);
2066 
2067         dev->irq = irq;
2068 
2069         if (!(status = de4x5_hw_init (dev, iobase, gendev))) {
2070                 return 0;
2071         }
2072 
2073         free_netdev (dev);
2074  release_reg_2:
2075         release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2076  release_reg_1:
2077         release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2078 
2079         return status;
2080 }
2081 
2082 static int de4x5_eisa_remove(struct device *device)
2083 {
2084         struct net_device *dev;
2085         u_long iobase;
2086 
2087         dev = dev_get_drvdata(device);
2088         iobase = dev->base_addr;
2089 
2090         unregister_netdev (dev);
2091         free_netdev (dev);
2092         release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2093         release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2094 
2095         return 0;
2096 }
2097 
2098 static struct eisa_device_id de4x5_eisa_ids[] = {
2099         { "DEC4250", 0 },       /* 0 is the board name index... */
2100         { "" }
2101 };
2102 MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2103 
2104 static struct eisa_driver de4x5_eisa_driver = {
2105         .id_table = de4x5_eisa_ids,
2106         .driver   = {
2107                 .name    = "de4x5",
2108                 .probe   = de4x5_eisa_probe,
2109                 .remove  = de4x5_eisa_remove,
2110         }
2111 };
2112 MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2113 #endif
2114 
2115 #ifdef CONFIG_PCI
2116 
2117 /*
2118 ** This function searches the current bus (which is >0) for a DECchip with an
2119 ** SROM, so that in multiport cards that have one SROM shared between multiple
2120 ** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2121 ** For single port cards this is a time waster...
2122 */
2123 static void
2124 srom_search(struct net_device *dev, struct pci_dev *pdev)
2125 {
2126     u_char pb;
2127     u_short vendor, status;
2128     u_int irq = 0, device;
2129     u_long iobase = 0;                     /* Clear upper 32 bits in Alphas */
2130     int i, j;
2131     struct de4x5_private *lp = netdev_priv(dev);
2132     struct pci_dev *this_dev;
2133 
2134     list_for_each_entry(this_dev, &pdev->bus->devices, bus_list) {
2135         vendor = this_dev->vendor;
2136         device = this_dev->device << 8;
2137         if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2138 
2139         /* Get the chip configuration revision register */
2140         pb = this_dev->bus->number;
2141 
2142         /* Set the device number information */
2143         lp->device = PCI_SLOT(this_dev->devfn);
2144         lp->bus_num = pb;
2145 
2146         /* Set the chipset information */
2147         if (is_DC2114x) {
2148             device = ((this_dev->revision & CFRV_RN) < DC2114x_BRK
2149                       ? DC21142 : DC21143);
2150         }
2151         lp->chipset = device;
2152 
2153         /* Get the board I/O address (64 bits on sparc64) */
2154         iobase = pci_resource_start(this_dev, 0);
2155 
2156         /* Fetch the IRQ to be used */
2157         irq = this_dev->irq;
2158         if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2159 
2160         /* Check if I/O accesses are enabled */
2161         pci_read_config_word(this_dev, PCI_COMMAND, &status);
2162         if (!(status & PCI_COMMAND_IO)) continue;
2163 
2164         /* Search for a valid SROM attached to this DECchip */
2165         DevicePresent(dev, DE4X5_APROM);
2166         for (j=0, i=0; i<ETH_ALEN; i++) {
2167             j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2168         }
2169         if (j != 0 && j != 6 * 0xff) {
2170             last.chipset = device;
2171             last.bus = pb;
2172             last.irq = irq;
2173             for (i=0; i<ETH_ALEN; i++) {
2174                 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2175             }
2176             return;
2177         }
2178     }
2179 }
2180 
2181 /*
2182 ** PCI bus I/O device probe
2183 ** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not
2184 ** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be
2185 ** enabled by the user first in the set up utility. Hence we just check for
2186 ** enabled features and silently ignore the card if they're not.
2187 **
2188 ** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering
2189 ** bit. Here, check for I/O accesses and then set BM. If you put the card in
2190 ** a non BM slot, you're on your own (and complain to the PC vendor that your
2191 ** PC doesn't conform to the PCI standard)!
2192 **
2193 ** This function is only compatible with the *latest* 2.1.x kernels. For 2.0.x
2194 ** kernels use the V0.535[n] drivers.
2195 */
2196 
2197 static int de4x5_pci_probe(struct pci_dev *pdev,
2198                            const struct pci_device_id *ent)
2199 {
2200         u_char pb, pbus = 0, dev_num, dnum = 0, timer;
2201         u_short vendor, status;
2202         u_int irq = 0, device;
2203         u_long iobase = 0;      /* Clear upper 32 bits in Alphas */
2204         int error;
2205         struct net_device *dev;
2206         struct de4x5_private *lp;
2207 
2208         dev_num = PCI_SLOT(pdev->devfn);
2209         pb = pdev->bus->number;
2210 
2211         if (io) { /* probe a single PCI device */
2212                 pbus = (u_short)(io >> 8);
2213                 dnum = (u_short)(io & 0xff);
2214                 if ((pbus != pb) || (dnum != dev_num))
2215                         return -ENODEV;
2216         }
2217 
2218         vendor = pdev->vendor;
2219         device = pdev->device << 8;
2220         if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x))
2221                 return -ENODEV;
2222 
2223         /* Ok, the device seems to be for us. */
2224         if ((error = pci_enable_device (pdev)))
2225                 return error;
2226 
2227         if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2228                 error = -ENOMEM;
2229                 goto disable_dev;
2230         }
2231 
2232         lp = netdev_priv(dev);
2233         lp->bus = PCI;
2234         lp->bus_num = 0;
2235 
2236         /* Search for an SROM on this bus */
2237         if (lp->bus_num != pb) {
2238             lp->bus_num = pb;
2239             srom_search(dev, pdev);
2240         }
2241 
2242         /* Get the chip configuration revision register */
2243         lp->cfrv = pdev->revision;
2244 
2245         /* Set the device number information */
2246         lp->device = dev_num;
2247         lp->bus_num = pb;
2248 
2249         /* Set the chipset information */
2250         if (is_DC2114x) {
2251             device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2252         }
2253         lp->chipset = device;
2254 
2255         /* Get the board I/O address (64 bits on sparc64) */
2256         iobase = pci_resource_start(pdev, 0);
2257 
2258         /* Fetch the IRQ to be used */
2259         irq = pdev->irq;
2260         if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) {
2261                 error = -ENODEV;
2262                 goto free_dev;
2263         }
2264 
2265         /* Check if I/O accesses and Bus Mastering are enabled */
2266         pci_read_config_word(pdev, PCI_COMMAND, &status);
2267 #ifdef __powerpc__
2268         if (!(status & PCI_COMMAND_IO)) {
2269             status |= PCI_COMMAND_IO;
2270             pci_write_config_word(pdev, PCI_COMMAND, status);
2271             pci_read_config_word(pdev, PCI_COMMAND, &status);
2272         }
2273 #endif /* __powerpc__ */
2274         if (!(status & PCI_COMMAND_IO)) {
2275                 error = -ENODEV;
2276                 goto free_dev;
2277         }
2278 
2279         if (!(status & PCI_COMMAND_MASTER)) {
2280             status |= PCI_COMMAND_MASTER;
2281             pci_write_config_word(pdev, PCI_COMMAND, status);
2282             pci_read_config_word(pdev, PCI_COMMAND, &status);
2283         }
2284         if (!(status & PCI_COMMAND_MASTER)) {
2285                 error = -ENODEV;
2286                 goto free_dev;
2287         }
2288 
2289         /* Check the latency timer for values >= 0x60 */
2290         pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &timer);
2291         if (timer < 0x60) {
2292             pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x60);
2293         }
2294 
2295         DevicePresent(dev, DE4X5_APROM);
2296 
2297         if (!request_region (iobase, DE4X5_PCI_TOTAL_SIZE, "de4x5")) {
2298                 error = -EBUSY;
2299                 goto free_dev;
2300         }
2301 
2302         dev->irq = irq;
2303 
2304         if ((error = de4x5_hw_init(dev, iobase, &pdev->dev))) {
2305                 goto release;
2306         }
2307 
2308         return 0;
2309 
2310  release:
2311         release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2312  free_dev:
2313         free_netdev (dev);
2314  disable_dev:
2315         pci_disable_device (pdev);
2316         return error;
2317 }
2318 
2319 static void de4x5_pci_remove(struct pci_dev *pdev)
2320 {
2321         struct net_device *dev;
2322         u_long iobase;
2323 
2324         dev = pci_get_drvdata(pdev);
2325         iobase = dev->base_addr;
2326 
2327         unregister_netdev (dev);
2328         free_netdev (dev);
2329         release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2330         pci_disable_device (pdev);
2331 }
2332 
2333 static const struct pci_device_id de4x5_pci_tbl[] = {
2334         { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP,
2335           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
2336         { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_PLUS,
2337           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
2338         { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
2339           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
2340         { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142,
2341           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
2342         { },
2343 };
2344 
2345 static struct pci_driver de4x5_pci_driver = {
2346         .name           = "de4x5",
2347         .id_table       = de4x5_pci_tbl,
2348         .probe          = de4x5_pci_probe,
2349         .remove         = de4x5_pci_remove,
2350 };
2351 
2352 #endif
2353 
2354 /*
2355 ** Auto configure the media here rather than setting the port at compile
2356 ** time. This routine is called by de4x5_init() and when a loss of media is
2357 ** detected (excessive collisions, loss of carrier, no carrier or link fail
2358 ** [TP] or no recent receive activity) to check whether the user has been
2359 ** sneaky and changed the port on us.
2360 */
2361 static int
2362 autoconf_media(struct net_device *dev)
2363 {
2364         struct de4x5_private *lp = netdev_priv(dev);
2365         u_long iobase = dev->base_addr;
2366 
2367         disable_ast(dev);
2368 
2369         lp->c_media = AUTO;                     /* Bogus last media */
2370         inl(DE4X5_MFC);                         /* Zero the lost frames counter */
2371         lp->media = INIT;
2372         lp->tcount = 0;
2373 
2374         de4x5_ast(dev);
2375 
2376         return lp->media;
2377 }
2378 
2379 /*
2380 ** Autoconfigure the media when using the DC21040. AUI cannot be distinguished
2381 ** from BNC as the port has a jumper to set thick or thin wire. When set for
2382 ** BNC, the BNC port will indicate activity if it's not terminated correctly.
2383 ** The only way to test for that is to place a loopback packet onto the
2384 ** network and watch for errors. Since we're messing with the interrupt mask
2385 ** register, disable the board interrupts and do not allow any more packets to
2386 ** be queued to the hardware. Re-enable everything only when the media is
2387 ** found.
2388 ** I may have to "age out" locally queued packets so that the higher layer
2389 ** timeouts don't effectively duplicate packets on the network.
2390 */
2391 static int
2392 dc21040_autoconf(struct net_device *dev)
2393 {
2394     struct de4x5_private *lp = netdev_priv(dev);
2395     u_long iobase = dev->base_addr;
2396     int next_tick = DE4X5_AUTOSENSE_MS;
2397     s32 imr;
2398 
2399     switch (lp->media) {
2400     case INIT:
2401         DISABLE_IRQs;
2402         lp->tx_enable = false;
2403         lp->timeout = -1;
2404         de4x5_save_skbs(dev);
2405         if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2406             lp->media = TP;
2407         } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2408             lp->media = BNC_AUI;
2409         } else if (lp->autosense == EXT_SIA) {
2410             lp->media = EXT_SIA;
2411         } else {
2412             lp->media = NC;
2413         }
2414         lp->local_state = 0;
2415         next_tick = dc21040_autoconf(dev);
2416         break;
2417 
2418     case TP:
2419         next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
2420                                                          TP_SUSPECT, test_tp);
2421         break;
2422 
2423     case TP_SUSPECT:
2424         next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
2425         break;
2426 
2427     case BNC:
2428     case AUI:
2429     case BNC_AUI:
2430         next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
2431                                                   BNC_AUI_SUSPECT, ping_media);
2432         break;
2433 
2434     case BNC_AUI_SUSPECT:
2435         next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
2436         break;
2437 
2438     case EXT_SIA:
2439         next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
2440                                               NC, EXT_SIA_SUSPECT, ping_media);
2441         break;
2442 
2443     case EXT_SIA_SUSPECT:
2444         next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
2445         break;
2446 
2447     case NC:
2448         /* default to TP for all */
2449         reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
2450         if (lp->media != lp->c_media) {
2451             de4x5_dbg_media(dev);
2452             lp->c_media = lp->media;
2453         }
2454         lp->media = INIT;
2455         lp->tx_enable = false;
2456         break;
2457     }
2458 
2459     return next_tick;
2460 }
2461 
2462 static int
2463 dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout,
2464               int next_state, int suspect_state,
2465               int (*fn)(struct net_device *, int))
2466 {
2467     struct de4x5_private *lp = netdev_priv(dev);
2468     int next_tick = DE4X5_AUTOSENSE_MS;
2469     int linkBad;
2470 
2471     switch (lp->local_state) {
2472     case 0:
2473         reset_init_sia(dev, csr13, csr14, csr15);
2474         lp->local_state++;
2475         next_tick = 500;
2476         break;
2477 
2478     case 1:
2479         if (!lp->tx_enable) {
2480             linkBad = fn(dev, timeout);
2481             if (linkBad < 0) {
2482                 next_tick = linkBad & ~TIMER_CB;
2483             } else {
2484                 if (linkBad && (lp->autosense == AUTO)) {
2485                     lp->local_state = 0;
2486                     lp->media = next_state;
2487                 } else {
2488                     de4x5_init_connection(dev);
2489                 }
2490             }
2491         } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2492             lp->media = suspect_state;
2493             next_tick = 3000;
2494         }
2495         break;
2496     }
2497 
2498     return next_tick;
2499 }
2500 
2501 static int
2502 de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state,
2503                       int (*fn)(struct net_device *, int),
2504                       int (*asfn)(struct net_device *))
2505 {
2506     struct de4x5_private *lp = netdev_priv(dev);
2507     int next_tick = DE4X5_AUTOSENSE_MS;
2508     int linkBad;
2509 
2510     switch (lp->local_state) {
2511     case 1:
2512         if (lp->linkOK) {
2513             lp->media = prev_state;
2514         } else {
2515             lp->local_state++;
2516             next_tick = asfn(dev);
2517         }
2518         break;
2519 
2520     case 2:
2521         linkBad = fn(dev, timeout);
2522         if (linkBad < 0) {
2523             next_tick = linkBad & ~TIMER_CB;
2524         } else if (!linkBad) {
2525             lp->local_state--;
2526             lp->media = prev_state;
2527         } else {
2528             lp->media = INIT;
2529             lp->tcount++;
2530         }
2531     }
2532 
2533     return next_tick;
2534 }
2535 
2536 /*
2537 ** Autoconfigure the media when using the DC21041. AUI needs to be tested
2538 ** before BNC, because the BNC port will indicate activity if it's not
2539 ** terminated correctly. The only way to test for that is to place a loopback
2540 ** packet onto the network and watch for errors. Since we're messing with
2541 ** the interrupt mask register, disable the board interrupts and do not allow
2542 ** any more packets to be queued to the hardware. Re-enable everything only
2543 ** when the media is found.
2544 */
2545 static int
2546 dc21041_autoconf(struct net_device *dev)
2547 {
2548     struct de4x5_private *lp = netdev_priv(dev);
2549     u_long iobase = dev->base_addr;
2550     s32 sts, irqs, irq_mask, imr, omr;
2551     int next_tick = DE4X5_AUTOSENSE_MS;
2552 
2553     switch (lp->media) {
2554     case INIT:
2555         DISABLE_IRQs;
2556         lp->tx_enable = false;
2557         lp->timeout = -1;
2558         de4x5_save_skbs(dev);          /* Save non transmitted skb's */
2559         if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2560             lp->media = TP;            /* On chip auto negotiation is broken */
2561         } else if (lp->autosense == TP) {
2562             lp->media = TP;
2563         } else if (lp->autosense == BNC) {
2564             lp->media = BNC;
2565         } else if (lp->autosense == AUI) {
2566             lp->media = AUI;
2567         } else {
2568             lp->media = NC;
2569         }
2570         lp->local_state = 0;
2571         next_tick = dc21041_autoconf(dev);
2572         break;
2573 
2574     case TP_NW:
2575         if (lp->timeout < 0) {
2576             omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */
2577             outl(omr | OMR_FDX, DE4X5_OMR);
2578         }
2579         irqs = STS_LNF | STS_LNP;
2580         irq_mask = IMR_LFM | IMR_LPM;
2581         sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
2582         if (sts < 0) {
2583             next_tick = sts & ~TIMER_CB;
2584         } else {
2585             if (sts & STS_LNP) {
2586                 lp->media = ANS;
2587             } else {
2588                 lp->media = AUI;
2589             }
2590             next_tick = dc21041_autoconf(dev);
2591         }
2592         break;
2593 
2594     case ANS:
2595         if (!lp->tx_enable) {
2596             irqs = STS_LNP;
2597             irq_mask = IMR_LPM;
2598             sts = test_ans(dev, irqs, irq_mask, 3000);
2599             if (sts < 0) {
2600                 next_tick = sts & ~TIMER_CB;
2601             } else {
2602                 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2603                     lp->media = TP;
2604                     next_tick = dc21041_autoconf(dev);
2605                 } else {
2606                     lp->local_state = 1;
2607                     de4x5_init_connection(dev);
2608                 }
2609             }
2610         } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2611             lp->media = ANS_SUSPECT;
2612             next_tick = 3000;
2613         }
2614         break;
2615 
2616     case ANS_SUSPECT:
2617         next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
2618         break;
2619 
2620     case TP:
2621         if (!lp->tx_enable) {
2622             if (lp->timeout < 0) {
2623                 omr = inl(DE4X5_OMR);          /* Set up half duplex for TP */
2624                 outl(omr & ~OMR_FDX, DE4X5_OMR);
2625             }
2626             irqs = STS_LNF | STS_LNP;
2627             irq_mask = IMR_LFM | IMR_LPM;
2628             sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
2629             if (sts < 0) {
2630                 next_tick = sts & ~TIMER_CB;
2631             } else {
2632                 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2633                     if (inl(DE4X5_SISR) & SISR_NRA) {
2634                         lp->media = AUI;       /* Non selected port activity */
2635                     } else {
2636                         lp->media = BNC;
2637                     }
2638                     next_tick = dc21041_autoconf(dev);
2639                 } else {
2640                     lp->local_state = 1;
2641                     de4x5_init_connection(dev);
2642                 }
2643             }
2644         } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2645             lp->media = TP_SUSPECT;
2646             next_tick = 3000;
2647         }
2648         break;
2649 
2650     case TP_SUSPECT:
2651         next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
2652         break;
2653 
2654     case AUI:
2655         if (!lp->tx_enable) {
2656             if (lp->timeout < 0) {
2657                 omr = inl(DE4X5_OMR);          /* Set up half duplex for AUI */
2658                 outl(omr & ~OMR_FDX, DE4X5_OMR);
2659             }
2660             irqs = 0;
2661             irq_mask = 0;
2662             sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000);
2663             if (sts < 0) {
2664                 next_tick = sts & ~TIMER_CB;
2665             } else {
2666                 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2667                     lp->media = BNC;
2668                     next_tick = dc21041_autoconf(dev);
2669                 } else {
2670                     lp->local_state = 1;
2671                     de4x5_init_connection(dev);
2672                 }
2673             }
2674         } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2675             lp->media = AUI_SUSPECT;
2676             next_tick = 3000;
2677         }
2678         break;
2679 
2680     case AUI_SUSPECT:
2681         next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
2682         break;
2683 
2684     case BNC:
2685         switch (lp->local_state) {
2686         case 0:
2687             if (lp->timeout < 0) {
2688                 omr = inl(DE4X5_OMR);          /* Set up half duplex for BNC */
2689                 outl(omr & ~OMR_FDX, DE4X5_OMR);
2690             }
2691             irqs = 0;
2692             irq_mask = 0;
2693             sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000);
2694             if (sts < 0) {
2695                 next_tick = sts & ~TIMER_CB;
2696             } else {
2697                 lp->local_state++;             /* Ensure media connected */
2698                 next_tick = dc21041_autoconf(dev);
2699             }
2700             break;
2701 
2702         case 1:
2703             if (!lp->tx_enable) {
2704                 if ((sts = ping_media(dev, 3000)) < 0) {
2705                     next_tick = sts & ~TIMER_CB;
2706                 } else {
2707                     if (sts) {
2708                         lp->local_state = 0;
2709                         lp->media = NC;
2710                     } else {
2711                         de4x5_init_connection(dev);
2712                     }
2713                 }
2714             } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2715                 lp->media = BNC_SUSPECT;
2716                 next_tick = 3000;
2717             }
2718             break;
2719         }
2720         break;
2721 
2722     case BNC_SUSPECT:
2723         next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
2724         break;
2725 
2726     case NC:
2727         omr = inl(DE4X5_OMR);    /* Set up full duplex for the autonegotiate */
2728         outl(omr | OMR_FDX, DE4X5_OMR);
2729         reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
2730         if (lp->media != lp->c_media) {
2731             de4x5_dbg_media(dev);
2732             lp->c_media = lp->media;
2733         }
2734         lp->media = INIT;
2735         lp->tx_enable = false;
2736         break;
2737     }
2738 
2739     return next_tick;
2740 }
2741 
2742 /*
2743 ** Some autonegotiation chips are broken in that they do not return the
2744 ** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement
2745 ** register, except at the first power up negotiation.
2746 */
2747 static int
2748 dc21140m_autoconf(struct net_device *dev)
2749 {
2750     struct de4x5_private *lp = netdev_priv(dev);
2751     int ana, anlpa, cap, cr, slnk, sr;
2752     int next_tick = DE4X5_AUTOSENSE_MS;
2753     u_long imr, omr, iobase = dev->base_addr;
2754 
2755     switch(lp->media) {
2756     case INIT:
2757         if (lp->timeout < 0) {
2758             DISABLE_IRQs;
2759             lp->tx_enable = false;
2760             lp->linkOK = 0;
2761             de4x5_save_skbs(dev);          /* Save non transmitted skb's */
2762         }
2763         if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2764             next_tick &= ~TIMER_CB;
2765         } else {
2766             if (lp->useSROM) {
2767                 if (srom_map_media(dev) < 0) {
2768                     lp->tcount++;
2769                     return next_tick;
2770                 }
2771                 srom_exec(dev, lp->phy[lp->active].gep);
2772                 if (lp->infoblock_media == ANS) {
2773                     ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2774                     mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2775                 }
2776             } else {
2777                 lp->tmp = MII_SR_ASSC;     /* Fake out the MII speed set */
2778                 SET_10Mb;
2779                 if (lp->autosense == _100Mb) {
2780                     lp->media = _100Mb;
2781                 } else if (lp->autosense == _10Mb) {
2782                     lp->media = _10Mb;
2783                 } else if ((lp->autosense == AUTO) &&
2784                                     ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2785                     ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2786                     ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2787                     mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2788                     lp->media = ANS;
2789                 } else if (lp->autosense == AUTO) {
2790                     lp->media = SPD_DET;
2791                 } else if (is_spd_100(dev) && is_100_up(dev)) {
2792                     lp->media = _100Mb;
2793                 } else {
2794                     lp->media = NC;
2795                 }
2796             }
2797             lp->local_state = 0;
2798             next_tick = dc21140m_autoconf(dev);
2799         }
2800         break;
2801 
2802     case ANS:
2803         switch (lp->local_state) {
2804         case 0:
2805             if (lp->timeout < 0) {
2806                 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2807             }
2808             cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, false, 500);
2809             if (cr < 0) {
2810                 next_tick = cr & ~TIMER_CB;
2811             } else {
2812                 if (cr) {
2813                     lp->local_state = 0;
2814                     lp->media = SPD_DET;
2815                 } else {
2816                     lp->local_state++;
2817                 }
2818                 next_tick = dc21140m_autoconf(dev);
2819             }
2820             break;
2821 
2822         case 1:
2823             if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, true, 2000)) < 0) {
2824                 next_tick = sr & ~TIMER_CB;
2825             } else {
2826                 lp->media = SPD_DET;
2827                 lp->local_state = 0;
2828                 if (sr) {                         /* Success! */
2829                     lp->tmp = MII_SR_ASSC;
2830                     anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2831                     ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2832                     if (!(anlpa & MII_ANLPA_RF) &&
2833                          (cap = anlpa & MII_ANLPA_TAF & ana)) {
2834                         if (cap & MII_ANA_100M) {
2835                             lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
2836                             lp->media = _100Mb;
2837                         } else if (cap & MII_ANA_10M) {
2838                             lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
2839 
2840                             lp->media = _10Mb;
2841                         }
2842                     }
2843                 }                       /* Auto Negotiation failed to finish */
2844                 next_tick = dc21140m_autoconf(dev);
2845             }                           /* Auto Negotiation failed to start */
2846             break;
2847         }
2848         break;
2849 
2850     case SPD_DET:                              /* Choose 10Mb/s or 100Mb/s */
2851         if (lp->timeout < 0) {
2852             lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2853                                                   (~gep_rd(dev) & GEP_LNP));
2854             SET_100Mb_PDET;
2855         }
2856         if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
2857             next_tick = slnk & ~TIMER_CB;
2858         } else {
2859             if (is_spd_100(dev) && is_100_up(dev)) {
2860                 lp->media = _100Mb;
2861             } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2862                 lp->media = _10Mb;
2863             } else {
2864                 lp->media = NC;
2865             }
2866             next_tick = dc21140m_autoconf(dev);
2867         }
2868         break;
2869 
2870     case _100Mb:                               /* Set 100Mb/s */
2871         next_tick = 3000;
2872         if (!lp->tx_enable) {
2873             SET_100Mb;
2874             de4x5_init_connection(dev);
2875         } else {
2876             if (!lp->linkOK && (lp->autosense == AUTO)) {
2877                 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2878                     lp->media = INIT;
2879                     lp->tcount++;
2880                     next_tick = DE4X5_AUTOSENSE_MS;
2881                 }
2882             }
2883         }
2884         break;
2885 
2886     case BNC:
2887     case AUI:
2888     case _10Mb:                                /* Set 10Mb/s */
2889         next_tick = 3000;
2890         if (!lp->tx_enable) {
2891             SET_10Mb;
2892             de4x5_init_connection(dev);
2893         } else {
2894             if (!lp->linkOK && (lp->autosense == AUTO)) {
2895                 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2896                     lp->media = INIT;
2897                     lp->tcount++;
2898                     next_tick = DE4X5_AUTOSENSE_MS;
2899                 }
2900             }
2901         }
2902         break;
2903 
2904     case NC:
2905         if (lp->media != lp->c_media) {
2906             de4x5_dbg_media(dev);
2907             lp->c_media = lp->media;
2908         }
2909         lp->media = INIT;
2910         lp->tx_enable = false;
2911         break;
2912     }
2913 
2914     return next_tick;
2915 }
2916 
2917 /*
2918 ** This routine may be merged into dc21140m_autoconf() sometime as I'm
2919 ** changing how I figure out the media - but trying to keep it backwards
2920 ** compatible with the de500-xa and de500-aa.
2921 ** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock
2922 ** functions and set during de4x5_mac_port() and/or de4x5_reset_phy().
2923 ** This routine just has to figure out whether 10Mb/s or 100Mb/s is
2924 ** active.
2925 ** When autonegotiation is working, the ANS part searches the SROM for
2926 ** the highest common speed (TP) link that both can run and if that can
2927 ** be full duplex. That infoblock is executed and then the link speed set.
2928 **
2929 ** Only _10Mb and _100Mb are tested here.
2930 */
2931 static int
2932 dc2114x_autoconf(struct net_device *dev)
2933 {
2934     struct de4x5_private *lp = netdev_priv(dev);
2935     u_long iobase = dev->base_addr;
2936     s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts;
2937     int next_tick = DE4X5_AUTOSENSE_MS;
2938 
2939     switch (lp->media) {
2940     case INIT:
2941         if (lp->timeout < 0) {
2942             DISABLE_IRQs;
2943             lp->tx_enable = false;
2944             lp->linkOK = 0;
2945             lp->timeout = -1;
2946             de4x5_save_skbs(dev);            /* Save non transmitted skb's */
2947             if (lp->params.autosense & ~AUTO) {
2948                 srom_map_media(dev);         /* Fixed media requested      */
2949                 if (lp->media != lp->params.autosense) {
2950                     lp->tcount++;
2951                     lp->media = INIT;
2952                     return next_tick;
2953                 }
2954                 lp->media = INIT;
2955             }
2956         }
2957         if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2958             next_tick &= ~TIMER_CB;
2959         } else {
2960             if (lp->autosense == _100Mb) {
2961                 lp->media = _100Mb;
2962             } else if (lp->autosense == _10Mb) {
2963                 lp->media = _10Mb;
2964             } else if (lp->autosense == TP) {
2965                 lp->media = TP;
2966             } else if (lp->autosense == BNC) {
2967                 lp->media = BNC;
2968             } else if (lp->autosense == AUI) {
2969                 lp->media = AUI;
2970             } else {
2971                 lp->media = SPD_DET;
2972                 if ((lp->infoblock_media == ANS) &&
2973                                     ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2974                     ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2975                     ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2976                     mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2977                     lp->media = ANS;
2978                 }
2979             }
2980             lp->local_state = 0;
2981             next_tick = dc2114x_autoconf(dev);
2982         }
2983         break;
2984 
2985     case ANS:
2986         switch (lp->local_state) {
2987         case 0:
2988             if (lp->timeout < 0) {
2989                 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2990             }
2991             cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, false, 500);
2992             if (cr < 0) {
2993                 next_tick = cr & ~TIMER_CB;
2994             } else {
2995                 if (cr) {
2996                     lp->local_state = 0;
2997                     lp->media = SPD_DET;
2998                 } else {
2999                     lp->local_state++;
3000                 }
3001                 next_tick = dc2114x_autoconf(dev);
3002             }
3003             break;
3004 
3005         case 1:
3006             sr = test_mii_reg(dev, MII_SR, MII_SR_ASSC, true, 2000);
3007             if (sr < 0) {
3008                 next_tick = sr & ~TIMER_CB;
3009             } else {
3010                 lp->media = SPD_DET;
3011                 lp->local_state = 0;
3012                 if (sr) {                         /* Success! */
3013                     lp->tmp = MII_SR_ASSC;
3014                     anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3015                     ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3016                     if (!(anlpa & MII_ANLPA_RF) &&
3017                          (cap = anlpa & MII_ANLPA_TAF & ana)) {
3018                         if (cap & MII_ANA_100M) {
3019                             lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
3020                             lp->media = _100Mb;
3021                         } else if (cap & MII_ANA_10M) {
3022                             lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
3023                             lp->media = _10Mb;
3024                         }
3025                     }
3026                 }                       /* Auto Negotiation failed to finish */
3027                 next_tick = dc2114x_autoconf(dev);
3028             }                           /* Auto Negotiation failed to start  */
3029             break;
3030         }
3031         break;
3032 
3033     case AUI:
3034         if (!lp->tx_enable) {
3035             if (lp->timeout < 0) {
3036                 omr = inl(DE4X5_OMR);   /* Set up half duplex for AUI        */
3037                 outl(omr & ~OMR_FDX, DE4X5_OMR);
3038             }
3039             irqs = 0;
3040             irq_mask = 0;
3041             sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3042             if (sts < 0) {
3043                 next_tick = sts & ~TIMER_CB;
3044             } else {
3045                 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3046                     lp->media = BNC;
3047                     next_tick = dc2114x_autoconf(dev);
3048                 } else {
3049                     lp->local_state = 1;
3050                     de4x5_init_connection(dev);
3051                 }
3052             }
3053         } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3054             lp->media = AUI_SUSPECT;
3055             next_tick = 3000;
3056         }
3057         break;
3058 
3059     case AUI_SUSPECT:
3060         next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf);
3061         break;
3062 
3063     case BNC:
3064         switch (lp->local_state) {
3065         case 0:
3066             if (lp->timeout < 0) {
3067                 omr = inl(DE4X5_OMR);          /* Set up half duplex for BNC */
3068                 outl(omr & ~OMR_FDX, DE4X5_OMR);
3069             }
3070             irqs = 0;
3071             irq_mask = 0;
3072             sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3073             if (sts < 0) {
3074                 next_tick = sts & ~TIMER_CB;
3075             } else {
3076                 lp->local_state++;             /* Ensure media connected */
3077                 next_tick = dc2114x_autoconf(dev);
3078             }
3079             break;
3080 
3081         case 1:
3082             if (!lp->tx_enable) {
3083                 if ((sts = ping_media(dev, 3000)) < 0) {
3084                     next_tick = sts & ~TIMER_CB;
3085                 } else {
3086                     if (sts) {
3087                         lp->local_state = 0;
3088                         lp->tcount++;
3089                         lp->media = INIT;
3090                     } else {
3091                         de4x5_init_connection(dev);
3092                     }
3093                 }
3094             } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3095                 lp->media = BNC_SUSPECT;
3096                 next_tick = 3000;
3097             }
3098             break;
3099         }
3100         break;
3101 
3102     case BNC_SUSPECT:
3103         next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf);
3104         break;
3105 
3106     case SPD_DET:                              /* Choose 10Mb/s or 100Mb/s */
3107           if (srom_map_media(dev) < 0) {
3108               lp->tcount++;
3109               lp->media = INIT;
3110               return next_tick;
3111           }
3112           if (lp->media == _100Mb) {
3113               if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3114                   lp->media = SPD_DET;
3115                   return slnk & ~TIMER_CB;
3116               }
3117           } else {
3118               if (wait_for_link(dev) < 0) {
3119                   lp->media = SPD_DET;
3120                   return PDET_LINK_WAIT;
3121               }
3122           }
3123           if (lp->media == ANS) {           /* Do MII parallel detection */
3124               if (is_spd_100(dev)) {
3125                   lp->media = _100Mb;
3126               } else {
3127                   lp->media = _10Mb;
3128               }
3129               next_tick = dc2114x_autoconf(dev);
3130           } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3131                      (((lp->media == _10Mb) || (lp->media == TP) ||
3132                        (lp->media == BNC)   || (lp->media == AUI)) &&
3133                       is_10_up(dev))) {
3134               next_tick = dc2114x_autoconf(dev);
3135           } else {
3136               lp->tcount++;
3137               lp->media = INIT;
3138           }
3139           break;
3140 
3141     case _10Mb:
3142         next_tick = 3000;
3143         if (!lp->tx_enable) {
3144             SET_10Mb;
3145             de4x5_init_connection(dev);
3146         } else {
3147             if (!lp->linkOK && (lp->autosense == AUTO)) {
3148                 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3149                     lp->media = INIT;
3150                     lp->tcount++;
3151                     next_tick = DE4X5_AUTOSENSE_MS;
3152                 }
3153             }
3154         }
3155         break;
3156 
3157     case _100Mb:
3158         next_tick = 3000;
3159         if (!lp->tx_enable) {
3160             SET_100Mb;
3161             de4x5_init_connection(dev);
3162         } else {
3163             if (!lp->linkOK && (lp->autosense == AUTO)) {
3164                 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3165                     lp->media = INIT;
3166                     lp->tcount++;
3167                     next_tick = DE4X5_AUTOSENSE_MS;
3168                 }
3169             }
3170         }
3171         break;
3172 
3173     default:
3174         lp->tcount++;
3175 printk("Huh?: media:%02x\n", lp->media);
3176         lp->media = INIT;
3177         break;
3178     }
3179 
3180     return next_tick;
3181 }
3182 
3183 static int
3184 srom_autoconf(struct net_device *dev)
3185 {
3186     struct de4x5_private *lp = netdev_priv(dev);
3187 
3188     return lp->infoleaf_fn(dev);
3189 }
3190 
3191 /*
3192 ** This mapping keeps the original media codes and FDX flag unchanged.
3193 ** While it isn't strictly necessary, it helps me for the moment...
3194 ** The early return avoids a media state / SROM media space clash.
3195 */
3196 static int
3197 srom_map_media(struct net_device *dev)
3198 {
3199     struct de4x5_private *lp = netdev_priv(dev);
3200 
3201     lp->fdx = false;
3202     if (lp->infoblock_media == lp->media)
3203       return 0;
3204 
3205     switch(lp->infoblock_media) {
3206       case SROM_10BASETF:
3207         if (!lp->params.fdx) return -1;
3208         lp->fdx = true;
3209       case SROM_10BASET:
3210         if (lp->params.fdx && !lp->fdx) return -1;
3211         if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3212             lp->media = _10Mb;
3213         } else {
3214             lp->media = TP;
3215         }
3216         break;
3217 
3218       case SROM_10BASE2:
3219         lp->media = BNC;
3220         break;
3221 
3222       case SROM_10BASE5:
3223         lp->media = AUI;
3224         break;
3225 
3226       case SROM_100BASETF:
3227         if (!lp->params.fdx) return -1;
3228         lp->fdx = true;
3229       case SROM_100BASET:
3230         if (lp->params.fdx && !lp->fdx) return -1;
3231         lp->media = _100Mb;
3232         break;
3233 
3234       case SROM_100BASET4:
3235         lp->media = _100Mb;
3236         break;
3237 
3238       case SROM_100BASEFF:
3239         if (!lp->params.fdx) return -1;
3240         lp->fdx = true;
3241       case SROM_100BASEF:
3242         if (lp->params.fdx && !lp->fdx) return -1;
3243         lp->media = _100Mb;
3244         break;
3245 
3246       case ANS:
3247         lp->media = ANS;
3248         lp->fdx = lp->params.fdx;
3249         break;
3250 
3251       default:
3252         printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
3253                                                           lp->infoblock_media);
3254         return -1;
3255     }
3256 
3257     return 0;
3258 }
3259 
3260 static void
3261 de4x5_init_connection(struct net_device *dev)
3262 {
3263     struct de4x5_private *lp = netdev_priv(dev);
3264     u_long iobase = dev->base_addr;
3265     u_long flags = 0;
3266 
3267     if (lp->media != lp->c_media) {
3268         de4x5_dbg_media(dev);
3269         lp->c_media = lp->media;          /* Stop scrolling media messages */
3270     }
3271 
3272     spin_lock_irqsave(&lp->lock, flags);
3273     de4x5_rst_desc_ring(dev);
3274     de4x5_setup_intr(dev);
3275     lp->tx_enable = true;
3276     spin_unlock_irqrestore(&lp->lock, flags);
3277     outl(POLL_DEMAND, DE4X5_TPD);
3278 
3279     netif_wake_queue(dev);
3280 }
3281 
3282 /*
3283 ** General PHY reset function. Some MII devices don't reset correctly
3284 ** since their MII address pins can float at voltages that are dependent
3285 ** on the signal pin use. Do a double reset to ensure a reset.
3286 */
3287 static int
3288 de4x5_reset_phy(struct net_device *dev)
3289 {
3290     struct de4x5_private *lp = netdev_priv(dev);
3291     u_long iobase = dev->base_addr;
3292     int next_tick = 0;
3293 
3294     if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3295         if (lp->timeout < 0) {
3296             if (lp->useSROM) {
3297                 if (lp->phy[lp->active].rst) {
3298                     srom_exec(dev, lp->phy[lp->active].rst);
3299                     srom_exec(dev, lp->phy[lp->active].rst);
3300                 } else if (lp->rst) {          /* Type 5 infoblock reset */
3301                     srom_exec(dev, lp->rst);
3302                     srom_exec(dev, lp->rst);
3303                 }
3304             } else {
3305                 PHY_HARD_RESET;
3306             }
3307             if (lp->useMII) {
3308                 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3309             }
3310         }
3311         if (lp->useMII) {
3312             next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, false, 500);
3313         }
3314     } else if (lp->chipset == DC21140) {
3315         PHY_HARD_RESET;
3316     }
3317 
3318     return next_tick;
3319 }
3320 
3321 static int
3322 test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
3323 {
3324     struct de4x5_private *lp = netdev_priv(dev);
3325     u_long iobase = dev->base_addr;
3326     s32 sts, csr12;
3327 
3328     if (lp->timeout < 0) {
3329         lp->timeout = msec/100;
3330         if (!lp->useSROM) {      /* Already done if by SROM, else dc2104[01] */
3331             reset_init_sia(dev, csr13, csr14, csr15);
3332         }
3333 
3334         /* set up the interrupt mask */
3335         outl(irq_mask, DE4X5_IMR);
3336 
3337         /* clear all pending interrupts */
3338         sts = inl(DE4X5_STS);
3339         outl(sts, DE4X5_STS);
3340 
3341         /* clear csr12 NRA and SRA bits */
3342         if ((lp->chipset == DC21041) || lp->useSROM) {
3343             csr12 = inl(DE4X5_SISR);
3344             outl(csr12, DE4X5_SISR);
3345         }
3346     }
3347 
3348     sts = inl(DE4X5_STS) & ~TIMER_CB;
3349 
3350     if (!(sts & irqs) && --lp->timeout) {
3351         sts = 100 | TIMER_CB;
3352     } else {
3353         lp->timeout = -1;
3354     }
3355 
3356     return sts;
3357 }
3358 
3359 static int
3360 test_tp(struct net_device *dev, s32 msec)
3361 {
3362     struct de4x5_private *lp = netdev_priv(dev);
3363     u_long iobase = dev->base_addr;
3364     int sisr;
3365 
3366     if (lp->timeout < 0) {
3367         lp->timeout = msec/100;
3368     }
3369 
3370     sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
3371 
3372     if (sisr && --lp->timeout) {
3373         sisr = 100 | TIMER_CB;
3374     } else {
3375         lp->timeout = -1;
3376     }
3377 
3378     return sisr;
3379 }
3380 
3381 /*
3382 ** Samples the 100Mb Link State Signal. The sample interval is important
3383 ** because too fast a rate can give erroneous results and confuse the
3384 ** speed sense algorithm.
3385 */
3386 #define SAMPLE_INTERVAL 500  /* ms */
3387 #define SAMPLE_DELAY    2000 /* ms */
3388 static int
3389 test_for_100Mb(struct net_device *dev, int msec)
3390 {
3391     struct de4x5_private *lp = netdev_priv(dev);
3392     int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3393 
3394     if (lp->timeout < 0) {
3395         if ((msec/SAMPLE_INTERVAL) <= 0) return 0;
3396         if (msec > SAMPLE_DELAY) {
3397             lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3398             gep = SAMPLE_DELAY | TIMER_CB;
3399             return gep;
3400         } else {
3401             lp->timeout = msec/SAMPLE_INTERVAL;
3402         }
3403     }
3404 
3405     if (lp->phy[lp->active].id || lp->useSROM) {
3406         gep = is_100_up(dev) | is_spd_100(dev);
3407     } else {
3408         gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP));
3409     }
3410     if (!(gep & ret) && --lp->timeout) {
3411         gep = SAMPLE_INTERVAL | TIMER_CB;
3412     } else {
3413         lp->timeout = -1;
3414     }
3415 
3416     return gep;
3417 }
3418 
3419 static int
3420 wait_for_link(struct net_device *dev)
3421 {
3422     struct de4x5_private *lp = netdev_priv(dev);
3423 
3424     if (lp->timeout < 0) {
3425         lp->timeout = 1;
3426     }
3427 
3428     if (lp->timeout--) {
3429         return TIMER_CB;
3430     } else {
3431         lp->timeout = -1;
3432     }
3433 
3434     return 0;
3435 }
3436 
3437 /*
3438 **
3439 **
3440 */
3441 static int
3442 test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec)
3443 {
3444     struct de4x5_private *lp = netdev_priv(dev);
3445     int test;
3446     u_long iobase = dev->base_addr;
3447 
3448     if (lp->timeout < 0) {
3449         lp->timeout = msec/100;
3450     }
3451 
3452     reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3453     test = (reg ^ (pol ? ~0 : 0)) & mask;
3454 
3455     if (test && --lp->timeout) {
3456         reg = 100 | TIMER_CB;
3457     } else {
3458         lp->timeout = -1;
3459     }
3460 
3461     return reg;
3462 }
3463 
3464 static int
3465 is_spd_100(struct net_device *dev)
3466 {
3467     struct de4x5_private *lp = netdev_priv(dev);
3468     u_long iobase = dev->base_addr;
3469     int spd;
3470 
3471     if (lp->useMII) {
3472         spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3473         spd = ~(spd ^ lp->phy[lp->active].spd.value);
3474         spd &= lp->phy[lp->active].spd.mask;
3475     } else if (!lp->useSROM) {                      /* de500-xa */
3476         spd = ((~gep_rd(dev)) & GEP_SLNK);
3477     } else {
3478         if ((lp->ibn == 2) || !lp->asBitValid)
3479             return (lp->chipset == DC21143) ? (~inl(DE4X5_SISR)&SISR_LS100) : 0;
3480 
3481         spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3482                   (lp->linkOK & ~lp->asBitValid);
3483     }
3484 
3485     return spd;
3486 }
3487 
3488 static int
3489 is_100_up(struct net_device *dev)
3490 {
3491     struct de4x5_private *lp = netdev_priv(dev);
3492     u_long iobase = dev->base_addr;
3493 
3494     if (lp->useMII) {
3495         /* Double read for sticky bits & temporary drops */
3496         mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3497         return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS;
3498     } else if (!lp->useSROM) {                       /* de500-xa */
3499         return (~gep_rd(dev)) & GEP_SLNK;
3500     } else {
3501         if ((lp->ibn == 2) || !lp->asBitValid)
3502             return (lp->chipset == DC21143) ? (~inl(DE4X5_SISR)&SISR_LS100) : 0;
3503 
3504         return (lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3505                 (lp->linkOK & ~lp->asBitValid);
3506     }
3507 }
3508 
3509 static int
3510 is_10_up(struct net_device *dev)
3511 {
3512     struct de4x5_private *lp = netdev_priv(dev);
3513     u_long iobase = dev->base_addr;
3514 
3515     if (lp->useMII) {
3516         /* Double read for sticky bits & temporary drops */
3517         mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3518         return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS;
3519     } else if (!lp->useSROM) {                       /* de500-xa */
3520         return (~gep_rd(dev)) & GEP_LNP;
3521     } else {
3522         if ((lp->ibn == 2) || !lp->asBitValid)
3523             return ((lp->chipset & ~0x00ff) == DC2114x) ?
3524                     (~inl(DE4X5_SISR)&SISR_LS10):
3525                     0;
3526 
3527         return  (lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3528                 (lp->linkOK & ~lp->asBitValid);
3529     }
3530 }
3531 
3532 static int
3533 is_anc_capable(struct net_device *dev)
3534 {
3535     struct de4x5_private *lp = netdev_priv(dev);
3536     u_long iobase = dev->base_addr;
3537 
3538     if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3539         return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3540     } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3541         return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3542     } else {
3543         return 0;
3544     }
3545 }
3546 
3547 /*
3548 ** Send a packet onto the media and watch for send errors that indicate the
3549 ** media is bad or unconnected.
3550 */
3551 static int
3552 ping_media(struct net_device *dev, int msec)
3553 {
3554     struct de4x5_private *lp = netdev_priv(dev);
3555     u_long iobase = dev->base_addr;
3556     int sisr;
3557 
3558     if (lp->timeout < 0) {
3559         lp->timeout = msec/100;
3560 
3561         lp->tmp = lp->tx_new;                /* Remember the ring position */
3562         load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1);
3563         lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
3564         outl(POLL_DEMAND, DE4X5_TPD);
3565     }
3566 
3567     sisr = inl(DE4X5_SISR);
3568 
3569     if ((!(sisr & SISR_NCR)) &&
3570         ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3571          (--lp->timeout)) {
3572         sisr = 100 | TIMER_CB;
3573     } else {
3574         if ((!(sisr & SISR_NCR)) &&
3575             !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3576             lp->timeout) {
3577             sisr = 0;
3578         } else {
3579             sisr = 1;
3580         }
3581         lp->timeout = -1;
3582     }
3583 
3584     return sisr;
3585 }
3586 
3587 /*
3588 ** This function does 2 things: on Intels it kmalloc's another buffer to
3589 ** replace the one about to be passed up. On Alpha's it kmallocs a buffer
3590 ** into which the packet is copied.
3591 */
3592 static struct sk_buff *
3593 de4x5_alloc_rx_buff(struct net_device *dev, int index, int len)
3594 {
3595     struct de4x5_private *lp = netdev_priv(dev);
3596     struct sk_buff *p;
3597 
3598 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY)
3599     struct sk_buff *ret;
3600     u_long i=0, tmp;
3601 
3602     p = netdev_alloc_skb(dev, IEEE802_3_SZ + DE4X5_ALIGN + 2);
3603     if (!p) return NULL;
3604 
3605     tmp = virt_to_bus(p->data);
3606     i = ((tmp + DE4X5_ALIGN) & ~DE4X5_ALIGN) - tmp;
3607     skb_reserve(p, i);
3608     lp->rx_ring[index].buf = cpu_to_le32(tmp + i);
3609 
3610     ret = lp->rx_skb[index];
3611     lp->rx_skb[index] = p;
3612 
3613     if ((u_long) ret > 1) {
3614         skb_put(ret, len);
3615     }
3616 
3617     return ret;
3618 
3619 #else
3620     if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */
3621 
3622     p = netdev_alloc_skb(dev, len + 2);
3623     if (!p) return NULL;
3624 
3625     skb_reserve(p, 2);                                 /* Align */
3626     if (index < lp->rx_old) {                          /* Wrapped buffer */
3627         short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3628         memcpy(skb_put(p,tlen),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,tlen);
3629         memcpy(skb_put(p,len-tlen),lp->rx_bufs,len-tlen);
3630     } else {                                           /* Linear buffer */
3631         memcpy(skb_put(p,len),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,len);
3632     }
3633 
3634     return p;
3635 #endif
3636 }
3637 
3638 static void
3639 de4x5_free_rx_buffs(struct net_device *dev)
3640 {
3641     struct de4x5_private *lp = netdev_priv(dev);
3642     int i;
3643 
3644     for (i=0; i<lp->rxRingSize; i++) {
3645         if ((u_long) lp->rx_skb[i] > 1) {
3646             dev_kfree_skb(lp->rx_skb[i]);
3647         }
3648         lp->rx_ring[i].status = 0;
3649         lp->rx_skb[i] = (struct sk_buff *)1;    /* Dummy entry */
3650     }
3651 }
3652 
3653 static void
3654 de4x5_free_tx_buffs(struct net_device *dev)
3655 {
3656     struct de4x5_private *lp = netdev_priv(dev);
3657     int i;
3658 
3659     for (i=0; i<lp->txRingSize; i++) {
3660         if (lp->tx_skb[i])
3661             de4x5_free_tx_buff(lp, i);
3662         lp->tx_ring[i].status = 0;
3663     }
3664 
3665     /* Unload the locally queued packets */
3666     __skb_queue_purge(&lp->cache.queue);
3667 }
3668 
3669 /*
3670 ** When a user pulls a connection, the DECchip can end up in a
3671 ** 'running - waiting for end of transmission' state. This means that we
3672 ** have to perform a chip soft reset to ensure that we can synchronize
3673 ** the hardware and software and make any media probes using a loopback
3674 ** packet meaningful.
3675 */
3676 static void
3677 de4x5_save_skbs(struct net_device *dev)
3678 {
3679     struct de4x5_private *lp = netdev_priv(dev);
3680     u_long iobase = dev->base_addr;
3681     s32 omr;
3682 
3683     if (!lp->cache.save_cnt) {
3684         STOP_DE4X5;
3685         de4x5_tx(dev);                          /* Flush any sent skb's */
3686         de4x5_free_tx_buffs(dev);
3687         de4x5_cache_state(dev, DE4X5_SAVE_STATE);
3688         de4x5_sw_reset(dev);
3689         de4x5_cache_state(dev, DE4X5_RESTORE_STATE);
3690         lp->cache.save_cnt++;
3691         START_DE4X5;
3692     }
3693 }
3694 
3695 static void
3696 de4x5_rst_desc_ring(struct net_device *dev)
3697 {
3698     struct de4x5_private *lp = netdev_priv(dev);
3699     u_long iobase = dev->base_addr;
3700     int i;
3701     s32 omr;
3702 
3703     if (lp->cache.save_cnt) {
3704         STOP_DE4X5;
3705         outl(lp->dma_rings, DE4X5_RRBA);
3706         outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
3707              DE4X5_TRBA);
3708 
3709         lp->rx_new = lp->rx_old = 0;
3710         lp->tx_new = lp->tx_old = 0;
3711 
3712         for (i = 0; i < lp->rxRingSize; i++) {
3713             lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3714         }
3715 
3716         for (i = 0; i < lp->txRingSize; i++) {
3717             lp->tx_ring[i].status = cpu_to_le32(0);
3718         }
3719 
3720         barrier();
3721         lp->cache.save_cnt--;
3722         START_DE4X5;
3723     }
3724 }
3725 
3726 static void
3727 de4x5_cache_state(struct net_device *dev, int flag)
3728 {
3729     struct de4x5_private *lp = netdev_priv(dev);
3730     u_long iobase = dev->base_addr;
3731 
3732     switch(flag) {
3733       case DE4X5_SAVE_STATE:
3734         lp->cache.csr0 = inl(DE4X5_BMR);
3735         lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3736         lp->cache.csr7 = inl(DE4X5_IMR);
3737         break;
3738 
3739       case DE4X5_RESTORE_STATE:
3740         outl(lp->cache.csr0, DE4X5_BMR);
3741         outl(lp->cache.csr6, DE4X5_OMR);
3742         outl(lp->cache.csr7, DE4X5_IMR);
3743         if (lp->chipset == DC21140) {
3744             gep_wr(lp->cache.gepc, dev);
3745             gep_wr(lp->cache.gep, dev);
3746         } else {
3747             reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
3748                                                               lp->cache.csr15);
3749         }
3750         break;
3751     }
3752 }
3753 
3754 static void
3755 de4x5_put_cache(struct net_device *dev, struct sk_buff *skb)
3756 {
3757     struct de4x5_private *lp = netdev_priv(dev);
3758 
3759     __skb_queue_tail(&lp->cache.queue, skb);
3760 }
3761 
3762 static void
3763 de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb)
3764 {
3765     struct de4x5_private *lp = netdev_priv(dev);
3766 
3767     __skb_queue_head(&lp->cache.queue, skb);
3768 }
3769 
3770 static struct sk_buff *
3771 de4x5_get_cache(struct net_device *dev)
3772 {
3773     struct de4x5_private *lp = netdev_priv(dev);
3774 
3775     return __skb_dequeue(&lp->cache.queue);
3776 }
3777 
3778 /*
3779 ** Check the Auto Negotiation State. Return OK when a link pass interrupt
3780 ** is received and the auto-negotiation status is NWAY OK.
3781 */
3782 static int
3783 test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec)
3784 {
3785     struct de4x5_private *lp = netdev_priv(dev);
3786     u_long iobase = dev->base_addr;
3787     s32 sts, ans;
3788 
3789     if (lp->timeout < 0) {
3790         lp->timeout = msec/100;
3791         outl(irq_mask, DE4X5_IMR);
3792 
3793         /* clear all pending interrupts */
3794         sts = inl(DE4X5_STS);
3795         outl(sts, DE4X5_STS);
3796     }
3797 
3798     ans = inl(DE4X5_SISR) & SISR_ANS;
3799     sts = inl(DE4X5_STS) & ~TIMER_CB;
3800 
3801     if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3802         sts = 100 | TIMER_CB;
3803     } else {
3804         lp->timeout = -1;
3805     }
3806 
3807     return sts;
3808 }
3809 
3810 static void
3811 de4x5_setup_intr(struct net_device *dev)
3812 {
3813     struct de4x5_private *lp = netdev_priv(dev);
3814     u_long iobase = dev->base_addr;
3815     s32 imr, sts;
3816 
3817     if (inl(DE4X5_OMR) & OMR_SR) {   /* Only unmask if TX/RX is enabled */
3818         imr = 0;
3819         UNMASK_IRQs;
3820         sts = inl(DE4X5_STS);        /* Reset any pending (stale) interrupts */
3821         outl(sts, DE4X5_STS);
3822         ENABLE_IRQs;
3823     }
3824 }
3825 
3826 /*
3827 **
3828 */
3829 static void
3830 reset_init_sia(struct net_device *dev, s32 csr13, s32 csr14, s32 csr15)
3831 {
3832     struct de4x5_private *lp = netdev_priv(dev);
3833     u_long iobase = dev->base_addr;
3834 
3835     RESET_SIA;
3836     if (lp->useSROM) {
3837         if (lp->ibn == 3) {
3838             srom_exec(dev, lp->phy[lp->active].rst);
3839             srom_exec(dev, lp->phy[lp->active].gep);
3840             outl(1, DE4X5_SICR);
3841             return;
3842         } else {
3843             csr15 = lp->cache.csr15;
3844             csr14 = lp->cache.csr14;
3845             csr13 = lp->cache.csr13;
3846             outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3847             outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3848         }
3849     } else {
3850         outl(csr15, DE4X5_SIGR);
3851     }
3852     outl(csr14, DE4X5_STRR);
3853     outl(csr13, DE4X5_SICR);
3854 
3855     mdelay(10);
3856 }
3857 
3858 /*
3859 ** Create a loopback ethernet packet
3860 */
3861 static void
3862 create_packet(struct net_device *dev, char *frame, int len)
3863 {
3864     int i;
3865     char *buf = frame;
3866 
3867     for (i=0; i<ETH_ALEN; i++) {             /* Use this source address */
3868         *buf++ = dev->dev_addr[i];
3869     }
3870     for (i=0; i<ETH_ALEN; i++) {             /* Use this destination address */
3871         *buf++ = dev->dev_addr[i];
3872     }
3873 
3874     *buf++ = 0;                              /* Packet length (2 bytes) */
3875     *buf++ = 1;
3876 }
3877 
3878 /*
3879 ** Look for a particular board name in the EISA configuration space
3880 */
3881 static int
3882 EISA_signature(char *name, struct device *device)
3883 {
3884     int i, status = 0, siglen = ARRAY_SIZE(de4x5_signatures);
3885     struct eisa_device *edev;
3886 
3887     *name = '\0';
3888     edev = to_eisa_device (device);
3889     i = edev->id.driver_data;
3890 
3891     if (i >= 0 && i < siglen) {
3892             strcpy (name, de4x5_signatures[i]);
3893             status = 1;
3894     }
3895 
3896     return status;                         /* return the device name string */
3897 }
3898 
3899 /*
3900 ** Look for a particular board name in the PCI configuration space
3901 */
3902 static int
3903 PCI_signature(char *name, struct de4x5_private *lp)
3904 {
3905     int i, status = 0, siglen = ARRAY_SIZE(de4x5_signatures);
3906 
3907     if (lp->chipset == DC21040) {
3908         strcpy(name, "DE434/5");
3909         return status;
3910     } else {                           /* Search for a DEC name in the SROM */
3911         int tmp = *((char *)&lp->srom + 19) * 3;
3912         strncpy(name, (char *)&lp->srom + 26 + tmp, 8);
3913     }
3914     name[8] = '\0';
3915     for (i=0; i<siglen; i++) {
3916         if (strstr(name,de4x5_signatures[i])!=NULL) break;
3917     }
3918     if (i == siglen) {
3919         if (dec_only) {
3920             *name = '\0';
3921         } else {                        /* Use chip name to avoid confusion */
3922             strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
3923                            ((lp->chipset == DC21041) ? "DC21041" :
3924                             ((lp->chipset == DC21140) ? "DC21140" :
3925                              ((lp->chipset == DC21142) ? "DC21142" :
3926                               ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
3927                              )))))));
3928         }
3929         if (lp->chipset != DC21041) {
3930             lp->useSROM = true;             /* card is not recognisably DEC */
3931         }
3932     } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3933         lp->useSROM = true;
3934     }
3935 
3936     return status;
3937 }
3938 
3939 /*
3940 ** Set up the Ethernet PROM counter to the start of the Ethernet address on
3941 ** the DC21040, else  read the SROM for the other chips.
3942 ** The SROM may not be present in a multi-MAC card, so first read the
3943 ** MAC address and check for a bad address. If there is a bad one then exit
3944 ** immediately with the prior srom contents intact (the h/w address will
3945 ** be fixed up later).
3946 */
3947 static void
3948 DevicePresent(struct net_device *dev, u_long aprom_addr)
3949 {
3950     int i, j=0;
3951     struct de4x5_private *lp = netdev_priv(dev);
3952 
3953     if (lp->chipset == DC21040) {
3954         if (lp->bus == EISA) {
3955             enet_addr_rst(aprom_addr); /* Reset Ethernet Address ROM Pointer */
3956         } else {
3957             outl(0, aprom_addr);       /* Reset Ethernet Address ROM Pointer */
3958         }
3959     } else {                           /* Read new srom */
3960         u_short tmp;
3961         __le16 *p = (__le16 *)((char *)&lp->srom + SROM_HWADD);
3962         for (i=0; i<(ETH_ALEN>>1); i++) {
3963             tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
3964             j += tmp;   /* for check for 0:0:0:0:0:0 or ff:ff:ff:ff:ff:ff */
3965             *p = cpu_to_le16(tmp);
3966         }
3967         if (j == 0 || j == 3 * 0xffff) {
3968                 /* could get 0 only from all-0 and 3 * 0xffff only from all-1 */
3969                 return;
3970         }
3971 
3972         p = (__le16 *)&lp->srom;
3973         for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
3974             tmp = srom_rd(aprom_addr, i);
3975             *p++ = cpu_to_le16(tmp);
3976         }
3977         de4x5_dbg_srom(&lp->srom);
3978     }
3979 }
3980 
3981 /*
3982 ** Since the write on the Enet PROM register doesn't seem to reset the PROM
3983 ** pointer correctly (at least on my DE425 EISA card), this routine should do
3984 ** it...from depca.c.
3985 */
3986 static void
3987 enet_addr_rst(u_long aprom_addr)
3988 {
3989     union {
3990         struct {
3991             u32 a;
3992             u32 b;
3993         } llsig;
3994         char Sig[sizeof(u32) << 1];
3995     } dev;
3996     short sigLength=0;
3997     s8 data;
3998     int i, j;
3999 
4000     dev.llsig.a = ETH_PROM_SIG;
4001     dev.llsig.b = ETH_PROM_SIG;
4002     sigLength = sizeof(u32) << 1;
4003 
4004     for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
4005         data = inb(aprom_addr);
4006         if (dev.Sig[j] == data) {    /* track signature */
4007             j++;
4008         } else {                     /* lost signature; begin search again */
4009             if (data == dev.Sig[0]) {  /* rare case.... */
4010                 j=1;
4011             } else {
4012                 j=0;
4013             }
4014         }
4015     }
4016 }
4017 
4018 /*
4019 ** For the bad status case and no SROM, then add one to the previous
4020 ** address. However, need to add one backwards in case we have 0xff
4021 ** as one or more of the bytes. Only the last 3 bytes should be checked
4022 ** as the first three are invariant - assigned to an organisation.
4023 */
4024 static int
4025 get_hw_addr(struct net_device *dev)
4026 {
4027     u_long iobase = dev->base_addr;
4028     int broken, i, k, tmp, status = 0;
4029     u_short j,chksum;
4030     struct de4x5_private *lp = netdev_priv(dev);
4031 
4032     broken = de4x5_bad_srom(lp);
4033 
4034     for (i=0,k=0,j=0;j<3;j++) {
4035         k <<= 1;
4036         if (k > 0xffff) k-=0xffff;
4037 
4038         if (lp->bus == PCI) {
4039             if (lp->chipset == DC21040) {
4040                 while ((tmp = inl(DE4X5_APROM)) < 0);
4041                 k += (u_char) tmp;
4042                 dev->dev_addr[i++] = (u_char) tmp;
4043                 while ((tmp = inl(DE4X5_APROM)) < 0);
4044                 k += (u_short) (tmp << 8);
4045                 dev->dev_addr[i++] = (u_char) tmp;
4046             } else if (!broken) {
4047                 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4048                 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4049             } else if ((broken == SMC) || (broken == ACCTON)) {
4050                 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4051                 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4052             }
4053         } else {
4054             k += (u_char) (tmp = inb(EISA_APROM));
4055             dev->dev_addr[i++] = (u_char) tmp;
4056             k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4057             dev->dev_addr[i++] = (u_char) tmp;
4058         }
4059 
4060         if (k > 0xffff) k-=0xffff;
4061     }
4062     if (k == 0xffff) k=0;
4063 
4064     if (lp->bus == PCI) {
4065         if (lp->chipset == DC21040) {
4066             while ((tmp = inl(DE4X5_APROM)) < 0);
4067             chksum = (u_char) tmp;
4068             while ((tmp = inl(DE4X5_APROM)) < 0);
4069             chksum |= (u_short) (tmp << 8);
4070             if ((k != chksum) && (dec_only)) status = -1;
4071         }
4072     } else {
4073         chksum = (u_char) inb(EISA_APROM);
4074         chksum |= (u_short) (inb(EISA_APROM) << 8);
4075         if ((k != chksum) && (dec_only)) status = -1;
4076     }
4077 
4078     /* If possible, try to fix a broken card - SMC only so far */
4079     srom_repair(dev, broken);
4080 
4081 #ifdef CONFIG_PPC_PMAC
4082     /*
4083     ** If the address starts with 00 a0, we have to bit-reverse
4084     ** each byte of the address.
4085     */
4086     if ( machine_is(powermac) &&
4087          (dev->dev_addr[0] == 0) &&
4088          (dev->dev_addr[1] == 0xa0) )
4089     {
4090             for (i = 0; i < ETH_ALEN; ++i)
4091             {
4092                     int x = dev->dev_addr[i];
4093                     x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4);
4094                     x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2);
4095                     dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
4096             }
4097     }
4098 #endif /* CONFIG_PPC_PMAC */
4099 
4100     /* Test for a bad enet address */
4101     status = test_bad_enet(dev, status);
4102 
4103     return status;
4104 }
4105 
4106 /*
4107 ** Test for enet addresses in the first 32 bytes.
4108 */
4109 static int
4110 de4x5_bad_srom(struct de4x5_private *lp)
4111 {
4112     int i, status = 0;
4113 
4114     for (i = 0; i < ARRAY_SIZE(enet_det); i++) {
4115         if (!memcmp(&lp->srom, &enet_det[i], 3) &&
4116             !memcmp((char *)&lp->srom+0x10, &enet_det[i], 3)) {
4117             if (i == 0) {
4118                 status = SMC;
4119             } else if (i == 1) {
4120                 status = ACCTON;
4121             }
4122             break;
4123         }
4124     }
4125 
4126     return status;
4127 }
4128 
4129 static void
4130 srom_repair(struct net_device *dev, int card)
4131 {
4132     struct de4x5_private *lp = netdev_priv(dev);
4133 
4134     switch(card) {
4135       case SMC:
4136         memset((char *)&lp->srom, 0, sizeof(struct de4x5_srom));
4137         memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4138         memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4139         lp->useSROM = true;
4140         break;
4141     }
4142 }
4143 
4144 /*
4145 ** Assume that the irq's do not follow the PCI spec - this is seems
4146 ** to be true so far (2 for 2).
4147 */
4148 static int
4149 test_bad_enet(struct net_device *dev, int status)
4150 {
4151     struct de4x5_private *lp = netdev_priv(dev);
4152     int i, tmp;
4153 
4154     for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4155     if ((tmp == 0) || (tmp == 0x5fa)) {
4156         if ((lp->chipset == last.chipset) &&
4157             (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4158             for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
4159             for (i=ETH_ALEN-1; i>2; --i) {
4160                 dev->dev_addr[i] += 1;
4161                 if (dev->dev_addr[i] != 0) break;
4162             }
4163             for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4164             if (!an_exception(lp)) {
4165                 dev->irq = last.irq;
4166             }
4167 
4168             status = 0;
4169         }
4170     } else if (!status) {
4171         last.chipset = lp->chipset;
4172         last.bus = lp->bus_num;
4173         last.irq = dev->irq;
4174         for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4175     }
4176 
4177     return status;
4178 }
4179 
4180 /*
4181 ** List of board exceptions with correctly wired IRQs
4182 */
4183 static int
4184 an_exception(struct de4x5_private *lp)
4185 {
4186     if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
4187         (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4188         return -1;
4189     }
4190 
4191     return 0;
4192 }
4193 
4194 /*
4195 ** SROM Read
4196 */
4197 static short
4198 srom_rd(u_long addr, u_char offset)
4199 {
4200     sendto_srom(SROM_RD | SROM_SR, addr);
4201 
4202     srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
4203     srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
4204     srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
4205 
4206     return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
4207 }
4208 
4209 static void
4210 srom_latch(u_int command, u_long addr)
4211 {
4212     sendto_srom(command, addr);
4213     sendto_srom(command | DT_CLK, addr);
4214     sendto_srom(command, addr);
4215 }
4216 
4217 static void
4218 srom_command(u_int command, u_long addr)
4219 {
4220     srom_latch(command, addr);
4221     srom_latch(command, addr);
4222     srom_latch((command & 0x0000ff00) | DT_CS, addr);
4223 }
4224 
4225 static void
4226 srom_address(u_int command, u_long addr, u_char offset)
4227 {
4228     int i, a;
4229 
4230     a = offset << 2;
4231     for (i=0; i<6; i++, a <<= 1) {
4232         srom_latch(command | ((a & 0x80) ? DT_IN : 0), addr);
4233     }
4234     udelay(1);
4235 
4236     i = (getfrom_srom(addr) >> 3) & 0x01;
4237 }
4238 
4239 static short
4240 srom_data(u_int command, u_long addr)
4241 {
4242     int i;
4243     short word = 0;
4244     s32 tmp;
4245 
4246     for (i=0; i<16; i++) {
4247         sendto_srom(command  | DT_CLK, addr);
4248         tmp = getfrom_srom(addr);
4249         sendto_srom(command, addr);
4250 
4251         word = (word << 1) | ((tmp >> 3) & 0x01);
4252     }
4253 
4254     sendto_srom(command & 0x0000ff00, addr);
4255 
4256     return word;
4257 }
4258 
4259 /*
4260 static void
4261 srom_busy(u_int command, u_long addr)
4262 {
4263    sendto_srom((command & 0x0000ff00) | DT_CS, addr);
4264 
4265    while (!((getfrom_srom(addr) >> 3) & 0x01)) {
4266        mdelay(1);
4267    }
4268 
4269    sendto_srom(command & 0x0000ff00, addr);
4270 }
4271 */
4272 
4273 static void
4274 sendto_srom(u_int command, u_long addr)
4275 {
4276     outl(command, addr);
4277     udelay(1);
4278 }
4279 
4280 static int
4281 getfrom_srom(u_long addr)
4282 {
4283     s32 tmp;
4284 
4285     tmp = inl(addr);
4286     udelay(1);
4287 
4288     return tmp;
4289 }
4290 
4291 static int
4292 srom_infoleaf_info(struct net_device *dev)
4293 {
4294     struct de4x5_private *lp = netdev_priv(dev);
4295     int i, count;
4296     u_char *p;
4297 
4298     /* Find the infoleaf decoder function that matches this chipset */
4299     for (i=0; i<INFOLEAF_SIZE; i++) {
4300         if (lp->chipset == infoleaf_array[i].chipset) break;
4301     }
4302     if (i == INFOLEAF_SIZE) {
4303         lp->useSROM = false;
4304         printk("%s: Cannot find correct chipset for SROM decoding!\n",
4305                                                                   dev->name);
4306         return -ENXIO;
4307     }
4308 
4309     lp->infoleaf_fn = infoleaf_array[i].fn;
4310 
4311     /* Find the information offset that this function should use */
4312     count = *((u_char *)&lp->srom + 19);
4313     p  = (u_char *)&lp->srom + 26;
4314 
4315     if (count > 1) {
4316         for (i=count; i; --i, p+=3) {
4317             if (lp->device == *p) break;
4318         }
4319         if (i == 0) {
4320             lp->useSROM = false;
4321             printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
4322                                                        dev->name, lp->device);
4323             return -ENXIO;
4324         }
4325     }
4326 
4327         lp->infoleaf_offset = get_unaligned_le16(p + 1);
4328 
4329     return 0;
4330 }
4331 
4332 /*
4333 ** This routine loads any type 1 or 3 MII info into the mii device
4334 ** struct and executes any type 5 code to reset PHY devices for this
4335 ** controller.
4336 ** The info for the MII devices will be valid since the index used
4337 ** will follow the discovery process from MII address 1-31 then 0.
4338 */
4339 static void
4340 srom_init(struct net_device *dev)
4341 {
4342     struct de4x5_private *lp = netdev_priv(dev);
4343     u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4344     u_char count;
4345 
4346     p+=2;
4347     if (lp->chipset == DC21140) {
4348         lp->cache.gepc = (*p++ | GEP_CTRL);
4349         gep_wr(lp->cache.gepc, dev);
4350     }
4351 
4352     /* Block count */
4353     count = *p++;
4354 
4355     /* Jump the infoblocks to find types */
4356     for (;count; --count) {
4357         if (*p < 128) {
4358             p += COMPACT_LEN;
4359         } else if (*(p+1) == 5) {
4360             type5_infoblock(dev, 1, p);
4361             p += ((*p & BLOCK_LEN) + 1);
4362         } else if (*(p+1) == 4) {
4363             p += ((*p & BLOCK_LEN) + 1);
4364         } else if (*(p+1) == 3) {
4365             type3_infoblock(dev, 1, p);
4366             p += ((*p & BLOCK_LEN) + 1);
4367         } else if (*(p+1) == 2) {
4368             p += ((*p & BLOCK_LEN) + 1);
4369         } else if (*(p+1) == 1) {
4370             type1_infoblock(dev, 1, p);
4371             p += ((*p & BLOCK_LEN) + 1);
4372         } else {
4373             p += ((*p & BLOCK_LEN) + 1);
4374         }
4375     }
4376 }
4377 
4378 /*
4379 ** A generic routine that writes GEP control, data and reset information
4380 ** to the GEP register (21140) or csr15 GEP portion (2114[23]).
4381 */
4382 static void
4383 srom_exec(struct net_device *dev, u_char *p)
4384 {
4385     struct de4x5_private *lp = netdev_priv(dev);
4386     u_long iobase = dev->base_addr;
4387     u_char count = (p ? *p++ : 0);
4388     u_short *w = (u_short *)p;
4389 
4390     if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4391 
4392     if (lp->chipset != DC21140) RESET_SIA;
4393 
4394     while (count--) {
4395         gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
4396                                                    *p++ : get_unaligned_le16(w++)), dev);
4397         mdelay(2);                          /* 2ms per action */
4398     }
4399 
4400     if (lp->chipset != DC21140) {
4401         outl(lp->cache.csr14, DE4X5_STRR);
4402         outl(lp->cache.csr13, DE4X5_SICR);
4403     }
4404 }
4405 
4406 /*
4407 ** Basically this function is a NOP since it will never be called,
4408 ** unless I implement the DC21041 SROM functions. There's no need
4409 ** since the existing code will be satisfactory for all boards.
4410 */
4411 static int
4412 dc21041_infoleaf(struct net_device *dev)
4413 {
4414     return DE4X5_AUTOSENSE_MS;
4415 }
4416 
4417 static int
4418 dc21140_infoleaf(struct net_device *dev)
4419 {
4420     struct de4x5_private *lp = netdev_priv(dev);
4421     u_char count = 0;
4422     u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4423     int next_tick = DE4X5_AUTOSENSE_MS;
4424 
4425     /* Read the connection type */
4426     p+=2;
4427 
4428     /* GEP control */
4429     lp->cache.gepc = (*p++ | GEP_CTRL);
4430 
4431     /* Block count */
4432     count = *p++;
4433 
4434     /* Recursively figure out the info blocks */
4435     if (*p < 128) {
4436         next_tick = dc_infoblock[COMPACT](dev, count, p);
4437     } else {
4438         next_tick = dc_infoblock[*(p+1)](dev, count, p);
4439     }
4440 
4441     if (lp->tcount == count) {
4442         lp->media = NC;
4443         if (lp->media != lp->c_media) {
4444             de4x5_dbg_media(dev);
4445             lp->c_media = lp->media;
4446         }
4447         lp->media = INIT;
4448         lp->tcount = 0;
4449         lp->tx_enable = false;
4450     }
4451 
4452     return next_tick & ~TIMER_CB;
4453 }
4454 
4455 static int
4456 dc21142_infoleaf(struct net_device *dev)
4457 {
4458     struct de4x5_private *lp = netdev_priv(dev);
4459     u_char count = 0;
4460     u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4461     int next_tick = DE4X5_AUTOSENSE_MS;
4462 
4463     /* Read the connection type */
4464     p+=2;
4465 
4466     /* Block count */
4467     count = *p++;
4468 
4469     /* Recursively figure out the info blocks */
4470     if (*p < 128) {
4471         next_tick = dc_infoblock[COMPACT](dev, count, p);
4472     } else {
4473         next_tick = dc_infoblock[*(p+1)](dev, count, p);
4474     }
4475 
4476     if (lp->tcount == count) {
4477         lp->media = NC;
4478         if (lp->media != lp->c_media) {
4479             de4x5_dbg_media(dev);
4480             lp->c_media = lp->media;
4481         }
4482         lp->media = INIT;
4483         lp->tcount = 0;
4484         lp->tx_enable = false;
4485     }
4486 
4487     return next_tick & ~TIMER_CB;
4488 }
4489 
4490 static int
4491 dc21143_infoleaf(struct net_device *dev)
4492 {
4493     struct de4x5_private *lp = netdev_priv(dev);
4494     u_char count = 0;
4495     u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4496     int next_tick = DE4X5_AUTOSENSE_MS;
4497 
4498     /* Read the connection type */
4499     p+=2;
4500 
4501     /* Block count */
4502     count = *p++;
4503 
4504     /* Recursively figure out the info blocks */
4505     if (*p < 128) {
4506         next_tick = dc_infoblock[COMPACT](dev, count, p);
4507     } else {
4508         next_tick = dc_infoblock[*(p+1)](dev, count, p);
4509     }
4510     if (lp->tcount == count) {
4511         lp->media = NC;
4512         if (lp->media != lp->c_media) {
4513             de4x5_dbg_media(dev);
4514             lp->c_media = lp->media;
4515         }
4516         lp->media = INIT;
4517         lp->tcount = 0;
4518         lp->tx_enable = false;
4519     }
4520 
4521     return next_tick & ~TIMER_CB;
4522 }
4523 
4524 /*
4525 ** The compact infoblock is only designed for DC21140[A] chips, so
4526 ** we'll reuse the dc21140m_autoconf function. Non MII media only.
4527 */
4528 static int
4529 compact_infoblock(struct net_device *dev, u_char count, u_char *p)
4530 {
4531     struct de4x5_private *lp = netdev_priv(dev);
4532     u_char flags, csr6;
4533 
4534     /* Recursively figure out the info blocks */
4535     if (--count > lp->tcount) {
4536         if (*(p+COMPACT_LEN) < 128) {
4537             return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
4538         } else {
4539             return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
4540         }
4541     }
4542 
4543     if ((lp->media == INIT) && (lp->timeout < 0)) {
4544         lp->ibn = COMPACT;
4545         lp->active = 0;
4546         gep_wr(lp->cache.gepc, dev);
4547         lp->infoblock_media = (*p++) & COMPACT_MC;
4548         lp->cache.gep = *p++;
4549         csr6 = *p++;
4550         flags = *p++;
4551 
4552         lp->asBitValid = (flags & 0x80) ? 0 : -1;
4553         lp->defMedium = (flags & 0x40) ? -1 : 0;
4554         lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4555         lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4556         lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4557         lp->useMII = false;
4558 
4559         de4x5_switch_mac_port(dev);
4560     }
4561 
4562     return dc21140m_autoconf(dev);
4563 }
4564 
4565 /*
4566 ** This block describes non MII media for the DC21140[A] only.
4567 */
4568 static int
4569 type0_infoblock(struct net_device *dev, u_char count, u_char *p)
4570 {
4571     struct de4x5_private *lp = netdev_priv(dev);
4572     u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4573 
4574     /* Recursively figure out the info blocks */
4575     if (--count > lp->tcount) {
4576         if (*(p+len) < 128) {
4577             return dc_infoblock[COMPACT](dev, count, p+len);
4578         } else {
4579             return dc_infoblock[*(p+len+1)](dev, count, p+len);
4580         }
4581     }
4582 
4583     if ((lp->media == INIT) && (lp->timeout < 0)) {
4584         lp->ibn = 0;
4585         lp->active = 0;
4586         gep_wr(lp->cache.gepc, dev);
4587         p+=2;
4588         lp->infoblock_media = (*p++) & BLOCK0_MC;
4589         lp->cache.gep = *p++;
4590         csr6 = *p++;
4591         flags = *p++;
4592 
4593         lp->asBitValid = (flags & 0x80) ? 0 : -1;
4594         lp->defMedium = (flags & 0x40) ? -1 : 0;
4595         lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4596         lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4597         lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4598         lp->useMII = false;
4599 
4600         de4x5_switch_mac_port(dev);
4601     }
4602 
4603     return dc21140m_autoconf(dev);
4604 }
4605 
4606 /* These functions are under construction! */
4607 
4608 static int
4609 type1_infoblock(struct net_device *dev, u_char count, u_char *p)
4610 {
4611     struct de4x5_private *lp = netdev_priv(dev);
4612     u_char len = (*p & BLOCK_LEN)+1;
4613 
4614     /* Recursively figure out the info blocks */
4615     if (--count > lp->tcount) {
4616         if (*(p+len) < 128) {
4617             return dc_infoblock[COMPACT](dev, count, p+len);
4618         } else {
4619             return dc_infoblock[*(p+len+1)](dev, count, p+len);
4620         }
4621     }
4622 
4623     p += 2;
4624     if (lp->state == INITIALISED) {
4625         lp->ibn = 1;
4626         lp->active = *p++;
4627         lp->phy[lp->active].gep = (*p ? p : NULL); p += (*p + 1);
4628         lp->phy[lp->active].rst = (*p ? p : NULL); p += (*p + 1);
4629         lp->phy[lp->active].mc  = get_unaligned_le16(p); p += 2;
4630         lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2;
4631         lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2;
4632         lp->phy[lp->active].ttm = get_unaligned_le16(p);
4633         return 0;
4634     } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4635         lp->ibn = 1;
4636         lp->active = *p;
4637         lp->infoblock_csr6 = OMR_MII_100;
4638         lp->useMII = true;
4639         lp->infoblock_media = ANS;
4640 
4641         de4x5_switch_mac_port(dev);
4642     }
4643 
4644     return dc21140m_autoconf(dev);
4645 }
4646 
4647 static int
4648 type2_infoblock(struct net_device *dev, u_char count, u_char *p)
4649 {
4650     struct de4x5_private *lp = netdev_priv(dev);
4651     u_char len = (*p & BLOCK_LEN)+1;
4652 
4653     /* Recursively figure out the info blocks */
4654     if (--count > lp->tcount) {
4655         if (*(p+len) < 128) {
4656             return dc_infoblock[COMPACT](dev, count, p+len);
4657         } else {
4658             return dc_infoblock[*(p+len+1)](dev, count, p+len);
4659         }
4660     }
4661 
4662     if ((lp->media == INIT) && (lp->timeout < 0)) {
4663         lp->ibn = 2;
4664         lp->active = 0;
4665         p += 2;
4666         lp->infoblock_media = (*p) & MEDIA_CODE;
4667 
4668         if ((*p++) & EXT_FIELD) {
4669             lp->cache.csr13 = get_unaligned_le16(p); p += 2;
4670             lp->cache.csr14 = get_unaligned_le16(p); p += 2;
4671             lp->cache.csr15 = get_unaligned_le16(p); p += 2;
4672         } else {
4673             lp->cache.csr13 = CSR13;
4674             lp->cache.csr14 = CSR14;
4675             lp->cache.csr15 = CSR15;
4676         }
4677         lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4678         lp->cache.gep  = ((s32)(get_unaligned_le16(p)) << 16);
4679         lp->infoblock_csr6 = OMR_SIA;
4680         lp->useMII = false;
4681 
4682         de4x5_switch_mac_port(dev);
4683     }
4684 
4685     return dc2114x_autoconf(dev);
4686 }
4687 
4688 static int
4689 type3_infoblock(struct net_device *dev, u_char count, u_char *p)
4690 {
4691     struct de4x5_private *lp = netdev_priv(dev);
4692     u_char len = (*p & BLOCK_LEN)+1;
4693 
4694     /* Recursively figure out the info blocks */
4695     if (--count > lp->tcount) {
4696         if (*(p+len) < 128) {
4697             return dc_infoblock[COMPACT](dev, count, p+len);
4698         } else {
4699             return dc_infoblock[*(p+len+1)](dev, count, p+len);
4700         }
4701     }
4702 
4703     p += 2;
4704     if (lp->state == INITIALISED) {
4705         lp->ibn = 3;
4706         lp->active = *p++;
4707         if (MOTO_SROM_BUG) lp->active = 0;
4708         lp->phy[lp->active].gep = (*p ? p : NULL); p += (2 * (*p) + 1);
4709         lp->phy[lp->active].rst = (*p ? p : NULL); p += (2 * (*p) + 1);
4710         lp->phy[lp->active].mc  = get_unaligned_le16(p); p += 2;
4711         lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2;
4712         lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2;
4713         lp->phy[lp->active].ttm = get_unaligned_le16(p); p += 2;
4714         lp->phy[lp->active].mci = *p;
4715         return 0;
4716     } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4717         lp->ibn = 3;
4718         lp->active = *p;
4719         if (MOTO_SROM_BUG) lp->active = 0;
4720         lp->infoblock_csr6 = OMR_MII_100;
4721         lp->useMII = true;
4722         lp->infoblock_media = ANS;
4723 
4724         de4x5_switch_mac_port(dev);
4725     }
4726 
4727     return dc2114x_autoconf(dev);
4728 }
4729 
4730 static int
4731 type4_infoblock(struct net_device *dev, u_char count, u_char *p)
4732 {
4733     struct de4x5_private *lp = netdev_priv(dev);
4734     u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4735 
4736     /* Recursively figure out the info blocks */
4737     if (--count > lp->tcount) {
4738         if (*(p+len) < 128) {
4739             return dc_infoblock[COMPACT](dev, count, p+len);
4740         } else {
4741             return dc_infoblock[*(p+len+1)](dev, count, p+len);
4742         }
4743     }
4744 
4745     if ((lp->media == INIT) && (lp->timeout < 0)) {
4746         lp->ibn = 4;
4747         lp->active = 0;
4748         p+=2;
4749         lp->infoblock_media = (*p++) & MEDIA_CODE;
4750         lp->cache.csr13 = CSR13;              /* Hard coded defaults */
4751         lp->cache.csr14 = CSR14;
4752         lp->cache.csr15 = CSR15;
4753         lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4754         lp->cache.gep  = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4755         csr6 = *p++;
4756         flags = *p++;
4757 
4758         lp->asBitValid = (flags & 0x80) ? 0 : -1;
4759         lp->defMedium = (flags & 0x40) ? -1 : 0;
4760         lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4761         lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4762         lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4763         lp->useMII = false;
4764 
4765         de4x5_switch_mac_port(dev);
4766     }
4767 
4768     return dc2114x_autoconf(dev);
4769 }
4770 
4771 /*
4772 ** This block type provides information for resetting external devices
4773 ** (chips) through the General Purpose Register.
4774 */
4775 static int
4776 type5_infoblock(struct net_device *dev, u_char count, u_char *p)
4777 {
4778     struct de4x5_private *lp = netdev_priv(dev);
4779     u_char len = (*p & BLOCK_LEN)+1;
4780 
4781     /* Recursively figure out the info blocks */
4782     if (--count > lp->tcount) {
4783         if (*(p+len) < 128) {
4784             return dc_infoblock[COMPACT](dev, count, p+len);
4785         } else {
4786             return dc_infoblock[*(p+len+1)](dev, count, p+len);
4787         }
4788     }
4789 
4790     /* Must be initializing to run this code */
4791     if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4792         p+=2;
4793         lp->rst = p;
4794         srom_exec(dev, lp->rst);
4795     }
4796 
4797     return DE4X5_AUTOSENSE_MS;
4798 }
4799 
4800 /*
4801 ** MII Read/Write
4802 */
4803 
4804 static int
4805 mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)
4806 {
4807     mii_wdata(MII_PREAMBLE,  2, ioaddr);   /* Start of 34 bit preamble...    */
4808     mii_wdata(MII_PREAMBLE, 32, ioaddr);   /* ...continued                   */
4809     mii_wdata(MII_STRD, 4, ioaddr);        /* SFD and Read operation         */
4810     mii_address(phyaddr, ioaddr);          /* PHY address to be accessed     */
4811     mii_address(phyreg, ioaddr);           /* PHY Register to read           */
4812     mii_ta(MII_STRD, ioaddr);              /* Turn around time - 2 MDC       */
4813 
4814     return mii_rdata(ioaddr);              /* Read data                      */
4815 }
4816 
4817 static void
4818 mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)
4819 {
4820     mii_wdata(MII_PREAMBLE,  2, ioaddr);   /* Start of 34 bit preamble...    */
4821     mii_wdata(MII_PREAMBLE, 32, ioaddr);   /* ...continued                   */
4822     mii_wdata(MII_STWR, 4, ioaddr);        /* SFD and Write operation        */
4823     mii_address(phyaddr, ioaddr);          /* PHY address to be accessed     */
4824     mii_address(phyreg, ioaddr);           /* PHY Register to write          */
4825     mii_ta(MII_STWR, ioaddr);              /* Turn around time - 2 MDC       */
4826     data = mii_swap(data, 16);             /* Swap data bit ordering         */
4827     mii_wdata(data, 16, ioaddr);           /* Write data                     */
4828 }
4829 
4830 static int
4831 mii_rdata(u_long ioaddr)
4832 {
4833     int i;
4834     s32 tmp = 0;
4835 
4836     for (i=0; i<16; i++) {
4837         tmp <<= 1;
4838         tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4839     }
4840 
4841     return tmp;
4842 }
4843 
4844 static void
4845 mii_wdata(int data, int len, u_long ioaddr)
4846 {
4847     int i;
4848 
4849     for (i=0; i<len; i++) {
4850         sendto_mii(MII_MWR | MII_WR, data, ioaddr);
4851         data >>= 1;
4852     }
4853 }
4854 
4855 static void
4856 mii_address(u_char addr, u_long ioaddr)
4857 {
4858     int i;
4859 
4860     addr = mii_swap(addr, 5);
4861     for (i=0; i<5; i++) {
4862         sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
4863         addr >>= 1;
4864     }
4865 }
4866 
4867 static void
4868 mii_ta(u_long rw, u_long ioaddr)
4869 {
4870     if (rw == MII_STWR) {
4871         sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
4872         sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
4873     } else {
4874         getfrom_mii(MII_MRD | MII_RD, ioaddr);        /* Tri-state MDIO */
4875     }
4876 }
4877 
4878 static int
4879 mii_swap(int data, int len)
4880 {
4881     int i, tmp = 0;
4882 
4883     for (i=0; i<len; i++) {
4884         tmp <<= 1;
4885         tmp |= (data & 1);
4886         data >>= 1;
4887     }
4888 
4889     return tmp;
4890 }
4891 
4892 static void
4893 sendto_mii(u32 command, int data, u_long ioaddr)
4894 {
4895     u32 j;
4896 
4897     j = (data & 1) << 17;
4898     outl(command | j, ioaddr);
4899     udelay(1);
4900     outl(command | MII_MDC | j, ioaddr);
4901     udelay(1);
4902 }
4903 
4904 static int
4905 getfrom_mii(u32 command, u_long ioaddr)
4906 {
4907     outl(command, ioaddr);
4908     udelay(1);
4909     outl(command | MII_MDC, ioaddr);
4910     udelay(1);
4911 
4912     return (inl(ioaddr) >> 19) & 1;
4913 }
4914 
4915 /*
4916 ** Here's 3 ways to calculate the OUI from the ID registers.
4917 */
4918 static int
4919 mii_get_oui(u_char phyaddr, u_long ioaddr)
4920 {
4921 /*
4922     union {
4923         u_short reg;
4924         u_char breg[2];
4925     } a;
4926     int i, r2, r3, ret=0;*/
4927     int r2, r3;
4928 
4929     /* Read r2 and r3 */
4930     r2 = mii_rd(MII_ID0, phyaddr, ioaddr);
4931     r3 = mii_rd(MII_ID1, phyaddr, ioaddr);
4932                                                 /* SEEQ and Cypress way * /
4933     / * Shuffle r2 and r3 * /
4934     a.reg=0;
4935     r3 = ((r3>>10)|(r2<<6))&0x0ff;
4936     r2 = ((r2>>2)&0x3fff);
4937 
4938     / * Bit reverse r3 * /
4939     for (i=0;i<8;i++) {
4940         ret<<=1;
4941         ret |= (r3&1);
4942         r3>>=1;
4943     }
4944 
4945     / * Bit reverse r2 * /
4946     for (i=0;i<16;i++) {
4947         a.reg<<=1;
4948         a.reg |= (r2&1);
4949         r2>>=1;
4950     }
4951 
4952     / * Swap r2 bytes * /
4953     i=a.breg[0];
4954     a.breg[0]=a.breg[1];
4955     a.breg[1]=i;
4956 
4957     return (a.reg<<8)|ret; */                 /* SEEQ and Cypress way */
4958 /*    return (r2<<6)|(u_int)(r3>>10); */      /* NATIONAL and BROADCOM way */
4959     return r2;                                  /* (I did it) My way */
4960 }
4961 
4962 /*
4963 ** The SROM spec forces us to search addresses [1-31 0]. Bummer.
4964 */
4965 static int
4966 mii_get_phy(struct net_device *dev)
4967 {
4968     struct de4x5_private *lp = netdev_priv(dev);
4969     u_long iobase = dev->base_addr;
4970     int i, j, k, n, limit=ARRAY_SIZE(phy_info);
4971     int id;
4972 
4973     lp->active = 0;
4974     lp->useMII = true;
4975 
4976     /* Search the MII address space for possible PHY devices */
4977     for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(i+1)%DE4X5_MAX_MII) {
4978         lp->phy[lp->active].addr = i;
4979         if (i==0) n++;                             /* Count cycles */
4980         while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */
4981         id = mii_get_oui(i, DE4X5_MII);
4982         if ((id == 0) || (id == 65535)) continue;  /* Valid ID? */
4983         for (j=0; j<limit; j++) {                  /* Search PHY table */
4984             if (id != phy_info[j].id) continue;    /* ID match? */
4985             for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++);
4986             if (k < DE4X5_MAX_PHY) {
4987                 memcpy((char *)&lp->phy[k],
4988                        (char *)&phy_info[j], sizeof(struct phy_table));
4989                 lp->phy[k].addr = i;
4990                 lp->mii_cnt++;
4991                 lp->active++;
4992             } else {
4993                 goto purgatory;                    /* Stop the search */
4994             }
4995             break;
4996         }
4997         if ((j == limit) && (i < DE4X5_MAX_MII)) {
4998             for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++);
4999             lp->phy[k].addr = i;
5000             lp->phy[k].id = id;
5001             lp->phy[k].spd.reg = GENERIC_REG;      /* ANLPA register         */
5002             lp->phy[k].spd.mask = GENERIC_MASK;    /* 100Mb/s technologies   */
5003             lp->phy[k].spd.value = GENERIC_VALUE;  /* TX & T4, H/F Duplex    */
5004             lp->mii_cnt++;
5005             lp->active++;
5006             printk("%s: Using generic MII device control. If the board doesn't operate,\nplease mail the following dump to the author:\n", dev->name);
5007             j = de4x5_debug;
5008             de4x5_debug |= DEBUG_MII;
5009             de4x5_dbg_mii(dev, k);
5010             de4x5_debug = j;
5011             printk("\n");
5012         }
5013     }
5014   purgatory:
5015     lp->active = 0;
5016     if (lp->phy[0].id) {                           /* Reset the PHY devices */
5017         for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++) { /*For each PHY*/
5018             mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5019             while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
5020 
5021             de4x5_dbg_mii(dev, k);
5022         }
5023     }
5024     if (!lp->mii_cnt) lp->useMII = false;
5025 
5026     return lp->mii_cnt;
5027 }
5028 
5029 static char *
5030 build_setup_frame(struct net_device *dev, int mode)
5031 {
5032     struct de4x5_private *lp = netdev_priv(dev);
5033     int i;
5034     char *pa = lp->setup_frame;
5035 
5036     /* Initialise the setup frame */
5037     if (mode == ALL) {
5038         memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5039     }
5040 
5041     if (lp->setup_f == HASH_PERF) {
5042         for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5043             *(pa + i) = dev->dev_addr[i];                 /* Host address */
5044             if (i & 0x01) pa += 2;
5045         }
5046         *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
5047     } else {
5048         for (i=0; i<ETH_ALEN; i++) { /* Host address */
5049             *(pa + (i&1)) = dev->dev_addr[i];
5050             if (i & 0x01) pa += 4;
5051         }
5052         for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */
5053             *(pa + (i&1)) = (char) 0xff;
5054             if (i & 0x01) pa += 4;
5055         }
5056     }
5057 
5058     return pa;                     /* Points to the next entry */
5059 }
5060 
5061 static void
5062 disable_ast(struct net_device *dev)
5063 {
5064         struct de4x5_private *lp = netdev_priv(dev);
5065         del_timer_sync(&lp->timer);
5066 }
5067 
5068 static long
5069 de4x5_switch_mac_port(struct net_device *dev)
5070 {
5071     struct de4x5_private *lp = netdev_priv(dev);
5072     u_long iobase = dev->base_addr;
5073     s32 omr;
5074 
5075     STOP_DE4X5;
5076 
5077     /* Assert the OMR_PS bit in CSR6 */
5078     omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
5079                                                                      OMR_FDX));
5080     omr |= lp->infoblock_csr6;
5081     if (omr & OMR_PS) omr |= OMR_HBD;
5082     outl(omr, DE4X5_OMR);
5083 
5084     /* Soft Reset */
5085     RESET_DE4X5;
5086 
5087     /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */
5088     if (lp->chipset == DC21140) {
5089         gep_wr(lp->cache.gepc, dev);
5090         gep_wr(lp->cache.gep, dev);
5091     } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5092         reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5093     }
5094 
5095     /* Restore CSR6 */
5096     outl(omr, DE4X5_OMR);
5097 
5098     /* Reset CSR8 */
5099     inl(DE4X5_MFC);
5100 
5101     return omr;
5102 }
5103 
5104 static void
5105 gep_wr(s32 data, struct net_device *dev)
5106 {
5107     struct de4x5_private *lp = netdev_priv(dev);
5108     u_long iobase = dev->base_addr;
5109 
5110     if (lp->chipset == DC21140) {
5111         outl(data, DE4X5_GEP);
5112     } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5113         outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5114     }
5115 }
5116 
5117 static int
5118 gep_rd(struct net_device *dev)
5119 {
5120     struct de4x5_private *lp = netdev_priv(dev);
5121     u_long iobase = dev->base_addr;
5122 
5123     if (lp->chipset == DC21140) {
5124         return inl(DE4X5_GEP);
5125     } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5126         return inl(DE4X5_SIGR) & 0x000fffff;
5127     }
5128 
5129     return 0;
5130 }
5131 
5132 static void
5133 yawn(struct net_device *dev, int state)
5134 {
5135     struct de4x5_private *lp = netdev_priv(dev);
5136     u_long iobase = dev->base_addr;
5137 
5138     if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5139 
5140     if(lp->bus == EISA) {
5141         switch(state) {
5142           case WAKEUP:
5143             outb(WAKEUP, PCI_CFPM);
5144             mdelay(10);
5145             break;
5146 
5147           case SNOOZE:
5148             outb(SNOOZE, PCI_CFPM);
5149             break;
5150 
5151           case SLEEP:
5152             outl(0, DE4X5_SICR);
5153             outb(SLEEP, PCI_CFPM);
5154             break;
5155         }
5156     } else {
5157         struct pci_dev *pdev = to_pci_dev (lp->gendev);
5158         switch(state) {
5159           case WAKEUP:
5160             pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
5161             mdelay(10);
5162             break;
5163 
5164           case SNOOZE:
5165             pci_write_config_byte(pdev, PCI_CFDA_PSM, SNOOZE);
5166             break;
5167 
5168           case SLEEP:
5169             outl(0, DE4X5_SICR);
5170             pci_write_config_byte(pdev, PCI_CFDA_PSM, SLEEP);
5171             break;
5172         }
5173     }
5174 }
5175 
5176 static void
5177 de4x5_parse_params(struct net_device *dev)
5178 {
5179     struct de4x5_private *lp = netdev_priv(dev);
5180     char *p, *q, t;
5181 
5182     lp->params.fdx = false;
5183     lp->params.autosense = AUTO;
5184 
5185     if (args == NULL) return;
5186 
5187     if ((p = strstr(args, dev->name))) {
5188         if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p);
5189         t = *q;
5190         *q = '\0';
5191 
5192         if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = true;
5193 
5194         if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) {
5195             if (strstr(p, "TP_NW")) {
5196                 lp->params.autosense = TP_NW;
5197             } else if (strstr(p, "TP")) {
5198                 lp->params.autosense = TP;
5199             } else if (strstr(p, "BNC_AUI")) {
5200                 lp->params.autosense = BNC;
5201             } else if (strstr(p, "BNC")) {
5202                 lp->params.autosense = BNC;
5203             } else if (strstr(p, "AUI")) {
5204                 lp->params.autosense = AUI;
5205             } else if (strstr(p, "10Mb")) {
5206                 lp->params.autosense = _10Mb;
5207             } else if (strstr(p, "100Mb")) {
5208                 lp->params.autosense = _100Mb;
5209             } else if (strstr(p, "AUTO")) {
5210                 lp->params.autosense = AUTO;
5211             }
5212         }
5213         *q = t;
5214     }
5215 }
5216 
5217 static void
5218 de4x5_dbg_open(struct net_device *dev)
5219 {
5220     struct de4x5_private *lp = netdev_priv(dev);
5221     int i;
5222 
5223     if (de4x5_debug & DEBUG_OPEN) {
5224         printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
5225         printk("\tphysical address: %pM\n", dev->dev_addr);
5226         printk("Descriptor head addresses:\n");
5227         printk("\t0x%8.8lx  0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5228         printk("Descriptor addresses:\nRX: ");
5229         for (i=0;i<lp->rxRingSize-1;i++){
5230             if (i < 3) {
5231                 printk("0x%8.8lx  ",(u_long)&lp->rx_ring[i].status);
5232             }
5233         }
5234         printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5235         printk("TX: ");
5236         for (i=0;i<lp->txRingSize-1;i++){
5237             if (i < 3) {
5238                 printk("0x%8.8lx  ", (u_long)&lp->tx_ring[i].status);
5239             }
5240         }
5241         printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5242         printk("Descriptor buffers:\nRX: ");
5243         for (i=0;i<lp->rxRingSize-1;i++){
5244             if (i < 3) {
5245                 printk("0x%8.8x  ",le32_to_cpu(lp->rx_ring[i].buf));
5246             }
5247         }
5248         printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5249         printk("TX: ");
5250         for (i=0;i<lp->txRingSize-1;i++){
5251             if (i < 3) {
5252                 printk("0x%8.8x  ", le32_to_cpu(lp->tx_ring[i].buf));
5253             }
5254         }
5255         printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
5256         printk("Ring size:\nRX: %d\nTX: %d\n",
5257                (short)lp->rxRingSize,
5258                (short)lp->txRingSize);
5259     }
5260 }
5261 
5262 static void
5263 de4x5_dbg_mii(struct net_device *dev, int k)
5264 {
5265     struct de4x5_private *lp = netdev_priv(dev);
5266     u_long iobase = dev->base_addr;
5267 
5268     if (de4x5_debug & DEBUG_MII) {
5269         printk("\nMII device address: %d\n", lp->phy[k].addr);
5270         printk("MII CR:  %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5271         printk("MII SR:  %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5272         printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5273         printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5274         if (lp->phy[k].id != BROADCOM_T4) {
5275             printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5276             printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5277         }
5278         printk("MII 16:  %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5279         if (lp->phy[k].id != BROADCOM_T4) {
5280             printk("MII 17:  %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5281             printk("MII 18:  %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5282         } else {
5283             printk("MII 20:  %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5284         }
5285     }
5286 }
5287 
5288 static void
5289 de4x5_dbg_media(struct net_device *dev)
5290 {
5291     struct de4x5_private *lp = netdev_priv(dev);
5292 
5293     if (lp->media != lp->c_media) {
5294         if (de4x5_debug & DEBUG_MEDIA) {
5295             printk("%s: media is %s%s\n", dev->name,
5296                    (lp->media == NC  ? "unconnected, link down or incompatible connection" :
5297                     (lp->media == TP  ? "TP" :
5298                      (lp->media == ANS ? "TP/Nway" :
5299                       (lp->media == BNC ? "BNC" :
5300                        (lp->media == AUI ? "AUI" :
5301                         (lp->media == BNC_AUI ? "BNC/AUI" :
5302                          (lp->media == EXT_SIA ? "EXT SIA" :
5303                           (lp->media == _100Mb  ? "100Mb/s" :
5304                            (lp->media == _10Mb   ? "10Mb/s" :
5305                             "???"
5306                             ))))))))), (lp->fdx?" full duplex.":"."));
5307         }
5308         lp->c_media = lp->media;
5309     }
5310 }
5311 
5312 static void
5313 de4x5_dbg_srom(struct de4x5_srom *p)
5314 {
5315     int i;
5316 
5317     if (de4x5_debug & DEBUG_SROM) {
5318         printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
5319         printk("Sub-system ID:        %04x\n", *((u_short *)p->sub_system_id));
5320         printk("ID Block CRC:         %02x\n", (u_char)(p->id_block_crc));
5321         printk("SROM version:         %02x\n", (u_char)(p->version));
5322         printk("# controllers:        %02x\n", (u_char)(p->num_controllers));
5323 
5324         printk("Hardware Address:     %pM\n", p->ieee_addr);
5325         printk("CRC checksum:         %04x\n", (u_short)(p->chksum));
5326         for (i=0; i<64; i++) {
5327             printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i));
5328         }
5329     }
5330 }
5331 
5332 static void
5333 de4x5_dbg_rx(struct sk_buff *skb, int len)
5334 {
5335     int i, j;
5336 
5337     if (de4x5_debug & DEBUG_RX) {
5338         printk("R: %pM <- %pM len/SAP:%02x%02x [%d]\n",
5339                skb->data, &skb->data[6],
5340                (u_char)skb->data[12],
5341                (u_char)skb->data[13],
5342                len);
5343         for (j=0; len>0;j+=16, len-=16) {
5344           printk("    %03x: ",j);
5345           for (i=0; i<16 && i<len; i++) {
5346             printk("%02x ",(u_char)skb->data[i+j]);
5347           }
5348           printk("\n");
5349         }
5350     }
5351 }
5352 
5353 /*
5354 ** Perform IOCTL call functions here. Some are privileged operations and the
5355 ** effective uid is checked in those cases. In the normal course of events
5356 ** this function is only used for my testing.
5357 */
5358 static int
5359 de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5360 {
5361     struct de4x5_private *lp = netdev_priv(dev);
5362     struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_ifru;
5363     u_long iobase = dev->base_addr;
5364     int i, j, status = 0;
5365     s32 omr;
5366     union {
5367         u8  addr[144];
5368         u16 sval[72];
5369         u32 lval[36];
5370     } tmp;
5371     u_long flags = 0;
5372 
5373     switch(ioc->cmd) {
5374     case DE4X5_GET_HWADDR:           /* Get the hardware address */
5375         ioc->len = ETH_ALEN;
5376         for (i=0; i<ETH_ALEN; i++) {
5377             tmp.addr[i] = dev->dev_addr[i];
5378         }
5379         if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5380         break;
5381 
5382     case DE4X5_SET_HWADDR:           /* Set the hardware address */
5383         if (!capable(CAP_NET_ADMIN)) return -EPERM;
5384         if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT;
5385         if (netif_queue_stopped(dev))
5386                 return -EBUSY;
5387         netif_stop_queue(dev);
5388         for (i=0; i<ETH_ALEN; i++) {
5389             dev->dev_addr[i] = tmp.addr[i];
5390         }
5391         build_setup_frame(dev, PHYS_ADDR_ONLY);
5392         /* Set up the descriptor and give ownership to the card */
5393         load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5394                                                        SETUP_FRAME_LEN, (struct sk_buff *)1);
5395         lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
5396         outl(POLL_DEMAND, DE4X5_TPD);                /* Start the TX */
5397         netif_wake_queue(dev);                      /* Unlock the TX ring */
5398         break;
5399 
5400     case DE4X5_SAY_BOO:              /* Say "Boo!" to the kernel log file */
5401         if (!capable(CAP_NET_ADMIN)) return -EPERM;
5402         printk("%s: Boo!\n", dev->name);
5403         break;
5404 
5405     case DE4X5_MCA_EN:               /* Enable pass all multicast addressing */
5406         if (!capable(CAP_NET_ADMIN)) return -EPERM;
5407         omr = inl(DE4X5_OMR);
5408         omr |= OMR_PM;
5409         outl(omr, DE4X5_OMR);
5410         break;
5411 
5412     case DE4X5_GET_STATS:            /* Get the driver statistics */
5413     {
5414         struct pkt_stats statbuf;
5415         ioc->len = sizeof(statbuf);
5416         spin_lock_irqsave(&lp->lock, flags);
5417         memcpy(&statbuf, &lp->pktStats, ioc->len);
5418         spin_unlock_irqrestore(&lp->lock, flags);
5419         if (copy_to_user(ioc->data, &statbuf, ioc->len))
5420                 return -EFAULT;
5421         break;
5422     }
5423     case DE4X5_CLR_STATS:            /* Zero out the driver statistics */
5424         if (!capable(CAP_NET_ADMIN)) return -EPERM;
5425         spin_lock_irqsave(&lp->lock, flags);
5426         memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5427         spin_unlock_irqrestore(&lp->lock, flags);
5428         break;
5429 
5430     case DE4X5_GET_OMR:              /* Get the OMR Register contents */
5431         tmp.addr[0] = inl(DE4X5_OMR);
5432         if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT;
5433         break;
5434 
5435     case DE4X5_SET_OMR:              /* Set the OMR Register contents */
5436         if (!capable(CAP_NET_ADMIN)) return -EPERM;
5437         if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT;
5438         outl(tmp.addr[0], DE4X5_OMR);
5439         break;
5440 
5441     case DE4X5_GET_REG:              /* Get the DE4X5 Registers */
5442         j = 0;
5443         tmp.lval[0] = inl(DE4X5_STS); j+=4;
5444         tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5445         tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5446         tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5447         tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5448         tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5449         tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5450         tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5451         ioc->len = j;
5452         if (copy_to_user(ioc->data, tmp.lval, ioc->len))
5453                 return -EFAULT;
5454         break;
5455 
5456 #define DE4X5_DUMP              0x0f /* Dump the DE4X5 Status */
5457 /*
5458       case DE4X5_DUMP:
5459         j = 0;
5460         tmp.addr[j++] = dev->irq;
5461         for (i=0; i<ETH_ALEN; i++) {
5462             tmp.addr[j++] = dev->dev_addr[i];
5463         }
5464         tmp.addr[j++] = lp->rxRingSize;
5465         tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5466         tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
5467 
5468         for (i=0;i<lp->rxRingSize-1;i++){
5469             if (i < 3) {
5470                 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5471             }
5472         }
5473         tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5474         for (i=0;i<lp->txRingSize-1;i++){
5475             if (i < 3) {
5476                 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5477             }
5478         }
5479         tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5480 
5481         for (i=0;i<lp->rxRingSize-1;i++){
5482             if (i < 3) {
5483                 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5484             }
5485         }
5486         tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5487         for (i=0;i<lp->txRingSize-1;i++){
5488             if (i < 3) {
5489                 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5490             }
5491         }
5492         tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5493 
5494         for (i=0;i<lp->rxRingSize;i++){
5495             tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5496         }
5497         for (i=0;i<lp->txRingSize;i++){
5498             tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5499         }
5500 
5501         tmp.lval[j>>2] = inl(DE4X5_BMR);  j+=4;
5502         tmp.lval[j>>2] = inl(DE4X5_TPD);  j+=4;
5503         tmp.lval[j>>2] = inl(DE4X5_RPD);  j+=4;
5504         tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4;
5505         tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4;
5506         tmp.lval[j>>2] = inl(DE4X5_STS);  j+=4;
5507         tmp.lval[j>>2] = inl(DE4X5_OMR);  j+=4;
5508         tmp.lval[j>>2] = inl(DE4X5_IMR);  j+=4;
5509         tmp.lval[j>>2] = lp->chipset; j+=4;
5510         if (lp->chipset == DC21140) {
5511             tmp.lval[j>>2] = gep_rd(dev);  j+=4;
5512         } else {
5513             tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
5514             tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
5515             tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
5516             tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
5517         }
5518         tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
5519         if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
5520             tmp.lval[j>>2] = lp->active; j+=4;
5521             tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5522             tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5523             tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5524             tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5525             if (lp->phy[lp->active].id != BROADCOM_T4) {
5526                 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5527                 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5528             }
5529             tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5530             if (lp->phy[lp->active].id != BROADCOM_T4) {
5531                 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5532                 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5533             } else {
5534                 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5535             }
5536         }
5537 
5538         tmp.addr[j++] = lp->txRingSize;
5539         tmp.addr[j++] = netif_queue_stopped(dev);
5540 
5541         ioc->len = j;
5542         if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5543         break;
5544 
5545 */
5546     default:
5547         return -EOPNOTSUPP;
5548     }
5549 
5550     return status;
5551 }
5552 
5553 static int __init de4x5_module_init (void)
5554 {
5555         int err = 0;
5556 
5557 #ifdef CONFIG_PCI
5558         err = pci_register_driver(&de4x5_pci_driver);
5559 #endif
5560 #ifdef CONFIG_EISA
5561         err |= eisa_driver_register (&de4x5_eisa_driver);
5562 #endif
5563 
5564         return err;
5565 }
5566 
5567 static void __exit de4x5_module_exit (void)
5568 {
5569 #ifdef CONFIG_PCI
5570         pci_unregister_driver (&de4x5_pci_driver);
5571 #endif
5572 #ifdef CONFIG_EISA
5573         eisa_driver_unregister (&de4x5_eisa_driver);
5574 #endif
5575 }
5576 
5577 module_init (de4x5_module_init);
5578 module_exit (de4x5_module_exit);
5579 

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